1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2019 NXP. 4 */ 5 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/of_address.h> 9 #include <linux/slab.h> 10 #include <linux/sys_soc.h> 11 #include <linux/platform_device.h> 12 #include <linux/arm-smccc.h> 13 #include <linux/of.h> 14 #include <linux/clk.h> 15 16 #define REV_B1 0x21 17 18 #define IMX8MQ_SW_INFO_B1 0x40 19 #define IMX8MQ_SW_MAGIC_B1 0xff0055aa 20 21 #define IMX_SIP_GET_SOC_INFO 0xc2000006 22 23 #define OCOTP_UID_LOW 0x410 24 #define OCOTP_UID_HIGH 0x420 25 26 #define IMX8MP_OCOTP_UID_OFFSET 0x10 27 28 /* Same as ANADIG_DIGPROG_IMX7D */ 29 #define ANADIG_DIGPROG_IMX8MM 0x800 30 31 struct imx8_soc_data { 32 char *name; 33 int (*soc_revision)(u32 *socrev, u64 *socuid); 34 }; 35 36 #ifdef CONFIG_HAVE_ARM_SMCCC 37 static u32 imx8mq_soc_revision_from_atf(void) 38 { 39 struct arm_smccc_res res; 40 41 arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res); 42 43 if (res.a0 == SMCCC_RET_NOT_SUPPORTED) 44 return 0; 45 else 46 return res.a0 & 0xff; 47 } 48 #else 49 static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; }; 50 #endif 51 52 static int imx8mq_soc_revision(u32 *socrev, u64 *socuid) 53 { 54 struct device_node *np __free(device_node) = 55 of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); 56 void __iomem *ocotp_base; 57 u32 magic; 58 u32 rev; 59 struct clk *clk; 60 int ret; 61 62 if (!np) 63 return -EINVAL; 64 65 ocotp_base = of_iomap(np, 0); 66 if (!ocotp_base) 67 return -EINVAL; 68 69 clk = of_clk_get_by_name(np, NULL); 70 if (IS_ERR(clk)) { 71 ret = PTR_ERR(clk); 72 goto err_clk; 73 } 74 75 clk_prepare_enable(clk); 76 77 /* 78 * SOC revision on older imx8mq is not available in fuses so query 79 * the value from ATF instead. 80 */ 81 rev = imx8mq_soc_revision_from_atf(); 82 if (!rev) { 83 magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1); 84 if (magic == IMX8MQ_SW_MAGIC_B1) 85 rev = REV_B1; 86 } 87 88 *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); 89 *socuid <<= 32; 90 *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); 91 92 *socrev = rev; 93 94 clk_disable_unprepare(clk); 95 clk_put(clk); 96 iounmap(ocotp_base); 97 98 return 0; 99 100 err_clk: 101 iounmap(ocotp_base); 102 return ret; 103 } 104 105 static int imx8mm_soc_uid(u64 *socuid) 106 { 107 struct device_node *np __free(device_node) = 108 of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); 109 void __iomem *ocotp_base; 110 struct clk *clk; 111 int ret = 0; 112 u32 offset = of_machine_is_compatible("fsl,imx8mp") ? 113 IMX8MP_OCOTP_UID_OFFSET : 0; 114 115 if (!np) 116 return -EINVAL; 117 118 ocotp_base = of_iomap(np, 0); 119 if (!ocotp_base) 120 return -EINVAL; 121 122 clk = of_clk_get_by_name(np, NULL); 123 if (IS_ERR(clk)) { 124 ret = PTR_ERR(clk); 125 goto err_clk; 126 } 127 128 clk_prepare_enable(clk); 129 130 *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset); 131 *socuid <<= 32; 132 *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset); 133 134 clk_disable_unprepare(clk); 135 clk_put(clk); 136 137 err_clk: 138 iounmap(ocotp_base); 139 return ret; 140 } 141 142 static int imx8mm_soc_revision(u32 *socrev, u64 *socuid) 143 { 144 struct device_node *np __free(device_node) = 145 of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); 146 void __iomem *anatop_base; 147 148 if (!np) 149 return -EINVAL; 150 151 anatop_base = of_iomap(np, 0); 152 if (!anatop_base) 153 return -EINVAL; 154 155 *socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); 156 157 iounmap(anatop_base); 158 159 return imx8mm_soc_uid(socuid); 160 } 161 162 static const struct imx8_soc_data imx8mq_soc_data = { 163 .name = "i.MX8MQ", 164 .soc_revision = imx8mq_soc_revision, 165 }; 166 167 static const struct imx8_soc_data imx8mm_soc_data = { 168 .name = "i.MX8MM", 169 .soc_revision = imx8mm_soc_revision, 170 }; 171 172 static const struct imx8_soc_data imx8mn_soc_data = { 173 .name = "i.MX8MN", 174 .soc_revision = imx8mm_soc_revision, 175 }; 176 177 static const struct imx8_soc_data imx8mp_soc_data = { 178 .name = "i.MX8MP", 179 .soc_revision = imx8mm_soc_revision, 180 }; 181 182 static __maybe_unused const struct of_device_id imx8_soc_match[] = { 183 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, }, 184 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, }, 185 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, }, 186 { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, }, 187 { } 188 }; 189 190 #define imx8_revision(dev, soc_rev) \ 191 (soc_rev) ? \ 192 devm_kasprintf((dev), GFP_KERNEL, "%d.%d", ((soc_rev) >> 4) & 0xf, (soc_rev) & 0xf) : \ 193 "unknown" 194 195 static void imx8m_unregister_soc(void *data) 196 { 197 soc_device_unregister(data); 198 } 199 200 static void imx8m_unregister_cpufreq(void *data) 201 { 202 platform_device_unregister(data); 203 } 204 205 static int imx8m_soc_probe(struct platform_device *pdev) 206 { 207 struct soc_device_attribute *soc_dev_attr; 208 struct platform_device *cpufreq_dev; 209 const struct imx8_soc_data *data; 210 struct device *dev = &pdev->dev; 211 const struct of_device_id *id; 212 struct soc_device *soc_dev; 213 u32 soc_rev = 0; 214 u64 soc_uid = 0; 215 int ret; 216 217 soc_dev_attr = devm_kzalloc(dev, sizeof(*soc_dev_attr), GFP_KERNEL); 218 if (!soc_dev_attr) 219 return -ENOMEM; 220 221 soc_dev_attr->family = "Freescale i.MX"; 222 223 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); 224 if (ret) 225 return ret; 226 227 id = of_match_node(imx8_soc_match, of_root); 228 if (!id) 229 return -ENODEV; 230 231 data = id->data; 232 if (data) { 233 soc_dev_attr->soc_id = data->name; 234 if (data->soc_revision) { 235 ret = data->soc_revision(&soc_rev, &soc_uid); 236 if (ret) 237 return ret; 238 } 239 } 240 241 soc_dev_attr->revision = imx8_revision(dev, soc_rev); 242 if (!soc_dev_attr->revision) 243 return -ENOMEM; 244 245 soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX", soc_uid); 246 if (!soc_dev_attr->serial_number) 247 return -ENOMEM; 248 249 soc_dev = soc_device_register(soc_dev_attr); 250 if (IS_ERR(soc_dev)) 251 return PTR_ERR(soc_dev); 252 253 ret = devm_add_action(dev, imx8m_unregister_soc, soc_dev); 254 if (ret) 255 return ret; 256 257 pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id, 258 soc_dev_attr->revision); 259 260 if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) { 261 cpufreq_dev = platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); 262 if (IS_ERR(cpufreq_dev)) 263 return dev_err_probe(dev, PTR_ERR(cpufreq_dev), 264 "Failed to register imx-cpufreq-dev device\n"); 265 ret = devm_add_action(dev, imx8m_unregister_cpufreq, cpufreq_dev); 266 if (ret) 267 return ret; 268 } 269 270 return 0; 271 } 272 273 static struct platform_driver imx8m_soc_driver = { 274 .probe = imx8m_soc_probe, 275 .driver = { 276 .name = "imx8m-soc", 277 }, 278 }; 279 280 static int __init imx8_soc_init(void) 281 { 282 struct platform_device *pdev; 283 int ret; 284 285 /* No match means this is non-i.MX8M hardware, do nothing. */ 286 if (!of_match_node(imx8_soc_match, of_root)) 287 return 0; 288 289 ret = platform_driver_register(&imx8m_soc_driver); 290 if (ret) { 291 pr_err("Failed to register imx8m-soc platform driver: %d\n", ret); 292 return ret; 293 } 294 295 pdev = platform_device_register_simple("imx8m-soc", -1, NULL, 0); 296 if (IS_ERR(pdev)) { 297 pr_err("Failed to register imx8m-soc platform device: %ld\n", PTR_ERR(pdev)); 298 platform_driver_unregister(&imx8m_soc_driver); 299 return PTR_ERR(pdev); 300 } 301 302 return 0; 303 } 304 device_initcall(imx8_soc_init); 305 MODULE_DESCRIPTION("NXP i.MX8M SoC driver"); 306 MODULE_LICENSE("GPL"); 307