1 /* 2 * arch/powerpc/sysdev/qe_lib/qe_ic.c 3 * 4 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Li Yang <leoli@freescale.com> 7 * Based on code from Shlomi Gridish <gridish@freescale.com> 8 * 9 * QUICC ENGINE Interrupt Controller 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #include <linux/of_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/errno.h> 22 #include <linux/reboot.h> 23 #include <linux/slab.h> 24 #include <linux/stddef.h> 25 #include <linux/sched.h> 26 #include <linux/signal.h> 27 #include <linux/device.h> 28 #include <linux/spinlock.h> 29 #include <asm/irq.h> 30 #include <asm/io.h> 31 #include <soc/fsl/qe/qe_ic.h> 32 33 #include "qe_ic.h" 34 35 static DEFINE_RAW_SPINLOCK(qe_ic_lock); 36 37 static struct qe_ic_info qe_ic_info[] = { 38 [1] = { 39 .mask = 0x00008000, 40 .mask_reg = QEIC_CIMR, 41 .pri_code = 0, 42 .pri_reg = QEIC_CIPWCC, 43 }, 44 [2] = { 45 .mask = 0x00004000, 46 .mask_reg = QEIC_CIMR, 47 .pri_code = 1, 48 .pri_reg = QEIC_CIPWCC, 49 }, 50 [3] = { 51 .mask = 0x00002000, 52 .mask_reg = QEIC_CIMR, 53 .pri_code = 2, 54 .pri_reg = QEIC_CIPWCC, 55 }, 56 [10] = { 57 .mask = 0x00000040, 58 .mask_reg = QEIC_CIMR, 59 .pri_code = 1, 60 .pri_reg = QEIC_CIPZCC, 61 }, 62 [11] = { 63 .mask = 0x00000020, 64 .mask_reg = QEIC_CIMR, 65 .pri_code = 2, 66 .pri_reg = QEIC_CIPZCC, 67 }, 68 [12] = { 69 .mask = 0x00000010, 70 .mask_reg = QEIC_CIMR, 71 .pri_code = 3, 72 .pri_reg = QEIC_CIPZCC, 73 }, 74 [13] = { 75 .mask = 0x00000008, 76 .mask_reg = QEIC_CIMR, 77 .pri_code = 4, 78 .pri_reg = QEIC_CIPZCC, 79 }, 80 [14] = { 81 .mask = 0x00000004, 82 .mask_reg = QEIC_CIMR, 83 .pri_code = 5, 84 .pri_reg = QEIC_CIPZCC, 85 }, 86 [15] = { 87 .mask = 0x00000002, 88 .mask_reg = QEIC_CIMR, 89 .pri_code = 6, 90 .pri_reg = QEIC_CIPZCC, 91 }, 92 [20] = { 93 .mask = 0x10000000, 94 .mask_reg = QEIC_CRIMR, 95 .pri_code = 3, 96 .pri_reg = QEIC_CIPRTA, 97 }, 98 [25] = { 99 .mask = 0x00800000, 100 .mask_reg = QEIC_CRIMR, 101 .pri_code = 0, 102 .pri_reg = QEIC_CIPRTB, 103 }, 104 [26] = { 105 .mask = 0x00400000, 106 .mask_reg = QEIC_CRIMR, 107 .pri_code = 1, 108 .pri_reg = QEIC_CIPRTB, 109 }, 110 [27] = { 111 .mask = 0x00200000, 112 .mask_reg = QEIC_CRIMR, 113 .pri_code = 2, 114 .pri_reg = QEIC_CIPRTB, 115 }, 116 [28] = { 117 .mask = 0x00100000, 118 .mask_reg = QEIC_CRIMR, 119 .pri_code = 3, 120 .pri_reg = QEIC_CIPRTB, 121 }, 122 [32] = { 123 .mask = 0x80000000, 124 .mask_reg = QEIC_CIMR, 125 .pri_code = 0, 126 .pri_reg = QEIC_CIPXCC, 127 }, 128 [33] = { 129 .mask = 0x40000000, 130 .mask_reg = QEIC_CIMR, 131 .pri_code = 1, 132 .pri_reg = QEIC_CIPXCC, 133 }, 134 [34] = { 135 .mask = 0x20000000, 136 .mask_reg = QEIC_CIMR, 137 .pri_code = 2, 138 .pri_reg = QEIC_CIPXCC, 139 }, 140 [35] = { 141 .mask = 0x10000000, 142 .mask_reg = QEIC_CIMR, 143 .pri_code = 3, 144 .pri_reg = QEIC_CIPXCC, 145 }, 146 [36] = { 147 .mask = 0x08000000, 148 .mask_reg = QEIC_CIMR, 149 .pri_code = 4, 150 .pri_reg = QEIC_CIPXCC, 151 }, 152 [40] = { 153 .mask = 0x00800000, 154 .mask_reg = QEIC_CIMR, 155 .pri_code = 0, 156 .pri_reg = QEIC_CIPYCC, 157 }, 158 [41] = { 159 .mask = 0x00400000, 160 .mask_reg = QEIC_CIMR, 161 .pri_code = 1, 162 .pri_reg = QEIC_CIPYCC, 163 }, 164 [42] = { 165 .mask = 0x00200000, 166 .mask_reg = QEIC_CIMR, 167 .pri_code = 2, 168 .pri_reg = QEIC_CIPYCC, 169 }, 170 [43] = { 171 .mask = 0x00100000, 172 .mask_reg = QEIC_CIMR, 173 .pri_code = 3, 174 .pri_reg = QEIC_CIPYCC, 175 }, 176 }; 177 178 static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) 179 { 180 return in_be32(base + (reg >> 2)); 181 } 182 183 static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, 184 u32 value) 185 { 186 out_be32(base + (reg >> 2), value); 187 } 188 189 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) 190 { 191 return irq_get_chip_data(virq); 192 } 193 194 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) 195 { 196 return irq_data_get_irq_chip_data(d); 197 } 198 199 static void qe_ic_unmask_irq(struct irq_data *d) 200 { 201 struct qe_ic *qe_ic = qe_ic_from_irq_data(d); 202 unsigned int src = irqd_to_hwirq(d); 203 unsigned long flags; 204 u32 temp; 205 206 raw_spin_lock_irqsave(&qe_ic_lock, flags); 207 208 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); 209 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, 210 temp | qe_ic_info[src].mask); 211 212 raw_spin_unlock_irqrestore(&qe_ic_lock, flags); 213 } 214 215 static void qe_ic_mask_irq(struct irq_data *d) 216 { 217 struct qe_ic *qe_ic = qe_ic_from_irq_data(d); 218 unsigned int src = irqd_to_hwirq(d); 219 unsigned long flags; 220 u32 temp; 221 222 raw_spin_lock_irqsave(&qe_ic_lock, flags); 223 224 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); 225 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, 226 temp & ~qe_ic_info[src].mask); 227 228 /* Flush the above write before enabling interrupts; otherwise, 229 * spurious interrupts will sometimes happen. To be 100% sure 230 * that the write has reached the device before interrupts are 231 * enabled, the mask register would have to be read back; however, 232 * this is not required for correctness, only to avoid wasting 233 * time on a large number of spurious interrupts. In testing, 234 * a sync reduced the observed spurious interrupts to zero. 235 */ 236 mb(); 237 238 raw_spin_unlock_irqrestore(&qe_ic_lock, flags); 239 } 240 241 static struct irq_chip qe_ic_irq_chip = { 242 .name = "QEIC", 243 .irq_unmask = qe_ic_unmask_irq, 244 .irq_mask = qe_ic_mask_irq, 245 .irq_mask_ack = qe_ic_mask_irq, 246 }; 247 248 static int qe_ic_host_match(struct irq_domain *h, struct device_node *node, 249 enum irq_domain_bus_token bus_token) 250 { 251 /* Exact match, unless qe_ic node is NULL */ 252 struct device_node *of_node = irq_domain_get_of_node(h); 253 return of_node == NULL || of_node == node; 254 } 255 256 static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, 257 irq_hw_number_t hw) 258 { 259 struct qe_ic *qe_ic = h->host_data; 260 struct irq_chip *chip; 261 262 if (qe_ic_info[hw].mask == 0) { 263 printk(KERN_ERR "Can't map reserved IRQ\n"); 264 return -EINVAL; 265 } 266 /* Default chip */ 267 chip = &qe_ic->hc_irq; 268 269 irq_set_chip_data(virq, qe_ic); 270 irq_set_status_flags(virq, IRQ_LEVEL); 271 272 irq_set_chip_and_handler(virq, chip, handle_level_irq); 273 274 return 0; 275 } 276 277 static const struct irq_domain_ops qe_ic_host_ops = { 278 .match = qe_ic_host_match, 279 .map = qe_ic_host_map, 280 .xlate = irq_domain_xlate_onetwocell, 281 }; 282 283 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ 284 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) 285 { 286 int irq; 287 288 BUG_ON(qe_ic == NULL); 289 290 /* get the interrupt source vector. */ 291 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26; 292 293 if (irq == 0) 294 return NO_IRQ; 295 296 return irq_linear_revmap(qe_ic->irqhost, irq); 297 } 298 299 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ 300 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) 301 { 302 int irq; 303 304 BUG_ON(qe_ic == NULL); 305 306 /* get the interrupt source vector. */ 307 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26; 308 309 if (irq == 0) 310 return NO_IRQ; 311 312 return irq_linear_revmap(qe_ic->irqhost, irq); 313 } 314 315 void __init qe_ic_init(struct device_node *node, unsigned int flags, 316 void (*low_handler)(struct irq_desc *desc), 317 void (*high_handler)(struct irq_desc *desc)) 318 { 319 struct qe_ic *qe_ic; 320 struct resource res; 321 u32 temp = 0, ret, high_active = 0; 322 323 ret = of_address_to_resource(node, 0, &res); 324 if (ret) 325 return; 326 327 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL); 328 if (qe_ic == NULL) 329 return; 330 331 qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, 332 &qe_ic_host_ops, qe_ic); 333 if (qe_ic->irqhost == NULL) { 334 kfree(qe_ic); 335 return; 336 } 337 338 qe_ic->regs = ioremap(res.start, resource_size(&res)); 339 340 qe_ic->hc_irq = qe_ic_irq_chip; 341 342 qe_ic->virq_high = irq_of_parse_and_map(node, 0); 343 qe_ic->virq_low = irq_of_parse_and_map(node, 1); 344 345 if (qe_ic->virq_low == NO_IRQ) { 346 printk(KERN_ERR "Failed to map QE_IC low IRQ\n"); 347 kfree(qe_ic); 348 return; 349 } 350 351 /* default priority scheme is grouped. If spread mode is */ 352 /* required, configure cicr accordingly. */ 353 if (flags & QE_IC_SPREADMODE_GRP_W) 354 temp |= CICR_GWCC; 355 if (flags & QE_IC_SPREADMODE_GRP_X) 356 temp |= CICR_GXCC; 357 if (flags & QE_IC_SPREADMODE_GRP_Y) 358 temp |= CICR_GYCC; 359 if (flags & QE_IC_SPREADMODE_GRP_Z) 360 temp |= CICR_GZCC; 361 if (flags & QE_IC_SPREADMODE_GRP_RISCA) 362 temp |= CICR_GRTA; 363 if (flags & QE_IC_SPREADMODE_GRP_RISCB) 364 temp |= CICR_GRTB; 365 366 /* choose destination signal for highest priority interrupt */ 367 if (flags & QE_IC_HIGH_SIGNAL) { 368 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT); 369 high_active = 1; 370 } 371 372 qe_ic_write(qe_ic->regs, QEIC_CICR, temp); 373 374 irq_set_handler_data(qe_ic->virq_low, qe_ic); 375 irq_set_chained_handler(qe_ic->virq_low, low_handler); 376 377 if (qe_ic->virq_high != NO_IRQ && 378 qe_ic->virq_high != qe_ic->virq_low) { 379 irq_set_handler_data(qe_ic->virq_high, qe_ic); 380 irq_set_chained_handler(qe_ic->virq_high, high_handler); 381 } 382 } 383 384 void qe_ic_set_highest_priority(unsigned int virq, int high) 385 { 386 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 387 unsigned int src = virq_to_hw(virq); 388 u32 temp = 0; 389 390 temp = qe_ic_read(qe_ic->regs, QEIC_CICR); 391 392 temp &= ~CICR_HP_MASK; 393 temp |= src << CICR_HP_SHIFT; 394 395 temp &= ~CICR_HPIT_MASK; 396 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT; 397 398 qe_ic_write(qe_ic->regs, QEIC_CICR, temp); 399 } 400 401 /* Set Priority level within its group, from 1 to 8 */ 402 int qe_ic_set_priority(unsigned int virq, unsigned int priority) 403 { 404 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 405 unsigned int src = virq_to_hw(virq); 406 u32 temp; 407 408 if (priority > 8 || priority == 0) 409 return -EINVAL; 410 if (src > 127) 411 return -EINVAL; 412 if (qe_ic_info[src].pri_reg == 0) 413 return -EINVAL; 414 415 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); 416 417 if (priority < 4) { 418 temp &= ~(0x7 << (32 - priority * 3)); 419 temp |= qe_ic_info[src].pri_code << (32 - priority * 3); 420 } else { 421 temp &= ~(0x7 << (24 - priority * 3)); 422 temp |= qe_ic_info[src].pri_code << (24 - priority * 3); 423 } 424 425 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); 426 427 return 0; 428 } 429 430 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */ 431 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) 432 { 433 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 434 unsigned int src = virq_to_hw(virq); 435 u32 temp, control_reg = QEIC_CICNR, shift = 0; 436 437 if (priority > 2 || priority == 0) 438 return -EINVAL; 439 440 switch (qe_ic_info[src].pri_reg) { 441 case QEIC_CIPZCC: 442 shift = CICNR_ZCC1T_SHIFT; 443 break; 444 case QEIC_CIPWCC: 445 shift = CICNR_WCC1T_SHIFT; 446 break; 447 case QEIC_CIPYCC: 448 shift = CICNR_YCC1T_SHIFT; 449 break; 450 case QEIC_CIPXCC: 451 shift = CICNR_XCC1T_SHIFT; 452 break; 453 case QEIC_CIPRTA: 454 shift = CRICR_RTA1T_SHIFT; 455 control_reg = QEIC_CRICR; 456 break; 457 case QEIC_CIPRTB: 458 shift = CRICR_RTB1T_SHIFT; 459 control_reg = QEIC_CRICR; 460 break; 461 default: 462 return -EINVAL; 463 } 464 465 shift += (2 - priority) * 2; 466 temp = qe_ic_read(qe_ic->regs, control_reg); 467 temp &= ~(SIGNAL_MASK << shift); 468 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift; 469 qe_ic_write(qe_ic->regs, control_reg, temp); 470 471 return 0; 472 } 473 474 static struct bus_type qe_ic_subsys = { 475 .name = "qe_ic", 476 .dev_name = "qe_ic", 477 }; 478 479 static struct device device_qe_ic = { 480 .id = 0, 481 .bus = &qe_ic_subsys, 482 }; 483 484 static int __init init_qe_ic_sysfs(void) 485 { 486 int rc; 487 488 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n"); 489 490 rc = subsys_system_register(&qe_ic_subsys, NULL); 491 if (rc) { 492 printk(KERN_ERR "Failed registering qe_ic sys class\n"); 493 return -ENODEV; 494 } 495 rc = device_register(&device_qe_ic); 496 if (rc) { 497 printk(KERN_ERR "Failed registering qe_ic sys device\n"); 498 return -ENODEV; 499 } 500 return 0; 501 } 502 503 subsys_initcall(init_qe_ic_sysfs); 504