1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * QUICC Engine GPIOs 4 * 5 * Copyright (c) MontaVista Software, Inc. 2008. 6 * 7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/spinlock.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/gpio/legacy-of-mm-gpiochip.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/slab.h> 20 #include <linux/export.h> 21 #include <linux/property.h> 22 23 #include <soc/fsl/qe/qe.h> 24 25 struct qe_gpio_chip { 26 struct of_mm_gpio_chip mm_gc; 27 spinlock_t lock; 28 29 /* shadowed data register to clear/set bits safely */ 30 u32 cpdata; 31 32 /* saved_regs used to restore dedicated functions */ 33 struct qe_pio_regs saved_regs; 34 }; 35 36 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) 37 { 38 struct qe_gpio_chip *qe_gc = 39 container_of(mm_gc, struct qe_gpio_chip, mm_gc); 40 struct qe_pio_regs __iomem *regs = mm_gc->regs; 41 42 qe_gc->cpdata = ioread32be(®s->cpdata); 43 qe_gc->saved_regs.cpdata = qe_gc->cpdata; 44 qe_gc->saved_regs.cpdir1 = ioread32be(®s->cpdir1); 45 qe_gc->saved_regs.cpdir2 = ioread32be(®s->cpdir2); 46 qe_gc->saved_regs.cppar1 = ioread32be(®s->cppar1); 47 qe_gc->saved_regs.cppar2 = ioread32be(®s->cppar2); 48 qe_gc->saved_regs.cpodr = ioread32be(®s->cpodr); 49 } 50 51 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) 52 { 53 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 54 struct qe_pio_regs __iomem *regs = mm_gc->regs; 55 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 56 57 return !!(ioread32be(®s->cpdata) & pin_mask); 58 } 59 60 static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 61 { 62 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 63 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 64 struct qe_pio_regs __iomem *regs = mm_gc->regs; 65 unsigned long flags; 66 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 67 68 spin_lock_irqsave(&qe_gc->lock, flags); 69 70 if (val) 71 qe_gc->cpdata |= pin_mask; 72 else 73 qe_gc->cpdata &= ~pin_mask; 74 75 iowrite32be(qe_gc->cpdata, ®s->cpdata); 76 77 spin_unlock_irqrestore(&qe_gc->lock, flags); 78 79 return 0; 80 } 81 82 static int qe_gpio_set_multiple(struct gpio_chip *gc, 83 unsigned long *mask, unsigned long *bits) 84 { 85 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 86 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 87 struct qe_pio_regs __iomem *regs = mm_gc->regs; 88 unsigned long flags; 89 int i; 90 91 spin_lock_irqsave(&qe_gc->lock, flags); 92 93 for (i = 0; i < gc->ngpio; i++) { 94 if (*mask == 0) 95 break; 96 if (__test_and_clear_bit(i, mask)) { 97 if (test_bit(i, bits)) 98 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); 99 else 100 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); 101 } 102 } 103 104 iowrite32be(qe_gc->cpdata, ®s->cpdata); 105 106 spin_unlock_irqrestore(&qe_gc->lock, flags); 107 108 return 0; 109 } 110 111 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 112 { 113 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 114 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 115 unsigned long flags; 116 117 spin_lock_irqsave(&qe_gc->lock, flags); 118 119 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); 120 121 spin_unlock_irqrestore(&qe_gc->lock, flags); 122 123 return 0; 124 } 125 126 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 127 { 128 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 129 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 130 unsigned long flags; 131 132 qe_gpio_set(gc, gpio, val); 133 134 spin_lock_irqsave(&qe_gc->lock, flags); 135 136 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); 137 138 spin_unlock_irqrestore(&qe_gc->lock, flags); 139 140 return 0; 141 } 142 143 struct qe_pin { 144 /* 145 * The qe_gpio_chip name is unfortunate, we should change that to 146 * something like qe_pio_controller. Someday. 147 */ 148 struct qe_gpio_chip *controller; 149 int num; 150 }; 151 152 /** 153 * qe_pin_request - Request a QE pin 154 * @dev: device to get the pin from 155 * @index: index of the pin in the device tree 156 * Context: non-atomic 157 * 158 * This function return qe_pin so that you could use it with the rest of 159 * the QE Pin Multiplexing API. 160 */ 161 struct qe_pin *qe_pin_request(struct device *dev, int index) 162 { 163 struct qe_pin *qe_pin; 164 struct gpio_chip *gc; 165 struct gpio_desc *gpiod; 166 int gpio_num; 167 int err; 168 169 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL); 170 if (!qe_pin) { 171 dev_dbg(dev, "%s: can't allocate memory\n", __func__); 172 return ERR_PTR(-ENOMEM); 173 } 174 175 /* 176 * Request gpio as nonexclusive as it was likely reserved by the 177 * caller, and we are not planning on controlling it, we only need 178 * the descriptor to the to the gpio chip structure. 179 */ 180 gpiod = gpiod_get_index(dev, NULL, index, 181 GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE); 182 err = PTR_ERR_OR_ZERO(gpiod); 183 if (err) 184 goto err0; 185 186 gc = gpiod_to_chip(gpiod); 187 gpio_num = desc_to_gpio(gpiod); 188 /* We no longer need this descriptor */ 189 gpiod_put(gpiod); 190 191 if (WARN_ON(!gc)) { 192 err = -ENODEV; 193 goto err0; 194 } 195 196 qe_pin->controller = gpiochip_get_data(gc); 197 /* 198 * FIXME: this gets the local offset on the gpio_chip so that the driver 199 * can manipulate pin control settings through its custom API. The real 200 * solution is to create a real pin control driver for this. 201 */ 202 qe_pin->num = gpio_num - gc->base; 203 204 if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) { 205 dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); 206 err = -EINVAL; 207 goto err0; 208 } 209 return qe_pin; 210 err0: 211 kfree(qe_pin); 212 dev_dbg(dev, "%s failed with status %d\n", __func__, err); 213 return ERR_PTR(err); 214 } 215 EXPORT_SYMBOL(qe_pin_request); 216 217 /** 218 * qe_pin_free - Free a pin 219 * @qe_pin: pointer to the qe_pin structure 220 * Context: any 221 * 222 * This function frees the qe_pin structure and makes a pin available 223 * for further qe_pin_request() calls. 224 */ 225 void qe_pin_free(struct qe_pin *qe_pin) 226 { 227 kfree(qe_pin); 228 } 229 EXPORT_SYMBOL(qe_pin_free); 230 231 /** 232 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode 233 * @qe_pin: pointer to the qe_pin structure 234 * Context: any 235 * 236 * This function resets a pin to a dedicated peripheral function that 237 * has been set up by the firmware. 238 */ 239 void qe_pin_set_dedicated(struct qe_pin *qe_pin) 240 { 241 struct qe_gpio_chip *qe_gc = qe_pin->controller; 242 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 243 struct qe_pio_regs *sregs = &qe_gc->saved_regs; 244 int pin = qe_pin->num; 245 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); 246 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); 247 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; 248 unsigned long flags; 249 250 spin_lock_irqsave(&qe_gc->lock, flags); 251 252 if (second_reg) { 253 qe_clrsetbits_be32(®s->cpdir2, mask2, 254 sregs->cpdir2 & mask2); 255 qe_clrsetbits_be32(®s->cppar2, mask2, 256 sregs->cppar2 & mask2); 257 } else { 258 qe_clrsetbits_be32(®s->cpdir1, mask2, 259 sregs->cpdir1 & mask2); 260 qe_clrsetbits_be32(®s->cppar1, mask2, 261 sregs->cppar1 & mask2); 262 } 263 264 if (sregs->cpdata & mask1) 265 qe_gc->cpdata |= mask1; 266 else 267 qe_gc->cpdata &= ~mask1; 268 269 iowrite32be(qe_gc->cpdata, ®s->cpdata); 270 qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); 271 272 spin_unlock_irqrestore(&qe_gc->lock, flags); 273 } 274 EXPORT_SYMBOL(qe_pin_set_dedicated); 275 276 /** 277 * qe_pin_set_gpio - Set a pin to the GPIO mode 278 * @qe_pin: pointer to the qe_pin structure 279 * Context: any 280 * 281 * This function sets a pin to the GPIO mode. 282 */ 283 void qe_pin_set_gpio(struct qe_pin *qe_pin) 284 { 285 struct qe_gpio_chip *qe_gc = qe_pin->controller; 286 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 287 unsigned long flags; 288 289 spin_lock_irqsave(&qe_gc->lock, flags); 290 291 /* Let's make it input by default, GPIO API is able to change that. */ 292 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0); 293 294 spin_unlock_irqrestore(&qe_gc->lock, flags); 295 } 296 EXPORT_SYMBOL(qe_pin_set_gpio); 297 298 static int __init qe_add_gpiochips(void) 299 { 300 struct device_node *np; 301 302 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { 303 int ret; 304 struct qe_gpio_chip *qe_gc; 305 struct of_mm_gpio_chip *mm_gc; 306 struct gpio_chip *gc; 307 308 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL); 309 if (!qe_gc) { 310 ret = -ENOMEM; 311 goto err; 312 } 313 314 spin_lock_init(&qe_gc->lock); 315 316 mm_gc = &qe_gc->mm_gc; 317 gc = &mm_gc->gc; 318 319 mm_gc->save_regs = qe_gpio_save_regs; 320 gc->ngpio = QE_PIO_PINS; 321 gc->direction_input = qe_gpio_dir_in; 322 gc->direction_output = qe_gpio_dir_out; 323 gc->get = qe_gpio_get; 324 gc->set = qe_gpio_set; 325 gc->set_multiple = qe_gpio_set_multiple; 326 327 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc); 328 if (ret) 329 goto err; 330 continue; 331 err: 332 pr_err("%pOF: registration failed with status %d\n", 333 np, ret); 334 kfree(qe_gc); 335 /* try others anyway */ 336 } 337 return 0; 338 } 339 arch_initcall(qe_add_gpiochips); 340