xref: /linux/drivers/soc/fsl/qe/Kconfig (revision eb680d563089e55b20cb7730ed881638fe4425b7)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
27aa1aa6eSZhao Qiang#
37aa1aa6eSZhao Qiang# QE Communication options
47aa1aa6eSZhao Qiang#
57aa1aa6eSZhao Qiang
67aa1aa6eSZhao Qiangconfig QUICC_ENGINE
746252108SLi Yang	bool "QUICC Engine (QE) framework support"
85a35435eSRasmus Villemoes	depends on OF && HAS_IOMEM
95a35435eSRasmus Villemoes	depends on PPC || ARM || ARM64 || COMPILE_TEST
107aa1aa6eSZhao Qiang	select GENERIC_ALLOCATOR
117aa1aa6eSZhao Qiang	select CRC32
127aa1aa6eSZhao Qiang	help
137aa1aa6eSZhao Qiang	  The QUICC Engine (QE) is a new generation of communications
147aa1aa6eSZhao Qiang	  coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
157aa1aa6eSZhao Qiang	  Selecting this option means that you wish to build a kernel
167aa1aa6eSZhao Qiang	  for a machine with a QE coprocessor.
177aa1aa6eSZhao Qiang
187aa1aa6eSZhao Qiangconfig UCC_SLOW
197aa1aa6eSZhao Qiang	bool
20*eb680d56SHerve Codina	default y if SERIAL_QE || (CPM_QMC && QUICC_ENGINE)
217aa1aa6eSZhao Qiang	help
227aa1aa6eSZhao Qiang	  This option provides qe_lib support to UCC slow
237aa1aa6eSZhao Qiang	  protocols: UART, BISYNC, QMC
247aa1aa6eSZhao Qiang
257aa1aa6eSZhao Qiangconfig UCC_FAST
267aa1aa6eSZhao Qiang	bool
2735ef1c20SZhao Qiang	default y if UCC_GETH || QE_TDM
287aa1aa6eSZhao Qiang	help
297aa1aa6eSZhao Qiang	  This option provides qe_lib support to UCC fast
307aa1aa6eSZhao Qiang	  protocols: HDLC, Ethernet, ATM, transparent
317aa1aa6eSZhao Qiang
327aa1aa6eSZhao Qiangconfig UCC
337aa1aa6eSZhao Qiang	bool
347ac94702SHerve Codina	default y if UCC_FAST || UCC_SLOW || (CPM_TSA && QUICC_ENGINE)
357aa1aa6eSZhao Qiang
361d4ba0b8SHerve Codinaconfig CPM_TSA
377ac94702SHerve Codina	tristate "CPM/QE TSA support"
381d4ba0b8SHerve Codina	depends on OF && HAS_IOMEM
397ac94702SHerve Codina	depends on CPM1 || QUICC_ENGINE || \
407ac94702SHerve Codina		   ((CPM || QUICC_ENGINE) && COMPILE_TEST)
411d4ba0b8SHerve Codina	help
427ac94702SHerve Codina	  Freescale CPM/QE Time Slot Assigner (TSA)
431d4ba0b8SHerve Codina	  controller.
441d4ba0b8SHerve Codina
451d4ba0b8SHerve Codina	  This option enables support for this
461d4ba0b8SHerve Codina	  controller
471d4ba0b8SHerve Codina
483178d58eSHerve Codinaconfig CPM_QMC
49*eb680d56SHerve Codina	tristate "CPM/QE QMC support"
503178d58eSHerve Codina	depends on OF && HAS_IOMEM
51*eb680d56SHerve Codina	depends on CPM1 || QUICC_ENGINE || \
52*eb680d56SHerve Codina		   (FSL_SOC && (CPM || QUICC_ENGINE) && COMPILE_TEST)
533178d58eSHerve Codina	depends on CPM_TSA
543178d58eSHerve Codina	help
55*eb680d56SHerve Codina	  Freescale CPM/QE QUICC Multichannel Controller
563178d58eSHerve Codina	  (QMC)
573178d58eSHerve Codina
583178d58eSHerve Codina	  This option enables support for this
593178d58eSHerve Codina	  controller
603178d58eSHerve Codina
6135ef1c20SZhao Qiangconfig QE_TDM
6235ef1c20SZhao Qiang	bool
6335ef1c20SZhao Qiang	default y if FSL_UCC_HDLC
6435ef1c20SZhao Qiang
657aa1aa6eSZhao Qiangconfig QE_USB
667aa1aa6eSZhao Qiang	bool
677b1a78baSRandy Dunlap	depends on QUICC_ENGINE
687aa1aa6eSZhao Qiang	default y if USB_FSL_QE
697aa1aa6eSZhao Qiang	help
707aa1aa6eSZhao Qiang	  QE USB Controller support
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