xref: /linux/drivers/soc/fsl/qe/Kconfig (revision 1d4ba0b81c1cf2bfc0c55658f53809846ae9de52)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
27aa1aa6eSZhao Qiang#
37aa1aa6eSZhao Qiang# QE Communication options
47aa1aa6eSZhao Qiang#
57aa1aa6eSZhao Qiang
67aa1aa6eSZhao Qiangconfig QUICC_ENGINE
746252108SLi Yang	bool "QUICC Engine (QE) framework support"
85a35435eSRasmus Villemoes	depends on OF && HAS_IOMEM
95a35435eSRasmus Villemoes	depends on PPC || ARM || ARM64 || COMPILE_TEST
107aa1aa6eSZhao Qiang	select GENERIC_ALLOCATOR
117aa1aa6eSZhao Qiang	select CRC32
127aa1aa6eSZhao Qiang	help
137aa1aa6eSZhao Qiang	  The QUICC Engine (QE) is a new generation of communications
147aa1aa6eSZhao Qiang	  coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
157aa1aa6eSZhao Qiang	  Selecting this option means that you wish to build a kernel
167aa1aa6eSZhao Qiang	  for a machine with a QE coprocessor.
177aa1aa6eSZhao Qiang
187aa1aa6eSZhao Qiangconfig UCC_SLOW
197aa1aa6eSZhao Qiang	bool
207aa1aa6eSZhao Qiang	default y if SERIAL_QE
217aa1aa6eSZhao Qiang	help
227aa1aa6eSZhao Qiang	  This option provides qe_lib support to UCC slow
237aa1aa6eSZhao Qiang	  protocols: UART, BISYNC, QMC
247aa1aa6eSZhao Qiang
257aa1aa6eSZhao Qiangconfig UCC_FAST
267aa1aa6eSZhao Qiang	bool
2735ef1c20SZhao Qiang	default y if UCC_GETH || QE_TDM
287aa1aa6eSZhao Qiang	help
297aa1aa6eSZhao Qiang	  This option provides qe_lib support to UCC fast
307aa1aa6eSZhao Qiang	  protocols: HDLC, Ethernet, ATM, transparent
317aa1aa6eSZhao Qiang
327aa1aa6eSZhao Qiangconfig UCC
337aa1aa6eSZhao Qiang	bool
347aa1aa6eSZhao Qiang	default y if UCC_FAST || UCC_SLOW
357aa1aa6eSZhao Qiang
36*1d4ba0b8SHerve Codinaconfig CPM_TSA
37*1d4ba0b8SHerve Codina	tristate "CPM TSA support"
38*1d4ba0b8SHerve Codina	depends on OF && HAS_IOMEM
39*1d4ba0b8SHerve Codina	depends on CPM1 || COMPILE_TEST
40*1d4ba0b8SHerve Codina	help
41*1d4ba0b8SHerve Codina	  Freescale CPM Time Slot Assigner (TSA)
42*1d4ba0b8SHerve Codina	  controller.
43*1d4ba0b8SHerve Codina
44*1d4ba0b8SHerve Codina	  This option enables support for this
45*1d4ba0b8SHerve Codina	  controller
46*1d4ba0b8SHerve Codina
4735ef1c20SZhao Qiangconfig QE_TDM
4835ef1c20SZhao Qiang	bool
4935ef1c20SZhao Qiang	default y if FSL_UCC_HDLC
5035ef1c20SZhao Qiang
517aa1aa6eSZhao Qiangconfig QE_USB
527aa1aa6eSZhao Qiang	bool
537aa1aa6eSZhao Qiang	default y if USB_FSL_QE
547aa1aa6eSZhao Qiang	help
557aa1aa6eSZhao Qiang	  QE USB Controller support
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