1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Freescale Semiconductor nor the 11 * names of its contributors may be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * ALTERNATIVELY, this software may be distributed under the terms of the 15 * GNU General Public License ("GPL") as published by the Free Software 16 * Foundation, either version 2 of that License or (at your option) any 17 * later version. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qman_priv.h" 32 33 #define DQRR_MAXFILL 15 34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */ 35 #define IRQNAME "QMan portal %d" 36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */ 37 #define QMAN_POLL_LIMIT 32 38 #define QMAN_PIRQ_DQRR_ITHRESH 12 39 #define QMAN_DQRR_IT_MAX 15 40 #define QMAN_ITP_MAX 0xFFF 41 #define QMAN_PIRQ_MR_ITHRESH 4 42 #define QMAN_PIRQ_IPERIOD 100 43 44 /* Portal register assists */ 45 46 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 47 /* Cache-inhibited register offsets */ 48 #define QM_REG_EQCR_PI_CINH 0x3000 49 #define QM_REG_EQCR_CI_CINH 0x3040 50 #define QM_REG_EQCR_ITR 0x3080 51 #define QM_REG_DQRR_PI_CINH 0x3100 52 #define QM_REG_DQRR_CI_CINH 0x3140 53 #define QM_REG_DQRR_ITR 0x3180 54 #define QM_REG_DQRR_DCAP 0x31C0 55 #define QM_REG_DQRR_SDQCR 0x3200 56 #define QM_REG_DQRR_VDQCR 0x3240 57 #define QM_REG_DQRR_PDQCR 0x3280 58 #define QM_REG_MR_PI_CINH 0x3300 59 #define QM_REG_MR_CI_CINH 0x3340 60 #define QM_REG_MR_ITR 0x3380 61 #define QM_REG_CFG 0x3500 62 #define QM_REG_ISR 0x3600 63 #define QM_REG_IER 0x3640 64 #define QM_REG_ISDR 0x3680 65 #define QM_REG_IIR 0x36C0 66 #define QM_REG_ITPR 0x3740 67 68 /* Cache-enabled register offsets */ 69 #define QM_CL_EQCR 0x0000 70 #define QM_CL_DQRR 0x1000 71 #define QM_CL_MR 0x2000 72 #define QM_CL_EQCR_PI_CENA 0x3000 73 #define QM_CL_EQCR_CI_CENA 0x3040 74 #define QM_CL_DQRR_PI_CENA 0x3100 75 #define QM_CL_DQRR_CI_CENA 0x3140 76 #define QM_CL_MR_PI_CENA 0x3300 77 #define QM_CL_MR_CI_CENA 0x3340 78 #define QM_CL_CR 0x3800 79 #define QM_CL_RR0 0x3900 80 #define QM_CL_RR1 0x3940 81 82 #else 83 /* Cache-inhibited register offsets */ 84 #define QM_REG_EQCR_PI_CINH 0x0000 85 #define QM_REG_EQCR_CI_CINH 0x0004 86 #define QM_REG_EQCR_ITR 0x0008 87 #define QM_REG_DQRR_PI_CINH 0x0040 88 #define QM_REG_DQRR_CI_CINH 0x0044 89 #define QM_REG_DQRR_ITR 0x0048 90 #define QM_REG_DQRR_DCAP 0x0050 91 #define QM_REG_DQRR_SDQCR 0x0054 92 #define QM_REG_DQRR_VDQCR 0x0058 93 #define QM_REG_DQRR_PDQCR 0x005c 94 #define QM_REG_MR_PI_CINH 0x0080 95 #define QM_REG_MR_CI_CINH 0x0084 96 #define QM_REG_MR_ITR 0x0088 97 #define QM_REG_CFG 0x0100 98 #define QM_REG_ISR 0x0e00 99 #define QM_REG_IER 0x0e04 100 #define QM_REG_ISDR 0x0e08 101 #define QM_REG_IIR 0x0e0c 102 #define QM_REG_ITPR 0x0e14 103 104 /* Cache-enabled register offsets */ 105 #define QM_CL_EQCR 0x0000 106 #define QM_CL_DQRR 0x1000 107 #define QM_CL_MR 0x2000 108 #define QM_CL_EQCR_PI_CENA 0x3000 109 #define QM_CL_EQCR_CI_CENA 0x3100 110 #define QM_CL_DQRR_PI_CENA 0x3200 111 #define QM_CL_DQRR_CI_CENA 0x3300 112 #define QM_CL_MR_PI_CENA 0x3400 113 #define QM_CL_MR_CI_CENA 0x3500 114 #define QM_CL_CR 0x3800 115 #define QM_CL_RR0 0x3900 116 #define QM_CL_RR1 0x3940 117 #endif 118 119 /* 120 * BTW, the drivers (and h/w programming model) already obtain the required 121 * synchronisation for portal accesses and data-dependencies. Use of barrier()s 122 * or other order-preserving primitives simply degrade performance. Hence the 123 * use of the __raw_*() interfaces, which simply ensure that the compiler treats 124 * the portal registers as volatile 125 */ 126 127 /* Cache-enabled ring access */ 128 #define qm_cl(base, idx) ((void *)base + ((idx) << 6)) 129 130 /* 131 * Portal modes. 132 * Enum types; 133 * pmode == production mode 134 * cmode == consumption mode, 135 * dmode == h/w dequeue mode. 136 * Enum values use 3 letter codes. First letter matches the portal mode, 137 * remaining two letters indicate; 138 * ci == cache-inhibited portal register 139 * ce == cache-enabled portal register 140 * vb == in-band valid-bit (cache-enabled) 141 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only 142 * As for "enum qm_dqrr_dmode", it should be self-explanatory. 143 */ 144 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */ 145 qm_eqcr_pci = 0, /* PI index, cache-inhibited */ 146 qm_eqcr_pce = 1, /* PI index, cache-enabled */ 147 qm_eqcr_pvb = 2 /* valid-bit */ 148 }; 149 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */ 150 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */ 151 qm_dqrr_dpull = 1 /* PDQCR */ 152 }; 153 enum qm_dqrr_pmode { /* s/w-only */ 154 qm_dqrr_pci, /* reads DQRR_PI_CINH */ 155 qm_dqrr_pce, /* reads DQRR_PI_CENA */ 156 qm_dqrr_pvb /* reads valid-bit */ 157 }; 158 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */ 159 qm_dqrr_cci = 0, /* CI index, cache-inhibited */ 160 qm_dqrr_cce = 1, /* CI index, cache-enabled */ 161 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */ 162 }; 163 enum qm_mr_pmode { /* s/w-only */ 164 qm_mr_pci, /* reads MR_PI_CINH */ 165 qm_mr_pce, /* reads MR_PI_CENA */ 166 qm_mr_pvb /* reads valid-bit */ 167 }; 168 enum qm_mr_cmode { /* matches QCSP_CFG::MM */ 169 qm_mr_cci = 0, /* CI index, cache-inhibited */ 170 qm_mr_cce = 1 /* CI index, cache-enabled */ 171 }; 172 173 /* --- Portal structures --- */ 174 175 #define QM_EQCR_SIZE 8 176 #define QM_DQRR_SIZE 16 177 #define QM_MR_SIZE 8 178 179 /* "Enqueue Command" */ 180 struct qm_eqcr_entry { 181 u8 _ncw_verb; /* writes to this are non-coherent */ 182 u8 dca; 183 __be16 seqnum; 184 u8 __reserved[4]; 185 __be32 fqid; /* 24-bit */ 186 __be32 tag; 187 struct qm_fd fd; 188 u8 __reserved3[32]; 189 } __packed; 190 #define QM_EQCR_VERB_VBIT 0x80 191 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */ 192 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01 193 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */ 194 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */ 195 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */ 196 197 struct qm_eqcr { 198 struct qm_eqcr_entry *ring, *cursor; 199 u8 ci, available, ithresh, vbit; 200 #ifdef CONFIG_FSL_DPAA_CHECKING 201 u32 busy; 202 enum qm_eqcr_pmode pmode; 203 #endif 204 }; 205 206 struct qm_dqrr { 207 const struct qm_dqrr_entry *ring, *cursor; 208 u8 pi, ci, fill, ithresh, vbit; 209 #ifdef CONFIG_FSL_DPAA_CHECKING 210 enum qm_dqrr_dmode dmode; 211 enum qm_dqrr_pmode pmode; 212 enum qm_dqrr_cmode cmode; 213 #endif 214 }; 215 216 struct qm_mr { 217 union qm_mr_entry *ring, *cursor; 218 u8 pi, ci, fill, ithresh, vbit; 219 #ifdef CONFIG_FSL_DPAA_CHECKING 220 enum qm_mr_pmode pmode; 221 enum qm_mr_cmode cmode; 222 #endif 223 }; 224 225 /* MC (Management Command) command */ 226 /* "FQ" command layout */ 227 struct qm_mcc_fq { 228 u8 _ncw_verb; 229 u8 __reserved1[3]; 230 __be32 fqid; /* 24-bit */ 231 u8 __reserved2[56]; 232 } __packed; 233 234 /* "CGR" command layout */ 235 struct qm_mcc_cgr { 236 u8 _ncw_verb; 237 u8 __reserved1[30]; 238 u8 cgid; 239 u8 __reserved2[32]; 240 }; 241 242 #define QM_MCC_VERB_VBIT 0x80 243 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */ 244 #define QM_MCC_VERB_INITFQ_PARKED 0x40 245 #define QM_MCC_VERB_INITFQ_SCHED 0x41 246 #define QM_MCC_VERB_QUERYFQ 0x44 247 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */ 248 #define QM_MCC_VERB_QUERYWQ 0x46 249 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47 250 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */ 251 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */ 252 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */ 253 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */ 254 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */ 255 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */ 256 #define QM_MCC_VERB_INITCGR 0x50 257 #define QM_MCC_VERB_MODIFYCGR 0x51 258 #define QM_MCC_VERB_CGRTESTWRITE 0x52 259 #define QM_MCC_VERB_QUERYCGR 0x58 260 #define QM_MCC_VERB_QUERYCONGESTION 0x59 261 union qm_mc_command { 262 struct { 263 u8 _ncw_verb; /* writes to this are non-coherent */ 264 u8 __reserved[63]; 265 }; 266 struct qm_mcc_initfq initfq; 267 struct qm_mcc_initcgr initcgr; 268 struct qm_mcc_fq fq; 269 struct qm_mcc_cgr cgr; 270 }; 271 272 /* MC (Management Command) result */ 273 /* "Query FQ" */ 274 struct qm_mcr_queryfq { 275 u8 verb; 276 u8 result; 277 u8 __reserved1[8]; 278 struct qm_fqd fqd; /* the FQD fields are here */ 279 u8 __reserved2[30]; 280 } __packed; 281 282 /* "Alter FQ State Commands" */ 283 struct qm_mcr_alterfq { 284 u8 verb; 285 u8 result; 286 u8 fqs; /* Frame Queue Status */ 287 u8 __reserved1[61]; 288 }; 289 #define QM_MCR_VERB_RRID 0x80 290 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK 291 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED 292 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED 293 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ 294 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP 295 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ 296 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED 297 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED 298 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE 299 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE 300 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS 301 #define QM_MCR_RESULT_NULL 0x00 302 #define QM_MCR_RESULT_OK 0xf0 303 #define QM_MCR_RESULT_ERR_FQID 0xf1 304 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2 305 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */ 306 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4 307 #define QM_MCR_RESULT_PENDING 0xf8 308 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff 309 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ 310 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ 311 #define QM_MCR_TIMEOUT 10000 /* us */ 312 union qm_mc_result { 313 struct { 314 u8 verb; 315 u8 result; 316 u8 __reserved1[62]; 317 }; 318 struct qm_mcr_queryfq queryfq; 319 struct qm_mcr_alterfq alterfq; 320 struct qm_mcr_querycgr querycgr; 321 struct qm_mcr_querycongestion querycongestion; 322 struct qm_mcr_querywq querywq; 323 struct qm_mcr_queryfq_np queryfq_np; 324 }; 325 326 struct qm_mc { 327 union qm_mc_command *cr; 328 union qm_mc_result *rr; 329 u8 rridx, vbit; 330 #ifdef CONFIG_FSL_DPAA_CHECKING 331 enum { 332 /* Can be _mc_start()ed */ 333 qman_mc_idle, 334 /* Can be _mc_commit()ed or _mc_abort()ed */ 335 qman_mc_user, 336 /* Can only be _mc_retry()ed */ 337 qman_mc_hw 338 } state; 339 #endif 340 }; 341 342 struct qm_addr { 343 void *ce; /* cache-enabled */ 344 __be32 *ce_be; /* same value as above but for direct access */ 345 void __iomem *ci; /* cache-inhibited */ 346 }; 347 348 struct qm_portal { 349 /* 350 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to 351 * and including 'mc' fits within a cacheline (yay!). The 'config' part 352 * is setup-only, so isn't a cause for a concern. In other words, don't 353 * rearrange this structure on a whim, there be dragons ... 354 */ 355 struct qm_addr addr; 356 struct qm_eqcr eqcr; 357 struct qm_dqrr dqrr; 358 struct qm_mr mr; 359 struct qm_mc mc; 360 } ____cacheline_aligned; 361 362 /* Cache-inhibited register access. */ 363 static inline u32 qm_in(struct qm_portal *p, u32 offset) 364 { 365 return ioread32be(p->addr.ci + offset); 366 } 367 368 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val) 369 { 370 iowrite32be(val, p->addr.ci + offset); 371 } 372 373 /* Cache Enabled Portal Access */ 374 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset) 375 { 376 dpaa_invalidate(p->addr.ce + offset); 377 } 378 379 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset) 380 { 381 dpaa_touch_ro(p->addr.ce + offset); 382 } 383 384 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset) 385 { 386 return be32_to_cpu(*(p->addr.ce_be + (offset/4))); 387 } 388 389 /* --- EQCR API --- */ 390 391 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry)) 392 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT) 393 394 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */ 395 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p) 396 { 397 uintptr_t addr = (uintptr_t)p; 398 399 addr &= ~EQCR_CARRY; 400 401 return (struct qm_eqcr_entry *)addr; 402 } 403 404 /* Bit-wise logic to convert a ring pointer to a ring index */ 405 static int eqcr_ptr2idx(struct qm_eqcr_entry *e) 406 { 407 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1); 408 } 409 410 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */ 411 static inline void eqcr_inc(struct qm_eqcr *eqcr) 412 { 413 /* increment to the next EQCR pointer and handle overflow and 'vbit' */ 414 struct qm_eqcr_entry *partial = eqcr->cursor + 1; 415 416 eqcr->cursor = eqcr_carryclear(partial); 417 if (partial != eqcr->cursor) 418 eqcr->vbit ^= QM_EQCR_VERB_VBIT; 419 } 420 421 static inline int qm_eqcr_init(struct qm_portal *portal, 422 enum qm_eqcr_pmode pmode, 423 unsigned int eq_stash_thresh, 424 int eq_stash_prio) 425 { 426 struct qm_eqcr *eqcr = &portal->eqcr; 427 u32 cfg; 428 u8 pi; 429 430 eqcr->ring = portal->addr.ce + QM_CL_EQCR; 431 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); 432 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA); 433 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); 434 eqcr->cursor = eqcr->ring + pi; 435 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ? 436 QM_EQCR_VERB_VBIT : 0; 437 eqcr->available = QM_EQCR_SIZE - 1 - 438 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi); 439 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR); 440 #ifdef CONFIG_FSL_DPAA_CHECKING 441 eqcr->busy = 0; 442 eqcr->pmode = pmode; 443 #endif 444 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) | 445 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */ 446 (eq_stash_prio << 26) | /* QCSP_CFG: EP */ 447 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */ 448 qm_out(portal, QM_REG_CFG, cfg); 449 return 0; 450 } 451 452 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal) 453 { 454 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7; 455 } 456 457 static inline void qm_eqcr_finish(struct qm_portal *portal) 458 { 459 struct qm_eqcr *eqcr = &portal->eqcr; 460 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); 461 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); 462 463 DPAA_ASSERT(!eqcr->busy); 464 if (pi != eqcr_ptr2idx(eqcr->cursor)) 465 pr_crit("losing uncommitted EQCR entries\n"); 466 if (ci != eqcr->ci) 467 pr_crit("missing existing EQCR completions\n"); 468 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor)) 469 pr_crit("EQCR destroyed unquiesced\n"); 470 } 471 472 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal 473 *portal) 474 { 475 struct qm_eqcr *eqcr = &portal->eqcr; 476 477 DPAA_ASSERT(!eqcr->busy); 478 if (!eqcr->available) 479 return NULL; 480 481 #ifdef CONFIG_FSL_DPAA_CHECKING 482 eqcr->busy = 1; 483 #endif 484 dpaa_zero(eqcr->cursor); 485 return eqcr->cursor; 486 } 487 488 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal 489 *portal) 490 { 491 struct qm_eqcr *eqcr = &portal->eqcr; 492 u8 diff, old_ci; 493 494 DPAA_ASSERT(!eqcr->busy); 495 if (!eqcr->available) { 496 old_ci = eqcr->ci; 497 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & 498 (QM_EQCR_SIZE - 1); 499 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); 500 eqcr->available += diff; 501 if (!diff) 502 return NULL; 503 } 504 #ifdef CONFIG_FSL_DPAA_CHECKING 505 eqcr->busy = 1; 506 #endif 507 dpaa_zero(eqcr->cursor); 508 return eqcr->cursor; 509 } 510 511 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr) 512 { 513 DPAA_ASSERT(eqcr->busy); 514 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK)); 515 DPAA_ASSERT(eqcr->available >= 1); 516 } 517 518 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb) 519 { 520 struct qm_eqcr *eqcr = &portal->eqcr; 521 struct qm_eqcr_entry *eqcursor; 522 523 eqcr_commit_checks(eqcr); 524 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb); 525 dma_wmb(); 526 eqcursor = eqcr->cursor; 527 eqcursor->_ncw_verb = myverb | eqcr->vbit; 528 dpaa_flush(eqcursor); 529 eqcr_inc(eqcr); 530 eqcr->available--; 531 #ifdef CONFIG_FSL_DPAA_CHECKING 532 eqcr->busy = 0; 533 #endif 534 } 535 536 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal) 537 { 538 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA); 539 } 540 541 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal) 542 { 543 struct qm_eqcr *eqcr = &portal->eqcr; 544 u8 diff, old_ci = eqcr->ci; 545 546 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1); 547 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA); 548 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); 549 eqcr->available += diff; 550 return diff; 551 } 552 553 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh) 554 { 555 struct qm_eqcr *eqcr = &portal->eqcr; 556 557 eqcr->ithresh = ithresh; 558 qm_out(portal, QM_REG_EQCR_ITR, ithresh); 559 } 560 561 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal) 562 { 563 struct qm_eqcr *eqcr = &portal->eqcr; 564 565 return eqcr->available; 566 } 567 568 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal) 569 { 570 struct qm_eqcr *eqcr = &portal->eqcr; 571 572 return QM_EQCR_SIZE - 1 - eqcr->available; 573 } 574 575 /* --- DQRR API --- */ 576 577 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry)) 578 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT) 579 580 static const struct qm_dqrr_entry *dqrr_carryclear( 581 const struct qm_dqrr_entry *p) 582 { 583 uintptr_t addr = (uintptr_t)p; 584 585 addr &= ~DQRR_CARRY; 586 587 return (const struct qm_dqrr_entry *)addr; 588 } 589 590 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e) 591 { 592 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1); 593 } 594 595 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e) 596 { 597 return dqrr_carryclear(e + 1); 598 } 599 600 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf) 601 { 602 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) | 603 ((mf & (QM_DQRR_SIZE - 1)) << 20)); 604 } 605 606 static inline int qm_dqrr_init(struct qm_portal *portal, 607 const struct qm_portal_config *config, 608 enum qm_dqrr_dmode dmode, 609 enum qm_dqrr_pmode pmode, 610 enum qm_dqrr_cmode cmode, u8 max_fill) 611 { 612 struct qm_dqrr *dqrr = &portal->dqrr; 613 u32 cfg; 614 615 /* Make sure the DQRR will be idle when we enable */ 616 qm_out(portal, QM_REG_DQRR_SDQCR, 0); 617 qm_out(portal, QM_REG_DQRR_VDQCR, 0); 618 qm_out(portal, QM_REG_DQRR_PDQCR, 0); 619 dqrr->ring = portal->addr.ce + QM_CL_DQRR; 620 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1); 621 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1); 622 dqrr->cursor = dqrr->ring + dqrr->ci; 623 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi); 624 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ? 625 QM_DQRR_VERB_VBIT : 0; 626 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR); 627 #ifdef CONFIG_FSL_DPAA_CHECKING 628 dqrr->dmode = dmode; 629 dqrr->pmode = pmode; 630 dqrr->cmode = cmode; 631 #endif 632 /* Invalidate every ring entry before beginning */ 633 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++) 634 dpaa_invalidate(qm_cl(dqrr->ring, cfg)); 635 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) | 636 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */ 637 ((dmode & 1) << 18) | /* DP */ 638 ((cmode & 3) << 16) | /* DCM */ 639 0xa0 | /* RE+SE */ 640 (0 ? 0x40 : 0) | /* Ignore RP */ 641 (0 ? 0x10 : 0); /* Ignore SP */ 642 qm_out(portal, QM_REG_CFG, cfg); 643 qm_dqrr_set_maxfill(portal, max_fill); 644 return 0; 645 } 646 647 static inline void qm_dqrr_finish(struct qm_portal *portal) 648 { 649 #ifdef CONFIG_FSL_DPAA_CHECKING 650 struct qm_dqrr *dqrr = &portal->dqrr; 651 652 if (dqrr->cmode != qm_dqrr_cdc && 653 dqrr->ci != dqrr_ptr2idx(dqrr->cursor)) 654 pr_crit("Ignoring completed DQRR entries\n"); 655 #endif 656 } 657 658 static inline const struct qm_dqrr_entry *qm_dqrr_current( 659 struct qm_portal *portal) 660 { 661 struct qm_dqrr *dqrr = &portal->dqrr; 662 663 if (!dqrr->fill) 664 return NULL; 665 return dqrr->cursor; 666 } 667 668 static inline u8 qm_dqrr_next(struct qm_portal *portal) 669 { 670 struct qm_dqrr *dqrr = &portal->dqrr; 671 672 DPAA_ASSERT(dqrr->fill); 673 dqrr->cursor = dqrr_inc(dqrr->cursor); 674 return --dqrr->fill; 675 } 676 677 static inline void qm_dqrr_pvb_update(struct qm_portal *portal) 678 { 679 struct qm_dqrr *dqrr = &portal->dqrr; 680 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi); 681 682 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb); 683 #ifndef CONFIG_FSL_PAMU 684 /* 685 * If PAMU is not available we need to invalidate the cache. 686 * When PAMU is available the cache is updated by stash 687 */ 688 dpaa_invalidate_touch_ro(res); 689 #endif 690 if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) { 691 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1); 692 if (!dqrr->pi) 693 dqrr->vbit ^= QM_DQRR_VERB_VBIT; 694 dqrr->fill++; 695 } 696 } 697 698 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal, 699 const struct qm_dqrr_entry *dq, 700 int park) 701 { 702 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr; 703 int idx = dqrr_ptr2idx(dq); 704 705 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc); 706 DPAA_ASSERT((dqrr->ring + idx) == dq); 707 DPAA_ASSERT(idx < QM_DQRR_SIZE); 708 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */ 709 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */ 710 idx); /* DQRR_DCAP::DCAP_CI */ 711 } 712 713 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask) 714 { 715 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr; 716 717 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc); 718 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */ 719 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */ 720 } 721 722 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr) 723 { 724 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr); 725 } 726 727 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr) 728 { 729 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr); 730 } 731 732 static inline int qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh) 733 { 734 735 if (ithresh > QMAN_DQRR_IT_MAX) 736 return -EINVAL; 737 738 qm_out(portal, QM_REG_DQRR_ITR, ithresh); 739 740 return 0; 741 } 742 743 /* --- MR API --- */ 744 745 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry)) 746 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT) 747 748 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p) 749 { 750 uintptr_t addr = (uintptr_t)p; 751 752 addr &= ~MR_CARRY; 753 754 return (union qm_mr_entry *)addr; 755 } 756 757 static inline int mr_ptr2idx(const union qm_mr_entry *e) 758 { 759 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1); 760 } 761 762 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e) 763 { 764 return mr_carryclear(e + 1); 765 } 766 767 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode, 768 enum qm_mr_cmode cmode) 769 { 770 struct qm_mr *mr = &portal->mr; 771 u32 cfg; 772 773 mr->ring = portal->addr.ce + QM_CL_MR; 774 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1); 775 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1); 776 mr->cursor = mr->ring + mr->ci; 777 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi); 778 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE) 779 ? QM_MR_VERB_VBIT : 0; 780 mr->ithresh = qm_in(portal, QM_REG_MR_ITR); 781 #ifdef CONFIG_FSL_DPAA_CHECKING 782 mr->pmode = pmode; 783 mr->cmode = cmode; 784 #endif 785 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) | 786 ((cmode & 1) << 8); /* QCSP_CFG:MM */ 787 qm_out(portal, QM_REG_CFG, cfg); 788 return 0; 789 } 790 791 static inline void qm_mr_finish(struct qm_portal *portal) 792 { 793 struct qm_mr *mr = &portal->mr; 794 795 if (mr->ci != mr_ptr2idx(mr->cursor)) 796 pr_crit("Ignoring completed MR entries\n"); 797 } 798 799 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal) 800 { 801 struct qm_mr *mr = &portal->mr; 802 803 if (!mr->fill) 804 return NULL; 805 return mr->cursor; 806 } 807 808 static inline int qm_mr_next(struct qm_portal *portal) 809 { 810 struct qm_mr *mr = &portal->mr; 811 812 DPAA_ASSERT(mr->fill); 813 mr->cursor = mr_inc(mr->cursor); 814 return --mr->fill; 815 } 816 817 static inline void qm_mr_pvb_update(struct qm_portal *portal) 818 { 819 struct qm_mr *mr = &portal->mr; 820 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi); 821 822 DPAA_ASSERT(mr->pmode == qm_mr_pvb); 823 824 if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) { 825 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1); 826 if (!mr->pi) 827 mr->vbit ^= QM_MR_VERB_VBIT; 828 mr->fill++; 829 res = mr_inc(res); 830 } 831 dpaa_invalidate_touch_ro(res); 832 } 833 834 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num) 835 { 836 struct qm_mr *mr = &portal->mr; 837 838 DPAA_ASSERT(mr->cmode == qm_mr_cci); 839 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1); 840 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci); 841 } 842 843 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal) 844 { 845 struct qm_mr *mr = &portal->mr; 846 847 DPAA_ASSERT(mr->cmode == qm_mr_cci); 848 mr->ci = mr_ptr2idx(mr->cursor); 849 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci); 850 } 851 852 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh) 853 { 854 qm_out(portal, QM_REG_MR_ITR, ithresh); 855 } 856 857 /* --- Management command API --- */ 858 859 static inline int qm_mc_init(struct qm_portal *portal) 860 { 861 u8 rr0, rr1; 862 struct qm_mc *mc = &portal->mc; 863 864 mc->cr = portal->addr.ce + QM_CL_CR; 865 mc->rr = portal->addr.ce + QM_CL_RR0; 866 /* 867 * The expected valid bit polarity for the next CR command is 0 868 * if RR1 contains a valid response, and is 1 if RR0 contains a 869 * valid response. If both RR contain all 0, this indicates either 870 * that no command has been executed since reset (in which case the 871 * expected valid bit polarity is 1) 872 */ 873 rr0 = mc->rr->verb; 874 rr1 = (mc->rr+1)->verb; 875 if ((rr0 == 0 && rr1 == 0) || rr0 != 0) 876 mc->rridx = 1; 877 else 878 mc->rridx = 0; 879 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0; 880 #ifdef CONFIG_FSL_DPAA_CHECKING 881 mc->state = qman_mc_idle; 882 #endif 883 return 0; 884 } 885 886 static inline void qm_mc_finish(struct qm_portal *portal) 887 { 888 #ifdef CONFIG_FSL_DPAA_CHECKING 889 struct qm_mc *mc = &portal->mc; 890 891 DPAA_ASSERT(mc->state == qman_mc_idle); 892 if (mc->state != qman_mc_idle) 893 pr_crit("Losing incomplete MC command\n"); 894 #endif 895 } 896 897 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal) 898 { 899 struct qm_mc *mc = &portal->mc; 900 901 DPAA_ASSERT(mc->state == qman_mc_idle); 902 #ifdef CONFIG_FSL_DPAA_CHECKING 903 mc->state = qman_mc_user; 904 #endif 905 dpaa_zero(mc->cr); 906 return mc->cr; 907 } 908 909 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb) 910 { 911 struct qm_mc *mc = &portal->mc; 912 union qm_mc_result *rr = mc->rr + mc->rridx; 913 914 DPAA_ASSERT(mc->state == qman_mc_user); 915 dma_wmb(); 916 mc->cr->_ncw_verb = myverb | mc->vbit; 917 dpaa_flush(mc->cr); 918 dpaa_invalidate_touch_ro(rr); 919 #ifdef CONFIG_FSL_DPAA_CHECKING 920 mc->state = qman_mc_hw; 921 #endif 922 } 923 924 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal) 925 { 926 struct qm_mc *mc = &portal->mc; 927 union qm_mc_result *rr = mc->rr + mc->rridx; 928 929 DPAA_ASSERT(mc->state == qman_mc_hw); 930 /* 931 * The inactive response register's verb byte always returns zero until 932 * its command is submitted and completed. This includes the valid-bit, 933 * in case you were wondering... 934 */ 935 if (!rr->verb) { 936 dpaa_invalidate_touch_ro(rr); 937 return NULL; 938 } 939 mc->rridx ^= 1; 940 mc->vbit ^= QM_MCC_VERB_VBIT; 941 #ifdef CONFIG_FSL_DPAA_CHECKING 942 mc->state = qman_mc_idle; 943 #endif 944 return rr; 945 } 946 947 static inline int qm_mc_result_timeout(struct qm_portal *portal, 948 union qm_mc_result **mcr) 949 { 950 int timeout = QM_MCR_TIMEOUT; 951 952 do { 953 *mcr = qm_mc_result(portal); 954 if (*mcr) 955 break; 956 udelay(1); 957 } while (--timeout); 958 959 return timeout; 960 } 961 962 static inline void fq_set(struct qman_fq *fq, u32 mask) 963 { 964 fq->flags |= mask; 965 } 966 967 static inline void fq_clear(struct qman_fq *fq, u32 mask) 968 { 969 fq->flags &= ~mask; 970 } 971 972 static inline int fq_isset(struct qman_fq *fq, u32 mask) 973 { 974 return fq->flags & mask; 975 } 976 977 static inline int fq_isclear(struct qman_fq *fq, u32 mask) 978 { 979 return !(fq->flags & mask); 980 } 981 982 struct qman_portal { 983 struct qm_portal p; 984 /* PORTAL_BITS_*** - dynamic, strictly internal */ 985 unsigned long bits; 986 /* interrupt sources processed by portal_isr(), configurable */ 987 unsigned long irq_sources; 988 u32 use_eqcr_ci_stashing; 989 /* only 1 volatile dequeue at a time */ 990 struct qman_fq *vdqcr_owned; 991 u32 sdqcr; 992 /* probing time config params for cpu-affine portals */ 993 const struct qm_portal_config *config; 994 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */ 995 struct qman_cgrs *cgrs; 996 /* linked-list of CSCN handlers. */ 997 struct list_head cgr_cbs; 998 /* list lock */ 999 spinlock_t cgr_lock; 1000 struct work_struct congestion_work; 1001 struct work_struct mr_work; 1002 char irqname[MAX_IRQNAME]; 1003 }; 1004 1005 static cpumask_t affine_mask; 1006 static DEFINE_SPINLOCK(affine_mask_lock); 1007 static u16 affine_channels[NR_CPUS]; 1008 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal); 1009 struct qman_portal *affine_portals[NR_CPUS]; 1010 1011 static inline struct qman_portal *get_affine_portal(void) 1012 { 1013 return &get_cpu_var(qman_affine_portal); 1014 } 1015 1016 static inline void put_affine_portal(void) 1017 { 1018 put_cpu_var(qman_affine_portal); 1019 } 1020 1021 1022 static inline struct qman_portal *get_portal_for_channel(u16 channel) 1023 { 1024 int i; 1025 1026 for (i = 0; i < num_possible_cpus(); i++) { 1027 if (affine_portals[i] && 1028 affine_portals[i]->config->channel == channel) 1029 return affine_portals[i]; 1030 } 1031 1032 return NULL; 1033 } 1034 1035 static struct workqueue_struct *qm_portal_wq; 1036 1037 int qman_dqrr_set_ithresh(struct qman_portal *portal, u8 ithresh) 1038 { 1039 int res; 1040 1041 if (!portal) 1042 return -EINVAL; 1043 1044 res = qm_dqrr_set_ithresh(&portal->p, ithresh); 1045 if (res) 1046 return res; 1047 1048 portal->p.dqrr.ithresh = ithresh; 1049 1050 return 0; 1051 } 1052 EXPORT_SYMBOL(qman_dqrr_set_ithresh); 1053 1054 void qman_dqrr_get_ithresh(struct qman_portal *portal, u8 *ithresh) 1055 { 1056 if (portal && ithresh) 1057 *ithresh = qm_in(&portal->p, QM_REG_DQRR_ITR); 1058 } 1059 EXPORT_SYMBOL(qman_dqrr_get_ithresh); 1060 1061 void qman_portal_get_iperiod(struct qman_portal *portal, u32 *iperiod) 1062 { 1063 if (portal && iperiod) 1064 *iperiod = qm_in(&portal->p, QM_REG_ITPR); 1065 } 1066 EXPORT_SYMBOL(qman_portal_get_iperiod); 1067 1068 int qman_portal_set_iperiod(struct qman_portal *portal, u32 iperiod) 1069 { 1070 if (!portal || iperiod > QMAN_ITP_MAX) 1071 return -EINVAL; 1072 1073 qm_out(&portal->p, QM_REG_ITPR, iperiod); 1074 1075 return 0; 1076 } 1077 EXPORT_SYMBOL(qman_portal_set_iperiod); 1078 1079 int qman_wq_alloc(void) 1080 { 1081 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1); 1082 if (!qm_portal_wq) 1083 return -ENOMEM; 1084 return 0; 1085 } 1086 1087 1088 void qman_enable_irqs(void) 1089 { 1090 int i; 1091 1092 for (i = 0; i < num_possible_cpus(); i++) { 1093 if (affine_portals[i]) { 1094 qm_out(&affine_portals[i]->p, QM_REG_ISR, 0xffffffff); 1095 qm_out(&affine_portals[i]->p, QM_REG_IIR, 0); 1096 } 1097 1098 } 1099 } 1100 1101 /* 1102 * This is what everything can wait on, even if it migrates to a different cpu 1103 * to the one whose affine portal it is waiting on. 1104 */ 1105 static DECLARE_WAIT_QUEUE_HEAD(affine_queue); 1106 1107 static struct qman_fq **fq_table; 1108 static u32 num_fqids; 1109 1110 int qman_alloc_fq_table(u32 _num_fqids) 1111 { 1112 num_fqids = _num_fqids; 1113 1114 fq_table = vzalloc(array3_size(sizeof(struct qman_fq *), 1115 num_fqids, 2)); 1116 if (!fq_table) 1117 return -ENOMEM; 1118 1119 pr_debug("Allocated fq lookup table at %p, entry count %u\n", 1120 fq_table, num_fqids * 2); 1121 return 0; 1122 } 1123 1124 static struct qman_fq *idx_to_fq(u32 idx) 1125 { 1126 struct qman_fq *fq; 1127 1128 #ifdef CONFIG_FSL_DPAA_CHECKING 1129 if (WARN_ON(idx >= num_fqids * 2)) 1130 return NULL; 1131 #endif 1132 fq = fq_table[idx]; 1133 DPAA_ASSERT(!fq || idx == fq->idx); 1134 1135 return fq; 1136 } 1137 1138 /* 1139 * Only returns full-service fq objects, not enqueue-only 1140 * references (QMAN_FQ_FLAG_NO_MODIFY). 1141 */ 1142 static struct qman_fq *fqid_to_fq(u32 fqid) 1143 { 1144 return idx_to_fq(fqid * 2); 1145 } 1146 1147 static struct qman_fq *tag_to_fq(u32 tag) 1148 { 1149 #if BITS_PER_LONG == 64 1150 return idx_to_fq(tag); 1151 #else 1152 return (struct qman_fq *)tag; 1153 #endif 1154 } 1155 1156 static u32 fq_to_tag(struct qman_fq *fq) 1157 { 1158 #if BITS_PER_LONG == 64 1159 return fq->idx; 1160 #else 1161 return (u32)fq; 1162 #endif 1163 } 1164 1165 static u32 __poll_portal_slow(struct qman_portal *p, u32 is); 1166 static inline unsigned int __poll_portal_fast(struct qman_portal *p, 1167 unsigned int poll_limit); 1168 static void qm_congestion_task(struct work_struct *work); 1169 static void qm_mr_process_task(struct work_struct *work); 1170 1171 static irqreturn_t portal_isr(int irq, void *ptr) 1172 { 1173 struct qman_portal *p = ptr; 1174 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources; 1175 u32 clear = 0; 1176 1177 if (unlikely(!is)) 1178 return IRQ_NONE; 1179 1180 /* DQRR-handling if it's interrupt-driven */ 1181 if (is & QM_PIRQ_DQRI) { 1182 __poll_portal_fast(p, QMAN_POLL_LIMIT); 1183 clear = QM_DQAVAIL_MASK | QM_PIRQ_DQRI; 1184 } 1185 /* Handling of anything else that's interrupt-driven */ 1186 clear |= __poll_portal_slow(p, is) & QM_PIRQ_SLOW; 1187 qm_out(&p->p, QM_REG_ISR, clear); 1188 return IRQ_HANDLED; 1189 } 1190 1191 static int drain_mr_fqrni(struct qm_portal *p) 1192 { 1193 const union qm_mr_entry *msg; 1194 loop: 1195 qm_mr_pvb_update(p); 1196 msg = qm_mr_current(p); 1197 if (!msg) { 1198 /* 1199 * if MR was full and h/w had other FQRNI entries to produce, we 1200 * need to allow it time to produce those entries once the 1201 * existing entries are consumed. A worst-case situation 1202 * (fully-loaded system) means h/w sequencers may have to do 3-4 1203 * other things before servicing the portal's MR pump, each of 1204 * which (if slow) may take ~50 qman cycles (which is ~200 1205 * processor cycles). So rounding up and then multiplying this 1206 * worst-case estimate by a factor of 10, just to be 1207 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume 1208 * one entry at a time, so h/w has an opportunity to produce new 1209 * entries well before the ring has been fully consumed, so 1210 * we're being *really* paranoid here. 1211 */ 1212 mdelay(1); 1213 qm_mr_pvb_update(p); 1214 msg = qm_mr_current(p); 1215 if (!msg) 1216 return 0; 1217 } 1218 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) { 1219 /* We aren't draining anything but FQRNIs */ 1220 pr_err("Found verb 0x%x in MR\n", msg->verb); 1221 return -1; 1222 } 1223 qm_mr_next(p); 1224 qm_mr_cci_consume(p, 1); 1225 goto loop; 1226 } 1227 1228 static int qman_create_portal(struct qman_portal *portal, 1229 const struct qm_portal_config *c, 1230 const struct qman_cgrs *cgrs) 1231 { 1232 struct qm_portal *p; 1233 int ret; 1234 u32 isdr; 1235 1236 p = &portal->p; 1237 1238 #ifdef CONFIG_FSL_PAMU 1239 /* PAMU is required for stashing */ 1240 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0); 1241 #else 1242 portal->use_eqcr_ci_stashing = 0; 1243 #endif 1244 /* 1245 * prep the low-level portal struct with the mapped addresses from the 1246 * config, everything that follows depends on it and "config" is more 1247 * for (de)reference 1248 */ 1249 p->addr.ce = c->addr_virt_ce; 1250 p->addr.ce_be = c->addr_virt_ce; 1251 p->addr.ci = c->addr_virt_ci; 1252 /* 1253 * If CI-stashing is used, the current defaults use a threshold of 3, 1254 * and stash with high-than-DQRR priority. 1255 */ 1256 if (qm_eqcr_init(p, qm_eqcr_pvb, 1257 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) { 1258 dev_err(c->dev, "EQCR initialisation failed\n"); 1259 goto fail_eqcr; 1260 } 1261 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb, 1262 qm_dqrr_cdc, DQRR_MAXFILL)) { 1263 dev_err(c->dev, "DQRR initialisation failed\n"); 1264 goto fail_dqrr; 1265 } 1266 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) { 1267 dev_err(c->dev, "MR initialisation failed\n"); 1268 goto fail_mr; 1269 } 1270 if (qm_mc_init(p)) { 1271 dev_err(c->dev, "MC initialisation failed\n"); 1272 goto fail_mc; 1273 } 1274 /* static interrupt-gating controls */ 1275 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH); 1276 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH); 1277 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD); 1278 portal->cgrs = kmalloc_array(2, sizeof(*cgrs), GFP_KERNEL); 1279 if (!portal->cgrs) 1280 goto fail_cgrs; 1281 /* initial snapshot is no-depletion */ 1282 qman_cgrs_init(&portal->cgrs[1]); 1283 if (cgrs) 1284 portal->cgrs[0] = *cgrs; 1285 else 1286 /* if the given mask is NULL, assume all CGRs can be seen */ 1287 qman_cgrs_fill(&portal->cgrs[0]); 1288 INIT_LIST_HEAD(&portal->cgr_cbs); 1289 spin_lock_init(&portal->cgr_lock); 1290 INIT_WORK(&portal->congestion_work, qm_congestion_task); 1291 INIT_WORK(&portal->mr_work, qm_mr_process_task); 1292 portal->bits = 0; 1293 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 | 1294 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS | 1295 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED; 1296 isdr = 0xffffffff; 1297 qm_out(p, QM_REG_ISDR, isdr); 1298 portal->irq_sources = 0; 1299 qm_out(p, QM_REG_IER, 0); 1300 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu); 1301 qm_out(p, QM_REG_IIR, 1); 1302 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) { 1303 dev_err(c->dev, "request_irq() failed\n"); 1304 goto fail_irq; 1305 } 1306 1307 if (dpaa_set_portal_irq_affinity(c->dev, c->irq, c->cpu)) 1308 goto fail_affinity; 1309 1310 /* Need EQCR to be empty before continuing */ 1311 isdr &= ~QM_PIRQ_EQCI; 1312 qm_out(p, QM_REG_ISDR, isdr); 1313 ret = qm_eqcr_get_fill(p); 1314 if (ret) { 1315 dev_err(c->dev, "EQCR unclean\n"); 1316 goto fail_eqcr_empty; 1317 } 1318 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI); 1319 qm_out(p, QM_REG_ISDR, isdr); 1320 if (qm_dqrr_current(p)) { 1321 dev_dbg(c->dev, "DQRR unclean\n"); 1322 qm_dqrr_cdc_consume_n(p, 0xffff); 1323 } 1324 if (qm_mr_current(p) && drain_mr_fqrni(p)) { 1325 /* special handling, drain just in case it's a few FQRNIs */ 1326 const union qm_mr_entry *e = qm_mr_current(p); 1327 1328 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n", 1329 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd)); 1330 goto fail_dqrr_mr_empty; 1331 } 1332 /* Success */ 1333 portal->config = c; 1334 qm_out(p, QM_REG_ISR, 0xffffffff); 1335 qm_out(p, QM_REG_ISDR, 0); 1336 if (!qman_requires_cleanup()) 1337 qm_out(p, QM_REG_IIR, 0); 1338 /* Write a sane SDQCR */ 1339 qm_dqrr_sdqcr_set(p, portal->sdqcr); 1340 return 0; 1341 1342 fail_dqrr_mr_empty: 1343 fail_eqcr_empty: 1344 fail_affinity: 1345 free_irq(c->irq, portal); 1346 fail_irq: 1347 kfree(portal->cgrs); 1348 fail_cgrs: 1349 qm_mc_finish(p); 1350 fail_mc: 1351 qm_mr_finish(p); 1352 fail_mr: 1353 qm_dqrr_finish(p); 1354 fail_dqrr: 1355 qm_eqcr_finish(p); 1356 fail_eqcr: 1357 return -EIO; 1358 } 1359 1360 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c, 1361 const struct qman_cgrs *cgrs) 1362 { 1363 struct qman_portal *portal; 1364 int err; 1365 1366 portal = &per_cpu(qman_affine_portal, c->cpu); 1367 err = qman_create_portal(portal, c, cgrs); 1368 if (err) 1369 return NULL; 1370 1371 spin_lock(&affine_mask_lock); 1372 cpumask_set_cpu(c->cpu, &affine_mask); 1373 affine_channels[c->cpu] = c->channel; 1374 affine_portals[c->cpu] = portal; 1375 spin_unlock(&affine_mask_lock); 1376 1377 return portal; 1378 } 1379 1380 static void qman_destroy_portal(struct qman_portal *qm) 1381 { 1382 const struct qm_portal_config *pcfg; 1383 1384 /* Stop dequeues on the portal */ 1385 qm_dqrr_sdqcr_set(&qm->p, 0); 1386 1387 /* 1388 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or 1389 * something related to QM_PIRQ_EQCI, this may need fixing. 1390 * Also, due to the prefetching model used for CI updates in the enqueue 1391 * path, this update will only invalidate the CI cacheline *after* 1392 * working on it, so we need to call this twice to ensure a full update 1393 * irrespective of where the enqueue processing was at when the teardown 1394 * began. 1395 */ 1396 qm_eqcr_cce_update(&qm->p); 1397 qm_eqcr_cce_update(&qm->p); 1398 pcfg = qm->config; 1399 1400 free_irq(pcfg->irq, qm); 1401 1402 kfree(qm->cgrs); 1403 qm_mc_finish(&qm->p); 1404 qm_mr_finish(&qm->p); 1405 qm_dqrr_finish(&qm->p); 1406 qm_eqcr_finish(&qm->p); 1407 1408 qm->config = NULL; 1409 } 1410 1411 const struct qm_portal_config *qman_destroy_affine_portal(void) 1412 { 1413 struct qman_portal *qm = get_affine_portal(); 1414 const struct qm_portal_config *pcfg; 1415 int cpu; 1416 1417 pcfg = qm->config; 1418 cpu = pcfg->cpu; 1419 1420 qman_destroy_portal(qm); 1421 1422 spin_lock(&affine_mask_lock); 1423 cpumask_clear_cpu(cpu, &affine_mask); 1424 spin_unlock(&affine_mask_lock); 1425 put_affine_portal(); 1426 return pcfg; 1427 } 1428 1429 /* Inline helper to reduce nesting in __poll_portal_slow() */ 1430 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq, 1431 const union qm_mr_entry *msg, u8 verb) 1432 { 1433 switch (verb) { 1434 case QM_MR_VERB_FQRL: 1435 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL)); 1436 fq_clear(fq, QMAN_FQ_STATE_ORL); 1437 break; 1438 case QM_MR_VERB_FQRN: 1439 DPAA_ASSERT(fq->state == qman_fq_state_parked || 1440 fq->state == qman_fq_state_sched); 1441 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING)); 1442 fq_clear(fq, QMAN_FQ_STATE_CHANGING); 1443 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY) 1444 fq_set(fq, QMAN_FQ_STATE_NE); 1445 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT) 1446 fq_set(fq, QMAN_FQ_STATE_ORL); 1447 fq->state = qman_fq_state_retired; 1448 break; 1449 case QM_MR_VERB_FQPN: 1450 DPAA_ASSERT(fq->state == qman_fq_state_sched); 1451 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING)); 1452 fq->state = qman_fq_state_parked; 1453 } 1454 } 1455 1456 static void qm_congestion_task(struct work_struct *work) 1457 { 1458 struct qman_portal *p = container_of(work, struct qman_portal, 1459 congestion_work); 1460 struct qman_cgrs rr, c; 1461 union qm_mc_result *mcr; 1462 struct qman_cgr *cgr; 1463 1464 spin_lock(&p->cgr_lock); 1465 qm_mc_start(&p->p); 1466 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION); 1467 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1468 spin_unlock(&p->cgr_lock); 1469 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n"); 1470 qman_p_irqsource_add(p, QM_PIRQ_CSCI); 1471 return; 1472 } 1473 /* mask out the ones I'm not interested in */ 1474 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state, 1475 &p->cgrs[0]); 1476 /* check previous snapshot for delta, enter/exit congestion */ 1477 qman_cgrs_xor(&c, &rr, &p->cgrs[1]); 1478 /* update snapshot */ 1479 qman_cgrs_cp(&p->cgrs[1], &rr); 1480 /* Invoke callback */ 1481 list_for_each_entry(cgr, &p->cgr_cbs, node) 1482 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid)) 1483 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid)); 1484 spin_unlock(&p->cgr_lock); 1485 qman_p_irqsource_add(p, QM_PIRQ_CSCI); 1486 } 1487 1488 static void qm_mr_process_task(struct work_struct *work) 1489 { 1490 struct qman_portal *p = container_of(work, struct qman_portal, 1491 mr_work); 1492 const union qm_mr_entry *msg; 1493 struct qman_fq *fq; 1494 u8 verb, num = 0; 1495 1496 preempt_disable(); 1497 1498 while (1) { 1499 qm_mr_pvb_update(&p->p); 1500 msg = qm_mr_current(&p->p); 1501 if (!msg) 1502 break; 1503 1504 verb = msg->verb & QM_MR_VERB_TYPE_MASK; 1505 /* The message is a software ERN iff the 0x20 bit is clear */ 1506 if (verb & 0x20) { 1507 switch (verb) { 1508 case QM_MR_VERB_FQRNI: 1509 /* nada, we drop FQRNIs on the floor */ 1510 break; 1511 case QM_MR_VERB_FQRN: 1512 case QM_MR_VERB_FQRL: 1513 /* Lookup in the retirement table */ 1514 fq = fqid_to_fq(qm_fqid_get(&msg->fq)); 1515 if (WARN_ON(!fq)) 1516 break; 1517 fq_state_change(p, fq, msg, verb); 1518 if (fq->cb.fqs) 1519 fq->cb.fqs(p, fq, msg); 1520 break; 1521 case QM_MR_VERB_FQPN: 1522 /* Parked */ 1523 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b)); 1524 fq_state_change(p, fq, msg, verb); 1525 if (fq->cb.fqs) 1526 fq->cb.fqs(p, fq, msg); 1527 break; 1528 case QM_MR_VERB_DC_ERN: 1529 /* DCP ERN */ 1530 pr_crit_once("Leaking DCP ERNs!\n"); 1531 break; 1532 default: 1533 pr_crit("Invalid MR verb 0x%02x\n", verb); 1534 } 1535 } else { 1536 /* Its a software ERN */ 1537 fq = tag_to_fq(be32_to_cpu(msg->ern.tag)); 1538 fq->cb.ern(p, fq, msg); 1539 } 1540 num++; 1541 qm_mr_next(&p->p); 1542 } 1543 1544 qm_mr_cci_consume(&p->p, num); 1545 qman_p_irqsource_add(p, QM_PIRQ_MRI); 1546 preempt_enable(); 1547 } 1548 1549 static u32 __poll_portal_slow(struct qman_portal *p, u32 is) 1550 { 1551 if (is & QM_PIRQ_CSCI) { 1552 qman_p_irqsource_remove(p, QM_PIRQ_CSCI); 1553 queue_work_on(smp_processor_id(), qm_portal_wq, 1554 &p->congestion_work); 1555 } 1556 1557 if (is & QM_PIRQ_EQRI) { 1558 qm_eqcr_cce_update(&p->p); 1559 qm_eqcr_set_ithresh(&p->p, 0); 1560 wake_up(&affine_queue); 1561 } 1562 1563 if (is & QM_PIRQ_MRI) { 1564 qman_p_irqsource_remove(p, QM_PIRQ_MRI); 1565 queue_work_on(smp_processor_id(), qm_portal_wq, 1566 &p->mr_work); 1567 } 1568 1569 return is; 1570 } 1571 1572 /* 1573 * remove some slowish-path stuff from the "fast path" and make sure it isn't 1574 * inlined. 1575 */ 1576 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq) 1577 { 1578 p->vdqcr_owned = NULL; 1579 fq_clear(fq, QMAN_FQ_STATE_VDQCR); 1580 wake_up(&affine_queue); 1581 } 1582 1583 /* 1584 * The only states that would conflict with other things if they ran at the 1585 * same time on the same cpu are: 1586 * 1587 * (i) setting/clearing vdqcr_owned, and 1588 * (ii) clearing the NE (Not Empty) flag. 1589 * 1590 * Both are safe. Because; 1591 * 1592 * (i) this clearing can only occur after qman_volatile_dequeue() has set the 1593 * vdqcr_owned field (which it does before setting VDQCR), and 1594 * qman_volatile_dequeue() blocks interrupts and preemption while this is 1595 * done so that we can't interfere. 1596 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as 1597 * with (i) that API prevents us from interfering until it's safe. 1598 * 1599 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far 1600 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett 1601 * advantage comes from this function not having to "lock" anything at all. 1602 * 1603 * Note also that the callbacks are invoked at points which are safe against the 1604 * above potential conflicts, but that this function itself is not re-entrant 1605 * (this is because the function tracks one end of each FIFO in the portal and 1606 * we do *not* want to lock that). So the consequence is that it is safe for 1607 * user callbacks to call into any QMan API. 1608 */ 1609 static inline unsigned int __poll_portal_fast(struct qman_portal *p, 1610 unsigned int poll_limit) 1611 { 1612 const struct qm_dqrr_entry *dq; 1613 struct qman_fq *fq; 1614 enum qman_cb_dqrr_result res; 1615 unsigned int limit = 0; 1616 1617 do { 1618 qm_dqrr_pvb_update(&p->p); 1619 dq = qm_dqrr_current(&p->p); 1620 if (!dq) 1621 break; 1622 1623 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) { 1624 /* 1625 * VDQCR: don't trust context_b as the FQ may have 1626 * been configured for h/w consumption and we're 1627 * draining it post-retirement. 1628 */ 1629 fq = p->vdqcr_owned; 1630 /* 1631 * We only set QMAN_FQ_STATE_NE when retiring, so we 1632 * only need to check for clearing it when doing 1633 * volatile dequeues. It's one less thing to check 1634 * in the critical path (SDQCR). 1635 */ 1636 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY) 1637 fq_clear(fq, QMAN_FQ_STATE_NE); 1638 /* 1639 * This is duplicated from the SDQCR code, but we 1640 * have stuff to do before *and* after this callback, 1641 * and we don't want multiple if()s in the critical 1642 * path (SDQCR). 1643 */ 1644 res = fq->cb.dqrr(p, fq, dq); 1645 if (res == qman_cb_dqrr_stop) 1646 break; 1647 /* Check for VDQCR completion */ 1648 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED) 1649 clear_vdqcr(p, fq); 1650 } else { 1651 /* SDQCR: context_b points to the FQ */ 1652 fq = tag_to_fq(be32_to_cpu(dq->context_b)); 1653 /* Now let the callback do its stuff */ 1654 res = fq->cb.dqrr(p, fq, dq); 1655 /* 1656 * The callback can request that we exit without 1657 * consuming this entry nor advancing; 1658 */ 1659 if (res == qman_cb_dqrr_stop) 1660 break; 1661 } 1662 /* Interpret 'dq' from a driver perspective. */ 1663 /* 1664 * Parking isn't possible unless HELDACTIVE was set. NB, 1665 * FORCEELIGIBLE implies HELDACTIVE, so we only need to 1666 * check for HELDACTIVE to cover both. 1667 */ 1668 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) || 1669 (res != qman_cb_dqrr_park)); 1670 /* just means "skip it, I'll consume it myself later on" */ 1671 if (res != qman_cb_dqrr_defer) 1672 qm_dqrr_cdc_consume_1ptr(&p->p, dq, 1673 res == qman_cb_dqrr_park); 1674 /* Move forward */ 1675 qm_dqrr_next(&p->p); 1676 /* 1677 * Entry processed and consumed, increment our counter. The 1678 * callback can request that we exit after consuming the 1679 * entry, and we also exit if we reach our processing limit, 1680 * so loop back only if neither of these conditions is met. 1681 */ 1682 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop); 1683 1684 return limit; 1685 } 1686 1687 void qman_p_irqsource_add(struct qman_portal *p, u32 bits) 1688 { 1689 unsigned long irqflags; 1690 1691 local_irq_save(irqflags); 1692 p->irq_sources |= bits & QM_PIRQ_VISIBLE; 1693 qm_out(&p->p, QM_REG_IER, p->irq_sources); 1694 local_irq_restore(irqflags); 1695 } 1696 EXPORT_SYMBOL(qman_p_irqsource_add); 1697 1698 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits) 1699 { 1700 unsigned long irqflags; 1701 u32 ier; 1702 1703 /* 1704 * Our interrupt handler only processes+clears status register bits that 1705 * are in p->irq_sources. As we're trimming that mask, if one of them 1706 * were to assert in the status register just before we remove it from 1707 * the enable register, there would be an interrupt-storm when we 1708 * release the IRQ lock. So we wait for the enable register update to 1709 * take effect in h/w (by reading it back) and then clear all other bits 1710 * in the status register. Ie. we clear them from ISR once it's certain 1711 * IER won't allow them to reassert. 1712 */ 1713 local_irq_save(irqflags); 1714 bits &= QM_PIRQ_VISIBLE; 1715 p->irq_sources &= ~bits; 1716 qm_out(&p->p, QM_REG_IER, p->irq_sources); 1717 ier = qm_in(&p->p, QM_REG_IER); 1718 /* 1719 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a 1720 * data-dependency, ie. to protect against re-ordering. 1721 */ 1722 qm_out(&p->p, QM_REG_ISR, ~ier); 1723 local_irq_restore(irqflags); 1724 } 1725 EXPORT_SYMBOL(qman_p_irqsource_remove); 1726 1727 const cpumask_t *qman_affine_cpus(void) 1728 { 1729 return &affine_mask; 1730 } 1731 EXPORT_SYMBOL(qman_affine_cpus); 1732 1733 u16 qman_affine_channel(int cpu) 1734 { 1735 if (cpu < 0) { 1736 struct qman_portal *portal = get_affine_portal(); 1737 1738 cpu = portal->config->cpu; 1739 put_affine_portal(); 1740 } 1741 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask)); 1742 return affine_channels[cpu]; 1743 } 1744 EXPORT_SYMBOL(qman_affine_channel); 1745 1746 struct qman_portal *qman_get_affine_portal(int cpu) 1747 { 1748 return affine_portals[cpu]; 1749 } 1750 EXPORT_SYMBOL(qman_get_affine_portal); 1751 1752 int qman_start_using_portal(struct qman_portal *p, struct device *dev) 1753 { 1754 return (!device_link_add(dev, p->config->dev, 1755 DL_FLAG_AUTOREMOVE_CONSUMER)) ? -EINVAL : 0; 1756 } 1757 EXPORT_SYMBOL(qman_start_using_portal); 1758 1759 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit) 1760 { 1761 return __poll_portal_fast(p, limit); 1762 } 1763 EXPORT_SYMBOL(qman_p_poll_dqrr); 1764 1765 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools) 1766 { 1767 unsigned long irqflags; 1768 1769 local_irq_save(irqflags); 1770 pools &= p->config->pools; 1771 p->sdqcr |= pools; 1772 qm_dqrr_sdqcr_set(&p->p, p->sdqcr); 1773 local_irq_restore(irqflags); 1774 } 1775 EXPORT_SYMBOL(qman_p_static_dequeue_add); 1776 1777 /* Frame queue API */ 1778 1779 static const char *mcr_result_str(u8 result) 1780 { 1781 switch (result) { 1782 case QM_MCR_RESULT_NULL: 1783 return "QM_MCR_RESULT_NULL"; 1784 case QM_MCR_RESULT_OK: 1785 return "QM_MCR_RESULT_OK"; 1786 case QM_MCR_RESULT_ERR_FQID: 1787 return "QM_MCR_RESULT_ERR_FQID"; 1788 case QM_MCR_RESULT_ERR_FQSTATE: 1789 return "QM_MCR_RESULT_ERR_FQSTATE"; 1790 case QM_MCR_RESULT_ERR_NOTEMPTY: 1791 return "QM_MCR_RESULT_ERR_NOTEMPTY"; 1792 case QM_MCR_RESULT_PENDING: 1793 return "QM_MCR_RESULT_PENDING"; 1794 case QM_MCR_RESULT_ERR_BADCOMMAND: 1795 return "QM_MCR_RESULT_ERR_BADCOMMAND"; 1796 } 1797 return "<unknown MCR result>"; 1798 } 1799 1800 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq) 1801 { 1802 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) { 1803 int ret = qman_alloc_fqid(&fqid); 1804 1805 if (ret) 1806 return ret; 1807 } 1808 fq->fqid = fqid; 1809 fq->flags = flags; 1810 fq->state = qman_fq_state_oos; 1811 fq->cgr_groupid = 0; 1812 1813 /* A context_b of 0 is allegedly special, so don't use that fqid */ 1814 if (fqid == 0 || fqid >= num_fqids) { 1815 WARN(1, "bad fqid %d\n", fqid); 1816 return -EINVAL; 1817 } 1818 1819 fq->idx = fqid * 2; 1820 if (flags & QMAN_FQ_FLAG_NO_MODIFY) 1821 fq->idx++; 1822 1823 WARN_ON(fq_table[fq->idx]); 1824 fq_table[fq->idx] = fq; 1825 1826 return 0; 1827 } 1828 EXPORT_SYMBOL(qman_create_fq); 1829 1830 void qman_destroy_fq(struct qman_fq *fq) 1831 { 1832 /* 1833 * We don't need to lock the FQ as it is a pre-condition that the FQ be 1834 * quiesced. Instead, run some checks. 1835 */ 1836 switch (fq->state) { 1837 case qman_fq_state_parked: 1838 case qman_fq_state_oos: 1839 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID)) 1840 qman_release_fqid(fq->fqid); 1841 1842 DPAA_ASSERT(fq_table[fq->idx]); 1843 fq_table[fq->idx] = NULL; 1844 return; 1845 default: 1846 break; 1847 } 1848 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!"); 1849 } 1850 EXPORT_SYMBOL(qman_destroy_fq); 1851 1852 u32 qman_fq_fqid(struct qman_fq *fq) 1853 { 1854 return fq->fqid; 1855 } 1856 EXPORT_SYMBOL(qman_fq_fqid); 1857 1858 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts) 1859 { 1860 union qm_mc_command *mcc; 1861 union qm_mc_result *mcr; 1862 struct qman_portal *p; 1863 u8 res, myverb; 1864 int ret = 0; 1865 1866 myverb = (flags & QMAN_INITFQ_FLAG_SCHED) 1867 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED; 1868 1869 if (fq->state != qman_fq_state_oos && 1870 fq->state != qman_fq_state_parked) 1871 return -EINVAL; 1872 #ifdef CONFIG_FSL_DPAA_CHECKING 1873 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1874 return -EINVAL; 1875 #endif 1876 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) { 1877 /* And can't be set at the same time as TDTHRESH */ 1878 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH) 1879 return -EINVAL; 1880 } 1881 /* Issue an INITFQ_[PARKED|SCHED] management command */ 1882 p = get_affine_portal(); 1883 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 1884 (fq->state != qman_fq_state_oos && 1885 fq->state != qman_fq_state_parked)) { 1886 ret = -EBUSY; 1887 goto out; 1888 } 1889 mcc = qm_mc_start(&p->p); 1890 if (opts) 1891 mcc->initfq = *opts; 1892 qm_fqid_set(&mcc->fq, fq->fqid); 1893 mcc->initfq.count = 0; 1894 /* 1895 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a 1896 * demux pointer. Otherwise, the caller-provided value is allowed to 1897 * stand, don't overwrite it. 1898 */ 1899 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) { 1900 dma_addr_t phys_fq; 1901 1902 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB); 1903 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq)); 1904 /* 1905 * and the physical address - NB, if the user wasn't trying to 1906 * set CONTEXTA, clear the stashing settings. 1907 */ 1908 if (!(be16_to_cpu(mcc->initfq.we_mask) & 1909 QM_INITFQ_WE_CONTEXTA)) { 1910 mcc->initfq.we_mask |= 1911 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1912 memset(&mcc->initfq.fqd.context_a, 0, 1913 sizeof(mcc->initfq.fqd.context_a)); 1914 } else { 1915 struct qman_portal *p = qman_dma_portal; 1916 1917 phys_fq = dma_map_single(p->config->dev, fq, 1918 sizeof(*fq), DMA_TO_DEVICE); 1919 if (dma_mapping_error(p->config->dev, phys_fq)) { 1920 dev_err(p->config->dev, "dma_mapping failed\n"); 1921 ret = -EIO; 1922 goto out; 1923 } 1924 1925 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq); 1926 } 1927 } 1928 if (flags & QMAN_INITFQ_FLAG_LOCAL) { 1929 int wq = 0; 1930 1931 if (!(be16_to_cpu(mcc->initfq.we_mask) & 1932 QM_INITFQ_WE_DESTWQ)) { 1933 mcc->initfq.we_mask |= 1934 cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1935 wq = 4; 1936 } 1937 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq); 1938 } 1939 qm_mc_commit(&p->p, myverb); 1940 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1941 dev_err(p->config->dev, "MCR timeout\n"); 1942 ret = -ETIMEDOUT; 1943 goto out; 1944 } 1945 1946 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb); 1947 res = mcr->result; 1948 if (res != QM_MCR_RESULT_OK) { 1949 ret = -EIO; 1950 goto out; 1951 } 1952 if (opts) { 1953 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) { 1954 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE) 1955 fq_set(fq, QMAN_FQ_STATE_CGR_EN); 1956 else 1957 fq_clear(fq, QMAN_FQ_STATE_CGR_EN); 1958 } 1959 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID) 1960 fq->cgr_groupid = opts->fqd.cgid; 1961 } 1962 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ? 1963 qman_fq_state_sched : qman_fq_state_parked; 1964 1965 out: 1966 put_affine_portal(); 1967 return ret; 1968 } 1969 EXPORT_SYMBOL(qman_init_fq); 1970 1971 int qman_schedule_fq(struct qman_fq *fq) 1972 { 1973 union qm_mc_command *mcc; 1974 union qm_mc_result *mcr; 1975 struct qman_portal *p; 1976 int ret = 0; 1977 1978 if (fq->state != qman_fq_state_parked) 1979 return -EINVAL; 1980 #ifdef CONFIG_FSL_DPAA_CHECKING 1981 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1982 return -EINVAL; 1983 #endif 1984 /* Issue a ALTERFQ_SCHED management command */ 1985 p = get_affine_portal(); 1986 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 1987 fq->state != qman_fq_state_parked) { 1988 ret = -EBUSY; 1989 goto out; 1990 } 1991 mcc = qm_mc_start(&p->p); 1992 qm_fqid_set(&mcc->fq, fq->fqid); 1993 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED); 1994 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1995 dev_err(p->config->dev, "ALTER_SCHED timeout\n"); 1996 ret = -ETIMEDOUT; 1997 goto out; 1998 } 1999 2000 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED); 2001 if (mcr->result != QM_MCR_RESULT_OK) { 2002 ret = -EIO; 2003 goto out; 2004 } 2005 fq->state = qman_fq_state_sched; 2006 out: 2007 put_affine_portal(); 2008 return ret; 2009 } 2010 EXPORT_SYMBOL(qman_schedule_fq); 2011 2012 int qman_retire_fq(struct qman_fq *fq, u32 *flags) 2013 { 2014 union qm_mc_command *mcc; 2015 union qm_mc_result *mcr; 2016 struct qman_portal *p; 2017 int ret; 2018 u8 res; 2019 2020 if (fq->state != qman_fq_state_parked && 2021 fq->state != qman_fq_state_sched) 2022 return -EINVAL; 2023 #ifdef CONFIG_FSL_DPAA_CHECKING 2024 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 2025 return -EINVAL; 2026 #endif 2027 p = get_affine_portal(); 2028 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 2029 fq->state == qman_fq_state_retired || 2030 fq->state == qman_fq_state_oos) { 2031 ret = -EBUSY; 2032 goto out; 2033 } 2034 mcc = qm_mc_start(&p->p); 2035 qm_fqid_set(&mcc->fq, fq->fqid); 2036 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE); 2037 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2038 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n"); 2039 ret = -ETIMEDOUT; 2040 goto out; 2041 } 2042 2043 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE); 2044 res = mcr->result; 2045 /* 2046 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING, 2047 * and defer the flags until FQRNI or FQRN (respectively) show up. But 2048 * "Friendly" is to process OK immediately, and not set CHANGING. We do 2049 * friendly, otherwise the caller doesn't necessarily have a fully 2050 * "retired" FQ on return even if the retirement was immediate. However 2051 * this does mean some code duplication between here and 2052 * fq_state_change(). 2053 */ 2054 if (res == QM_MCR_RESULT_OK) { 2055 ret = 0; 2056 /* Process 'fq' right away, we'll ignore FQRNI */ 2057 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) 2058 fq_set(fq, QMAN_FQ_STATE_NE); 2059 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT) 2060 fq_set(fq, QMAN_FQ_STATE_ORL); 2061 if (flags) 2062 *flags = fq->flags; 2063 fq->state = qman_fq_state_retired; 2064 if (fq->cb.fqs) { 2065 /* 2066 * Another issue with supporting "immediate" retirement 2067 * is that we're forced to drop FQRNIs, because by the 2068 * time they're seen it may already be "too late" (the 2069 * fq may have been OOS'd and free()'d already). But if 2070 * the upper layer wants a callback whether it's 2071 * immediate or not, we have to fake a "MR" entry to 2072 * look like an FQRNI... 2073 */ 2074 union qm_mr_entry msg; 2075 2076 msg.verb = QM_MR_VERB_FQRNI; 2077 msg.fq.fqs = mcr->alterfq.fqs; 2078 qm_fqid_set(&msg.fq, fq->fqid); 2079 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq)); 2080 fq->cb.fqs(p, fq, &msg); 2081 } 2082 } else if (res == QM_MCR_RESULT_PENDING) { 2083 ret = 1; 2084 fq_set(fq, QMAN_FQ_STATE_CHANGING); 2085 } else { 2086 ret = -EIO; 2087 } 2088 out: 2089 put_affine_portal(); 2090 return ret; 2091 } 2092 EXPORT_SYMBOL(qman_retire_fq); 2093 2094 int qman_oos_fq(struct qman_fq *fq) 2095 { 2096 union qm_mc_command *mcc; 2097 union qm_mc_result *mcr; 2098 struct qman_portal *p; 2099 int ret = 0; 2100 2101 if (fq->state != qman_fq_state_retired) 2102 return -EINVAL; 2103 #ifdef CONFIG_FSL_DPAA_CHECKING 2104 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 2105 return -EINVAL; 2106 #endif 2107 p = get_affine_portal(); 2108 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) || 2109 fq->state != qman_fq_state_retired) { 2110 ret = -EBUSY; 2111 goto out; 2112 } 2113 mcc = qm_mc_start(&p->p); 2114 qm_fqid_set(&mcc->fq, fq->fqid); 2115 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 2116 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2117 ret = -ETIMEDOUT; 2118 goto out; 2119 } 2120 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS); 2121 if (mcr->result != QM_MCR_RESULT_OK) { 2122 ret = -EIO; 2123 goto out; 2124 } 2125 fq->state = qman_fq_state_oos; 2126 out: 2127 put_affine_portal(); 2128 return ret; 2129 } 2130 EXPORT_SYMBOL(qman_oos_fq); 2131 2132 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd) 2133 { 2134 union qm_mc_command *mcc; 2135 union qm_mc_result *mcr; 2136 struct qman_portal *p = get_affine_portal(); 2137 int ret = 0; 2138 2139 mcc = qm_mc_start(&p->p); 2140 qm_fqid_set(&mcc->fq, fq->fqid); 2141 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); 2142 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2143 ret = -ETIMEDOUT; 2144 goto out; 2145 } 2146 2147 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); 2148 if (mcr->result == QM_MCR_RESULT_OK) 2149 *fqd = mcr->queryfq.fqd; 2150 else 2151 ret = -EIO; 2152 out: 2153 put_affine_portal(); 2154 return ret; 2155 } 2156 2157 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np) 2158 { 2159 union qm_mc_command *mcc; 2160 union qm_mc_result *mcr; 2161 struct qman_portal *p = get_affine_portal(); 2162 int ret = 0; 2163 2164 mcc = qm_mc_start(&p->p); 2165 qm_fqid_set(&mcc->fq, fq->fqid); 2166 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); 2167 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2168 ret = -ETIMEDOUT; 2169 goto out; 2170 } 2171 2172 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); 2173 if (mcr->result == QM_MCR_RESULT_OK) 2174 *np = mcr->queryfq_np; 2175 else if (mcr->result == QM_MCR_RESULT_ERR_FQID) 2176 ret = -ERANGE; 2177 else 2178 ret = -EIO; 2179 out: 2180 put_affine_portal(); 2181 return ret; 2182 } 2183 EXPORT_SYMBOL(qman_query_fq_np); 2184 2185 static int qman_query_cgr(struct qman_cgr *cgr, 2186 struct qm_mcr_querycgr *cgrd) 2187 { 2188 union qm_mc_command *mcc; 2189 union qm_mc_result *mcr; 2190 struct qman_portal *p = get_affine_portal(); 2191 int ret = 0; 2192 2193 mcc = qm_mc_start(&p->p); 2194 mcc->cgr.cgid = cgr->cgrid; 2195 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR); 2196 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2197 ret = -ETIMEDOUT; 2198 goto out; 2199 } 2200 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR); 2201 if (mcr->result == QM_MCR_RESULT_OK) 2202 *cgrd = mcr->querycgr; 2203 else { 2204 dev_err(p->config->dev, "QUERY_CGR failed: %s\n", 2205 mcr_result_str(mcr->result)); 2206 ret = -EIO; 2207 } 2208 out: 2209 put_affine_portal(); 2210 return ret; 2211 } 2212 2213 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result) 2214 { 2215 struct qm_mcr_querycgr query_cgr; 2216 int err; 2217 2218 err = qman_query_cgr(cgr, &query_cgr); 2219 if (err) 2220 return err; 2221 2222 *result = !!query_cgr.cgr.cs; 2223 return 0; 2224 } 2225 EXPORT_SYMBOL(qman_query_cgr_congested); 2226 2227 /* internal function used as a wait_event() expression */ 2228 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr) 2229 { 2230 unsigned long irqflags; 2231 int ret = -EBUSY; 2232 2233 local_irq_save(irqflags); 2234 if (p->vdqcr_owned) 2235 goto out; 2236 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) 2237 goto out; 2238 2239 fq_set(fq, QMAN_FQ_STATE_VDQCR); 2240 p->vdqcr_owned = fq; 2241 qm_dqrr_vdqcr_set(&p->p, vdqcr); 2242 ret = 0; 2243 out: 2244 local_irq_restore(irqflags); 2245 return ret; 2246 } 2247 2248 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr) 2249 { 2250 int ret; 2251 2252 *p = get_affine_portal(); 2253 ret = set_p_vdqcr(*p, fq, vdqcr); 2254 put_affine_portal(); 2255 return ret; 2256 } 2257 2258 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq, 2259 u32 vdqcr, u32 flags) 2260 { 2261 int ret = 0; 2262 2263 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) 2264 ret = wait_event_interruptible(affine_queue, 2265 !set_vdqcr(p, fq, vdqcr)); 2266 else 2267 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr)); 2268 return ret; 2269 } 2270 2271 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr) 2272 { 2273 struct qman_portal *p; 2274 int ret; 2275 2276 if (fq->state != qman_fq_state_parked && 2277 fq->state != qman_fq_state_retired) 2278 return -EINVAL; 2279 if (vdqcr & QM_VDQCR_FQID_MASK) 2280 return -EINVAL; 2281 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) 2282 return -EBUSY; 2283 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid; 2284 if (flags & QMAN_VOLATILE_FLAG_WAIT) 2285 ret = wait_vdqcr_start(&p, fq, vdqcr, flags); 2286 else 2287 ret = set_vdqcr(&p, fq, vdqcr); 2288 if (ret) 2289 return ret; 2290 /* VDQCR is set */ 2291 if (flags & QMAN_VOLATILE_FLAG_FINISH) { 2292 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) 2293 /* 2294 * NB: don't propagate any error - the caller wouldn't 2295 * know whether the VDQCR was issued or not. A signal 2296 * could arrive after returning anyway, so the caller 2297 * can check signal_pending() if that's an issue. 2298 */ 2299 wait_event_interruptible(affine_queue, 2300 !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); 2301 else 2302 wait_event(affine_queue, 2303 !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); 2304 } 2305 return 0; 2306 } 2307 EXPORT_SYMBOL(qman_volatile_dequeue); 2308 2309 static void update_eqcr_ci(struct qman_portal *p, u8 avail) 2310 { 2311 if (avail) 2312 qm_eqcr_cce_prefetch(&p->p); 2313 else 2314 qm_eqcr_cce_update(&p->p); 2315 } 2316 2317 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd) 2318 { 2319 struct qman_portal *p; 2320 struct qm_eqcr_entry *eq; 2321 unsigned long irqflags; 2322 u8 avail; 2323 2324 p = get_affine_portal(); 2325 local_irq_save(irqflags); 2326 2327 if (p->use_eqcr_ci_stashing) { 2328 /* 2329 * The stashing case is easy, only update if we need to in 2330 * order to try and liberate ring entries. 2331 */ 2332 eq = qm_eqcr_start_stash(&p->p); 2333 } else { 2334 /* 2335 * The non-stashing case is harder, need to prefetch ahead of 2336 * time. 2337 */ 2338 avail = qm_eqcr_get_avail(&p->p); 2339 if (avail < 2) 2340 update_eqcr_ci(p, avail); 2341 eq = qm_eqcr_start_no_stash(&p->p); 2342 } 2343 2344 if (unlikely(!eq)) 2345 goto out; 2346 2347 qm_fqid_set(eq, fq->fqid); 2348 eq->tag = cpu_to_be32(fq_to_tag(fq)); 2349 eq->fd = *fd; 2350 2351 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE); 2352 out: 2353 local_irq_restore(irqflags); 2354 put_affine_portal(); 2355 return 0; 2356 } 2357 EXPORT_SYMBOL(qman_enqueue); 2358 2359 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags, 2360 struct qm_mcc_initcgr *opts) 2361 { 2362 union qm_mc_command *mcc; 2363 union qm_mc_result *mcr; 2364 struct qman_portal *p = get_affine_portal(); 2365 u8 verb = QM_MCC_VERB_MODIFYCGR; 2366 int ret = 0; 2367 2368 mcc = qm_mc_start(&p->p); 2369 if (opts) 2370 mcc->initcgr = *opts; 2371 mcc->initcgr.cgid = cgr->cgrid; 2372 if (flags & QMAN_CGR_FLAG_USE_INIT) 2373 verb = QM_MCC_VERB_INITCGR; 2374 qm_mc_commit(&p->p, verb); 2375 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2376 ret = -ETIMEDOUT; 2377 goto out; 2378 } 2379 2380 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb); 2381 if (mcr->result != QM_MCR_RESULT_OK) 2382 ret = -EIO; 2383 2384 out: 2385 put_affine_portal(); 2386 return ret; 2387 } 2388 2389 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0) 2390 2391 /* congestion state change notification target update control */ 2392 static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val) 2393 { 2394 if (qman_ip_rev >= QMAN_REV30) 2395 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi | 2396 QM_CGR_TARG_UDP_CTRL_WRITE_BIT); 2397 else 2398 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi)); 2399 } 2400 2401 static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val) 2402 { 2403 if (qman_ip_rev >= QMAN_REV30) 2404 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi); 2405 else 2406 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi)); 2407 } 2408 2409 static u8 qman_cgr_cpus[CGR_NUM]; 2410 2411 void qman_init_cgr_all(void) 2412 { 2413 struct qman_cgr cgr; 2414 int err_cnt = 0; 2415 2416 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) { 2417 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL)) 2418 err_cnt++; 2419 } 2420 2421 if (err_cnt) 2422 pr_err("Warning: %d error%s while initialising CGR h/w\n", 2423 err_cnt, (err_cnt > 1) ? "s" : ""); 2424 } 2425 2426 int qman_create_cgr(struct qman_cgr *cgr, u32 flags, 2427 struct qm_mcc_initcgr *opts) 2428 { 2429 struct qm_mcr_querycgr cgr_state; 2430 int ret; 2431 struct qman_portal *p; 2432 2433 /* 2434 * We have to check that the provided CGRID is within the limits of the 2435 * data-structures, for obvious reasons. However we'll let h/w take 2436 * care of determining whether it's within the limits of what exists on 2437 * the SoC. 2438 */ 2439 if (cgr->cgrid >= CGR_NUM) 2440 return -EINVAL; 2441 2442 preempt_disable(); 2443 p = get_affine_portal(); 2444 qman_cgr_cpus[cgr->cgrid] = smp_processor_id(); 2445 preempt_enable(); 2446 2447 cgr->chan = p->config->channel; 2448 spin_lock(&p->cgr_lock); 2449 2450 if (opts) { 2451 struct qm_mcc_initcgr local_opts = *opts; 2452 2453 ret = qman_query_cgr(cgr, &cgr_state); 2454 if (ret) 2455 goto out; 2456 2457 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p), 2458 be32_to_cpu(cgr_state.cgr.cscn_targ)); 2459 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG); 2460 2461 /* send init if flags indicate so */ 2462 if (flags & QMAN_CGR_FLAG_USE_INIT) 2463 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, 2464 &local_opts); 2465 else 2466 ret = qm_modify_cgr(cgr, 0, &local_opts); 2467 if (ret) 2468 goto out; 2469 } 2470 2471 list_add(&cgr->node, &p->cgr_cbs); 2472 2473 /* Determine if newly added object requires its callback to be called */ 2474 ret = qman_query_cgr(cgr, &cgr_state); 2475 if (ret) { 2476 /* we can't go back, so proceed and return success */ 2477 dev_err(p->config->dev, "CGR HW state partially modified\n"); 2478 ret = 0; 2479 goto out; 2480 } 2481 if (cgr->cb && cgr_state.cgr.cscn_en && 2482 qman_cgrs_get(&p->cgrs[1], cgr->cgrid)) 2483 cgr->cb(p, cgr, 1); 2484 out: 2485 spin_unlock(&p->cgr_lock); 2486 put_affine_portal(); 2487 return ret; 2488 } 2489 EXPORT_SYMBOL(qman_create_cgr); 2490 2491 int qman_delete_cgr(struct qman_cgr *cgr) 2492 { 2493 unsigned long irqflags; 2494 struct qm_mcr_querycgr cgr_state; 2495 struct qm_mcc_initcgr local_opts; 2496 int ret = 0; 2497 struct qman_cgr *i; 2498 struct qman_portal *p = get_affine_portal(); 2499 2500 if (cgr->chan != p->config->channel) { 2501 /* attempt to delete from other portal than creator */ 2502 dev_err(p->config->dev, "CGR not owned by current portal"); 2503 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n", 2504 cgr->chan, p->config->channel); 2505 2506 ret = -EINVAL; 2507 goto put_portal; 2508 } 2509 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr)); 2510 spin_lock_irqsave(&p->cgr_lock, irqflags); 2511 list_del(&cgr->node); 2512 /* 2513 * If there are no other CGR objects for this CGRID in the list, 2514 * update CSCN_TARG accordingly 2515 */ 2516 list_for_each_entry(i, &p->cgr_cbs, node) 2517 if (i->cgrid == cgr->cgrid && i->cb) 2518 goto release_lock; 2519 ret = qman_query_cgr(cgr, &cgr_state); 2520 if (ret) { 2521 /* add back to the list */ 2522 list_add(&cgr->node, &p->cgr_cbs); 2523 goto release_lock; 2524 } 2525 2526 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG); 2527 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p), 2528 be32_to_cpu(cgr_state.cgr.cscn_targ)); 2529 2530 ret = qm_modify_cgr(cgr, 0, &local_opts); 2531 if (ret) 2532 /* add back to the list */ 2533 list_add(&cgr->node, &p->cgr_cbs); 2534 release_lock: 2535 spin_unlock_irqrestore(&p->cgr_lock, irqflags); 2536 put_portal: 2537 put_affine_portal(); 2538 return ret; 2539 } 2540 EXPORT_SYMBOL(qman_delete_cgr); 2541 2542 struct cgr_comp { 2543 struct qman_cgr *cgr; 2544 struct completion completion; 2545 }; 2546 2547 static void qman_delete_cgr_smp_call(void *p) 2548 { 2549 qman_delete_cgr((struct qman_cgr *)p); 2550 } 2551 2552 void qman_delete_cgr_safe(struct qman_cgr *cgr) 2553 { 2554 preempt_disable(); 2555 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) { 2556 smp_call_function_single(qman_cgr_cpus[cgr->cgrid], 2557 qman_delete_cgr_smp_call, cgr, true); 2558 preempt_enable(); 2559 return; 2560 } 2561 2562 qman_delete_cgr(cgr); 2563 preempt_enable(); 2564 } 2565 EXPORT_SYMBOL(qman_delete_cgr_safe); 2566 2567 /* Cleanup FQs */ 2568 2569 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v) 2570 { 2571 const union qm_mr_entry *msg; 2572 int found = 0; 2573 2574 qm_mr_pvb_update(p); 2575 msg = qm_mr_current(p); 2576 while (msg) { 2577 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v) 2578 found = 1; 2579 qm_mr_next(p); 2580 qm_mr_cci_consume_to_current(p); 2581 qm_mr_pvb_update(p); 2582 msg = qm_mr_current(p); 2583 } 2584 return found; 2585 } 2586 2587 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s, 2588 bool wait) 2589 { 2590 const struct qm_dqrr_entry *dqrr; 2591 int found = 0; 2592 2593 do { 2594 qm_dqrr_pvb_update(p); 2595 dqrr = qm_dqrr_current(p); 2596 if (!dqrr) 2597 cpu_relax(); 2598 } while (wait && !dqrr); 2599 2600 while (dqrr) { 2601 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s)) 2602 found = 1; 2603 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0); 2604 qm_dqrr_pvb_update(p); 2605 qm_dqrr_next(p); 2606 dqrr = qm_dqrr_current(p); 2607 } 2608 return found; 2609 } 2610 2611 #define qm_mr_drain(p, V) \ 2612 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V) 2613 2614 #define qm_dqrr_drain(p, f, S) \ 2615 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false) 2616 2617 #define qm_dqrr_drain_wait(p, f, S) \ 2618 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true) 2619 2620 #define qm_dqrr_drain_nomatch(p) \ 2621 _qm_dqrr_consume_and_match(p, 0, 0, false) 2622 2623 int qman_shutdown_fq(u32 fqid) 2624 { 2625 struct qman_portal *p, *channel_portal; 2626 struct device *dev; 2627 union qm_mc_command *mcc; 2628 union qm_mc_result *mcr; 2629 int orl_empty, drain = 0, ret = 0; 2630 u32 channel, wq, res; 2631 u8 state; 2632 2633 p = get_affine_portal(); 2634 dev = p->config->dev; 2635 /* Determine the state of the FQID */ 2636 mcc = qm_mc_start(&p->p); 2637 qm_fqid_set(&mcc->fq, fqid); 2638 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); 2639 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2640 dev_err(dev, "QUERYFQ_NP timeout\n"); 2641 ret = -ETIMEDOUT; 2642 goto out; 2643 } 2644 2645 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); 2646 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK; 2647 if (state == QM_MCR_NP_STATE_OOS) 2648 goto out; /* Already OOS, no need to do anymore checks */ 2649 2650 /* Query which channel the FQ is using */ 2651 mcc = qm_mc_start(&p->p); 2652 qm_fqid_set(&mcc->fq, fqid); 2653 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); 2654 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2655 dev_err(dev, "QUERYFQ timeout\n"); 2656 ret = -ETIMEDOUT; 2657 goto out; 2658 } 2659 2660 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); 2661 /* Need to store these since the MCR gets reused */ 2662 channel = qm_fqd_get_chan(&mcr->queryfq.fqd); 2663 wq = qm_fqd_get_wq(&mcr->queryfq.fqd); 2664 2665 if (channel < qm_channel_pool1) { 2666 channel_portal = get_portal_for_channel(channel); 2667 if (channel_portal == NULL) { 2668 dev_err(dev, "Can't find portal for dedicated channel 0x%x\n", 2669 channel); 2670 ret = -EIO; 2671 goto out; 2672 } 2673 } else 2674 channel_portal = p; 2675 2676 switch (state) { 2677 case QM_MCR_NP_STATE_TEN_SCHED: 2678 case QM_MCR_NP_STATE_TRU_SCHED: 2679 case QM_MCR_NP_STATE_ACTIVE: 2680 case QM_MCR_NP_STATE_PARKED: 2681 orl_empty = 0; 2682 mcc = qm_mc_start(&channel_portal->p); 2683 qm_fqid_set(&mcc->fq, fqid); 2684 qm_mc_commit(&channel_portal->p, QM_MCC_VERB_ALTER_RETIRE); 2685 if (!qm_mc_result_timeout(&channel_portal->p, &mcr)) { 2686 dev_err(dev, "ALTER_RETIRE timeout\n"); 2687 ret = -ETIMEDOUT; 2688 goto out; 2689 } 2690 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2691 QM_MCR_VERB_ALTER_RETIRE); 2692 res = mcr->result; /* Make a copy as we reuse MCR below */ 2693 2694 if (res == QM_MCR_RESULT_OK) 2695 drain_mr_fqrni(&channel_portal->p); 2696 2697 if (res == QM_MCR_RESULT_PENDING) { 2698 /* 2699 * Need to wait for the FQRN in the message ring, which 2700 * will only occur once the FQ has been drained. In 2701 * order for the FQ to drain the portal needs to be set 2702 * to dequeue from the channel the FQ is scheduled on 2703 */ 2704 int found_fqrn = 0; 2705 u16 dequeue_wq = 0; 2706 2707 /* Flag that we need to drain FQ */ 2708 drain = 1; 2709 2710 if (channel >= qm_channel_pool1 && 2711 channel < qm_channel_pool1 + 15) { 2712 /* Pool channel, enable the bit in the portal */ 2713 dequeue_wq = (channel - 2714 qm_channel_pool1 + 1)<<4 | wq; 2715 } else if (channel < qm_channel_pool1) { 2716 /* Dedicated channel */ 2717 dequeue_wq = wq; 2718 } else { 2719 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x", 2720 fqid, channel); 2721 ret = -EBUSY; 2722 goto out; 2723 } 2724 /* Set the sdqcr to drain this channel */ 2725 if (channel < qm_channel_pool1) 2726 qm_dqrr_sdqcr_set(&channel_portal->p, 2727 QM_SDQCR_TYPE_ACTIVE | 2728 QM_SDQCR_CHANNELS_DEDICATED); 2729 else 2730 qm_dqrr_sdqcr_set(&channel_portal->p, 2731 QM_SDQCR_TYPE_ACTIVE | 2732 QM_SDQCR_CHANNELS_POOL_CONV 2733 (channel)); 2734 do { 2735 /* Keep draining DQRR while checking the MR*/ 2736 qm_dqrr_drain_nomatch(&channel_portal->p); 2737 /* Process message ring too */ 2738 found_fqrn = qm_mr_drain(&channel_portal->p, 2739 FQRN); 2740 cpu_relax(); 2741 } while (!found_fqrn); 2742 /* Restore SDQCR */ 2743 qm_dqrr_sdqcr_set(&channel_portal->p, 2744 channel_portal->sdqcr); 2745 2746 } 2747 if (res != QM_MCR_RESULT_OK && 2748 res != QM_MCR_RESULT_PENDING) { 2749 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n", 2750 fqid, res); 2751 ret = -EIO; 2752 goto out; 2753 } 2754 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) { 2755 /* 2756 * ORL had no entries, no need to wait until the 2757 * ERNs come in 2758 */ 2759 orl_empty = 1; 2760 } 2761 /* 2762 * Retirement succeeded, check to see if FQ needs 2763 * to be drained 2764 */ 2765 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) { 2766 /* FQ is Not Empty, drain using volatile DQ commands */ 2767 do { 2768 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3); 2769 2770 qm_dqrr_vdqcr_set(&p->p, vdqcr); 2771 /* 2772 * Wait for a dequeue and process the dequeues, 2773 * making sure to empty the ring completely 2774 */ 2775 } while (!qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY)); 2776 } 2777 2778 while (!orl_empty) { 2779 /* Wait for the ORL to have been completely drained */ 2780 orl_empty = qm_mr_drain(&p->p, FQRL); 2781 cpu_relax(); 2782 } 2783 mcc = qm_mc_start(&p->p); 2784 qm_fqid_set(&mcc->fq, fqid); 2785 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 2786 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2787 ret = -ETIMEDOUT; 2788 goto out; 2789 } 2790 2791 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2792 QM_MCR_VERB_ALTER_OOS); 2793 if (mcr->result != QM_MCR_RESULT_OK) { 2794 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n", 2795 fqid, mcr->result); 2796 ret = -EIO; 2797 goto out; 2798 } 2799 break; 2800 2801 case QM_MCR_NP_STATE_RETIRED: 2802 /* Send OOS Command */ 2803 mcc = qm_mc_start(&p->p); 2804 qm_fqid_set(&mcc->fq, fqid); 2805 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 2806 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2807 ret = -ETIMEDOUT; 2808 goto out; 2809 } 2810 2811 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2812 QM_MCR_VERB_ALTER_OOS); 2813 if (mcr->result != QM_MCR_RESULT_OK) { 2814 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n", 2815 fqid, mcr->result); 2816 ret = -EIO; 2817 goto out; 2818 } 2819 break; 2820 2821 case QM_MCR_NP_STATE_OOS: 2822 /* Done */ 2823 break; 2824 2825 default: 2826 ret = -EIO; 2827 } 2828 2829 out: 2830 put_affine_portal(); 2831 return ret; 2832 } 2833 2834 const struct qm_portal_config *qman_get_qm_portal_config( 2835 struct qman_portal *portal) 2836 { 2837 return portal->config; 2838 } 2839 EXPORT_SYMBOL(qman_get_qm_portal_config); 2840 2841 struct gen_pool *qm_fqalloc; /* FQID allocator */ 2842 struct gen_pool *qm_qpalloc; /* pool-channel allocator */ 2843 struct gen_pool *qm_cgralloc; /* CGR ID allocator */ 2844 2845 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt) 2846 { 2847 unsigned long addr; 2848 2849 if (!p) 2850 return -ENODEV; 2851 2852 addr = gen_pool_alloc(p, cnt); 2853 if (!addr) 2854 return -ENOMEM; 2855 2856 *result = addr & ~DPAA_GENALLOC_OFF; 2857 2858 return 0; 2859 } 2860 2861 int qman_alloc_fqid_range(u32 *result, u32 count) 2862 { 2863 return qman_alloc_range(qm_fqalloc, result, count); 2864 } 2865 EXPORT_SYMBOL(qman_alloc_fqid_range); 2866 2867 int qman_alloc_pool_range(u32 *result, u32 count) 2868 { 2869 return qman_alloc_range(qm_qpalloc, result, count); 2870 } 2871 EXPORT_SYMBOL(qman_alloc_pool_range); 2872 2873 int qman_alloc_cgrid_range(u32 *result, u32 count) 2874 { 2875 return qman_alloc_range(qm_cgralloc, result, count); 2876 } 2877 EXPORT_SYMBOL(qman_alloc_cgrid_range); 2878 2879 int qman_release_fqid(u32 fqid) 2880 { 2881 int ret = qman_shutdown_fq(fqid); 2882 2883 if (ret) { 2884 pr_debug("FQID %d leaked\n", fqid); 2885 return ret; 2886 } 2887 2888 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1); 2889 return 0; 2890 } 2891 EXPORT_SYMBOL(qman_release_fqid); 2892 2893 static int qpool_cleanup(u32 qp) 2894 { 2895 /* 2896 * We query all FQDs starting from 2897 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs 2898 * whose destination channel is the pool-channel being released. 2899 * When a non-OOS FQD is found we attempt to clean it up 2900 */ 2901 struct qman_fq fq = { 2902 .fqid = QM_FQID_RANGE_START 2903 }; 2904 int err; 2905 2906 do { 2907 struct qm_mcr_queryfq_np np; 2908 2909 err = qman_query_fq_np(&fq, &np); 2910 if (err == -ERANGE) 2911 /* FQID range exceeded, found no problems */ 2912 return 0; 2913 else if (WARN_ON(err)) 2914 return err; 2915 2916 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { 2917 struct qm_fqd fqd; 2918 2919 err = qman_query_fq(&fq, &fqd); 2920 if (WARN_ON(err)) 2921 return err; 2922 if (qm_fqd_get_chan(&fqd) == qp) { 2923 /* The channel is the FQ's target, clean it */ 2924 err = qman_shutdown_fq(fq.fqid); 2925 if (err) 2926 /* 2927 * Couldn't shut down the FQ 2928 * so the pool must be leaked 2929 */ 2930 return err; 2931 } 2932 } 2933 /* Move to the next FQID */ 2934 fq.fqid++; 2935 } while (1); 2936 } 2937 2938 int qman_release_pool(u32 qp) 2939 { 2940 int ret; 2941 2942 ret = qpool_cleanup(qp); 2943 if (ret) { 2944 pr_debug("CHID %d leaked\n", qp); 2945 return ret; 2946 } 2947 2948 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1); 2949 return 0; 2950 } 2951 EXPORT_SYMBOL(qman_release_pool); 2952 2953 static int cgr_cleanup(u32 cgrid) 2954 { 2955 /* 2956 * query all FQDs starting from FQID 1 until we get an "invalid FQID" 2957 * error, looking for non-OOS FQDs whose CGR is the CGR being released 2958 */ 2959 struct qman_fq fq = { 2960 .fqid = QM_FQID_RANGE_START 2961 }; 2962 int err; 2963 2964 do { 2965 struct qm_mcr_queryfq_np np; 2966 2967 err = qman_query_fq_np(&fq, &np); 2968 if (err == -ERANGE) 2969 /* FQID range exceeded, found no problems */ 2970 return 0; 2971 else if (WARN_ON(err)) 2972 return err; 2973 2974 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { 2975 struct qm_fqd fqd; 2976 2977 err = qman_query_fq(&fq, &fqd); 2978 if (WARN_ON(err)) 2979 return err; 2980 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE && 2981 fqd.cgid == cgrid) { 2982 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n", 2983 cgrid, fq.fqid); 2984 return -EIO; 2985 } 2986 } 2987 /* Move to the next FQID */ 2988 fq.fqid++; 2989 } while (1); 2990 } 2991 2992 int qman_release_cgrid(u32 cgrid) 2993 { 2994 int ret; 2995 2996 ret = cgr_cleanup(cgrid); 2997 if (ret) { 2998 pr_debug("CGRID %d leaked\n", cgrid); 2999 return ret; 3000 } 3001 3002 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1); 3003 return 0; 3004 } 3005 EXPORT_SYMBOL(qman_release_cgrid); 3006