1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 /* 3 * Apple mailbox driver 4 * 5 * Copyright The Asahi Linux Contributors 6 * 7 * This driver adds support for two mailbox variants (called ASC and M3 by 8 * Apple) found in Apple SoCs such as the M1. It consists of two FIFOs used to 9 * exchange 64+32 bit messages between the main CPU and a co-processor. 10 * Various coprocessors implement different IPC protocols based on these simple 11 * messages and shared memory buffers. 12 * 13 * Both the main CPU and the co-processor see the same set of registers but 14 * the first FIFO (A2I) is always used to transfer messages from the application 15 * processor (us) to the I/O processor and the second one (I2A) for the 16 * other direction. 17 */ 18 19 #include <linux/bitfield.h> 20 #include <linux/bits.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/iopoll.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/spinlock.h> 32 #include <linux/types.h> 33 #include "mailbox.h" 34 35 #define APPLE_ASC_MBOX_CONTROL_FULL BIT(16) 36 #define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17) 37 38 #define APPLE_ASC_MBOX_A2I_CONTROL 0x110 39 #define APPLE_ASC_MBOX_A2I_SEND0 0x800 40 #define APPLE_ASC_MBOX_A2I_SEND1 0x808 41 #define APPLE_ASC_MBOX_A2I_RECV0 0x810 42 #define APPLE_ASC_MBOX_A2I_RECV1 0x818 43 44 #define APPLE_ASC_MBOX_I2A_CONTROL 0x114 45 #define APPLE_ASC_MBOX_I2A_SEND0 0x820 46 #define APPLE_ASC_MBOX_I2A_SEND1 0x828 47 #define APPLE_ASC_MBOX_I2A_RECV0 0x830 48 #define APPLE_ASC_MBOX_I2A_RECV1 0x838 49 50 #define APPLE_T8015_MBOX_A2I_CONTROL 0x108 51 #define APPLE_T8015_MBOX_I2A_CONTROL 0x10c 52 53 #define APPLE_M3_MBOX_CONTROL_FULL BIT(16) 54 #define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17) 55 56 #define APPLE_M3_MBOX_A2I_CONTROL 0x50 57 #define APPLE_M3_MBOX_A2I_SEND0 0x60 58 #define APPLE_M3_MBOX_A2I_SEND1 0x68 59 #define APPLE_M3_MBOX_A2I_RECV0 0x70 60 #define APPLE_M3_MBOX_A2I_RECV1 0x78 61 62 #define APPLE_M3_MBOX_I2A_CONTROL 0x80 63 #define APPLE_M3_MBOX_I2A_SEND0 0x90 64 #define APPLE_M3_MBOX_I2A_SEND1 0x98 65 #define APPLE_M3_MBOX_I2A_RECV0 0xa0 66 #define APPLE_M3_MBOX_I2A_RECV1 0xa8 67 68 #define APPLE_M3_MBOX_IRQ_ENABLE 0x48 69 #define APPLE_M3_MBOX_IRQ_ACK 0x4c 70 #define APPLE_M3_MBOX_IRQ_A2I_EMPTY BIT(0) 71 #define APPLE_M3_MBOX_IRQ_A2I_NOT_EMPTY BIT(1) 72 #define APPLE_M3_MBOX_IRQ_I2A_EMPTY BIT(2) 73 #define APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY BIT(3) 74 75 #define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52) 76 #define APPLE_MBOX_MSG1_INCNT GENMASK(51, 48) 77 #define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44) 78 #define APPLE_MBOX_MSG1_INPTR GENMASK(43, 40) 79 #define APPLE_MBOX_MSG1_MSG GENMASK(31, 0) 80 81 #define APPLE_MBOX_TX_TIMEOUT 500 82 83 struct apple_mbox_hw { 84 unsigned int control_full; 85 unsigned int control_empty; 86 87 unsigned int a2i_control; 88 unsigned int a2i_send0; 89 unsigned int a2i_send1; 90 91 unsigned int i2a_control; 92 unsigned int i2a_recv0; 93 unsigned int i2a_recv1; 94 95 bool has_irq_controls; 96 unsigned int irq_enable; 97 unsigned int irq_ack; 98 unsigned int irq_bit_recv_not_empty; 99 unsigned int irq_bit_send_empty; 100 }; 101 102 int apple_mbox_send(struct apple_mbox *mbox, const struct apple_mbox_msg msg, 103 bool atomic) 104 { 105 unsigned long flags; 106 int ret; 107 u32 mbox_ctrl; 108 long t; 109 110 spin_lock_irqsave(&mbox->tx_lock, flags); 111 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->a2i_control); 112 113 while (mbox_ctrl & mbox->hw->control_full) { 114 if (atomic) { 115 ret = readl_poll_timeout_atomic( 116 mbox->regs + mbox->hw->a2i_control, mbox_ctrl, 117 !(mbox_ctrl & mbox->hw->control_full), 100, 118 APPLE_MBOX_TX_TIMEOUT * 1000); 119 120 if (ret) { 121 spin_unlock_irqrestore(&mbox->tx_lock, flags); 122 return ret; 123 } 124 125 break; 126 } 127 /* 128 * The interrupt is level triggered and will keep firing as long as the 129 * FIFO is empty. It will also keep firing if the FIFO was empty 130 * at any point in the past until it has been acknowledged at the 131 * mailbox level. By acknowledging it here we can ensure that we will 132 * only get the interrupt once the FIFO has been cleared again. 133 * If the FIFO is already empty before the ack it will fire again 134 * immediately after the ack. 135 */ 136 if (mbox->hw->has_irq_controls) { 137 writel_relaxed(mbox->hw->irq_bit_send_empty, 138 mbox->regs + mbox->hw->irq_ack); 139 } 140 enable_irq(mbox->irq_send_empty); 141 reinit_completion(&mbox->tx_empty); 142 spin_unlock_irqrestore(&mbox->tx_lock, flags); 143 144 t = wait_for_completion_interruptible_timeout( 145 &mbox->tx_empty, 146 msecs_to_jiffies(APPLE_MBOX_TX_TIMEOUT)); 147 if (t < 0) 148 return t; 149 else if (t == 0) 150 return -ETIMEDOUT; 151 152 spin_lock_irqsave(&mbox->tx_lock, flags); 153 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->a2i_control); 154 } 155 156 writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0); 157 writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1), 158 mbox->regs + mbox->hw->a2i_send1); 159 160 spin_unlock_irqrestore(&mbox->tx_lock, flags); 161 162 return 0; 163 } 164 EXPORT_SYMBOL(apple_mbox_send); 165 166 static irqreturn_t apple_mbox_send_empty_irq(int irq, void *data) 167 { 168 struct apple_mbox *mbox = data; 169 170 /* 171 * We don't need to acknowledge the interrupt at the mailbox level 172 * here even if supported by the hardware. It will keep firing but that 173 * doesn't matter since it's disabled at the main interrupt controller. 174 * apple_mbox_send will acknowledge it before enabling 175 * it at the main controller again. 176 */ 177 spin_lock(&mbox->tx_lock); 178 disable_irq_nosync(mbox->irq_send_empty); 179 complete(&mbox->tx_empty); 180 spin_unlock(&mbox->tx_lock); 181 182 return IRQ_HANDLED; 183 } 184 185 static int apple_mbox_poll_locked(struct apple_mbox *mbox) 186 { 187 struct apple_mbox_msg msg; 188 int ret = 0; 189 190 u32 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->i2a_control); 191 192 while (!(mbox_ctrl & mbox->hw->control_empty)) { 193 msg.msg0 = readq_relaxed(mbox->regs + mbox->hw->i2a_recv0); 194 msg.msg1 = FIELD_GET( 195 APPLE_MBOX_MSG1_MSG, 196 readq_relaxed(mbox->regs + mbox->hw->i2a_recv1)); 197 198 mbox->rx(mbox, msg, mbox->cookie); 199 ret++; 200 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->i2a_control); 201 } 202 203 /* 204 * The interrupt will keep firing even if there are no more messages 205 * unless we also acknowledge it at the mailbox level here. 206 * There's no race if a message comes in between the check in the while 207 * loop above and the ack below: If a new messages arrives inbetween 208 * those two the interrupt will just fire again immediately after the 209 * ack since it's level triggered. 210 */ 211 if (mbox->hw->has_irq_controls) { 212 writel_relaxed(mbox->hw->irq_bit_recv_not_empty, 213 mbox->regs + mbox->hw->irq_ack); 214 } 215 216 return ret; 217 } 218 219 static irqreturn_t apple_mbox_recv_irq(int irq, void *data) 220 { 221 struct apple_mbox *mbox = data; 222 223 spin_lock(&mbox->rx_lock); 224 apple_mbox_poll_locked(mbox); 225 spin_unlock(&mbox->rx_lock); 226 227 return IRQ_HANDLED; 228 } 229 230 int apple_mbox_poll(struct apple_mbox *mbox) 231 { 232 unsigned long flags; 233 int ret; 234 235 spin_lock_irqsave(&mbox->rx_lock, flags); 236 ret = apple_mbox_poll_locked(mbox); 237 spin_unlock_irqrestore(&mbox->rx_lock, flags); 238 239 return ret; 240 } 241 EXPORT_SYMBOL(apple_mbox_poll); 242 243 int apple_mbox_start(struct apple_mbox *mbox) 244 { 245 int ret; 246 247 if (mbox->active) 248 return 0; 249 250 ret = pm_runtime_resume_and_get(mbox->dev); 251 if (ret) 252 return ret; 253 254 /* 255 * Only some variants of this mailbox HW provide interrupt control 256 * at the mailbox level. We therefore need to handle enabling/disabling 257 * interrupts at the main interrupt controller anyway for hardware that 258 * doesn't. Just always keep the interrupts we care about enabled at 259 * the mailbox level so that both hardware revisions behave almost 260 * the same. 261 */ 262 if (mbox->hw->has_irq_controls) { 263 writel_relaxed(mbox->hw->irq_bit_recv_not_empty | 264 mbox->hw->irq_bit_send_empty, 265 mbox->regs + mbox->hw->irq_enable); 266 } 267 268 enable_irq(mbox->irq_recv_not_empty); 269 mbox->active = true; 270 return 0; 271 } 272 EXPORT_SYMBOL(apple_mbox_start); 273 274 void apple_mbox_stop(struct apple_mbox *mbox) 275 { 276 if (!mbox->active) 277 return; 278 279 mbox->active = false; 280 disable_irq(mbox->irq_recv_not_empty); 281 pm_runtime_mark_last_busy(mbox->dev); 282 pm_runtime_put_autosuspend(mbox->dev); 283 } 284 EXPORT_SYMBOL(apple_mbox_stop); 285 286 struct apple_mbox *apple_mbox_get(struct device *dev, int index) 287 { 288 struct of_phandle_args args; 289 struct platform_device *pdev; 290 struct apple_mbox *mbox; 291 int ret; 292 293 ret = of_parse_phandle_with_args(dev->of_node, "mboxes", "#mbox-cells", 294 index, &args); 295 if (ret || !args.np) 296 return ERR_PTR(ret); 297 298 pdev = of_find_device_by_node(args.np); 299 of_node_put(args.np); 300 301 if (!pdev) 302 return ERR_PTR(-EPROBE_DEFER); 303 304 mbox = platform_get_drvdata(pdev); 305 if (!mbox) 306 return ERR_PTR(-EPROBE_DEFER); 307 308 if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_CONSUMER)) 309 return ERR_PTR(-ENODEV); 310 311 return mbox; 312 } 313 EXPORT_SYMBOL(apple_mbox_get); 314 315 struct apple_mbox *apple_mbox_get_byname(struct device *dev, const char *name) 316 { 317 int index; 318 319 index = of_property_match_string(dev->of_node, "mbox-names", name); 320 if (index < 0) 321 return ERR_PTR(index); 322 323 return apple_mbox_get(dev, index); 324 } 325 EXPORT_SYMBOL(apple_mbox_get_byname); 326 327 static int apple_mbox_probe(struct platform_device *pdev) 328 { 329 int ret; 330 char *irqname; 331 struct apple_mbox *mbox; 332 struct device *dev = &pdev->dev; 333 334 mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); 335 if (!mbox) 336 return -ENOMEM; 337 338 mbox->dev = &pdev->dev; 339 mbox->hw = of_device_get_match_data(dev); 340 if (!mbox->hw) 341 return -EINVAL; 342 343 mbox->regs = devm_platform_ioremap_resource(pdev, 0); 344 if (IS_ERR(mbox->regs)) 345 return PTR_ERR(mbox->regs); 346 347 mbox->irq_recv_not_empty = 348 platform_get_irq_byname(pdev, "recv-not-empty"); 349 if (mbox->irq_recv_not_empty < 0) 350 return -ENODEV; 351 352 mbox->irq_send_empty = platform_get_irq_byname(pdev, "send-empty"); 353 if (mbox->irq_send_empty < 0) 354 return -ENODEV; 355 356 spin_lock_init(&mbox->rx_lock); 357 spin_lock_init(&mbox->tx_lock); 358 init_completion(&mbox->tx_empty); 359 360 irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-recv", dev_name(dev)); 361 if (!irqname) 362 return -ENOMEM; 363 364 ret = devm_request_irq(dev, mbox->irq_recv_not_empty, 365 apple_mbox_recv_irq, 366 IRQF_NO_AUTOEN | IRQF_NO_SUSPEND, irqname, mbox); 367 if (ret) 368 return ret; 369 370 irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-send", dev_name(dev)); 371 if (!irqname) 372 return -ENOMEM; 373 374 ret = devm_request_irq(dev, mbox->irq_send_empty, 375 apple_mbox_send_empty_irq, 376 IRQF_NO_AUTOEN | IRQF_NO_SUSPEND, irqname, mbox); 377 if (ret) 378 return ret; 379 380 ret = devm_pm_runtime_enable(dev); 381 if (ret) 382 return ret; 383 384 platform_set_drvdata(pdev, mbox); 385 return 0; 386 } 387 388 static const struct apple_mbox_hw apple_mbox_t8015_hw = { 389 .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 390 .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, 391 392 .a2i_control = APPLE_T8015_MBOX_A2I_CONTROL, 393 .a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0, 394 .a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1, 395 396 .i2a_control = APPLE_T8015_MBOX_I2A_CONTROL, 397 .i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0, 398 .i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1, 399 400 .has_irq_controls = false, 401 }; 402 403 static const struct apple_mbox_hw apple_mbox_asc_hw = { 404 .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 405 .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, 406 407 .a2i_control = APPLE_ASC_MBOX_A2I_CONTROL, 408 .a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0, 409 .a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1, 410 411 .i2a_control = APPLE_ASC_MBOX_I2A_CONTROL, 412 .i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0, 413 .i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1, 414 415 .has_irq_controls = false, 416 }; 417 418 static const struct apple_mbox_hw apple_mbox_m3_hw = { 419 .control_full = APPLE_M3_MBOX_CONTROL_FULL, 420 .control_empty = APPLE_M3_MBOX_CONTROL_EMPTY, 421 422 .a2i_control = APPLE_M3_MBOX_A2I_CONTROL, 423 .a2i_send0 = APPLE_M3_MBOX_A2I_SEND0, 424 .a2i_send1 = APPLE_M3_MBOX_A2I_SEND1, 425 426 .i2a_control = APPLE_M3_MBOX_I2A_CONTROL, 427 .i2a_recv0 = APPLE_M3_MBOX_I2A_RECV0, 428 .i2a_recv1 = APPLE_M3_MBOX_I2A_RECV1, 429 430 .has_irq_controls = true, 431 .irq_enable = APPLE_M3_MBOX_IRQ_ENABLE, 432 .irq_ack = APPLE_M3_MBOX_IRQ_ACK, 433 .irq_bit_recv_not_empty = APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY, 434 .irq_bit_send_empty = APPLE_M3_MBOX_IRQ_A2I_EMPTY, 435 }; 436 437 static const struct of_device_id apple_mbox_of_match[] = { 438 { .compatible = "apple,asc-mailbox-v4", .data = &apple_mbox_asc_hw }, 439 { .compatible = "apple,t8015-asc-mailbox", .data = &apple_mbox_t8015_hw }, 440 { .compatible = "apple,m3-mailbox-v2", .data = &apple_mbox_m3_hw }, 441 {} 442 }; 443 MODULE_DEVICE_TABLE(of, apple_mbox_of_match); 444 445 static struct platform_driver apple_mbox_driver = { 446 .driver = { 447 .name = "apple-mailbox", 448 .of_match_table = apple_mbox_of_match, 449 }, 450 .probe = apple_mbox_probe, 451 }; 452 module_platform_driver(apple_mbox_driver); 453 454 MODULE_LICENSE("Dual MIT/GPL"); 455 MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>"); 456 MODULE_DESCRIPTION("Apple Mailbox driver"); 457