1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * Copyright (C) 2014 Endless Mobile 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/regmap.h> 12 #include <linux/soc/amlogic/meson-canvas.h> 13 #include <linux/of_address.h> 14 #include <linux/of_platform.h> 15 #include <linux/io.h> 16 17 #define NUM_CANVAS 256 18 19 /* DMC Registers */ 20 #define DMC_CAV_LUT_DATAL 0x00 21 #define CANVAS_WIDTH_LBIT 29 22 #define CANVAS_WIDTH_LWID 3 23 #define DMC_CAV_LUT_DATAH 0x04 24 #define CANVAS_WIDTH_HBIT 0 25 #define CANVAS_HEIGHT_BIT 9 26 #define CANVAS_WRAP_BIT 22 27 #define CANVAS_BLKMODE_BIT 24 28 #define CANVAS_ENDIAN_BIT 26 29 #define DMC_CAV_LUT_ADDR 0x08 30 #define CANVAS_LUT_WR_EN BIT(9) 31 #define CANVAS_LUT_RD_EN BIT(8) 32 33 struct meson_canvas { 34 struct device *dev; 35 void __iomem *reg_base; 36 spinlock_t lock; /* canvas device lock */ 37 u8 used[NUM_CANVAS]; 38 bool supports_endianness; 39 }; 40 41 static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val) 42 { 43 writel_relaxed(val, canvas->reg_base + reg); 44 } 45 46 static u32 canvas_read(struct meson_canvas *canvas, u32 reg) 47 { 48 return readl_relaxed(canvas->reg_base + reg); 49 } 50 51 struct meson_canvas *meson_canvas_get(struct device *dev) 52 { 53 struct device_node *canvas_node; 54 struct platform_device *canvas_pdev; 55 struct meson_canvas *canvas; 56 57 canvas_node = of_parse_phandle(dev->of_node, "amlogic,canvas", 0); 58 if (!canvas_node) 59 return ERR_PTR(-ENODEV); 60 61 canvas_pdev = of_find_device_by_node(canvas_node); 62 if (!canvas_pdev) { 63 of_node_put(canvas_node); 64 return ERR_PTR(-EPROBE_DEFER); 65 } 66 67 of_node_put(canvas_node); 68 69 /* 70 * If priv is NULL, it's probably because the canvas hasn't 71 * properly initialized. Bail out with -EINVAL because, in the 72 * current state, this driver probe cannot return -EPROBE_DEFER 73 */ 74 canvas = dev_get_drvdata(&canvas_pdev->dev); 75 if (!canvas) 76 return ERR_PTR(-EINVAL); 77 78 return canvas; 79 } 80 EXPORT_SYMBOL_GPL(meson_canvas_get); 81 82 int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index, 83 u32 addr, u32 stride, u32 height, 84 unsigned int wrap, 85 unsigned int blkmode, 86 unsigned int endian) 87 { 88 unsigned long flags; 89 90 if (endian && !canvas->supports_endianness) { 91 dev_err(canvas->dev, 92 "Endianness is not supported on this SoC\n"); 93 return -EINVAL; 94 } 95 96 spin_lock_irqsave(&canvas->lock, flags); 97 if (!canvas->used[canvas_index]) { 98 dev_err(canvas->dev, 99 "Trying to setup non allocated canvas %u\n", 100 canvas_index); 101 spin_unlock_irqrestore(&canvas->lock, flags); 102 return -EINVAL; 103 } 104 105 canvas_write(canvas, DMC_CAV_LUT_DATAL, 106 ((addr + 7) >> 3) | 107 (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT)); 108 109 canvas_write(canvas, DMC_CAV_LUT_DATAH, 110 ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) << 111 CANVAS_WIDTH_HBIT) | 112 (height << CANVAS_HEIGHT_BIT) | 113 (wrap << CANVAS_WRAP_BIT) | 114 (blkmode << CANVAS_BLKMODE_BIT) | 115 (endian << CANVAS_ENDIAN_BIT)); 116 117 canvas_write(canvas, DMC_CAV_LUT_ADDR, 118 CANVAS_LUT_WR_EN | canvas_index); 119 120 /* Force a read-back to make sure everything is flushed. */ 121 canvas_read(canvas, DMC_CAV_LUT_DATAH); 122 spin_unlock_irqrestore(&canvas->lock, flags); 123 124 return 0; 125 } 126 EXPORT_SYMBOL_GPL(meson_canvas_config); 127 128 int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index) 129 { 130 int i; 131 unsigned long flags; 132 133 spin_lock_irqsave(&canvas->lock, flags); 134 for (i = 0; i < NUM_CANVAS; ++i) { 135 if (!canvas->used[i]) { 136 canvas->used[i] = 1; 137 spin_unlock_irqrestore(&canvas->lock, flags); 138 *canvas_index = i; 139 return 0; 140 } 141 } 142 spin_unlock_irqrestore(&canvas->lock, flags); 143 144 dev_err(canvas->dev, "No more canvas available\n"); 145 return -ENODEV; 146 } 147 EXPORT_SYMBOL_GPL(meson_canvas_alloc); 148 149 int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&canvas->lock, flags); 154 if (!canvas->used[canvas_index]) { 155 dev_err(canvas->dev, 156 "Trying to free unused canvas %u\n", canvas_index); 157 spin_unlock_irqrestore(&canvas->lock, flags); 158 return -EINVAL; 159 } 160 canvas->used[canvas_index] = 0; 161 spin_unlock_irqrestore(&canvas->lock, flags); 162 163 return 0; 164 } 165 EXPORT_SYMBOL_GPL(meson_canvas_free); 166 167 static int meson_canvas_probe(struct platform_device *pdev) 168 { 169 struct resource *res; 170 struct meson_canvas *canvas; 171 struct device *dev = &pdev->dev; 172 173 canvas = devm_kzalloc(dev, sizeof(*canvas), GFP_KERNEL); 174 if (!canvas) 175 return -ENOMEM; 176 177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 178 canvas->reg_base = devm_ioremap_resource(dev, res); 179 if (IS_ERR(canvas->reg_base)) 180 return PTR_ERR(canvas->reg_base); 181 182 canvas->supports_endianness = of_device_get_match_data(dev); 183 184 canvas->dev = dev; 185 spin_lock_init(&canvas->lock); 186 dev_set_drvdata(dev, canvas); 187 188 return 0; 189 } 190 191 static const struct of_device_id canvas_dt_match[] = { 192 { .compatible = "amlogic,meson8-canvas", .data = (void *)false, }, 193 { .compatible = "amlogic,meson8b-canvas", .data = (void *)false, }, 194 { .compatible = "amlogic,meson8m2-canvas", .data = (void *)false, }, 195 { .compatible = "amlogic,canvas", .data = (void *)true, }, 196 {} 197 }; 198 MODULE_DEVICE_TABLE(of, canvas_dt_match); 199 200 static struct platform_driver meson_canvas_driver = { 201 .probe = meson_canvas_probe, 202 .driver = { 203 .name = "amlogic-canvas", 204 .of_match_table = canvas_dt_match, 205 }, 206 }; 207 module_platform_driver(meson_canvas_driver); 208 209 MODULE_DESCRIPTION("Amlogic Canvas driver"); 210 MODULE_AUTHOR("Maxime Jourdan <mjourdan@baylibre.com>"); 211 MODULE_LICENSE("GPL"); 212