1 /* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx> 7 * 8 * This driver is derived from the Linux sym53c8xx driver. 9 * Copyright (C) 1998-2000 Gerard Roudier 10 * 11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 12 * a port of the FreeBSD ncr driver to Linux-1.2.13. 13 * 14 * The original ncr driver has been written for 386bsd and FreeBSD by 15 * Wolfgang Stanglmeier <wolf@cologne.de> 16 * Stefan Esser <se@mi.Uni-Koeln.de> 17 * Copyright (C) 1994 Wolfgang Stanglmeier 18 * 19 * Other major contributions: 20 * 21 * NVRAM detection and reading. 22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 23 * 24 *----------------------------------------------------------------------------- 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 */ 40 41 #include <linux/slab.h> 42 43 #include "sym_glue.h" 44 #include "sym_nvram.h" 45 46 #if 0 47 #define SYM_DEBUG_GENERIC_SUPPORT 48 #endif 49 50 /* 51 * Needed function prototypes. 52 */ 53 static void sym_int_ma (struct sym_hcb *np); 54 static void sym_int_sir (struct sym_hcb *np); 55 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np); 56 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa); 57 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln); 58 static void sym_complete_error (struct sym_hcb *np, struct sym_ccb *cp); 59 static void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp); 60 static int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp); 61 62 /* 63 * Print a buffer in hexadecimal format with a ".\n" at end. 64 */ 65 static void sym_printl_hex(u_char *p, int n) 66 { 67 while (n-- > 0) 68 printf (" %x", *p++); 69 printf (".\n"); 70 } 71 72 /* 73 * Print out the content of a SCSI message. 74 */ 75 static int sym_show_msg (u_char * msg) 76 { 77 u_char i; 78 printf ("%x",*msg); 79 if (*msg==M_EXTENDED) { 80 for (i=1;i<8;i++) { 81 if (i-1>msg[1]) break; 82 printf ("-%x",msg[i]); 83 } 84 return (i+1); 85 } else if ((*msg & 0xf0) == 0x20) { 86 printf ("-%x",msg[1]); 87 return (2); 88 } 89 return (1); 90 } 91 92 static void sym_print_msg(struct sym_ccb *cp, char *label, u_char *msg) 93 { 94 sym_print_addr(cp->cmd, "%s: ", label); 95 96 sym_show_msg(msg); 97 printf(".\n"); 98 } 99 100 static void sym_print_nego_msg(struct sym_hcb *np, int target, char *label, u_char *msg) 101 { 102 struct sym_tcb *tp = &np->target[target]; 103 dev_info(&tp->starget->dev, "%s: ", label); 104 105 sym_show_msg(msg); 106 printf(".\n"); 107 } 108 109 /* 110 * Print something that tells about extended errors. 111 */ 112 void sym_print_xerr(struct scsi_cmnd *cmd, int x_status) 113 { 114 if (x_status & XE_PARITY_ERR) { 115 sym_print_addr(cmd, "unrecovered SCSI parity error.\n"); 116 } 117 if (x_status & XE_EXTRA_DATA) { 118 sym_print_addr(cmd, "extraneous data discarded.\n"); 119 } 120 if (x_status & XE_BAD_PHASE) { 121 sym_print_addr(cmd, "illegal scsi phase (4/5).\n"); 122 } 123 if (x_status & XE_SODL_UNRUN) { 124 sym_print_addr(cmd, "ODD transfer in DATA OUT phase.\n"); 125 } 126 if (x_status & XE_SWIDE_OVRUN) { 127 sym_print_addr(cmd, "ODD transfer in DATA IN phase.\n"); 128 } 129 } 130 131 /* 132 * Return a string for SCSI BUS mode. 133 */ 134 static char *sym_scsi_bus_mode(int mode) 135 { 136 switch(mode) { 137 case SMODE_HVD: return "HVD"; 138 case SMODE_SE: return "SE"; 139 case SMODE_LVD: return "LVD"; 140 } 141 return "??"; 142 } 143 144 /* 145 * Soft reset the chip. 146 * 147 * Raising SRST when the chip is running may cause 148 * problems on dual function chips (see below). 149 * On the other hand, LVD devices need some delay 150 * to settle and report actual BUS mode in STEST4. 151 */ 152 static void sym_chip_reset (struct sym_hcb *np) 153 { 154 OUTB(np, nc_istat, SRST); 155 INB(np, nc_mbox1); 156 udelay(10); 157 OUTB(np, nc_istat, 0); 158 INB(np, nc_mbox1); 159 udelay(2000); /* For BUS MODE to settle */ 160 } 161 162 /* 163 * Really soft reset the chip.:) 164 * 165 * Some 896 and 876 chip revisions may hang-up if we set 166 * the SRST (soft reset) bit at the wrong time when SCRIPTS 167 * are running. 168 * So, we need to abort the current operation prior to 169 * soft resetting the chip. 170 */ 171 static void sym_soft_reset (struct sym_hcb *np) 172 { 173 u_char istat = 0; 174 int i; 175 176 if (!(np->features & FE_ISTAT1) || !(INB(np, nc_istat1) & SCRUN)) 177 goto do_chip_reset; 178 179 OUTB(np, nc_istat, CABRT); 180 for (i = 100000 ; i ; --i) { 181 istat = INB(np, nc_istat); 182 if (istat & SIP) { 183 INW(np, nc_sist); 184 } 185 else if (istat & DIP) { 186 if (INB(np, nc_dstat) & ABRT) 187 break; 188 } 189 udelay(5); 190 } 191 OUTB(np, nc_istat, 0); 192 if (!i) 193 printf("%s: unable to abort current chip operation, " 194 "ISTAT=0x%02x.\n", sym_name(np), istat); 195 do_chip_reset: 196 sym_chip_reset(np); 197 } 198 199 /* 200 * Start reset process. 201 * 202 * The interrupt handler will reinitialize the chip. 203 */ 204 static void sym_start_reset(struct sym_hcb *np) 205 { 206 sym_reset_scsi_bus(np, 1); 207 } 208 209 int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int) 210 { 211 u32 term; 212 int retv = 0; 213 214 sym_soft_reset(np); /* Soft reset the chip */ 215 if (enab_int) 216 OUTW(np, nc_sien, RST); 217 /* 218 * Enable Tolerant, reset IRQD if present and 219 * properly set IRQ mode, prior to resetting the bus. 220 */ 221 OUTB(np, nc_stest3, TE); 222 OUTB(np, nc_dcntl, (np->rv_dcntl & IRQM)); 223 OUTB(np, nc_scntl1, CRST); 224 INB(np, nc_mbox1); 225 udelay(200); 226 227 if (!SYM_SETUP_SCSI_BUS_CHECK) 228 goto out; 229 /* 230 * Check for no terminators or SCSI bus shorts to ground. 231 * Read SCSI data bus, data parity bits and control signals. 232 * We are expecting RESET to be TRUE and other signals to be 233 * FALSE. 234 */ 235 term = INB(np, nc_sstat0); 236 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 237 term |= ((INB(np, nc_sstat2) & 0x01) << 26) | /* sdp1 */ 238 ((INW(np, nc_sbdl) & 0xff) << 9) | /* d7-0 */ 239 ((INW(np, nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 240 INB(np, nc_sbcl); /* req ack bsy sel atn msg cd io */ 241 242 if (!np->maxwide) 243 term &= 0x3ffff; 244 245 if (term != (2<<7)) { 246 printf("%s: suspicious SCSI data while resetting the BUS.\n", 247 sym_name(np)); 248 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 249 "0x%lx, expecting 0x%lx\n", 250 sym_name(np), 251 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 252 (u_long)term, (u_long)(2<<7)); 253 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 254 retv = 1; 255 } 256 out: 257 OUTB(np, nc_scntl1, 0); 258 return retv; 259 } 260 261 /* 262 * Select SCSI clock frequency 263 */ 264 static void sym_selectclock(struct sym_hcb *np, u_char scntl3) 265 { 266 /* 267 * If multiplier not present or not selected, leave here. 268 */ 269 if (np->multiplier <= 1) { 270 OUTB(np, nc_scntl3, scntl3); 271 return; 272 } 273 274 if (sym_verbose >= 2) 275 printf ("%s: enabling clock multiplier\n", sym_name(np)); 276 277 OUTB(np, nc_stest1, DBLEN); /* Enable clock multiplier */ 278 /* 279 * Wait for the LCKFRQ bit to be set if supported by the chip. 280 * Otherwise wait 50 micro-seconds (at least). 281 */ 282 if (np->features & FE_LCKFRQ) { 283 int i = 20; 284 while (!(INB(np, nc_stest4) & LCKFRQ) && --i > 0) 285 udelay(20); 286 if (!i) 287 printf("%s: the chip cannot lock the frequency\n", 288 sym_name(np)); 289 } else { 290 INB(np, nc_mbox1); 291 udelay(50+10); 292 } 293 OUTB(np, nc_stest3, HSC); /* Halt the scsi clock */ 294 OUTB(np, nc_scntl3, scntl3); 295 OUTB(np, nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 296 OUTB(np, nc_stest3, 0x00); /* Restart scsi clock */ 297 } 298 299 300 /* 301 * Determine the chip's clock frequency. 302 * 303 * This is essential for the negotiation of the synchronous 304 * transfer rate. 305 * 306 * Note: we have to return the correct value. 307 * THERE IS NO SAFE DEFAULT VALUE. 308 * 309 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 310 * 53C860 and 53C875 rev. 1 support fast20 transfers but 311 * do not have a clock doubler and so are provided with a 312 * 80 MHz clock. All other fast20 boards incorporate a doubler 313 * and so should be delivered with a 40 MHz clock. 314 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 315 * clock and provide a clock quadrupler (160 Mhz). 316 */ 317 318 /* 319 * calculate SCSI clock frequency (in KHz) 320 */ 321 static unsigned getfreq (struct sym_hcb *np, int gen) 322 { 323 unsigned int ms = 0; 324 unsigned int f; 325 326 /* 327 * Measure GEN timer delay in order 328 * to calculate SCSI clock frequency 329 * 330 * This code will never execute too 331 * many loop iterations (if DELAY is 332 * reasonably correct). It could get 333 * too low a delay (too high a freq.) 334 * if the CPU is slow executing the 335 * loop for some reason (an NMI, for 336 * example). For this reason we will 337 * if multiple measurements are to be 338 * performed trust the higher delay 339 * (lower frequency returned). 340 */ 341 OUTW(np, nc_sien, 0); /* mask all scsi interrupts */ 342 INW(np, nc_sist); /* clear pending scsi interrupt */ 343 OUTB(np, nc_dien, 0); /* mask all dma interrupts */ 344 INW(np, nc_sist); /* another one, just to be sure :) */ 345 /* 346 * The C1010-33 core does not report GEN in SIST, 347 * if this interrupt is masked in SIEN. 348 * I don't know yet if the C1010-66 behaves the same way. 349 */ 350 if (np->features & FE_C10) { 351 OUTW(np, nc_sien, GEN); 352 OUTB(np, nc_istat1, SIRQD); 353 } 354 OUTB(np, nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 355 OUTB(np, nc_stime1, 0); /* disable general purpose timer */ 356 OUTB(np, nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 357 while (!(INW(np, nc_sist) & GEN) && ms++ < 100000) 358 udelay(1000/4); /* count in 1/4 of ms */ 359 OUTB(np, nc_stime1, 0); /* disable general purpose timer */ 360 /* 361 * Undo C1010-33 specific settings. 362 */ 363 if (np->features & FE_C10) { 364 OUTW(np, nc_sien, 0); 365 OUTB(np, nc_istat1, 0); 366 } 367 /* 368 * set prescaler to divide by whatever 0 means 369 * 0 ought to choose divide by 2, but appears 370 * to set divide by 3.5 mode in my 53c810 ... 371 */ 372 OUTB(np, nc_scntl3, 0); 373 374 /* 375 * adjust for prescaler, and convert into KHz 376 */ 377 f = ms ? ((1 << gen) * (4340*4)) / ms : 0; 378 379 /* 380 * The C1010-33 result is biased by a factor 381 * of 2/3 compared to earlier chips. 382 */ 383 if (np->features & FE_C10) 384 f = (f * 2) / 3; 385 386 if (sym_verbose >= 2) 387 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 388 sym_name(np), gen, ms/4, f); 389 390 return f; 391 } 392 393 static unsigned sym_getfreq (struct sym_hcb *np) 394 { 395 u_int f1, f2; 396 int gen = 8; 397 398 getfreq (np, gen); /* throw away first result */ 399 f1 = getfreq (np, gen); 400 f2 = getfreq (np, gen); 401 if (f1 > f2) f1 = f2; /* trust lower result */ 402 return f1; 403 } 404 405 /* 406 * Get/probe chip SCSI clock frequency 407 */ 408 static void sym_getclock (struct sym_hcb *np, int mult) 409 { 410 unsigned char scntl3 = np->sv_scntl3; 411 unsigned char stest1 = np->sv_stest1; 412 unsigned f1; 413 414 np->multiplier = 1; 415 f1 = 40000; 416 /* 417 * True with 875/895/896/895A with clock multiplier selected 418 */ 419 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 420 if (sym_verbose >= 2) 421 printf ("%s: clock multiplier found\n", sym_name(np)); 422 np->multiplier = mult; 423 } 424 425 /* 426 * If multiplier not found or scntl3 not 7,5,3, 427 * reset chip and get frequency from general purpose timer. 428 * Otherwise trust scntl3 BIOS setting. 429 */ 430 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 431 OUTB(np, nc_stest1, 0); /* make sure doubler is OFF */ 432 f1 = sym_getfreq (np); 433 434 if (sym_verbose) 435 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 436 437 if (f1 < 45000) f1 = 40000; 438 else if (f1 < 55000) f1 = 50000; 439 else f1 = 80000; 440 441 if (f1 < 80000 && mult > 1) { 442 if (sym_verbose >= 2) 443 printf ("%s: clock multiplier assumed\n", 444 sym_name(np)); 445 np->multiplier = mult; 446 } 447 } else { 448 if ((scntl3 & 7) == 3) f1 = 40000; 449 else if ((scntl3 & 7) == 5) f1 = 80000; 450 else f1 = 160000; 451 452 f1 /= np->multiplier; 453 } 454 455 /* 456 * Compute controller synchronous parameters. 457 */ 458 f1 *= np->multiplier; 459 np->clock_khz = f1; 460 } 461 462 /* 463 * Get/probe PCI clock frequency 464 */ 465 static int sym_getpciclock (struct sym_hcb *np) 466 { 467 int f = 0; 468 469 /* 470 * For now, we only need to know about the actual 471 * PCI BUS clock frequency for C1010-66 chips. 472 */ 473 #if 1 474 if (np->features & FE_66MHZ) { 475 #else 476 if (1) { 477 #endif 478 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 479 f = sym_getfreq(np); 480 OUTB(np, nc_stest1, 0); 481 } 482 np->pciclk_khz = f; 483 484 return f; 485 } 486 487 /* 488 * SYMBIOS chip clock divisor table. 489 * 490 * Divisors are multiplied by 10,000,000 in order to make 491 * calculations more simple. 492 */ 493 #define _5M 5000000 494 static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 495 496 /* 497 * Get clock factor and sync divisor for a given 498 * synchronous factor period. 499 */ 500 static int 501 sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 502 { 503 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 504 int div = np->clock_divn; /* Number of divisors supported */ 505 u32 fak; /* Sync factor in sxfer */ 506 u32 per; /* Period in tenths of ns */ 507 u32 kpc; /* (per * clk) */ 508 int ret; 509 510 /* 511 * Compute the synchronous period in tenths of nano-seconds 512 */ 513 if (dt && sfac <= 9) per = 125; 514 else if (sfac <= 10) per = 250; 515 else if (sfac == 11) per = 303; 516 else if (sfac == 12) per = 500; 517 else per = 40 * sfac; 518 ret = per; 519 520 kpc = per * clk; 521 if (dt) 522 kpc <<= 1; 523 524 /* 525 * For earliest C10 revision 0, we cannot use extra 526 * clocks for the setting of the SCSI clocking. 527 * Note that this limits the lowest sync data transfer 528 * to 5 Mega-transfers per second and may result in 529 * using higher clock divisors. 530 */ 531 #if 1 532 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 533 /* 534 * Look for the lowest clock divisor that allows an 535 * output speed not faster than the period. 536 */ 537 while (div > 0) { 538 --div; 539 if (kpc > (div_10M[div] << 2)) { 540 ++div; 541 break; 542 } 543 } 544 fak = 0; /* No extra clocks */ 545 if (div == np->clock_divn) { /* Are we too fast ? */ 546 ret = -1; 547 } 548 *divp = div; 549 *fakp = fak; 550 return ret; 551 } 552 #endif 553 554 /* 555 * Look for the greatest clock divisor that allows an 556 * input speed faster than the period. 557 */ 558 while (div-- > 0) 559 if (kpc >= (div_10M[div] << 2)) break; 560 561 /* 562 * Calculate the lowest clock factor that allows an output 563 * speed not faster than the period, and the max output speed. 564 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 565 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 566 */ 567 if (dt) { 568 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 569 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 570 } else { 571 fak = (kpc - 1) / div_10M[div] + 1 - 4; 572 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 573 } 574 575 /* 576 * Check against our hardware limits, or bugs :). 577 */ 578 if (fak > 2) { 579 fak = 2; 580 ret = -1; 581 } 582 583 /* 584 * Compute and return sync parameters. 585 */ 586 *divp = div; 587 *fakp = fak; 588 589 return ret; 590 } 591 592 /* 593 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 594 * 128 transfers. All chips support at least 16 transfers 595 * bursts. The 825A, 875 and 895 chips support bursts of up 596 * to 128 transfers and the 895A and 896 support bursts of up 597 * to 64 transfers. All other chips support up to 16 598 * transfers bursts. 599 * 600 * For PCI 32 bit data transfers each transfer is a DWORD. 601 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 602 * 603 * We use log base 2 (burst length) as internal code, with 604 * value 0 meaning "burst disabled". 605 */ 606 607 /* 608 * Burst length from burst code. 609 */ 610 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 611 612 /* 613 * Burst code from io register bits. 614 */ 615 #define burst_code(dmode, ctest4, ctest5) \ 616 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 617 618 /* 619 * Set initial io register bits from burst code. 620 */ 621 static __inline void sym_init_burst(struct sym_hcb *np, u_char bc) 622 { 623 np->rv_ctest4 &= ~0x80; 624 np->rv_dmode &= ~(0x3 << 6); 625 np->rv_ctest5 &= ~0x4; 626 627 if (!bc) { 628 np->rv_ctest4 |= 0x80; 629 } 630 else { 631 --bc; 632 np->rv_dmode |= ((bc & 0x3) << 6); 633 np->rv_ctest5 |= (bc & 0x4); 634 } 635 } 636 637 638 /* 639 * Print out the list of targets that have some flag disabled by user. 640 */ 641 static void sym_print_targets_flag(struct sym_hcb *np, int mask, char *msg) 642 { 643 int cnt; 644 int i; 645 646 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 647 if (i == np->myaddr) 648 continue; 649 if (np->target[i].usrflags & mask) { 650 if (!cnt++) 651 printf("%s: %s disabled for targets", 652 sym_name(np), msg); 653 printf(" %d", i); 654 } 655 } 656 if (cnt) 657 printf(".\n"); 658 } 659 660 /* 661 * Save initial settings of some IO registers. 662 * Assumed to have been set by BIOS. 663 * We cannot reset the chip prior to reading the 664 * IO registers, since informations will be lost. 665 * Since the SCRIPTS processor may be running, this 666 * is not safe on paper, but it seems to work quite 667 * well. :) 668 */ 669 static void sym_save_initial_setting (struct sym_hcb *np) 670 { 671 np->sv_scntl0 = INB(np, nc_scntl0) & 0x0a; 672 np->sv_scntl3 = INB(np, nc_scntl3) & 0x07; 673 np->sv_dmode = INB(np, nc_dmode) & 0xce; 674 np->sv_dcntl = INB(np, nc_dcntl) & 0xa8; 675 np->sv_ctest3 = INB(np, nc_ctest3) & 0x01; 676 np->sv_ctest4 = INB(np, nc_ctest4) & 0x80; 677 np->sv_gpcntl = INB(np, nc_gpcntl); 678 np->sv_stest1 = INB(np, nc_stest1); 679 np->sv_stest2 = INB(np, nc_stest2) & 0x20; 680 np->sv_stest4 = INB(np, nc_stest4); 681 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 682 np->sv_scntl4 = INB(np, nc_scntl4); 683 np->sv_ctest5 = INB(np, nc_ctest5) & 0x04; 684 } 685 else 686 np->sv_ctest5 = INB(np, nc_ctest5) & 0x24; 687 } 688 689 /* 690 * Prepare io register values used by sym_start_up() 691 * according to selected and supported features. 692 */ 693 static int sym_prepare_setting(struct Scsi_Host *shost, struct sym_hcb *np, struct sym_nvram *nvram) 694 { 695 u_char burst_max; 696 u32 period; 697 int i; 698 699 /* 700 * Wide ? 701 */ 702 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 703 704 /* 705 * Guess the frequency of the chip's clock. 706 */ 707 if (np->features & (FE_ULTRA3 | FE_ULTRA2)) 708 np->clock_khz = 160000; 709 else if (np->features & FE_ULTRA) 710 np->clock_khz = 80000; 711 else 712 np->clock_khz = 40000; 713 714 /* 715 * Get the clock multiplier factor. 716 */ 717 if (np->features & FE_QUAD) 718 np->multiplier = 4; 719 else if (np->features & FE_DBLR) 720 np->multiplier = 2; 721 else 722 np->multiplier = 1; 723 724 /* 725 * Measure SCSI clock frequency for chips 726 * it may vary from assumed one. 727 */ 728 if (np->features & FE_VARCLK) 729 sym_getclock(np, np->multiplier); 730 731 /* 732 * Divisor to be used for async (timer pre-scaler). 733 */ 734 i = np->clock_divn - 1; 735 while (--i >= 0) { 736 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 737 ++i; 738 break; 739 } 740 } 741 np->rv_scntl3 = i+1; 742 743 /* 744 * The C1010 uses hardwired divisors for async. 745 * So, we just throw away, the async. divisor.:-) 746 */ 747 if (np->features & FE_C10) 748 np->rv_scntl3 = 0; 749 750 /* 751 * Minimum synchronous period factor supported by the chip. 752 * Btw, 'period' is in tenths of nanoseconds. 753 */ 754 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 755 756 if (period <= 250) np->minsync = 10; 757 else if (period <= 303) np->minsync = 11; 758 else if (period <= 500) np->minsync = 12; 759 else np->minsync = (period + 40 - 1) / 40; 760 761 /* 762 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 763 */ 764 if (np->minsync < 25 && 765 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 766 np->minsync = 25; 767 else if (np->minsync < 12 && 768 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 769 np->minsync = 12; 770 771 /* 772 * Maximum synchronous period factor supported by the chip. 773 */ 774 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 775 np->maxsync = period > 2540 ? 254 : period / 10; 776 777 /* 778 * If chip is a C1010, guess the sync limits in DT mode. 779 */ 780 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 781 if (np->clock_khz == 160000) { 782 np->minsync_dt = 9; 783 np->maxsync_dt = 50; 784 np->maxoffs_dt = nvram->type ? 62 : 31; 785 } 786 } 787 788 /* 789 * 64 bit addressing (895A/896/1010) ? 790 */ 791 if (np->features & FE_DAC) { 792 #if SYM_CONF_DMA_ADDRESSING_MODE == 0 793 np->rv_ccntl1 |= (DDAC); 794 #elif SYM_CONF_DMA_ADDRESSING_MODE == 1 795 if (!np->use_dac) 796 np->rv_ccntl1 |= (DDAC); 797 else 798 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 799 #elif SYM_CONF_DMA_ADDRESSING_MODE == 2 800 if (!np->use_dac) 801 np->rv_ccntl1 |= (DDAC); 802 else 803 np->rv_ccntl1 |= (0 | EXTIBMV); 804 #endif 805 } 806 807 /* 808 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 809 */ 810 if (np->features & FE_NOPM) 811 np->rv_ccntl0 |= (ENPMJ); 812 813 /* 814 * C1010-33 Errata: Part Number:609-039638 (rev. 1) is fixed. 815 * In dual channel mode, contention occurs if internal cycles 816 * are used. Disable internal cycles. 817 */ 818 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_33 && 819 np->revision_id < 0x1) 820 np->rv_ccntl0 |= DILS; 821 822 /* 823 * Select burst length (dwords) 824 */ 825 burst_max = SYM_SETUP_BURST_ORDER; 826 if (burst_max == 255) 827 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 828 np->sv_ctest5); 829 if (burst_max > 7) 830 burst_max = 7; 831 if (burst_max > np->maxburst) 832 burst_max = np->maxburst; 833 834 /* 835 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 836 * This chip and the 860 Rev 1 may wrongly use PCI cache line 837 * based transactions on LOAD/STORE instructions. So we have 838 * to prevent these chips from using such PCI transactions in 839 * this driver. The generic ncr driver that does not use 840 * LOAD/STORE instructions does not need this work-around. 841 */ 842 if ((np->device_id == PCI_DEVICE_ID_NCR_53C810 && 843 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 844 (np->device_id == PCI_DEVICE_ID_NCR_53C860 && 845 np->revision_id <= 0x1)) 846 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 847 848 /* 849 * Select all supported special features. 850 * If we are using on-board RAM for scripts, prefetch (PFEN) 851 * does not help, but burst op fetch (BOF) does. 852 * Disabling PFEN makes sure BOF will be used. 853 */ 854 if (np->features & FE_ERL) 855 np->rv_dmode |= ERL; /* Enable Read Line */ 856 if (np->features & FE_BOF) 857 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 858 if (np->features & FE_ERMP) 859 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 860 #if 1 861 if ((np->features & FE_PFEN) && !np->ram_ba) 862 #else 863 if (np->features & FE_PFEN) 864 #endif 865 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 866 if (np->features & FE_CLSE) 867 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 868 if (np->features & FE_WRIE) 869 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 870 if (np->features & FE_DFS) 871 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 872 873 /* 874 * Select some other 875 */ 876 np->rv_ctest4 |= MPEE; /* Master parity checking */ 877 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 878 879 /* 880 * Get parity checking, host ID and verbose mode from NVRAM 881 */ 882 np->myaddr = 255; 883 sym_nvram_setup_host(shost, np, nvram); 884 885 /* 886 * Get SCSI addr of host adapter (set by bios?). 887 */ 888 if (np->myaddr == 255) { 889 np->myaddr = INB(np, nc_scid) & 0x07; 890 if (!np->myaddr) 891 np->myaddr = SYM_SETUP_HOST_ID; 892 } 893 894 /* 895 * Prepare initial io register bits for burst length 896 */ 897 sym_init_burst(np, burst_max); 898 899 /* 900 * Set SCSI BUS mode. 901 * - LVD capable chips (895/895A/896/1010) report the 902 * current BUS mode through the STEST4 IO register. 903 * - For previous generation chips (825/825A/875), 904 * user has to tell us how to check against HVD, 905 * since a 100% safe algorithm is not possible. 906 */ 907 np->scsi_mode = SMODE_SE; 908 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 909 np->scsi_mode = (np->sv_stest4 & SMODE); 910 else if (np->features & FE_DIFF) { 911 if (SYM_SETUP_SCSI_DIFF == 1) { 912 if (np->sv_scntl3) { 913 if (np->sv_stest2 & 0x20) 914 np->scsi_mode = SMODE_HVD; 915 } 916 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 917 if (!(INB(np, nc_gpreg) & 0x08)) 918 np->scsi_mode = SMODE_HVD; 919 } 920 } 921 else if (SYM_SETUP_SCSI_DIFF == 2) 922 np->scsi_mode = SMODE_HVD; 923 } 924 if (np->scsi_mode == SMODE_HVD) 925 np->rv_stest2 |= 0x20; 926 927 /* 928 * Set LED support from SCRIPTS. 929 * Ignore this feature for boards known to use a 930 * specific GPIO wiring and for the 895A, 896 931 * and 1010 that drive the LED directly. 932 */ 933 if ((SYM_SETUP_SCSI_LED || 934 (nvram->type == SYM_SYMBIOS_NVRAM || 935 (nvram->type == SYM_TEKRAM_NVRAM && 936 np->device_id == PCI_DEVICE_ID_NCR_53C895))) && 937 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 938 np->features |= FE_LED0; 939 940 /* 941 * Set irq mode. 942 */ 943 switch(SYM_SETUP_IRQ_MODE & 3) { 944 case 2: 945 np->rv_dcntl |= IRQM; 946 break; 947 case 1: 948 np->rv_dcntl |= (np->sv_dcntl & IRQM); 949 break; 950 default: 951 break; 952 } 953 954 /* 955 * Configure targets according to driver setup. 956 * If NVRAM present get targets setup from NVRAM. 957 */ 958 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 959 struct sym_tcb *tp = &np->target[i]; 960 961 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 962 tp->usrtags = SYM_SETUP_MAX_TAG; 963 964 sym_nvram_setup_target(np, i, nvram); 965 966 if (!tp->usrtags) 967 tp->usrflags &= ~SYM_TAGS_ENABLED; 968 } 969 970 /* 971 * Let user know about the settings. 972 */ 973 printf("%s: %s, ID %d, Fast-%d, %s, %s\n", sym_name(np), 974 sym_nvram_type(nvram), np->myaddr, 975 (np->features & FE_ULTRA3) ? 80 : 976 (np->features & FE_ULTRA2) ? 40 : 977 (np->features & FE_ULTRA) ? 20 : 10, 978 sym_scsi_bus_mode(np->scsi_mode), 979 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 980 /* 981 * Tell him more on demand. 982 */ 983 if (sym_verbose) { 984 printf("%s: %s IRQ line driver%s\n", 985 sym_name(np), 986 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 987 np->ram_ba ? ", using on-chip SRAM" : ""); 988 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 989 if (np->features & FE_NOPM) 990 printf("%s: handling phase mismatch from SCRIPTS.\n", 991 sym_name(np)); 992 } 993 /* 994 * And still more. 995 */ 996 if (sym_verbose >= 2) { 997 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 998 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 999 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 1000 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 1001 1002 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 1003 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 1004 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 1005 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 1006 } 1007 /* 1008 * Let user be aware of targets that have some disable flags set. 1009 */ 1010 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 1011 if (sym_verbose) 1012 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 1013 "SCAN FOR LUNS"); 1014 1015 return 0; 1016 } 1017 1018 /* 1019 * Test the pci bus snoop logic :-( 1020 * 1021 * Has to be called with interrupts disabled. 1022 */ 1023 #ifndef CONFIG_SCSI_SYM53C8XX_IOMAPPED 1024 static int sym_regtest (struct sym_hcb *np) 1025 { 1026 register volatile u32 data; 1027 /* 1028 * chip registers may NOT be cached. 1029 * write 0xffffffff to a read only register area, 1030 * and try to read it back. 1031 */ 1032 data = 0xffffffff; 1033 OUTL(np, nc_dstat, data); 1034 data = INL(np, nc_dstat); 1035 #if 1 1036 if (data == 0xffffffff) { 1037 #else 1038 if ((data & 0xe2f0fffd) != 0x02000080) { 1039 #endif 1040 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 1041 (unsigned) data); 1042 return (0x10); 1043 } 1044 return (0); 1045 } 1046 #endif 1047 1048 static int sym_snooptest (struct sym_hcb *np) 1049 { 1050 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 1051 int i, err=0; 1052 #ifndef CONFIG_SCSI_SYM53C8XX_IOMAPPED 1053 err |= sym_regtest (np); 1054 if (err) return (err); 1055 #endif 1056 restart_test: 1057 /* 1058 * Enable Master Parity Checking as we intend 1059 * to enable it for normal operations. 1060 */ 1061 OUTB(np, nc_ctest4, (np->rv_ctest4 & MPEE)); 1062 /* 1063 * init 1064 */ 1065 pc = SCRIPTZ_BA(np, snooptest); 1066 host_wr = 1; 1067 sym_wr = 2; 1068 /* 1069 * Set memory and register. 1070 */ 1071 np->scratch = cpu_to_scr(host_wr); 1072 OUTL(np, nc_temp, sym_wr); 1073 /* 1074 * Start script (exchange values) 1075 */ 1076 OUTL(np, nc_dsa, np->hcb_ba); 1077 OUTL_DSP(np, pc); 1078 /* 1079 * Wait 'til done (with timeout) 1080 */ 1081 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 1082 if (INB(np, nc_istat) & (INTF|SIP|DIP)) 1083 break; 1084 if (i>=SYM_SNOOP_TIMEOUT) { 1085 printf ("CACHE TEST FAILED: timeout.\n"); 1086 return (0x20); 1087 } 1088 /* 1089 * Check for fatal DMA errors. 1090 */ 1091 dstat = INB(np, nc_dstat); 1092 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 1093 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 1094 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 1095 "DISABLING MASTER DATA PARITY CHECKING.\n", 1096 sym_name(np)); 1097 np->rv_ctest4 &= ~MPEE; 1098 goto restart_test; 1099 } 1100 #endif 1101 if (dstat & (MDPE|BF|IID)) { 1102 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 1103 return (0x80); 1104 } 1105 /* 1106 * Save termination position. 1107 */ 1108 pc = INL(np, nc_dsp); 1109 /* 1110 * Read memory and register. 1111 */ 1112 host_rd = scr_to_cpu(np->scratch); 1113 sym_rd = INL(np, nc_scratcha); 1114 sym_bk = INL(np, nc_temp); 1115 /* 1116 * Check termination position. 1117 */ 1118 if (pc != SCRIPTZ_BA(np, snoopend)+8) { 1119 printf ("CACHE TEST FAILED: script execution failed.\n"); 1120 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 1121 (u_long) SCRIPTZ_BA(np, snooptest), (u_long) pc, 1122 (u_long) SCRIPTZ_BA(np, snoopend) +8); 1123 return (0x40); 1124 } 1125 /* 1126 * Show results. 1127 */ 1128 if (host_wr != sym_rd) { 1129 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 1130 (int) host_wr, (int) sym_rd); 1131 err |= 1; 1132 } 1133 if (host_rd != sym_wr) { 1134 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 1135 (int) sym_wr, (int) host_rd); 1136 err |= 2; 1137 } 1138 if (sym_bk != sym_wr) { 1139 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 1140 (int) sym_wr, (int) sym_bk); 1141 err |= 4; 1142 } 1143 1144 return (err); 1145 } 1146 1147 /* 1148 * log message for real hard errors 1149 * 1150 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sx/s3/s4) @ name (dsp:dbc). 1151 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 1152 * 1153 * exception register: 1154 * ds: dstat 1155 * si: sist 1156 * 1157 * SCSI bus lines: 1158 * so: control lines as driven by chip. 1159 * si: control lines as seen by chip. 1160 * sd: scsi data lines as seen by chip. 1161 * 1162 * wide/fastmode: 1163 * sx: sxfer (see the manual) 1164 * s3: scntl3 (see the manual) 1165 * s4: scntl4 (see the manual) 1166 * 1167 * current script command: 1168 * dsp: script address (relative to start of script). 1169 * dbc: first word of script command. 1170 * 1171 * First 24 register of the chip: 1172 * r0..rf 1173 */ 1174 static void sym_log_hard_error(struct sym_hcb *np, u_short sist, u_char dstat) 1175 { 1176 u32 dsp; 1177 int script_ofs; 1178 int script_size; 1179 char *script_name; 1180 u_char *script_base; 1181 int i; 1182 1183 dsp = INL(np, nc_dsp); 1184 1185 if (dsp > np->scripta_ba && 1186 dsp <= np->scripta_ba + np->scripta_sz) { 1187 script_ofs = dsp - np->scripta_ba; 1188 script_size = np->scripta_sz; 1189 script_base = (u_char *) np->scripta0; 1190 script_name = "scripta"; 1191 } 1192 else if (np->scriptb_ba < dsp && 1193 dsp <= np->scriptb_ba + np->scriptb_sz) { 1194 script_ofs = dsp - np->scriptb_ba; 1195 script_size = np->scriptb_sz; 1196 script_base = (u_char *) np->scriptb0; 1197 script_name = "scriptb"; 1198 } else { 1199 script_ofs = dsp; 1200 script_size = 0; 1201 script_base = NULL; 1202 script_name = "mem"; 1203 } 1204 1205 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x/%x) @ (%s %x:%08x).\n", 1206 sym_name(np), (unsigned)INB(np, nc_sdid)&0x0f, dstat, sist, 1207 (unsigned)INB(np, nc_socl), (unsigned)INB(np, nc_sbcl), 1208 (unsigned)INB(np, nc_sbdl), (unsigned)INB(np, nc_sxfer), 1209 (unsigned)INB(np, nc_scntl3), 1210 (np->features & FE_C10) ? (unsigned)INB(np, nc_scntl4) : 0, 1211 script_name, script_ofs, (unsigned)INL(np, nc_dbc)); 1212 1213 if (((script_ofs & 3) == 0) && 1214 (unsigned)script_ofs < script_size) { 1215 printf ("%s: script cmd = %08x\n", sym_name(np), 1216 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 1217 } 1218 1219 printf ("%s: regdump:", sym_name(np)); 1220 for (i=0; i<24;i++) 1221 printf (" %02x", (unsigned)INB_OFF(np, i)); 1222 printf (".\n"); 1223 1224 /* 1225 * PCI BUS error. 1226 */ 1227 if (dstat & (MDPE|BF)) 1228 sym_log_bus_error(np); 1229 } 1230 1231 static struct sym_chip sym_dev_table[] = { 1232 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, 64, 1233 FE_ERL} 1234 , 1235 #ifdef SYM_DEBUG_GENERIC_SUPPORT 1236 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1, 1237 FE_BOF} 1238 , 1239 #else 1240 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1, 1241 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 1242 , 1243 #endif 1244 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, 64, 1245 FE_BOF|FE_ERL} 1246 , 1247 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 6, 8, 4, 64, 1248 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 1249 , 1250 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, 2, 1251 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 1252 , 1253 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, 1, 1254 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 1255 , 1256 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, 2, 1257 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1258 FE_RAM|FE_DIFF|FE_VARCLK} 1259 , 1260 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, 2, 1261 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1262 FE_RAM|FE_DIFF|FE_VARCLK} 1263 , 1264 {PCI_DEVICE_ID_NCR_53C875J, 0xff, "875J", 6, 16, 5, 2, 1265 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1266 FE_RAM|FE_DIFF|FE_VARCLK} 1267 , 1268 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, 2, 1269 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1270 FE_RAM|FE_DIFF|FE_VARCLK} 1271 , 1272 #ifdef SYM_DEBUG_GENERIC_SUPPORT 1273 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2, 1274 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 1275 FE_RAM|FE_LCKFRQ} 1276 , 1277 #else 1278 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2, 1279 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1280 FE_RAM|FE_LCKFRQ} 1281 , 1282 #endif 1283 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, 4, 1284 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1285 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1286 , 1287 {PCI_DEVICE_ID_LSI_53C895A, 0xff, "895a", 6, 31, 7, 4, 1288 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1289 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1290 , 1291 {PCI_DEVICE_ID_LSI_53C875A, 0xff, "875a", 6, 31, 7, 4, 1292 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1293 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1294 , 1295 {PCI_DEVICE_ID_LSI_53C1010_33, 0x00, "1010-33", 6, 31, 7, 8, 1296 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1297 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 1298 FE_C10} 1299 , 1300 {PCI_DEVICE_ID_LSI_53C1010_33, 0xff, "1010-33", 6, 31, 7, 8, 1301 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1302 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 1303 FE_C10|FE_U3EN} 1304 , 1305 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 31, 7, 8, 1306 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1307 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 1308 FE_C10|FE_U3EN} 1309 , 1310 {PCI_DEVICE_ID_LSI_53C1510, 0xff, "1510d", 6, 31, 7, 4, 1311 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1312 FE_RAM|FE_IO256|FE_LEDC} 1313 }; 1314 1315 #define sym_num_devs \ 1316 (sizeof(sym_dev_table) / sizeof(sym_dev_table[0])) 1317 1318 /* 1319 * Look up the chip table. 1320 * 1321 * Return a pointer to the chip entry if found, 1322 * zero otherwise. 1323 */ 1324 struct sym_chip * 1325 sym_lookup_chip_table (u_short device_id, u_char revision) 1326 { 1327 struct sym_chip *chip; 1328 int i; 1329 1330 for (i = 0; i < sym_num_devs; i++) { 1331 chip = &sym_dev_table[i]; 1332 if (device_id != chip->device_id) 1333 continue; 1334 if (revision > chip->revision_id) 1335 continue; 1336 return chip; 1337 } 1338 1339 return NULL; 1340 } 1341 1342 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1343 /* 1344 * Lookup the 64 bit DMA segments map. 1345 * This is only used if the direct mapping 1346 * has been unsuccessful. 1347 */ 1348 int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s) 1349 { 1350 int i; 1351 1352 if (!np->use_dac) 1353 goto weird; 1354 1355 /* Look up existing mappings */ 1356 for (i = SYM_DMAP_SIZE-1; i > 0; i--) { 1357 if (h == np->dmap_bah[i]) 1358 return i; 1359 } 1360 /* If direct mapping is free, get it */ 1361 if (!np->dmap_bah[s]) 1362 goto new; 1363 /* Collision -> lookup free mappings */ 1364 for (s = SYM_DMAP_SIZE-1; s > 0; s--) { 1365 if (!np->dmap_bah[s]) 1366 goto new; 1367 } 1368 weird: 1369 panic("sym: ran out of 64 bit DMA segment registers"); 1370 return -1; 1371 new: 1372 np->dmap_bah[s] = h; 1373 np->dmap_dirty = 1; 1374 return s; 1375 } 1376 1377 /* 1378 * Update IO registers scratch C..R so they will be 1379 * in sync. with queued CCB expectations. 1380 */ 1381 static void sym_update_dmap_regs(struct sym_hcb *np) 1382 { 1383 int o, i; 1384 1385 if (!np->dmap_dirty) 1386 return; 1387 o = offsetof(struct sym_reg, nc_scrx[0]); 1388 for (i = 0; i < SYM_DMAP_SIZE; i++) { 1389 OUTL_OFF(np, o, np->dmap_bah[i]); 1390 o += 4; 1391 } 1392 np->dmap_dirty = 0; 1393 } 1394 #endif 1395 1396 /* Enforce all the fiddly SPI rules and the chip limitations */ 1397 static void sym_check_goals(struct sym_hcb *np, struct scsi_target *starget, 1398 struct sym_trans *goal) 1399 { 1400 if (!spi_support_wide(starget)) 1401 goal->width = 0; 1402 1403 if (!spi_support_sync(starget)) { 1404 goal->iu = 0; 1405 goal->dt = 0; 1406 goal->qas = 0; 1407 goal->period = 0; 1408 goal->offset = 0; 1409 return; 1410 } 1411 1412 if (spi_support_dt(starget)) { 1413 if (spi_support_dt_only(starget)) 1414 goal->dt = 1; 1415 1416 if (goal->offset == 0) 1417 goal->dt = 0; 1418 } else { 1419 goal->dt = 0; 1420 } 1421 1422 /* Some targets fail to properly negotiate DT in SE mode */ 1423 if ((np->scsi_mode != SMODE_LVD) || !(np->features & FE_U3EN)) 1424 goal->dt = 0; 1425 1426 if (goal->dt) { 1427 /* all DT transfers must be wide */ 1428 goal->width = 1; 1429 if (goal->offset > np->maxoffs_dt) 1430 goal->offset = np->maxoffs_dt; 1431 if (goal->period < np->minsync_dt) 1432 goal->period = np->minsync_dt; 1433 if (goal->period > np->maxsync_dt) 1434 goal->period = np->maxsync_dt; 1435 } else { 1436 goal->iu = goal->qas = 0; 1437 if (goal->offset > np->maxoffs) 1438 goal->offset = np->maxoffs; 1439 if (goal->period < np->minsync) 1440 goal->period = np->minsync; 1441 if (goal->period > np->maxsync) 1442 goal->period = np->maxsync; 1443 } 1444 } 1445 1446 /* 1447 * Prepare the next negotiation message if needed. 1448 * 1449 * Fill in the part of message buffer that contains the 1450 * negotiation and the nego_status field of the CCB. 1451 * Returns the size of the message in bytes. 1452 */ 1453 static int sym_prepare_nego(struct sym_hcb *np, struct sym_ccb *cp, u_char *msgptr) 1454 { 1455 struct sym_tcb *tp = &np->target[cp->target]; 1456 struct scsi_target *starget = tp->starget; 1457 struct sym_trans *goal = &tp->tgoal; 1458 int msglen = 0; 1459 int nego; 1460 1461 sym_check_goals(np, starget, goal); 1462 1463 /* 1464 * Many devices implement PPR in a buggy way, so only use it if we 1465 * really want to. 1466 */ 1467 if (goal->iu || goal->dt || goal->qas || (goal->period < 0xa)) { 1468 nego = NS_PPR; 1469 } else if (spi_width(starget) != goal->width) { 1470 nego = NS_WIDE; 1471 } else if (spi_period(starget) != goal->period || 1472 spi_offset(starget) != goal->offset) { 1473 nego = NS_SYNC; 1474 } else { 1475 goal->check_nego = 0; 1476 nego = 0; 1477 } 1478 1479 switch (nego) { 1480 case NS_SYNC: 1481 msgptr[msglen++] = M_EXTENDED; 1482 msgptr[msglen++] = 3; 1483 msgptr[msglen++] = M_X_SYNC_REQ; 1484 msgptr[msglen++] = goal->period; 1485 msgptr[msglen++] = goal->offset; 1486 break; 1487 case NS_WIDE: 1488 msgptr[msglen++] = M_EXTENDED; 1489 msgptr[msglen++] = 2; 1490 msgptr[msglen++] = M_X_WIDE_REQ; 1491 msgptr[msglen++] = goal->width; 1492 break; 1493 case NS_PPR: 1494 msgptr[msglen++] = M_EXTENDED; 1495 msgptr[msglen++] = 6; 1496 msgptr[msglen++] = M_X_PPR_REQ; 1497 msgptr[msglen++] = goal->period; 1498 msgptr[msglen++] = 0; 1499 msgptr[msglen++] = goal->offset; 1500 msgptr[msglen++] = goal->width; 1501 msgptr[msglen++] = (goal->iu ? PPR_OPT_IU : 0) | 1502 (goal->dt ? PPR_OPT_DT : 0) | 1503 (goal->qas ? PPR_OPT_QAS : 0); 1504 break; 1505 } 1506 1507 cp->nego_status = nego; 1508 1509 if (nego) { 1510 tp->nego_cp = cp; /* Keep track a nego will be performed */ 1511 if (DEBUG_FLAGS & DEBUG_NEGO) { 1512 sym_print_nego_msg(np, cp->target, 1513 nego == NS_SYNC ? "sync msgout" : 1514 nego == NS_WIDE ? "wide msgout" : 1515 "ppr msgout", msgptr); 1516 } 1517 } 1518 1519 return msglen; 1520 } 1521 1522 /* 1523 * Insert a job into the start queue. 1524 */ 1525 void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp) 1526 { 1527 u_short qidx; 1528 1529 #ifdef SYM_CONF_IARB_SUPPORT 1530 /* 1531 * If the previously queued CCB is not yet done, 1532 * set the IARB hint. The SCRIPTS will go with IARB 1533 * for this job when starting the previous one. 1534 * We leave devices a chance to win arbitration by 1535 * not using more than 'iarb_max' consecutive 1536 * immediate arbitrations. 1537 */ 1538 if (np->last_cp && np->iarb_count < np->iarb_max) { 1539 np->last_cp->host_flags |= HF_HINT_IARB; 1540 ++np->iarb_count; 1541 } 1542 else 1543 np->iarb_count = 0; 1544 np->last_cp = cp; 1545 #endif 1546 1547 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1548 /* 1549 * Make SCRIPTS aware of the 64 bit DMA 1550 * segment registers not being up-to-date. 1551 */ 1552 if (np->dmap_dirty) 1553 cp->host_xflags |= HX_DMAP_DIRTY; 1554 #endif 1555 1556 /* 1557 * Insert first the idle task and then our job. 1558 * The MBs should ensure proper ordering. 1559 */ 1560 qidx = np->squeueput + 2; 1561 if (qidx >= MAX_QUEUE*2) qidx = 0; 1562 1563 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 1564 MEMORY_WRITE_BARRIER(); 1565 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 1566 1567 np->squeueput = qidx; 1568 1569 if (DEBUG_FLAGS & DEBUG_QUEUE) 1570 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 1571 1572 /* 1573 * Script processor may be waiting for reselect. 1574 * Wake it up. 1575 */ 1576 MEMORY_WRITE_BARRIER(); 1577 OUTB(np, nc_istat, SIGP|np->istat_sem); 1578 } 1579 1580 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 1581 /* 1582 * Start next ready-to-start CCBs. 1583 */ 1584 void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn) 1585 { 1586 SYM_QUEHEAD *qp; 1587 struct sym_ccb *cp; 1588 1589 /* 1590 * Paranoia, as usual. :-) 1591 */ 1592 assert(!lp->started_tags || !lp->started_no_tag); 1593 1594 /* 1595 * Try to start as many commands as asked by caller. 1596 * Prevent from having both tagged and untagged 1597 * commands queued to the device at the same time. 1598 */ 1599 while (maxn--) { 1600 qp = sym_remque_head(&lp->waiting_ccbq); 1601 if (!qp) 1602 break; 1603 cp = sym_que_entry(qp, struct sym_ccb, link2_ccbq); 1604 if (cp->tag != NO_TAG) { 1605 if (lp->started_no_tag || 1606 lp->started_tags >= lp->started_max) { 1607 sym_insque_head(qp, &lp->waiting_ccbq); 1608 break; 1609 } 1610 lp->itlq_tbl[cp->tag] = cpu_to_scr(cp->ccb_ba); 1611 lp->head.resel_sa = 1612 cpu_to_scr(SCRIPTA_BA(np, resel_tag)); 1613 ++lp->started_tags; 1614 } else { 1615 if (lp->started_no_tag || lp->started_tags) { 1616 sym_insque_head(qp, &lp->waiting_ccbq); 1617 break; 1618 } 1619 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 1620 lp->head.resel_sa = 1621 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag)); 1622 ++lp->started_no_tag; 1623 } 1624 cp->started = 1; 1625 sym_insque_tail(qp, &lp->started_ccbq); 1626 sym_put_start_queue(np, cp); 1627 } 1628 } 1629 #endif /* SYM_OPT_HANDLE_DEVICE_QUEUEING */ 1630 1631 /* 1632 * The chip may have completed jobs. Look at the DONE QUEUE. 1633 * 1634 * On paper, memory read barriers may be needed here to 1635 * prevent out of order LOADs by the CPU from having 1636 * prefetched stale data prior to DMA having occurred. 1637 */ 1638 static int sym_wakeup_done (struct sym_hcb *np) 1639 { 1640 struct sym_ccb *cp; 1641 int i, n; 1642 u32 dsa; 1643 1644 n = 0; 1645 i = np->dqueueget; 1646 1647 /* MEMORY_READ_BARRIER(); */ 1648 while (1) { 1649 dsa = scr_to_cpu(np->dqueue[i]); 1650 if (!dsa) 1651 break; 1652 np->dqueue[i] = 0; 1653 if ((i = i+2) >= MAX_QUEUE*2) 1654 i = 0; 1655 1656 cp = sym_ccb_from_dsa(np, dsa); 1657 if (cp) { 1658 MEMORY_READ_BARRIER(); 1659 sym_complete_ok (np, cp); 1660 ++n; 1661 } 1662 else 1663 printf ("%s: bad DSA (%x) in done queue.\n", 1664 sym_name(np), (u_int) dsa); 1665 } 1666 np->dqueueget = i; 1667 1668 return n; 1669 } 1670 1671 /* 1672 * Complete all CCBs queued to the COMP queue. 1673 * 1674 * These CCBs are assumed: 1675 * - Not to be referenced either by devices or 1676 * SCRIPTS-related queues and datas. 1677 * - To have to be completed with an error condition 1678 * or requeued. 1679 * 1680 * The device queue freeze count is incremented 1681 * for each CCB that does not prevent this. 1682 * This function is called when all CCBs involved 1683 * in error handling/recovery have been reaped. 1684 */ 1685 static void sym_flush_comp_queue(struct sym_hcb *np, int cam_status) 1686 { 1687 SYM_QUEHEAD *qp; 1688 struct sym_ccb *cp; 1689 1690 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) { 1691 struct scsi_cmnd *cmd; 1692 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 1693 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 1694 /* Leave quiet CCBs waiting for resources */ 1695 if (cp->host_status == HS_WAIT) 1696 continue; 1697 cmd = cp->cmd; 1698 if (cam_status) 1699 sym_set_cam_status(cmd, cam_status); 1700 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 1701 if (sym_get_cam_status(cmd) == DID_SOFT_ERROR) { 1702 struct sym_tcb *tp = &np->target[cp->target]; 1703 struct sym_lcb *lp = sym_lp(tp, cp->lun); 1704 if (lp) { 1705 sym_remque(&cp->link2_ccbq); 1706 sym_insque_tail(&cp->link2_ccbq, 1707 &lp->waiting_ccbq); 1708 if (cp->started) { 1709 if (cp->tag != NO_TAG) 1710 --lp->started_tags; 1711 else 1712 --lp->started_no_tag; 1713 } 1714 } 1715 cp->started = 0; 1716 continue; 1717 } 1718 #endif 1719 sym_free_ccb(np, cp); 1720 sym_xpt_done(np, cmd); 1721 } 1722 } 1723 1724 /* 1725 * Complete all active CCBs with error. 1726 * Used on CHIP/SCSI RESET. 1727 */ 1728 static void sym_flush_busy_queue (struct sym_hcb *np, int cam_status) 1729 { 1730 /* 1731 * Move all active CCBs to the COMP queue 1732 * and flush this queue. 1733 */ 1734 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 1735 sym_que_init(&np->busy_ccbq); 1736 sym_flush_comp_queue(np, cam_status); 1737 } 1738 1739 /* 1740 * Start chip. 1741 * 1742 * 'reason' means: 1743 * 0: initialisation. 1744 * 1: SCSI BUS RESET delivered or received. 1745 * 2: SCSI BUS MODE changed. 1746 */ 1747 void sym_start_up (struct sym_hcb *np, int reason) 1748 { 1749 int i; 1750 u32 phys; 1751 1752 /* 1753 * Reset chip if asked, otherwise just clear fifos. 1754 */ 1755 if (reason == 1) 1756 sym_soft_reset(np); 1757 else { 1758 OUTB(np, nc_stest3, TE|CSF); 1759 OUTONB(np, nc_ctest3, CLF); 1760 } 1761 1762 /* 1763 * Clear Start Queue 1764 */ 1765 phys = np->squeue_ba; 1766 for (i = 0; i < MAX_QUEUE*2; i += 2) { 1767 np->squeue[i] = cpu_to_scr(np->idletask_ba); 1768 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 1769 } 1770 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 1771 1772 /* 1773 * Start at first entry. 1774 */ 1775 np->squeueput = 0; 1776 1777 /* 1778 * Clear Done Queue 1779 */ 1780 phys = np->dqueue_ba; 1781 for (i = 0; i < MAX_QUEUE*2; i += 2) { 1782 np->dqueue[i] = 0; 1783 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 1784 } 1785 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 1786 1787 /* 1788 * Start at first entry. 1789 */ 1790 np->dqueueget = 0; 1791 1792 /* 1793 * Install patches in scripts. 1794 * This also let point to first position the start 1795 * and done queue pointers used from SCRIPTS. 1796 */ 1797 np->fw_patch(np); 1798 1799 /* 1800 * Wakeup all pending jobs. 1801 */ 1802 sym_flush_busy_queue(np, DID_RESET); 1803 1804 /* 1805 * Init chip. 1806 */ 1807 OUTB(np, nc_istat, 0x00); /* Remove Reset, abort */ 1808 INB(np, nc_mbox1); 1809 udelay(2000); /* The 895 needs time for the bus mode to settle */ 1810 1811 OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0); 1812 /* full arb., ena parity, par->ATN */ 1813 OUTB(np, nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 1814 1815 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 1816 1817 OUTB(np, nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 1818 OUTW(np, nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 1819 OUTB(np, nc_istat , SIGP ); /* Signal Process */ 1820 OUTB(np, nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 1821 OUTB(np, nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 1822 1823 OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 1824 OUTB(np, nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 1825 OUTB(np, nc_ctest4, np->rv_ctest4); /* Master parity checking */ 1826 1827 /* Extended Sreq/Sack filtering not supported on the C10 */ 1828 if (np->features & FE_C10) 1829 OUTB(np, nc_stest2, np->rv_stest2); 1830 else 1831 OUTB(np, nc_stest2, EXT|np->rv_stest2); 1832 1833 OUTB(np, nc_stest3, TE); /* TolerANT enable */ 1834 OUTB(np, nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 1835 1836 /* 1837 * For now, disable AIP generation on C1010-66. 1838 */ 1839 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_66) 1840 OUTB(np, nc_aipcntl1, DISAIP); 1841 1842 /* 1843 * C10101 rev. 0 errata. 1844 * Errant SGE's when in narrow. Write bits 4 & 5 of 1845 * STEST1 register to disable SGE. We probably should do 1846 * that from SCRIPTS for each selection/reselection, but 1847 * I just don't want. :) 1848 */ 1849 if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_33 && 1850 np->revision_id < 1) 1851 OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30); 1852 1853 /* 1854 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 1855 * Disable overlapped arbitration for some dual function devices, 1856 * regardless revision id (kind of post-chip-design feature. ;-)) 1857 */ 1858 if (np->device_id == PCI_DEVICE_ID_NCR_53C875) 1859 OUTB(np, nc_ctest0, (1<<5)); 1860 else if (np->device_id == PCI_DEVICE_ID_NCR_53C896) 1861 np->rv_ccntl0 |= DPR; 1862 1863 /* 1864 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 1865 * and/or hardware phase mismatch, since only such chips 1866 * seem to support those IO registers. 1867 */ 1868 if (np->features & (FE_DAC|FE_NOPM)) { 1869 OUTB(np, nc_ccntl0, np->rv_ccntl0); 1870 OUTB(np, nc_ccntl1, np->rv_ccntl1); 1871 } 1872 1873 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1874 /* 1875 * Set up scratch C and DRS IO registers to map the 32 bit 1876 * DMA address range our data structures are located in. 1877 */ 1878 if (np->use_dac) { 1879 np->dmap_bah[0] = 0; /* ??? */ 1880 OUTL(np, nc_scrx[0], np->dmap_bah[0]); 1881 OUTL(np, nc_drs, np->dmap_bah[0]); 1882 } 1883 #endif 1884 1885 /* 1886 * If phase mismatch handled by scripts (895A/896/1010), 1887 * set PM jump addresses. 1888 */ 1889 if (np->features & FE_NOPM) { 1890 OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle)); 1891 OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle)); 1892 } 1893 1894 /* 1895 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 1896 * Also set GPIO5 and clear GPIO6 if hardware LED control. 1897 */ 1898 if (np->features & FE_LED0) 1899 OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01); 1900 else if (np->features & FE_LEDC) 1901 OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20); 1902 1903 /* 1904 * enable ints 1905 */ 1906 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 1907 OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID); 1908 1909 /* 1910 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 1911 * Try to eat the spurious SBMC interrupt that may occur when 1912 * we reset the chip but not the SCSI BUS (at initialization). 1913 */ 1914 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 1915 OUTONW(np, nc_sien, SBMC); 1916 if (reason == 0) { 1917 INB(np, nc_mbox1); 1918 mdelay(100); 1919 INW(np, nc_sist); 1920 } 1921 np->scsi_mode = INB(np, nc_stest4) & SMODE; 1922 } 1923 1924 /* 1925 * Fill in target structure. 1926 * Reinitialize usrsync. 1927 * Reinitialize usrwide. 1928 * Prepare sync negotiation according to actual SCSI bus mode. 1929 */ 1930 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 1931 struct sym_tcb *tp = &np->target[i]; 1932 1933 tp->to_reset = 0; 1934 tp->head.sval = 0; 1935 tp->head.wval = np->rv_scntl3; 1936 tp->head.uval = 0; 1937 } 1938 1939 /* 1940 * Download SCSI SCRIPTS to on-chip RAM if present, 1941 * and start script processor. 1942 * We do the download preferently from the CPU. 1943 * For platforms that may not support PCI memory mapping, 1944 * we use simple SCRIPTS that performs MEMORY MOVEs. 1945 */ 1946 phys = SCRIPTA_BA(np, init); 1947 if (np->ram_ba) { 1948 if (sym_verbose >= 2) 1949 printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np)); 1950 memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz); 1951 if (np->ram_ws == 8192) { 1952 memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz); 1953 phys = scr_to_cpu(np->scr_ram_seg); 1954 OUTL(np, nc_mmws, phys); 1955 OUTL(np, nc_mmrs, phys); 1956 OUTL(np, nc_sfs, phys); 1957 phys = SCRIPTB_BA(np, start64); 1958 } 1959 } 1960 1961 np->istat_sem = 0; 1962 1963 OUTL(np, nc_dsa, np->hcb_ba); 1964 OUTL_DSP(np, phys); 1965 1966 /* 1967 * Notify the XPT about the RESET condition. 1968 */ 1969 if (reason != 0) 1970 sym_xpt_async_bus_reset(np); 1971 } 1972 1973 /* 1974 * Switch trans mode for current job and its target. 1975 */ 1976 static void sym_settrans(struct sym_hcb *np, int target, u_char opts, u_char ofs, 1977 u_char per, u_char wide, u_char div, u_char fak) 1978 { 1979 SYM_QUEHEAD *qp; 1980 u_char sval, wval, uval; 1981 struct sym_tcb *tp = &np->target[target]; 1982 1983 assert(target == (INB(np, nc_sdid) & 0x0f)); 1984 1985 sval = tp->head.sval; 1986 wval = tp->head.wval; 1987 uval = tp->head.uval; 1988 1989 #if 0 1990 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 1991 sval, wval, uval, np->rv_scntl3); 1992 #endif 1993 /* 1994 * Set the offset. 1995 */ 1996 if (!(np->features & FE_C10)) 1997 sval = (sval & ~0x1f) | ofs; 1998 else 1999 sval = (sval & ~0x3f) | ofs; 2000 2001 /* 2002 * Set the sync divisor and extra clock factor. 2003 */ 2004 if (ofs != 0) { 2005 wval = (wval & ~0x70) | ((div+1) << 4); 2006 if (!(np->features & FE_C10)) 2007 sval = (sval & ~0xe0) | (fak << 5); 2008 else { 2009 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 2010 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 2011 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 2012 } 2013 } 2014 2015 /* 2016 * Set the bus width. 2017 */ 2018 wval = wval & ~EWS; 2019 if (wide != 0) 2020 wval |= EWS; 2021 2022 /* 2023 * Set misc. ultra enable bits. 2024 */ 2025 if (np->features & FE_C10) { 2026 uval = uval & ~(U3EN|AIPCKEN); 2027 if (opts) { 2028 assert(np->features & FE_U3EN); 2029 uval |= U3EN; 2030 } 2031 } else { 2032 wval = wval & ~ULTRA; 2033 if (per <= 12) wval |= ULTRA; 2034 } 2035 2036 /* 2037 * Stop there if sync parameters are unchanged. 2038 */ 2039 if (tp->head.sval == sval && 2040 tp->head.wval == wval && 2041 tp->head.uval == uval) 2042 return; 2043 tp->head.sval = sval; 2044 tp->head.wval = wval; 2045 tp->head.uval = uval; 2046 2047 /* 2048 * Disable extended Sreq/Sack filtering if per < 50. 2049 * Not supported on the C1010. 2050 */ 2051 if (per < 50 && !(np->features & FE_C10)) 2052 OUTOFFB(np, nc_stest2, EXT); 2053 2054 /* 2055 * set actual value and sync_status 2056 */ 2057 OUTB(np, nc_sxfer, tp->head.sval); 2058 OUTB(np, nc_scntl3, tp->head.wval); 2059 2060 if (np->features & FE_C10) { 2061 OUTB(np, nc_scntl4, tp->head.uval); 2062 } 2063 2064 /* 2065 * patch ALL busy ccbs of this target. 2066 */ 2067 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 2068 struct sym_ccb *cp; 2069 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 2070 if (cp->target != target) 2071 continue; 2072 cp->phys.select.sel_scntl3 = tp->head.wval; 2073 cp->phys.select.sel_sxfer = tp->head.sval; 2074 if (np->features & FE_C10) { 2075 cp->phys.select.sel_scntl4 = tp->head.uval; 2076 } 2077 } 2078 } 2079 2080 /* 2081 * We received a WDTR. 2082 * Let everything be aware of the changes. 2083 */ 2084 static void sym_setwide(struct sym_hcb *np, int target, u_char wide) 2085 { 2086 struct sym_tcb *tp = &np->target[target]; 2087 struct scsi_target *starget = tp->starget; 2088 2089 if (spi_width(starget) == wide) 2090 return; 2091 2092 sym_settrans(np, target, 0, 0, 0, wide, 0, 0); 2093 2094 tp->tgoal.width = wide; 2095 spi_offset(starget) = 0; 2096 spi_period(starget) = 0; 2097 spi_width(starget) = wide; 2098 spi_iu(starget) = 0; 2099 spi_dt(starget) = 0; 2100 spi_qas(starget) = 0; 2101 2102 if (sym_verbose >= 3) 2103 spi_display_xfer_agreement(starget); 2104 } 2105 2106 /* 2107 * We received a SDTR. 2108 * Let everything be aware of the changes. 2109 */ 2110 static void 2111 sym_setsync(struct sym_hcb *np, int target, 2112 u_char ofs, u_char per, u_char div, u_char fak) 2113 { 2114 struct sym_tcb *tp = &np->target[target]; 2115 struct scsi_target *starget = tp->starget; 2116 u_char wide = (tp->head.wval & EWS) ? BUS_16_BIT : BUS_8_BIT; 2117 2118 sym_settrans(np, target, 0, ofs, per, wide, div, fak); 2119 2120 spi_period(starget) = per; 2121 spi_offset(starget) = ofs; 2122 spi_iu(starget) = spi_dt(starget) = spi_qas(starget) = 0; 2123 2124 if (!tp->tgoal.dt && !tp->tgoal.iu && !tp->tgoal.qas) { 2125 tp->tgoal.period = per; 2126 tp->tgoal.offset = ofs; 2127 tp->tgoal.check_nego = 0; 2128 } 2129 2130 spi_display_xfer_agreement(starget); 2131 } 2132 2133 /* 2134 * We received a PPR. 2135 * Let everything be aware of the changes. 2136 */ 2137 static void 2138 sym_setpprot(struct sym_hcb *np, int target, u_char opts, u_char ofs, 2139 u_char per, u_char wide, u_char div, u_char fak) 2140 { 2141 struct sym_tcb *tp = &np->target[target]; 2142 struct scsi_target *starget = tp->starget; 2143 2144 sym_settrans(np, target, opts, ofs, per, wide, div, fak); 2145 2146 spi_width(starget) = tp->tgoal.width = wide; 2147 spi_period(starget) = tp->tgoal.period = per; 2148 spi_offset(starget) = tp->tgoal.offset = ofs; 2149 spi_iu(starget) = tp->tgoal.iu = !!(opts & PPR_OPT_IU); 2150 spi_dt(starget) = tp->tgoal.dt = !!(opts & PPR_OPT_DT); 2151 spi_qas(starget) = tp->tgoal.qas = !!(opts & PPR_OPT_QAS); 2152 tp->tgoal.check_nego = 0; 2153 2154 spi_display_xfer_agreement(starget); 2155 } 2156 2157 /* 2158 * generic recovery from scsi interrupt 2159 * 2160 * The doc says that when the chip gets an SCSI interrupt, 2161 * it tries to stop in an orderly fashion, by completing 2162 * an instruction fetch that had started or by flushing 2163 * the DMA fifo for a write to memory that was executing. 2164 * Such a fashion is not enough to know if the instruction 2165 * that was just before the current DSP value has been 2166 * executed or not. 2167 * 2168 * There are some small SCRIPTS sections that deal with 2169 * the start queue and the done queue that may break any 2170 * assomption from the C code if we are interrupted 2171 * inside, so we reset if this happens. Btw, since these 2172 * SCRIPTS sections are executed while the SCRIPTS hasn't 2173 * started SCSI operations, it is very unlikely to happen. 2174 * 2175 * All the driver data structures are supposed to be 2176 * allocated from the same 4 GB memory window, so there 2177 * is a 1 to 1 relationship between DSA and driver data 2178 * structures. Since we are careful :) to invalidate the 2179 * DSA when we complete a command or when the SCRIPTS 2180 * pushes a DSA into a queue, we can trust it when it 2181 * points to a CCB. 2182 */ 2183 static void sym_recover_scsi_int (struct sym_hcb *np, u_char hsts) 2184 { 2185 u32 dsp = INL(np, nc_dsp); 2186 u32 dsa = INL(np, nc_dsa); 2187 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 2188 2189 /* 2190 * If we haven't been interrupted inside the SCRIPTS 2191 * critical pathes, we can safely restart the SCRIPTS 2192 * and trust the DSA value if it matches a CCB. 2193 */ 2194 if ((!(dsp > SCRIPTA_BA(np, getjob_begin) && 2195 dsp < SCRIPTA_BA(np, getjob_end) + 1)) && 2196 (!(dsp > SCRIPTA_BA(np, ungetjob) && 2197 dsp < SCRIPTA_BA(np, reselect) + 1)) && 2198 (!(dsp > SCRIPTB_BA(np, sel_for_abort) && 2199 dsp < SCRIPTB_BA(np, sel_for_abort_1) + 1)) && 2200 (!(dsp > SCRIPTA_BA(np, done) && 2201 dsp < SCRIPTA_BA(np, done_end) + 1))) { 2202 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 2203 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */ 2204 /* 2205 * If we have a CCB, let the SCRIPTS call us back for 2206 * the handling of the error with SCRATCHA filled with 2207 * STARTPOS. This way, we will be able to freeze the 2208 * device queue and requeue awaiting IOs. 2209 */ 2210 if (cp) { 2211 cp->host_status = hsts; 2212 OUTL_DSP(np, SCRIPTA_BA(np, complete_error)); 2213 } 2214 /* 2215 * Otherwise just restart the SCRIPTS. 2216 */ 2217 else { 2218 OUTL(np, nc_dsa, 0xffffff); 2219 OUTL_DSP(np, SCRIPTA_BA(np, start)); 2220 } 2221 } 2222 else 2223 goto reset_all; 2224 2225 return; 2226 2227 reset_all: 2228 sym_start_reset(np); 2229 } 2230 2231 /* 2232 * chip exception handler for selection timeout 2233 */ 2234 static void sym_int_sto (struct sym_hcb *np) 2235 { 2236 u32 dsp = INL(np, nc_dsp); 2237 2238 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 2239 2240 if (dsp == SCRIPTA_BA(np, wf_sel_done) + 8) 2241 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 2242 else 2243 sym_start_reset(np); 2244 } 2245 2246 /* 2247 * chip exception handler for unexpected disconnect 2248 */ 2249 static void sym_int_udc (struct sym_hcb *np) 2250 { 2251 printf ("%s: unexpected disconnect\n", sym_name(np)); 2252 sym_recover_scsi_int(np, HS_UNEXPECTED); 2253 } 2254 2255 /* 2256 * chip exception handler for SCSI bus mode change 2257 * 2258 * spi2-r12 11.2.3 says a transceiver mode change must 2259 * generate a reset event and a device that detects a reset 2260 * event shall initiate a hard reset. It says also that a 2261 * device that detects a mode change shall set data transfer 2262 * mode to eight bit asynchronous, etc... 2263 * So, just reinitializing all except chip should be enough. 2264 */ 2265 static void sym_int_sbmc (struct sym_hcb *np) 2266 { 2267 u_char scsi_mode = INB(np, nc_stest4) & SMODE; 2268 2269 /* 2270 * Notify user. 2271 */ 2272 printf("%s: SCSI BUS mode change from %s to %s.\n", sym_name(np), 2273 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 2274 2275 /* 2276 * Should suspend command processing for a few seconds and 2277 * reinitialize all except the chip. 2278 */ 2279 sym_start_up (np, 2); 2280 } 2281 2282 /* 2283 * chip exception handler for SCSI parity error. 2284 * 2285 * When the chip detects a SCSI parity error and is 2286 * currently executing a (CH)MOV instruction, it does 2287 * not interrupt immediately, but tries to finish the 2288 * transfer of the current scatter entry before 2289 * interrupting. The following situations may occur: 2290 * 2291 * - The complete scatter entry has been transferred 2292 * without the device having changed phase. 2293 * The chip will then interrupt with the DSP pointing 2294 * to the instruction that follows the MOV. 2295 * 2296 * - A phase mismatch occurs before the MOV finished 2297 * and phase errors are to be handled by the C code. 2298 * The chip will then interrupt with both PAR and MA 2299 * conditions set. 2300 * 2301 * - A phase mismatch occurs before the MOV finished and 2302 * phase errors are to be handled by SCRIPTS. 2303 * The chip will load the DSP with the phase mismatch 2304 * JUMP address and interrupt the host processor. 2305 */ 2306 static void sym_int_par (struct sym_hcb *np, u_short sist) 2307 { 2308 u_char hsts = INB(np, HS_PRT); 2309 u32 dsp = INL(np, nc_dsp); 2310 u32 dbc = INL(np, nc_dbc); 2311 u32 dsa = INL(np, nc_dsa); 2312 u_char sbcl = INB(np, nc_sbcl); 2313 u_char cmd = dbc >> 24; 2314 int phase = cmd & 7; 2315 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 2316 2317 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 2318 sym_name(np), hsts, dbc, sbcl); 2319 2320 /* 2321 * Check that the chip is connected to the SCSI BUS. 2322 */ 2323 if (!(INB(np, nc_scntl1) & ISCON)) { 2324 sym_recover_scsi_int(np, HS_UNEXPECTED); 2325 return; 2326 } 2327 2328 /* 2329 * If the nexus is not clearly identified, reset the bus. 2330 * We will try to do better later. 2331 */ 2332 if (!cp) 2333 goto reset_all; 2334 2335 /* 2336 * Check instruction was a MOV, direction was INPUT and 2337 * ATN is asserted. 2338 */ 2339 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 2340 goto reset_all; 2341 2342 /* 2343 * Keep track of the parity error. 2344 */ 2345 OUTONB(np, HF_PRT, HF_EXT_ERR); 2346 cp->xerr_status |= XE_PARITY_ERR; 2347 2348 /* 2349 * Prepare the message to send to the device. 2350 */ 2351 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 2352 2353 /* 2354 * If the old phase was DATA IN phase, we have to deal with 2355 * the 3 situations described above. 2356 * For other input phases (MSG IN and STATUS), the device 2357 * must resend the whole thing that failed parity checking 2358 * or signal error. So, jumping to dispatcher should be OK. 2359 */ 2360 if (phase == 1 || phase == 5) { 2361 /* Phase mismatch handled by SCRIPTS */ 2362 if (dsp == SCRIPTB_BA(np, pm_handle)) 2363 OUTL_DSP(np, dsp); 2364 /* Phase mismatch handled by the C code */ 2365 else if (sist & MA) 2366 sym_int_ma (np); 2367 /* No phase mismatch occurred */ 2368 else { 2369 sym_set_script_dp (np, cp, dsp); 2370 OUTL_DSP(np, SCRIPTA_BA(np, dispatch)); 2371 } 2372 } 2373 else if (phase == 7) /* We definitely cannot handle parity errors */ 2374 #if 1 /* in message-in phase due to the relection */ 2375 goto reset_all; /* path and various message anticipations. */ 2376 #else 2377 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 2378 #endif 2379 else 2380 OUTL_DSP(np, SCRIPTA_BA(np, dispatch)); 2381 return; 2382 2383 reset_all: 2384 sym_start_reset(np); 2385 return; 2386 } 2387 2388 /* 2389 * chip exception handler for phase errors. 2390 * 2391 * We have to construct a new transfer descriptor, 2392 * to transfer the rest of the current block. 2393 */ 2394 static void sym_int_ma (struct sym_hcb *np) 2395 { 2396 u32 dbc; 2397 u32 rest; 2398 u32 dsp; 2399 u32 dsa; 2400 u32 nxtdsp; 2401 u32 *vdsp; 2402 u32 oadr, olen; 2403 u32 *tblp; 2404 u32 newcmd; 2405 u_int delta; 2406 u_char cmd; 2407 u_char hflags, hflags0; 2408 struct sym_pmc *pm; 2409 struct sym_ccb *cp; 2410 2411 dsp = INL(np, nc_dsp); 2412 dbc = INL(np, nc_dbc); 2413 dsa = INL(np, nc_dsa); 2414 2415 cmd = dbc >> 24; 2416 rest = dbc & 0xffffff; 2417 delta = 0; 2418 2419 /* 2420 * locate matching cp if any. 2421 */ 2422 cp = sym_ccb_from_dsa(np, dsa); 2423 2424 /* 2425 * Donnot take into account dma fifo and various buffers in 2426 * INPUT phase since the chip flushes everything before 2427 * raising the MA interrupt for interrupted INPUT phases. 2428 * For DATA IN phase, we will check for the SWIDE later. 2429 */ 2430 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 2431 u_char ss0, ss2; 2432 2433 if (np->features & FE_DFBC) 2434 delta = INW(np, nc_dfbc); 2435 else { 2436 u32 dfifo; 2437 2438 /* 2439 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 2440 */ 2441 dfifo = INL(np, nc_dfifo); 2442 2443 /* 2444 * Calculate remaining bytes in DMA fifo. 2445 * (CTEST5 = dfifo >> 16) 2446 */ 2447 if (dfifo & (DFS << 16)) 2448 delta = ((((dfifo >> 8) & 0x300) | 2449 (dfifo & 0xff)) - rest) & 0x3ff; 2450 else 2451 delta = ((dfifo & 0xff) - rest) & 0x7f; 2452 } 2453 2454 /* 2455 * The data in the dma fifo has not been transfered to 2456 * the target -> add the amount to the rest 2457 * and clear the data. 2458 * Check the sstat2 register in case of wide transfer. 2459 */ 2460 rest += delta; 2461 ss0 = INB(np, nc_sstat0); 2462 if (ss0 & OLF) rest++; 2463 if (!(np->features & FE_C10)) 2464 if (ss0 & ORF) rest++; 2465 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 2466 ss2 = INB(np, nc_sstat2); 2467 if (ss2 & OLF1) rest++; 2468 if (!(np->features & FE_C10)) 2469 if (ss2 & ORF1) rest++; 2470 } 2471 2472 /* 2473 * Clear fifos. 2474 */ 2475 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 2476 OUTB(np, nc_stest3, TE|CSF); /* scsi fifo */ 2477 } 2478 2479 /* 2480 * log the information 2481 */ 2482 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 2483 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(np, nc_sbcl)&7, 2484 (unsigned) rest, (unsigned) delta); 2485 2486 /* 2487 * try to find the interrupted script command, 2488 * and the address at which to continue. 2489 */ 2490 vdsp = NULL; 2491 nxtdsp = 0; 2492 if (dsp > np->scripta_ba && 2493 dsp <= np->scripta_ba + np->scripta_sz) { 2494 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 2495 nxtdsp = dsp; 2496 } 2497 else if (dsp > np->scriptb_ba && 2498 dsp <= np->scriptb_ba + np->scriptb_sz) { 2499 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 2500 nxtdsp = dsp; 2501 } 2502 2503 /* 2504 * log the information 2505 */ 2506 if (DEBUG_FLAGS & DEBUG_PHASE) { 2507 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 2508 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 2509 } 2510 2511 if (!vdsp) { 2512 printf ("%s: interrupted SCRIPT address not found.\n", 2513 sym_name (np)); 2514 goto reset_all; 2515 } 2516 2517 if (!cp) { 2518 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 2519 sym_name (np)); 2520 goto reset_all; 2521 } 2522 2523 /* 2524 * get old startaddress and old length. 2525 */ 2526 oadr = scr_to_cpu(vdsp[1]); 2527 2528 if (cmd & 0x10) { /* Table indirect */ 2529 tblp = (u32 *) ((char*) &cp->phys + oadr); 2530 olen = scr_to_cpu(tblp[0]); 2531 oadr = scr_to_cpu(tblp[1]); 2532 } else { 2533 tblp = (u32 *) 0; 2534 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 2535 } 2536 2537 if (DEBUG_FLAGS & DEBUG_PHASE) { 2538 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 2539 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 2540 tblp, 2541 (unsigned) olen, 2542 (unsigned) oadr); 2543 } 2544 2545 /* 2546 * check cmd against assumed interrupted script command. 2547 * If dt data phase, the MOVE instruction hasn't bit 4 of 2548 * the phase. 2549 */ 2550 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 2551 sym_print_addr(cp->cmd, 2552 "internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 2553 cmd, scr_to_cpu(vdsp[0]) >> 24); 2554 2555 goto reset_all; 2556 } 2557 2558 /* 2559 * if old phase not dataphase, leave here. 2560 */ 2561 if (cmd & 2) { 2562 sym_print_addr(cp->cmd, 2563 "phase change %x-%x %d@%08x resid=%d.\n", 2564 cmd&7, INB(np, nc_sbcl)&7, (unsigned)olen, 2565 (unsigned)oadr, (unsigned)rest); 2566 goto unexpected_phase; 2567 } 2568 2569 /* 2570 * Choose the correct PM save area. 2571 * 2572 * Look at the PM_SAVE SCRIPT if you want to understand 2573 * this stuff. The equivalent code is implemented in 2574 * SCRIPTS for the 895A, 896 and 1010 that are able to 2575 * handle PM from the SCRIPTS processor. 2576 */ 2577 hflags0 = INB(np, HF_PRT); 2578 hflags = hflags0; 2579 2580 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 2581 if (hflags & HF_IN_PM0) 2582 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 2583 else if (hflags & HF_IN_PM1) 2584 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 2585 2586 if (hflags & HF_DP_SAVED) 2587 hflags ^= HF_ACT_PM; 2588 } 2589 2590 if (!(hflags & HF_ACT_PM)) { 2591 pm = &cp->phys.pm0; 2592 newcmd = SCRIPTA_BA(np, pm0_data); 2593 } 2594 else { 2595 pm = &cp->phys.pm1; 2596 newcmd = SCRIPTA_BA(np, pm1_data); 2597 } 2598 2599 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 2600 if (hflags != hflags0) 2601 OUTB(np, HF_PRT, hflags); 2602 2603 /* 2604 * fillin the phase mismatch context 2605 */ 2606 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 2607 pm->sg.size = cpu_to_scr(rest); 2608 pm->ret = cpu_to_scr(nxtdsp); 2609 2610 /* 2611 * If we have a SWIDE, 2612 * - prepare the address to write the SWIDE from SCRIPTS, 2613 * - compute the SCRIPTS address to restart from, 2614 * - move current data pointer context by one byte. 2615 */ 2616 nxtdsp = SCRIPTA_BA(np, dispatch); 2617 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 2618 (INB(np, nc_scntl2) & WSR)) { 2619 u32 tmp; 2620 2621 /* 2622 * Set up the table indirect for the MOVE 2623 * of the residual byte and adjust the data 2624 * pointer context. 2625 */ 2626 tmp = scr_to_cpu(pm->sg.addr); 2627 cp->phys.wresid.addr = cpu_to_scr(tmp); 2628 pm->sg.addr = cpu_to_scr(tmp + 1); 2629 tmp = scr_to_cpu(pm->sg.size); 2630 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 2631 pm->sg.size = cpu_to_scr(tmp - 1); 2632 2633 /* 2634 * If only the residual byte is to be moved, 2635 * no PM context is needed. 2636 */ 2637 if ((tmp&0xffffff) == 1) 2638 newcmd = pm->ret; 2639 2640 /* 2641 * Prepare the address of SCRIPTS that will 2642 * move the residual byte to memory. 2643 */ 2644 nxtdsp = SCRIPTB_BA(np, wsr_ma_helper); 2645 } 2646 2647 if (DEBUG_FLAGS & DEBUG_PHASE) { 2648 sym_print_addr(cp->cmd, "PM %x %x %x / %x %x %x.\n", 2649 hflags0, hflags, newcmd, 2650 (unsigned)scr_to_cpu(pm->sg.addr), 2651 (unsigned)scr_to_cpu(pm->sg.size), 2652 (unsigned)scr_to_cpu(pm->ret)); 2653 } 2654 2655 /* 2656 * Restart the SCRIPTS processor. 2657 */ 2658 sym_set_script_dp (np, cp, newcmd); 2659 OUTL_DSP(np, nxtdsp); 2660 return; 2661 2662 /* 2663 * Unexpected phase changes that occurs when the current phase 2664 * is not a DATA IN or DATA OUT phase are due to error conditions. 2665 * Such event may only happen when the SCRIPTS is using a 2666 * multibyte SCSI MOVE. 2667 * 2668 * Phase change Some possible cause 2669 * 2670 * COMMAND --> MSG IN SCSI parity error detected by target. 2671 * COMMAND --> STATUS Bad command or refused by target. 2672 * MSG OUT --> MSG IN Message rejected by target. 2673 * MSG OUT --> COMMAND Bogus target that discards extended 2674 * negotiation messages. 2675 * 2676 * The code below does not care of the new phase and so 2677 * trusts the target. Why to annoy it ? 2678 * If the interrupted phase is COMMAND phase, we restart at 2679 * dispatcher. 2680 * If a target does not get all the messages after selection, 2681 * the code assumes blindly that the target discards extended 2682 * messages and clears the negotiation status. 2683 * If the target does not want all our response to negotiation, 2684 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 2685 * bloat for such a should_not_happen situation). 2686 * In all other situation, we reset the BUS. 2687 * Are these assumptions reasonnable ? (Wait and see ...) 2688 */ 2689 unexpected_phase: 2690 dsp -= 8; 2691 nxtdsp = 0; 2692 2693 switch (cmd & 7) { 2694 case 2: /* COMMAND phase */ 2695 nxtdsp = SCRIPTA_BA(np, dispatch); 2696 break; 2697 #if 0 2698 case 3: /* STATUS phase */ 2699 nxtdsp = SCRIPTA_BA(np, dispatch); 2700 break; 2701 #endif 2702 case 6: /* MSG OUT phase */ 2703 /* 2704 * If the device may want to use untagged when we want 2705 * tagged, we prepare an IDENTIFY without disc. granted, 2706 * since we will not be able to handle reselect. 2707 * Otherwise, we just don't care. 2708 */ 2709 if (dsp == SCRIPTA_BA(np, send_ident)) { 2710 if (cp->tag != NO_TAG && olen - rest <= 3) { 2711 cp->host_status = HS_BUSY; 2712 np->msgout[0] = IDENTIFY(0, cp->lun); 2713 nxtdsp = SCRIPTB_BA(np, ident_break_atn); 2714 } 2715 else 2716 nxtdsp = SCRIPTB_BA(np, ident_break); 2717 } 2718 else if (dsp == SCRIPTB_BA(np, send_wdtr) || 2719 dsp == SCRIPTB_BA(np, send_sdtr) || 2720 dsp == SCRIPTB_BA(np, send_ppr)) { 2721 nxtdsp = SCRIPTB_BA(np, nego_bad_phase); 2722 if (dsp == SCRIPTB_BA(np, send_ppr)) { 2723 struct scsi_device *dev = cp->cmd->device; 2724 dev->ppr = 0; 2725 } 2726 } 2727 break; 2728 #if 0 2729 case 7: /* MSG IN phase */ 2730 nxtdsp = SCRIPTA_BA(np, clrack); 2731 break; 2732 #endif 2733 } 2734 2735 if (nxtdsp) { 2736 OUTL_DSP(np, nxtdsp); 2737 return; 2738 } 2739 2740 reset_all: 2741 sym_start_reset(np); 2742 } 2743 2744 /* 2745 * chip interrupt handler 2746 * 2747 * In normal situations, interrupt conditions occur one at 2748 * a time. But when something bad happens on the SCSI BUS, 2749 * the chip may raise several interrupt flags before 2750 * stopping and interrupting the CPU. The additionnal 2751 * interrupt flags are stacked in some extra registers 2752 * after the SIP and/or DIP flag has been raised in the 2753 * ISTAT. After the CPU has read the interrupt condition 2754 * flag from SIST or DSTAT, the chip unstacks the other 2755 * interrupt flags and sets the corresponding bits in 2756 * SIST or DSTAT. Since the chip starts stacking once the 2757 * SIP or DIP flag is set, there is a small window of time 2758 * where the stacking does not occur. 2759 * 2760 * Typically, multiple interrupt conditions may happen in 2761 * the following situations: 2762 * 2763 * - SCSI parity error + Phase mismatch (PAR|MA) 2764 * When an parity error is detected in input phase 2765 * and the device switches to msg-in phase inside a 2766 * block MOV. 2767 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 2768 * When a stupid device does not want to handle the 2769 * recovery of an SCSI parity error. 2770 * - Some combinations of STO, PAR, UDC, ... 2771 * When using non compliant SCSI stuff, when user is 2772 * doing non compliant hot tampering on the BUS, when 2773 * something really bad happens to a device, etc ... 2774 * 2775 * The heuristic suggested by SYMBIOS to handle 2776 * multiple interrupts is to try unstacking all 2777 * interrupts conditions and to handle them on some 2778 * priority based on error severity. 2779 * This will work when the unstacking has been 2780 * successful, but we cannot be 100 % sure of that, 2781 * since the CPU may have been faster to unstack than 2782 * the chip is able to stack. Hmmm ... But it seems that 2783 * such a situation is very unlikely to happen. 2784 * 2785 * If this happen, for example STO caught by the CPU 2786 * then UDC happenning before the CPU have restarted 2787 * the SCRIPTS, the driver may wrongly complete the 2788 * same command on UDC, since the SCRIPTS didn't restart 2789 * and the DSA still points to the same command. 2790 * We avoid this situation by setting the DSA to an 2791 * invalid value when the CCB is completed and before 2792 * restarting the SCRIPTS. 2793 * 2794 * Another issue is that we need some section of our 2795 * recovery procedures to be somehow uninterruptible but 2796 * the SCRIPTS processor does not provides such a 2797 * feature. For this reason, we handle recovery preferently 2798 * from the C code and check against some SCRIPTS critical 2799 * sections from the C code. 2800 * 2801 * Hopefully, the interrupt handling of the driver is now 2802 * able to resist to weird BUS error conditions, but donnot 2803 * ask me for any guarantee that it will never fail. :-) 2804 * Use at your own decision and risk. 2805 */ 2806 2807 void sym_interrupt (struct sym_hcb *np) 2808 { 2809 u_char istat, istatc; 2810 u_char dstat; 2811 u_short sist; 2812 2813 /* 2814 * interrupt on the fly ? 2815 * (SCRIPTS may still be running) 2816 * 2817 * A `dummy read' is needed to ensure that the 2818 * clear of the INTF flag reaches the device 2819 * and that posted writes are flushed to memory 2820 * before the scanning of the DONE queue. 2821 * Note that SCRIPTS also (dummy) read to memory 2822 * prior to deliver the INTF interrupt condition. 2823 */ 2824 istat = INB(np, nc_istat); 2825 if (istat & INTF) { 2826 OUTB(np, nc_istat, (istat & SIGP) | INTF | np->istat_sem); 2827 istat = INB(np, nc_istat); /* DUMMY READ */ 2828 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 2829 sym_wakeup_done(np); 2830 } 2831 2832 if (!(istat & (SIP|DIP))) 2833 return; 2834 2835 #if 0 /* We should never get this one */ 2836 if (istat & CABRT) 2837 OUTB(np, nc_istat, CABRT); 2838 #endif 2839 2840 /* 2841 * PAR and MA interrupts may occur at the same time, 2842 * and we need to know of both in order to handle 2843 * this situation properly. We try to unstack SCSI 2844 * interrupts for that reason. BTW, I dislike a LOT 2845 * such a loop inside the interrupt routine. 2846 * Even if DMA interrupt stacking is very unlikely to 2847 * happen, we also try unstacking these ones, since 2848 * this has no performance impact. 2849 */ 2850 sist = 0; 2851 dstat = 0; 2852 istatc = istat; 2853 do { 2854 if (istatc & SIP) 2855 sist |= INW(np, nc_sist); 2856 if (istatc & DIP) 2857 dstat |= INB(np, nc_dstat); 2858 istatc = INB(np, nc_istat); 2859 istat |= istatc; 2860 } while (istatc & (SIP|DIP)); 2861 2862 if (DEBUG_FLAGS & DEBUG_TINY) 2863 printf ("<%d|%x:%x|%x:%x>", 2864 (int)INB(np, nc_scr0), 2865 dstat,sist, 2866 (unsigned)INL(np, nc_dsp), 2867 (unsigned)INL(np, nc_dbc)); 2868 /* 2869 * On paper, a memory read barrier may be needed here to 2870 * prevent out of order LOADs by the CPU from having 2871 * prefetched stale data prior to DMA having occurred. 2872 * And since we are paranoid ... :) 2873 */ 2874 MEMORY_READ_BARRIER(); 2875 2876 /* 2877 * First, interrupts we want to service cleanly. 2878 * 2879 * Phase mismatch (MA) is the most frequent interrupt 2880 * for chip earlier than the 896 and so we have to service 2881 * it as quickly as possible. 2882 * A SCSI parity error (PAR) may be combined with a phase 2883 * mismatch condition (MA). 2884 * Programmed interrupts (SIR) are used to call the C code 2885 * from SCRIPTS. 2886 * The single step interrupt (SSI) is not used in this 2887 * driver. 2888 */ 2889 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 2890 !(dstat & (MDPE|BF|ABRT|IID))) { 2891 if (sist & PAR) sym_int_par (np, sist); 2892 else if (sist & MA) sym_int_ma (np); 2893 else if (dstat & SIR) sym_int_sir (np); 2894 else if (dstat & SSI) OUTONB_STD(); 2895 else goto unknown_int; 2896 return; 2897 } 2898 2899 /* 2900 * Now, interrupts that donnot happen in normal 2901 * situations and that we may need to recover from. 2902 * 2903 * On SCSI RESET (RST), we reset everything. 2904 * On SCSI BUS MODE CHANGE (SBMC), we complete all 2905 * active CCBs with RESET status, prepare all devices 2906 * for negotiating again and restart the SCRIPTS. 2907 * On STO and UDC, we complete the CCB with the corres- 2908 * ponding status and restart the SCRIPTS. 2909 */ 2910 if (sist & RST) { 2911 printf("%s: SCSI BUS reset detected.\n", sym_name(np)); 2912 sym_start_up (np, 1); 2913 return; 2914 } 2915 2916 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 2917 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */ 2918 2919 if (!(sist & (GEN|HTH|SGE)) && 2920 !(dstat & (MDPE|BF|ABRT|IID))) { 2921 if (sist & SBMC) sym_int_sbmc (np); 2922 else if (sist & STO) sym_int_sto (np); 2923 else if (sist & UDC) sym_int_udc (np); 2924 else goto unknown_int; 2925 return; 2926 } 2927 2928 /* 2929 * Now, interrupts we are not able to recover cleanly. 2930 * 2931 * Log message for hard errors. 2932 * Reset everything. 2933 */ 2934 2935 sym_log_hard_error(np, sist, dstat); 2936 2937 if ((sist & (GEN|HTH|SGE)) || 2938 (dstat & (MDPE|BF|ABRT|IID))) { 2939 sym_start_reset(np); 2940 return; 2941 } 2942 2943 unknown_int: 2944 /* 2945 * We just miss the cause of the interrupt. :( 2946 * Print a message. The timeout will do the real work. 2947 */ 2948 printf( "%s: unknown interrupt(s) ignored, " 2949 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 2950 sym_name(np), istat, dstat, sist); 2951 } 2952 2953 /* 2954 * Dequeue from the START queue all CCBs that match 2955 * a given target/lun/task condition (-1 means all), 2956 * and move them from the BUSY queue to the COMP queue 2957 * with DID_SOFT_ERROR status condition. 2958 * This function is used during error handling/recovery. 2959 * It is called with SCRIPTS not running. 2960 */ 2961 static int 2962 sym_dequeue_from_squeue(struct sym_hcb *np, int i, int target, int lun, int task) 2963 { 2964 int j; 2965 struct sym_ccb *cp; 2966 2967 /* 2968 * Make sure the starting index is within range. 2969 */ 2970 assert((i >= 0) && (i < 2*MAX_QUEUE)); 2971 2972 /* 2973 * Walk until end of START queue and dequeue every job 2974 * that matches the target/lun/task condition. 2975 */ 2976 j = i; 2977 while (i != np->squeueput) { 2978 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 2979 assert(cp); 2980 #ifdef SYM_CONF_IARB_SUPPORT 2981 /* Forget hints for IARB, they may be no longer relevant */ 2982 cp->host_flags &= ~HF_HINT_IARB; 2983 #endif 2984 if ((target == -1 || cp->target == target) && 2985 (lun == -1 || cp->lun == lun) && 2986 (task == -1 || cp->tag == task)) { 2987 sym_set_cam_status(cp->cmd, DID_SOFT_ERROR); 2988 sym_remque(&cp->link_ccbq); 2989 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 2990 } 2991 else { 2992 if (i != j) 2993 np->squeue[j] = np->squeue[i]; 2994 if ((j += 2) >= MAX_QUEUE*2) j = 0; 2995 } 2996 if ((i += 2) >= MAX_QUEUE*2) i = 0; 2997 } 2998 if (i != j) /* Copy back the idle task if needed */ 2999 np->squeue[j] = np->squeue[i]; 3000 np->squeueput = j; /* Update our current start queue pointer */ 3001 3002 return (i - j) / 2; 3003 } 3004 3005 /* 3006 * chip handler for bad SCSI status condition 3007 * 3008 * In case of bad SCSI status, we unqueue all the tasks 3009 * currently queued to the controller but not yet started 3010 * and then restart the SCRIPTS processor immediately. 3011 * 3012 * QUEUE FULL and BUSY conditions are handled the same way. 3013 * Basically all the not yet started tasks are requeued in 3014 * device queue and the queue is frozen until a completion. 3015 * 3016 * For CHECK CONDITION and COMMAND TERMINATED status, we use 3017 * the CCB of the failed command to prepare a REQUEST SENSE 3018 * SCSI command and queue it to the controller queue. 3019 * 3020 * SCRATCHA is assumed to have been loaded with STARTPOS 3021 * before the SCRIPTS called the C code. 3022 */ 3023 static void sym_sir_bad_scsi_status(struct sym_hcb *np, int num, struct sym_ccb *cp) 3024 { 3025 u32 startp; 3026 u_char s_status = cp->ssss_status; 3027 u_char h_flags = cp->host_flags; 3028 int msglen; 3029 int i; 3030 3031 /* 3032 * Compute the index of the next job to start from SCRIPTS. 3033 */ 3034 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3035 3036 /* 3037 * The last CCB queued used for IARB hint may be 3038 * no longer relevant. Forget it. 3039 */ 3040 #ifdef SYM_CONF_IARB_SUPPORT 3041 if (np->last_cp) 3042 np->last_cp = 0; 3043 #endif 3044 3045 /* 3046 * Now deal with the SCSI status. 3047 */ 3048 switch(s_status) { 3049 case S_BUSY: 3050 case S_QUEUE_FULL: 3051 if (sym_verbose >= 2) { 3052 sym_print_addr(cp->cmd, "%s\n", 3053 s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 3054 } 3055 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 3056 sym_complete_error (np, cp); 3057 break; 3058 case S_TERMINATED: 3059 case S_CHECK_COND: 3060 /* 3061 * If we get an SCSI error when requesting sense, give up. 3062 */ 3063 if (h_flags & HF_SENSE) { 3064 sym_complete_error (np, cp); 3065 break; 3066 } 3067 3068 /* 3069 * Dequeue all queued CCBs for that device not yet started, 3070 * and restart the SCRIPTS processor immediately. 3071 */ 3072 sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 3073 OUTL_DSP(np, SCRIPTA_BA(np, start)); 3074 3075 /* 3076 * Save some info of the actual IO. 3077 * Compute the data residual. 3078 */ 3079 cp->sv_scsi_status = cp->ssss_status; 3080 cp->sv_xerr_status = cp->xerr_status; 3081 cp->sv_resid = sym_compute_residual(np, cp); 3082 3083 /* 3084 * Prepare all needed data structures for 3085 * requesting sense data. 3086 */ 3087 3088 cp->scsi_smsg2[0] = IDENTIFY(0, cp->lun); 3089 msglen = 1; 3090 3091 /* 3092 * If we are currently using anything different from 3093 * async. 8 bit data transfers with that target, 3094 * start a negotiation, since the device may want 3095 * to report us a UNIT ATTENTION condition due to 3096 * a cause we currently ignore, and we donnot want 3097 * to be stuck with WIDE and/or SYNC data transfer. 3098 * 3099 * cp->nego_status is filled by sym_prepare_nego(). 3100 */ 3101 cp->nego_status = 0; 3102 msglen += sym_prepare_nego(np, cp, &cp->scsi_smsg2[msglen]); 3103 /* 3104 * Message table indirect structure. 3105 */ 3106 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg2); 3107 cp->phys.smsg.size = cpu_to_scr(msglen); 3108 3109 /* 3110 * sense command 3111 */ 3112 cp->phys.cmd.addr = CCB_BA(cp, sensecmd); 3113 cp->phys.cmd.size = cpu_to_scr(6); 3114 3115 /* 3116 * patch requested size into sense command 3117 */ 3118 cp->sensecmd[0] = REQUEST_SENSE; 3119 cp->sensecmd[1] = 0; 3120 if (cp->cmd->device->scsi_level <= SCSI_2 && cp->lun <= 7) 3121 cp->sensecmd[1] = cp->lun << 5; 3122 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 3123 cp->data_len = SYM_SNS_BBUF_LEN; 3124 3125 /* 3126 * sense data 3127 */ 3128 memset(cp->sns_bbuf, 0, SYM_SNS_BBUF_LEN); 3129 cp->phys.sense.addr = CCB_BA(cp, sns_bbuf); 3130 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 3131 3132 /* 3133 * requeue the command. 3134 */ 3135 startp = SCRIPTB_BA(np, sdata_in); 3136 3137 cp->phys.head.savep = cpu_to_scr(startp); 3138 cp->phys.head.lastp = cpu_to_scr(startp); 3139 cp->startp = cpu_to_scr(startp); 3140 cp->goalp = cpu_to_scr(startp + 16); 3141 3142 cp->host_xflags = 0; 3143 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 3144 cp->ssss_status = S_ILLEGAL; 3145 cp->host_flags = (HF_SENSE|HF_DATA_IN); 3146 cp->xerr_status = 0; 3147 cp->extra_bytes = 0; 3148 3149 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select)); 3150 3151 /* 3152 * Requeue the command. 3153 */ 3154 sym_put_start_queue(np, cp); 3155 3156 /* 3157 * Give back to upper layer everything we have dequeued. 3158 */ 3159 sym_flush_comp_queue(np, 0); 3160 break; 3161 } 3162 } 3163 3164 /* 3165 * After a device has accepted some management message 3166 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 3167 * a device signals a UNIT ATTENTION condition, some 3168 * tasks are thrown away by the device. We are required 3169 * to reflect that on our tasks list since the device 3170 * will never complete these tasks. 3171 * 3172 * This function move from the BUSY queue to the COMP 3173 * queue all disconnected CCBs for a given target that 3174 * match the following criteria: 3175 * - lun=-1 means any logical UNIT otherwise a given one. 3176 * - task=-1 means any task, otherwise a given one. 3177 */ 3178 int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task) 3179 { 3180 SYM_QUEHEAD qtmp, *qp; 3181 int i = 0; 3182 struct sym_ccb *cp; 3183 3184 /* 3185 * Move the entire BUSY queue to our temporary queue. 3186 */ 3187 sym_que_init(&qtmp); 3188 sym_que_splice(&np->busy_ccbq, &qtmp); 3189 sym_que_init(&np->busy_ccbq); 3190 3191 /* 3192 * Put all CCBs that matches our criteria into 3193 * the COMP queue and put back other ones into 3194 * the BUSY queue. 3195 */ 3196 while ((qp = sym_remque_head(&qtmp)) != 0) { 3197 struct scsi_cmnd *cmd; 3198 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3199 cmd = cp->cmd; 3200 if (cp->host_status != HS_DISCONNECT || 3201 cp->target != target || 3202 (lun != -1 && cp->lun != lun) || 3203 (task != -1 && 3204 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 3205 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 3206 continue; 3207 } 3208 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 3209 3210 /* Preserve the software timeout condition */ 3211 if (sym_get_cam_status(cmd) != DID_TIME_OUT) 3212 sym_set_cam_status(cmd, cam_status); 3213 ++i; 3214 #if 0 3215 printf("XXXX TASK @%p CLEARED\n", cp); 3216 #endif 3217 } 3218 return i; 3219 } 3220 3221 /* 3222 * chip handler for TASKS recovery 3223 * 3224 * We cannot safely abort a command, while the SCRIPTS 3225 * processor is running, since we just would be in race 3226 * with it. 3227 * 3228 * As long as we have tasks to abort, we keep the SEM 3229 * bit set in the ISTAT. When this bit is set, the 3230 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 3231 * each time it enters the scheduler. 3232 * 3233 * If we have to reset a target, clear tasks of a unit, 3234 * or to perform the abort of a disconnected job, we 3235 * restart the SCRIPTS for selecting the target. Once 3236 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 3237 * If it loses arbitration, the SCRIPTS will interrupt again 3238 * the next time it will enter its scheduler, and so on ... 3239 * 3240 * On SIR_TARGET_SELECTED, we scan for the more 3241 * appropriate thing to do: 3242 * 3243 * - If nothing, we just sent a M_ABORT message to the 3244 * target to get rid of the useless SCSI bus ownership. 3245 * According to the specs, no tasks shall be affected. 3246 * - If the target is to be reset, we send it a M_RESET 3247 * message. 3248 * - If a logical UNIT is to be cleared , we send the 3249 * IDENTIFY(lun) + M_ABORT. 3250 * - If an untagged task is to be aborted, we send the 3251 * IDENTIFY(lun) + M_ABORT. 3252 * - If a tagged task is to be aborted, we send the 3253 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 3254 * 3255 * Once our 'kiss of death' :) message has been accepted 3256 * by the target, the SCRIPTS interrupts again 3257 * (SIR_ABORT_SENT). On this interrupt, we complete 3258 * all the CCBs that should have been aborted by the 3259 * target according to our message. 3260 */ 3261 static void sym_sir_task_recovery(struct sym_hcb *np, int num) 3262 { 3263 SYM_QUEHEAD *qp; 3264 struct sym_ccb *cp; 3265 struct sym_tcb *tp = NULL; /* gcc isn't quite smart enough yet */ 3266 struct scsi_target *starget; 3267 int target=-1, lun=-1, task; 3268 int i, k; 3269 3270 switch(num) { 3271 /* 3272 * The SCRIPTS processor stopped before starting 3273 * the next command in order to allow us to perform 3274 * some task recovery. 3275 */ 3276 case SIR_SCRIPT_STOPPED: 3277 /* 3278 * Do we have any target to reset or unit to clear ? 3279 */ 3280 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 3281 tp = &np->target[i]; 3282 if (tp->to_reset || 3283 (tp->lun0p && tp->lun0p->to_clear)) { 3284 target = i; 3285 break; 3286 } 3287 if (!tp->lunmp) 3288 continue; 3289 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 3290 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 3291 target = i; 3292 break; 3293 } 3294 } 3295 if (target != -1) 3296 break; 3297 } 3298 3299 /* 3300 * If not, walk the busy queue for any 3301 * disconnected CCB to be aborted. 3302 */ 3303 if (target == -1) { 3304 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3305 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 3306 if (cp->host_status != HS_DISCONNECT) 3307 continue; 3308 if (cp->to_abort) { 3309 target = cp->target; 3310 break; 3311 } 3312 } 3313 } 3314 3315 /* 3316 * If some target is to be selected, 3317 * prepare and start the selection. 3318 */ 3319 if (target != -1) { 3320 tp = &np->target[target]; 3321 np->abrt_sel.sel_id = target; 3322 np->abrt_sel.sel_scntl3 = tp->head.wval; 3323 np->abrt_sel.sel_sxfer = tp->head.sval; 3324 OUTL(np, nc_dsa, np->hcb_ba); 3325 OUTL_DSP(np, SCRIPTB_BA(np, sel_for_abort)); 3326 return; 3327 } 3328 3329 /* 3330 * Now look for a CCB to abort that haven't started yet. 3331 * Btw, the SCRIPTS processor is still stopped, so 3332 * we are not in race. 3333 */ 3334 i = 0; 3335 cp = NULL; 3336 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3337 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3338 if (cp->host_status != HS_BUSY && 3339 cp->host_status != HS_NEGOTIATE) 3340 continue; 3341 if (!cp->to_abort) 3342 continue; 3343 #ifdef SYM_CONF_IARB_SUPPORT 3344 /* 3345 * If we are using IMMEDIATE ARBITRATION, we donnot 3346 * want to cancel the last queued CCB, since the 3347 * SCRIPTS may have anticipated the selection. 3348 */ 3349 if (cp == np->last_cp) { 3350 cp->to_abort = 0; 3351 continue; 3352 } 3353 #endif 3354 i = 1; /* Means we have found some */ 3355 break; 3356 } 3357 if (!i) { 3358 /* 3359 * We are done, so we donnot need 3360 * to synchronize with the SCRIPTS anylonger. 3361 * Remove the SEM flag from the ISTAT. 3362 */ 3363 np->istat_sem = 0; 3364 OUTB(np, nc_istat, SIGP); 3365 break; 3366 } 3367 /* 3368 * Compute index of next position in the start 3369 * queue the SCRIPTS intends to start and dequeue 3370 * all CCBs for that device that haven't been started. 3371 */ 3372 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3373 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 3374 3375 /* 3376 * Make sure at least our IO to abort has been dequeued. 3377 */ 3378 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 3379 assert(i && sym_get_cam_status(cp->cmd) == DID_SOFT_ERROR); 3380 #else 3381 sym_remque(&cp->link_ccbq); 3382 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 3383 #endif 3384 /* 3385 * Keep track in cam status of the reason of the abort. 3386 */ 3387 if (cp->to_abort == 2) 3388 sym_set_cam_status(cp->cmd, DID_TIME_OUT); 3389 else 3390 sym_set_cam_status(cp->cmd, DID_ABORT); 3391 3392 /* 3393 * Complete with error everything that we have dequeued. 3394 */ 3395 sym_flush_comp_queue(np, 0); 3396 break; 3397 /* 3398 * The SCRIPTS processor has selected a target 3399 * we may have some manual recovery to perform for. 3400 */ 3401 case SIR_TARGET_SELECTED: 3402 target = INB(np, nc_sdid) & 0xf; 3403 tp = &np->target[target]; 3404 3405 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 3406 3407 /* 3408 * If the target is to be reset, prepare a 3409 * M_RESET message and clear the to_reset flag 3410 * since we donnot expect this operation to fail. 3411 */ 3412 if (tp->to_reset) { 3413 np->abrt_msg[0] = M_RESET; 3414 np->abrt_tbl.size = 1; 3415 tp->to_reset = 0; 3416 break; 3417 } 3418 3419 /* 3420 * Otherwise, look for some logical unit to be cleared. 3421 */ 3422 if (tp->lun0p && tp->lun0p->to_clear) 3423 lun = 0; 3424 else if (tp->lunmp) { 3425 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 3426 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 3427 lun = k; 3428 break; 3429 } 3430 } 3431 } 3432 3433 /* 3434 * If a logical unit is to be cleared, prepare 3435 * an IDENTIFY(lun) + ABORT MESSAGE. 3436 */ 3437 if (lun != -1) { 3438 struct sym_lcb *lp = sym_lp(tp, lun); 3439 lp->to_clear = 0; /* We don't expect to fail here */ 3440 np->abrt_msg[0] = IDENTIFY(0, lun); 3441 np->abrt_msg[1] = M_ABORT; 3442 np->abrt_tbl.size = 2; 3443 break; 3444 } 3445 3446 /* 3447 * Otherwise, look for some disconnected job to 3448 * abort for this target. 3449 */ 3450 i = 0; 3451 cp = NULL; 3452 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3453 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3454 if (cp->host_status != HS_DISCONNECT) 3455 continue; 3456 if (cp->target != target) 3457 continue; 3458 if (!cp->to_abort) 3459 continue; 3460 i = 1; /* Means we have some */ 3461 break; 3462 } 3463 3464 /* 3465 * If we have none, probably since the device has 3466 * completed the command before we won abitration, 3467 * send a M_ABORT message without IDENTIFY. 3468 * According to the specs, the device must just 3469 * disconnect the BUS and not abort any task. 3470 */ 3471 if (!i) { 3472 np->abrt_msg[0] = M_ABORT; 3473 np->abrt_tbl.size = 1; 3474 break; 3475 } 3476 3477 /* 3478 * We have some task to abort. 3479 * Set the IDENTIFY(lun) 3480 */ 3481 np->abrt_msg[0] = IDENTIFY(0, cp->lun); 3482 3483 /* 3484 * If we want to abort an untagged command, we 3485 * will send a IDENTIFY + M_ABORT. 3486 * Otherwise (tagged command), we will send 3487 * a IDENTITFY + task attributes + ABORT TAG. 3488 */ 3489 if (cp->tag == NO_TAG) { 3490 np->abrt_msg[1] = M_ABORT; 3491 np->abrt_tbl.size = 2; 3492 } else { 3493 np->abrt_msg[1] = cp->scsi_smsg[1]; 3494 np->abrt_msg[2] = cp->scsi_smsg[2]; 3495 np->abrt_msg[3] = M_ABORT_TAG; 3496 np->abrt_tbl.size = 4; 3497 } 3498 /* 3499 * Keep track of software timeout condition, since the 3500 * peripheral driver may not count retries on abort 3501 * conditions not due to timeout. 3502 */ 3503 if (cp->to_abort == 2) 3504 sym_set_cam_status(cp->cmd, DID_TIME_OUT); 3505 cp->to_abort = 0; /* We donnot expect to fail here */ 3506 break; 3507 3508 /* 3509 * The target has accepted our message and switched 3510 * to BUS FREE phase as we expected. 3511 */ 3512 case SIR_ABORT_SENT: 3513 target = INB(np, nc_sdid) & 0xf; 3514 tp = &np->target[target]; 3515 starget = tp->starget; 3516 3517 /* 3518 ** If we didn't abort anything, leave here. 3519 */ 3520 if (np->abrt_msg[0] == M_ABORT) 3521 break; 3522 3523 /* 3524 * If we sent a M_RESET, then a hardware reset has 3525 * been performed by the target. 3526 * - Reset everything to async 8 bit 3527 * - Tell ourself to negotiate next time :-) 3528 * - Prepare to clear all disconnected CCBs for 3529 * this target from our task list (lun=task=-1) 3530 */ 3531 lun = -1; 3532 task = -1; 3533 if (np->abrt_msg[0] == M_RESET) { 3534 tp->head.sval = 0; 3535 tp->head.wval = np->rv_scntl3; 3536 tp->head.uval = 0; 3537 spi_period(starget) = 0; 3538 spi_offset(starget) = 0; 3539 spi_width(starget) = 0; 3540 spi_iu(starget) = 0; 3541 spi_dt(starget) = 0; 3542 spi_qas(starget) = 0; 3543 tp->tgoal.check_nego = 1; 3544 } 3545 3546 /* 3547 * Otherwise, check for the LUN and TASK(s) 3548 * concerned by the cancelation. 3549 * If it is not ABORT_TAG then it is CLEAR_QUEUE 3550 * or an ABORT message :-) 3551 */ 3552 else { 3553 lun = np->abrt_msg[0] & 0x3f; 3554 if (np->abrt_msg[1] == M_ABORT_TAG) 3555 task = np->abrt_msg[2]; 3556 } 3557 3558 /* 3559 * Complete all the CCBs the device should have 3560 * aborted due to our 'kiss of death' message. 3561 */ 3562 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3563 sym_dequeue_from_squeue(np, i, target, lun, -1); 3564 sym_clear_tasks(np, DID_ABORT, target, lun, task); 3565 sym_flush_comp_queue(np, 0); 3566 3567 /* 3568 * If we sent a BDR, make upper layer aware of that. 3569 */ 3570 if (np->abrt_msg[0] == M_RESET) 3571 sym_xpt_async_sent_bdr(np, target); 3572 break; 3573 } 3574 3575 /* 3576 * Print to the log the message we intend to send. 3577 */ 3578 if (num == SIR_TARGET_SELECTED) { 3579 dev_info(&tp->starget->dev, "control msgout:"); 3580 sym_printl_hex(np->abrt_msg, np->abrt_tbl.size); 3581 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 3582 } 3583 3584 /* 3585 * Let the SCRIPTS processor continue. 3586 */ 3587 OUTONB_STD(); 3588 } 3589 3590 /* 3591 * Gerard's alchemy:) that deals with with the data 3592 * pointer for both MDP and the residual calculation. 3593 * 3594 * I didn't want to bloat the code by more than 200 3595 * lines for the handling of both MDP and the residual. 3596 * This has been achieved by using a data pointer 3597 * representation consisting in an index in the data 3598 * array (dp_sg) and a negative offset (dp_ofs) that 3599 * have the following meaning: 3600 * 3601 * - dp_sg = SYM_CONF_MAX_SG 3602 * we are at the end of the data script. 3603 * - dp_sg < SYM_CONF_MAX_SG 3604 * dp_sg points to the next entry of the scatter array 3605 * we want to transfer. 3606 * - dp_ofs < 0 3607 * dp_ofs represents the residual of bytes of the 3608 * previous entry scatter entry we will send first. 3609 * - dp_ofs = 0 3610 * no residual to send first. 3611 * 3612 * The function sym_evaluate_dp() accepts an arbitray 3613 * offset (basically from the MDP message) and returns 3614 * the corresponding values of dp_sg and dp_ofs. 3615 */ 3616 3617 static int sym_evaluate_dp(struct sym_hcb *np, struct sym_ccb *cp, u32 scr, int *ofs) 3618 { 3619 u32 dp_scr; 3620 int dp_ofs, dp_sg, dp_sgmin; 3621 int tmp; 3622 struct sym_pmc *pm; 3623 3624 /* 3625 * Compute the resulted data pointer in term of a script 3626 * address within some DATA script and a signed byte offset. 3627 */ 3628 dp_scr = scr; 3629 dp_ofs = *ofs; 3630 if (dp_scr == SCRIPTA_BA(np, pm0_data)) 3631 pm = &cp->phys.pm0; 3632 else if (dp_scr == SCRIPTA_BA(np, pm1_data)) 3633 pm = &cp->phys.pm1; 3634 else 3635 pm = NULL; 3636 3637 if (pm) { 3638 dp_scr = scr_to_cpu(pm->ret); 3639 dp_ofs -= scr_to_cpu(pm->sg.size); 3640 } 3641 3642 /* 3643 * If we are auto-sensing, then we are done. 3644 */ 3645 if (cp->host_flags & HF_SENSE) { 3646 *ofs = dp_ofs; 3647 return 0; 3648 } 3649 3650 /* 3651 * Deduce the index of the sg entry. 3652 * Keep track of the index of the first valid entry. 3653 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 3654 * end of the data. 3655 */ 3656 tmp = scr_to_cpu(sym_goalp(cp)); 3657 dp_sg = SYM_CONF_MAX_SG; 3658 if (dp_scr != tmp) 3659 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 3660 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 3661 3662 /* 3663 * Move to the sg entry the data pointer belongs to. 3664 * 3665 * If we are inside the data area, we expect result to be: 3666 * 3667 * Either, 3668 * dp_ofs = 0 and dp_sg is the index of the sg entry 3669 * the data pointer belongs to (or the end of the data) 3670 * Or, 3671 * dp_ofs < 0 and dp_sg is the index of the sg entry 3672 * the data pointer belongs to + 1. 3673 */ 3674 if (dp_ofs < 0) { 3675 int n; 3676 while (dp_sg > dp_sgmin) { 3677 --dp_sg; 3678 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3679 n = dp_ofs + (tmp & 0xffffff); 3680 if (n > 0) { 3681 ++dp_sg; 3682 break; 3683 } 3684 dp_ofs = n; 3685 } 3686 } 3687 else if (dp_ofs > 0) { 3688 while (dp_sg < SYM_CONF_MAX_SG) { 3689 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3690 dp_ofs -= (tmp & 0xffffff); 3691 ++dp_sg; 3692 if (dp_ofs <= 0) 3693 break; 3694 } 3695 } 3696 3697 /* 3698 * Make sure the data pointer is inside the data area. 3699 * If not, return some error. 3700 */ 3701 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 3702 goto out_err; 3703 else if (dp_sg > SYM_CONF_MAX_SG || 3704 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 3705 goto out_err; 3706 3707 /* 3708 * Save the extreme pointer if needed. 3709 */ 3710 if (dp_sg > cp->ext_sg || 3711 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 3712 cp->ext_sg = dp_sg; 3713 cp->ext_ofs = dp_ofs; 3714 } 3715 3716 /* 3717 * Return data. 3718 */ 3719 *ofs = dp_ofs; 3720 return dp_sg; 3721 3722 out_err: 3723 return -1; 3724 } 3725 3726 /* 3727 * chip handler for MODIFY DATA POINTER MESSAGE 3728 * 3729 * We also call this function on IGNORE WIDE RESIDUE 3730 * messages that do not match a SWIDE full condition. 3731 * Btw, we assume in that situation that such a message 3732 * is equivalent to a MODIFY DATA POINTER (offset=-1). 3733 */ 3734 3735 static void sym_modify_dp(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp, int ofs) 3736 { 3737 int dp_ofs = ofs; 3738 u32 dp_scr = sym_get_script_dp (np, cp); 3739 u32 dp_ret; 3740 u32 tmp; 3741 u_char hflags; 3742 int dp_sg; 3743 struct sym_pmc *pm; 3744 3745 /* 3746 * Not supported for auto-sense. 3747 */ 3748 if (cp->host_flags & HF_SENSE) 3749 goto out_reject; 3750 3751 /* 3752 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 3753 * to the resulted data pointer. 3754 */ 3755 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 3756 if (dp_sg < 0) 3757 goto out_reject; 3758 3759 /* 3760 * And our alchemy:) allows to easily calculate the data 3761 * script address we want to return for the next data phase. 3762 */ 3763 dp_ret = cpu_to_scr(sym_goalp(cp)); 3764 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 3765 3766 /* 3767 * If offset / scatter entry is zero we donnot need 3768 * a context for the new current data pointer. 3769 */ 3770 if (dp_ofs == 0) { 3771 dp_scr = dp_ret; 3772 goto out_ok; 3773 } 3774 3775 /* 3776 * Get a context for the new current data pointer. 3777 */ 3778 hflags = INB(np, HF_PRT); 3779 3780 if (hflags & HF_DP_SAVED) 3781 hflags ^= HF_ACT_PM; 3782 3783 if (!(hflags & HF_ACT_PM)) { 3784 pm = &cp->phys.pm0; 3785 dp_scr = SCRIPTA_BA(np, pm0_data); 3786 } 3787 else { 3788 pm = &cp->phys.pm1; 3789 dp_scr = SCRIPTA_BA(np, pm1_data); 3790 } 3791 3792 hflags &= ~(HF_DP_SAVED); 3793 3794 OUTB(np, HF_PRT, hflags); 3795 3796 /* 3797 * Set up the new current data pointer. 3798 * ofs < 0 there, and for the next data phase, we 3799 * want to transfer part of the data of the sg entry 3800 * corresponding to index dp_sg-1 prior to returning 3801 * to the main data script. 3802 */ 3803 pm->ret = cpu_to_scr(dp_ret); 3804 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 3805 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 3806 pm->sg.addr = cpu_to_scr(tmp); 3807 pm->sg.size = cpu_to_scr(-dp_ofs); 3808 3809 out_ok: 3810 sym_set_script_dp (np, cp, dp_scr); 3811 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 3812 return; 3813 3814 out_reject: 3815 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 3816 } 3817 3818 3819 /* 3820 * chip calculation of the data residual. 3821 * 3822 * As I used to say, the requirement of data residual 3823 * in SCSI is broken, useless and cannot be achieved 3824 * without huge complexity. 3825 * But most OSes and even the official CAM require it. 3826 * When stupidity happens to be so widely spread inside 3827 * a community, it gets hard to convince. 3828 * 3829 * Anyway, I don't care, since I am not going to use 3830 * any software that considers this data residual as 3831 * a relevant information. :) 3832 */ 3833 3834 int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp) 3835 { 3836 int dp_sg, dp_sgmin, resid = 0; 3837 int dp_ofs = 0; 3838 3839 /* 3840 * Check for some data lost or just thrown away. 3841 * We are not required to be quite accurate in this 3842 * situation. Btw, if we are odd for output and the 3843 * device claims some more data, it may well happen 3844 * than our residual be zero. :-) 3845 */ 3846 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 3847 if (cp->xerr_status & XE_EXTRA_DATA) 3848 resid -= cp->extra_bytes; 3849 if (cp->xerr_status & XE_SODL_UNRUN) 3850 ++resid; 3851 if (cp->xerr_status & XE_SWIDE_OVRUN) 3852 --resid; 3853 } 3854 3855 /* 3856 * If all data has been transferred, 3857 * there is no residual. 3858 */ 3859 if (cp->phys.head.lastp == sym_goalp(cp)) 3860 return resid; 3861 3862 /* 3863 * If no data transfer occurs, or if the data 3864 * pointer is weird, return full residual. 3865 */ 3866 if (cp->startp == cp->phys.head.lastp || 3867 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 3868 &dp_ofs) < 0) { 3869 return cp->data_len; 3870 } 3871 3872 /* 3873 * If we were auto-sensing, then we are done. 3874 */ 3875 if (cp->host_flags & HF_SENSE) { 3876 return -dp_ofs; 3877 } 3878 3879 /* 3880 * We are now full comfortable in the computation 3881 * of the data residual (2's complement). 3882 */ 3883 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 3884 resid = -cp->ext_ofs; 3885 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 3886 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3887 resid += (tmp & 0xffffff); 3888 } 3889 3890 resid -= cp->odd_byte_adjustment; 3891 3892 /* 3893 * Hopefully, the result is not too wrong. 3894 */ 3895 return resid; 3896 } 3897 3898 /* 3899 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 3900 * 3901 * When we try to negotiate, we append the negotiation message 3902 * to the identify and (maybe) simple tag message. 3903 * The host status field is set to HS_NEGOTIATE to mark this 3904 * situation. 3905 * 3906 * If the target doesn't answer this message immediately 3907 * (as required by the standard), the SIR_NEGO_FAILED interrupt 3908 * will be raised eventually. 3909 * The handler removes the HS_NEGOTIATE status, and sets the 3910 * negotiated value to the default (async / nowide). 3911 * 3912 * If we receive a matching answer immediately, we check it 3913 * for validity, and set the values. 3914 * 3915 * If we receive a Reject message immediately, we assume the 3916 * negotiation has failed, and fall back to standard values. 3917 * 3918 * If we receive a negotiation message while not in HS_NEGOTIATE 3919 * state, it's a target initiated negotiation. We prepare a 3920 * (hopefully) valid answer, set our parameters, and send back 3921 * this answer to the target. 3922 * 3923 * If the target doesn't fetch the answer (no message out phase), 3924 * we assume the negotiation has failed, and fall back to default 3925 * settings (SIR_NEGO_PROTO interrupt). 3926 * 3927 * When we set the values, we adjust them in all ccbs belonging 3928 * to this target, in the controller's register, and in the "phys" 3929 * field of the controller's struct sym_hcb. 3930 */ 3931 3932 /* 3933 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 3934 */ 3935 static int 3936 sym_sync_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp) 3937 { 3938 int target = cp->target; 3939 u_char chg, ofs, per, fak, div; 3940 3941 if (DEBUG_FLAGS & DEBUG_NEGO) { 3942 sym_print_nego_msg(np, target, "sync msgin", np->msgin); 3943 } 3944 3945 /* 3946 * Get requested values. 3947 */ 3948 chg = 0; 3949 per = np->msgin[3]; 3950 ofs = np->msgin[4]; 3951 3952 /* 3953 * Check values against our limits. 3954 */ 3955 if (ofs) { 3956 if (ofs > np->maxoffs) 3957 {chg = 1; ofs = np->maxoffs;} 3958 } 3959 3960 if (ofs) { 3961 if (per < np->minsync) 3962 {chg = 1; per = np->minsync;} 3963 } 3964 3965 /* 3966 * Get new chip synchronous parameters value. 3967 */ 3968 div = fak = 0; 3969 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 3970 goto reject_it; 3971 3972 if (DEBUG_FLAGS & DEBUG_NEGO) { 3973 sym_print_addr(cp->cmd, 3974 "sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 3975 ofs, per, div, fak, chg); 3976 } 3977 3978 /* 3979 * If it was an answer we want to change, 3980 * then it isn't acceptable. Reject it. 3981 */ 3982 if (!req && chg) 3983 goto reject_it; 3984 3985 /* 3986 * Apply new values. 3987 */ 3988 sym_setsync (np, target, ofs, per, div, fak); 3989 3990 /* 3991 * It was an answer. We are done. 3992 */ 3993 if (!req) 3994 return 0; 3995 3996 /* 3997 * It was a request. Prepare an answer message. 3998 */ 3999 np->msgout[0] = M_EXTENDED; 4000 np->msgout[1] = 3; 4001 np->msgout[2] = M_X_SYNC_REQ; 4002 np->msgout[3] = per; 4003 np->msgout[4] = ofs; 4004 4005 if (DEBUG_FLAGS & DEBUG_NEGO) { 4006 sym_print_nego_msg(np, target, "sync msgout", np->msgout); 4007 } 4008 4009 np->msgin [0] = M_NOOP; 4010 4011 return 0; 4012 4013 reject_it: 4014 sym_setsync (np, target, 0, 0, 0, 0); 4015 return -1; 4016 } 4017 4018 static void sym_sync_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4019 { 4020 int req = 1; 4021 int result; 4022 4023 /* 4024 * Request or answer ? 4025 */ 4026 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 4027 OUTB(np, HS_PRT, HS_BUSY); 4028 if (cp->nego_status && cp->nego_status != NS_SYNC) 4029 goto reject_it; 4030 req = 0; 4031 } 4032 4033 /* 4034 * Check and apply new values. 4035 */ 4036 result = sym_sync_nego_check(np, req, cp); 4037 if (result) /* Not acceptable, reject it */ 4038 goto reject_it; 4039 if (req) { /* Was a request, send response. */ 4040 cp->nego_status = NS_SYNC; 4041 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp)); 4042 } 4043 else /* Was a response, we are done. */ 4044 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4045 return; 4046 4047 reject_it: 4048 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4049 } 4050 4051 /* 4052 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 4053 */ 4054 static int 4055 sym_ppr_nego_check(struct sym_hcb *np, int req, int target) 4056 { 4057 struct sym_tcb *tp = &np->target[target]; 4058 unsigned char fak, div; 4059 int dt, chg = 0; 4060 4061 unsigned char per = np->msgin[3]; 4062 unsigned char ofs = np->msgin[5]; 4063 unsigned char wide = np->msgin[6]; 4064 unsigned char opts = np->msgin[7] & PPR_OPT_MASK; 4065 4066 if (DEBUG_FLAGS & DEBUG_NEGO) { 4067 sym_print_nego_msg(np, target, "ppr msgin", np->msgin); 4068 } 4069 4070 /* 4071 * Check values against our limits. 4072 */ 4073 if (wide > np->maxwide) { 4074 chg = 1; 4075 wide = np->maxwide; 4076 } 4077 if (!wide || !(np->features & FE_U3EN)) 4078 opts = 0; 4079 4080 if (opts != (np->msgin[7] & PPR_OPT_MASK)) 4081 chg = 1; 4082 4083 dt = opts & PPR_OPT_DT; 4084 4085 if (ofs) { 4086 unsigned char maxoffs = dt ? np->maxoffs_dt : np->maxoffs; 4087 if (ofs > maxoffs) { 4088 chg = 1; 4089 ofs = maxoffs; 4090 } 4091 } 4092 4093 if (ofs) { 4094 unsigned char minsync = dt ? np->minsync_dt : np->minsync; 4095 if (per < minsync) { 4096 chg = 1; 4097 per = minsync; 4098 } 4099 } 4100 4101 /* 4102 * Get new chip synchronous parameters value. 4103 */ 4104 div = fak = 0; 4105 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 4106 goto reject_it; 4107 4108 /* 4109 * If it was an answer we want to change, 4110 * then it isn't acceptable. Reject it. 4111 */ 4112 if (!req && chg) 4113 goto reject_it; 4114 4115 /* 4116 * Apply new values. 4117 */ 4118 sym_setpprot(np, target, opts, ofs, per, wide, div, fak); 4119 4120 /* 4121 * It was an answer. We are done. 4122 */ 4123 if (!req) 4124 return 0; 4125 4126 /* 4127 * It was a request. Prepare an answer message. 4128 */ 4129 np->msgout[0] = M_EXTENDED; 4130 np->msgout[1] = 6; 4131 np->msgout[2] = M_X_PPR_REQ; 4132 np->msgout[3] = per; 4133 np->msgout[4] = 0; 4134 np->msgout[5] = ofs; 4135 np->msgout[6] = wide; 4136 np->msgout[7] = opts; 4137 4138 if (DEBUG_FLAGS & DEBUG_NEGO) { 4139 sym_print_nego_msg(np, target, "ppr msgout", np->msgout); 4140 } 4141 4142 np->msgin [0] = M_NOOP; 4143 4144 return 0; 4145 4146 reject_it: 4147 sym_setpprot (np, target, 0, 0, 0, 0, 0, 0); 4148 /* 4149 * If it is a device response that should result in 4150 * ST, we may want to try a legacy negotiation later. 4151 */ 4152 if (!req && !opts) { 4153 tp->tgoal.period = per; 4154 tp->tgoal.offset = ofs; 4155 tp->tgoal.width = wide; 4156 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0; 4157 tp->tgoal.check_nego = 1; 4158 } 4159 return -1; 4160 } 4161 4162 static void sym_ppr_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4163 { 4164 int req = 1; 4165 int result; 4166 4167 /* 4168 * Request or answer ? 4169 */ 4170 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 4171 OUTB(np, HS_PRT, HS_BUSY); 4172 if (cp->nego_status && cp->nego_status != NS_PPR) 4173 goto reject_it; 4174 req = 0; 4175 } 4176 4177 /* 4178 * Check and apply new values. 4179 */ 4180 result = sym_ppr_nego_check(np, req, cp->target); 4181 if (result) /* Not acceptable, reject it */ 4182 goto reject_it; 4183 if (req) { /* Was a request, send response. */ 4184 cp->nego_status = NS_PPR; 4185 OUTL_DSP(np, SCRIPTB_BA(np, ppr_resp)); 4186 } 4187 else /* Was a response, we are done. */ 4188 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4189 return; 4190 4191 reject_it: 4192 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4193 } 4194 4195 /* 4196 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 4197 */ 4198 static int 4199 sym_wide_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp) 4200 { 4201 int target = cp->target; 4202 u_char chg, wide; 4203 4204 if (DEBUG_FLAGS & DEBUG_NEGO) { 4205 sym_print_nego_msg(np, target, "wide msgin", np->msgin); 4206 } 4207 4208 /* 4209 * Get requested values. 4210 */ 4211 chg = 0; 4212 wide = np->msgin[3]; 4213 4214 /* 4215 * Check values against our limits. 4216 */ 4217 if (wide > np->maxwide) { 4218 chg = 1; 4219 wide = np->maxwide; 4220 } 4221 4222 if (DEBUG_FLAGS & DEBUG_NEGO) { 4223 sym_print_addr(cp->cmd, "wdtr: wide=%d chg=%d.\n", 4224 wide, chg); 4225 } 4226 4227 /* 4228 * If it was an answer we want to change, 4229 * then it isn't acceptable. Reject it. 4230 */ 4231 if (!req && chg) 4232 goto reject_it; 4233 4234 /* 4235 * Apply new values. 4236 */ 4237 sym_setwide (np, target, wide); 4238 4239 /* 4240 * It was an answer. We are done. 4241 */ 4242 if (!req) 4243 return 0; 4244 4245 /* 4246 * It was a request. Prepare an answer message. 4247 */ 4248 np->msgout[0] = M_EXTENDED; 4249 np->msgout[1] = 2; 4250 np->msgout[2] = M_X_WIDE_REQ; 4251 np->msgout[3] = wide; 4252 4253 np->msgin [0] = M_NOOP; 4254 4255 if (DEBUG_FLAGS & DEBUG_NEGO) { 4256 sym_print_nego_msg(np, target, "wide msgout", np->msgout); 4257 } 4258 4259 return 0; 4260 4261 reject_it: 4262 return -1; 4263 } 4264 4265 static void sym_wide_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4266 { 4267 int req = 1; 4268 int result; 4269 4270 /* 4271 * Request or answer ? 4272 */ 4273 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 4274 OUTB(np, HS_PRT, HS_BUSY); 4275 if (cp->nego_status && cp->nego_status != NS_WIDE) 4276 goto reject_it; 4277 req = 0; 4278 } 4279 4280 /* 4281 * Check and apply new values. 4282 */ 4283 result = sym_wide_nego_check(np, req, cp); 4284 if (result) /* Not acceptable, reject it */ 4285 goto reject_it; 4286 if (req) { /* Was a request, send response. */ 4287 cp->nego_status = NS_WIDE; 4288 OUTL_DSP(np, SCRIPTB_BA(np, wdtr_resp)); 4289 } else { /* Was a response. */ 4290 /* 4291 * Negotiate for SYNC immediately after WIDE response. 4292 * This allows to negotiate for both WIDE and SYNC on 4293 * a single SCSI command (Suggested by Justin Gibbs). 4294 */ 4295 if (tp->tgoal.offset) { 4296 np->msgout[0] = M_EXTENDED; 4297 np->msgout[1] = 3; 4298 np->msgout[2] = M_X_SYNC_REQ; 4299 np->msgout[3] = tp->tgoal.period; 4300 np->msgout[4] = tp->tgoal.offset; 4301 4302 if (DEBUG_FLAGS & DEBUG_NEGO) { 4303 sym_print_nego_msg(np, cp->target, 4304 "sync msgout", np->msgout); 4305 } 4306 4307 cp->nego_status = NS_SYNC; 4308 OUTB(np, HS_PRT, HS_NEGOTIATE); 4309 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp)); 4310 return; 4311 } else 4312 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4313 } 4314 4315 return; 4316 4317 reject_it: 4318 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4319 } 4320 4321 /* 4322 * Reset DT, SYNC or WIDE to default settings. 4323 * 4324 * Called when a negotiation does not succeed either 4325 * on rejection or on protocol error. 4326 * 4327 * A target that understands a PPR message should never 4328 * reject it, and messing with it is very unlikely. 4329 * So, if a PPR makes problems, we may just want to 4330 * try a legacy negotiation later. 4331 */ 4332 static void sym_nego_default(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4333 { 4334 switch (cp->nego_status) { 4335 case NS_PPR: 4336 #if 0 4337 sym_setpprot (np, cp->target, 0, 0, 0, 0, 0, 0); 4338 #else 4339 if (tp->tgoal.period < np->minsync) 4340 tp->tgoal.period = np->minsync; 4341 if (tp->tgoal.offset > np->maxoffs) 4342 tp->tgoal.offset = np->maxoffs; 4343 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0; 4344 tp->tgoal.check_nego = 1; 4345 #endif 4346 break; 4347 case NS_SYNC: 4348 sym_setsync (np, cp->target, 0, 0, 0, 0); 4349 break; 4350 case NS_WIDE: 4351 sym_setwide (np, cp->target, 0); 4352 break; 4353 } 4354 np->msgin [0] = M_NOOP; 4355 np->msgout[0] = M_NOOP; 4356 cp->nego_status = 0; 4357 } 4358 4359 /* 4360 * chip handler for MESSAGE REJECT received in response to 4361 * PPR, WIDE or SYNCHRONOUS negotiation. 4362 */ 4363 static void sym_nego_rejected(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4364 { 4365 sym_nego_default(np, tp, cp); 4366 OUTB(np, HS_PRT, HS_BUSY); 4367 } 4368 4369 /* 4370 * chip exception handler for programmed interrupts. 4371 */ 4372 static void sym_int_sir (struct sym_hcb *np) 4373 { 4374 u_char num = INB(np, nc_dsps); 4375 u32 dsa = INL(np, nc_dsa); 4376 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 4377 u_char target = INB(np, nc_sdid) & 0x0f; 4378 struct sym_tcb *tp = &np->target[target]; 4379 int tmp; 4380 4381 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 4382 4383 switch (num) { 4384 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 4385 /* 4386 * SCRIPTS tell us that we may have to update 4387 * 64 bit DMA segment registers. 4388 */ 4389 case SIR_DMAP_DIRTY: 4390 sym_update_dmap_regs(np); 4391 goto out; 4392 #endif 4393 /* 4394 * Command has been completed with error condition 4395 * or has been auto-sensed. 4396 */ 4397 case SIR_COMPLETE_ERROR: 4398 sym_complete_error(np, cp); 4399 return; 4400 /* 4401 * The C code is currently trying to recover from something. 4402 * Typically, user want to abort some command. 4403 */ 4404 case SIR_SCRIPT_STOPPED: 4405 case SIR_TARGET_SELECTED: 4406 case SIR_ABORT_SENT: 4407 sym_sir_task_recovery(np, num); 4408 return; 4409 /* 4410 * The device didn't go to MSG OUT phase after having 4411 * been selected with ATN. We donnot want to handle 4412 * that. 4413 */ 4414 case SIR_SEL_ATN_NO_MSG_OUT: 4415 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 4416 sym_name (np), target); 4417 goto out_stuck; 4418 /* 4419 * The device didn't switch to MSG IN phase after 4420 * having reseleted the initiator. 4421 */ 4422 case SIR_RESEL_NO_MSG_IN: 4423 printf ("%s:%d: No MSG IN phase after reselection.\n", 4424 sym_name (np), target); 4425 goto out_stuck; 4426 /* 4427 * After reselection, the device sent a message that wasn't 4428 * an IDENTIFY. 4429 */ 4430 case SIR_RESEL_NO_IDENTIFY: 4431 printf ("%s:%d: No IDENTIFY after reselection.\n", 4432 sym_name (np), target); 4433 goto out_stuck; 4434 /* 4435 * The device reselected a LUN we donnot know about. 4436 */ 4437 case SIR_RESEL_BAD_LUN: 4438 np->msgout[0] = M_RESET; 4439 goto out; 4440 /* 4441 * The device reselected for an untagged nexus and we 4442 * haven't any. 4443 */ 4444 case SIR_RESEL_BAD_I_T_L: 4445 np->msgout[0] = M_ABORT; 4446 goto out; 4447 /* 4448 * The device reselected for a tagged nexus that we donnot 4449 * have. 4450 */ 4451 case SIR_RESEL_BAD_I_T_L_Q: 4452 np->msgout[0] = M_ABORT_TAG; 4453 goto out; 4454 /* 4455 * The SCRIPTS let us know that the device has grabbed 4456 * our message and will abort the job. 4457 */ 4458 case SIR_RESEL_ABORTED: 4459 np->lastmsg = np->msgout[0]; 4460 np->msgout[0] = M_NOOP; 4461 printf ("%s:%d: message %x sent on bad reselection.\n", 4462 sym_name (np), target, np->lastmsg); 4463 goto out; 4464 /* 4465 * The SCRIPTS let us know that a message has been 4466 * successfully sent to the device. 4467 */ 4468 case SIR_MSG_OUT_DONE: 4469 np->lastmsg = np->msgout[0]; 4470 np->msgout[0] = M_NOOP; 4471 /* Should we really care of that */ 4472 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 4473 if (cp) { 4474 cp->xerr_status &= ~XE_PARITY_ERR; 4475 if (!cp->xerr_status) 4476 OUTOFFB(np, HF_PRT, HF_EXT_ERR); 4477 } 4478 } 4479 goto out; 4480 /* 4481 * The device didn't send a GOOD SCSI status. 4482 * We may have some work to do prior to allow 4483 * the SCRIPTS processor to continue. 4484 */ 4485 case SIR_BAD_SCSI_STATUS: 4486 if (!cp) 4487 goto out; 4488 sym_sir_bad_scsi_status(np, num, cp); 4489 return; 4490 /* 4491 * We are asked by the SCRIPTS to prepare a 4492 * REJECT message. 4493 */ 4494 case SIR_REJECT_TO_SEND: 4495 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 4496 np->msgout[0] = M_REJECT; 4497 goto out; 4498 /* 4499 * We have been ODD at the end of a DATA IN 4500 * transfer and the device didn't send a 4501 * IGNORE WIDE RESIDUE message. 4502 * It is a data overrun condition. 4503 */ 4504 case SIR_SWIDE_OVERRUN: 4505 if (cp) { 4506 OUTONB(np, HF_PRT, HF_EXT_ERR); 4507 cp->xerr_status |= XE_SWIDE_OVRUN; 4508 } 4509 goto out; 4510 /* 4511 * We have been ODD at the end of a DATA OUT 4512 * transfer. 4513 * It is a data underrun condition. 4514 */ 4515 case SIR_SODL_UNDERRUN: 4516 if (cp) { 4517 OUTONB(np, HF_PRT, HF_EXT_ERR); 4518 cp->xerr_status |= XE_SODL_UNRUN; 4519 } 4520 goto out; 4521 /* 4522 * The device wants us to tranfer more data than 4523 * expected or in the wrong direction. 4524 * The number of extra bytes is in scratcha. 4525 * It is a data overrun condition. 4526 */ 4527 case SIR_DATA_OVERRUN: 4528 if (cp) { 4529 OUTONB(np, HF_PRT, HF_EXT_ERR); 4530 cp->xerr_status |= XE_EXTRA_DATA; 4531 cp->extra_bytes += INL(np, nc_scratcha); 4532 } 4533 goto out; 4534 /* 4535 * The device switched to an illegal phase (4/5). 4536 */ 4537 case SIR_BAD_PHASE: 4538 if (cp) { 4539 OUTONB(np, HF_PRT, HF_EXT_ERR); 4540 cp->xerr_status |= XE_BAD_PHASE; 4541 } 4542 goto out; 4543 /* 4544 * We received a message. 4545 */ 4546 case SIR_MSG_RECEIVED: 4547 if (!cp) 4548 goto out_stuck; 4549 switch (np->msgin [0]) { 4550 /* 4551 * We received an extended message. 4552 * We handle MODIFY DATA POINTER, SDTR, WDTR 4553 * and reject all other extended messages. 4554 */ 4555 case M_EXTENDED: 4556 switch (np->msgin [2]) { 4557 case M_X_MODIFY_DP: 4558 if (DEBUG_FLAGS & DEBUG_POINTER) 4559 sym_print_msg(cp,"modify DP",np->msgin); 4560 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 4561 (np->msgin[5]<<8) + (np->msgin[6]); 4562 sym_modify_dp(np, tp, cp, tmp); 4563 return; 4564 case M_X_SYNC_REQ: 4565 sym_sync_nego(np, tp, cp); 4566 return; 4567 case M_X_PPR_REQ: 4568 sym_ppr_nego(np, tp, cp); 4569 return; 4570 case M_X_WIDE_REQ: 4571 sym_wide_nego(np, tp, cp); 4572 return; 4573 default: 4574 goto out_reject; 4575 } 4576 break; 4577 /* 4578 * We received a 1/2 byte message not handled from SCRIPTS. 4579 * We are only expecting MESSAGE REJECT and IGNORE WIDE 4580 * RESIDUE messages that haven't been anticipated by 4581 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 4582 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 4583 */ 4584 case M_IGN_RESIDUE: 4585 if (DEBUG_FLAGS & DEBUG_POINTER) 4586 sym_print_msg(cp,"ign wide residue", np->msgin); 4587 if (cp->host_flags & HF_SENSE) 4588 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4589 else 4590 sym_modify_dp(np, tp, cp, -1); 4591 return; 4592 case M_REJECT: 4593 if (INB(np, HS_PRT) == HS_NEGOTIATE) 4594 sym_nego_rejected(np, tp, cp); 4595 else { 4596 sym_print_addr(cp->cmd, 4597 "M_REJECT received (%x:%x).\n", 4598 scr_to_cpu(np->lastmsg), np->msgout[0]); 4599 } 4600 goto out_clrack; 4601 break; 4602 default: 4603 goto out_reject; 4604 } 4605 break; 4606 /* 4607 * We received an unknown message. 4608 * Ignore all MSG IN phases and reject it. 4609 */ 4610 case SIR_MSG_WEIRD: 4611 sym_print_msg(cp, "WEIRD message received", np->msgin); 4612 OUTL_DSP(np, SCRIPTB_BA(np, msg_weird)); 4613 return; 4614 /* 4615 * Negotiation failed. 4616 * Target does not send us the reply. 4617 * Remove the HS_NEGOTIATE status. 4618 */ 4619 case SIR_NEGO_FAILED: 4620 OUTB(np, HS_PRT, HS_BUSY); 4621 /* 4622 * Negotiation failed. 4623 * Target does not want answer message. 4624 */ 4625 case SIR_NEGO_PROTO: 4626 sym_nego_default(np, tp, cp); 4627 goto out; 4628 } 4629 4630 out: 4631 OUTONB_STD(); 4632 return; 4633 out_reject: 4634 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4635 return; 4636 out_clrack: 4637 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4638 return; 4639 out_stuck: 4640 return; 4641 } 4642 4643 /* 4644 * Acquire a control block 4645 */ 4646 struct sym_ccb *sym_get_ccb (struct sym_hcb *np, struct scsi_cmnd *cmd, u_char tag_order) 4647 { 4648 u_char tn = cmd->device->id; 4649 u_char ln = cmd->device->lun; 4650 struct sym_tcb *tp = &np->target[tn]; 4651 struct sym_lcb *lp = sym_lp(tp, ln); 4652 u_short tag = NO_TAG; 4653 SYM_QUEHEAD *qp; 4654 struct sym_ccb *cp = NULL; 4655 4656 /* 4657 * Look for a free CCB 4658 */ 4659 if (sym_que_empty(&np->free_ccbq)) 4660 sym_alloc_ccb(np); 4661 qp = sym_remque_head(&np->free_ccbq); 4662 if (!qp) 4663 goto out; 4664 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4665 4666 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4667 /* 4668 * If the LCB is not yet available and the LUN 4669 * has been probed ok, try to allocate the LCB. 4670 */ 4671 if (!lp && sym_is_bit(tp->lun_map, ln)) { 4672 lp = sym_alloc_lcb(np, tn, ln); 4673 if (!lp) 4674 goto out_free; 4675 } 4676 #endif 4677 4678 /* 4679 * If the LCB is not available here, then the 4680 * logical unit is not yet discovered. For those 4681 * ones only accept 1 SCSI IO per logical unit, 4682 * since we cannot allow disconnections. 4683 */ 4684 if (!lp) { 4685 if (!sym_is_bit(tp->busy0_map, ln)) 4686 sym_set_bit(tp->busy0_map, ln); 4687 else 4688 goto out_free; 4689 } else { 4690 /* 4691 * If we have been asked for a tagged command. 4692 */ 4693 if (tag_order) { 4694 /* 4695 * Debugging purpose. 4696 */ 4697 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4698 assert(lp->busy_itl == 0); 4699 #endif 4700 /* 4701 * Allocate resources for tags if not yet. 4702 */ 4703 if (!lp->cb_tags) { 4704 sym_alloc_lcb_tags(np, tn, ln); 4705 if (!lp->cb_tags) 4706 goto out_free; 4707 } 4708 /* 4709 * Get a tag for this SCSI IO and set up 4710 * the CCB bus address for reselection, 4711 * and count it for this LUN. 4712 * Toggle reselect path to tagged. 4713 */ 4714 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 4715 tag = lp->cb_tags[lp->ia_tag]; 4716 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 4717 lp->ia_tag = 0; 4718 ++lp->busy_itlq; 4719 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4720 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 4721 lp->head.resel_sa = 4722 cpu_to_scr(SCRIPTA_BA(np, resel_tag)); 4723 #endif 4724 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 4725 cp->tags_si = lp->tags_si; 4726 ++lp->tags_sum[cp->tags_si]; 4727 ++lp->tags_since; 4728 #endif 4729 } 4730 else 4731 goto out_free; 4732 } 4733 /* 4734 * This command will not be tagged. 4735 * If we already have either a tagged or untagged 4736 * one, refuse to overlap this untagged one. 4737 */ 4738 else { 4739 /* 4740 * Debugging purpose. 4741 */ 4742 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4743 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 4744 #endif 4745 /* 4746 * Count this nexus for this LUN. 4747 * Set up the CCB bus address for reselection. 4748 * Toggle reselect path to untagged. 4749 */ 4750 ++lp->busy_itl; 4751 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4752 if (lp->busy_itl == 1) { 4753 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 4754 lp->head.resel_sa = 4755 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag)); 4756 } 4757 else 4758 goto out_free; 4759 #endif 4760 } 4761 } 4762 /* 4763 * Put the CCB into the busy queue. 4764 */ 4765 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4766 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4767 if (lp) { 4768 sym_remque(&cp->link2_ccbq); 4769 sym_insque_tail(&cp->link2_ccbq, &lp->waiting_ccbq); 4770 } 4771 4772 #endif 4773 cp->to_abort = 0; 4774 cp->odd_byte_adjustment = 0; 4775 cp->tag = tag; 4776 cp->order = tag_order; 4777 cp->target = tn; 4778 cp->lun = ln; 4779 4780 if (DEBUG_FLAGS & DEBUG_TAGS) { 4781 sym_print_addr(cmd, "ccb @%p using tag %d.\n", cp, tag); 4782 } 4783 4784 out: 4785 return cp; 4786 out_free: 4787 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4788 return NULL; 4789 } 4790 4791 /* 4792 * Release one control block 4793 */ 4794 void sym_free_ccb (struct sym_hcb *np, struct sym_ccb *cp) 4795 { 4796 struct sym_tcb *tp = &np->target[cp->target]; 4797 struct sym_lcb *lp = sym_lp(tp, cp->lun); 4798 4799 if (DEBUG_FLAGS & DEBUG_TAGS) { 4800 sym_print_addr(cp->cmd, "ccb @%p freeing tag %d.\n", 4801 cp, cp->tag); 4802 } 4803 4804 /* 4805 * If LCB available, 4806 */ 4807 if (lp) { 4808 /* 4809 * If tagged, release the tag, set the relect path 4810 */ 4811 if (cp->tag != NO_TAG) { 4812 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 4813 --lp->tags_sum[cp->tags_si]; 4814 #endif 4815 /* 4816 * Free the tag value. 4817 */ 4818 lp->cb_tags[lp->if_tag] = cp->tag; 4819 if (++lp->if_tag == SYM_CONF_MAX_TASK) 4820 lp->if_tag = 0; 4821 /* 4822 * Make the reselect path invalid, 4823 * and uncount this CCB. 4824 */ 4825 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 4826 --lp->busy_itlq; 4827 } else { /* Untagged */ 4828 /* 4829 * Make the reselect path invalid, 4830 * and uncount this CCB. 4831 */ 4832 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 4833 --lp->busy_itl; 4834 } 4835 /* 4836 * If no JOB active, make the LUN reselect path invalid. 4837 */ 4838 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 4839 lp->head.resel_sa = 4840 cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 4841 } 4842 /* 4843 * Otherwise, we only accept 1 IO per LUN. 4844 * Clear the bit that keeps track of this IO. 4845 */ 4846 else 4847 sym_clr_bit(tp->busy0_map, cp->lun); 4848 4849 /* 4850 * We donnot queue more than 1 ccb per target 4851 * with negotiation at any time. If this ccb was 4852 * used for negotiation, clear this info in the tcb. 4853 */ 4854 if (cp == tp->nego_cp) 4855 tp->nego_cp = NULL; 4856 4857 #ifdef SYM_CONF_IARB_SUPPORT 4858 /* 4859 * If we just complete the last queued CCB, 4860 * clear this info that is no longer relevant. 4861 */ 4862 if (cp == np->last_cp) 4863 np->last_cp = 0; 4864 #endif 4865 4866 /* 4867 * Make this CCB available. 4868 */ 4869 cp->cmd = NULL; 4870 cp->host_status = HS_IDLE; 4871 sym_remque(&cp->link_ccbq); 4872 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4873 4874 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4875 if (lp) { 4876 sym_remque(&cp->link2_ccbq); 4877 sym_insque_tail(&cp->link2_ccbq, &np->dummy_ccbq); 4878 if (cp->started) { 4879 if (cp->tag != NO_TAG) 4880 --lp->started_tags; 4881 else 4882 --lp->started_no_tag; 4883 } 4884 } 4885 cp->started = 0; 4886 #endif 4887 } 4888 4889 /* 4890 * Allocate a CCB from memory and initialize its fixed part. 4891 */ 4892 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np) 4893 { 4894 struct sym_ccb *cp = NULL; 4895 int hcode; 4896 4897 /* 4898 * Prevent from allocating more CCBs than we can 4899 * queue to the controller. 4900 */ 4901 if (np->actccbs >= SYM_CONF_MAX_START) 4902 return NULL; 4903 4904 /* 4905 * Allocate memory for this CCB. 4906 */ 4907 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 4908 if (!cp) 4909 goto out_free; 4910 4911 /* 4912 * Count it. 4913 */ 4914 np->actccbs++; 4915 4916 /* 4917 * Compute the bus address of this ccb. 4918 */ 4919 cp->ccb_ba = vtobus(cp); 4920 4921 /* 4922 * Insert this ccb into the hashed list. 4923 */ 4924 hcode = CCB_HASH_CODE(cp->ccb_ba); 4925 cp->link_ccbh = np->ccbh[hcode]; 4926 np->ccbh[hcode] = cp; 4927 4928 /* 4929 * Initialyze the start and restart actions. 4930 */ 4931 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 4932 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 4933 4934 /* 4935 * Initilialyze some other fields. 4936 */ 4937 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 4938 4939 /* 4940 * Chain into free ccb queue. 4941 */ 4942 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4943 4944 /* 4945 * Chain into optionnal lists. 4946 */ 4947 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4948 sym_insque_head(&cp->link2_ccbq, &np->dummy_ccbq); 4949 #endif 4950 return cp; 4951 out_free: 4952 if (cp) 4953 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 4954 return NULL; 4955 } 4956 4957 /* 4958 * Look up a CCB from a DSA value. 4959 */ 4960 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa) 4961 { 4962 int hcode; 4963 struct sym_ccb *cp; 4964 4965 hcode = CCB_HASH_CODE(dsa); 4966 cp = np->ccbh[hcode]; 4967 while (cp) { 4968 if (cp->ccb_ba == dsa) 4969 break; 4970 cp = cp->link_ccbh; 4971 } 4972 4973 return cp; 4974 } 4975 4976 /* 4977 * Target control block initialisation. 4978 * Nothing important to do at the moment. 4979 */ 4980 static void sym_init_tcb (struct sym_hcb *np, u_char tn) 4981 { 4982 #if 0 /* Hmmm... this checking looks paranoid. */ 4983 /* 4984 * Check some alignments required by the chip. 4985 */ 4986 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 4987 offsetof(struct sym_tcb, head.sval)) &3) == 0); 4988 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 4989 offsetof(struct sym_tcb, head.wval)) &3) == 0); 4990 #endif 4991 } 4992 4993 /* 4994 * Lun control block allocation and initialization. 4995 */ 4996 struct sym_lcb *sym_alloc_lcb (struct sym_hcb *np, u_char tn, u_char ln) 4997 { 4998 struct sym_tcb *tp = &np->target[tn]; 4999 struct sym_lcb *lp = sym_lp(tp, ln); 5000 5001 /* 5002 * Already done, just return. 5003 */ 5004 if (lp) 5005 return lp; 5006 5007 /* 5008 * Donnot allow LUN control block 5009 * allocation for not probed LUNs. 5010 */ 5011 if (!sym_is_bit(tp->lun_map, ln)) 5012 return NULL; 5013 5014 /* 5015 * Initialize the target control block if not yet. 5016 */ 5017 sym_init_tcb (np, tn); 5018 5019 /* 5020 * Allocate the LCB bus address array. 5021 * Compute the bus address of this table. 5022 */ 5023 if (ln && !tp->luntbl) { 5024 int i; 5025 5026 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 5027 if (!tp->luntbl) 5028 goto fail; 5029 for (i = 0 ; i < 64 ; i++) 5030 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 5031 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 5032 } 5033 5034 /* 5035 * Allocate the table of pointers for LUN(s) > 0, if needed. 5036 */ 5037 if (ln && !tp->lunmp) { 5038 tp->lunmp = kcalloc(SYM_CONF_MAX_LUN, sizeof(struct sym_lcb *), 5039 GFP_KERNEL); 5040 if (!tp->lunmp) 5041 goto fail; 5042 } 5043 5044 /* 5045 * Allocate the lcb. 5046 * Make it available to the chip. 5047 */ 5048 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 5049 if (!lp) 5050 goto fail; 5051 if (ln) { 5052 tp->lunmp[ln] = lp; 5053 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 5054 } 5055 else { 5056 tp->lun0p = lp; 5057 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 5058 } 5059 5060 /* 5061 * Let the itl task point to error handling. 5062 */ 5063 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 5064 5065 /* 5066 * Set the reselect pattern to our default. :) 5067 */ 5068 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 5069 5070 /* 5071 * Set user capabilities. 5072 */ 5073 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 5074 5075 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5076 /* 5077 * Initialize device queueing. 5078 */ 5079 sym_que_init(&lp->waiting_ccbq); 5080 sym_que_init(&lp->started_ccbq); 5081 lp->started_max = SYM_CONF_MAX_TASK; 5082 lp->started_limit = SYM_CONF_MAX_TASK; 5083 #endif 5084 /* 5085 * If we are busy, count the IO. 5086 */ 5087 if (sym_is_bit(tp->busy0_map, ln)) { 5088 lp->busy_itl = 1; 5089 sym_clr_bit(tp->busy0_map, ln); 5090 } 5091 fail: 5092 return lp; 5093 } 5094 5095 /* 5096 * Allocate LCB resources for tagged command queuing. 5097 */ 5098 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln) 5099 { 5100 struct sym_tcb *tp = &np->target[tn]; 5101 struct sym_lcb *lp = sym_lp(tp, ln); 5102 int i; 5103 5104 /* 5105 * If LCB not available, try to allocate it. 5106 */ 5107 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 5108 goto fail; 5109 5110 /* 5111 * Allocate the task table and and the tag allocation 5112 * circular buffer. We want both or none. 5113 */ 5114 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 5115 if (!lp->itlq_tbl) 5116 goto fail; 5117 lp->cb_tags = kcalloc(SYM_CONF_MAX_TASK, 1, GFP_ATOMIC); 5118 if (!lp->cb_tags) { 5119 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 5120 lp->itlq_tbl = NULL; 5121 goto fail; 5122 } 5123 5124 /* 5125 * Initialize the task table with invalid entries. 5126 */ 5127 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 5128 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 5129 5130 /* 5131 * Fill up the tag buffer with tag numbers. 5132 */ 5133 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 5134 lp->cb_tags[i] = i; 5135 5136 /* 5137 * Make the task table available to SCRIPTS, 5138 * And accept tagged commands now. 5139 */ 5140 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 5141 5142 return; 5143 fail: 5144 return; 5145 } 5146 5147 /* 5148 * Queue a SCSI IO to the controller. 5149 */ 5150 int sym_queue_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, struct sym_ccb *cp) 5151 { 5152 struct scsi_device *sdev = cmd->device; 5153 struct sym_tcb *tp; 5154 struct sym_lcb *lp; 5155 u_char *msgptr; 5156 u_int msglen; 5157 int can_disconnect; 5158 5159 /* 5160 * Keep track of the IO in our CCB. 5161 */ 5162 cp->cmd = cmd; 5163 5164 /* 5165 * Retrieve the target descriptor. 5166 */ 5167 tp = &np->target[cp->target]; 5168 5169 /* 5170 * Retrieve the lun descriptor. 5171 */ 5172 lp = sym_lp(tp, sdev->lun); 5173 5174 can_disconnect = (cp->tag != NO_TAG) || 5175 (lp && (lp->curr_flags & SYM_DISC_ENABLED)); 5176 5177 msgptr = cp->scsi_smsg; 5178 msglen = 0; 5179 msgptr[msglen++] = IDENTIFY(can_disconnect, sdev->lun); 5180 5181 /* 5182 * Build the tag message if present. 5183 */ 5184 if (cp->tag != NO_TAG) { 5185 u_char order = cp->order; 5186 5187 switch(order) { 5188 case M_ORDERED_TAG: 5189 break; 5190 case M_HEAD_TAG: 5191 break; 5192 default: 5193 order = M_SIMPLE_TAG; 5194 } 5195 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 5196 /* 5197 * Avoid too much reordering of SCSI commands. 5198 * The algorithm tries to prevent completion of any 5199 * tagged command from being delayed against more 5200 * than 3 times the max number of queued commands. 5201 */ 5202 if (lp && lp->tags_since > 3*SYM_CONF_MAX_TAG) { 5203 lp->tags_si = !(lp->tags_si); 5204 if (lp->tags_sum[lp->tags_si]) { 5205 order = M_ORDERED_TAG; 5206 if ((DEBUG_FLAGS & DEBUG_TAGS)||sym_verbose>1) { 5207 sym_print_addr(cmd, 5208 "ordered tag forced.\n"); 5209 } 5210 } 5211 lp->tags_since = 0; 5212 } 5213 #endif 5214 msgptr[msglen++] = order; 5215 5216 /* 5217 * For less than 128 tags, actual tags are numbered 5218 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 5219 * with devices that have problems with #TAG 0 or too 5220 * great #TAG numbers. For more tags (up to 256), 5221 * we use directly our tag number. 5222 */ 5223 #if SYM_CONF_MAX_TASK > (512/4) 5224 msgptr[msglen++] = cp->tag; 5225 #else 5226 msgptr[msglen++] = (cp->tag << 1) + 1; 5227 #endif 5228 } 5229 5230 /* 5231 * Build a negotiation message if needed. 5232 * (nego_status is filled by sym_prepare_nego()) 5233 */ 5234 cp->nego_status = 0; 5235 if (tp->tgoal.check_nego && !tp->nego_cp && lp) { 5236 msglen += sym_prepare_nego(np, cp, msgptr + msglen); 5237 } 5238 5239 /* 5240 * Startqueue 5241 */ 5242 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select)); 5243 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA(np, resel_dsa)); 5244 5245 /* 5246 * select 5247 */ 5248 cp->phys.select.sel_id = cp->target; 5249 cp->phys.select.sel_scntl3 = tp->head.wval; 5250 cp->phys.select.sel_sxfer = tp->head.sval; 5251 cp->phys.select.sel_scntl4 = tp->head.uval; 5252 5253 /* 5254 * message 5255 */ 5256 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg); 5257 cp->phys.smsg.size = cpu_to_scr(msglen); 5258 5259 /* 5260 * status 5261 */ 5262 cp->host_xflags = 0; 5263 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 5264 cp->ssss_status = S_ILLEGAL; 5265 cp->xerr_status = 0; 5266 cp->host_flags = 0; 5267 cp->extra_bytes = 0; 5268 5269 /* 5270 * extreme data pointer. 5271 * shall be positive, so -1 is lower than lowest.:) 5272 */ 5273 cp->ext_sg = -1; 5274 cp->ext_ofs = 0; 5275 5276 /* 5277 * Build the CDB and DATA descriptor block 5278 * and start the IO. 5279 */ 5280 return sym_setup_data_and_start(np, cmd, cp); 5281 } 5282 5283 /* 5284 * Reset a SCSI target (all LUNs of this target). 5285 */ 5286 int sym_reset_scsi_target(struct sym_hcb *np, int target) 5287 { 5288 struct sym_tcb *tp; 5289 5290 if (target == np->myaddr || (u_int)target >= SYM_CONF_MAX_TARGET) 5291 return -1; 5292 5293 tp = &np->target[target]; 5294 tp->to_reset = 1; 5295 5296 np->istat_sem = SEM; 5297 OUTB(np, nc_istat, SIGP|SEM); 5298 5299 return 0; 5300 } 5301 5302 /* 5303 * Abort a SCSI IO. 5304 */ 5305 static int sym_abort_ccb(struct sym_hcb *np, struct sym_ccb *cp, int timed_out) 5306 { 5307 /* 5308 * Check that the IO is active. 5309 */ 5310 if (!cp || !cp->host_status || cp->host_status == HS_WAIT) 5311 return -1; 5312 5313 /* 5314 * If a previous abort didn't succeed in time, 5315 * perform a BUS reset. 5316 */ 5317 if (cp->to_abort) { 5318 sym_reset_scsi_bus(np, 1); 5319 return 0; 5320 } 5321 5322 /* 5323 * Mark the CCB for abort and allow time for. 5324 */ 5325 cp->to_abort = timed_out ? 2 : 1; 5326 5327 /* 5328 * Tell the SCRIPTS processor to stop and synchronize with us. 5329 */ 5330 np->istat_sem = SEM; 5331 OUTB(np, nc_istat, SIGP|SEM); 5332 return 0; 5333 } 5334 5335 int sym_abort_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, int timed_out) 5336 { 5337 struct sym_ccb *cp; 5338 SYM_QUEHEAD *qp; 5339 5340 /* 5341 * Look up our CCB control block. 5342 */ 5343 cp = NULL; 5344 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5345 struct sym_ccb *cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5346 if (cp2->cmd == cmd) { 5347 cp = cp2; 5348 break; 5349 } 5350 } 5351 5352 return sym_abort_ccb(np, cp, timed_out); 5353 } 5354 5355 /* 5356 * Complete execution of a SCSI command with extended 5357 * error, SCSI status error, or having been auto-sensed. 5358 * 5359 * The SCRIPTS processor is not running there, so we 5360 * can safely access IO registers and remove JOBs from 5361 * the START queue. 5362 * SCRATCHA is assumed to have been loaded with STARTPOS 5363 * before the SCRIPTS called the C code. 5364 */ 5365 void sym_complete_error(struct sym_hcb *np, struct sym_ccb *cp) 5366 { 5367 struct scsi_device *sdev; 5368 struct scsi_cmnd *cmd; 5369 struct sym_tcb *tp; 5370 struct sym_lcb *lp; 5371 int resid; 5372 int i; 5373 5374 /* 5375 * Paranoid check. :) 5376 */ 5377 if (!cp || !cp->cmd) 5378 return; 5379 5380 cmd = cp->cmd; 5381 sdev = cmd->device; 5382 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 5383 dev_info(&sdev->sdev_gendev, "CCB=%p STAT=%x/%x/%x\n", cp, 5384 cp->host_status, cp->ssss_status, cp->host_flags); 5385 } 5386 5387 /* 5388 * Get target and lun pointers. 5389 */ 5390 tp = &np->target[cp->target]; 5391 lp = sym_lp(tp, sdev->lun); 5392 5393 /* 5394 * Check for extended errors. 5395 */ 5396 if (cp->xerr_status) { 5397 if (sym_verbose) 5398 sym_print_xerr(cmd, cp->xerr_status); 5399 if (cp->host_status == HS_COMPLETE) 5400 cp->host_status = HS_COMP_ERR; 5401 } 5402 5403 /* 5404 * Calculate the residual. 5405 */ 5406 resid = sym_compute_residual(np, cp); 5407 5408 if (!SYM_SETUP_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 5409 resid = 0; /* throw them away. :) */ 5410 cp->sv_resid = 0; 5411 } 5412 #ifdef DEBUG_2_0_X 5413 if (resid) 5414 printf("XXXX RESID= %d - 0x%x\n", resid, resid); 5415 #endif 5416 5417 /* 5418 * Dequeue all queued CCBs for that device 5419 * not yet started by SCRIPTS. 5420 */ 5421 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 5422 i = sym_dequeue_from_squeue(np, i, cp->target, sdev->lun, -1); 5423 5424 /* 5425 * Restart the SCRIPTS processor. 5426 */ 5427 OUTL_DSP(np, SCRIPTA_BA(np, start)); 5428 5429 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5430 if (cp->host_status == HS_COMPLETE && 5431 cp->ssss_status == S_QUEUE_FULL) { 5432 if (!lp || lp->started_tags - i < 2) 5433 goto weirdness; 5434 /* 5435 * Decrease queue depth as needed. 5436 */ 5437 lp->started_max = lp->started_tags - i - 1; 5438 lp->num_sgood = 0; 5439 5440 if (sym_verbose >= 2) { 5441 sym_print_addr(cmd, " queue depth is now %d\n", 5442 lp->started_max); 5443 } 5444 5445 /* 5446 * Repair the CCB. 5447 */ 5448 cp->host_status = HS_BUSY; 5449 cp->ssss_status = S_ILLEGAL; 5450 5451 /* 5452 * Let's requeue it to device. 5453 */ 5454 sym_set_cam_status(cmd, DID_SOFT_ERROR); 5455 goto finish; 5456 } 5457 weirdness: 5458 #endif 5459 /* 5460 * Build result in CAM ccb. 5461 */ 5462 sym_set_cam_result_error(np, cp, resid); 5463 5464 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5465 finish: 5466 #endif 5467 /* 5468 * Add this one to the COMP queue. 5469 */ 5470 sym_remque(&cp->link_ccbq); 5471 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 5472 5473 /* 5474 * Complete all those commands with either error 5475 * or requeue condition. 5476 */ 5477 sym_flush_comp_queue(np, 0); 5478 5479 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5480 /* 5481 * Donnot start more than 1 command after an error. 5482 */ 5483 if (lp) 5484 sym_start_next_ccbs(np, lp, 1); 5485 #endif 5486 } 5487 5488 /* 5489 * Complete execution of a successful SCSI command. 5490 * 5491 * Only successful commands go to the DONE queue, 5492 * since we need to have the SCRIPTS processor 5493 * stopped on any error condition. 5494 * The SCRIPTS processor is running while we are 5495 * completing successful commands. 5496 */ 5497 void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp) 5498 { 5499 struct sym_tcb *tp; 5500 struct sym_lcb *lp; 5501 struct scsi_cmnd *cmd; 5502 int resid; 5503 5504 /* 5505 * Paranoid check. :) 5506 */ 5507 if (!cp || !cp->cmd) 5508 return; 5509 assert (cp->host_status == HS_COMPLETE); 5510 5511 /* 5512 * Get user command. 5513 */ 5514 cmd = cp->cmd; 5515 5516 /* 5517 * Get target and lun pointers. 5518 */ 5519 tp = &np->target[cp->target]; 5520 lp = sym_lp(tp, cp->lun); 5521 5522 /* 5523 * Assume device discovered on first success. 5524 */ 5525 if (!lp) 5526 sym_set_bit(tp->lun_map, cp->lun); 5527 5528 /* 5529 * If all data have been transferred, given than no 5530 * extended error did occur, there is no residual. 5531 */ 5532 resid = 0; 5533 if (cp->phys.head.lastp != sym_goalp(cp)) 5534 resid = sym_compute_residual(np, cp); 5535 5536 /* 5537 * Wrong transfer residuals may be worse than just always 5538 * returning zero. User can disable this feature in 5539 * sym53c8xx.h. Residual support is enabled by default. 5540 */ 5541 if (!SYM_SETUP_RESIDUAL_SUPPORT) 5542 resid = 0; 5543 #ifdef DEBUG_2_0_X 5544 if (resid) 5545 printf("XXXX RESID= %d - 0x%x\n", resid, resid); 5546 #endif 5547 5548 /* 5549 * Build result in CAM ccb. 5550 */ 5551 sym_set_cam_result_ok(cp, cmd, resid); 5552 5553 #ifdef SYM_OPT_SNIFF_INQUIRY 5554 /* 5555 * On standard INQUIRY response (EVPD and CmDt 5556 * not set), sniff out device capabilities. 5557 */ 5558 if (cp->cdb_buf[0] == INQUIRY && !(cp->cdb_buf[1] & 0x3)) 5559 sym_sniff_inquiry(np, cmd, resid); 5560 #endif 5561 5562 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5563 /* 5564 * If max number of started ccbs had been reduced, 5565 * increase it if 200 good status received. 5566 */ 5567 if (lp && lp->started_max < lp->started_limit) { 5568 ++lp->num_sgood; 5569 if (lp->num_sgood >= 200) { 5570 lp->num_sgood = 0; 5571 ++lp->started_max; 5572 if (sym_verbose >= 2) { 5573 sym_print_addr(cmd, " queue depth is now %d\n", 5574 lp->started_max); 5575 } 5576 } 5577 } 5578 #endif 5579 5580 /* 5581 * Free our CCB. 5582 */ 5583 sym_free_ccb (np, cp); 5584 5585 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5586 /* 5587 * Requeue a couple of awaiting scsi commands. 5588 */ 5589 if (lp && !sym_que_empty(&lp->waiting_ccbq)) 5590 sym_start_next_ccbs(np, lp, 2); 5591 #endif 5592 /* 5593 * Complete the command. 5594 */ 5595 sym_xpt_done(np, cmd); 5596 } 5597 5598 /* 5599 * Soft-attach the controller. 5600 */ 5601 int sym_hcb_attach(struct Scsi_Host *shost, struct sym_fw *fw, struct sym_nvram *nvram) 5602 { 5603 struct sym_hcb *np = sym_get_hcb(shost); 5604 int i; 5605 5606 /* 5607 * Get some info about the firmware. 5608 */ 5609 np->scripta_sz = fw->a_size; 5610 np->scriptb_sz = fw->b_size; 5611 np->scriptz_sz = fw->z_size; 5612 np->fw_setup = fw->setup; 5613 np->fw_patch = fw->patch; 5614 np->fw_name = fw->name; 5615 5616 /* 5617 * Save setting of some IO registers, so we will 5618 * be able to probe specific implementations. 5619 */ 5620 sym_save_initial_setting (np); 5621 5622 /* 5623 * Reset the chip now, since it has been reported 5624 * that SCSI clock calibration may not work properly 5625 * if the chip is currently active. 5626 */ 5627 sym_chip_reset(np); 5628 5629 /* 5630 * Prepare controller and devices settings, according 5631 * to chip features, user set-up and driver set-up. 5632 */ 5633 sym_prepare_setting(shost, np, nvram); 5634 5635 /* 5636 * Check the PCI clock frequency. 5637 * Must be performed after prepare_setting since it destroys 5638 * STEST1 that is used to probe for the clock doubler. 5639 */ 5640 i = sym_getpciclock(np); 5641 if (i > 37000 && !(np->features & FE_66MHZ)) 5642 printf("%s: PCI BUS clock seems too high: %u KHz.\n", 5643 sym_name(np), i); 5644 5645 /* 5646 * Allocate the start queue. 5647 */ 5648 np->squeue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 5649 if (!np->squeue) 5650 goto attach_failed; 5651 np->squeue_ba = vtobus(np->squeue); 5652 5653 /* 5654 * Allocate the done queue. 5655 */ 5656 np->dqueue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 5657 if (!np->dqueue) 5658 goto attach_failed; 5659 np->dqueue_ba = vtobus(np->dqueue); 5660 5661 /* 5662 * Allocate the target bus address array. 5663 */ 5664 np->targtbl = sym_calloc_dma(256, "TARGTBL"); 5665 if (!np->targtbl) 5666 goto attach_failed; 5667 np->targtbl_ba = vtobus(np->targtbl); 5668 5669 /* 5670 * Allocate SCRIPTS areas. 5671 */ 5672 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 5673 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 5674 np->scriptz0 = sym_calloc_dma(np->scriptz_sz, "SCRIPTZ0"); 5675 if (!np->scripta0 || !np->scriptb0 || !np->scriptz0) 5676 goto attach_failed; 5677 5678 /* 5679 * Allocate the array of lists of CCBs hashed by DSA. 5680 */ 5681 np->ccbh = kcalloc(sizeof(struct sym_ccb **), CCB_HASH_SIZE, GFP_KERNEL); 5682 if (!np->ccbh) 5683 goto attach_failed; 5684 5685 /* 5686 * Initialyze the CCB free and busy queues. 5687 */ 5688 sym_que_init(&np->free_ccbq); 5689 sym_que_init(&np->busy_ccbq); 5690 sym_que_init(&np->comp_ccbq); 5691 5692 /* 5693 * Initialization for optional handling 5694 * of device queueing. 5695 */ 5696 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5697 sym_que_init(&np->dummy_ccbq); 5698 #endif 5699 /* 5700 * Allocate some CCB. We need at least ONE. 5701 */ 5702 if (!sym_alloc_ccb(np)) 5703 goto attach_failed; 5704 5705 /* 5706 * Calculate BUS addresses where we are going 5707 * to load the SCRIPTS. 5708 */ 5709 np->scripta_ba = vtobus(np->scripta0); 5710 np->scriptb_ba = vtobus(np->scriptb0); 5711 np->scriptz_ba = vtobus(np->scriptz0); 5712 5713 if (np->ram_ba) { 5714 np->scripta_ba = np->ram_ba; 5715 if (np->features & FE_RAM8K) { 5716 np->ram_ws = 8192; 5717 np->scriptb_ba = np->scripta_ba + 4096; 5718 #if 0 /* May get useful for 64 BIT PCI addressing */ 5719 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 5720 #endif 5721 } 5722 else 5723 np->ram_ws = 4096; 5724 } 5725 5726 /* 5727 * Copy scripts to controller instance. 5728 */ 5729 memcpy(np->scripta0, fw->a_base, np->scripta_sz); 5730 memcpy(np->scriptb0, fw->b_base, np->scriptb_sz); 5731 memcpy(np->scriptz0, fw->z_base, np->scriptz_sz); 5732 5733 /* 5734 * Setup variable parts in scripts and compute 5735 * scripts bus addresses used from the C code. 5736 */ 5737 np->fw_setup(np, fw); 5738 5739 /* 5740 * Bind SCRIPTS with physical addresses usable by the 5741 * SCRIPTS processor (as seen from the BUS = BUS addresses). 5742 */ 5743 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 5744 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 5745 sym_fw_bind_script(np, (u32 *) np->scriptz0, np->scriptz_sz); 5746 5747 #ifdef SYM_CONF_IARB_SUPPORT 5748 /* 5749 * If user wants IARB to be set when we win arbitration 5750 * and have other jobs, compute the max number of consecutive 5751 * settings of IARB hints before we leave devices a chance to 5752 * arbitrate for reselection. 5753 */ 5754 #ifdef SYM_SETUP_IARB_MAX 5755 np->iarb_max = SYM_SETUP_IARB_MAX; 5756 #else 5757 np->iarb_max = 4; 5758 #endif 5759 #endif 5760 5761 /* 5762 * Prepare the idle and invalid task actions. 5763 */ 5764 np->idletask.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5765 np->idletask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5766 np->idletask_ba = vtobus(&np->idletask); 5767 5768 np->notask.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5769 np->notask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5770 np->notask_ba = vtobus(&np->notask); 5771 5772 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5773 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5774 np->bad_itl_ba = vtobus(&np->bad_itl); 5775 5776 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5777 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA(np,bad_i_t_l_q)); 5778 np->bad_itlq_ba = vtobus(&np->bad_itlq); 5779 5780 /* 5781 * Allocate and prepare the lun JUMP table that is used 5782 * for a target prior the probing of devices (bad lun table). 5783 * A private table will be allocated for the target on the 5784 * first INQUIRY response received. 5785 */ 5786 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 5787 if (!np->badluntbl) 5788 goto attach_failed; 5789 5790 np->badlun_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 5791 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 5792 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 5793 5794 /* 5795 * Prepare the bus address array that contains the bus 5796 * address of each target control block. 5797 * For now, assume all logical units are wrong. :) 5798 */ 5799 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 5800 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 5801 np->target[i].head.luntbl_sa = 5802 cpu_to_scr(vtobus(np->badluntbl)); 5803 np->target[i].head.lun0_sa = 5804 cpu_to_scr(vtobus(&np->badlun_sa)); 5805 } 5806 5807 /* 5808 * Now check the cache handling of the pci chipset. 5809 */ 5810 if (sym_snooptest (np)) { 5811 printf("%s: CACHE INCORRECTLY CONFIGURED.\n", sym_name(np)); 5812 goto attach_failed; 5813 } 5814 5815 /* 5816 * Sigh! we are done. 5817 */ 5818 return 0; 5819 5820 attach_failed: 5821 return -ENXIO; 5822 } 5823 5824 /* 5825 * Free everything that has been allocated for this device. 5826 */ 5827 void sym_hcb_free(struct sym_hcb *np) 5828 { 5829 SYM_QUEHEAD *qp; 5830 struct sym_ccb *cp; 5831 struct sym_tcb *tp; 5832 struct sym_lcb *lp; 5833 int target, lun; 5834 5835 if (np->scriptz0) 5836 sym_mfree_dma(np->scriptz0, np->scriptz_sz, "SCRIPTZ0"); 5837 if (np->scriptb0) 5838 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 5839 if (np->scripta0) 5840 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 5841 if (np->squeue) 5842 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 5843 if (np->dqueue) 5844 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 5845 5846 if (np->actccbs) { 5847 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) { 5848 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5849 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 5850 } 5851 } 5852 kfree(np->ccbh); 5853 5854 if (np->badluntbl) 5855 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 5856 5857 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 5858 tp = &np->target[target]; 5859 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 5860 lp = sym_lp(tp, lun); 5861 if (!lp) 5862 continue; 5863 if (lp->itlq_tbl) 5864 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 5865 "ITLQ_TBL"); 5866 kfree(lp->cb_tags); 5867 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 5868 } 5869 #if SYM_CONF_MAX_LUN > 1 5870 kfree(tp->lunmp); 5871 #endif 5872 } 5873 if (np->targtbl) 5874 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 5875 } 5876