1 /* 2 * SuperTrak EX Series Storage Controller driver for Linux 3 * 4 * Copyright (C) 2005-2015 Promise Technology Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Written By: 12 * Ed Lin <promise_linux@promise.com> 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/interrupt.h> 25 #include <linux/types.h> 26 #include <linux/module.h> 27 #include <linux/spinlock.h> 28 #include <linux/ktime.h> 29 #include <linux/reboot.h> 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 #include <asm/byteorder.h> 33 #include <scsi/scsi.h> 34 #include <scsi/scsi_device.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_host.h> 37 #include <scsi/scsi_tcq.h> 38 #include <scsi/scsi_dbg.h> 39 #include <scsi/scsi_eh.h> 40 41 #define DRV_NAME "stex" 42 #define ST_DRIVER_VERSION "6.02.0000.01" 43 #define ST_VER_MAJOR 6 44 #define ST_VER_MINOR 02 45 #define ST_OEM 0000 46 #define ST_BUILD_VER 01 47 48 enum { 49 /* MU register offset */ 50 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ 51 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ 52 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ 53 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ 54 IDBL = 0x20, /* MU_INBOUND_DOORBELL */ 55 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ 56 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ 57 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ 58 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ 59 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ 60 61 YIOA_STATUS = 0x00, 62 YH2I_INT = 0x20, 63 YINT_EN = 0x34, 64 YI2H_INT = 0x9c, 65 YI2H_INT_C = 0xa0, 66 YH2I_REQ = 0xc0, 67 YH2I_REQ_HI = 0xc4, 68 PSCRATCH0 = 0xb0, 69 PSCRATCH1 = 0xb4, 70 PSCRATCH2 = 0xb8, 71 PSCRATCH3 = 0xbc, 72 PSCRATCH4 = 0xc8, 73 MAILBOX_BASE = 0x1000, 74 MAILBOX_HNDSHK_STS = 0x0, 75 76 /* MU register value */ 77 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0), 78 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1), 79 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2), 80 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3), 81 MU_INBOUND_DOORBELL_RESET = (1 << 4), 82 83 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0), 84 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1), 85 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2), 86 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3), 87 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4), 88 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27), 89 90 /* MU status code */ 91 MU_STATE_STARTING = 1, 92 MU_STATE_STARTED = 2, 93 MU_STATE_RESETTING = 3, 94 MU_STATE_FAILED = 4, 95 MU_STATE_STOP = 5, 96 MU_STATE_NOCONNECT = 6, 97 98 MU_MAX_DELAY = 50, 99 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 100 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 101 MU_HARD_RESET_WAIT = 30000, 102 HMU_PARTNER_TYPE = 2, 103 104 /* firmware returned values */ 105 SRB_STATUS_SUCCESS = 0x01, 106 SRB_STATUS_ERROR = 0x04, 107 SRB_STATUS_BUSY = 0x05, 108 SRB_STATUS_INVALID_REQUEST = 0x06, 109 SRB_STATUS_SELECTION_TIMEOUT = 0x0A, 110 SRB_SEE_SENSE = 0x80, 111 112 /* task attribute */ 113 TASK_ATTRIBUTE_SIMPLE = 0x0, 114 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, 115 TASK_ATTRIBUTE_ORDERED = 0x2, 116 TASK_ATTRIBUTE_ACA = 0x4, 117 118 SS_STS_NORMAL = 0x80000000, 119 SS_STS_DONE = 0x40000000, 120 SS_STS_HANDSHAKE = 0x20000000, 121 122 SS_HEAD_HANDSHAKE = 0x80, 123 124 SS_H2I_INT_RESET = 0x100, 125 126 SS_I2H_REQUEST_RESET = 0x2000, 127 128 SS_MU_OPERATIONAL = 0x80000000, 129 130 STEX_CDB_LENGTH = 16, 131 STATUS_VAR_LEN = 128, 132 133 /* sg flags */ 134 SG_CF_EOT = 0x80, /* end of table */ 135 SG_CF_64B = 0x40, /* 64 bit item */ 136 SG_CF_HOST = 0x20, /* sg in host memory */ 137 MSG_DATA_DIR_ND = 0, 138 MSG_DATA_DIR_IN = 1, 139 MSG_DATA_DIR_OUT = 2, 140 141 st_shasta = 0, 142 st_vsc = 1, 143 st_yosemite = 2, 144 st_seq = 3, 145 st_yel = 4, 146 st_P3 = 5, 147 148 PASSTHRU_REQ_TYPE = 0x00000001, 149 PASSTHRU_REQ_NO_WAKEUP = 0x00000100, 150 ST_INTERNAL_TIMEOUT = 180, 151 152 ST_TO_CMD = 0, 153 ST_FROM_CMD = 1, 154 155 /* vendor specific commands of Promise */ 156 MGT_CMD = 0xd8, 157 SINBAND_MGT_CMD = 0xd9, 158 ARRAY_CMD = 0xe0, 159 CONTROLLER_CMD = 0xe1, 160 DEBUGGING_CMD = 0xe2, 161 PASSTHRU_CMD = 0xe3, 162 163 PASSTHRU_GET_ADAPTER = 0x05, 164 PASSTHRU_GET_DRVVER = 0x10, 165 166 CTLR_CONFIG_CMD = 0x03, 167 CTLR_SHUTDOWN = 0x0d, 168 169 CTLR_POWER_STATE_CHANGE = 0x0e, 170 CTLR_POWER_SAVING = 0x01, 171 172 PASSTHRU_SIGNATURE = 0x4e415041, 173 MGT_CMD_SIGNATURE = 0xba, 174 175 INQUIRY_EVPD = 0x01, 176 177 ST_ADDITIONAL_MEM = 0x200000, 178 ST_ADDITIONAL_MEM_MIN = 0x80000, 179 PMIC_SHUTDOWN = 0x0D, 180 PMIC_REUMSE = 0x10, 181 ST_IGNORED = -1, 182 ST_NOTHANDLED = 7, 183 ST_S3 = 3, 184 ST_S4 = 4, 185 ST_S5 = 5, 186 ST_S6 = 6, 187 }; 188 189 struct st_sgitem { 190 u8 ctrl; /* SG_CF_xxx */ 191 u8 reserved[3]; 192 __le32 count; 193 __le64 addr; 194 }; 195 196 struct st_ss_sgitem { 197 __le32 addr; 198 __le32 addr_hi; 199 __le32 count; 200 }; 201 202 struct st_sgtable { 203 __le16 sg_count; 204 __le16 max_sg_count; 205 __le32 sz_in_byte; 206 }; 207 208 struct st_msg_header { 209 __le64 handle; 210 u8 flag; 211 u8 channel; 212 __le16 timeout; 213 u32 reserved; 214 }; 215 216 struct handshake_frame { 217 __le64 rb_phy; /* request payload queue physical address */ 218 __le16 req_sz; /* size of each request payload */ 219 __le16 req_cnt; /* count of reqs the buffer can hold */ 220 __le16 status_sz; /* size of each status payload */ 221 __le16 status_cnt; /* count of status the buffer can hold */ 222 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */ 223 u8 partner_type; /* who sends this frame */ 224 u8 reserved0[7]; 225 __le32 partner_ver_major; 226 __le32 partner_ver_minor; 227 __le32 partner_ver_oem; 228 __le32 partner_ver_build; 229 __le32 extra_offset; /* NEW */ 230 __le32 extra_size; /* NEW */ 231 __le32 scratch_size; 232 u32 reserved1; 233 }; 234 235 struct req_msg { 236 __le16 tag; 237 u8 lun; 238 u8 target; 239 u8 task_attr; 240 u8 task_manage; 241 u8 data_dir; 242 u8 payload_sz; /* payload size in 4-byte, not used */ 243 u8 cdb[STEX_CDB_LENGTH]; 244 u32 variable[0]; 245 }; 246 247 struct status_msg { 248 __le16 tag; 249 u8 lun; 250 u8 target; 251 u8 srb_status; 252 u8 scsi_status; 253 u8 reserved; 254 u8 payload_sz; /* payload size in 4-byte */ 255 u8 variable[STATUS_VAR_LEN]; 256 }; 257 258 struct ver_info { 259 u32 major; 260 u32 minor; 261 u32 oem; 262 u32 build; 263 u32 reserved[2]; 264 }; 265 266 struct st_frame { 267 u32 base[6]; 268 u32 rom_addr; 269 270 struct ver_info drv_ver; 271 struct ver_info bios_ver; 272 273 u32 bus; 274 u32 slot; 275 u32 irq_level; 276 u32 irq_vec; 277 u32 id; 278 u32 subid; 279 280 u32 dimm_size; 281 u8 dimm_type; 282 u8 reserved[3]; 283 284 u32 channel; 285 u32 reserved1; 286 }; 287 288 struct st_drvver { 289 u32 major; 290 u32 minor; 291 u32 oem; 292 u32 build; 293 u32 signature[2]; 294 u8 console_id; 295 u8 host_no; 296 u8 reserved0[2]; 297 u32 reserved[3]; 298 }; 299 300 struct st_ccb { 301 struct req_msg *req; 302 struct scsi_cmnd *cmd; 303 304 void *sense_buffer; 305 unsigned int sense_bufflen; 306 int sg_count; 307 308 u32 req_type; 309 u8 srb_status; 310 u8 scsi_status; 311 u8 reserved[2]; 312 }; 313 314 struct st_hba { 315 void __iomem *mmio_base; /* iomapped PCI memory space */ 316 void *dma_mem; 317 dma_addr_t dma_handle; 318 size_t dma_size; 319 320 struct Scsi_Host *host; 321 struct pci_dev *pdev; 322 323 struct req_msg * (*alloc_rq) (struct st_hba *); 324 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 325 void (*send) (struct st_hba *, struct req_msg *, u16); 326 327 u32 req_head; 328 u32 req_tail; 329 u32 status_head; 330 u32 status_tail; 331 332 struct status_msg *status_buffer; 333 void *copy_buffer; /* temp buffer for driver-handled commands */ 334 struct st_ccb *ccb; 335 struct st_ccb *wait_ccb; 336 __le32 *scratch; 337 338 char work_q_name[20]; 339 struct workqueue_struct *work_q; 340 struct work_struct reset_work; 341 wait_queue_head_t reset_waitq; 342 unsigned int mu_status; 343 unsigned int cardtype; 344 int msi_enabled; 345 int out_req_cnt; 346 u32 extra_offset; 347 u16 rq_count; 348 u16 rq_size; 349 u16 sts_count; 350 u8 supports_pm; 351 int msi_lock; 352 }; 353 354 struct st_card_info { 355 struct req_msg * (*alloc_rq) (struct st_hba *); 356 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 357 void (*send) (struct st_hba *, struct req_msg *, u16); 358 unsigned int max_id; 359 unsigned int max_lun; 360 unsigned int max_channel; 361 u16 rq_count; 362 u16 rq_size; 363 u16 sts_count; 364 }; 365 366 static int S6flag; 367 static int stex_halt(struct notifier_block *nb, ulong event, void *buf); 368 static struct notifier_block stex_notifier = { 369 stex_halt, NULL, 0 370 }; 371 372 static int msi; 373 module_param(msi, int, 0); 374 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)"); 375 376 static const char console_inq_page[] = 377 { 378 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, 379 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ 380 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ 381 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ 382 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ 383 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ 384 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ 385 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 386 }; 387 388 MODULE_AUTHOR("Ed Lin"); 389 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); 390 MODULE_LICENSE("GPL"); 391 MODULE_VERSION(ST_DRIVER_VERSION); 392 393 static struct status_msg *stex_get_status(struct st_hba *hba) 394 { 395 struct status_msg *status = hba->status_buffer + hba->status_tail; 396 397 ++hba->status_tail; 398 hba->status_tail %= hba->sts_count+1; 399 400 return status; 401 } 402 403 static void stex_invalid_field(struct scsi_cmnd *cmd, 404 void (*done)(struct scsi_cmnd *)) 405 { 406 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; 407 408 /* "Invalid field in cdb" */ 409 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, 410 0x0); 411 done(cmd); 412 } 413 414 static struct req_msg *stex_alloc_req(struct st_hba *hba) 415 { 416 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size; 417 418 ++hba->req_head; 419 hba->req_head %= hba->rq_count+1; 420 421 return req; 422 } 423 424 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba) 425 { 426 return (struct req_msg *)(hba->dma_mem + 427 hba->req_head * hba->rq_size + sizeof(struct st_msg_header)); 428 } 429 430 static int stex_map_sg(struct st_hba *hba, 431 struct req_msg *req, struct st_ccb *ccb) 432 { 433 struct scsi_cmnd *cmd; 434 struct scatterlist *sg; 435 struct st_sgtable *dst; 436 struct st_sgitem *table; 437 int i, nseg; 438 439 cmd = ccb->cmd; 440 nseg = scsi_dma_map(cmd); 441 BUG_ON(nseg < 0); 442 if (nseg) { 443 dst = (struct st_sgtable *)req->variable; 444 445 ccb->sg_count = nseg; 446 dst->sg_count = cpu_to_le16((u16)nseg); 447 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 448 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 449 450 table = (struct st_sgitem *)(dst + 1); 451 scsi_for_each_sg(cmd, sg, nseg, i) { 452 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 453 table[i].addr = cpu_to_le64(sg_dma_address(sg)); 454 table[i].ctrl = SG_CF_64B | SG_CF_HOST; 455 } 456 table[--i].ctrl |= SG_CF_EOT; 457 } 458 459 return nseg; 460 } 461 462 static int stex_ss_map_sg(struct st_hba *hba, 463 struct req_msg *req, struct st_ccb *ccb) 464 { 465 struct scsi_cmnd *cmd; 466 struct scatterlist *sg; 467 struct st_sgtable *dst; 468 struct st_ss_sgitem *table; 469 int i, nseg; 470 471 cmd = ccb->cmd; 472 nseg = scsi_dma_map(cmd); 473 BUG_ON(nseg < 0); 474 if (nseg) { 475 dst = (struct st_sgtable *)req->variable; 476 477 ccb->sg_count = nseg; 478 dst->sg_count = cpu_to_le16((u16)nseg); 479 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 480 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 481 482 table = (struct st_ss_sgitem *)(dst + 1); 483 scsi_for_each_sg(cmd, sg, nseg, i) { 484 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 485 table[i].addr = 486 cpu_to_le32(sg_dma_address(sg) & 0xffffffff); 487 table[i].addr_hi = 488 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); 489 } 490 } 491 492 return nseg; 493 } 494 495 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) 496 { 497 struct st_frame *p; 498 size_t count = sizeof(struct st_frame); 499 500 p = hba->copy_buffer; 501 scsi_sg_copy_to_buffer(ccb->cmd, p, count); 502 memset(p->base, 0, sizeof(u32)*6); 503 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); 504 p->rom_addr = 0; 505 506 p->drv_ver.major = ST_VER_MAJOR; 507 p->drv_ver.minor = ST_VER_MINOR; 508 p->drv_ver.oem = ST_OEM; 509 p->drv_ver.build = ST_BUILD_VER; 510 511 p->bus = hba->pdev->bus->number; 512 p->slot = hba->pdev->devfn; 513 p->irq_level = 0; 514 p->irq_vec = hba->pdev->irq; 515 p->id = hba->pdev->vendor << 16 | hba->pdev->device; 516 p->subid = 517 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; 518 519 scsi_sg_copy_from_buffer(ccb->cmd, p, count); 520 } 521 522 static void 523 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 524 { 525 req->tag = cpu_to_le16(tag); 526 527 hba->ccb[tag].req = req; 528 hba->out_req_cnt++; 529 530 writel(hba->req_head, hba->mmio_base + IMR0); 531 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); 532 readl(hba->mmio_base + IDBL); /* flush */ 533 } 534 535 static void 536 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 537 { 538 struct scsi_cmnd *cmd; 539 struct st_msg_header *msg_h; 540 dma_addr_t addr; 541 542 req->tag = cpu_to_le16(tag); 543 544 hba->ccb[tag].req = req; 545 hba->out_req_cnt++; 546 547 cmd = hba->ccb[tag].cmd; 548 msg_h = (struct st_msg_header *)req - 1; 549 if (likely(cmd)) { 550 msg_h->channel = (u8)cmd->device->channel; 551 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ); 552 } 553 addr = hba->dma_handle + hba->req_head * hba->rq_size; 554 addr += (hba->ccb[tag].sg_count+4)/11; 555 msg_h->handle = cpu_to_le64(addr); 556 557 ++hba->req_head; 558 hba->req_head %= hba->rq_count+1; 559 if (hba->cardtype == st_P3) { 560 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); 561 writel(addr, hba->mmio_base + YH2I_REQ); 562 } else { 563 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); 564 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ 565 writel(addr, hba->mmio_base + YH2I_REQ); 566 readl(hba->mmio_base + YH2I_REQ); /* flush */ 567 } 568 } 569 570 static void return_abnormal_state(struct st_hba *hba, int status) 571 { 572 struct st_ccb *ccb; 573 unsigned long flags; 574 u16 tag; 575 576 spin_lock_irqsave(hba->host->host_lock, flags); 577 for (tag = 0; tag < hba->host->can_queue; tag++) { 578 ccb = &hba->ccb[tag]; 579 if (ccb->req == NULL) 580 continue; 581 ccb->req = NULL; 582 if (ccb->cmd) { 583 scsi_dma_unmap(ccb->cmd); 584 ccb->cmd->result = status << 16; 585 ccb->cmd->scsi_done(ccb->cmd); 586 ccb->cmd = NULL; 587 } 588 } 589 spin_unlock_irqrestore(hba->host->host_lock, flags); 590 } 591 static int 592 stex_slave_config(struct scsi_device *sdev) 593 { 594 sdev->use_10_for_rw = 1; 595 sdev->use_10_for_ms = 1; 596 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); 597 598 return 0; 599 } 600 601 static int 602 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) 603 { 604 struct st_hba *hba; 605 struct Scsi_Host *host; 606 unsigned int id, lun; 607 struct req_msg *req; 608 u16 tag; 609 610 host = cmd->device->host; 611 id = cmd->device->id; 612 lun = cmd->device->lun; 613 hba = (struct st_hba *) &host->hostdata[0]; 614 if (hba->mu_status == MU_STATE_NOCONNECT) { 615 cmd->result = DID_NO_CONNECT; 616 done(cmd); 617 return 0; 618 } 619 if (unlikely(hba->mu_status != MU_STATE_STARTED)) 620 return SCSI_MLQUEUE_HOST_BUSY; 621 622 switch (cmd->cmnd[0]) { 623 case MODE_SENSE_10: 624 { 625 static char ms10_caching_page[12] = 626 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; 627 unsigned char page; 628 629 page = cmd->cmnd[2] & 0x3f; 630 if (page == 0x8 || page == 0x3f) { 631 scsi_sg_copy_from_buffer(cmd, ms10_caching_page, 632 sizeof(ms10_caching_page)); 633 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 634 done(cmd); 635 } else 636 stex_invalid_field(cmd, done); 637 return 0; 638 } 639 case REPORT_LUNS: 640 /* 641 * The shasta firmware does not report actual luns in the 642 * target, so fail the command to force sequential lun scan. 643 * Also, the console device does not support this command. 644 */ 645 if (hba->cardtype == st_shasta || id == host->max_id - 1) { 646 stex_invalid_field(cmd, done); 647 return 0; 648 } 649 break; 650 case TEST_UNIT_READY: 651 if (id == host->max_id - 1) { 652 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 653 done(cmd); 654 return 0; 655 } 656 break; 657 case INQUIRY: 658 if (lun >= host->max_lun) { 659 cmd->result = DID_NO_CONNECT << 16; 660 done(cmd); 661 return 0; 662 } 663 if (id != host->max_id - 1) 664 break; 665 if (!lun && !cmd->device->channel && 666 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { 667 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, 668 sizeof(console_inq_page)); 669 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 670 done(cmd); 671 } else 672 stex_invalid_field(cmd, done); 673 return 0; 674 case PASSTHRU_CMD: 675 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { 676 struct st_drvver ver; 677 size_t cp_len = sizeof(ver); 678 679 ver.major = ST_VER_MAJOR; 680 ver.minor = ST_VER_MINOR; 681 ver.oem = ST_OEM; 682 ver.build = ST_BUILD_VER; 683 ver.signature[0] = PASSTHRU_SIGNATURE; 684 ver.console_id = host->max_id - 1; 685 ver.host_no = hba->host->host_no; 686 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); 687 cmd->result = sizeof(ver) == cp_len ? 688 DID_OK << 16 | COMMAND_COMPLETE << 8 : 689 DID_ERROR << 16 | COMMAND_COMPLETE << 8; 690 done(cmd); 691 return 0; 692 } 693 default: 694 break; 695 } 696 697 cmd->scsi_done = done; 698 699 tag = cmd->request->tag; 700 701 if (unlikely(tag >= host->can_queue)) 702 return SCSI_MLQUEUE_HOST_BUSY; 703 704 req = hba->alloc_rq(hba); 705 706 req->lun = lun; 707 req->target = id; 708 709 /* cdb */ 710 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); 711 712 if (cmd->sc_data_direction == DMA_FROM_DEVICE) 713 req->data_dir = MSG_DATA_DIR_IN; 714 else if (cmd->sc_data_direction == DMA_TO_DEVICE) 715 req->data_dir = MSG_DATA_DIR_OUT; 716 else 717 req->data_dir = MSG_DATA_DIR_ND; 718 719 hba->ccb[tag].cmd = cmd; 720 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; 721 hba->ccb[tag].sense_buffer = cmd->sense_buffer; 722 723 if (!hba->map_sg(hba, req, &hba->ccb[tag])) { 724 hba->ccb[tag].sg_count = 0; 725 memset(&req->variable[0], 0, 8); 726 } 727 728 hba->send(hba, req, tag); 729 return 0; 730 } 731 732 static DEF_SCSI_QCMD(stex_queuecommand) 733 734 static void stex_scsi_done(struct st_ccb *ccb) 735 { 736 struct scsi_cmnd *cmd = ccb->cmd; 737 int result; 738 739 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { 740 result = ccb->scsi_status; 741 switch (ccb->scsi_status) { 742 case SAM_STAT_GOOD: 743 result |= DID_OK << 16 | COMMAND_COMPLETE << 8; 744 break; 745 case SAM_STAT_CHECK_CONDITION: 746 result |= DRIVER_SENSE << 24; 747 break; 748 case SAM_STAT_BUSY: 749 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 750 break; 751 default: 752 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; 753 break; 754 } 755 } 756 else if (ccb->srb_status & SRB_SEE_SENSE) 757 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; 758 else switch (ccb->srb_status) { 759 case SRB_STATUS_SELECTION_TIMEOUT: 760 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; 761 break; 762 case SRB_STATUS_BUSY: 763 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 764 break; 765 case SRB_STATUS_INVALID_REQUEST: 766 case SRB_STATUS_ERROR: 767 default: 768 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; 769 break; 770 } 771 772 cmd->result = result; 773 cmd->scsi_done(cmd); 774 } 775 776 static void stex_copy_data(struct st_ccb *ccb, 777 struct status_msg *resp, unsigned int variable) 778 { 779 if (resp->scsi_status != SAM_STAT_GOOD) { 780 if (ccb->sense_buffer != NULL) 781 memcpy(ccb->sense_buffer, resp->variable, 782 min(variable, ccb->sense_bufflen)); 783 return; 784 } 785 786 if (ccb->cmd == NULL) 787 return; 788 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable); 789 } 790 791 static void stex_check_cmd(struct st_hba *hba, 792 struct st_ccb *ccb, struct status_msg *resp) 793 { 794 if (ccb->cmd->cmnd[0] == MGT_CMD && 795 resp->scsi_status != SAM_STAT_CHECK_CONDITION) 796 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - 797 le32_to_cpu(*(__le32 *)&resp->variable[0])); 798 } 799 800 static void stex_mu_intr(struct st_hba *hba, u32 doorbell) 801 { 802 void __iomem *base = hba->mmio_base; 803 struct status_msg *resp; 804 struct st_ccb *ccb; 805 unsigned int size; 806 u16 tag; 807 808 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))) 809 return; 810 811 /* status payloads */ 812 hba->status_head = readl(base + OMR1); 813 if (unlikely(hba->status_head > hba->sts_count)) { 814 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", 815 pci_name(hba->pdev)); 816 return; 817 } 818 819 /* 820 * it's not a valid status payload if: 821 * 1. there are no pending requests(e.g. during init stage) 822 * 2. there are some pending requests, but the controller is in 823 * reset status, and its type is not st_yosemite 824 * firmware of st_yosemite in reset status will return pending requests 825 * to driver, so we allow it to pass 826 */ 827 if (unlikely(hba->out_req_cnt <= 0 || 828 (hba->mu_status == MU_STATE_RESETTING && 829 hba->cardtype != st_yosemite))) { 830 hba->status_tail = hba->status_head; 831 goto update_status; 832 } 833 834 while (hba->status_tail != hba->status_head) { 835 resp = stex_get_status(hba); 836 tag = le16_to_cpu(resp->tag); 837 if (unlikely(tag >= hba->host->can_queue)) { 838 printk(KERN_WARNING DRV_NAME 839 "(%s): invalid tag\n", pci_name(hba->pdev)); 840 continue; 841 } 842 843 hba->out_req_cnt--; 844 ccb = &hba->ccb[tag]; 845 if (unlikely(hba->wait_ccb == ccb)) 846 hba->wait_ccb = NULL; 847 if (unlikely(ccb->req == NULL)) { 848 printk(KERN_WARNING DRV_NAME 849 "(%s): lagging req\n", pci_name(hba->pdev)); 850 continue; 851 } 852 853 size = resp->payload_sz * sizeof(u32); /* payload size */ 854 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 855 size > sizeof(*resp))) { 856 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", 857 pci_name(hba->pdev)); 858 } else { 859 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ 860 if (size) 861 stex_copy_data(ccb, resp, size); 862 } 863 864 ccb->req = NULL; 865 ccb->srb_status = resp->srb_status; 866 ccb->scsi_status = resp->scsi_status; 867 868 if (likely(ccb->cmd != NULL)) { 869 if (hba->cardtype == st_yosemite) 870 stex_check_cmd(hba, ccb, resp); 871 872 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && 873 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) 874 stex_controller_info(hba, ccb); 875 876 scsi_dma_unmap(ccb->cmd); 877 stex_scsi_done(ccb); 878 } else 879 ccb->req_type = 0; 880 } 881 882 update_status: 883 writel(hba->status_head, base + IMR1); 884 readl(base + IMR1); /* flush */ 885 } 886 887 static irqreturn_t stex_intr(int irq, void *__hba) 888 { 889 struct st_hba *hba = __hba; 890 void __iomem *base = hba->mmio_base; 891 u32 data; 892 unsigned long flags; 893 894 spin_lock_irqsave(hba->host->host_lock, flags); 895 896 data = readl(base + ODBL); 897 898 if (data && data != 0xffffffff) { 899 /* clear the interrupt */ 900 writel(data, base + ODBL); 901 readl(base + ODBL); /* flush */ 902 stex_mu_intr(hba, data); 903 spin_unlock_irqrestore(hba->host->host_lock, flags); 904 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET && 905 hba->cardtype == st_shasta)) 906 queue_work(hba->work_q, &hba->reset_work); 907 return IRQ_HANDLED; 908 } 909 910 spin_unlock_irqrestore(hba->host->host_lock, flags); 911 912 return IRQ_NONE; 913 } 914 915 static void stex_ss_mu_intr(struct st_hba *hba) 916 { 917 struct status_msg *resp; 918 struct st_ccb *ccb; 919 __le32 *scratch; 920 unsigned int size; 921 int count = 0; 922 u32 value; 923 u16 tag; 924 925 if (unlikely(hba->out_req_cnt <= 0 || 926 hba->mu_status == MU_STATE_RESETTING)) 927 return; 928 929 while (count < hba->sts_count) { 930 scratch = hba->scratch + hba->status_tail; 931 value = le32_to_cpu(*scratch); 932 if (unlikely(!(value & SS_STS_NORMAL))) 933 return; 934 935 resp = hba->status_buffer + hba->status_tail; 936 *scratch = 0; 937 ++count; 938 ++hba->status_tail; 939 hba->status_tail %= hba->sts_count+1; 940 941 tag = (u16)value; 942 if (unlikely(tag >= hba->host->can_queue)) { 943 printk(KERN_WARNING DRV_NAME 944 "(%s): invalid tag\n", pci_name(hba->pdev)); 945 continue; 946 } 947 948 hba->out_req_cnt--; 949 ccb = &hba->ccb[tag]; 950 if (unlikely(hba->wait_ccb == ccb)) 951 hba->wait_ccb = NULL; 952 if (unlikely(ccb->req == NULL)) { 953 printk(KERN_WARNING DRV_NAME 954 "(%s): lagging req\n", pci_name(hba->pdev)); 955 continue; 956 } 957 958 ccb->req = NULL; 959 if (likely(value & SS_STS_DONE)) { /* normal case */ 960 ccb->srb_status = SRB_STATUS_SUCCESS; 961 ccb->scsi_status = SAM_STAT_GOOD; 962 } else { 963 ccb->srb_status = resp->srb_status; 964 ccb->scsi_status = resp->scsi_status; 965 size = resp->payload_sz * sizeof(u32); 966 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 967 size > sizeof(*resp))) { 968 printk(KERN_WARNING DRV_NAME 969 "(%s): bad status size\n", 970 pci_name(hba->pdev)); 971 } else { 972 size -= sizeof(*resp) - STATUS_VAR_LEN; 973 if (size) 974 stex_copy_data(ccb, resp, size); 975 } 976 if (likely(ccb->cmd != NULL)) 977 stex_check_cmd(hba, ccb, resp); 978 } 979 980 if (likely(ccb->cmd != NULL)) { 981 scsi_dma_unmap(ccb->cmd); 982 stex_scsi_done(ccb); 983 } else 984 ccb->req_type = 0; 985 } 986 } 987 988 static irqreturn_t stex_ss_intr(int irq, void *__hba) 989 { 990 struct st_hba *hba = __hba; 991 void __iomem *base = hba->mmio_base; 992 u32 data; 993 unsigned long flags; 994 995 spin_lock_irqsave(hba->host->host_lock, flags); 996 997 if (hba->cardtype == st_yel) { 998 data = readl(base + YI2H_INT); 999 if (data && data != 0xffffffff) { 1000 /* clear the interrupt */ 1001 writel(data, base + YI2H_INT_C); 1002 stex_ss_mu_intr(hba); 1003 spin_unlock_irqrestore(hba->host->host_lock, flags); 1004 if (unlikely(data & SS_I2H_REQUEST_RESET)) 1005 queue_work(hba->work_q, &hba->reset_work); 1006 return IRQ_HANDLED; 1007 } 1008 } else { 1009 data = readl(base + PSCRATCH4); 1010 if (data != 0xffffffff) { 1011 if (data != 0) { 1012 /* clear the interrupt */ 1013 writel(data, base + PSCRATCH1); 1014 writel((1 << 22), base + YH2I_INT); 1015 } 1016 stex_ss_mu_intr(hba); 1017 spin_unlock_irqrestore(hba->host->host_lock, flags); 1018 if (unlikely(data & SS_I2H_REQUEST_RESET)) 1019 queue_work(hba->work_q, &hba->reset_work); 1020 return IRQ_HANDLED; 1021 } 1022 } 1023 1024 spin_unlock_irqrestore(hba->host->host_lock, flags); 1025 1026 return IRQ_NONE; 1027 } 1028 1029 static int stex_common_handshake(struct st_hba *hba) 1030 { 1031 void __iomem *base = hba->mmio_base; 1032 struct handshake_frame *h; 1033 dma_addr_t status_phys; 1034 u32 data; 1035 unsigned long before; 1036 1037 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1038 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1039 readl(base + IDBL); 1040 before = jiffies; 1041 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1042 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1043 printk(KERN_ERR DRV_NAME 1044 "(%s): no handshake signature\n", 1045 pci_name(hba->pdev)); 1046 return -1; 1047 } 1048 rmb(); 1049 msleep(1); 1050 } 1051 } 1052 1053 udelay(10); 1054 1055 data = readl(base + OMR1); 1056 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { 1057 data &= 0x0000ffff; 1058 if (hba->host->can_queue > data) { 1059 hba->host->can_queue = data; 1060 hba->host->cmd_per_lun = data; 1061 } 1062 } 1063 1064 h = (struct handshake_frame *)hba->status_buffer; 1065 h->rb_phy = cpu_to_le64(hba->dma_handle); 1066 h->req_sz = cpu_to_le16(hba->rq_size); 1067 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1068 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1069 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1070 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1071 h->partner_type = HMU_PARTNER_TYPE; 1072 if (hba->extra_offset) { 1073 h->extra_offset = cpu_to_le32(hba->extra_offset); 1074 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset); 1075 } else 1076 h->extra_offset = h->extra_size = 0; 1077 1078 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size; 1079 writel(status_phys, base + IMR0); 1080 readl(base + IMR0); 1081 writel((status_phys >> 16) >> 16, base + IMR1); 1082 readl(base + IMR1); 1083 1084 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ 1085 readl(base + OMR0); 1086 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1087 readl(base + IDBL); /* flush */ 1088 1089 udelay(10); 1090 before = jiffies; 1091 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1092 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1093 printk(KERN_ERR DRV_NAME 1094 "(%s): no signature after handshake frame\n", 1095 pci_name(hba->pdev)); 1096 return -1; 1097 } 1098 rmb(); 1099 msleep(1); 1100 } 1101 1102 writel(0, base + IMR0); 1103 readl(base + IMR0); 1104 writel(0, base + OMR0); 1105 readl(base + OMR0); 1106 writel(0, base + IMR1); 1107 readl(base + IMR1); 1108 writel(0, base + OMR1); 1109 readl(base + OMR1); /* flush */ 1110 return 0; 1111 } 1112 1113 static int stex_ss_handshake(struct st_hba *hba) 1114 { 1115 void __iomem *base = hba->mmio_base; 1116 struct st_msg_header *msg_h; 1117 struct handshake_frame *h; 1118 __le32 *scratch; 1119 u32 data, scratch_size, mailboxdata, operationaldata; 1120 unsigned long before; 1121 int ret = 0; 1122 1123 before = jiffies; 1124 1125 if (hba->cardtype == st_yel) { 1126 operationaldata = readl(base + YIOA_STATUS); 1127 while (operationaldata != SS_MU_OPERATIONAL) { 1128 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1129 printk(KERN_ERR DRV_NAME 1130 "(%s): firmware not operational\n", 1131 pci_name(hba->pdev)); 1132 return -1; 1133 } 1134 msleep(1); 1135 operationaldata = readl(base + YIOA_STATUS); 1136 } 1137 } else { 1138 operationaldata = readl(base + PSCRATCH3); 1139 while (operationaldata != SS_MU_OPERATIONAL) { 1140 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1141 printk(KERN_ERR DRV_NAME 1142 "(%s): firmware not operational\n", 1143 pci_name(hba->pdev)); 1144 return -1; 1145 } 1146 msleep(1); 1147 operationaldata = readl(base + PSCRATCH3); 1148 } 1149 } 1150 1151 msg_h = (struct st_msg_header *)hba->dma_mem; 1152 msg_h->handle = cpu_to_le64(hba->dma_handle); 1153 msg_h->flag = SS_HEAD_HANDSHAKE; 1154 1155 h = (struct handshake_frame *)(msg_h + 1); 1156 h->rb_phy = cpu_to_le64(hba->dma_handle); 1157 h->req_sz = cpu_to_le16(hba->rq_size); 1158 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1159 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1160 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1161 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1162 h->partner_type = HMU_PARTNER_TYPE; 1163 h->extra_offset = h->extra_size = 0; 1164 scratch_size = (hba->sts_count+1)*sizeof(u32); 1165 h->scratch_size = cpu_to_le32(scratch_size); 1166 1167 if (hba->cardtype == st_yel) { 1168 data = readl(base + YINT_EN); 1169 data &= ~4; 1170 writel(data, base + YINT_EN); 1171 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); 1172 readl(base + YH2I_REQ_HI); 1173 writel(hba->dma_handle, base + YH2I_REQ); 1174 readl(base + YH2I_REQ); /* flush */ 1175 } else { 1176 data = readl(base + YINT_EN); 1177 data &= ~(1 << 0); 1178 data &= ~(1 << 2); 1179 writel(data, base + YINT_EN); 1180 if (hba->msi_lock == 0) { 1181 /* P3 MSI Register cannot access twice */ 1182 writel((1 << 6), base + YH2I_INT); 1183 hba->msi_lock = 1; 1184 } 1185 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); 1186 writel(hba->dma_handle, base + YH2I_REQ); 1187 } 1188 1189 before = jiffies; 1190 scratch = hba->scratch; 1191 if (hba->cardtype == st_yel) { 1192 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) { 1193 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1194 printk(KERN_ERR DRV_NAME 1195 "(%s): no signature after handshake frame\n", 1196 pci_name(hba->pdev)); 1197 ret = -1; 1198 break; 1199 } 1200 rmb(); 1201 msleep(1); 1202 } 1203 } else { 1204 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); 1205 while (mailboxdata != SS_STS_HANDSHAKE) { 1206 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1207 printk(KERN_ERR DRV_NAME 1208 "(%s): no signature after handshake frame\n", 1209 pci_name(hba->pdev)); 1210 ret = -1; 1211 break; 1212 } 1213 rmb(); 1214 msleep(1); 1215 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); 1216 } 1217 } 1218 memset(scratch, 0, scratch_size); 1219 msg_h->flag = 0; 1220 1221 return ret; 1222 } 1223 1224 static int stex_handshake(struct st_hba *hba) 1225 { 1226 int err; 1227 unsigned long flags; 1228 unsigned int mu_status; 1229 1230 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1231 err = stex_ss_handshake(hba); 1232 else 1233 err = stex_common_handshake(hba); 1234 spin_lock_irqsave(hba->host->host_lock, flags); 1235 mu_status = hba->mu_status; 1236 if (err == 0) { 1237 hba->req_head = 0; 1238 hba->req_tail = 0; 1239 hba->status_head = 0; 1240 hba->status_tail = 0; 1241 hba->out_req_cnt = 0; 1242 hba->mu_status = MU_STATE_STARTED; 1243 } else 1244 hba->mu_status = MU_STATE_FAILED; 1245 if (mu_status == MU_STATE_RESETTING) 1246 wake_up_all(&hba->reset_waitq); 1247 spin_unlock_irqrestore(hba->host->host_lock, flags); 1248 return err; 1249 } 1250 1251 static int stex_abort(struct scsi_cmnd *cmd) 1252 { 1253 struct Scsi_Host *host = cmd->device->host; 1254 struct st_hba *hba = (struct st_hba *)host->hostdata; 1255 u16 tag = cmd->request->tag; 1256 void __iomem *base; 1257 u32 data; 1258 int result = SUCCESS; 1259 unsigned long flags; 1260 1261 scmd_printk(KERN_INFO, cmd, "aborting command\n"); 1262 1263 base = hba->mmio_base; 1264 spin_lock_irqsave(host->host_lock, flags); 1265 if (tag < host->can_queue && 1266 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd) 1267 hba->wait_ccb = &hba->ccb[tag]; 1268 else 1269 goto out; 1270 1271 if (hba->cardtype == st_yel) { 1272 data = readl(base + YI2H_INT); 1273 if (data == 0 || data == 0xffffffff) 1274 goto fail_out; 1275 1276 writel(data, base + YI2H_INT_C); 1277 stex_ss_mu_intr(hba); 1278 } else if (hba->cardtype == st_P3) { 1279 data = readl(base + PSCRATCH4); 1280 if (data == 0xffffffff) 1281 goto fail_out; 1282 if (data != 0) { 1283 writel(data, base + PSCRATCH1); 1284 writel((1 << 22), base + YH2I_INT); 1285 } 1286 stex_ss_mu_intr(hba); 1287 } else { 1288 data = readl(base + ODBL); 1289 if (data == 0 || data == 0xffffffff) 1290 goto fail_out; 1291 1292 writel(data, base + ODBL); 1293 readl(base + ODBL); /* flush */ 1294 stex_mu_intr(hba, data); 1295 } 1296 if (hba->wait_ccb == NULL) { 1297 printk(KERN_WARNING DRV_NAME 1298 "(%s): lost interrupt\n", pci_name(hba->pdev)); 1299 goto out; 1300 } 1301 1302 fail_out: 1303 scsi_dma_unmap(cmd); 1304 hba->wait_ccb->req = NULL; /* nullify the req's future return */ 1305 hba->wait_ccb = NULL; 1306 result = FAILED; 1307 out: 1308 spin_unlock_irqrestore(host->host_lock, flags); 1309 return result; 1310 } 1311 1312 static void stex_hard_reset(struct st_hba *hba) 1313 { 1314 struct pci_bus *bus; 1315 int i; 1316 u16 pci_cmd; 1317 u8 pci_bctl; 1318 1319 for (i = 0; i < 16; i++) 1320 pci_read_config_dword(hba->pdev, i * 4, 1321 &hba->pdev->saved_config_space[i]); 1322 1323 /* Reset secondary bus. Our controller(MU/ATU) is the only device on 1324 secondary bus. Consult Intel 80331/3 developer's manual for detail */ 1325 bus = hba->pdev->bus; 1326 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); 1327 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; 1328 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1329 1330 /* 1331 * 1 ms may be enough for 8-port controllers. But 16-port controllers 1332 * require more time to finish bus reset. Use 100 ms here for safety 1333 */ 1334 msleep(100); 1335 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1336 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1337 1338 for (i = 0; i < MU_HARD_RESET_WAIT; i++) { 1339 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1340 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1341 break; 1342 msleep(1); 1343 } 1344 1345 ssleep(5); 1346 for (i = 0; i < 16; i++) 1347 pci_write_config_dword(hba->pdev, i * 4, 1348 hba->pdev->saved_config_space[i]); 1349 } 1350 1351 static int stex_yos_reset(struct st_hba *hba) 1352 { 1353 void __iomem *base; 1354 unsigned long flags, before; 1355 int ret = 0; 1356 1357 base = hba->mmio_base; 1358 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL); 1359 readl(base + IDBL); /* flush */ 1360 before = jiffies; 1361 while (hba->out_req_cnt > 0) { 1362 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1363 printk(KERN_WARNING DRV_NAME 1364 "(%s): reset timeout\n", pci_name(hba->pdev)); 1365 ret = -1; 1366 break; 1367 } 1368 msleep(1); 1369 } 1370 1371 spin_lock_irqsave(hba->host->host_lock, flags); 1372 if (ret == -1) 1373 hba->mu_status = MU_STATE_FAILED; 1374 else 1375 hba->mu_status = MU_STATE_STARTED; 1376 wake_up_all(&hba->reset_waitq); 1377 spin_unlock_irqrestore(hba->host->host_lock, flags); 1378 1379 return ret; 1380 } 1381 1382 static void stex_ss_reset(struct st_hba *hba) 1383 { 1384 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); 1385 readl(hba->mmio_base + YH2I_INT); 1386 ssleep(5); 1387 } 1388 1389 static void stex_p3_reset(struct st_hba *hba) 1390 { 1391 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); 1392 ssleep(5); 1393 } 1394 1395 static int stex_do_reset(struct st_hba *hba) 1396 { 1397 unsigned long flags; 1398 unsigned int mu_status = MU_STATE_RESETTING; 1399 1400 spin_lock_irqsave(hba->host->host_lock, flags); 1401 if (hba->mu_status == MU_STATE_STARTING) { 1402 spin_unlock_irqrestore(hba->host->host_lock, flags); 1403 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n", 1404 pci_name(hba->pdev)); 1405 return 0; 1406 } 1407 while (hba->mu_status == MU_STATE_RESETTING) { 1408 spin_unlock_irqrestore(hba->host->host_lock, flags); 1409 wait_event_timeout(hba->reset_waitq, 1410 hba->mu_status != MU_STATE_RESETTING, 1411 MU_MAX_DELAY * HZ); 1412 spin_lock_irqsave(hba->host->host_lock, flags); 1413 mu_status = hba->mu_status; 1414 } 1415 1416 if (mu_status != MU_STATE_RESETTING) { 1417 spin_unlock_irqrestore(hba->host->host_lock, flags); 1418 return (mu_status == MU_STATE_STARTED) ? 0 : -1; 1419 } 1420 1421 hba->mu_status = MU_STATE_RESETTING; 1422 spin_unlock_irqrestore(hba->host->host_lock, flags); 1423 1424 if (hba->cardtype == st_yosemite) 1425 return stex_yos_reset(hba); 1426 1427 if (hba->cardtype == st_shasta) 1428 stex_hard_reset(hba); 1429 else if (hba->cardtype == st_yel) 1430 stex_ss_reset(hba); 1431 else if (hba->cardtype == st_P3) 1432 stex_p3_reset(hba); 1433 1434 return_abnormal_state(hba, DID_RESET); 1435 1436 if (stex_handshake(hba) == 0) 1437 return 0; 1438 1439 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n", 1440 pci_name(hba->pdev)); 1441 return -1; 1442 } 1443 1444 static int stex_reset(struct scsi_cmnd *cmd) 1445 { 1446 struct st_hba *hba; 1447 1448 hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 1449 1450 shost_printk(KERN_INFO, cmd->device->host, 1451 "resetting host\n"); 1452 1453 return stex_do_reset(hba) ? FAILED : SUCCESS; 1454 } 1455 1456 static void stex_reset_work(struct work_struct *work) 1457 { 1458 struct st_hba *hba = container_of(work, struct st_hba, reset_work); 1459 1460 stex_do_reset(hba); 1461 } 1462 1463 static int stex_biosparam(struct scsi_device *sdev, 1464 struct block_device *bdev, sector_t capacity, int geom[]) 1465 { 1466 int heads = 255, sectors = 63; 1467 1468 if (capacity < 0x200000) { 1469 heads = 64; 1470 sectors = 32; 1471 } 1472 1473 sector_div(capacity, heads * sectors); 1474 1475 geom[0] = heads; 1476 geom[1] = sectors; 1477 geom[2] = capacity; 1478 1479 return 0; 1480 } 1481 1482 static struct scsi_host_template driver_template = { 1483 .module = THIS_MODULE, 1484 .name = DRV_NAME, 1485 .proc_name = DRV_NAME, 1486 .bios_param = stex_biosparam, 1487 .queuecommand = stex_queuecommand, 1488 .slave_configure = stex_slave_config, 1489 .eh_abort_handler = stex_abort, 1490 .eh_host_reset_handler = stex_reset, 1491 .this_id = -1, 1492 }; 1493 1494 static struct pci_device_id stex_pci_tbl[] = { 1495 /* st_shasta */ 1496 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1497 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ 1498 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1499 st_shasta }, /* SuperTrak EX12350 */ 1500 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1501 st_shasta }, /* SuperTrak EX4350 */ 1502 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1503 st_shasta }, /* SuperTrak EX24350 */ 1504 1505 /* st_vsc */ 1506 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, 1507 1508 /* st_yosemite */ 1509 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite }, 1510 1511 /* st_seq */ 1512 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, 1513 1514 /* st_yel */ 1515 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel }, 1516 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel }, 1517 1518 /* st_P3, pluto */ 1519 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE, 1520 0x8870, 0, 0, st_P3 }, 1521 /* st_P3, p3 */ 1522 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE, 1523 0x4300, 0, 0, st_P3 }, 1524 1525 /* st_P3, SymplyStor4E */ 1526 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1527 0x4311, 0, 0, st_P3 }, 1528 /* st_P3, SymplyStor8E */ 1529 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1530 0x4312, 0, 0, st_P3 }, 1531 /* st_P3, SymplyStor4 */ 1532 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1533 0x4321, 0, 0, st_P3 }, 1534 /* st_P3, SymplyStor8 */ 1535 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1536 0x4322, 0, 0, st_P3 }, 1537 { } /* terminate list */ 1538 }; 1539 1540 static struct st_card_info stex_card_info[] = { 1541 /* st_shasta */ 1542 { 1543 .max_id = 17, 1544 .max_lun = 8, 1545 .max_channel = 0, 1546 .rq_count = 32, 1547 .rq_size = 1048, 1548 .sts_count = 32, 1549 .alloc_rq = stex_alloc_req, 1550 .map_sg = stex_map_sg, 1551 .send = stex_send_cmd, 1552 }, 1553 1554 /* st_vsc */ 1555 { 1556 .max_id = 129, 1557 .max_lun = 1, 1558 .max_channel = 0, 1559 .rq_count = 32, 1560 .rq_size = 1048, 1561 .sts_count = 32, 1562 .alloc_rq = stex_alloc_req, 1563 .map_sg = stex_map_sg, 1564 .send = stex_send_cmd, 1565 }, 1566 1567 /* st_yosemite */ 1568 { 1569 .max_id = 2, 1570 .max_lun = 256, 1571 .max_channel = 0, 1572 .rq_count = 256, 1573 .rq_size = 1048, 1574 .sts_count = 256, 1575 .alloc_rq = stex_alloc_req, 1576 .map_sg = stex_map_sg, 1577 .send = stex_send_cmd, 1578 }, 1579 1580 /* st_seq */ 1581 { 1582 .max_id = 129, 1583 .max_lun = 1, 1584 .max_channel = 0, 1585 .rq_count = 32, 1586 .rq_size = 1048, 1587 .sts_count = 32, 1588 .alloc_rq = stex_alloc_req, 1589 .map_sg = stex_map_sg, 1590 .send = stex_send_cmd, 1591 }, 1592 1593 /* st_yel */ 1594 { 1595 .max_id = 129, 1596 .max_lun = 256, 1597 .max_channel = 3, 1598 .rq_count = 801, 1599 .rq_size = 512, 1600 .sts_count = 801, 1601 .alloc_rq = stex_ss_alloc_req, 1602 .map_sg = stex_ss_map_sg, 1603 .send = stex_ss_send_cmd, 1604 }, 1605 1606 /* st_P3 */ 1607 { 1608 .max_id = 129, 1609 .max_lun = 256, 1610 .max_channel = 0, 1611 .rq_count = 801, 1612 .rq_size = 512, 1613 .sts_count = 801, 1614 .alloc_rq = stex_ss_alloc_req, 1615 .map_sg = stex_ss_map_sg, 1616 .send = stex_ss_send_cmd, 1617 }, 1618 }; 1619 1620 static int stex_set_dma_mask(struct pci_dev * pdev) 1621 { 1622 int ret; 1623 1624 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) 1625 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) 1626 return 0; 1627 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1628 if (!ret) 1629 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1630 return ret; 1631 } 1632 1633 static int stex_request_irq(struct st_hba *hba) 1634 { 1635 struct pci_dev *pdev = hba->pdev; 1636 int status; 1637 1638 if (msi || hba->cardtype == st_P3) { 1639 status = pci_enable_msi(pdev); 1640 if (status != 0) 1641 printk(KERN_ERR DRV_NAME 1642 "(%s): error %d setting up MSI\n", 1643 pci_name(pdev), status); 1644 else 1645 hba->msi_enabled = 1; 1646 } else 1647 hba->msi_enabled = 0; 1648 1649 status = request_irq(pdev->irq, 1650 (hba->cardtype == st_yel || hba->cardtype == st_P3) ? 1651 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba); 1652 1653 if (status != 0) { 1654 if (hba->msi_enabled) 1655 pci_disable_msi(pdev); 1656 } 1657 return status; 1658 } 1659 1660 static void stex_free_irq(struct st_hba *hba) 1661 { 1662 struct pci_dev *pdev = hba->pdev; 1663 1664 free_irq(pdev->irq, hba); 1665 if (hba->msi_enabled) 1666 pci_disable_msi(pdev); 1667 } 1668 1669 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1670 { 1671 struct st_hba *hba; 1672 struct Scsi_Host *host; 1673 const struct st_card_info *ci = NULL; 1674 u32 sts_offset, cp_offset, scratch_offset; 1675 int err; 1676 1677 err = pci_enable_device(pdev); 1678 if (err) 1679 return err; 1680 1681 pci_set_master(pdev); 1682 1683 S6flag = 0; 1684 register_reboot_notifier(&stex_notifier); 1685 1686 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); 1687 1688 if (!host) { 1689 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", 1690 pci_name(pdev)); 1691 err = -ENOMEM; 1692 goto out_disable; 1693 } 1694 1695 hba = (struct st_hba *)host->hostdata; 1696 memset(hba, 0, sizeof(struct st_hba)); 1697 1698 err = pci_request_regions(pdev, DRV_NAME); 1699 if (err < 0) { 1700 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", 1701 pci_name(pdev)); 1702 goto out_scsi_host_put; 1703 } 1704 1705 hba->mmio_base = pci_ioremap_bar(pdev, 0); 1706 if ( !hba->mmio_base) { 1707 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", 1708 pci_name(pdev)); 1709 err = -ENOMEM; 1710 goto out_release_regions; 1711 } 1712 1713 err = stex_set_dma_mask(pdev); 1714 if (err) { 1715 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", 1716 pci_name(pdev)); 1717 goto out_iounmap; 1718 } 1719 1720 hba->cardtype = (unsigned int) id->driver_data; 1721 ci = &stex_card_info[hba->cardtype]; 1722 switch (id->subdevice) { 1723 case 0x4221: 1724 case 0x4222: 1725 case 0x4223: 1726 case 0x4224: 1727 case 0x4225: 1728 case 0x4226: 1729 case 0x4227: 1730 case 0x4261: 1731 case 0x4262: 1732 case 0x4263: 1733 case 0x4264: 1734 case 0x4265: 1735 break; 1736 default: 1737 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1738 hba->supports_pm = 1; 1739 } 1740 1741 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size; 1742 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1743 sts_offset += (ci->sts_count+1) * sizeof(u32); 1744 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg); 1745 hba->dma_size = cp_offset + sizeof(struct st_frame); 1746 if (hba->cardtype == st_seq || 1747 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1748 hba->extra_offset = hba->dma_size; 1749 hba->dma_size += ST_ADDITIONAL_MEM; 1750 } 1751 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1752 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1753 if (!hba->dma_mem) { 1754 /* Retry minimum coherent mapping for st_seq and st_vsc */ 1755 if (hba->cardtype == st_seq || 1756 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1757 printk(KERN_WARNING DRV_NAME 1758 "(%s): allocating min buffer for controller\n", 1759 pci_name(pdev)); 1760 hba->dma_size = hba->extra_offset 1761 + ST_ADDITIONAL_MEM_MIN; 1762 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1763 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1764 } 1765 1766 if (!hba->dma_mem) { 1767 err = -ENOMEM; 1768 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", 1769 pci_name(pdev)); 1770 goto out_iounmap; 1771 } 1772 } 1773 1774 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL); 1775 if (!hba->ccb) { 1776 err = -ENOMEM; 1777 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n", 1778 pci_name(pdev)); 1779 goto out_pci_free; 1780 } 1781 1782 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1783 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset); 1784 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset); 1785 hba->copy_buffer = hba->dma_mem + cp_offset; 1786 hba->rq_count = ci->rq_count; 1787 hba->rq_size = ci->rq_size; 1788 hba->sts_count = ci->sts_count; 1789 hba->alloc_rq = ci->alloc_rq; 1790 hba->map_sg = ci->map_sg; 1791 hba->send = ci->send; 1792 hba->mu_status = MU_STATE_STARTING; 1793 hba->msi_lock = 0; 1794 1795 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1796 host->sg_tablesize = 38; 1797 else 1798 host->sg_tablesize = 32; 1799 host->can_queue = ci->rq_count; 1800 host->cmd_per_lun = ci->rq_count; 1801 host->max_id = ci->max_id; 1802 host->max_lun = ci->max_lun; 1803 host->max_channel = ci->max_channel; 1804 host->unique_id = host->host_no; 1805 host->max_cmd_len = STEX_CDB_LENGTH; 1806 1807 hba->host = host; 1808 hba->pdev = pdev; 1809 init_waitqueue_head(&hba->reset_waitq); 1810 1811 snprintf(hba->work_q_name, sizeof(hba->work_q_name), 1812 "stex_wq_%d", host->host_no); 1813 hba->work_q = create_singlethread_workqueue(hba->work_q_name); 1814 if (!hba->work_q) { 1815 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n", 1816 pci_name(pdev)); 1817 err = -ENOMEM; 1818 goto out_ccb_free; 1819 } 1820 INIT_WORK(&hba->reset_work, stex_reset_work); 1821 1822 err = stex_request_irq(hba); 1823 if (err) { 1824 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", 1825 pci_name(pdev)); 1826 goto out_free_wq; 1827 } 1828 1829 err = stex_handshake(hba); 1830 if (err) 1831 goto out_free_irq; 1832 1833 pci_set_drvdata(pdev, hba); 1834 1835 err = scsi_add_host(host, &pdev->dev); 1836 if (err) { 1837 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", 1838 pci_name(pdev)); 1839 goto out_free_irq; 1840 } 1841 1842 scsi_scan_host(host); 1843 1844 return 0; 1845 1846 out_free_irq: 1847 stex_free_irq(hba); 1848 out_free_wq: 1849 destroy_workqueue(hba->work_q); 1850 out_ccb_free: 1851 kfree(hba->ccb); 1852 out_pci_free: 1853 dma_free_coherent(&pdev->dev, hba->dma_size, 1854 hba->dma_mem, hba->dma_handle); 1855 out_iounmap: 1856 iounmap(hba->mmio_base); 1857 out_release_regions: 1858 pci_release_regions(pdev); 1859 out_scsi_host_put: 1860 scsi_host_put(host); 1861 out_disable: 1862 pci_disable_device(pdev); 1863 1864 return err; 1865 } 1866 1867 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic) 1868 { 1869 struct req_msg *req; 1870 struct st_msg_header *msg_h; 1871 unsigned long flags; 1872 unsigned long before; 1873 u16 tag = 0; 1874 1875 spin_lock_irqsave(hba->host->host_lock, flags); 1876 1877 if ((hba->cardtype == st_yel || hba->cardtype == st_P3) && 1878 hba->supports_pm == 1) { 1879 if (st_sleep_mic == ST_NOTHANDLED) { 1880 spin_unlock_irqrestore(hba->host->host_lock, flags); 1881 return; 1882 } 1883 } 1884 req = hba->alloc_rq(hba); 1885 if (hba->cardtype == st_yel || hba->cardtype == st_P3) { 1886 msg_h = (struct st_msg_header *)req - 1; 1887 memset(msg_h, 0, hba->rq_size); 1888 } else 1889 memset(req, 0, hba->rq_size); 1890 1891 if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel 1892 || hba->cardtype == st_P3) 1893 && st_sleep_mic == ST_IGNORED) { 1894 req->cdb[0] = MGT_CMD; 1895 req->cdb[1] = MGT_CMD_SIGNATURE; 1896 req->cdb[2] = CTLR_CONFIG_CMD; 1897 req->cdb[3] = CTLR_SHUTDOWN; 1898 } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3) 1899 && st_sleep_mic != ST_IGNORED) { 1900 req->cdb[0] = MGT_CMD; 1901 req->cdb[1] = MGT_CMD_SIGNATURE; 1902 req->cdb[2] = CTLR_CONFIG_CMD; 1903 req->cdb[3] = PMIC_SHUTDOWN; 1904 req->cdb[4] = st_sleep_mic; 1905 } else { 1906 req->cdb[0] = CONTROLLER_CMD; 1907 req->cdb[1] = CTLR_POWER_STATE_CHANGE; 1908 req->cdb[2] = CTLR_POWER_SAVING; 1909 } 1910 hba->ccb[tag].cmd = NULL; 1911 hba->ccb[tag].sg_count = 0; 1912 hba->ccb[tag].sense_bufflen = 0; 1913 hba->ccb[tag].sense_buffer = NULL; 1914 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE; 1915 hba->send(hba, req, tag); 1916 spin_unlock_irqrestore(hba->host->host_lock, flags); 1917 before = jiffies; 1918 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { 1919 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1920 hba->ccb[tag].req_type = 0; 1921 hba->mu_status = MU_STATE_STOP; 1922 return; 1923 } 1924 msleep(1); 1925 } 1926 hba->mu_status = MU_STATE_STOP; 1927 } 1928 1929 static void stex_hba_free(struct st_hba *hba) 1930 { 1931 stex_free_irq(hba); 1932 1933 destroy_workqueue(hba->work_q); 1934 1935 iounmap(hba->mmio_base); 1936 1937 pci_release_regions(hba->pdev); 1938 1939 kfree(hba->ccb); 1940 1941 dma_free_coherent(&hba->pdev->dev, hba->dma_size, 1942 hba->dma_mem, hba->dma_handle); 1943 } 1944 1945 static void stex_remove(struct pci_dev *pdev) 1946 { 1947 struct st_hba *hba = pci_get_drvdata(pdev); 1948 1949 hba->mu_status = MU_STATE_NOCONNECT; 1950 return_abnormal_state(hba, DID_NO_CONNECT); 1951 scsi_remove_host(hba->host); 1952 1953 scsi_block_requests(hba->host); 1954 1955 stex_hba_free(hba); 1956 1957 scsi_host_put(hba->host); 1958 1959 pci_disable_device(pdev); 1960 1961 unregister_reboot_notifier(&stex_notifier); 1962 } 1963 1964 static void stex_shutdown(struct pci_dev *pdev) 1965 { 1966 struct st_hba *hba = pci_get_drvdata(pdev); 1967 1968 if (hba->supports_pm == 0) { 1969 stex_hba_stop(hba, ST_IGNORED); 1970 } else if (hba->supports_pm == 1 && S6flag) { 1971 unregister_reboot_notifier(&stex_notifier); 1972 stex_hba_stop(hba, ST_S6); 1973 } else 1974 stex_hba_stop(hba, ST_S5); 1975 } 1976 1977 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state) 1978 { 1979 switch (state.event) { 1980 case PM_EVENT_SUSPEND: 1981 return ST_S3; 1982 case PM_EVENT_HIBERNATE: 1983 hba->msi_lock = 0; 1984 return ST_S4; 1985 default: 1986 return ST_NOTHANDLED; 1987 } 1988 } 1989 1990 static int stex_suspend(struct pci_dev *pdev, pm_message_t state) 1991 { 1992 struct st_hba *hba = pci_get_drvdata(pdev); 1993 1994 if ((hba->cardtype == st_yel || hba->cardtype == st_P3) 1995 && hba->supports_pm == 1) 1996 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state)); 1997 else 1998 stex_hba_stop(hba, ST_IGNORED); 1999 return 0; 2000 } 2001 2002 static int stex_resume(struct pci_dev *pdev) 2003 { 2004 struct st_hba *hba = pci_get_drvdata(pdev); 2005 2006 hba->mu_status = MU_STATE_STARTING; 2007 stex_handshake(hba); 2008 return 0; 2009 } 2010 2011 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf) 2012 { 2013 S6flag = 1; 2014 return NOTIFY_OK; 2015 } 2016 MODULE_DEVICE_TABLE(pci, stex_pci_tbl); 2017 2018 static struct pci_driver stex_pci_driver = { 2019 .name = DRV_NAME, 2020 .id_table = stex_pci_tbl, 2021 .probe = stex_probe, 2022 .remove = stex_remove, 2023 .shutdown = stex_shutdown, 2024 .suspend = stex_suspend, 2025 .resume = stex_resume, 2026 }; 2027 2028 static int __init stex_init(void) 2029 { 2030 printk(KERN_INFO DRV_NAME 2031 ": Promise SuperTrak EX Driver version: %s\n", 2032 ST_DRIVER_VERSION); 2033 2034 return pci_register_driver(&stex_pci_driver); 2035 } 2036 2037 static void __exit stex_exit(void) 2038 { 2039 pci_unregister_driver(&stex_pci_driver); 2040 } 2041 2042 module_init(stex_init); 2043 module_exit(stex_exit); 2044