1 /* 2 * SuperTrak EX Series Storage Controller driver for Linux 3 * 4 * Copyright (C) 2005, 2006 Promise Technology Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Written By: 12 * Ed Lin <promise_linux@promise.com> 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/sched.h> 21 #include <linux/time.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/interrupt.h> 25 #include <linux/types.h> 26 #include <linux/module.h> 27 #include <linux/spinlock.h> 28 #include <asm/io.h> 29 #include <asm/irq.h> 30 #include <asm/byteorder.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_host.h> 35 #include <scsi/scsi_tcq.h> 36 37 #define DRV_NAME "stex" 38 #define ST_DRIVER_VERSION "3.1.0.1" 39 #define ST_VER_MAJOR 3 40 #define ST_VER_MINOR 1 41 #define ST_OEM 0 42 #define ST_BUILD_VER 1 43 44 enum { 45 /* MU register offset */ 46 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ 47 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ 48 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ 49 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ 50 IDBL = 0x20, /* MU_INBOUND_DOORBELL */ 51 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ 52 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ 53 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ 54 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ 55 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ 56 57 /* MU register value */ 58 MU_INBOUND_DOORBELL_HANDSHAKE = 1, 59 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2, 60 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4, 61 MU_INBOUND_DOORBELL_HMUSTOPPED = 8, 62 MU_INBOUND_DOORBELL_RESET = 16, 63 64 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1, 65 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2, 66 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4, 67 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8, 68 MU_OUTBOUND_DOORBELL_HASEVENT = 16, 69 70 /* MU status code */ 71 MU_STATE_STARTING = 1, 72 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2, 73 MU_STATE_SEND_HANDSHAKE_FRAME = 3, 74 MU_STATE_STARTED = 4, 75 MU_STATE_RESETTING = 5, 76 77 MU_MAX_DELAY = 120, 78 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 79 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 80 MU_HARD_RESET_WAIT = 30000, 81 HMU_PARTNER_TYPE = 2, 82 83 /* firmware returned values */ 84 SRB_STATUS_SUCCESS = 0x01, 85 SRB_STATUS_ERROR = 0x04, 86 SRB_STATUS_BUSY = 0x05, 87 SRB_STATUS_INVALID_REQUEST = 0x06, 88 SRB_STATUS_SELECTION_TIMEOUT = 0x0A, 89 SRB_SEE_SENSE = 0x80, 90 91 /* task attribute */ 92 TASK_ATTRIBUTE_SIMPLE = 0x0, 93 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, 94 TASK_ATTRIBUTE_ORDERED = 0x2, 95 TASK_ATTRIBUTE_ACA = 0x4, 96 97 /* request count, etc. */ 98 MU_MAX_REQUEST = 32, 99 100 /* one message wasted, use MU_MAX_REQUEST+1 101 to handle MU_MAX_REQUEST messages */ 102 MU_REQ_COUNT = (MU_MAX_REQUEST + 1), 103 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1), 104 105 STEX_CDB_LENGTH = MAX_COMMAND_SIZE, 106 REQ_VARIABLE_LEN = 1024, 107 STATUS_VAR_LEN = 128, 108 ST_CAN_QUEUE = MU_MAX_REQUEST, 109 ST_CMD_PER_LUN = MU_MAX_REQUEST, 110 ST_MAX_SG = 32, 111 112 /* sg flags */ 113 SG_CF_EOT = 0x80, /* end of table */ 114 SG_CF_64B = 0x40, /* 64 bit item */ 115 SG_CF_HOST = 0x20, /* sg in host memory */ 116 117 ST_MAX_ARRAY_SUPPORTED = 16, 118 ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1), 119 ST_MAX_LUN_PER_TARGET = 16, 120 121 st_shasta = 0, 122 st_vsc = 1, 123 st_vsc1 = 2, 124 st_yosemite = 3, 125 126 PASSTHRU_REQ_TYPE = 0x00000001, 127 PASSTHRU_REQ_NO_WAKEUP = 0x00000100, 128 ST_INTERNAL_TIMEOUT = 30, 129 130 ST_TO_CMD = 0, 131 ST_FROM_CMD = 1, 132 133 /* vendor specific commands of Promise */ 134 MGT_CMD = 0xd8, 135 SINBAND_MGT_CMD = 0xd9, 136 ARRAY_CMD = 0xe0, 137 CONTROLLER_CMD = 0xe1, 138 DEBUGGING_CMD = 0xe2, 139 PASSTHRU_CMD = 0xe3, 140 141 PASSTHRU_GET_ADAPTER = 0x05, 142 PASSTHRU_GET_DRVVER = 0x10, 143 144 CTLR_CONFIG_CMD = 0x03, 145 CTLR_SHUTDOWN = 0x0d, 146 147 CTLR_POWER_STATE_CHANGE = 0x0e, 148 CTLR_POWER_SAVING = 0x01, 149 150 PASSTHRU_SIGNATURE = 0x4e415041, 151 MGT_CMD_SIGNATURE = 0xba, 152 153 INQUIRY_EVPD = 0x01, 154 155 ST_ADDITIONAL_MEM = 0x200000, 156 }; 157 158 /* SCSI inquiry data */ 159 typedef struct st_inq { 160 u8 DeviceType :5; 161 u8 DeviceTypeQualifier :3; 162 u8 DeviceTypeModifier :7; 163 u8 RemovableMedia :1; 164 u8 Versions; 165 u8 ResponseDataFormat :4; 166 u8 HiSupport :1; 167 u8 NormACA :1; 168 u8 ReservedBit :1; 169 u8 AERC :1; 170 u8 AdditionalLength; 171 u8 Reserved[2]; 172 u8 SoftReset :1; 173 u8 CommandQueue :1; 174 u8 Reserved2 :1; 175 u8 LinkedCommands :1; 176 u8 Synchronous :1; 177 u8 Wide16Bit :1; 178 u8 Wide32Bit :1; 179 u8 RelativeAddressing :1; 180 u8 VendorId[8]; 181 u8 ProductId[16]; 182 u8 ProductRevisionLevel[4]; 183 u8 VendorSpecific[20]; 184 u8 Reserved3[40]; 185 } ST_INQ; 186 187 struct st_sgitem { 188 u8 ctrl; /* SG_CF_xxx */ 189 u8 reserved[3]; 190 __le32 count; 191 __le32 addr; 192 __le32 addr_hi; 193 }; 194 195 struct st_sgtable { 196 __le16 sg_count; 197 __le16 max_sg_count; 198 __le32 sz_in_byte; 199 struct st_sgitem table[ST_MAX_SG]; 200 }; 201 202 struct handshake_frame { 203 __le32 rb_phy; /* request payload queue physical address */ 204 __le32 rb_phy_hi; 205 __le16 req_sz; /* size of each request payload */ 206 __le16 req_cnt; /* count of reqs the buffer can hold */ 207 __le16 status_sz; /* size of each status payload */ 208 __le16 status_cnt; /* count of status the buffer can hold */ 209 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */ 210 __le32 hosttime_hi; 211 u8 partner_type; /* who sends this frame */ 212 u8 reserved0[7]; 213 __le32 partner_ver_major; 214 __le32 partner_ver_minor; 215 __le32 partner_ver_oem; 216 __le32 partner_ver_build; 217 __le32 extra_offset; /* NEW */ 218 __le32 extra_size; /* NEW */ 219 u32 reserved1[2]; 220 }; 221 222 struct req_msg { 223 __le16 tag; 224 u8 lun; 225 u8 target; 226 u8 task_attr; 227 u8 task_manage; 228 u8 prd_entry; 229 u8 payload_sz; /* payload size in 4-byte, not used */ 230 u8 cdb[STEX_CDB_LENGTH]; 231 u8 variable[REQ_VARIABLE_LEN]; 232 }; 233 234 struct status_msg { 235 __le16 tag; 236 u8 lun; 237 u8 target; 238 u8 srb_status; 239 u8 scsi_status; 240 u8 reserved; 241 u8 payload_sz; /* payload size in 4-byte */ 242 u8 variable[STATUS_VAR_LEN]; 243 }; 244 245 struct ver_info { 246 u32 major; 247 u32 minor; 248 u32 oem; 249 u32 build; 250 u32 reserved[2]; 251 }; 252 253 struct st_frame { 254 u32 base[6]; 255 u32 rom_addr; 256 257 struct ver_info drv_ver; 258 struct ver_info bios_ver; 259 260 u32 bus; 261 u32 slot; 262 u32 irq_level; 263 u32 irq_vec; 264 u32 id; 265 u32 subid; 266 267 u32 dimm_size; 268 u8 dimm_type; 269 u8 reserved[3]; 270 271 u32 channel; 272 u32 reserved1; 273 }; 274 275 struct st_drvver { 276 u32 major; 277 u32 minor; 278 u32 oem; 279 u32 build; 280 u32 signature[2]; 281 u8 console_id; 282 u8 host_no; 283 u8 reserved0[2]; 284 u32 reserved[3]; 285 }; 286 287 #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg)) 288 #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg)) 289 #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE) 290 #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ)) 291 #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE) 292 293 struct st_ccb { 294 struct req_msg *req; 295 struct scsi_cmnd *cmd; 296 297 void *sense_buffer; 298 unsigned int sense_bufflen; 299 int sg_count; 300 301 u32 req_type; 302 u8 srb_status; 303 u8 scsi_status; 304 }; 305 306 struct st_hba { 307 void __iomem *mmio_base; /* iomapped PCI memory space */ 308 void *dma_mem; 309 dma_addr_t dma_handle; 310 size_t dma_size; 311 312 struct Scsi_Host *host; 313 struct pci_dev *pdev; 314 315 u32 req_head; 316 u32 req_tail; 317 u32 status_head; 318 u32 status_tail; 319 320 struct status_msg *status_buffer; 321 void *copy_buffer; /* temp buffer for driver-handled commands */ 322 struct st_ccb ccb[MU_MAX_REQUEST]; 323 struct st_ccb *wait_ccb; 324 wait_queue_head_t waitq; 325 326 unsigned int mu_status; 327 int out_req_cnt; 328 329 unsigned int cardtype; 330 }; 331 332 static const char console_inq_page[] = 333 { 334 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, 335 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ 336 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ 337 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ 338 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ 339 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ 340 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ 341 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 342 }; 343 344 MODULE_AUTHOR("Ed Lin"); 345 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); 346 MODULE_LICENSE("GPL"); 347 MODULE_VERSION(ST_DRIVER_VERSION); 348 349 static void stex_gettime(__le32 *time) 350 { 351 struct timeval tv; 352 do_gettimeofday(&tv); 353 354 *time = cpu_to_le32(tv.tv_sec & 0xffffffff); 355 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16); 356 } 357 358 static struct status_msg *stex_get_status(struct st_hba *hba) 359 { 360 struct status_msg *status = 361 hba->status_buffer + hba->status_tail; 362 363 ++hba->status_tail; 364 hba->status_tail %= MU_STATUS_COUNT; 365 366 return status; 367 } 368 369 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq) 370 { 371 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; 372 373 cmd->sense_buffer[0] = 0x70; /* fixed format, current */ 374 cmd->sense_buffer[2] = sk; 375 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */ 376 cmd->sense_buffer[12] = asc; 377 cmd->sense_buffer[13] = ascq; 378 } 379 380 static void stex_invalid_field(struct scsi_cmnd *cmd, 381 void (*done)(struct scsi_cmnd *)) 382 { 383 /* "Invalid field in cbd" */ 384 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0); 385 done(cmd); 386 } 387 388 static struct req_msg *stex_alloc_req(struct st_hba *hba) 389 { 390 struct req_msg *req = ((struct req_msg *)hba->dma_mem) + 391 hba->req_head; 392 393 ++hba->req_head; 394 hba->req_head %= MU_REQ_COUNT; 395 396 return req; 397 } 398 399 static int stex_map_sg(struct st_hba *hba, 400 struct req_msg *req, struct st_ccb *ccb) 401 { 402 struct pci_dev *pdev = hba->pdev; 403 struct scsi_cmnd *cmd; 404 dma_addr_t dma_handle; 405 struct scatterlist *src; 406 struct st_sgtable *dst; 407 int i; 408 409 cmd = ccb->cmd; 410 dst = (struct st_sgtable *)req->variable; 411 dst->max_sg_count = cpu_to_le16(ST_MAX_SG); 412 dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen); 413 414 if (cmd->use_sg) { 415 int n_elem; 416 417 src = (struct scatterlist *) cmd->request_buffer; 418 n_elem = pci_map_sg(pdev, src, 419 cmd->use_sg, cmd->sc_data_direction); 420 if (n_elem <= 0) 421 return -EIO; 422 423 ccb->sg_count = n_elem; 424 dst->sg_count = cpu_to_le16((u16)n_elem); 425 426 for (i = 0; i < n_elem; i++, src++) { 427 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src)); 428 dst->table[i].addr = 429 cpu_to_le32(sg_dma_address(src) & 0xffffffff); 430 dst->table[i].addr_hi = 431 cpu_to_le32((sg_dma_address(src) >> 16) >> 16); 432 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST; 433 } 434 dst->table[--i].ctrl |= SG_CF_EOT; 435 return 0; 436 } 437 438 dma_handle = pci_map_single(pdev, cmd->request_buffer, 439 cmd->request_bufflen, cmd->sc_data_direction); 440 cmd->SCp.dma_handle = dma_handle; 441 442 ccb->sg_count = 1; 443 dst->sg_count = cpu_to_le16(1); 444 dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff); 445 dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16); 446 dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen); 447 dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST; 448 449 return 0; 450 } 451 452 static void stex_internal_copy(struct scsi_cmnd *cmd, 453 const void *src, size_t *count, int sg_count, int direction) 454 { 455 size_t lcount; 456 size_t len; 457 void *s, *d, *base = NULL; 458 if (*count > cmd->request_bufflen) 459 *count = cmd->request_bufflen; 460 lcount = *count; 461 while (lcount) { 462 len = lcount; 463 s = (void *)src; 464 if (cmd->use_sg) { 465 size_t offset = *count - lcount; 466 s += offset; 467 base = scsi_kmap_atomic_sg(cmd->request_buffer, 468 sg_count, &offset, &len); 469 if (base == NULL) { 470 *count -= lcount; 471 return; 472 } 473 d = base + offset; 474 } else 475 d = cmd->request_buffer; 476 477 if (direction == ST_TO_CMD) 478 memcpy(d, s, len); 479 else 480 memcpy(s, d, len); 481 482 lcount -= len; 483 if (cmd->use_sg) 484 scsi_kunmap_atomic_sg(base); 485 } 486 } 487 488 static int stex_direct_copy(struct scsi_cmnd *cmd, 489 const void *src, size_t count) 490 { 491 struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 492 size_t cp_len = count; 493 int n_elem = 0; 494 495 if (cmd->use_sg) { 496 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer, 497 cmd->use_sg, cmd->sc_data_direction); 498 if (n_elem <= 0) 499 return 0; 500 } 501 502 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD); 503 504 if (cmd->use_sg) 505 pci_unmap_sg(hba->pdev, cmd->request_buffer, 506 cmd->use_sg, cmd->sc_data_direction); 507 return cp_len == count; 508 } 509 510 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) 511 { 512 struct st_frame *p; 513 size_t count = sizeof(struct st_frame); 514 515 p = hba->copy_buffer; 516 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD); 517 memset(p->base, 0, sizeof(u32)*6); 518 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); 519 p->rom_addr = 0; 520 521 p->drv_ver.major = ST_VER_MAJOR; 522 p->drv_ver.minor = ST_VER_MINOR; 523 p->drv_ver.oem = ST_OEM; 524 p->drv_ver.build = ST_BUILD_VER; 525 526 p->bus = hba->pdev->bus->number; 527 p->slot = hba->pdev->devfn; 528 p->irq_level = 0; 529 p->irq_vec = hba->pdev->irq; 530 p->id = hba->pdev->vendor << 16 | hba->pdev->device; 531 p->subid = 532 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; 533 534 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD); 535 } 536 537 static void 538 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 539 { 540 req->tag = cpu_to_le16(tag); 541 req->task_attr = TASK_ATTRIBUTE_SIMPLE; 542 req->task_manage = 0; /* not supported yet */ 543 544 hba->ccb[tag].req = req; 545 hba->out_req_cnt++; 546 547 writel(hba->req_head, hba->mmio_base + IMR0); 548 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); 549 readl(hba->mmio_base + IDBL); /* flush */ 550 } 551 552 static int 553 stex_slave_alloc(struct scsi_device *sdev) 554 { 555 /* Cheat: usually extracted from Inquiry data */ 556 sdev->tagged_supported = 1; 557 558 scsi_activate_tcq(sdev, sdev->host->can_queue); 559 560 return 0; 561 } 562 563 static int 564 stex_slave_config(struct scsi_device *sdev) 565 { 566 sdev->use_10_for_rw = 1; 567 sdev->use_10_for_ms = 1; 568 sdev->timeout = 60 * HZ; 569 sdev->tagged_supported = 1; 570 571 return 0; 572 } 573 574 static void 575 stex_slave_destroy(struct scsi_device *sdev) 576 { 577 scsi_deactivate_tcq(sdev, 1); 578 } 579 580 static int 581 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *)) 582 { 583 struct st_hba *hba; 584 struct Scsi_Host *host; 585 unsigned int id,lun; 586 struct req_msg *req; 587 u16 tag; 588 host = cmd->device->host; 589 id = cmd->device->id; 590 lun = cmd->device->channel; /* firmware lun issue work around */ 591 hba = (struct st_hba *) &host->hostdata[0]; 592 593 switch (cmd->cmnd[0]) { 594 case MODE_SENSE_10: 595 { 596 static char ms10_caching_page[12] = 597 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; 598 unsigned char page; 599 page = cmd->cmnd[2] & 0x3f; 600 if (page == 0x8 || page == 0x3f) { 601 stex_direct_copy(cmd, ms10_caching_page, 602 sizeof(ms10_caching_page)); 603 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 604 done(cmd); 605 } else 606 stex_invalid_field(cmd, done); 607 return 0; 608 } 609 case INQUIRY: 610 if (id != ST_MAX_ARRAY_SUPPORTED) 611 break; 612 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { 613 stex_direct_copy(cmd, console_inq_page, 614 sizeof(console_inq_page)); 615 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 616 done(cmd); 617 } else 618 stex_invalid_field(cmd, done); 619 return 0; 620 case PASSTHRU_CMD: 621 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { 622 struct st_drvver ver; 623 ver.major = ST_VER_MAJOR; 624 ver.minor = ST_VER_MINOR; 625 ver.oem = ST_OEM; 626 ver.build = ST_BUILD_VER; 627 ver.signature[0] = PASSTHRU_SIGNATURE; 628 ver.console_id = ST_MAX_ARRAY_SUPPORTED; 629 ver.host_no = hba->host->host_no; 630 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ? 631 DID_OK << 16 | COMMAND_COMPLETE << 8 : 632 DID_ERROR << 16 | COMMAND_COMPLETE << 8; 633 done(cmd); 634 return 0; 635 } 636 default: 637 break; 638 } 639 640 cmd->scsi_done = done; 641 642 tag = cmd->request->tag; 643 644 if (unlikely(tag >= host->can_queue)) 645 return SCSI_MLQUEUE_HOST_BUSY; 646 647 req = stex_alloc_req(hba); 648 649 if (hba->cardtype == st_yosemite) { 650 req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id; 651 req->target = 0; 652 } else { 653 req->lun = lun; 654 req->target = id; 655 } 656 657 /* cdb */ 658 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); 659 660 hba->ccb[tag].cmd = cmd; 661 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; 662 hba->ccb[tag].sense_buffer = cmd->sense_buffer; 663 hba->ccb[tag].req_type = 0; 664 665 if (cmd->sc_data_direction != DMA_NONE) 666 stex_map_sg(hba, req, &hba->ccb[tag]); 667 668 stex_send_cmd(hba, req, tag); 669 return 0; 670 } 671 672 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd) 673 { 674 if (cmd->sc_data_direction != DMA_NONE) { 675 if (cmd->use_sg) 676 pci_unmap_sg(hba->pdev, cmd->request_buffer, 677 cmd->use_sg, cmd->sc_data_direction); 678 else 679 pci_unmap_single(hba->pdev, cmd->SCp.dma_handle, 680 cmd->request_bufflen, cmd->sc_data_direction); 681 } 682 } 683 684 static void stex_scsi_done(struct st_ccb *ccb) 685 { 686 struct scsi_cmnd *cmd = ccb->cmd; 687 int result; 688 689 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { 690 result = ccb->scsi_status; 691 switch (ccb->scsi_status) { 692 case SAM_STAT_GOOD: 693 result |= DID_OK << 16 | COMMAND_COMPLETE << 8; 694 break; 695 case SAM_STAT_CHECK_CONDITION: 696 result |= DRIVER_SENSE << 24; 697 break; 698 case SAM_STAT_BUSY: 699 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 700 break; 701 default: 702 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; 703 break; 704 } 705 } 706 else if (ccb->srb_status & SRB_SEE_SENSE) 707 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; 708 else switch (ccb->srb_status) { 709 case SRB_STATUS_SELECTION_TIMEOUT: 710 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; 711 break; 712 case SRB_STATUS_BUSY: 713 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 714 break; 715 case SRB_STATUS_INVALID_REQUEST: 716 case SRB_STATUS_ERROR: 717 default: 718 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; 719 break; 720 } 721 722 cmd->result = result; 723 cmd->scsi_done(cmd); 724 } 725 726 static void stex_copy_data(struct st_ccb *ccb, 727 struct status_msg *resp, unsigned int variable) 728 { 729 size_t count = variable; 730 if (resp->scsi_status != SAM_STAT_GOOD) { 731 if (ccb->sense_buffer != NULL) 732 memcpy(ccb->sense_buffer, resp->variable, 733 min(variable, ccb->sense_bufflen)); 734 return; 735 } 736 737 if (ccb->cmd == NULL) 738 return; 739 stex_internal_copy(ccb->cmd, 740 resp->variable, &count, ccb->sg_count, ST_TO_CMD); 741 } 742 743 static void stex_ys_commands(struct st_hba *hba, 744 struct st_ccb *ccb, struct status_msg *resp) 745 { 746 size_t count; 747 748 if (ccb->cmd->cmnd[0] == MGT_CMD && 749 resp->scsi_status != SAM_STAT_CHECK_CONDITION) { 750 ccb->cmd->request_bufflen = 751 le32_to_cpu(*(__le32 *)&resp->variable[0]); 752 return; 753 } 754 755 if (resp->srb_status != 0) 756 return; 757 758 /* determine inquiry command status by DeviceTypeQualifier */ 759 if (ccb->cmd->cmnd[0] == INQUIRY && 760 resp->scsi_status == SAM_STAT_GOOD) { 761 ST_INQ *inq_data; 762 763 count = STEX_EXTRA_SIZE; 764 stex_internal_copy(ccb->cmd, hba->copy_buffer, 765 &count, ccb->sg_count, ST_FROM_CMD); 766 inq_data = (ST_INQ *)hba->copy_buffer; 767 if (inq_data->DeviceTypeQualifier != 0) 768 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT; 769 else 770 ccb->srb_status = SRB_STATUS_SUCCESS; 771 } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) { 772 u8 *report_lun_data = (u8 *)hba->copy_buffer; 773 774 count = STEX_EXTRA_SIZE; 775 stex_internal_copy(ccb->cmd, report_lun_data, 776 &count, ccb->sg_count, ST_FROM_CMD); 777 if (report_lun_data[2] || report_lun_data[3]) { 778 report_lun_data[2] = 0x00; 779 report_lun_data[3] = 0x08; 780 stex_internal_copy(ccb->cmd, report_lun_data, 781 &count, ccb->sg_count, ST_TO_CMD); 782 } 783 } 784 } 785 786 static void stex_mu_intr(struct st_hba *hba, u32 doorbell) 787 { 788 void __iomem *base = hba->mmio_base; 789 struct status_msg *resp; 790 struct st_ccb *ccb; 791 unsigned int size; 792 u16 tag; 793 794 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)) 795 return; 796 797 /* status payloads */ 798 hba->status_head = readl(base + OMR1); 799 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) { 800 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", 801 pci_name(hba->pdev)); 802 return; 803 } 804 805 /* 806 * it's not a valid status payload if: 807 * 1. there are no pending requests(e.g. during init stage) 808 * 2. there are some pending requests, but the controller is in 809 * reset status, and its type is not st_yosemite 810 * firmware of st_yosemite in reset status will return pending requests 811 * to driver, so we allow it to pass 812 */ 813 if (unlikely(hba->out_req_cnt <= 0 || 814 (hba->mu_status == MU_STATE_RESETTING && 815 hba->cardtype != st_yosemite))) { 816 hba->status_tail = hba->status_head; 817 goto update_status; 818 } 819 820 while (hba->status_tail != hba->status_head) { 821 resp = stex_get_status(hba); 822 tag = le16_to_cpu(resp->tag); 823 if (unlikely(tag >= hba->host->can_queue)) { 824 printk(KERN_WARNING DRV_NAME 825 "(%s): invalid tag\n", pci_name(hba->pdev)); 826 continue; 827 } 828 829 ccb = &hba->ccb[tag]; 830 if (hba->wait_ccb == ccb) 831 hba->wait_ccb = NULL; 832 if (unlikely(ccb->req == NULL)) { 833 printk(KERN_WARNING DRV_NAME 834 "(%s): lagging req\n", pci_name(hba->pdev)); 835 hba->out_req_cnt--; 836 continue; 837 } 838 839 size = resp->payload_sz * sizeof(u32); /* payload size */ 840 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 841 size > sizeof(*resp))) { 842 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", 843 pci_name(hba->pdev)); 844 } else { 845 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ 846 if (size) 847 stex_copy_data(ccb, resp, size); 848 } 849 850 ccb->srb_status = resp->srb_status; 851 ccb->scsi_status = resp->scsi_status; 852 853 if (likely(ccb->cmd != NULL)) { 854 if (hba->cardtype == st_yosemite) 855 stex_ys_commands(hba, ccb, resp); 856 857 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && 858 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) 859 stex_controller_info(hba, ccb); 860 861 stex_unmap_sg(hba, ccb->cmd); 862 stex_scsi_done(ccb); 863 hba->out_req_cnt--; 864 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) { 865 hba->out_req_cnt--; 866 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) { 867 ccb->req_type = 0; 868 continue; 869 } 870 ccb->req_type = 0; 871 if (waitqueue_active(&hba->waitq)) 872 wake_up(&hba->waitq); 873 } 874 } 875 876 update_status: 877 writel(hba->status_head, base + IMR1); 878 readl(base + IMR1); /* flush */ 879 } 880 881 static irqreturn_t stex_intr(int irq, void *__hba) 882 { 883 struct st_hba *hba = __hba; 884 void __iomem *base = hba->mmio_base; 885 u32 data; 886 unsigned long flags; 887 int handled = 0; 888 889 spin_lock_irqsave(hba->host->host_lock, flags); 890 891 data = readl(base + ODBL); 892 893 if (data && data != 0xffffffff) { 894 /* clear the interrupt */ 895 writel(data, base + ODBL); 896 readl(base + ODBL); /* flush */ 897 stex_mu_intr(hba, data); 898 handled = 1; 899 } 900 901 spin_unlock_irqrestore(hba->host->host_lock, flags); 902 903 return IRQ_RETVAL(handled); 904 } 905 906 static int stex_handshake(struct st_hba *hba) 907 { 908 void __iomem *base = hba->mmio_base; 909 struct handshake_frame *h; 910 dma_addr_t status_phys; 911 u32 data; 912 unsigned long before; 913 914 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 915 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 916 readl(base + IDBL); 917 before = jiffies; 918 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 919 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 920 printk(KERN_ERR DRV_NAME 921 "(%s): no handshake signature\n", 922 pci_name(hba->pdev)); 923 return -1; 924 } 925 rmb(); 926 msleep(1); 927 } 928 } 929 930 udelay(10); 931 932 data = readl(base + OMR1); 933 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { 934 data &= 0x0000ffff; 935 if (hba->host->can_queue > data) 936 hba->host->can_queue = data; 937 } 938 939 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); 940 h->rb_phy = cpu_to_le32(hba->dma_handle); 941 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16); 942 h->req_sz = cpu_to_le16(sizeof(struct req_msg)); 943 h->req_cnt = cpu_to_le16(MU_REQ_COUNT); 944 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 945 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT); 946 stex_gettime(&h->hosttime); 947 h->partner_type = HMU_PARTNER_TYPE; 948 if (hba->dma_size > STEX_BUFFER_SIZE) { 949 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE); 950 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM); 951 } else 952 h->extra_offset = h->extra_size = 0; 953 954 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE; 955 writel(status_phys, base + IMR0); 956 readl(base + IMR0); 957 writel((status_phys >> 16) >> 16, base + IMR1); 958 readl(base + IMR1); 959 960 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ 961 readl(base + OMR0); 962 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 963 readl(base + IDBL); /* flush */ 964 965 udelay(10); 966 before = jiffies; 967 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 968 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 969 printk(KERN_ERR DRV_NAME 970 "(%s): no signature after handshake frame\n", 971 pci_name(hba->pdev)); 972 return -1; 973 } 974 rmb(); 975 msleep(1); 976 } 977 978 writel(0, base + IMR0); 979 readl(base + IMR0); 980 writel(0, base + OMR0); 981 readl(base + OMR0); 982 writel(0, base + IMR1); 983 readl(base + IMR1); 984 writel(0, base + OMR1); 985 readl(base + OMR1); /* flush */ 986 hba->mu_status = MU_STATE_STARTED; 987 return 0; 988 } 989 990 static int stex_abort(struct scsi_cmnd *cmd) 991 { 992 struct Scsi_Host *host = cmd->device->host; 993 struct st_hba *hba = (struct st_hba *)host->hostdata; 994 u16 tag = cmd->request->tag; 995 void __iomem *base; 996 u32 data; 997 int result = SUCCESS; 998 unsigned long flags; 999 base = hba->mmio_base; 1000 spin_lock_irqsave(host->host_lock, flags); 1001 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd) 1002 hba->wait_ccb = &hba->ccb[tag]; 1003 else { 1004 for (tag = 0; tag < host->can_queue; tag++) 1005 if (hba->ccb[tag].cmd == cmd) { 1006 hba->wait_ccb = &hba->ccb[tag]; 1007 break; 1008 } 1009 if (tag >= host->can_queue) 1010 goto out; 1011 } 1012 1013 data = readl(base + ODBL); 1014 if (data == 0 || data == 0xffffffff) 1015 goto fail_out; 1016 1017 writel(data, base + ODBL); 1018 readl(base + ODBL); /* flush */ 1019 1020 stex_mu_intr(hba, data); 1021 1022 if (hba->wait_ccb == NULL) { 1023 printk(KERN_WARNING DRV_NAME 1024 "(%s): lost interrupt\n", pci_name(hba->pdev)); 1025 goto out; 1026 } 1027 1028 fail_out: 1029 stex_unmap_sg(hba, cmd); 1030 hba->wait_ccb->req = NULL; /* nullify the req's future return */ 1031 hba->wait_ccb = NULL; 1032 result = FAILED; 1033 out: 1034 spin_unlock_irqrestore(host->host_lock, flags); 1035 return result; 1036 } 1037 1038 static void stex_hard_reset(struct st_hba *hba) 1039 { 1040 struct pci_bus *bus; 1041 int i; 1042 u16 pci_cmd; 1043 u8 pci_bctl; 1044 1045 for (i = 0; i < 16; i++) 1046 pci_read_config_dword(hba->pdev, i * 4, 1047 &hba->pdev->saved_config_space[i]); 1048 1049 /* Reset secondary bus. Our controller(MU/ATU) is the only device on 1050 secondary bus. Consult Intel 80331/3 developer's manual for detail */ 1051 bus = hba->pdev->bus; 1052 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); 1053 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; 1054 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1055 msleep(1); 1056 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1057 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1058 1059 for (i = 0; i < MU_HARD_RESET_WAIT; i++) { 1060 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1061 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1062 break; 1063 msleep(1); 1064 } 1065 1066 ssleep(5); 1067 for (i = 0; i < 16; i++) 1068 pci_write_config_dword(hba->pdev, i * 4, 1069 hba->pdev->saved_config_space[i]); 1070 } 1071 1072 static int stex_reset(struct scsi_cmnd *cmd) 1073 { 1074 struct st_hba *hba; 1075 unsigned long flags; 1076 unsigned long before; 1077 hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 1078 1079 hba->mu_status = MU_STATE_RESETTING; 1080 1081 if (hba->cardtype == st_shasta) 1082 stex_hard_reset(hba); 1083 1084 if (hba->cardtype != st_yosemite) { 1085 if (stex_handshake(hba)) { 1086 printk(KERN_WARNING DRV_NAME 1087 "(%s): resetting: handshake failed\n", 1088 pci_name(hba->pdev)); 1089 return FAILED; 1090 } 1091 spin_lock_irqsave(hba->host->host_lock, flags); 1092 hba->req_head = 0; 1093 hba->req_tail = 0; 1094 hba->status_head = 0; 1095 hba->status_tail = 0; 1096 hba->out_req_cnt = 0; 1097 spin_unlock_irqrestore(hba->host->host_lock, flags); 1098 return SUCCESS; 1099 } 1100 1101 /* st_yosemite */ 1102 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL); 1103 readl(hba->mmio_base + IDBL); /* flush */ 1104 before = jiffies; 1105 while (hba->out_req_cnt > 0) { 1106 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1107 printk(KERN_WARNING DRV_NAME 1108 "(%s): reset timeout\n", pci_name(hba->pdev)); 1109 return FAILED; 1110 } 1111 msleep(1); 1112 } 1113 1114 hba->mu_status = MU_STATE_STARTED; 1115 return SUCCESS; 1116 } 1117 1118 static int stex_biosparam(struct scsi_device *sdev, 1119 struct block_device *bdev, sector_t capacity, int geom[]) 1120 { 1121 int heads = 255, sectors = 63; 1122 1123 if (capacity < 0x200000) { 1124 heads = 64; 1125 sectors = 32; 1126 } 1127 1128 sector_div(capacity, heads * sectors); 1129 1130 geom[0] = heads; 1131 geom[1] = sectors; 1132 geom[2] = capacity; 1133 1134 return 0; 1135 } 1136 1137 static struct scsi_host_template driver_template = { 1138 .module = THIS_MODULE, 1139 .name = DRV_NAME, 1140 .proc_name = DRV_NAME, 1141 .bios_param = stex_biosparam, 1142 .queuecommand = stex_queuecommand, 1143 .slave_alloc = stex_slave_alloc, 1144 .slave_configure = stex_slave_config, 1145 .slave_destroy = stex_slave_destroy, 1146 .eh_abort_handler = stex_abort, 1147 .eh_host_reset_handler = stex_reset, 1148 .can_queue = ST_CAN_QUEUE, 1149 .this_id = -1, 1150 .sg_tablesize = ST_MAX_SG, 1151 .cmd_per_lun = ST_CMD_PER_LUN, 1152 }; 1153 1154 static int stex_set_dma_mask(struct pci_dev * pdev) 1155 { 1156 int ret; 1157 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) 1158 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) 1159 return 0; 1160 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1161 if (!ret) 1162 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1163 return ret; 1164 } 1165 1166 static int __devinit 1167 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1168 { 1169 struct st_hba *hba; 1170 struct Scsi_Host *host; 1171 int err; 1172 1173 err = pci_enable_device(pdev); 1174 if (err) 1175 return err; 1176 1177 pci_set_master(pdev); 1178 1179 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); 1180 1181 if (!host) { 1182 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", 1183 pci_name(pdev)); 1184 err = -ENOMEM; 1185 goto out_disable; 1186 } 1187 1188 hba = (struct st_hba *)host->hostdata; 1189 memset(hba, 0, sizeof(struct st_hba)); 1190 1191 err = pci_request_regions(pdev, DRV_NAME); 1192 if (err < 0) { 1193 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", 1194 pci_name(pdev)); 1195 goto out_scsi_host_put; 1196 } 1197 1198 hba->mmio_base = ioremap(pci_resource_start(pdev, 0), 1199 pci_resource_len(pdev, 0)); 1200 if ( !hba->mmio_base) { 1201 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", 1202 pci_name(pdev)); 1203 err = -ENOMEM; 1204 goto out_release_regions; 1205 } 1206 1207 err = stex_set_dma_mask(pdev); 1208 if (err) { 1209 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", 1210 pci_name(pdev)); 1211 goto out_iounmap; 1212 } 1213 1214 hba->cardtype = (unsigned int) id->driver_data; 1215 if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1) 1216 hba->cardtype = st_vsc1; 1217 hba->dma_size = (hba->cardtype == st_vsc1) ? 1218 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE); 1219 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1220 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1221 if (!hba->dma_mem) { 1222 err = -ENOMEM; 1223 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", 1224 pci_name(pdev)); 1225 goto out_iounmap; 1226 } 1227 1228 hba->status_buffer = 1229 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); 1230 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE; 1231 hba->mu_status = MU_STATE_STARTING; 1232 1233 /* firmware uses id/lun pair for a logical drive, but lun would be 1234 always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use 1235 channel to map lun here */ 1236 host->max_channel = ST_MAX_LUN_PER_TARGET - 1; 1237 host->max_id = ST_MAX_TARGET_NUM; 1238 host->max_lun = 1; 1239 host->unique_id = host->host_no; 1240 host->max_cmd_len = STEX_CDB_LENGTH; 1241 1242 hba->host = host; 1243 hba->pdev = pdev; 1244 init_waitqueue_head(&hba->waitq); 1245 1246 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba); 1247 if (err) { 1248 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", 1249 pci_name(pdev)); 1250 goto out_pci_free; 1251 } 1252 1253 err = stex_handshake(hba); 1254 if (err) 1255 goto out_free_irq; 1256 1257 err = scsi_init_shared_tag_map(host, host->can_queue); 1258 if (err) { 1259 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n", 1260 pci_name(pdev)); 1261 goto out_free_irq; 1262 } 1263 1264 pci_set_drvdata(pdev, hba); 1265 1266 err = scsi_add_host(host, &pdev->dev); 1267 if (err) { 1268 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", 1269 pci_name(pdev)); 1270 goto out_free_irq; 1271 } 1272 1273 scsi_scan_host(host); 1274 1275 return 0; 1276 1277 out_free_irq: 1278 free_irq(pdev->irq, hba); 1279 out_pci_free: 1280 dma_free_coherent(&pdev->dev, hba->dma_size, 1281 hba->dma_mem, hba->dma_handle); 1282 out_iounmap: 1283 iounmap(hba->mmio_base); 1284 out_release_regions: 1285 pci_release_regions(pdev); 1286 out_scsi_host_put: 1287 scsi_host_put(host); 1288 out_disable: 1289 pci_disable_device(pdev); 1290 1291 return err; 1292 } 1293 1294 static void stex_hba_stop(struct st_hba *hba) 1295 { 1296 struct req_msg *req; 1297 unsigned long flags; 1298 unsigned long before; 1299 u16 tag = 0; 1300 1301 spin_lock_irqsave(hba->host->host_lock, flags); 1302 req = stex_alloc_req(hba); 1303 memset(req->cdb, 0, STEX_CDB_LENGTH); 1304 1305 if (hba->cardtype == st_yosemite) { 1306 req->cdb[0] = MGT_CMD; 1307 req->cdb[1] = MGT_CMD_SIGNATURE; 1308 req->cdb[2] = CTLR_CONFIG_CMD; 1309 req->cdb[3] = CTLR_SHUTDOWN; 1310 } else { 1311 req->cdb[0] = CONTROLLER_CMD; 1312 req->cdb[1] = CTLR_POWER_STATE_CHANGE; 1313 req->cdb[2] = CTLR_POWER_SAVING; 1314 } 1315 1316 hba->ccb[tag].cmd = NULL; 1317 hba->ccb[tag].sg_count = 0; 1318 hba->ccb[tag].sense_bufflen = 0; 1319 hba->ccb[tag].sense_buffer = NULL; 1320 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE; 1321 1322 stex_send_cmd(hba, req, tag); 1323 spin_unlock_irqrestore(hba->host->host_lock, flags); 1324 1325 before = jiffies; 1326 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { 1327 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) 1328 return; 1329 msleep(10); 1330 } 1331 } 1332 1333 static void stex_hba_free(struct st_hba *hba) 1334 { 1335 free_irq(hba->pdev->irq, hba); 1336 1337 iounmap(hba->mmio_base); 1338 1339 pci_release_regions(hba->pdev); 1340 1341 dma_free_coherent(&hba->pdev->dev, hba->dma_size, 1342 hba->dma_mem, hba->dma_handle); 1343 } 1344 1345 static void stex_remove(struct pci_dev *pdev) 1346 { 1347 struct st_hba *hba = pci_get_drvdata(pdev); 1348 1349 scsi_remove_host(hba->host); 1350 1351 pci_set_drvdata(pdev, NULL); 1352 1353 stex_hba_stop(hba); 1354 1355 stex_hba_free(hba); 1356 1357 scsi_host_put(hba->host); 1358 1359 pci_disable_device(pdev); 1360 } 1361 1362 static void stex_shutdown(struct pci_dev *pdev) 1363 { 1364 struct st_hba *hba = pci_get_drvdata(pdev); 1365 1366 stex_hba_stop(hba); 1367 } 1368 1369 static struct pci_device_id stex_pci_tbl[] = { 1370 /* st_shasta */ 1371 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1372 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ 1373 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1374 st_shasta }, /* SuperTrak EX12350 */ 1375 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1376 st_shasta }, /* SuperTrak EX4350 */ 1377 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1378 st_shasta }, /* SuperTrak EX24350 */ 1379 1380 /* st_vsc */ 1381 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, 1382 1383 /* st_yosemite */ 1384 { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0, 1385 st_yosemite }, /* SuperTrak EX4650 */ 1386 { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0, 1387 st_yosemite }, /* SuperTrak EX4650o */ 1388 { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0, 1389 st_yosemite }, /* SuperTrak EX8650EL */ 1390 { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0, 1391 st_yosemite }, /* SuperTrak EX8650 */ 1392 { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0, 1393 st_yosemite }, /* SuperTrak EX8654 */ 1394 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1395 st_yosemite }, /* generic st_yosemite */ 1396 { } /* terminate list */ 1397 }; 1398 MODULE_DEVICE_TABLE(pci, stex_pci_tbl); 1399 1400 static struct pci_driver stex_pci_driver = { 1401 .name = DRV_NAME, 1402 .id_table = stex_pci_tbl, 1403 .probe = stex_probe, 1404 .remove = __devexit_p(stex_remove), 1405 .shutdown = stex_shutdown, 1406 }; 1407 1408 static int __init stex_init(void) 1409 { 1410 printk(KERN_INFO DRV_NAME 1411 ": Promise SuperTrak EX Driver version: %s\n", 1412 ST_DRIVER_VERSION); 1413 1414 return pci_register_driver(&stex_pci_driver); 1415 } 1416 1417 static void __exit stex_exit(void) 1418 { 1419 pci_unregister_driver(&stex_pci_driver); 1420 } 1421 1422 module_init(stex_init); 1423 module_exit(stex_exit); 1424