1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef _QLA4X_FW_H 9 #define _QLA4X_FW_H 10 11 12 #define MAX_PRST_DEV_DB_ENTRIES 64 13 #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES 14 #define MAX_DEV_DB_ENTRIES 512 15 16 /************************************************************************* 17 * 18 * ISP 4010 I/O Register Set Structure and Definitions 19 * 20 *************************************************************************/ 21 22 struct port_ctrl_stat_regs { 23 __le32 ext_hw_conf; /* 0x50 R/W */ 24 __le32 rsrvd0; /* 0x54 */ 25 __le32 port_ctrl; /* 0x58 */ 26 __le32 port_status; /* 0x5c */ 27 __le32 rsrvd1[32]; /* 0x60-0xdf */ 28 __le32 gp_out; /* 0xe0 */ 29 __le32 gp_in; /* 0xe4 */ 30 __le32 rsrvd2[5]; /* 0xe8-0xfb */ 31 __le32 port_err_status; /* 0xfc */ 32 }; 33 34 struct host_mem_cfg_regs { 35 __le32 rsrvd0[12]; /* 0x50-0x79 */ 36 __le32 req_q_out; /* 0x80 */ 37 __le32 rsrvd1[31]; /* 0x84-0xFF */ 38 }; 39 40 /* 41 * ISP 82xx I/O Register Set structure definitions. 42 */ 43 struct device_reg_82xx { 44 __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ 45 __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ 46 __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ 47 __le32 reserve2[63]; /* Response Queue In-Pointer. */ 48 __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ 49 __le32 reserve3[63]; /* Response Queue Out-Pointer. */ 50 51 __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ 52 __le32 reserve4[24]; 53 __le32 hint; /* 0x0380 (R/W): Host interrupt register */ 54 #define HINT_MBX_INT_PENDING BIT_0 55 __le32 reserve5[31]; 56 __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ 57 __le32 reserve6[56]; 58 59 __le32 host_status; /* Offset 0x500 (R): host status */ 60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ 62 63 __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ 64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ 65 }; 66 67 /* remote register set (access via PCI memory read/write) */ 68 struct isp_reg { 69 #define MBOX_REG_COUNT 8 70 __le32 mailbox[MBOX_REG_COUNT]; 71 72 __le32 flash_address; /* 0x20 */ 73 __le32 flash_data; 74 __le32 ctrl_status; 75 76 union { 77 struct { 78 __le32 nvram; 79 __le32 reserved1[2]; /* 0x30 */ 80 } __attribute__ ((packed)) isp4010; 81 struct { 82 __le32 intr_mask; 83 __le32 nvram; /* 0x30 */ 84 __le32 semaphore; 85 } __attribute__ ((packed)) isp4022; 86 } u1; 87 88 __le32 req_q_in; /* SCSI Request Queue Producer Index */ 89 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ 90 91 __le32 reserved2[4]; /* 0x40 */ 92 93 union { 94 struct { 95 __le32 ext_hw_conf; /* 0x50 */ 96 __le32 flow_ctrl; 97 __le32 port_ctrl; 98 __le32 port_status; 99 100 __le32 reserved3[8]; /* 0x60 */ 101 102 __le32 req_q_out; /* 0x80 */ 103 104 __le32 reserved4[23]; /* 0x84 */ 105 106 __le32 gp_out; /* 0xe0 */ 107 __le32 gp_in; 108 109 __le32 reserved5[5]; 110 111 __le32 port_err_status; /* 0xfc */ 112 } __attribute__ ((packed)) isp4010; 113 struct { 114 union { 115 struct port_ctrl_stat_regs p0; 116 struct host_mem_cfg_regs p1; 117 }; 118 } __attribute__ ((packed)) isp4022; 119 } u2; 120 }; /* 256 x100 */ 121 122 123 /* Semaphore Defines for 4010 */ 124 #define QL4010_DRVR_SEM_BITS 0x00000030 125 #define QL4010_GPIO_SEM_BITS 0x000000c0 126 #define QL4010_SDRAM_SEM_BITS 0x00000300 127 #define QL4010_PHY_SEM_BITS 0x00000c00 128 #define QL4010_NVRAM_SEM_BITS 0x00003000 129 #define QL4010_FLASH_SEM_BITS 0x0000c000 130 131 #define QL4010_DRVR_SEM_MASK 0x00300000 132 #define QL4010_GPIO_SEM_MASK 0x00c00000 133 #define QL4010_SDRAM_SEM_MASK 0x03000000 134 #define QL4010_PHY_SEM_MASK 0x0c000000 135 #define QL4010_NVRAM_SEM_MASK 0x30000000 136 #define QL4010_FLASH_SEM_MASK 0xc0000000 137 138 /* Semaphore Defines for 4022 */ 139 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7 140 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4 141 142 143 #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) 144 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) 145 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) 146 #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) 147 #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) 148 149 /* nvram address for 4032 */ 150 #define NVRAM_PORT0_BOOT_MODE 0x03b1 151 #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2 152 #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb 153 #define NVRAM_PORT1_BOOT_MODE 0x07b1 154 #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2 155 #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb 156 157 158 /* Page # defines for 4022 */ 159 #define PORT_CTRL_STAT_PAGE 0 /* 4022 */ 160 #define HOST_MEM_CFG_PAGE 1 /* 4022 */ 161 #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ 162 #define PROT_STAT_PAGE 3 /* 4022 */ 163 164 /* Register Mask - sets corresponding mask bits in the upper word */ 165 static inline uint32_t set_rmask(uint32_t val) 166 { 167 return (val & 0xffff) | (val << 16); 168 } 169 170 171 static inline uint32_t clr_rmask(uint32_t val) 172 { 173 return 0 | (val << 16); 174 } 175 176 /* ctrl_status definitions */ 177 #define CSR_SCSI_PAGE_SELECT 0x00000003 178 #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ 179 #define CSR_SCSI_RESET_INTR 0x00000008 180 #define CSR_SCSI_COMPLETION_INTR 0x00000010 181 #define CSR_SCSI_PROCESSOR_INTR 0x00000020 182 #define CSR_INTR_RISC 0x00000040 183 #define CSR_BOOT_ENABLE 0x00000080 184 #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ 185 #define CSR_FUNC_NUM 0x00000700 /* 4022 */ 186 #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ 187 #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ 188 #define CSR_FATAL_ERROR 0x00004000 189 #define CSR_SOFT_RESET 0x00008000 190 #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM 191 #define ISP_CONTROL_FN0_SCSI 0x0500 192 #define ISP_CONTROL_FN1_SCSI 0x0700 193 194 #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ 195 CSR_SCSI_PROCESSOR_INTR |\ 196 CSR_SCSI_RESET_INTR) 197 198 /* ISP InterruptMask definitions */ 199 #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ 200 201 /* ISP 4022 nvram definitions */ 202 #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ 203 204 #define QL4010_NVRAM_SIZE 0x200 205 #define QL40X2_NVRAM_SIZE 0x800 206 207 /* ISP port_status definitions */ 208 209 /* ISP Semaphore definitions */ 210 211 /* ISP General Purpose Output definitions */ 212 #define GPOR_TOPCAT_RESET 0x00000004 213 214 /* shadow registers (DMA'd from HA to system memory. read only) */ 215 struct shadow_regs { 216 /* SCSI Request Queue Consumer Index */ 217 __le32 req_q_out; /* 0 x0 R */ 218 219 /* SCSI Completion Queue Producer Index */ 220 __le32 rsp_q_in; /* 4 x4 R */ 221 }; /* 8 x8 */ 222 223 224 /* External hardware configuration register */ 225 union external_hw_config_reg { 226 struct { 227 /* FIXME: Do we even need this? All values are 228 * referred to by 16 bit quantities. Platform and 229 * endianess issues. */ 230 __le32 bReserved0:1; 231 __le32 bSDRAMProtectionMethod:2; 232 __le32 bSDRAMBanks:1; 233 __le32 bSDRAMChipWidth:1; 234 __le32 bSDRAMChipSize:2; 235 __le32 bParityDisable:1; 236 __le32 bExternalMemoryType:1; 237 __le32 bFlashBIOSWriteEnable:1; 238 __le32 bFlashUpperBankSelect:1; 239 __le32 bWriteBurst:2; 240 __le32 bReserved1:3; 241 __le32 bMask:16; 242 }; 243 uint32_t Asuint32_t; 244 }; 245 246 /* 82XX Support start */ 247 /* 82xx Default FLT Addresses */ 248 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 249 #define FA_FLASH_DESCR_ADDR_82 0xFC000 250 #define FA_BOOT_LOAD_ADDR_82 0x04000 251 #define FA_BOOT_CODE_ADDR_82 0x20000 252 #define FA_RISC_CODE_ADDR_82 0x40000 253 #define FA_GOLD_RISC_CODE_ADDR_82 0x80000 254 #define FA_FLASH_ISCSI_CHAP 0x540000 255 #define FA_FLASH_CHAP_SIZE 0xC0000 256 257 /* Flash Description Table */ 258 struct qla_fdt_layout { 259 uint8_t sig[4]; 260 uint16_t version; 261 uint16_t len; 262 uint16_t checksum; 263 uint8_t unused1[2]; 264 uint8_t model[16]; 265 uint16_t man_id; 266 uint16_t id; 267 uint8_t flags; 268 uint8_t erase_cmd; 269 uint8_t alt_erase_cmd; 270 uint8_t wrt_enable_cmd; 271 uint8_t wrt_enable_bits; 272 uint8_t wrt_sts_reg_cmd; 273 uint8_t unprotect_sec_cmd; 274 uint8_t read_man_id_cmd; 275 uint32_t block_size; 276 uint32_t alt_block_size; 277 uint32_t flash_size; 278 uint32_t wrt_enable_data; 279 uint8_t read_id_addr_len; 280 uint8_t wrt_disable_bits; 281 uint8_t read_dev_id_len; 282 uint8_t chip_erase_cmd; 283 uint16_t read_timeout; 284 uint8_t protect_sec_cmd; 285 uint8_t unused2[65]; 286 }; 287 288 /* Flash Layout Table */ 289 290 struct qla_flt_location { 291 uint8_t sig[4]; 292 uint16_t start_lo; 293 uint16_t start_hi; 294 uint8_t version; 295 uint8_t unused[5]; 296 uint16_t checksum; 297 }; 298 299 struct qla_flt_header { 300 uint16_t version; 301 uint16_t length; 302 uint16_t checksum; 303 uint16_t unused; 304 }; 305 306 /* 82xx FLT Regions */ 307 #define FLT_REG_FDT 0x1a 308 #define FLT_REG_FLT 0x1c 309 #define FLT_REG_BOOTLOAD_82 0x72 310 #define FLT_REG_FW_82 0x74 311 #define FLT_REG_FW_82_1 0x97 312 #define FLT_REG_GOLD_FW_82 0x75 313 #define FLT_REG_BOOT_CODE_82 0x78 314 #define FLT_REG_ISCSI_PARAM 0x65 315 #define FLT_REG_ISCSI_CHAP 0x63 316 317 struct qla_flt_region { 318 uint32_t code; 319 uint32_t size; 320 uint32_t start; 321 uint32_t end; 322 }; 323 324 /************************************************************************* 325 * 326 * Mailbox Commands Structures and Definitions 327 * 328 *************************************************************************/ 329 330 /* Mailbox command definitions */ 331 #define MBOX_CMD_ABOUT_FW 0x0009 332 #define MBOX_CMD_PING 0x000B 333 #define MBOX_CMD_ENABLE_INTRS 0x0010 334 #define INTR_DISABLE 0 335 #define INTR_ENABLE 1 336 #define MBOX_CMD_STOP_FW 0x0014 337 #define MBOX_CMD_ABORT_TASK 0x0015 338 #define MBOX_CMD_LUN_RESET 0x0016 339 #define MBOX_CMD_TARGET_WARM_RESET 0x0017 340 #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E 341 #define MBOX_CMD_GET_FW_STATUS 0x001F 342 #define MBOX_CMD_SET_ISNS_SERVICE 0x0021 343 #define ISNS_DISABLE 0 344 #define ISNS_ENABLE 1 345 #define MBOX_CMD_COPY_FLASH 0x0024 346 #define MBOX_CMD_WRITE_FLASH 0x0025 347 #define MBOX_CMD_READ_FLASH 0x0026 348 #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 349 #define MBOX_CMD_CONN_OPEN 0x0074 350 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 351 #define LOGOUT_OPTION_CLOSE_SESSION 0x0002 352 #define LOGOUT_OPTION_RELOGIN 0x0004 353 #define LOGOUT_OPTION_FREE_DDB 0x0008 354 #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A 355 #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 356 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 357 #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 358 #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 359 #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 360 #define DDB_DS_UNASSIGNED 0x00 361 #define DDB_DS_NO_CONNECTION_ACTIVE 0x01 362 #define DDB_DS_DISCOVERY 0x02 363 #define DDB_DS_SESSION_ACTIVE 0x04 364 #define DDB_DS_SESSION_FAILED 0x06 365 #define DDB_DS_LOGIN_IN_PROCESS 0x07 366 #define MBOX_CMD_GET_FW_STATE 0x0069 367 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A 368 #define MBOX_CMD_GET_SYS_INFO 0x0078 369 #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */ 370 #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */ 371 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 372 #define MBOX_CMD_SET_ACB 0x0088 373 #define MBOX_CMD_GET_ACB 0x0089 374 #define MBOX_CMD_DISABLE_ACB 0x008A 375 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B 376 #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C 377 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D 378 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E 379 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 380 #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 381 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 382 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 383 384 /* Mailbox 1 */ 385 #define FW_STATE_READY 0x0000 386 #define FW_STATE_CONFIG_WAIT 0x0001 387 #define FW_STATE_WAIT_AUTOCONNECT 0x0002 388 #define FW_STATE_ERROR 0x0004 389 #define FW_STATE_CONFIGURING_IP 0x0008 390 391 /* Mailbox 3 */ 392 #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 393 #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 394 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 395 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 396 #define FW_ADDSTATE_LINK_UP 0x0010 397 #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 398 399 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B 400 #define IPV6_DEFAULT_DDB_ENTRY 0x0001 401 402 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 403 #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ 404 #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 405 406 /* Mailbox status definitions */ 407 #define MBOX_COMPLETION_STATUS 4 408 #define MBOX_STS_BUSY 0x0007 409 #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 410 #define MBOX_STS_COMMAND_COMPLETE 0x4000 411 #define MBOX_STS_COMMAND_ERROR 0x4005 412 413 #define MBOX_ASYNC_EVENT_STATUS 8 414 #define MBOX_ASTS_SYSTEM_ERROR 0x8002 415 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 416 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 417 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 418 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 419 #define MBOX_ASTS_LINK_UP 0x8010 420 #define MBOX_ASTS_LINK_DOWN 0x8011 421 #define MBOX_ASTS_DATABASE_CHANGED 0x8014 422 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 423 #define MBOX_ASTS_SELF_TEST_FAILED 0x8016 424 #define MBOX_ASTS_LOGIN_FAILED 0x8017 425 #define MBOX_ASTS_DNS 0x8018 426 #define MBOX_ASTS_HEARTBEAT 0x8019 427 #define MBOX_ASTS_NVRAM_INVALID 0x801A 428 #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B 429 #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C 430 #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D 431 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F 432 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 433 #define MBOX_ASTS_DUPLICATE_IP 0x8025 434 #define MBOX_ASTS_ARP_COMPLETE 0x8026 435 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 436 #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 437 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 438 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B 439 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C 440 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D 441 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E 442 #define MBOX_ASTS_TXSCVR_INSERTED 0x8130 443 #define MBOX_ASTS_TXSCVR_REMOVED 0x8131 444 445 #define ISNS_EVENT_DATA_RECEIVED 0x0000 446 #define ISNS_EVENT_CONNECTION_OPENED 0x0001 447 #define ISNS_EVENT_CONNECTION_FAILED 0x0002 448 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 449 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 450 451 /* ACB State Defines */ 452 #define ACB_STATE_UNCONFIGURED 0x00 453 #define ACB_STATE_INVALID 0x01 454 #define ACB_STATE_ACQUIRING 0x02 455 #define ACB_STATE_TENTATIVE 0x03 456 #define ACB_STATE_DEPRICATED 0x04 457 #define ACB_STATE_VALID 0x05 458 #define ACB_STATE_DISABLING 0x06 459 460 /* FLASH offsets */ 461 #define FLASH_SEGMENT_IFCB 0x04000000 462 463 #define FLASH_OPT_RMW_HOLD 0 464 #define FLASH_OPT_RMW_INIT 1 465 #define FLASH_OPT_COMMIT 2 466 #define FLASH_OPT_RMW_COMMIT 3 467 468 /*************************************************************************/ 469 470 /* Host Adapter Initialization Control Block (from host) */ 471 struct addr_ctrl_blk { 472 uint8_t version; /* 00 */ 473 #define IFCB_VER_MIN 0x01 474 #define IFCB_VER_MAX 0x02 475 uint8_t control; /* 01 */ 476 477 uint16_t fw_options; /* 02-03 */ 478 #define FWOPT_HEARTBEAT_ENABLE 0x1000 479 #define FWOPT_SESSION_MODE 0x0040 480 #define FWOPT_INITIATOR_MODE 0x0020 481 #define FWOPT_TARGET_MODE 0x0010 482 #define FWOPT_ENABLE_CRBDB 0x8000 483 484 uint16_t exec_throttle; /* 04-05 */ 485 uint8_t zio_count; /* 06 */ 486 uint8_t res0; /* 07 */ 487 uint16_t eth_mtu_size; /* 08-09 */ 488 uint16_t add_fw_options; /* 0A-0B */ 489 #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400 490 #define ADFWOPT_AUTOCONN_DISABLE 0x0002 491 492 uint8_t hb_interval; /* 0C */ 493 uint8_t inst_num; /* 0D */ 494 uint16_t res1; /* 0E-0F */ 495 uint16_t rqq_consumer_idx; /* 10-11 */ 496 uint16_t compq_producer_idx; /* 12-13 */ 497 uint16_t rqq_len; /* 14-15 */ 498 uint16_t compq_len; /* 16-17 */ 499 uint32_t rqq_addr_lo; /* 18-1B */ 500 uint32_t rqq_addr_hi; /* 1C-1F */ 501 uint32_t compq_addr_lo; /* 20-23 */ 502 uint32_t compq_addr_hi; /* 24-27 */ 503 uint32_t shdwreg_addr_lo; /* 28-2B */ 504 uint32_t shdwreg_addr_hi; /* 2C-2F */ 505 506 uint16_t iscsi_opts; /* 30-31 */ 507 uint16_t ipv4_tcp_opts; /* 32-33 */ 508 #define TCPOPT_DHCP_ENABLE 0x0200 509 uint16_t ipv4_ip_opts; /* 34-35 */ 510 #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000 511 #define IPOPT_VLAN_TAGGING_ENABLE 0x2000 512 513 uint16_t iscsi_max_pdu_size; /* 36-37 */ 514 uint8_t ipv4_tos; /* 38 */ 515 uint8_t ipv4_ttl; /* 39 */ 516 uint8_t acb_version; /* 3A */ 517 #define ACB_NOT_SUPPORTED 0x00 518 #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 519 Features */ 520 521 uint8_t res2; /* 3B */ 522 uint16_t def_timeout; /* 3C-3D */ 523 uint16_t iscsi_fburst_len; /* 3E-3F */ 524 uint16_t iscsi_def_time2wait; /* 40-41 */ 525 uint16_t iscsi_def_time2retain; /* 42-43 */ 526 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 527 uint16_t conn_ka_timeout; /* 46-47 */ 528 uint16_t ipv4_port; /* 48-49 */ 529 uint16_t iscsi_max_burst_len; /* 4A-4B */ 530 uint32_t res5; /* 4C-4F */ 531 uint8_t ipv4_addr[4]; /* 50-53 */ 532 uint16_t ipv4_vlan_tag; /* 54-55 */ 533 uint8_t ipv4_addr_state; /* 56 */ 534 uint8_t ipv4_cacheid; /* 57 */ 535 uint8_t res6[8]; /* 58-5F */ 536 uint8_t ipv4_subnet[4]; /* 60-63 */ 537 uint8_t res7[12]; /* 64-6F */ 538 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 539 uint8_t res8[0xc]; /* 74-7F */ 540 uint8_t pri_dns_srvr_ip[4];/* 80-83 */ 541 uint8_t sec_dns_srvr_ip[4];/* 84-87 */ 542 uint16_t min_eph_port; /* 88-89 */ 543 uint16_t max_eph_port; /* 8A-8B */ 544 uint8_t res9[4]; /* 8C-8F */ 545 uint8_t iscsi_alias[32];/* 90-AF */ 546 uint8_t res9_1[0x16]; /* B0-C5 */ 547 uint16_t tgt_portal_grp;/* C6-C7 */ 548 uint8_t abort_timer; /* C8 */ 549 uint8_t ipv4_tcp_wsf; /* C9 */ 550 uint8_t res10[6]; /* CA-CF */ 551 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ 552 uint8_t ipv4_dhcp_vid_len; /* D4 */ 553 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 554 uint8_t res11[20]; /* E0-F3 */ 555 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 556 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 557 uint8_t iscsi_name[224]; /* 100-1DF */ 558 uint8_t res12[32]; /* 1E0-1FF */ 559 uint32_t cookie; /* 200-203 */ 560 uint16_t ipv6_port; /* 204-205 */ 561 uint16_t ipv6_opts; /* 206-207 */ 562 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 563 #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000 564 565 uint16_t ipv6_addtl_opts; /* 208-209 */ 566 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB 567 Only */ 568 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 569 570 uint16_t ipv6_tcp_opts; /* 20A-20B */ 571 uint8_t ipv6_tcp_wsf; /* 20C */ 572 uint16_t ipv6_flow_lbl; /* 20D-20F */ 573 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 574 uint16_t ipv6_vlan_tag; /* 220-221 */ 575 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ 576 uint8_t ipv6_addr0_state; /* 223 */ 577 uint8_t ipv6_addr1_state; /* 224 */ 578 #define IP_ADDRSTATE_UNCONFIGURED 0 579 #define IP_ADDRSTATE_INVALID 1 580 #define IP_ADDRSTATE_ACQUIRING 2 581 #define IP_ADDRSTATE_TENTATIVE 3 582 #define IP_ADDRSTATE_DEPRICATED 4 583 #define IP_ADDRSTATE_PREFERRED 5 584 #define IP_ADDRSTATE_DISABLING 6 585 586 uint8_t ipv6_dflt_rtr_state; /* 225 */ 587 #define IPV6_RTRSTATE_UNKNOWN 0 588 #define IPV6_RTRSTATE_MANUAL 1 589 #define IPV6_RTRSTATE_ADVERTISED 3 590 #define IPV6_RTRSTATE_STALE 4 591 592 uint8_t ipv6_traffic_class; /* 226 */ 593 uint8_t ipv6_hop_limit; /* 227 */ 594 uint8_t ipv6_if_id[8]; /* 228-22F */ 595 uint8_t ipv6_addr0[16]; /* 230-23F */ 596 uint8_t ipv6_addr1[16]; /* 240-24F */ 597 uint32_t ipv6_nd_reach_time; /* 250-253 */ 598 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 599 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 600 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 601 uint8_t ipv6_cache_id; /* 25D */ 602 uint8_t res13[18]; /* 25E-26F */ 603 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 604 uint8_t res14[140]; /* 274-2FF */ 605 }; 606 607 struct init_fw_ctrl_blk { 608 struct addr_ctrl_blk pri; 609 /* struct addr_ctrl_blk sec;*/ 610 }; 611 612 #define PRIMARI_ACB 0 613 #define SECONDARY_ACB 1 614 615 struct addr_ctrl_blk_def { 616 uint8_t reserved1[1]; /* 00 */ 617 uint8_t control; /* 01 */ 618 uint8_t reserved2[11]; /* 02-0C */ 619 uint8_t inst_num; /* 0D */ 620 uint8_t reserved3[34]; /* 0E-2F */ 621 uint16_t iscsi_opts; /* 30-31 */ 622 uint16_t ipv4_tcp_opts; /* 32-33 */ 623 uint16_t ipv4_ip_opts; /* 34-35 */ 624 uint16_t iscsi_max_pdu_size; /* 36-37 */ 625 uint8_t ipv4_tos; /* 38 */ 626 uint8_t ipv4_ttl; /* 39 */ 627 uint8_t reserved4[2]; /* 3A-3B */ 628 uint16_t def_timeout; /* 3C-3D */ 629 uint16_t iscsi_fburst_len; /* 3E-3F */ 630 uint8_t reserved5[4]; /* 40-43 */ 631 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 632 uint8_t reserved6[2]; /* 46-47 */ 633 uint16_t ipv4_port; /* 48-49 */ 634 uint16_t iscsi_max_burst_len; /* 4A-4B */ 635 uint8_t reserved7[4]; /* 4C-4F */ 636 uint8_t ipv4_addr[4]; /* 50-53 */ 637 uint16_t ipv4_vlan_tag; /* 54-55 */ 638 uint8_t ipv4_addr_state; /* 56 */ 639 uint8_t ipv4_cacheid; /* 57 */ 640 uint8_t reserved8[8]; /* 58-5F */ 641 uint8_t ipv4_subnet[4]; /* 60-63 */ 642 uint8_t reserved9[12]; /* 64-6F */ 643 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 644 uint8_t reserved10[84]; /* 74-C7 */ 645 uint8_t abort_timer; /* C8 */ 646 uint8_t ipv4_tcp_wsf; /* C9 */ 647 uint8_t reserved11[10]; /* CA-D3 */ 648 uint8_t ipv4_dhcp_vid_len; /* D4 */ 649 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 650 uint8_t reserved12[20]; /* E0-F3 */ 651 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 652 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 653 uint8_t iscsi_name[224]; /* 100-1DF */ 654 uint8_t reserved13[32]; /* 1E0-1FF */ 655 uint32_t cookie; /* 200-203 */ 656 uint16_t ipv6_port; /* 204-205 */ 657 uint16_t ipv6_opts; /* 206-207 */ 658 uint16_t ipv6_addtl_opts; /* 208-209 */ 659 uint16_t ipv6_tcp_opts; /* 20A-20B */ 660 uint8_t ipv6_tcp_wsf; /* 20C */ 661 uint16_t ipv6_flow_lbl; /* 20D-20F */ 662 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 663 uint16_t ipv6_vlan_tag; /* 220-221 */ 664 uint8_t ipv6_lnk_lcl_addr_state; /* 222 */ 665 uint8_t ipv6_addr0_state; /* 223 */ 666 uint8_t ipv6_addr1_state; /* 224 */ 667 uint8_t ipv6_dflt_rtr_state; /* 225 */ 668 uint8_t ipv6_traffic_class; /* 226 */ 669 uint8_t ipv6_hop_limit; /* 227 */ 670 uint8_t ipv6_if_id[8]; /* 228-22F */ 671 uint8_t ipv6_addr0[16]; /* 230-23F */ 672 uint8_t ipv6_addr1[16]; /* 240-24F */ 673 uint32_t ipv6_nd_reach_time; /* 250-253 */ 674 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 675 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 676 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 677 uint8_t ipv6_cache_id; /* 25D */ 678 uint8_t reserved14[18]; /* 25E-26F */ 679 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 680 uint8_t reserved15[140]; /* 274-2FF */ 681 }; 682 683 /*************************************************************************/ 684 685 #define MAX_CHAP_ENTRIES_40XX 128 686 #define MAX_CHAP_ENTRIES_82XX 1024 687 #define MAX_RESRV_CHAP_IDX 3 688 #define FLASH_CHAP_OFFSET 0x06000000 689 690 struct ql4_chap_table { 691 uint16_t link; 692 uint8_t flags; 693 uint8_t secret_len; 694 #define MIN_CHAP_SECRET_LEN 12 695 #define MAX_CHAP_SECRET_LEN 100 696 uint8_t secret[MAX_CHAP_SECRET_LEN]; 697 #define MAX_CHAP_NAME_LEN 256 698 uint8_t name[MAX_CHAP_NAME_LEN]; 699 uint16_t reserved; 700 #define CHAP_VALID_COOKIE 0x4092 701 #define CHAP_INVALID_COOKIE 0xFFEE 702 uint16_t cookie; 703 }; 704 705 struct dev_db_entry { 706 uint16_t options; /* 00-01 */ 707 #define DDB_OPT_DISC_SESSION 0x10 708 #define DDB_OPT_TARGET 0x02 /* device is a target */ 709 #define DDB_OPT_IPV6_DEVICE 0x100 710 #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40 711 #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ 712 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ 713 714 uint16_t exec_throttle; /* 02-03 */ 715 uint16_t exec_count; /* 04-05 */ 716 uint16_t res0; /* 06-07 */ 717 uint16_t iscsi_options; /* 08-09 */ 718 uint16_t tcp_options; /* 0A-0B */ 719 uint16_t ip_options; /* 0C-0D */ 720 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ 721 #define BYTE_UNITS 512 722 uint32_t res1; /* 10-13 */ 723 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ 724 uint16_t iscsi_first_burst_len; /* 16-17 */ 725 uint16_t iscsi_def_time2wait; /* 18-19 */ 726 uint16_t iscsi_def_time2retain; /* 1A-1B */ 727 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ 728 uint16_t ka_timeout; /* 1E-1F */ 729 uint8_t isid[6]; /* 20-25 big-endian, must be converted 730 * to little-endian */ 731 uint16_t tsid; /* 26-27 */ 732 uint16_t port; /* 28-29 */ 733 uint16_t iscsi_max_burst_len; /* 2A-2B */ 734 uint16_t def_timeout; /* 2C-2D */ 735 uint16_t res2; /* 2E-2F */ 736 uint8_t ip_addr[0x10]; /* 30-3F */ 737 uint8_t iscsi_alias[0x20]; /* 40-5F */ 738 uint8_t tgt_addr[0x20]; /* 60-7F */ 739 uint16_t mss; /* 80-81 */ 740 uint16_t res3; /* 82-83 */ 741 uint16_t lcl_port; /* 84-85 */ 742 uint8_t ipv4_tos; /* 86 */ 743 uint16_t ipv6_flow_lbl; /* 87-89 */ 744 uint8_t res4[0x36]; /* 8A-BF */ 745 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a 746 * pointer to a string so we 747 * don't have to reserve soooo 748 * much RAM */ 749 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ 750 uint8_t res5[0x10]; /* 1B0-1BF */ 751 uint16_t ddb_link; /* 1C0-1C1 */ 752 uint16_t chap_tbl_idx; /* 1C2-1C3 */ 753 uint16_t tgt_portal_grp; /* 1C4-1C5 */ 754 uint8_t tcp_xmt_wsf; /* 1C6 */ 755 uint8_t tcp_rcv_wsf; /* 1C7 */ 756 uint32_t stat_sn; /* 1C8-1CB */ 757 uint32_t exp_stat_sn; /* 1CC-1CF */ 758 uint8_t res6[0x2b]; /* 1D0-1FB */ 759 #define DDB_VALID_COOKIE 0x9034 760 uint16_t cookie; /* 1FC-1FD */ 761 uint16_t len; /* 1FE-1FF */ 762 }; 763 764 /*************************************************************************/ 765 766 /* Flash definitions */ 767 768 #define FLASH_OFFSET_SYS_INFO 0x02000000 769 #define FLASH_DEFAULTBLOCKSIZE 0x20000 770 #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes 771 * for EOF 772 * signature */ 773 #define FLASH_RAW_ACCESS_ADDR 0x8e000000 774 775 #define BOOT_PARAM_OFFSET_PORT0 0x3b0 776 #define BOOT_PARAM_OFFSET_PORT1 0x7b0 777 778 #define FLASH_OFFSET_DB_INFO 0x05000000 779 #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) 780 781 782 struct sys_info_phys_addr { 783 uint8_t address[6]; /* 00-05 */ 784 uint8_t filler[2]; /* 06-07 */ 785 }; 786 787 struct flash_sys_info { 788 uint32_t cookie; /* 00-03 */ 789 uint32_t physAddrCount; /* 04-07 */ 790 struct sys_info_phys_addr physAddr[4]; /* 08-27 */ 791 uint8_t vendorId[128]; /* 28-A7 */ 792 uint8_t productId[128]; /* A8-127 */ 793 uint32_t serialNumber; /* 128-12B */ 794 795 /* PCI Configuration values */ 796 uint32_t pciDeviceVendor; /* 12C-12F */ 797 uint32_t pciDeviceId; /* 130-133 */ 798 uint32_t pciSubsysVendor; /* 134-137 */ 799 uint32_t pciSubsysId; /* 138-13B */ 800 801 /* This validates version 1. */ 802 uint32_t crumbs; /* 13C-13F */ 803 804 uint32_t enterpriseNumber; /* 140-143 */ 805 806 uint32_t mtu; /* 144-147 */ 807 uint32_t reserved0; /* 148-14b */ 808 uint32_t crumbs2; /* 14c-14f */ 809 uint8_t acSerialNumber[16]; /* 150-15f */ 810 uint32_t crumbs3; /* 160-16f */ 811 812 /* Leave this last in the struct so it is declared invalid if 813 * any new items are added. 814 */ 815 uint32_t reserved1[39]; /* 170-1ff */ 816 }; /* 200 */ 817 818 struct mbx_sys_info { 819 uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ 820 /* in this structure for GUI. */ 821 uint16_t board_id; /* 10-11 board ID code */ 822 uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ 823 uint16_t port_num; /* 14-15 network port for this PCI function */ 824 /* (port 0 is first port) */ 825 uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ 826 uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ 827 uint32_t pci_func; /* 20-23 this PCI function */ 828 unsigned char serial_number[16]; /* 24-33 serial number string */ 829 uint8_t reserved[12]; /* 34-3f */ 830 }; 831 832 struct about_fw_info { 833 uint16_t fw_major; /* 00 - 01 */ 834 uint16_t fw_minor; /* 02 - 03 */ 835 uint16_t fw_patch; /* 04 - 05 */ 836 uint16_t fw_build; /* 06 - 07 */ 837 uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ 838 uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ 839 uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ 840 uint16_t fw_load_source; /* 38 - 39 */ 841 /* 1 = Flash Primary, 842 2 = Flash Secondary, 843 3 = Host Download 844 */ 845 uint8_t reserved1[6]; /* 3A - 3F */ 846 uint16_t iscsi_major; /* 40 - 41 */ 847 uint16_t iscsi_minor; /* 42 - 43 */ 848 uint16_t bootload_major; /* 44 - 45 */ 849 uint16_t bootload_minor; /* 46 - 47 */ 850 uint16_t bootload_patch; /* 48 - 49 */ 851 uint16_t bootload_build; /* 4A - 4B */ 852 uint8_t reserved2[180]; /* 4C - FF */ 853 }; 854 855 struct crash_record { 856 uint16_t fw_major_version; /* 00 - 01 */ 857 uint16_t fw_minor_version; /* 02 - 03 */ 858 uint16_t fw_patch_version; /* 04 - 05 */ 859 uint16_t fw_build_version; /* 06 - 07 */ 860 861 uint8_t build_date[16]; /* 08 - 17 */ 862 uint8_t build_time[16]; /* 18 - 27 */ 863 uint8_t build_user[16]; /* 28 - 37 */ 864 uint8_t card_serial_num[16]; /* 38 - 47 */ 865 866 uint32_t time_of_crash_in_secs; /* 48 - 4B */ 867 uint32_t time_of_crash_in_ms; /* 4C - 4F */ 868 869 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ 870 uint16_t OAP_sd_num_words; /* 52 - 53 */ 871 uint16_t IAP_sd_num_frames; /* 54 - 55 */ 872 uint16_t in_RISC_sd_num_words; /* 56 - 57 */ 873 874 uint8_t reserved1[28]; /* 58 - 7F */ 875 876 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ 877 uint8_t in_RISC_reg_dump[256]; /*180 -27F */ 878 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ 879 }; 880 881 struct conn_event_log_entry { 882 #define MAX_CONN_EVENT_LOG_ENTRIES 100 883 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ 884 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ 885 uint16_t device_index; /* 08 - 09 */ 886 uint16_t fw_conn_state; /* 0A - 0B */ 887 uint8_t event_type; /* 0C - 0C */ 888 uint8_t error_code; /* 0D - 0D */ 889 uint16_t error_code_detail; /* 0E - 0F */ 890 uint8_t num_consecutive_events; /* 10 - 10 */ 891 uint8_t rsvd[3]; /* 11 - 13 */ 892 }; 893 894 /************************************************************************* 895 * 896 * IOCB Commands Structures and Definitions 897 * 898 *************************************************************************/ 899 #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ 900 #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ 901 #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ 902 903 /* IOCB header structure */ 904 struct qla4_header { 905 uint8_t entryType; 906 #define ET_STATUS 0x03 907 #define ET_MARKER 0x04 908 #define ET_CONT_T1 0x0A 909 #define ET_STATUS_CONTINUATION 0x10 910 #define ET_CMND_T3 0x19 911 #define ET_PASSTHRU0 0x3A 912 #define ET_PASSTHRU_STATUS 0x3C 913 914 uint8_t entryStatus; 915 uint8_t systemDefined; 916 #define SD_ISCSI_PDU 0x01 917 uint8_t entryCount; 918 919 /* SyetemDefined definition */ 920 }; 921 922 /* Generic queue entry structure*/ 923 struct queue_entry { 924 uint8_t data[60]; 925 uint32_t signature; 926 927 }; 928 929 /* 64 bit addressing segment counts*/ 930 931 #define COMMAND_SEG_A64 1 932 #define CONTINUE_SEG_A64 5 933 934 /* 64 bit addressing segment definition*/ 935 936 struct data_seg_a64 { 937 struct { 938 uint32_t addrLow; 939 uint32_t addrHigh; 940 941 } base; 942 943 uint32_t count; 944 945 }; 946 947 /* Command Type 3 entry structure*/ 948 949 struct command_t3_entry { 950 struct qla4_header hdr; /* 00-03 */ 951 952 uint32_t handle; /* 04-07 */ 953 uint16_t target; /* 08-09 */ 954 uint16_t connection_id; /* 0A-0B */ 955 956 uint8_t control_flags; /* 0C */ 957 958 /* data direction (bits 5-6) */ 959 #define CF_WRITE 0x20 960 #define CF_READ 0x40 961 #define CF_NO_DATA 0x00 962 963 /* task attributes (bits 2-0) */ 964 #define CF_HEAD_TAG 0x03 965 #define CF_ORDERED_TAG 0x02 966 #define CF_SIMPLE_TAG 0x01 967 968 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS 969 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS 970 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET 971 * PROPERLY. 972 */ 973 uint8_t state_flags; /* 0D */ 974 uint8_t cmdRefNum; /* 0E */ 975 uint8_t reserved1; /* 0F */ 976 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ 977 struct scsi_lun lun; /* FCP LUN (BE). */ 978 uint32_t cmdSeqNum; /* 28-2B */ 979 uint16_t timeout; /* 2C-2D */ 980 uint16_t dataSegCnt; /* 2E-2F */ 981 uint32_t ttlByteCnt; /* 30-33 */ 982 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ 983 984 }; 985 986 987 /* Continuation Type 1 entry structure*/ 988 struct continuation_t1_entry { 989 struct qla4_header hdr; 990 991 struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; 992 993 }; 994 995 /* Parameterize for 64 or 32 bits */ 996 #define COMMAND_SEG COMMAND_SEG_A64 997 #define CONTINUE_SEG CONTINUE_SEG_A64 998 999 #define ET_COMMAND ET_CMND_T3 1000 #define ET_CONTINUE ET_CONT_T1 1001 1002 /* Marker entry structure*/ 1003 struct qla4_marker_entry { 1004 struct qla4_header hdr; /* 00-03 */ 1005 1006 uint32_t system_defined; /* 04-07 */ 1007 uint16_t target; /* 08-09 */ 1008 uint16_t modifier; /* 0A-0B */ 1009 #define MM_LUN_RESET 0 1010 #define MM_TGT_WARM_RESET 1 1011 1012 uint16_t flags; /* 0C-0D */ 1013 uint16_t reserved1; /* 0E-0F */ 1014 struct scsi_lun lun; /* FCP LUN (BE). */ 1015 uint64_t reserved2; /* 18-1F */ 1016 uint64_t reserved3; /* 20-27 */ 1017 uint64_t reserved4; /* 28-2F */ 1018 uint64_t reserved5; /* 30-37 */ 1019 uint64_t reserved6; /* 38-3F */ 1020 }; 1021 1022 /* Status entry structure*/ 1023 struct status_entry { 1024 struct qla4_header hdr; /* 00-03 */ 1025 1026 uint32_t handle; /* 04-07 */ 1027 1028 uint8_t scsiStatus; /* 08 */ 1029 #define SCSI_CHECK_CONDITION 0x02 1030 1031 uint8_t iscsiFlags; /* 09 */ 1032 #define ISCSI_FLAG_RESIDUAL_UNDER 0x02 1033 #define ISCSI_FLAG_RESIDUAL_OVER 0x04 1034 1035 uint8_t iscsiResponse; /* 0A */ 1036 1037 uint8_t completionStatus; /* 0B */ 1038 #define SCS_COMPLETE 0x00 1039 #define SCS_INCOMPLETE 0x01 1040 #define SCS_RESET_OCCURRED 0x04 1041 #define SCS_ABORTED 0x05 1042 #define SCS_TIMEOUT 0x06 1043 #define SCS_DATA_OVERRUN 0x07 1044 #define SCS_DATA_UNDERRUN 0x15 1045 #define SCS_QUEUE_FULL 0x1C 1046 #define SCS_DEVICE_UNAVAILABLE 0x28 1047 #define SCS_DEVICE_LOGGED_OUT 0x29 1048 1049 uint8_t reserved1; /* 0C */ 1050 1051 /* state_flags MUST be at the same location as state_flags in 1052 * the Command_T3/4_Entry */ 1053 uint8_t state_flags; /* 0D */ 1054 1055 uint16_t senseDataByteCnt; /* 0E-0F */ 1056 uint32_t residualByteCnt; /* 10-13 */ 1057 uint32_t bidiResidualByteCnt; /* 14-17 */ 1058 uint32_t expSeqNum; /* 18-1B */ 1059 uint32_t maxCmdSeqNum; /* 1C-1F */ 1060 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ 1061 1062 }; 1063 1064 /* Status Continuation entry */ 1065 struct status_cont_entry { 1066 struct qla4_header hdr; /* 00-03 */ 1067 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ 1068 }; 1069 1070 struct passthru0 { 1071 struct qla4_header hdr; /* 00-03 */ 1072 uint32_t handle; /* 04-07 */ 1073 uint16_t target; /* 08-09 */ 1074 uint16_t connection_id; /* 0A-0B */ 1075 #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) 1076 1077 uint16_t control_flags; /* 0C-0D */ 1078 #define PT_FLAG_ETHERNET_FRAME 0x8000 1079 #define PT_FLAG_ISNS_PDU 0x8000 1080 #define PT_FLAG_SEND_BUFFER 0x0200 1081 #define PT_FLAG_WAIT_4_RESPONSE 0x0100 1082 #define PT_FLAG_ISCSI_PDU 0x1000 1083 1084 uint16_t timeout; /* 0E-0F */ 1085 #define PT_DEFAULT_TIMEOUT 30 /* seconds */ 1086 1087 struct data_seg_a64 out_dsd; /* 10-1B */ 1088 uint32_t res1; /* 1C-1F */ 1089 struct data_seg_a64 in_dsd; /* 20-2B */ 1090 uint8_t res2[20]; /* 2C-3F */ 1091 }; 1092 1093 struct passthru_status { 1094 struct qla4_header hdr; /* 00-03 */ 1095 uint32_t handle; /* 04-07 */ 1096 uint16_t target; /* 08-09 */ 1097 uint16_t connectionID; /* 0A-0B */ 1098 1099 uint8_t completionStatus; /* 0C */ 1100 #define PASSTHRU_STATUS_COMPLETE 0x01 1101 1102 uint8_t residualFlags; /* 0D */ 1103 1104 uint16_t timeout; /* 0E-0F */ 1105 uint16_t portNumber; /* 10-11 */ 1106 uint8_t res1[10]; /* 12-1B */ 1107 uint32_t outResidual; /* 1C-1F */ 1108 uint8_t res2[12]; /* 20-2B */ 1109 uint32_t inResidual; /* 2C-2F */ 1110 uint8_t res4[16]; /* 30-3F */ 1111 }; 1112 1113 /* 1114 * ISP queue - response queue entry definition. 1115 */ 1116 struct response { 1117 uint8_t data[60]; 1118 uint32_t signature; 1119 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1120 }; 1121 1122 struct ql_iscsi_stats { 1123 uint8_t reserved1[656]; /* 0000-028F */ 1124 uint32_t tx_cmd_pdu; /* 0290-0293 */ 1125 uint32_t tx_resp_pdu; /* 0294-0297 */ 1126 uint32_t rx_cmd_pdu; /* 0298-029B */ 1127 uint32_t rx_resp_pdu; /* 029C-029F */ 1128 1129 uint64_t tx_data_octets; /* 02A0-02A7 */ 1130 uint64_t rx_data_octets; /* 02A8-02AF */ 1131 1132 uint32_t hdr_digest_err; /* 02B0–02B3 */ 1133 uint32_t data_digest_err; /* 02B4–02B7 */ 1134 uint32_t conn_timeout_err; /* 02B8–02BB */ 1135 uint32_t framing_err; /* 02BC–02BF */ 1136 1137 uint32_t tx_nopout_pdus; /* 02C0–02C3 */ 1138 uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ 1139 uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ 1140 uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ 1141 uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ 1142 uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ 1143 uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ 1144 uint32_t tx_snack_req_pdus; /* 02DC–02DF */ 1145 1146 uint32_t rx_nopin_pdus; /* 02E0–02E3 */ 1147 uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ 1148 uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ 1149 uint32_t rx_login_resp_pdus; /* 02EC–02EF */ 1150 uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ 1151 uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ 1152 uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ 1153 1154 uint32_t rx_r2t_pdus; /* 02FC–02FF */ 1155 uint32_t rx_async_pdus; /* 0300–0303 */ 1156 uint32_t rx_reject_pdus; /* 0304–0307 */ 1157 1158 uint8_t reserved2[264]; /* 0x0308 - 0x040F */ 1159 }; 1160 1161 #endif /* _QLA4X_FW_H */ 1162