1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 #include <linux/bsg-lib.h> 29 30 #include <net/tcp.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_host.h> 33 #include <scsi/scsi_device.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_transport.h> 36 #include <scsi/scsi_transport_iscsi.h> 37 #include <scsi/scsi_bsg_iscsi.h> 38 #include <scsi/scsi_netlink.h> 39 #include <scsi/libiscsi.h> 40 41 #include "ql4_dbg.h" 42 #include "ql4_nx.h" 43 #include "ql4_fw.h" 44 #include "ql4_nvram.h" 45 46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 47 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 48 #endif 49 50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 51 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 52 #endif 53 54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 55 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 56 #endif 57 58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 59 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 60 #endif 61 62 #define ISP4XXX_PCI_FN_1 0x1 63 #define ISP4XXX_PCI_FN_2 0x3 64 65 #define QLA_SUCCESS 0 66 #define QLA_ERROR 1 67 68 /* 69 * Data bit definitions 70 */ 71 #define BIT_0 0x1 72 #define BIT_1 0x2 73 #define BIT_2 0x4 74 #define BIT_3 0x8 75 #define BIT_4 0x10 76 #define BIT_5 0x20 77 #define BIT_6 0x40 78 #define BIT_7 0x80 79 #define BIT_8 0x100 80 #define BIT_9 0x200 81 #define BIT_10 0x400 82 #define BIT_11 0x800 83 #define BIT_12 0x1000 84 #define BIT_13 0x2000 85 #define BIT_14 0x4000 86 #define BIT_15 0x8000 87 #define BIT_16 0x10000 88 #define BIT_17 0x20000 89 #define BIT_18 0x40000 90 #define BIT_19 0x80000 91 #define BIT_20 0x100000 92 #define BIT_21 0x200000 93 #define BIT_22 0x400000 94 #define BIT_23 0x800000 95 #define BIT_24 0x1000000 96 #define BIT_25 0x2000000 97 #define BIT_26 0x4000000 98 #define BIT_27 0x8000000 99 #define BIT_28 0x10000000 100 #define BIT_29 0x20000000 101 #define BIT_30 0x40000000 102 #define BIT_31 0x80000000 103 104 /** 105 * Macros to help code, maintain, etc. 106 **/ 107 #define ql4_printk(level, ha, format, arg...) \ 108 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 109 110 111 /* 112 * Host adapter default definitions 113 ***********************************/ 114 #define MAX_HBAS 16 115 #define MAX_BUSES 1 116 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 117 #define MAX_LUNS 0xffff 118 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 119 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 120 #define MAX_PDU_ENTRIES 32 121 #define INVALID_ENTRY 0xFFFF 122 #define MAX_CMDS_TO_RISC 1024 123 #define MAX_SRBS MAX_CMDS_TO_RISC 124 #define MBOX_AEN_REG_COUNT 8 125 #define MAX_INIT_RETRIES 5 126 127 /* 128 * Buffer sizes 129 */ 130 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 131 #define RESPONSE_QUEUE_DEPTH 64 132 #define QUEUE_SIZE 64 133 #define DMA_BUFFER_SIZE 512 134 135 /* 136 * Misc 137 */ 138 #define MAC_ADDR_LEN 6 /* in bytes */ 139 #define IP_ADDR_LEN 4 /* in bytes */ 140 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 141 #define DRIVER_NAME "qla4xxx" 142 143 #define MAX_LINKED_CMDS_PER_LUN 3 144 #define MAX_REQS_SERVICED_PER_INTR 1 145 146 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 147 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 148 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 149 150 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 151 /* recovery timeout */ 152 153 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 154 #define LSW(x) ((uint16_t)(x)) 155 #define LSDW(x) ((u32)((u64)(x))) 156 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 157 158 /* 159 * Retry & Timeout Values 160 */ 161 #define MBOX_TOV 60 162 #define SOFT_RESET_TOV 30 163 #define RESET_INTR_TOV 3 164 #define SEMAPHORE_TOV 10 165 #define ADAPTER_INIT_TOV 30 166 #define ADAPTER_RESET_TOV 180 167 #define EXTEND_CMD_TOV 60 168 #define WAIT_CMD_TOV 30 169 #define EH_WAIT_CMD_TOV 120 170 #define FIRMWARE_UP_TOV 60 171 #define RESET_FIRMWARE_TOV 30 172 #define LOGOUT_TOV 10 173 #define IOCB_TOV_MARGIN 10 174 #define RELOGIN_TOV 18 175 #define ISNS_DEREG_TOV 5 176 #define HBA_ONLINE_TOV 30 177 #define DISABLE_ACB_TOV 30 178 #define IP_CONFIG_TOV 30 179 #define LOGIN_TOV 12 180 181 #define MAX_RESET_HA_RETRIES 2 182 #define FW_ALIVE_WAIT_TOV 3 183 184 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 185 186 /* 187 * SCSI Request Block structure (srb) that is placed 188 * on cmd->SCp location of every I/O [We have 22 bytes available] 189 */ 190 struct srb { 191 struct list_head list; /* (8) */ 192 struct scsi_qla_host *ha; /* HA the SP is queued on */ 193 struct ddb_entry *ddb; 194 uint16_t flags; /* (1) Status flags. */ 195 196 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 197 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 198 uint8_t state; /* (1) Status flags. */ 199 200 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 201 #define SRB_FREE_STATE 1 202 #define SRB_ACTIVE_STATE 3 203 #define SRB_ACTIVE_TIMEOUT_STATE 4 204 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 205 206 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 207 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 208 struct kref srb_ref; /* reference count for this srb */ 209 uint8_t err_id; /* error id */ 210 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 211 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 212 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 213 #define SRB_ERR_OTHER 4 214 215 uint16_t reserved; 216 uint16_t iocb_tov; 217 uint16_t iocb_cnt; /* Number of used iocbs */ 218 uint16_t cc_stat; 219 220 /* Used for extended sense / status continuation */ 221 uint8_t *req_sense_ptr; 222 uint16_t req_sense_len; 223 uint16_t reserved2; 224 }; 225 226 /* 227 * Asynchronous Event Queue structure 228 */ 229 struct aen { 230 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 231 }; 232 233 struct ql4_aen_log { 234 int count; 235 struct aen entry[MAX_AEN_ENTRIES]; 236 }; 237 238 /* 239 * Device Database (DDB) structure 240 */ 241 struct ddb_entry { 242 struct scsi_qla_host *ha; 243 struct iscsi_cls_session *sess; 244 struct iscsi_cls_conn *conn; 245 246 uint16_t fw_ddb_index; /* DDB firmware index */ 247 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 248 uint16_t ddb_type; 249 #define FLASH_DDB 0x01 250 251 struct dev_db_entry fw_ddb_entry; 252 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 253 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 254 struct ddb_entry *ddb_entry, uint32_t state); 255 256 /* Driver Re-login */ 257 unsigned long flags; /* DDB Flags */ 258 uint16_t default_relogin_timeout; /* Max time to wait for 259 * relogin to complete */ 260 atomic_t retry_relogin_timer; /* Min Time between relogins 261 * (4000 only) */ 262 atomic_t relogin_timer; /* Max Time to wait for 263 * relogin to complete */ 264 atomic_t relogin_retry_count; /* Num of times relogin has been 265 * retried */ 266 uint32_t default_time2wait; /* Default Min time between 267 * relogins (+aens) */ 268 269 }; 270 271 struct qla_ddb_index { 272 struct list_head list; 273 uint16_t fw_ddb_idx; 274 struct dev_db_entry fw_ddb; 275 }; 276 277 #define DDB_IPADDR_LEN 64 278 279 struct ql4_tuple_ddb { 280 int port; 281 int tpgt; 282 char ip_addr[DDB_IPADDR_LEN]; 283 char iscsi_name[ISCSI_NAME_SIZE]; 284 uint16_t options; 285 #define DDB_OPT_IPV6 0x0e0e 286 #define DDB_OPT_IPV4 0x0f0f 287 }; 288 289 /* 290 * DDB states. 291 */ 292 #define DDB_STATE_DEAD 0 /* We can no longer talk to 293 * this device */ 294 #define DDB_STATE_ONLINE 1 /* Device ready to accept 295 * commands */ 296 #define DDB_STATE_MISSING 2 /* Device logged off, trying 297 * to re-login */ 298 299 /* 300 * DDB flags. 301 */ 302 #define DF_RELOGIN 0 /* Relogin to device */ 303 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 304 #define DF_FO_MASKED 3 305 306 307 308 struct ql82xx_hw_data { 309 /* Offsets for flash/nvram access (set to ~0 if not used). */ 310 uint32_t flash_conf_off; 311 uint32_t flash_data_off; 312 313 uint32_t fdt_wrt_disable; 314 uint32_t fdt_erase_cmd; 315 uint32_t fdt_block_size; 316 uint32_t fdt_unprotect_sec_cmd; 317 uint32_t fdt_protect_sec_cmd; 318 319 uint32_t flt_region_flt; 320 uint32_t flt_region_fdt; 321 uint32_t flt_region_boot; 322 uint32_t flt_region_bootload; 323 uint32_t flt_region_fw; 324 325 uint32_t flt_iscsi_param; 326 uint32_t flt_region_chap; 327 uint32_t flt_chap_size; 328 }; 329 330 struct qla4_8xxx_legacy_intr_set { 331 uint32_t int_vec_bit; 332 uint32_t tgt_status_reg; 333 uint32_t tgt_mask_reg; 334 uint32_t pci_int_reg; 335 }; 336 337 /* MSI-X Support */ 338 339 #define QLA_MSIX_DEFAULT 0x00 340 #define QLA_MSIX_RSP_Q 0x01 341 342 #define QLA_MSIX_ENTRIES 2 343 #define QLA_MIDX_DEFAULT 0 344 #define QLA_MIDX_RSP_Q 1 345 346 struct ql4_msix_entry { 347 int have_irq; 348 uint16_t msix_vector; 349 uint16_t msix_entry; 350 }; 351 352 /* 353 * ISP Operations 354 */ 355 struct isp_operations { 356 int (*iospace_config) (struct scsi_qla_host *ha); 357 void (*pci_config) (struct scsi_qla_host *); 358 void (*disable_intrs) (struct scsi_qla_host *); 359 void (*enable_intrs) (struct scsi_qla_host *); 360 int (*start_firmware) (struct scsi_qla_host *); 361 irqreturn_t (*intr_handler) (int , void *); 362 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 363 int (*reset_chip) (struct scsi_qla_host *); 364 int (*reset_firmware) (struct scsi_qla_host *); 365 void (*queue_iocb) (struct scsi_qla_host *); 366 void (*complete_iocb) (struct scsi_qla_host *); 367 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 368 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 369 int (*get_sys_info) (struct scsi_qla_host *); 370 }; 371 372 /*qla4xxx ipaddress configuration details */ 373 struct ipaddress_config { 374 uint16_t ipv4_options; 375 uint16_t tcp_options; 376 uint16_t ipv4_vlan_tag; 377 uint8_t ipv4_addr_state; 378 uint8_t ip_address[IP_ADDR_LEN]; 379 uint8_t subnet_mask[IP_ADDR_LEN]; 380 uint8_t gateway[IP_ADDR_LEN]; 381 uint32_t ipv6_options; 382 uint32_t ipv6_addl_options; 383 uint8_t ipv6_link_local_state; 384 uint8_t ipv6_addr0_state; 385 uint8_t ipv6_addr1_state; 386 uint8_t ipv6_default_router_state; 387 uint16_t ipv6_vlan_tag; 388 struct in6_addr ipv6_link_local_addr; 389 struct in6_addr ipv6_addr0; 390 struct in6_addr ipv6_addr1; 391 struct in6_addr ipv6_default_router_addr; 392 uint16_t eth_mtu_size; 393 uint16_t ipv4_port; 394 uint16_t ipv6_port; 395 }; 396 397 #define QL4_CHAP_MAX_NAME_LEN 256 398 #define QL4_CHAP_MAX_SECRET_LEN 100 399 #define LOCAL_CHAP 0 400 #define BIDI_CHAP 1 401 402 struct ql4_chap_format { 403 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 404 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 405 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 406 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 407 u16 intr_chap_name_length; 408 u16 intr_secret_length; 409 u16 target_chap_name_length; 410 u16 target_secret_length; 411 }; 412 413 struct ip_address_format { 414 u8 ip_type; 415 u8 ip_address[16]; 416 }; 417 418 struct ql4_conn_info { 419 u16 dest_port; 420 struct ip_address_format dest_ipaddr; 421 struct ql4_chap_format chap; 422 }; 423 424 struct ql4_boot_session_info { 425 u8 target_name[224]; 426 struct ql4_conn_info conn_list[1]; 427 }; 428 429 struct ql4_boot_tgt_info { 430 struct ql4_boot_session_info boot_pri_sess; 431 struct ql4_boot_session_info boot_sec_sess; 432 }; 433 434 /* 435 * Linux Host Adapter structure 436 */ 437 struct scsi_qla_host { 438 /* Linux adapter configuration data */ 439 unsigned long flags; 440 441 #define AF_ONLINE 0 /* 0x00000001 */ 442 #define AF_INIT_DONE 1 /* 0x00000002 */ 443 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 444 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 445 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 446 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 447 #define AF_LINK_UP 8 /* 0x00000100 */ 448 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 449 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 450 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 451 #define AF_INTx_ENABLED 15 /* 0x00008000 */ 452 #define AF_MSI_ENABLED 16 /* 0x00010000 */ 453 #define AF_MSIX_ENABLED 17 /* 0x00020000 */ 454 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 455 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 456 #define AF_EEH_BUSY 20 /* 0x00100000 */ 457 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 458 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 459 unsigned long dpc_flags; 460 461 #define DPC_RESET_HA 1 /* 0x00000002 */ 462 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 463 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 464 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 465 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 466 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 467 #define DPC_AEN 9 /* 0x00000200 */ 468 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 469 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 470 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */ 471 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/ 472 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/ 473 474 475 struct Scsi_Host *host; /* pointer to host data */ 476 uint32_t tot_ddbs; 477 478 uint16_t iocb_cnt; 479 480 /* SRB cache. */ 481 #define SRB_MIN_REQ 128 482 mempool_t *srb_mempool; 483 484 /* pci information */ 485 struct pci_dev *pdev; 486 487 struct isp_reg __iomem *reg; /* Base I/O address */ 488 unsigned long pio_address; 489 unsigned long pio_length; 490 #define MIN_IOBASE_LEN 0x100 491 492 uint16_t req_q_count; 493 494 unsigned long host_no; 495 496 /* NVRAM registers */ 497 struct eeprom_data *nvram; 498 spinlock_t hardware_lock ____cacheline_aligned; 499 uint32_t eeprom_cmd_data; 500 501 /* Counters for general statistics */ 502 uint64_t isr_count; 503 uint64_t adapter_error_count; 504 uint64_t device_error_count; 505 uint64_t total_io_count; 506 uint64_t total_mbytes_xferred; 507 uint64_t link_failure_count; 508 uint64_t invalid_crc_count; 509 uint32_t bytes_xfered; 510 uint32_t spurious_int_count; 511 uint32_t aborted_io_count; 512 uint32_t io_timeout_count; 513 uint32_t mailbox_timeout_count; 514 uint32_t seconds_since_last_intr; 515 uint32_t seconds_since_last_heartbeat; 516 uint32_t mac_index; 517 518 /* Info Needed for Management App */ 519 /* --- From GetFwVersion --- */ 520 uint32_t firmware_version[2]; 521 uint32_t patch_number; 522 uint32_t build_number; 523 uint32_t board_id; 524 525 /* --- From Init_FW --- */ 526 /* init_cb_t *init_cb; */ 527 uint16_t firmware_options; 528 uint8_t alias[32]; 529 uint8_t name_string[256]; 530 uint8_t heartbeat_interval; 531 532 /* --- From FlashSysInfo --- */ 533 uint8_t my_mac[MAC_ADDR_LEN]; 534 uint8_t serial_number[16]; 535 uint16_t port_num; 536 /* --- From GetFwState --- */ 537 uint32_t firmware_state; 538 uint32_t addl_fw_state; 539 540 /* Linux kernel thread */ 541 struct workqueue_struct *dpc_thread; 542 struct work_struct dpc_work; 543 544 /* Linux timer thread */ 545 struct timer_list timer; 546 uint32_t timer_active; 547 548 /* Recovery Timers */ 549 atomic_t check_relogin_timeouts; 550 uint32_t retry_reset_ha_cnt; 551 uint32_t isp_reset_timer; /* reset test timer */ 552 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 553 int eh_start; 554 struct list_head free_srb_q; 555 uint16_t free_srb_q_count; 556 uint16_t num_srbs_allocated; 557 558 /* DMA Memory Block */ 559 void *queues; 560 dma_addr_t queues_dma; 561 unsigned long queues_len; 562 563 #define MEM_ALIGN_VALUE \ 564 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 565 sizeof(struct queue_entry)) 566 /* request and response queue variables */ 567 dma_addr_t request_dma; 568 struct queue_entry *request_ring; 569 struct queue_entry *request_ptr; 570 dma_addr_t response_dma; 571 struct queue_entry *response_ring; 572 struct queue_entry *response_ptr; 573 dma_addr_t shadow_regs_dma; 574 struct shadow_regs *shadow_regs; 575 uint16_t request_in; /* Current indexes. */ 576 uint16_t request_out; 577 uint16_t response_in; 578 uint16_t response_out; 579 580 /* aen queue variables */ 581 uint16_t aen_q_count; /* Number of available aen_q entries */ 582 uint16_t aen_in; /* Current indexes */ 583 uint16_t aen_out; 584 struct aen aen_q[MAX_AEN_ENTRIES]; 585 586 struct ql4_aen_log aen_log;/* tracks all aens */ 587 588 /* This mutex protects several threads to do mailbox commands 589 * concurrently. 590 */ 591 struct mutex mbox_sem; 592 593 /* temporary mailbox status registers */ 594 volatile uint8_t mbox_status_count; 595 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 596 597 /* FW ddb index map */ 598 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 599 600 /* Saved srb for status continuation entry processing */ 601 struct srb *status_srb; 602 603 uint8_t acb_version; 604 605 /* qla82xx specific fields */ 606 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ 607 unsigned long nx_pcibase; /* Base I/O address */ 608 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 609 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 610 unsigned long first_page_group_start; 611 unsigned long first_page_group_end; 612 613 uint32_t crb_win; 614 uint32_t curr_window; 615 uint32_t ddr_mn_window; 616 unsigned long mn_win_crb; 617 unsigned long ms_win_crb; 618 int qdr_sn_window; 619 rwlock_t hw_lock; 620 uint16_t func_num; 621 int link_width; 622 623 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 624 u32 nx_crb_mask; 625 626 uint8_t revision_id; 627 uint32_t fw_heartbeat_counter; 628 629 struct isp_operations *isp_ops; 630 struct ql82xx_hw_data hw; 631 632 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES]; 633 634 uint32_t nx_dev_init_timeout; 635 uint32_t nx_reset_timeout; 636 637 struct completion mbx_intr_comp; 638 639 struct ipaddress_config ip_config; 640 struct iscsi_iface *iface_ipv4; 641 struct iscsi_iface *iface_ipv6_0; 642 struct iscsi_iface *iface_ipv6_1; 643 644 /* --- From About Firmware --- */ 645 uint16_t iscsi_major; 646 uint16_t iscsi_minor; 647 uint16_t bootload_major; 648 uint16_t bootload_minor; 649 uint16_t bootload_patch; 650 uint16_t bootload_build; 651 uint16_t def_timeout; /* Default login timeout */ 652 653 uint32_t flash_state; 654 #define QLFLASH_WAITING 0 655 #define QLFLASH_READING 1 656 #define QLFLASH_WRITING 2 657 struct dma_pool *chap_dma_pool; 658 uint8_t *chap_list; /* CHAP table cache */ 659 struct mutex chap_sem; 660 #define CHAP_DMA_BLOCK_SIZE 512 661 struct workqueue_struct *task_wq; 662 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 663 #define SYSFS_FLAG_FW_SEL_BOOT 2 664 struct iscsi_boot_kset *boot_kset; 665 struct ql4_boot_tgt_info boot_tgt; 666 uint16_t phy_port_num; 667 uint16_t phy_port_cnt; 668 uint16_t iscsi_pci_func_cnt; 669 uint8_t model_name[16]; 670 struct completion disable_acb_comp; 671 struct dma_pool *fw_ddb_dma_pool; 672 #define DDB_DMA_BLOCK_SIZE 512 673 uint16_t pri_ddb_idx; 674 uint16_t sec_ddb_idx; 675 int is_reset; 676 uint16_t temperature; 677 }; 678 679 struct ql4_task_data { 680 struct scsi_qla_host *ha; 681 uint8_t iocb_req_cnt; 682 dma_addr_t data_dma; 683 void *req_buffer; 684 dma_addr_t req_dma; 685 uint32_t req_len; 686 void *resp_buffer; 687 dma_addr_t resp_dma; 688 uint32_t resp_len; 689 struct iscsi_task *task; 690 struct passthru_status sts; 691 struct work_struct task_work; 692 }; 693 694 struct qla_endpoint { 695 struct Scsi_Host *host; 696 struct sockaddr dst_addr; 697 }; 698 699 struct qla_conn { 700 struct qla_endpoint *qla_ep; 701 }; 702 703 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 704 { 705 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 706 } 707 708 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 709 { 710 return ((ha->ip_config.ipv6_options & 711 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 712 } 713 714 static inline int is_qla4010(struct scsi_qla_host *ha) 715 { 716 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 717 } 718 719 static inline int is_qla4022(struct scsi_qla_host *ha) 720 { 721 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 722 } 723 724 static inline int is_qla4032(struct scsi_qla_host *ha) 725 { 726 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 727 } 728 729 static inline int is_qla40XX(struct scsi_qla_host *ha) 730 { 731 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 732 } 733 734 static inline int is_qla8022(struct scsi_qla_host *ha) 735 { 736 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 737 } 738 739 /* Note: Currently AER/EEH is now supported only for 8022 cards 740 * This function needs to be updated when AER/EEH is enabled 741 * for other cards. 742 */ 743 static inline int is_aer_supported(struct scsi_qla_host *ha) 744 { 745 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 746 } 747 748 static inline int adapter_up(struct scsi_qla_host *ha) 749 { 750 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 751 (test_bit(AF_LINK_UP, &ha->flags) != 0); 752 } 753 754 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 755 { 756 return (struct scsi_qla_host *)iscsi_host_priv(shost); 757 } 758 759 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 760 { 761 return (is_qla4010(ha) ? 762 &ha->reg->u1.isp4010.nvram : 763 &ha->reg->u1.isp4022.semaphore); 764 } 765 766 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 767 { 768 return (is_qla4010(ha) ? 769 &ha->reg->u1.isp4010.nvram : 770 &ha->reg->u1.isp4022.nvram); 771 } 772 773 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 774 { 775 return (is_qla4010(ha) ? 776 &ha->reg->u2.isp4010.ext_hw_conf : 777 &ha->reg->u2.isp4022.p0.ext_hw_conf); 778 } 779 780 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 781 { 782 return (is_qla4010(ha) ? 783 &ha->reg->u2.isp4010.port_status : 784 &ha->reg->u2.isp4022.p0.port_status); 785 } 786 787 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 788 { 789 return (is_qla4010(ha) ? 790 &ha->reg->u2.isp4010.port_ctrl : 791 &ha->reg->u2.isp4022.p0.port_ctrl); 792 } 793 794 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 795 { 796 return (is_qla4010(ha) ? 797 &ha->reg->u2.isp4010.port_err_status : 798 &ha->reg->u2.isp4022.p0.port_err_status); 799 } 800 801 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 802 { 803 return (is_qla4010(ha) ? 804 &ha->reg->u2.isp4010.gp_out : 805 &ha->reg->u2.isp4022.p0.gp_out); 806 } 807 808 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 809 { 810 return (is_qla4010(ha) ? 811 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 812 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 813 } 814 815 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 816 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 817 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 818 819 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 820 { 821 if (is_qla4010(a)) 822 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 823 QL4010_FLASH_SEM_BITS); 824 else 825 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 826 (QL4022_RESOURCE_BITS_BASE_CODE | 827 (a->mac_index)) << 13); 828 } 829 830 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 831 { 832 if (is_qla4010(a)) 833 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 834 else 835 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 836 } 837 838 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 839 { 840 if (is_qla4010(a)) 841 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 842 QL4010_NVRAM_SEM_BITS); 843 else 844 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 845 (QL4022_RESOURCE_BITS_BASE_CODE | 846 (a->mac_index)) << 10); 847 } 848 849 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 850 { 851 if (is_qla4010(a)) 852 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 853 else 854 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 855 } 856 857 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 858 { 859 if (is_qla4010(a)) 860 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 861 QL4010_DRVR_SEM_BITS); 862 else 863 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 864 (QL4022_RESOURCE_BITS_BASE_CODE | 865 (a->mac_index)) << 1); 866 } 867 868 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 869 { 870 if (is_qla4010(a)) 871 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 872 else 873 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 874 } 875 876 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 877 { 878 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 879 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 880 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 881 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 882 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 883 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 884 885 } 886 /*---------------------------------------------------------------------------*/ 887 888 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 889 890 #define INIT_ADAPTER 0 891 #define RESET_ADAPTER 1 892 893 #define PRESERVE_DDB_LIST 0 894 #define REBUILD_DDB_LIST 1 895 896 /* Defines for process_aen() */ 897 #define PROCESS_ALL_AENS 0 898 #define FLUSH_DDB_CHANGED_AENS 1 899 900 #endif /*_QLA4XXX_H */ 901