1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 #include <linux/bsg-lib.h> 29 #include <linux/vmalloc.h> 30 31 #include <net/tcp.h> 32 #include <scsi/scsi.h> 33 #include <scsi/scsi_host.h> 34 #include <scsi/scsi_device.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_transport.h> 37 #include <scsi/scsi_transport_iscsi.h> 38 #include <scsi/scsi_bsg_iscsi.h> 39 #include <scsi/scsi_netlink.h> 40 #include <scsi/libiscsi.h> 41 42 #include "ql4_dbg.h" 43 #include "ql4_nx.h" 44 #include "ql4_fw.h" 45 #include "ql4_nvram.h" 46 #include "ql4_83xx.h" 47 48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 49 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 50 #endif 51 52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 53 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 54 #endif 55 56 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 57 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 58 #endif 59 60 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 61 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 62 #endif 63 64 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324 65 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032 66 #endif 67 68 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042 69 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042 70 #endif 71 72 #define ISP4XXX_PCI_FN_1 0x1 73 #define ISP4XXX_PCI_FN_2 0x3 74 75 #define QLA_SUCCESS 0 76 #define QLA_ERROR 1 77 #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED" 78 79 /* 80 * Data bit definitions 81 */ 82 #define BIT_0 0x1 83 #define BIT_1 0x2 84 #define BIT_2 0x4 85 #define BIT_3 0x8 86 #define BIT_4 0x10 87 #define BIT_5 0x20 88 #define BIT_6 0x40 89 #define BIT_7 0x80 90 #define BIT_8 0x100 91 #define BIT_9 0x200 92 #define BIT_10 0x400 93 #define BIT_11 0x800 94 #define BIT_12 0x1000 95 #define BIT_13 0x2000 96 #define BIT_14 0x4000 97 #define BIT_15 0x8000 98 #define BIT_16 0x10000 99 #define BIT_17 0x20000 100 #define BIT_18 0x40000 101 #define BIT_19 0x80000 102 #define BIT_20 0x100000 103 #define BIT_21 0x200000 104 #define BIT_22 0x400000 105 #define BIT_23 0x800000 106 #define BIT_24 0x1000000 107 #define BIT_25 0x2000000 108 #define BIT_26 0x4000000 109 #define BIT_27 0x8000000 110 #define BIT_28 0x10000000 111 #define BIT_29 0x20000000 112 #define BIT_30 0x40000000 113 #define BIT_31 0x80000000 114 115 /** 116 * Macros to help code, maintain, etc. 117 **/ 118 #define ql4_printk(level, ha, format, arg...) \ 119 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 120 121 122 /* 123 * Host adapter default definitions 124 ***********************************/ 125 #define MAX_HBAS 16 126 #define MAX_BUSES 1 127 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 128 #define MAX_LUNS 0xffff 129 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 130 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 131 #define MAX_PDU_ENTRIES 32 132 #define INVALID_ENTRY 0xFFFF 133 #define MAX_CMDS_TO_RISC 1024 134 #define MAX_SRBS MAX_CMDS_TO_RISC 135 #define MBOX_AEN_REG_COUNT 8 136 #define MAX_INIT_RETRIES 5 137 138 /* 139 * Buffer sizes 140 */ 141 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 142 #define RESPONSE_QUEUE_DEPTH 64 143 #define QUEUE_SIZE 64 144 #define DMA_BUFFER_SIZE 512 145 #define IOCB_HIWAT_CUSHION 4 146 147 /* 148 * Misc 149 */ 150 #define MAC_ADDR_LEN 6 /* in bytes */ 151 #define IP_ADDR_LEN 4 /* in bytes */ 152 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 153 #define DRIVER_NAME "qla4xxx" 154 155 #define MAX_LINKED_CMDS_PER_LUN 3 156 #define MAX_REQS_SERVICED_PER_INTR 1 157 158 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 159 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 160 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 161 162 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 163 /* recovery timeout */ 164 165 #define LSDW(x) ((u32)((u64)(x))) 166 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 167 168 #define DEV_DB_NON_PERSISTENT 0 169 #define DEV_DB_PERSISTENT 1 170 171 #define COPY_ISID(dst_isid, src_isid) { \ 172 int i, j; \ 173 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \ 174 dst_isid[i++] = src_isid[j--]; \ 175 } 176 177 #define SET_BITVAL(o, n, v) { \ 178 if (o) \ 179 n |= v; \ 180 else \ 181 n &= ~v; \ 182 } 183 184 #define OP_STATE(o, f, p) { \ 185 p = (o & f) ? "enable" : "disable"; \ 186 } 187 188 /* 189 * Retry & Timeout Values 190 */ 191 #define MBOX_TOV 60 192 #define SOFT_RESET_TOV 30 193 #define RESET_INTR_TOV 3 194 #define SEMAPHORE_TOV 10 195 #define ADAPTER_INIT_TOV 30 196 #define ADAPTER_RESET_TOV 180 197 #define EXTEND_CMD_TOV 60 198 #define WAIT_CMD_TOV 5 199 #define EH_WAIT_CMD_TOV 120 200 #define FIRMWARE_UP_TOV 60 201 #define RESET_FIRMWARE_TOV 30 202 #define LOGOUT_TOV 10 203 #define IOCB_TOV_MARGIN 10 204 #define RELOGIN_TOV 18 205 #define ISNS_DEREG_TOV 5 206 #define HBA_ONLINE_TOV 30 207 #define DISABLE_ACB_TOV 30 208 #define IP_CONFIG_TOV 30 209 #define LOGIN_TOV 12 210 #define BOOT_LOGIN_RESP_TOV 60 211 212 #define MAX_RESET_HA_RETRIES 2 213 #define FW_ALIVE_WAIT_TOV 3 214 #define IDC_EXTEND_TOV 8 215 #define IDC_COMP_TOV 5 216 #define LINK_UP_COMP_TOV 30 217 218 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 219 220 /* 221 * SCSI Request Block structure (srb) that is placed 222 * on cmd->SCp location of every I/O [We have 22 bytes available] 223 */ 224 struct srb { 225 struct list_head list; /* (8) */ 226 struct scsi_qla_host *ha; /* HA the SP is queued on */ 227 struct ddb_entry *ddb; 228 uint16_t flags; /* (1) Status flags. */ 229 230 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 231 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 232 uint8_t state; /* (1) Status flags. */ 233 234 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 235 #define SRB_FREE_STATE 1 236 #define SRB_ACTIVE_STATE 3 237 #define SRB_ACTIVE_TIMEOUT_STATE 4 238 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 239 240 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 241 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 242 struct kref srb_ref; /* reference count for this srb */ 243 uint8_t err_id; /* error id */ 244 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 245 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 246 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 247 #define SRB_ERR_OTHER 4 248 249 uint16_t reserved; 250 uint16_t iocb_tov; 251 uint16_t iocb_cnt; /* Number of used iocbs */ 252 uint16_t cc_stat; 253 254 /* Used for extended sense / status continuation */ 255 uint8_t *req_sense_ptr; 256 uint16_t req_sense_len; 257 uint16_t reserved2; 258 }; 259 260 /* Mailbox request block structure */ 261 struct mrb { 262 struct scsi_qla_host *ha; 263 struct mbox_cmd_iocb *mbox; 264 uint32_t mbox_cmd; 265 uint16_t iocb_cnt; /* Number of used iocbs */ 266 uint32_t pid; 267 }; 268 269 /* 270 * Asynchronous Event Queue structure 271 */ 272 struct aen { 273 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 274 }; 275 276 struct ql4_aen_log { 277 int count; 278 struct aen entry[MAX_AEN_ENTRIES]; 279 }; 280 281 /* 282 * Device Database (DDB) structure 283 */ 284 struct ddb_entry { 285 struct scsi_qla_host *ha; 286 struct iscsi_cls_session *sess; 287 struct iscsi_cls_conn *conn; 288 289 uint16_t fw_ddb_index; /* DDB firmware index */ 290 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 291 uint16_t ddb_type; 292 #define FLASH_DDB 0x01 293 294 struct dev_db_entry fw_ddb_entry; 295 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 296 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 297 struct ddb_entry *ddb_entry, uint32_t state); 298 299 /* Driver Re-login */ 300 unsigned long flags; /* DDB Flags */ 301 #define DDB_CONN_CLOSE_FAILURE 0 /* 0x00000001 */ 302 303 uint16_t default_relogin_timeout; /* Max time to wait for 304 * relogin to complete */ 305 atomic_t retry_relogin_timer; /* Min Time between relogins 306 * (4000 only) */ 307 atomic_t relogin_timer; /* Max Time to wait for 308 * relogin to complete */ 309 atomic_t relogin_retry_count; /* Num of times relogin has been 310 * retried */ 311 uint32_t default_time2wait; /* Default Min time between 312 * relogins (+aens) */ 313 uint16_t chap_tbl_idx; 314 }; 315 316 struct qla_ddb_index { 317 struct list_head list; 318 uint16_t fw_ddb_idx; 319 uint16_t flash_ddb_idx; 320 struct dev_db_entry fw_ddb; 321 uint8_t flash_isid[6]; 322 }; 323 324 #define DDB_IPADDR_LEN 64 325 326 struct ql4_tuple_ddb { 327 int port; 328 int tpgt; 329 char ip_addr[DDB_IPADDR_LEN]; 330 char iscsi_name[ISCSI_NAME_SIZE]; 331 uint16_t options; 332 #define DDB_OPT_IPV6 0x0e0e 333 #define DDB_OPT_IPV4 0x0f0f 334 uint8_t isid[6]; 335 }; 336 337 /* 338 * DDB states. 339 */ 340 #define DDB_STATE_DEAD 0 /* We can no longer talk to 341 * this device */ 342 #define DDB_STATE_ONLINE 1 /* Device ready to accept 343 * commands */ 344 #define DDB_STATE_MISSING 2 /* Device logged off, trying 345 * to re-login */ 346 347 /* 348 * DDB flags. 349 */ 350 #define DF_RELOGIN 0 /* Relogin to device */ 351 #define DF_BOOT_TGT 1 /* Boot target entry */ 352 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 353 #define DF_FO_MASKED 3 354 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */ 355 356 enum qla4_work_type { 357 QLA4_EVENT_AEN, 358 QLA4_EVENT_PING_STATUS, 359 }; 360 361 struct qla4_work_evt { 362 struct list_head list; 363 enum qla4_work_type type; 364 union { 365 struct { 366 enum iscsi_host_event_code code; 367 uint32_t data_size; 368 uint8_t data[0]; 369 } aen; 370 struct { 371 uint32_t status; 372 uint32_t pid; 373 uint32_t data_size; 374 uint8_t data[0]; 375 } ping; 376 } u; 377 }; 378 379 struct ql82xx_hw_data { 380 /* Offsets for flash/nvram access (set to ~0 if not used). */ 381 uint32_t flash_conf_off; 382 uint32_t flash_data_off; 383 384 uint32_t fdt_wrt_disable; 385 uint32_t fdt_erase_cmd; 386 uint32_t fdt_block_size; 387 uint32_t fdt_unprotect_sec_cmd; 388 uint32_t fdt_protect_sec_cmd; 389 390 uint32_t flt_region_flt; 391 uint32_t flt_region_fdt; 392 uint32_t flt_region_boot; 393 uint32_t flt_region_bootload; 394 uint32_t flt_region_fw; 395 396 uint32_t flt_iscsi_param; 397 uint32_t flt_region_chap; 398 uint32_t flt_chap_size; 399 uint32_t flt_region_ddb; 400 uint32_t flt_ddb_size; 401 }; 402 403 struct qla4_8xxx_legacy_intr_set { 404 uint32_t int_vec_bit; 405 uint32_t tgt_status_reg; 406 uint32_t tgt_mask_reg; 407 uint32_t pci_int_reg; 408 }; 409 410 /* MSI-X Support */ 411 #define QLA_MSIX_ENTRIES 2 412 413 /* 414 * ISP Operations 415 */ 416 struct isp_operations { 417 int (*iospace_config) (struct scsi_qla_host *ha); 418 void (*pci_config) (struct scsi_qla_host *); 419 void (*disable_intrs) (struct scsi_qla_host *); 420 void (*enable_intrs) (struct scsi_qla_host *); 421 int (*start_firmware) (struct scsi_qla_host *); 422 int (*restart_firmware) (struct scsi_qla_host *); 423 irqreturn_t (*intr_handler) (int , void *); 424 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 425 int (*need_reset) (struct scsi_qla_host *); 426 int (*reset_chip) (struct scsi_qla_host *); 427 int (*reset_firmware) (struct scsi_qla_host *); 428 void (*queue_iocb) (struct scsi_qla_host *); 429 void (*complete_iocb) (struct scsi_qla_host *); 430 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 431 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 432 int (*get_sys_info) (struct scsi_qla_host *); 433 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong); 434 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t); 435 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *); 436 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t); 437 int (*idc_lock) (struct scsi_qla_host *); 438 void (*idc_unlock) (struct scsi_qla_host *); 439 void (*rom_lock_recovery) (struct scsi_qla_host *); 440 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int); 441 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int); 442 }; 443 444 struct ql4_mdump_size_table { 445 uint32_t size; 446 uint32_t size_cmask_02; 447 uint32_t size_cmask_04; 448 uint32_t size_cmask_08; 449 uint32_t size_cmask_10; 450 uint32_t size_cmask_FF; 451 uint32_t version; 452 }; 453 454 /*qla4xxx ipaddress configuration details */ 455 struct ipaddress_config { 456 uint16_t ipv4_options; 457 uint16_t tcp_options; 458 uint16_t ipv4_vlan_tag; 459 uint8_t ipv4_addr_state; 460 uint8_t ip_address[IP_ADDR_LEN]; 461 uint8_t subnet_mask[IP_ADDR_LEN]; 462 uint8_t gateway[IP_ADDR_LEN]; 463 uint32_t ipv6_options; 464 uint32_t ipv6_addl_options; 465 uint8_t ipv6_link_local_state; 466 uint8_t ipv6_addr0_state; 467 uint8_t ipv6_addr1_state; 468 uint8_t ipv6_default_router_state; 469 uint16_t ipv6_vlan_tag; 470 struct in6_addr ipv6_link_local_addr; 471 struct in6_addr ipv6_addr0; 472 struct in6_addr ipv6_addr1; 473 struct in6_addr ipv6_default_router_addr; 474 uint16_t eth_mtu_size; 475 uint16_t ipv4_port; 476 uint16_t ipv6_port; 477 uint8_t control; 478 uint16_t ipv6_tcp_options; 479 uint8_t tcp_wsf; 480 uint8_t ipv6_tcp_wsf; 481 uint8_t ipv4_tos; 482 uint8_t ipv4_cache_id; 483 uint8_t ipv6_cache_id; 484 uint8_t ipv4_alt_cid_len; 485 uint8_t ipv4_alt_cid[11]; 486 uint8_t ipv4_vid_len; 487 uint8_t ipv4_vid[11]; 488 uint8_t ipv4_ttl; 489 uint16_t ipv6_flow_lbl; 490 uint8_t ipv6_traffic_class; 491 uint8_t ipv6_hop_limit; 492 uint32_t ipv6_nd_reach_time; 493 uint32_t ipv6_nd_rexmit_timer; 494 uint32_t ipv6_nd_stale_timeout; 495 uint8_t ipv6_dup_addr_detect_count; 496 uint32_t ipv6_gw_advrt_mtu; 497 uint16_t def_timeout; 498 uint8_t abort_timer; 499 uint16_t iscsi_options; 500 uint16_t iscsi_max_pdu_size; 501 uint16_t iscsi_first_burst_len; 502 uint16_t iscsi_max_outstnd_r2t; 503 uint16_t iscsi_max_burst_len; 504 uint8_t iscsi_name[224]; 505 }; 506 507 #define QL4_CHAP_MAX_NAME_LEN 256 508 #define QL4_CHAP_MAX_SECRET_LEN 100 509 #define LOCAL_CHAP 0 510 #define BIDI_CHAP 1 511 512 struct ql4_chap_format { 513 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 514 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 515 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 516 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 517 u16 intr_chap_name_length; 518 u16 intr_secret_length; 519 u16 target_chap_name_length; 520 u16 target_secret_length; 521 }; 522 523 struct ip_address_format { 524 u8 ip_type; 525 u8 ip_address[16]; 526 }; 527 528 struct ql4_conn_info { 529 u16 dest_port; 530 struct ip_address_format dest_ipaddr; 531 struct ql4_chap_format chap; 532 }; 533 534 struct ql4_boot_session_info { 535 u8 target_name[224]; 536 struct ql4_conn_info conn_list[1]; 537 }; 538 539 struct ql4_boot_tgt_info { 540 struct ql4_boot_session_info boot_pri_sess; 541 struct ql4_boot_session_info boot_sec_sess; 542 }; 543 544 /* 545 * Linux Host Adapter structure 546 */ 547 struct scsi_qla_host { 548 /* Linux adapter configuration data */ 549 unsigned long flags; 550 551 #define AF_ONLINE 0 /* 0x00000001 */ 552 #define AF_INIT_DONE 1 /* 0x00000002 */ 553 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 554 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 555 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */ 556 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 557 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 558 #define AF_LINK_UP 8 /* 0x00000100 */ 559 #define AF_LOOPBACK 9 /* 0x00000200 */ 560 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 561 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 562 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 563 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 564 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 565 #define AF_EEH_BUSY 20 /* 0x00100000 */ 566 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 567 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 568 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ 569 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */ 570 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ 571 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */ 572 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */ 573 574 unsigned long dpc_flags; 575 576 #define DPC_RESET_HA 1 /* 0x00000002 */ 577 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 578 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 579 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 580 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 581 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 582 #define DPC_AEN 9 /* 0x00000200 */ 583 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 584 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 585 #define DPC_RESET_ACTIVE 20 /* 0x00100000 */ 586 #define DPC_HA_UNRECOVERABLE 21 /* 0x00200000 ISP-82xx only*/ 587 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00400000 ISP-82xx only*/ 588 #define DPC_POST_IDC_ACK 23 /* 0x00800000 */ 589 #define DPC_RESTORE_ACB 24 /* 0x01000000 */ 590 #define DPC_SYSFS_DDB_EXPORT 25 /* 0x02000000 */ 591 592 struct Scsi_Host *host; /* pointer to host data */ 593 uint32_t tot_ddbs; 594 595 uint16_t iocb_cnt; 596 uint16_t iocb_hiwat; 597 598 /* SRB cache. */ 599 #define SRB_MIN_REQ 128 600 mempool_t *srb_mempool; 601 602 /* pci information */ 603 struct pci_dev *pdev; 604 605 struct isp_reg __iomem *reg; /* Base I/O address */ 606 unsigned long pio_address; 607 unsigned long pio_length; 608 #define MIN_IOBASE_LEN 0x100 609 610 uint16_t req_q_count; 611 612 unsigned long host_no; 613 614 /* NVRAM registers */ 615 struct eeprom_data *nvram; 616 spinlock_t hardware_lock ____cacheline_aligned; 617 uint32_t eeprom_cmd_data; 618 619 /* Counters for general statistics */ 620 uint64_t isr_count; 621 uint64_t adapter_error_count; 622 uint64_t device_error_count; 623 uint64_t total_io_count; 624 uint64_t total_mbytes_xferred; 625 uint64_t link_failure_count; 626 uint64_t invalid_crc_count; 627 uint32_t bytes_xfered; 628 uint32_t spurious_int_count; 629 uint32_t aborted_io_count; 630 uint32_t io_timeout_count; 631 uint32_t mailbox_timeout_count; 632 uint32_t seconds_since_last_intr; 633 uint32_t seconds_since_last_heartbeat; 634 uint32_t mac_index; 635 636 /* Info Needed for Management App */ 637 /* --- From GetFwVersion --- */ 638 uint32_t firmware_version[2]; 639 uint32_t patch_number; 640 uint32_t build_number; 641 uint32_t board_id; 642 643 /* --- From Init_FW --- */ 644 /* init_cb_t *init_cb; */ 645 uint16_t firmware_options; 646 uint8_t alias[32]; 647 uint8_t name_string[256]; 648 uint8_t heartbeat_interval; 649 650 /* --- From FlashSysInfo --- */ 651 uint8_t my_mac[MAC_ADDR_LEN]; 652 uint8_t serial_number[16]; 653 uint16_t port_num; 654 /* --- From GetFwState --- */ 655 uint32_t firmware_state; 656 uint32_t addl_fw_state; 657 658 /* Linux kernel thread */ 659 struct workqueue_struct *dpc_thread; 660 struct work_struct dpc_work; 661 662 /* Linux timer thread */ 663 struct timer_list timer; 664 uint32_t timer_active; 665 666 /* Recovery Timers */ 667 atomic_t check_relogin_timeouts; 668 uint32_t retry_reset_ha_cnt; 669 uint32_t isp_reset_timer; /* reset test timer */ 670 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 671 int eh_start; 672 struct list_head free_srb_q; 673 uint16_t free_srb_q_count; 674 uint16_t num_srbs_allocated; 675 676 /* DMA Memory Block */ 677 void *queues; 678 dma_addr_t queues_dma; 679 unsigned long queues_len; 680 681 #define MEM_ALIGN_VALUE \ 682 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 683 sizeof(struct queue_entry)) 684 /* request and response queue variables */ 685 dma_addr_t request_dma; 686 struct queue_entry *request_ring; 687 struct queue_entry *request_ptr; 688 dma_addr_t response_dma; 689 struct queue_entry *response_ring; 690 struct queue_entry *response_ptr; 691 dma_addr_t shadow_regs_dma; 692 struct shadow_regs *shadow_regs; 693 uint16_t request_in; /* Current indexes. */ 694 uint16_t request_out; 695 uint16_t response_in; 696 uint16_t response_out; 697 698 /* aen queue variables */ 699 uint16_t aen_q_count; /* Number of available aen_q entries */ 700 uint16_t aen_in; /* Current indexes */ 701 uint16_t aen_out; 702 struct aen aen_q[MAX_AEN_ENTRIES]; 703 704 struct ql4_aen_log aen_log;/* tracks all aens */ 705 706 /* This mutex protects several threads to do mailbox commands 707 * concurrently. 708 */ 709 struct mutex mbox_sem; 710 711 /* temporary mailbox status registers */ 712 volatile uint8_t mbox_status_count; 713 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 714 715 /* FW ddb index map */ 716 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 717 718 /* Saved srb for status continuation entry processing */ 719 struct srb *status_srb; 720 721 uint8_t acb_version; 722 723 /* qla82xx specific fields */ 724 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */ 725 unsigned long nx_pcibase; /* Base I/O address */ 726 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 727 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 728 unsigned long first_page_group_start; 729 unsigned long first_page_group_end; 730 731 uint32_t crb_win; 732 uint32_t curr_window; 733 uint32_t ddr_mn_window; 734 unsigned long mn_win_crb; 735 unsigned long ms_win_crb; 736 int qdr_sn_window; 737 rwlock_t hw_lock; 738 uint16_t func_num; 739 int link_width; 740 741 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 742 u32 nx_crb_mask; 743 744 uint8_t revision_id; 745 uint32_t fw_heartbeat_counter; 746 747 struct isp_operations *isp_ops; 748 struct ql82xx_hw_data hw; 749 750 uint32_t nx_dev_init_timeout; 751 uint32_t nx_reset_timeout; 752 void *fw_dump; 753 uint32_t fw_dump_size; 754 uint32_t fw_dump_capture_mask; 755 void *fw_dump_tmplt_hdr; 756 uint32_t fw_dump_tmplt_size; 757 uint32_t fw_dump_skip_size; 758 759 struct completion mbx_intr_comp; 760 761 struct ipaddress_config ip_config; 762 struct iscsi_iface *iface_ipv4; 763 struct iscsi_iface *iface_ipv6_0; 764 struct iscsi_iface *iface_ipv6_1; 765 766 /* --- From About Firmware --- */ 767 struct about_fw_info fw_info; 768 uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */ 769 uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */ 770 uint16_t def_timeout; /* Default login timeout */ 771 772 uint32_t flash_state; 773 #define QLFLASH_WAITING 0 774 #define QLFLASH_READING 1 775 #define QLFLASH_WRITING 2 776 struct dma_pool *chap_dma_pool; 777 uint8_t *chap_list; /* CHAP table cache */ 778 struct mutex chap_sem; 779 780 #define CHAP_DMA_BLOCK_SIZE 512 781 struct workqueue_struct *task_wq; 782 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 783 #define SYSFS_FLAG_FW_SEL_BOOT 2 784 struct iscsi_boot_kset *boot_kset; 785 struct ql4_boot_tgt_info boot_tgt; 786 uint16_t phy_port_num; 787 uint16_t phy_port_cnt; 788 uint16_t iscsi_pci_func_cnt; 789 uint8_t model_name[16]; 790 struct completion disable_acb_comp; 791 struct dma_pool *fw_ddb_dma_pool; 792 #define DDB_DMA_BLOCK_SIZE 512 793 uint16_t pri_ddb_idx; 794 uint16_t sec_ddb_idx; 795 int is_reset; 796 uint16_t temperature; 797 798 /* event work list */ 799 struct list_head work_list; 800 spinlock_t work_lock; 801 802 /* mbox iocb */ 803 #define MAX_MRB 128 804 struct mrb *active_mrb_array[MAX_MRB]; 805 uint32_t mrb_index; 806 807 uint32_t *reg_tbl; 808 struct qla4_83xx_reset_template reset_tmplt; 809 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address 810 for ISP8324 and 811 and ISP8042 */ 812 uint32_t pf_bit; 813 struct qla4_83xx_idc_information idc_info; 814 struct addr_ctrl_blk *saved_acb; 815 int notify_idc_comp; 816 int notify_link_up_comp; 817 int idc_extend_tmo; 818 struct completion idc_comp; 819 struct completion link_up_comp; 820 }; 821 822 struct ql4_task_data { 823 struct scsi_qla_host *ha; 824 uint8_t iocb_req_cnt; 825 dma_addr_t data_dma; 826 void *req_buffer; 827 dma_addr_t req_dma; 828 uint32_t req_len; 829 void *resp_buffer; 830 dma_addr_t resp_dma; 831 uint32_t resp_len; 832 struct iscsi_task *task; 833 struct passthru_status sts; 834 struct work_struct task_work; 835 }; 836 837 struct qla_endpoint { 838 struct Scsi_Host *host; 839 struct sockaddr_storage dst_addr; 840 }; 841 842 struct qla_conn { 843 struct qla_endpoint *qla_ep; 844 }; 845 846 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 847 { 848 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 849 } 850 851 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 852 { 853 return ((ha->ip_config.ipv6_options & 854 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 855 } 856 857 static inline int is_qla4010(struct scsi_qla_host *ha) 858 { 859 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 860 } 861 862 static inline int is_qla4022(struct scsi_qla_host *ha) 863 { 864 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 865 } 866 867 static inline int is_qla4032(struct scsi_qla_host *ha) 868 { 869 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 870 } 871 872 static inline int is_qla40XX(struct scsi_qla_host *ha) 873 { 874 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 875 } 876 877 static inline int is_qla8022(struct scsi_qla_host *ha) 878 { 879 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 880 } 881 882 static inline int is_qla8032(struct scsi_qla_host *ha) 883 { 884 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324; 885 } 886 887 static inline int is_qla8042(struct scsi_qla_host *ha) 888 { 889 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042; 890 } 891 892 static inline int is_qla80XX(struct scsi_qla_host *ha) 893 { 894 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha); 895 } 896 897 static inline int is_aer_supported(struct scsi_qla_host *ha) 898 { 899 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) || 900 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) || 901 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042)); 902 } 903 904 static inline int adapter_up(struct scsi_qla_host *ha) 905 { 906 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 907 (test_bit(AF_LINK_UP, &ha->flags) != 0) && 908 (!test_bit(AF_LOOPBACK, &ha->flags)); 909 } 910 911 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 912 { 913 return (struct scsi_qla_host *)iscsi_host_priv(shost); 914 } 915 916 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 917 { 918 return (is_qla4010(ha) ? 919 &ha->reg->u1.isp4010.nvram : 920 &ha->reg->u1.isp4022.semaphore); 921 } 922 923 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 924 { 925 return (is_qla4010(ha) ? 926 &ha->reg->u1.isp4010.nvram : 927 &ha->reg->u1.isp4022.nvram); 928 } 929 930 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 931 { 932 return (is_qla4010(ha) ? 933 &ha->reg->u2.isp4010.ext_hw_conf : 934 &ha->reg->u2.isp4022.p0.ext_hw_conf); 935 } 936 937 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 938 { 939 return (is_qla4010(ha) ? 940 &ha->reg->u2.isp4010.port_status : 941 &ha->reg->u2.isp4022.p0.port_status); 942 } 943 944 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 945 { 946 return (is_qla4010(ha) ? 947 &ha->reg->u2.isp4010.port_ctrl : 948 &ha->reg->u2.isp4022.p0.port_ctrl); 949 } 950 951 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 952 { 953 return (is_qla4010(ha) ? 954 &ha->reg->u2.isp4010.port_err_status : 955 &ha->reg->u2.isp4022.p0.port_err_status); 956 } 957 958 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 959 { 960 return (is_qla4010(ha) ? 961 &ha->reg->u2.isp4010.gp_out : 962 &ha->reg->u2.isp4022.p0.gp_out); 963 } 964 965 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 966 { 967 return (is_qla4010(ha) ? 968 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 969 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 970 } 971 972 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 973 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 974 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 975 976 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 977 { 978 if (is_qla4010(a)) 979 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 980 QL4010_FLASH_SEM_BITS); 981 else 982 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 983 (QL4022_RESOURCE_BITS_BASE_CODE | 984 (a->mac_index)) << 13); 985 } 986 987 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 988 { 989 if (is_qla4010(a)) 990 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 991 else 992 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 993 } 994 995 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 996 { 997 if (is_qla4010(a)) 998 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 999 QL4010_NVRAM_SEM_BITS); 1000 else 1001 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 1002 (QL4022_RESOURCE_BITS_BASE_CODE | 1003 (a->mac_index)) << 10); 1004 } 1005 1006 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 1007 { 1008 if (is_qla4010(a)) 1009 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 1010 else 1011 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 1012 } 1013 1014 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 1015 { 1016 if (is_qla4010(a)) 1017 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 1018 QL4010_DRVR_SEM_BITS); 1019 else 1020 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 1021 (QL4022_RESOURCE_BITS_BASE_CODE | 1022 (a->mac_index)) << 1); 1023 } 1024 1025 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 1026 { 1027 if (is_qla4010(a)) 1028 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 1029 else 1030 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 1031 } 1032 1033 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 1034 { 1035 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 1036 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 1037 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 1038 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 1039 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 1040 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 1041 1042 } 1043 1044 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha, 1045 const uint32_t crb_reg) 1046 { 1047 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); 1048 } 1049 1050 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha, 1051 const uint32_t crb_reg, 1052 const uint32_t value) 1053 { 1054 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); 1055 } 1056 1057 /*---------------------------------------------------------------------------*/ 1058 1059 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 1060 1061 #define INIT_ADAPTER 0 1062 #define RESET_ADAPTER 1 1063 1064 #define PRESERVE_DDB_LIST 0 1065 #define REBUILD_DDB_LIST 1 1066 1067 /* Defines for process_aen() */ 1068 #define PROCESS_ALL_AENS 0 1069 #define FLUSH_DDB_CHANGED_AENS 1 1070 1071 /* Defines for udev events */ 1072 #define QL4_UEVENT_CODE_FW_DUMP 0 1073 1074 #endif /*_QLA4XXX_H */ 1075