1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2012 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL483XX_H 9 #define __QL483XX_H 10 11 /* Indirectly Mapped Registers */ 12 #define QLA83XX_FLASH_SPI_STATUS 0x2808E010 13 #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014 14 #define QLA83XX_FLASH_STATUS 0x42100004 15 #define QLA83XX_FLASH_CONTROL 0x42110004 16 #define QLA83XX_FLASH_ADDR 0x42110008 17 #define QLA83XX_FLASH_WRDATA 0x4211000C 18 #define QLA83XX_FLASH_RDDATA 0x42110018 19 #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030 20 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 21 22 /* Directly Mapped Registers in 83xx register table */ 23 24 /* Flash access regs */ 25 #define QLA83XX_FLASH_LOCK 0x3850 26 #define QLA83XX_FLASH_UNLOCK 0x3854 27 #define QLA83XX_FLASH_LOCK_ID 0x3500 28 29 /* Driver Lock regs */ 30 #define QLA83XX_DRV_LOCK 0x3868 31 #define QLA83XX_DRV_UNLOCK 0x386C 32 #define QLA83XX_DRV_LOCK_ID 0x3504 33 #define QLA83XX_DRV_LOCKRECOVERY 0x379C 34 35 /* IDC version */ 36 #define QLA83XX_IDC_VER_MAJ_VALUE 0x1 37 #define QLA83XX_IDC_VER_MIN_VALUE 0x0 38 39 /* IDC Registers : Driver Coexistence Defines */ 40 #define QLA83XX_CRB_IDC_VER_MAJOR 0x3780 41 #define QLA83XX_CRB_IDC_VER_MINOR 0x3798 42 #define QLA83XX_IDC_DRV_CTRL 0x3790 43 #define QLA83XX_IDC_DRV_AUDIT 0x3794 44 #define QLA83XX_SRE_SHIM_CONTROL 0x0D200284 45 #define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4 46 #define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4 47 #define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388 48 #define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388 49 #define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C 50 #define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C 51 #define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704 52 #define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704 53 54 /* set value to pause threshold value */ 55 #define QLA83XX_SET_PAUSE_VAL 0x0 56 #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF 57 58 /* qla_83xx_reg_tbl registers */ 59 #define QLA83XX_PEG_HALT_STATUS1 0x34A8 60 #define QLA83XX_PEG_HALT_STATUS2 0x34AC 61 #define QLA83XX_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */ 62 #define QLA83XX_FW_CAPABILITIES 0x3528 63 #define QLA83XX_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */ 64 #define QLA83XX_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */ 65 #define QLA83XX_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */ 66 #define QLA83XX_CRB_DRV_SCRATCH 0x3548 67 #define QLA83XX_CRB_DEV_PART_INFO1 0x37E0 68 #define QLA83XX_CRB_DEV_PART_INFO2 0x37E4 69 70 #define QLA83XX_FW_VER_MAJOR 0x3550 71 #define QLA83XX_FW_VER_MINOR 0x3554 72 #define QLA83XX_FW_VER_SUB 0x3558 73 #define QLA83XX_NPAR_STATE 0x359C 74 #define QLA83XX_FW_IMAGE_VALID 0x35FC 75 #define QLA83XX_CMDPEG_STATE 0x3650 76 #define QLA83XX_ASIC_TEMP 0x37B4 77 #define QLA83XX_FW_API 0x356C 78 #define QLA83XX_DRV_OP_MODE 0x3570 79 80 static const uint32_t qla4_83xx_reg_tbl[] = { 81 QLA83XX_PEG_HALT_STATUS1, 82 QLA83XX_PEG_HALT_STATUS2, 83 QLA83XX_PEG_ALIVE_COUNTER, 84 QLA83XX_CRB_DRV_ACTIVE, 85 QLA83XX_CRB_DEV_STATE, 86 QLA83XX_CRB_DRV_STATE, 87 QLA83XX_CRB_DRV_SCRATCH, 88 QLA83XX_CRB_DEV_PART_INFO1, 89 QLA83XX_CRB_IDC_VER_MAJOR, 90 QLA83XX_FW_VER_MAJOR, 91 QLA83XX_FW_VER_MINOR, 92 QLA83XX_FW_VER_SUB, 93 QLA83XX_CMDPEG_STATE, 94 QLA83XX_ASIC_TEMP, 95 }; 96 97 #define QLA83XX_CRB_WIN_BASE 0x3800 98 #define QLA83XX_CRB_WIN_FUNC(f) (QLA83XX_CRB_WIN_BASE+((f)*4)) 99 #define QLA83XX_SEM_LOCK_BASE 0x3840 100 #define QLA83XX_SEM_UNLOCK_BASE 0x3844 101 #define QLA83XX_SEM_LOCK_FUNC(f) (QLA83XX_SEM_LOCK_BASE+((f)*8)) 102 #define QLA83XX_SEM_UNLOCK_FUNC(f) (QLA83XX_SEM_UNLOCK_BASE+((f)*8)) 103 #define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 104 #define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 105 #define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4)) 106 #define QLA83XX_LINK_SPEED_FACTOR 10 107 108 /* FLASH API Defines */ 109 #define QLA83xx_FLASH_MAX_WAIT_USEC 100 110 #define QLA83XX_FLASH_LOCK_TIMEOUT 10000 111 #define QLA83XX_FLASH_SECTOR_SIZE 65536 112 #define QLA83XX_DRV_LOCK_TIMEOUT 2000 113 #define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 114 #define QLA83XX_FLASH_WRITE_CMD 0xdacdacda 115 #define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca 116 #define QLA83XX_FLASH_READ_RETRY_COUNT 2000 117 #define QLA83XX_FLASH_STATUS_READY 0x6 118 #define QLA83XX_FLASH_BUFFER_WRITE_MIN 2 119 #define QLA83XX_FLASH_BUFFER_WRITE_MAX 64 120 #define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1 121 #define QLA83XX_ERASE_MODE 1 122 #define QLA83XX_WRITE_MODE 2 123 #define QLA83XX_DWORD_WRITE_MODE 3 124 125 #define QLA83XX_GLOBAL_RESET 0x38CC 126 #define QLA83XX_WILDCARD 0x38F0 127 #define QLA83XX_INFORMANT 0x38FC 128 #define QLA83XX_HOST_MBX_CTRL 0x3038 129 #define QLA83XX_FW_MBX_CTRL 0x303C 130 #define QLA83XX_BOOTLOADER_ADDR 0x355C 131 #define QLA83XX_BOOTLOADER_SIZE 0x3560 132 #define QLA83XX_FW_IMAGE_ADDR 0x3564 133 #define QLA83XX_MBX_INTR_ENABLE 0x1000 134 #define QLA83XX_MBX_INTR_MASK 0x1200 135 136 /* IDC Control Register bit defines */ 137 #define DONTRESET_BIT0 0x1 138 #define GRACEFUL_RESET_BIT1 0x2 139 140 #define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29) 141 #define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29) 142 #define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29) 143 144 /* Firmware image definitions */ 145 #define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000 146 #define QLA83XX_BOOT_FROM_FLASH 0 147 148 #define QLA83XX_IDC_PARAM_ADDR 0x3e8020 149 /* Reset template definitions */ 150 #define QLA83XX_MAX_RESET_SEQ_ENTRIES 16 151 #define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000 152 #define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000 153 #define QLA83XX_RESET_SEQ_VERSION 0x0101 154 155 /* Reset template entry opcodes */ 156 #define OPCODE_NOP 0x0000 157 #define OPCODE_WRITE_LIST 0x0001 158 #define OPCODE_READ_WRITE_LIST 0x0002 159 #define OPCODE_POLL_LIST 0x0004 160 #define OPCODE_POLL_WRITE_LIST 0x0008 161 #define OPCODE_READ_MODIFY_WRITE 0x0010 162 #define OPCODE_SEQ_PAUSE 0x0020 163 #define OPCODE_SEQ_END 0x0040 164 #define OPCODE_TMPL_END 0x0080 165 #define OPCODE_POLL_READ_LIST 0x0100 166 167 /* Template Header */ 168 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE 169 struct qla4_83xx_reset_template_hdr { 170 __le16 version; 171 __le16 signature; 172 __le16 size; 173 __le16 entries; 174 __le16 hdr_size; 175 __le16 checksum; 176 __le16 init_seq_offset; 177 __le16 start_seq_offset; 178 } __packed; 179 180 /* Common Entry Header. */ 181 struct qla4_83xx_reset_entry_hdr { 182 __le16 cmd; 183 __le16 size; 184 __le16 count; 185 __le16 delay; 186 } __packed; 187 188 /* Generic poll entry type. */ 189 struct qla4_83xx_poll { 190 __le32 test_mask; 191 __le32 test_value; 192 } __packed; 193 194 /* Read modify write entry type. */ 195 struct qla4_83xx_rmw { 196 __le32 test_mask; 197 __le32 xor_value; 198 __le32 or_value; 199 uint8_t shl; 200 uint8_t shr; 201 uint8_t index_a; 202 uint8_t rsvd; 203 } __packed; 204 205 /* Generic Entry Item with 2 DWords. */ 206 struct qla4_83xx_entry { 207 __le32 arg1; 208 __le32 arg2; 209 } __packed; 210 211 /* Generic Entry Item with 4 DWords.*/ 212 struct qla4_83xx_quad_entry { 213 __le32 dr_addr; 214 __le32 dr_value; 215 __le32 ar_addr; 216 __le32 ar_value; 217 } __packed; 218 219 struct qla4_83xx_reset_template { 220 int seq_index; 221 int seq_error; 222 int array_index; 223 uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES]; 224 uint8_t *buff; 225 uint8_t *stop_offset; 226 uint8_t *start_offset; 227 uint8_t *init_offset; 228 struct qla4_83xx_reset_template_hdr *hdr; 229 uint8_t seq_end; 230 uint8_t template_end; 231 }; 232 233 /* POLLRD Entry */ 234 struct qla83xx_minidump_entry_pollrd { 235 struct qla8xxx_minidump_entry_hdr h; 236 uint32_t select_addr; 237 uint32_t read_addr; 238 uint32_t select_value; 239 uint16_t select_value_stride; 240 uint16_t op_count; 241 uint32_t poll_wait; 242 uint32_t poll_mask; 243 uint32_t data_size; 244 uint32_t rsvd_1; 245 }; 246 247 /* RDMUX2 Entry */ 248 struct qla83xx_minidump_entry_rdmux2 { 249 struct qla8xxx_minidump_entry_hdr h; 250 uint32_t select_addr_1; 251 uint32_t select_addr_2; 252 uint32_t select_value_1; 253 uint32_t select_value_2; 254 uint32_t op_count; 255 uint32_t select_value_mask; 256 uint32_t read_addr; 257 uint8_t select_value_stride; 258 uint8_t data_size; 259 uint8_t rsvd[2]; 260 }; 261 262 /* POLLRDMWR Entry */ 263 struct qla83xx_minidump_entry_pollrdmwr { 264 struct qla8xxx_minidump_entry_hdr h; 265 uint32_t addr_1; 266 uint32_t addr_2; 267 uint32_t value_1; 268 uint32_t value_2; 269 uint32_t poll_wait; 270 uint32_t poll_mask; 271 uint32_t modify_mask; 272 uint32_t data_size; 273 }; 274 275 /* IDC additional information */ 276 struct qla4_83xx_idc_information { 277 uint32_t request_desc; /* IDC request descriptor */ 278 uint32_t info1; /* IDC additional info */ 279 uint32_t info2; /* IDC additional info */ 280 uint32_t info3; /* IDC additional info */ 281 }; 282 283 #endif 284