1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <linux/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = RD_REG_WORD(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = RD_REG_WORD(®->nvram); 33 } 34 35 /* Lock resource */ 36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 37 RD_REG_WORD(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 44 RD_REG_WORD(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 62 RD_REG_WORD(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 RD_REG_WORD(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 RD_REG_WORD(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 RD_REG_WORD(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 124 RD_REG_WORD(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = RD_REG_WORD(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 WRT_REG_WORD(®->nvram, NVR_SELECT); 131 RD_REG_WORD(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 WRT_REG_WORD(®->nvram, NVR_DESELECT); 137 RD_REG_WORD(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 WRT_REG_WORD(®->nvram, NVR_DESELECT); 175 RD_REG_WORD(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 193 194 qla2x00_nv_write(ha, NVR_DATA_OUT); 195 qla2x00_nv_write(ha, 0); 196 qla2x00_nv_write(ha, 0); 197 198 for (word = 0; word < 8; word++) 199 qla2x00_nv_write(ha, NVR_DATA_OUT); 200 201 qla2x00_nv_deselect(ha); 202 203 /* Write data */ 204 nv_cmd = (addr << 16) | NV_WRITE_OP; 205 nv_cmd |= data; 206 nv_cmd <<= 5; 207 for (count = 0; count < 27; count++) { 208 if (nv_cmd & BIT_31) 209 qla2x00_nv_write(ha, NVR_DATA_OUT); 210 else 211 qla2x00_nv_write(ha, 0); 212 213 nv_cmd <<= 1; 214 } 215 216 qla2x00_nv_deselect(ha); 217 218 /* Wait for NVRAM to become ready */ 219 WRT_REG_WORD(®->nvram, NVR_SELECT); 220 RD_REG_WORD(®->nvram); /* PCI Posting. */ 221 wait_cnt = NVR_WAIT_CNT; 222 do { 223 if (!--wait_cnt) { 224 ql_dbg(ql_dbg_user, vha, 0x708d, 225 "NVRAM didn't go ready...\n"); 226 break; 227 } 228 NVRAM_DELAY(); 229 word = RD_REG_WORD(®->nvram); 230 } while ((word & NVR_DATA_IN) == 0); 231 232 qla2x00_nv_deselect(ha); 233 234 /* Disable writes */ 235 qla2x00_nv_write(ha, NVR_DATA_OUT); 236 for (count = 0; count < 10; count++) 237 qla2x00_nv_write(ha, 0); 238 239 qla2x00_nv_deselect(ha); 240 } 241 242 static int 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 244 uint16_t data, uint32_t tmo) 245 { 246 int ret, count; 247 uint16_t word; 248 uint32_t nv_cmd; 249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 250 251 ret = QLA_SUCCESS; 252 253 qla2x00_nv_write(ha, NVR_DATA_OUT); 254 qla2x00_nv_write(ha, 0); 255 qla2x00_nv_write(ha, 0); 256 257 for (word = 0; word < 8; word++) 258 qla2x00_nv_write(ha, NVR_DATA_OUT); 259 260 qla2x00_nv_deselect(ha); 261 262 /* Write data */ 263 nv_cmd = (addr << 16) | NV_WRITE_OP; 264 nv_cmd |= data; 265 nv_cmd <<= 5; 266 for (count = 0; count < 27; count++) { 267 if (nv_cmd & BIT_31) 268 qla2x00_nv_write(ha, NVR_DATA_OUT); 269 else 270 qla2x00_nv_write(ha, 0); 271 272 nv_cmd <<= 1; 273 } 274 275 qla2x00_nv_deselect(ha); 276 277 /* Wait for NVRAM to become ready */ 278 WRT_REG_WORD(®->nvram, NVR_SELECT); 279 RD_REG_WORD(®->nvram); /* PCI Posting. */ 280 do { 281 NVRAM_DELAY(); 282 word = RD_REG_WORD(®->nvram); 283 if (!--tmo) { 284 ret = QLA_FUNCTION_FAILED; 285 break; 286 } 287 } while ((word & NVR_DATA_IN) == 0); 288 289 qla2x00_nv_deselect(ha); 290 291 /* Disable writes */ 292 qla2x00_nv_write(ha, NVR_DATA_OUT); 293 for (count = 0; count < 10; count++) 294 qla2x00_nv_write(ha, 0); 295 296 qla2x00_nv_deselect(ha); 297 298 return ret; 299 } 300 301 /** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305 static int 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 307 { 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 uint16_t wprot, wprot_old; 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 313 314 /* Clear NVRAM write protection. */ 315 ret = QLA_FUNCTION_FAILED; 316 317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 319 cpu_to_le16(0x1234), 100000); 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 321 if (stat != QLA_SUCCESS || wprot != 0x1234) { 322 /* Write enable. */ 323 qla2x00_nv_write(ha, NVR_DATA_OUT); 324 qla2x00_nv_write(ha, 0); 325 qla2x00_nv_write(ha, 0); 326 for (word = 0; word < 8; word++) 327 qla2x00_nv_write(ha, NVR_DATA_OUT); 328 329 qla2x00_nv_deselect(ha); 330 331 /* Enable protection register. */ 332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 qla2x00_nv_write(ha, NVR_PR_ENABLE); 335 for (word = 0; word < 8; word++) 336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 337 338 qla2x00_nv_deselect(ha); 339 340 /* Clear protection register (ffff is cleared). */ 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 344 for (word = 0; word < 8; word++) 345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 346 347 qla2x00_nv_deselect(ha); 348 349 /* Wait for NVRAM to become ready. */ 350 WRT_REG_WORD(®->nvram, NVR_SELECT); 351 RD_REG_WORD(®->nvram); /* PCI Posting. */ 352 wait_cnt = NVR_WAIT_CNT; 353 do { 354 if (!--wait_cnt) { 355 ql_dbg(ql_dbg_user, vha, 0x708e, 356 "NVRAM didn't go ready...\n"); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = RD_REG_WORD(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369 } 370 371 static void 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 373 { 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 377 378 if (stat != QLA_SUCCESS) 379 return; 380 381 /* Set NVRAM write protection. */ 382 /* Write enable. */ 383 qla2x00_nv_write(ha, NVR_DATA_OUT); 384 qla2x00_nv_write(ha, 0); 385 qla2x00_nv_write(ha, 0); 386 for (word = 0; word < 8; word++) 387 qla2x00_nv_write(ha, NVR_DATA_OUT); 388 389 qla2x00_nv_deselect(ha); 390 391 /* Enable protection register. */ 392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 qla2x00_nv_write(ha, NVR_PR_ENABLE); 395 for (word = 0; word < 8; word++) 396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 397 398 qla2x00_nv_deselect(ha); 399 400 /* Enable protection register. */ 401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 404 for (word = 0; word < 8; word++) 405 qla2x00_nv_write(ha, NVR_PR_ENABLE); 406 407 qla2x00_nv_deselect(ha); 408 409 /* Wait for NVRAM to become ready. */ 410 WRT_REG_WORD(®->nvram, NVR_SELECT); 411 RD_REG_WORD(®->nvram); /* PCI Posting. */ 412 wait_cnt = NVR_WAIT_CNT; 413 do { 414 if (!--wait_cnt) { 415 ql_dbg(ql_dbg_user, vha, 0x708f, 416 "NVRAM didn't go ready...\n"); 417 break; 418 } 419 NVRAM_DELAY(); 420 word = RD_REG_WORD(®->nvram); 421 } while ((word & NVR_DATA_IN) == 0); 422 } 423 424 425 /*****************************************************************************/ 426 /* Flash Manipulation Routines */ 427 /*****************************************************************************/ 428 429 static inline uint32_t 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 431 { 432 return ha->flash_conf_off | faddr; 433 } 434 435 static inline uint32_t 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 437 { 438 return ha->flash_data_off | faddr; 439 } 440 441 static inline uint32_t 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 443 { 444 return ha->nvram_conf_off | naddr; 445 } 446 447 static inline uint32_t 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 449 { 450 return ha->nvram_data_off | naddr; 451 } 452 453 static uint32_t 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr) 455 { 456 int rval; 457 uint32_t cnt, data; 458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 459 460 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 461 /* Wait for READ cycle to complete. */ 462 rval = QLA_SUCCESS; 463 for (cnt = 3000; 464 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 465 rval == QLA_SUCCESS; cnt--) { 466 if (cnt) 467 udelay(10); 468 else 469 rval = QLA_FUNCTION_TIMEOUT; 470 cond_resched(); 471 } 472 473 /* TODO: What happens if we time out? */ 474 data = 0xDEADDEAD; 475 if (rval == QLA_SUCCESS) 476 data = RD_REG_DWORD(®->flash_data); 477 478 return data; 479 } 480 481 uint32_t * 482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 483 uint32_t dwords) 484 { 485 uint32_t i; 486 struct qla_hw_data *ha = vha->hw; 487 488 /* Dword reads to flash. */ 489 for (i = 0; i < dwords; i++, faddr++) 490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 491 flash_data_addr(ha, faddr))); 492 493 return dwptr; 494 } 495 496 static int 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 498 { 499 int rval; 500 uint32_t cnt; 501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 502 503 WRT_REG_DWORD(®->flash_data, data); 504 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 505 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 506 /* Wait for Write cycle to complete. */ 507 rval = QLA_SUCCESS; 508 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 509 rval == QLA_SUCCESS; cnt--) { 510 if (cnt) 511 udelay(10); 512 else 513 rval = QLA_FUNCTION_TIMEOUT; 514 cond_resched(); 515 } 516 return rval; 517 } 518 519 static void 520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 521 uint8_t *flash_id) 522 { 523 uint32_t ids; 524 525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab)); 526 *man_id = LSB(ids); 527 *flash_id = MSB(ids); 528 529 /* Check if man_id and flash_id are valid. */ 530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 531 /* Read information using 0x9f opcode 532 * Device ID, Mfg ID would be read in the format: 533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 534 * Example: ATMEL 0x00 01 45 1F 535 * Extract MFG and Dev ID from last two bytes. 536 */ 537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f)); 538 *man_id = LSB(ids); 539 *flash_id = MSB(ids); 540 } 541 } 542 543 static int 544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 545 { 546 const char *loc, *locations[] = { "DEF", "PCI" }; 547 uint32_t pcihdr, pcids; 548 uint32_t *dcode; 549 uint8_t *buf, *bcode, last_image; 550 uint16_t cnt, chksum, *wptr; 551 struct qla_flt_location *fltl; 552 struct qla_hw_data *ha = vha->hw; 553 struct req_que *req = ha->req_q_map[0]; 554 555 /* 556 * FLT-location structure resides after the last PCI region. 557 */ 558 559 /* Begin with sane defaults. */ 560 loc = locations[0]; 561 *start = 0; 562 if (IS_QLA24XX_TYPE(ha)) 563 *start = FA_FLASH_LAYOUT_ADDR_24; 564 else if (IS_QLA25XX(ha)) 565 *start = FA_FLASH_LAYOUT_ADDR; 566 else if (IS_QLA81XX(ha)) 567 *start = FA_FLASH_LAYOUT_ADDR_81; 568 else if (IS_P3P_TYPE(ha)) { 569 *start = FA_FLASH_LAYOUT_ADDR_82; 570 goto end; 571 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 572 *start = FA_FLASH_LAYOUT_ADDR_83; 573 goto end; 574 } else if (IS_QLA28XX(ha)) { 575 *start = FA_FLASH_LAYOUT_ADDR_28; 576 goto end; 577 } 578 /* Begin with first PCI expansion ROM header. */ 579 buf = (uint8_t *)req->ring; 580 dcode = (uint32_t *)req->ring; 581 pcihdr = 0; 582 last_image = 1; 583 do { 584 /* Verify PCI expansion ROM header. */ 585 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 586 bcode = buf + (pcihdr % 4); 587 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 588 goto end; 589 590 /* Locate PCI data structure. */ 591 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 592 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 593 bcode = buf + (pcihdr % 4); 594 595 /* Validate signature of PCI data structure. */ 596 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 597 bcode[0x2] != 'I' || bcode[0x3] != 'R') 598 goto end; 599 600 last_image = bcode[0x15] & BIT_7; 601 602 /* Locate next PCI expansion ROM. */ 603 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 604 } while (!last_image); 605 606 /* Now verify FLT-location structure. */ 607 fltl = (struct qla_flt_location *)req->ring; 608 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 609 sizeof(struct qla_flt_location) >> 2); 610 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || 611 fltl->sig[2] != 'L' || fltl->sig[3] != 'T') 612 goto end; 613 614 wptr = (uint16_t *)req->ring; 615 cnt = sizeof(struct qla_flt_location) >> 1; 616 for (chksum = 0; cnt--; wptr++) 617 chksum += le16_to_cpu(*wptr); 618 if (chksum) { 619 ql_log(ql_log_fatal, vha, 0x0045, 620 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 621 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 622 buf, sizeof(struct qla_flt_location)); 623 return QLA_FUNCTION_FAILED; 624 } 625 626 /* Good data. Use specified location. */ 627 loc = locations[1]; 628 *start = (le16_to_cpu(fltl->start_hi) << 16 | 629 le16_to_cpu(fltl->start_lo)) >> 2; 630 end: 631 ql_dbg(ql_dbg_init, vha, 0x0046, 632 "FLTL[%s] = 0x%x.\n", 633 loc, *start); 634 return QLA_SUCCESS; 635 } 636 637 static void 638 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 639 { 640 const char *loc, *locations[] = { "DEF", "FLT" }; 641 const uint32_t def_fw[] = 642 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 643 const uint32_t def_boot[] = 644 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 645 const uint32_t def_vpd_nvram[] = 646 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 647 const uint32_t def_vpd0[] = 648 { 0, 0, FA_VPD0_ADDR_81 }; 649 const uint32_t def_vpd1[] = 650 { 0, 0, FA_VPD1_ADDR_81 }; 651 const uint32_t def_nvram0[] = 652 { 0, 0, FA_NVRAM0_ADDR_81 }; 653 const uint32_t def_nvram1[] = 654 { 0, 0, FA_NVRAM1_ADDR_81 }; 655 const uint32_t def_fdt[] = 656 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 657 FA_FLASH_DESCR_ADDR_81 }; 658 const uint32_t def_npiv_conf0[] = 659 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 660 FA_NPIV_CONF0_ADDR_81 }; 661 const uint32_t def_npiv_conf1[] = 662 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 663 FA_NPIV_CONF1_ADDR_81 }; 664 const uint32_t fcp_prio_cfg0[] = 665 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 666 0 }; 667 const uint32_t fcp_prio_cfg1[] = 668 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 669 0 }; 670 uint32_t def; 671 uint16_t *wptr; 672 uint16_t cnt, chksum; 673 uint32_t start; 674 struct qla_flt_header *flt; 675 struct qla_flt_region *region; 676 struct qla_hw_data *ha = vha->hw; 677 struct req_que *req = ha->req_q_map[0]; 678 679 def = 0; 680 if (IS_QLA25XX(ha)) 681 def = 1; 682 else if (IS_QLA81XX(ha)) 683 def = 2; 684 685 /* Assign FCP prio region since older adapters may not have FLT, or 686 FCP prio region in it's FLT. 687 */ 688 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 689 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 690 691 ha->flt_region_flt = flt_addr; 692 wptr = (uint16_t *)req->ring; 693 flt = (struct qla_flt_header *)req->ring; 694 region = (struct qla_flt_region *)&flt[1]; 695 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 696 flt_addr << 2, OPTROM_BURST_SIZE); 697 if (*wptr == cpu_to_le16(0xffff)) 698 goto no_flash_data; 699 if (flt->version != cpu_to_le16(1)) { 700 ql_log(ql_log_warn, vha, 0x0047, 701 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 702 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 703 le16_to_cpu(flt->checksum)); 704 goto no_flash_data; 705 } 706 707 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 708 for (chksum = 0; cnt--; wptr++) 709 chksum += le16_to_cpu(*wptr); 710 if (chksum) { 711 ql_log(ql_log_fatal, vha, 0x0048, 712 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 713 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 714 le16_to_cpu(flt->checksum)); 715 goto no_flash_data; 716 } 717 718 loc = locations[1]; 719 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 720 for ( ; cnt; cnt--, region++) { 721 /* Store addresses as DWORD offsets. */ 722 start = le32_to_cpu(region->start) >> 2; 723 ql_dbg(ql_dbg_init, vha, 0x0049, 724 "FLT[%02x]: start=0x%x " 725 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff, 726 start, le32_to_cpu(region->end) >> 2, 727 le32_to_cpu(region->size)); 728 729 switch (le32_to_cpu(region->code) & 0xff) { 730 case FLT_REG_FCOE_FW: 731 if (!IS_QLA8031(ha)) 732 break; 733 ha->flt_region_fw = start; 734 break; 735 case FLT_REG_FW: 736 if (IS_QLA8031(ha)) 737 break; 738 ha->flt_region_fw = start; 739 break; 740 case FLT_REG_BOOT_CODE: 741 ha->flt_region_boot = start; 742 break; 743 case FLT_REG_VPD_0: 744 if (IS_QLA8031(ha)) 745 break; 746 ha->flt_region_vpd_nvram = start; 747 if (IS_P3P_TYPE(ha)) 748 break; 749 if (ha->port_no == 0) 750 ha->flt_region_vpd = start; 751 break; 752 case FLT_REG_VPD_1: 753 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 754 break; 755 if (ha->port_no == 1) 756 ha->flt_region_vpd = start; 757 break; 758 case FLT_REG_VPD_2: 759 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 760 break; 761 if (ha->port_no == 2) 762 ha->flt_region_vpd = start; 763 break; 764 case FLT_REG_VPD_3: 765 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 766 break; 767 if (ha->port_no == 3) 768 ha->flt_region_vpd = start; 769 break; 770 case FLT_REG_NVRAM_0: 771 if (IS_QLA8031(ha)) 772 break; 773 if (ha->port_no == 0) 774 ha->flt_region_nvram = start; 775 break; 776 case FLT_REG_NVRAM_1: 777 if (IS_QLA8031(ha)) 778 break; 779 if (ha->port_no == 1) 780 ha->flt_region_nvram = start; 781 break; 782 case FLT_REG_NVRAM_2: 783 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 784 break; 785 if (ha->port_no == 2) 786 ha->flt_region_nvram = start; 787 break; 788 case FLT_REG_NVRAM_3: 789 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 790 break; 791 if (ha->port_no == 3) 792 ha->flt_region_nvram = start; 793 break; 794 case FLT_REG_FDT: 795 ha->flt_region_fdt = start; 796 break; 797 case FLT_REG_NPIV_CONF_0: 798 if (ha->port_no == 0) 799 ha->flt_region_npiv_conf = start; 800 break; 801 case FLT_REG_NPIV_CONF_1: 802 if (ha->port_no == 1) 803 ha->flt_region_npiv_conf = start; 804 break; 805 case FLT_REG_GOLD_FW: 806 ha->flt_region_gold_fw = start; 807 break; 808 case FLT_REG_FCP_PRIO_0: 809 if (ha->port_no == 0) 810 ha->flt_region_fcp_prio = start; 811 break; 812 case FLT_REG_FCP_PRIO_1: 813 if (ha->port_no == 1) 814 ha->flt_region_fcp_prio = start; 815 break; 816 case FLT_REG_BOOT_CODE_82XX: 817 ha->flt_region_boot = start; 818 break; 819 case FLT_REG_BOOT_CODE_8044: 820 if (IS_QLA8044(ha)) 821 ha->flt_region_boot = start; 822 break; 823 case FLT_REG_FW_82XX: 824 ha->flt_region_fw = start; 825 break; 826 case FLT_REG_CNA_FW: 827 if (IS_CNA_CAPABLE(ha)) 828 ha->flt_region_fw = start; 829 break; 830 case FLT_REG_GOLD_FW_82XX: 831 ha->flt_region_gold_fw = start; 832 break; 833 case FLT_REG_BOOTLOAD_82XX: 834 ha->flt_region_bootload = start; 835 break; 836 case FLT_REG_VPD_8XXX: 837 if (IS_CNA_CAPABLE(ha)) 838 ha->flt_region_vpd = start; 839 break; 840 case FLT_REG_FCOE_NVRAM_0: 841 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 842 break; 843 if (ha->port_no == 0) 844 ha->flt_region_nvram = start; 845 break; 846 case FLT_REG_FCOE_NVRAM_1: 847 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 848 break; 849 if (ha->port_no == 1) 850 ha->flt_region_nvram = start; 851 break; 852 case FLT_REG_IMG_PRI_27XX: 853 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 854 ha->flt_region_img_status_pri = start; 855 break; 856 case FLT_REG_IMG_SEC_27XX: 857 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 858 ha->flt_region_img_status_sec = start; 859 break; 860 case FLT_REG_FW_SEC_27XX: 861 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 862 ha->flt_region_fw_sec = start; 863 break; 864 case FLT_REG_BOOTLOAD_SEC_27XX: 865 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 866 ha->flt_region_boot_sec = start; 867 break; 868 case FLT_REG_VPD_SEC_27XX_0: 869 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 870 ha->flt_region_vpd_sec = start; 871 break; 872 case FLT_REG_VPD_SEC_27XX_1: 873 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 874 ha->flt_region_vpd_sec = start; 875 break; 876 case FLT_REG_VPD_SEC_27XX_2: 877 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 878 ha->flt_region_vpd_sec = start; 879 break; 880 case FLT_REG_VPD_SEC_27XX_3: 881 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 882 ha->flt_region_vpd_sec = start; 883 break; 884 } 885 } 886 goto done; 887 888 no_flash_data: 889 /* Use hardcoded defaults. */ 890 loc = locations[0]; 891 ha->flt_region_fw = def_fw[def]; 892 ha->flt_region_boot = def_boot[def]; 893 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 894 ha->flt_region_vpd = (ha->port_no == 0) ? 895 def_vpd0[def] : def_vpd1[def]; 896 ha->flt_region_nvram = (ha->port_no == 0) ? 897 def_nvram0[def] : def_nvram1[def]; 898 ha->flt_region_fdt = def_fdt[def]; 899 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 900 def_npiv_conf0[def] : def_npiv_conf1[def]; 901 done: 902 ql_dbg(ql_dbg_init, vha, 0x004a, 903 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 904 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 905 loc, ha->flt_region_boot, ha->flt_region_fw, 906 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 907 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 908 ha->flt_region_fcp_prio); 909 } 910 911 static void 912 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 913 { 914 #define FLASH_BLK_SIZE_4K 0x1000 915 #define FLASH_BLK_SIZE_32K 0x8000 916 #define FLASH_BLK_SIZE_64K 0x10000 917 const char *loc, *locations[] = { "MID", "FDT" }; 918 uint16_t cnt, chksum; 919 uint16_t *wptr; 920 struct qla_fdt_layout *fdt; 921 uint8_t man_id, flash_id; 922 uint16_t mid = 0, fid = 0; 923 struct qla_hw_data *ha = vha->hw; 924 struct req_que *req = ha->req_q_map[0]; 925 926 wptr = (uint16_t *)req->ring; 927 fdt = (struct qla_fdt_layout *)req->ring; 928 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 929 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); 930 if (*wptr == cpu_to_le16(0xffff)) 931 goto no_flash_data; 932 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 933 fdt->sig[3] != 'D') 934 goto no_flash_data; 935 936 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 937 chksum += le16_to_cpu(*wptr); 938 if (chksum) { 939 ql_dbg(ql_dbg_init, vha, 0x004c, 940 "Inconsistent FDT detected:" 941 " checksum=0x%x id=%c version0x%x.\n", chksum, 942 fdt->sig[0], le16_to_cpu(fdt->version)); 943 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 944 (uint8_t *)fdt, sizeof(*fdt)); 945 goto no_flash_data; 946 } 947 948 loc = locations[1]; 949 mid = le16_to_cpu(fdt->man_id); 950 fid = le16_to_cpu(fdt->id); 951 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 952 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 953 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 954 if (IS_QLA8044(ha)) 955 ha->fdt_erase_cmd = fdt->erase_cmd; 956 else 957 ha->fdt_erase_cmd = 958 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 959 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 960 if (fdt->unprotect_sec_cmd) { 961 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 962 fdt->unprotect_sec_cmd); 963 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 964 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd): 965 flash_conf_addr(ha, 0x0336); 966 } 967 goto done; 968 no_flash_data: 969 loc = locations[0]; 970 if (IS_P3P_TYPE(ha)) { 971 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 972 goto done; 973 } 974 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 975 mid = man_id; 976 fid = flash_id; 977 ha->fdt_wrt_disable = 0x9c; 978 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 979 switch (man_id) { 980 case 0xbf: /* STT flash. */ 981 if (flash_id == 0x8e) 982 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 983 else 984 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 985 986 if (flash_id == 0x80) 987 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 988 break; 989 case 0x13: /* ST M25P80. */ 990 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 991 break; 992 case 0x1f: /* Atmel 26DF081A. */ 993 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 994 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 995 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 996 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 997 break; 998 default: 999 /* Default to 64 kb sector size. */ 1000 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1001 break; 1002 } 1003 done: 1004 ql_dbg(ql_dbg_init, vha, 0x004d, 1005 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1006 "pr=%x wrtd=0x%x blk=0x%x.\n", 1007 loc, mid, fid, 1008 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1009 ha->fdt_wrt_disable, ha->fdt_block_size); 1010 1011 } 1012 1013 static void 1014 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1015 { 1016 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1017 uint32_t *wptr; 1018 struct qla_hw_data *ha = vha->hw; 1019 struct req_que *req = ha->req_q_map[0]; 1020 1021 if (!(IS_P3P_TYPE(ha))) 1022 return; 1023 1024 wptr = (uint32_t *)req->ring; 1025 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 1026 QLA82XX_IDC_PARAM_ADDR , 8); 1027 1028 if (*wptr == cpu_to_le32(0xffffffff)) { 1029 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1030 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1031 } else { 1032 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1033 wptr++; 1034 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1035 } 1036 ql_dbg(ql_dbg_init, vha, 0x004e, 1037 "fcoe_dev_init_timeout=%d " 1038 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1039 ha->fcoe_reset_timeout); 1040 return; 1041 } 1042 1043 int 1044 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1045 { 1046 int ret; 1047 uint32_t flt_addr; 1048 struct qla_hw_data *ha = vha->hw; 1049 1050 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1051 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1052 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1053 return QLA_SUCCESS; 1054 1055 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1056 if (ret != QLA_SUCCESS) 1057 return ret; 1058 1059 qla2xxx_get_flt_info(vha, flt_addr); 1060 qla2xxx_get_fdt_info(vha); 1061 qla2xxx_get_idc_param(vha); 1062 1063 return QLA_SUCCESS; 1064 } 1065 1066 void 1067 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1068 { 1069 #define NPIV_CONFIG_SIZE (16*1024) 1070 void *data; 1071 uint16_t *wptr; 1072 uint16_t cnt, chksum; 1073 int i; 1074 struct qla_npiv_header hdr; 1075 struct qla_npiv_entry *entry; 1076 struct qla_hw_data *ha = vha->hw; 1077 1078 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1079 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1080 return; 1081 1082 if (ha->flags.nic_core_reset_hdlr_active) 1083 return; 1084 1085 if (IS_QLA8044(ha)) 1086 return; 1087 1088 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, 1089 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); 1090 if (hdr.version == cpu_to_le16(0xffff)) 1091 return; 1092 if (hdr.version != cpu_to_le16(1)) { 1093 ql_dbg(ql_dbg_user, vha, 0x7090, 1094 "Unsupported NPIV-Config " 1095 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1096 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1097 le16_to_cpu(hdr.checksum)); 1098 return; 1099 } 1100 1101 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1102 if (!data) { 1103 ql_log(ql_log_warn, vha, 0x7091, 1104 "Unable to allocate memory for data.\n"); 1105 return; 1106 } 1107 1108 ha->isp_ops->read_optrom(vha, (uint8_t *)data, 1109 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); 1110 1111 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1112 for (wptr = data, chksum = 0; cnt--; wptr++) 1113 chksum += le16_to_cpu(*wptr); 1114 if (chksum) { 1115 ql_dbg(ql_dbg_user, vha, 0x7092, 1116 "Inconsistent NPIV-Config " 1117 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1118 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1119 le16_to_cpu(hdr.checksum)); 1120 goto done; 1121 } 1122 1123 entry = data + sizeof(struct qla_npiv_header); 1124 cnt = le16_to_cpu(hdr.entries); 1125 for (i = 0; cnt; cnt--, entry++, i++) { 1126 uint16_t flags; 1127 struct fc_vport_identifiers vid; 1128 struct fc_vport *vport; 1129 1130 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1131 1132 flags = le16_to_cpu(entry->flags); 1133 if (flags == 0xffff) 1134 continue; 1135 if ((flags & BIT_0) == 0) 1136 continue; 1137 1138 memset(&vid, 0, sizeof(vid)); 1139 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1140 vid.vport_type = FC_PORTTYPE_NPIV; 1141 vid.disable = false; 1142 vid.port_name = wwn_to_u64(entry->port_name); 1143 vid.node_name = wwn_to_u64(entry->node_name); 1144 1145 ql_dbg(ql_dbg_user, vha, 0x7093, 1146 "NPIV[%02x]: wwpn=%llx " 1147 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt, 1148 (unsigned long long)vid.port_name, 1149 (unsigned long long)vid.node_name, 1150 le16_to_cpu(entry->vf_id), 1151 entry->q_qos, entry->f_qos); 1152 1153 if (i < QLA_PRECONFIG_VPORTS) { 1154 vport = fc_vport_create(vha->host, 0, &vid); 1155 if (!vport) 1156 ql_log(ql_log_warn, vha, 0x7094, 1157 "NPIV-Config Failed to create vport [%02x]: " 1158 "wwpn=%llx wwnn=%llx.\n", cnt, 1159 (unsigned long long)vid.port_name, 1160 (unsigned long long)vid.node_name); 1161 } 1162 } 1163 done: 1164 kfree(data); 1165 } 1166 1167 static int 1168 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1169 { 1170 struct qla_hw_data *ha = vha->hw; 1171 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1172 1173 if (ha->flags.fac_supported) 1174 return qla81xx_fac_do_write_enable(vha, 1); 1175 1176 /* Enable flash write. */ 1177 WRT_REG_DWORD(®->ctrl_status, 1178 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1179 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1180 1181 if (!ha->fdt_wrt_disable) 1182 goto done; 1183 1184 /* Disable flash write-protection, first clear SR protection bit */ 1185 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1186 /* Then write zero again to clear remaining SR bits.*/ 1187 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1188 done: 1189 return QLA_SUCCESS; 1190 } 1191 1192 static int 1193 qla24xx_protect_flash(scsi_qla_host_t *vha) 1194 { 1195 uint32_t cnt; 1196 struct qla_hw_data *ha = vha->hw; 1197 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1198 1199 if (ha->flags.fac_supported) 1200 return qla81xx_fac_do_write_enable(vha, 0); 1201 1202 if (!ha->fdt_wrt_disable) 1203 goto skip_wrt_protect; 1204 1205 /* Enable flash write-protection and wait for completion. */ 1206 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 1207 ha->fdt_wrt_disable); 1208 for (cnt = 300; cnt && 1209 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0; 1210 cnt--) { 1211 udelay(10); 1212 } 1213 1214 skip_wrt_protect: 1215 /* Disable flash write. */ 1216 WRT_REG_DWORD(®->ctrl_status, 1217 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1218 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1219 1220 return QLA_SUCCESS; 1221 } 1222 1223 static int 1224 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1225 { 1226 struct qla_hw_data *ha = vha->hw; 1227 uint32_t start, finish; 1228 1229 if (ha->flags.fac_supported) { 1230 start = fdata >> 2; 1231 finish = start + (ha->fdt_block_size >> 2) - 1; 1232 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1233 start), flash_data_addr(ha, finish)); 1234 } 1235 1236 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1237 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1238 ((fdata >> 16) & 0xff)); 1239 } 1240 1241 static int 1242 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 1243 uint32_t dwords) 1244 { 1245 int ret; 1246 uint32_t liter; 1247 uint32_t sec_mask, rest_addr; 1248 uint32_t fdata; 1249 dma_addr_t optrom_dma; 1250 void *optrom = NULL; 1251 struct qla_hw_data *ha = vha->hw; 1252 1253 /* Prepare burst-capable write on supported ISPs. */ 1254 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 1255 IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 1256 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) { 1257 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1258 &optrom_dma, GFP_KERNEL); 1259 if (!optrom) { 1260 ql_log(ql_log_warn, vha, 0x7095, 1261 "Unable to allocate " 1262 "memory for optrom burst write (%x KB).\n", 1263 OPTROM_BURST_SIZE / 1024); 1264 } 1265 } 1266 1267 rest_addr = (ha->fdt_block_size >> 2) - 1; 1268 sec_mask = ~rest_addr; 1269 1270 ret = qla24xx_unprotect_flash(vha); 1271 if (ret != QLA_SUCCESS) { 1272 ql_log(ql_log_warn, vha, 0x7096, 1273 "Unable to unprotect flash for update.\n"); 1274 goto done; 1275 } 1276 1277 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1278 fdata = (faddr & sec_mask) << 2; 1279 1280 /* Are we at the beginning of a sector? */ 1281 if ((faddr & rest_addr) == 0) { 1282 /* Do sector unprotect. */ 1283 if (ha->fdt_unprotect_sec_cmd) 1284 qla24xx_write_flash_dword(ha, 1285 ha->fdt_unprotect_sec_cmd, 1286 (fdata & 0xff00) | ((fdata << 16) & 1287 0xff0000) | ((fdata >> 16) & 0xff)); 1288 ret = qla24xx_erase_sector(vha, fdata); 1289 if (ret != QLA_SUCCESS) { 1290 ql_dbg(ql_dbg_user, vha, 0x7007, 1291 "Unable to erase erase sector: address=%x.\n", 1292 faddr); 1293 break; 1294 } 1295 } 1296 1297 /* Go with burst-write. */ 1298 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 1299 /* Copy data to DMA'ble buffer. */ 1300 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 1301 1302 ret = qla2x00_load_ram(vha, optrom_dma, 1303 flash_data_addr(ha, faddr), 1304 OPTROM_BURST_DWORDS); 1305 if (ret != QLA_SUCCESS) { 1306 ql_log(ql_log_warn, vha, 0x7097, 1307 "Unable to burst-write optrom segment " 1308 "(%x/%x/%llx).\n", ret, 1309 flash_data_addr(ha, faddr), 1310 (unsigned long long)optrom_dma); 1311 ql_log(ql_log_warn, vha, 0x7098, 1312 "Reverting to slow-write.\n"); 1313 1314 dma_free_coherent(&ha->pdev->dev, 1315 OPTROM_BURST_SIZE, optrom, optrom_dma); 1316 optrom = NULL; 1317 } else { 1318 liter += OPTROM_BURST_DWORDS - 1; 1319 faddr += OPTROM_BURST_DWORDS - 1; 1320 dwptr += OPTROM_BURST_DWORDS - 1; 1321 continue; 1322 } 1323 } 1324 1325 ret = qla24xx_write_flash_dword(ha, 1326 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); 1327 if (ret != QLA_SUCCESS) { 1328 ql_dbg(ql_dbg_user, vha, 0x7006, 1329 "Unable to program flash address=%x data=%x.\n", 1330 faddr, *dwptr); 1331 break; 1332 } 1333 1334 /* Do sector protect. */ 1335 if (ha->fdt_unprotect_sec_cmd && 1336 ((faddr & rest_addr) == rest_addr)) 1337 qla24xx_write_flash_dword(ha, 1338 ha->fdt_protect_sec_cmd, 1339 (fdata & 0xff00) | ((fdata << 16) & 1340 0xff0000) | ((fdata >> 16) & 0xff)); 1341 } 1342 1343 ret = qla24xx_protect_flash(vha); 1344 if (ret != QLA_SUCCESS) 1345 ql_log(ql_log_warn, vha, 0x7099, 1346 "Unable to protect flash after update.\n"); 1347 done: 1348 if (optrom) 1349 dma_free_coherent(&ha->pdev->dev, 1350 OPTROM_BURST_SIZE, optrom, optrom_dma); 1351 1352 return ret; 1353 } 1354 1355 uint8_t * 1356 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1357 uint32_t bytes) 1358 { 1359 uint32_t i; 1360 uint16_t *wptr; 1361 struct qla_hw_data *ha = vha->hw; 1362 1363 /* Word reads to NVRAM via registers. */ 1364 wptr = (uint16_t *)buf; 1365 qla2x00_lock_nvram_access(ha); 1366 for (i = 0; i < bytes >> 1; i++, naddr++) 1367 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1368 naddr)); 1369 qla2x00_unlock_nvram_access(ha); 1370 1371 return buf; 1372 } 1373 1374 uint8_t * 1375 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1376 uint32_t bytes) 1377 { 1378 uint32_t i; 1379 uint32_t *dwptr; 1380 struct qla_hw_data *ha = vha->hw; 1381 1382 if (IS_P3P_TYPE(ha)) 1383 return buf; 1384 1385 /* Dword reads to flash. */ 1386 dwptr = (uint32_t *)buf; 1387 for (i = 0; i < bytes >> 2; i++, naddr++) 1388 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1389 nvram_data_addr(ha, naddr))); 1390 1391 return buf; 1392 } 1393 1394 int 1395 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1396 uint32_t bytes) 1397 { 1398 int ret, stat; 1399 uint32_t i; 1400 uint16_t *wptr; 1401 unsigned long flags; 1402 struct qla_hw_data *ha = vha->hw; 1403 1404 ret = QLA_SUCCESS; 1405 1406 spin_lock_irqsave(&ha->hardware_lock, flags); 1407 qla2x00_lock_nvram_access(ha); 1408 1409 /* Disable NVRAM write-protection. */ 1410 stat = qla2x00_clear_nvram_protection(ha); 1411 1412 wptr = (uint16_t *)buf; 1413 for (i = 0; i < bytes >> 1; i++, naddr++) { 1414 qla2x00_write_nvram_word(ha, naddr, 1415 cpu_to_le16(*wptr)); 1416 wptr++; 1417 } 1418 1419 /* Enable NVRAM write-protection. */ 1420 qla2x00_set_nvram_protection(ha, stat); 1421 1422 qla2x00_unlock_nvram_access(ha); 1423 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1424 1425 return ret; 1426 } 1427 1428 int 1429 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1430 uint32_t bytes) 1431 { 1432 int ret; 1433 uint32_t i; 1434 uint32_t *dwptr; 1435 struct qla_hw_data *ha = vha->hw; 1436 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1437 1438 ret = QLA_SUCCESS; 1439 1440 if (IS_P3P_TYPE(ha)) 1441 return ret; 1442 1443 /* Enable flash write. */ 1444 WRT_REG_DWORD(®->ctrl_status, 1445 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1446 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1447 1448 /* Disable NVRAM write-protection. */ 1449 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1450 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1451 1452 /* Dword writes to flash. */ 1453 dwptr = (uint32_t *)buf; 1454 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 1455 ret = qla24xx_write_flash_dword(ha, 1456 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr)); 1457 if (ret != QLA_SUCCESS) { 1458 ql_dbg(ql_dbg_user, vha, 0x709a, 1459 "Unable to program nvram address=%x data=%x.\n", 1460 naddr, *dwptr); 1461 break; 1462 } 1463 } 1464 1465 /* Enable NVRAM write-protection. */ 1466 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1467 1468 /* Disable flash write. */ 1469 WRT_REG_DWORD(®->ctrl_status, 1470 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1471 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1472 1473 return ret; 1474 } 1475 1476 uint8_t * 1477 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1478 uint32_t bytes) 1479 { 1480 uint32_t i; 1481 uint32_t *dwptr; 1482 struct qla_hw_data *ha = vha->hw; 1483 1484 /* Dword reads to flash. */ 1485 dwptr = (uint32_t *)buf; 1486 for (i = 0; i < bytes >> 2; i++, naddr++) 1487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1488 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr))); 1489 1490 return buf; 1491 } 1492 1493 int 1494 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1495 uint32_t bytes) 1496 { 1497 struct qla_hw_data *ha = vha->hw; 1498 #define RMW_BUFFER_SIZE (64 * 1024) 1499 uint8_t *dbuf; 1500 1501 dbuf = vmalloc(RMW_BUFFER_SIZE); 1502 if (!dbuf) 1503 return QLA_MEMORY_ALLOC_FAILED; 1504 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1505 RMW_BUFFER_SIZE); 1506 memcpy(dbuf + (naddr << 2), buf, bytes); 1507 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1508 RMW_BUFFER_SIZE); 1509 vfree(dbuf); 1510 1511 return QLA_SUCCESS; 1512 } 1513 1514 static inline void 1515 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1516 { 1517 if (IS_QLA2322(ha)) { 1518 /* Flip all colors. */ 1519 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1520 /* Turn off. */ 1521 ha->beacon_color_state = 0; 1522 *pflags = GPIO_LED_ALL_OFF; 1523 } else { 1524 /* Turn on. */ 1525 ha->beacon_color_state = QLA_LED_ALL_ON; 1526 *pflags = GPIO_LED_RGA_ON; 1527 } 1528 } else { 1529 /* Flip green led only. */ 1530 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1531 /* Turn off. */ 1532 ha->beacon_color_state = 0; 1533 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1534 } else { 1535 /* Turn on. */ 1536 ha->beacon_color_state = QLA_LED_GRN_ON; 1537 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1538 } 1539 } 1540 } 1541 1542 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1543 1544 void 1545 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1546 { 1547 uint16_t gpio_enable; 1548 uint16_t gpio_data; 1549 uint16_t led_color = 0; 1550 unsigned long flags; 1551 struct qla_hw_data *ha = vha->hw; 1552 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1553 1554 if (IS_P3P_TYPE(ha)) 1555 return; 1556 1557 spin_lock_irqsave(&ha->hardware_lock, flags); 1558 1559 /* Save the Original GPIOE. */ 1560 if (ha->pio_address) { 1561 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1562 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1563 } else { 1564 gpio_enable = RD_REG_WORD(®->gpioe); 1565 gpio_data = RD_REG_WORD(®->gpiod); 1566 } 1567 1568 /* Set the modified gpio_enable values */ 1569 gpio_enable |= GPIO_LED_MASK; 1570 1571 if (ha->pio_address) { 1572 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1573 } else { 1574 WRT_REG_WORD(®->gpioe, gpio_enable); 1575 RD_REG_WORD(®->gpioe); 1576 } 1577 1578 qla2x00_flip_colors(ha, &led_color); 1579 1580 /* Clear out any previously set LED color. */ 1581 gpio_data &= ~GPIO_LED_MASK; 1582 1583 /* Set the new input LED color to GPIOD. */ 1584 gpio_data |= led_color; 1585 1586 /* Set the modified gpio_data values */ 1587 if (ha->pio_address) { 1588 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1589 } else { 1590 WRT_REG_WORD(®->gpiod, gpio_data); 1591 RD_REG_WORD(®->gpiod); 1592 } 1593 1594 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1595 } 1596 1597 int 1598 qla2x00_beacon_on(struct scsi_qla_host *vha) 1599 { 1600 uint16_t gpio_enable; 1601 uint16_t gpio_data; 1602 unsigned long flags; 1603 struct qla_hw_data *ha = vha->hw; 1604 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1605 1606 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1607 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1608 1609 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1610 ql_log(ql_log_warn, vha, 0x709b, 1611 "Unable to update fw options (beacon on).\n"); 1612 return QLA_FUNCTION_FAILED; 1613 } 1614 1615 /* Turn off LEDs. */ 1616 spin_lock_irqsave(&ha->hardware_lock, flags); 1617 if (ha->pio_address) { 1618 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1619 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1620 } else { 1621 gpio_enable = RD_REG_WORD(®->gpioe); 1622 gpio_data = RD_REG_WORD(®->gpiod); 1623 } 1624 gpio_enable |= GPIO_LED_MASK; 1625 1626 /* Set the modified gpio_enable values. */ 1627 if (ha->pio_address) { 1628 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1629 } else { 1630 WRT_REG_WORD(®->gpioe, gpio_enable); 1631 RD_REG_WORD(®->gpioe); 1632 } 1633 1634 /* Clear out previously set LED colour. */ 1635 gpio_data &= ~GPIO_LED_MASK; 1636 if (ha->pio_address) { 1637 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1638 } else { 1639 WRT_REG_WORD(®->gpiod, gpio_data); 1640 RD_REG_WORD(®->gpiod); 1641 } 1642 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1643 1644 /* 1645 * Let the per HBA timer kick off the blinking process based on 1646 * the following flags. No need to do anything else now. 1647 */ 1648 ha->beacon_blink_led = 1; 1649 ha->beacon_color_state = 0; 1650 1651 return QLA_SUCCESS; 1652 } 1653 1654 int 1655 qla2x00_beacon_off(struct scsi_qla_host *vha) 1656 { 1657 int rval = QLA_SUCCESS; 1658 struct qla_hw_data *ha = vha->hw; 1659 1660 ha->beacon_blink_led = 0; 1661 1662 /* Set the on flag so when it gets flipped it will be off. */ 1663 if (IS_QLA2322(ha)) 1664 ha->beacon_color_state = QLA_LED_ALL_ON; 1665 else 1666 ha->beacon_color_state = QLA_LED_GRN_ON; 1667 1668 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1669 1670 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1671 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1672 1673 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1674 if (rval != QLA_SUCCESS) 1675 ql_log(ql_log_warn, vha, 0x709c, 1676 "Unable to update fw options (beacon off).\n"); 1677 return rval; 1678 } 1679 1680 1681 static inline void 1682 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1683 { 1684 /* Flip all colors. */ 1685 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1686 /* Turn off. */ 1687 ha->beacon_color_state = 0; 1688 *pflags = 0; 1689 } else { 1690 /* Turn on. */ 1691 ha->beacon_color_state = QLA_LED_ALL_ON; 1692 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1693 } 1694 } 1695 1696 void 1697 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1698 { 1699 uint16_t led_color = 0; 1700 uint32_t gpio_data; 1701 unsigned long flags; 1702 struct qla_hw_data *ha = vha->hw; 1703 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1704 1705 /* Save the Original GPIOD. */ 1706 spin_lock_irqsave(&ha->hardware_lock, flags); 1707 gpio_data = RD_REG_DWORD(®->gpiod); 1708 1709 /* Enable the gpio_data reg for update. */ 1710 gpio_data |= GPDX_LED_UPDATE_MASK; 1711 1712 WRT_REG_DWORD(®->gpiod, gpio_data); 1713 gpio_data = RD_REG_DWORD(®->gpiod); 1714 1715 /* Set the color bits. */ 1716 qla24xx_flip_colors(ha, &led_color); 1717 1718 /* Clear out any previously set LED color. */ 1719 gpio_data &= ~GPDX_LED_COLOR_MASK; 1720 1721 /* Set the new input LED color to GPIOD. */ 1722 gpio_data |= led_color; 1723 1724 /* Set the modified gpio_data values. */ 1725 WRT_REG_DWORD(®->gpiod, gpio_data); 1726 gpio_data = RD_REG_DWORD(®->gpiod); 1727 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1728 } 1729 1730 static uint32_t 1731 qla83xx_select_led_port(struct qla_hw_data *ha) 1732 { 1733 uint32_t led_select_value = 0; 1734 1735 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1736 goto out; 1737 1738 if (ha->port_no == 0) 1739 led_select_value = QLA83XX_LED_PORT0; 1740 else 1741 led_select_value = QLA83XX_LED_PORT1; 1742 1743 out: 1744 return led_select_value; 1745 } 1746 1747 void 1748 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1749 { 1750 uint32_t led_select_value; 1751 struct qla_hw_data *ha = vha->hw; 1752 uint16_t led_cfg[6]; 1753 uint16_t orig_led_cfg[6]; 1754 uint32_t led_10_value, led_43_value; 1755 1756 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1757 !IS_QLA28XX(ha)) 1758 return; 1759 1760 if (!ha->beacon_blink_led) 1761 return; 1762 1763 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1764 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1765 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1766 } else if (IS_QLA2031(ha)) { 1767 led_select_value = qla83xx_select_led_port(ha); 1768 1769 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1770 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1771 } else if (IS_QLA8031(ha)) { 1772 led_select_value = qla83xx_select_led_port(ha); 1773 1774 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1775 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1776 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1777 msleep(500); 1778 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1779 msleep(1000); 1780 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1781 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1782 } else if (IS_QLA81XX(ha)) { 1783 int rval; 1784 1785 /* Save Current */ 1786 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1787 /* Do the blink */ 1788 if (rval == QLA_SUCCESS) { 1789 if (IS_QLA81XX(ha)) { 1790 led_cfg[0] = 0x4000; 1791 led_cfg[1] = 0x2000; 1792 led_cfg[2] = 0; 1793 led_cfg[3] = 0; 1794 led_cfg[4] = 0; 1795 led_cfg[5] = 0; 1796 } else { 1797 led_cfg[0] = 0x4000; 1798 led_cfg[1] = 0x4000; 1799 led_cfg[2] = 0x4000; 1800 led_cfg[3] = 0x2000; 1801 led_cfg[4] = 0; 1802 led_cfg[5] = 0x2000; 1803 } 1804 rval = qla81xx_set_led_config(vha, led_cfg); 1805 msleep(1000); 1806 if (IS_QLA81XX(ha)) { 1807 led_cfg[0] = 0x4000; 1808 led_cfg[1] = 0x2000; 1809 led_cfg[2] = 0; 1810 } else { 1811 led_cfg[0] = 0x4000; 1812 led_cfg[1] = 0x2000; 1813 led_cfg[2] = 0x4000; 1814 led_cfg[3] = 0x4000; 1815 led_cfg[4] = 0; 1816 led_cfg[5] = 0x2000; 1817 } 1818 rval = qla81xx_set_led_config(vha, led_cfg); 1819 } 1820 /* On exit, restore original (presumes no status change) */ 1821 qla81xx_set_led_config(vha, orig_led_cfg); 1822 } 1823 } 1824 1825 int 1826 qla24xx_beacon_on(struct scsi_qla_host *vha) 1827 { 1828 uint32_t gpio_data; 1829 unsigned long flags; 1830 struct qla_hw_data *ha = vha->hw; 1831 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1832 1833 if (IS_P3P_TYPE(ha)) 1834 return QLA_SUCCESS; 1835 1836 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1837 goto skip_gpio; /* let blink handle it */ 1838 1839 if (ha->beacon_blink_led == 0) { 1840 /* Enable firmware for update */ 1841 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1842 1843 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1844 return QLA_FUNCTION_FAILED; 1845 1846 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1847 QLA_SUCCESS) { 1848 ql_log(ql_log_warn, vha, 0x7009, 1849 "Unable to update fw options (beacon on).\n"); 1850 return QLA_FUNCTION_FAILED; 1851 } 1852 1853 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1854 goto skip_gpio; 1855 1856 spin_lock_irqsave(&ha->hardware_lock, flags); 1857 gpio_data = RD_REG_DWORD(®->gpiod); 1858 1859 /* Enable the gpio_data reg for update. */ 1860 gpio_data |= GPDX_LED_UPDATE_MASK; 1861 WRT_REG_DWORD(®->gpiod, gpio_data); 1862 RD_REG_DWORD(®->gpiod); 1863 1864 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1865 } 1866 1867 /* So all colors blink together. */ 1868 ha->beacon_color_state = 0; 1869 1870 skip_gpio: 1871 /* Let the per HBA timer kick off the blinking process. */ 1872 ha->beacon_blink_led = 1; 1873 1874 return QLA_SUCCESS; 1875 } 1876 1877 int 1878 qla24xx_beacon_off(struct scsi_qla_host *vha) 1879 { 1880 uint32_t gpio_data; 1881 unsigned long flags; 1882 struct qla_hw_data *ha = vha->hw; 1883 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1884 1885 if (IS_P3P_TYPE(ha)) 1886 return QLA_SUCCESS; 1887 1888 if (!ha->flags.fw_started) 1889 return QLA_SUCCESS; 1890 1891 ha->beacon_blink_led = 0; 1892 1893 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1894 goto set_fw_options; 1895 1896 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1897 return QLA_SUCCESS; 1898 1899 ha->beacon_color_state = QLA_LED_ALL_ON; 1900 1901 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1902 1903 /* Give control back to firmware. */ 1904 spin_lock_irqsave(&ha->hardware_lock, flags); 1905 gpio_data = RD_REG_DWORD(®->gpiod); 1906 1907 /* Disable the gpio_data reg for update. */ 1908 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1909 WRT_REG_DWORD(®->gpiod, gpio_data); 1910 RD_REG_DWORD(®->gpiod); 1911 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1912 1913 set_fw_options: 1914 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1915 1916 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1917 ql_log(ql_log_warn, vha, 0x704d, 1918 "Unable to update fw options (beacon on).\n"); 1919 return QLA_FUNCTION_FAILED; 1920 } 1921 1922 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1923 ql_log(ql_log_warn, vha, 0x704e, 1924 "Unable to update fw options (beacon on).\n"); 1925 return QLA_FUNCTION_FAILED; 1926 } 1927 1928 return QLA_SUCCESS; 1929 } 1930 1931 1932 /* 1933 * Flash support routines 1934 */ 1935 1936 /** 1937 * qla2x00_flash_enable() - Setup flash for reading and writing. 1938 * @ha: HA context 1939 */ 1940 static void 1941 qla2x00_flash_enable(struct qla_hw_data *ha) 1942 { 1943 uint16_t data; 1944 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1945 1946 data = RD_REG_WORD(®->ctrl_status); 1947 data |= CSR_FLASH_ENABLE; 1948 WRT_REG_WORD(®->ctrl_status, data); 1949 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1950 } 1951 1952 /** 1953 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1954 * @ha: HA context 1955 */ 1956 static void 1957 qla2x00_flash_disable(struct qla_hw_data *ha) 1958 { 1959 uint16_t data; 1960 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1961 1962 data = RD_REG_WORD(®->ctrl_status); 1963 data &= ~(CSR_FLASH_ENABLE); 1964 WRT_REG_WORD(®->ctrl_status, data); 1965 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1966 } 1967 1968 /** 1969 * qla2x00_read_flash_byte() - Reads a byte from flash 1970 * @ha: HA context 1971 * @addr: Address in flash to read 1972 * 1973 * A word is read from the chip, but, only the lower byte is valid. 1974 * 1975 * Returns the byte read from flash @addr. 1976 */ 1977 static uint8_t 1978 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 1979 { 1980 uint16_t data; 1981 uint16_t bank_select; 1982 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1983 1984 bank_select = RD_REG_WORD(®->ctrl_status); 1985 1986 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1987 /* Specify 64K address range: */ 1988 /* clear out Module Select and Flash Address bits [19:16]. */ 1989 bank_select &= ~0xf8; 1990 bank_select |= addr >> 12 & 0xf0; 1991 bank_select |= CSR_FLASH_64K_BANK; 1992 WRT_REG_WORD(®->ctrl_status, bank_select); 1993 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1994 1995 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1996 data = RD_REG_WORD(®->flash_data); 1997 1998 return (uint8_t)data; 1999 } 2000 2001 /* Setup bit 16 of flash address. */ 2002 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2003 bank_select |= CSR_FLASH_64K_BANK; 2004 WRT_REG_WORD(®->ctrl_status, bank_select); 2005 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2006 } else if (((addr & BIT_16) == 0) && 2007 (bank_select & CSR_FLASH_64K_BANK)) { 2008 bank_select &= ~(CSR_FLASH_64K_BANK); 2009 WRT_REG_WORD(®->ctrl_status, bank_select); 2010 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2011 } 2012 2013 /* Always perform IO mapped accesses to the FLASH registers. */ 2014 if (ha->pio_address) { 2015 uint16_t data2; 2016 2017 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2018 do { 2019 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2020 barrier(); 2021 cpu_relax(); 2022 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2023 } while (data != data2); 2024 } else { 2025 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2026 data = qla2x00_debounce_register(®->flash_data); 2027 } 2028 2029 return (uint8_t)data; 2030 } 2031 2032 /** 2033 * qla2x00_write_flash_byte() - Write a byte to flash 2034 * @ha: HA context 2035 * @addr: Address in flash to write 2036 * @data: Data to write 2037 */ 2038 static void 2039 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2040 { 2041 uint16_t bank_select; 2042 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2043 2044 bank_select = RD_REG_WORD(®->ctrl_status); 2045 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2046 /* Specify 64K address range: */ 2047 /* clear out Module Select and Flash Address bits [19:16]. */ 2048 bank_select &= ~0xf8; 2049 bank_select |= addr >> 12 & 0xf0; 2050 bank_select |= CSR_FLASH_64K_BANK; 2051 WRT_REG_WORD(®->ctrl_status, bank_select); 2052 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2053 2054 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2055 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2056 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2057 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2058 2059 return; 2060 } 2061 2062 /* Setup bit 16 of flash address. */ 2063 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2064 bank_select |= CSR_FLASH_64K_BANK; 2065 WRT_REG_WORD(®->ctrl_status, bank_select); 2066 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2067 } else if (((addr & BIT_16) == 0) && 2068 (bank_select & CSR_FLASH_64K_BANK)) { 2069 bank_select &= ~(CSR_FLASH_64K_BANK); 2070 WRT_REG_WORD(®->ctrl_status, bank_select); 2071 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2072 } 2073 2074 /* Always perform IO mapped accesses to the FLASH registers. */ 2075 if (ha->pio_address) { 2076 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2077 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2078 } else { 2079 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2080 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2081 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2082 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2083 } 2084 } 2085 2086 /** 2087 * qla2x00_poll_flash() - Polls flash for completion. 2088 * @ha: HA context 2089 * @addr: Address in flash to poll 2090 * @poll_data: Data to be polled 2091 * @man_id: Flash manufacturer ID 2092 * @flash_id: Flash ID 2093 * 2094 * This function polls the device until bit 7 of what is read matches data 2095 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 2096 * out (a fatal error). The flash book recommeds reading bit 7 again after 2097 * reading bit 5 as a 1. 2098 * 2099 * Returns 0 on success, else non-zero. 2100 */ 2101 static int 2102 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2103 uint8_t man_id, uint8_t flash_id) 2104 { 2105 int status; 2106 uint8_t flash_data; 2107 uint32_t cnt; 2108 2109 status = 1; 2110 2111 /* Wait for 30 seconds for command to finish. */ 2112 poll_data &= BIT_7; 2113 for (cnt = 3000000; cnt; cnt--) { 2114 flash_data = qla2x00_read_flash_byte(ha, addr); 2115 if ((flash_data & BIT_7) == poll_data) { 2116 status = 0; 2117 break; 2118 } 2119 2120 if (man_id != 0x40 && man_id != 0xda) { 2121 if ((flash_data & BIT_5) && cnt > 2) 2122 cnt = 2; 2123 } 2124 udelay(10); 2125 barrier(); 2126 cond_resched(); 2127 } 2128 return status; 2129 } 2130 2131 /** 2132 * qla2x00_program_flash_address() - Programs a flash address 2133 * @ha: HA context 2134 * @addr: Address in flash to program 2135 * @data: Data to be written in flash 2136 * @man_id: Flash manufacturer ID 2137 * @flash_id: Flash ID 2138 * 2139 * Returns 0 on success, else non-zero. 2140 */ 2141 static int 2142 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2143 uint8_t data, uint8_t man_id, uint8_t flash_id) 2144 { 2145 /* Write Program Command Sequence. */ 2146 if (IS_OEM_001(ha)) { 2147 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2148 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2149 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2150 qla2x00_write_flash_byte(ha, addr, data); 2151 } else { 2152 if (man_id == 0xda && flash_id == 0xc1) { 2153 qla2x00_write_flash_byte(ha, addr, data); 2154 if (addr & 0x7e) 2155 return 0; 2156 } else { 2157 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2158 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2159 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2160 qla2x00_write_flash_byte(ha, addr, data); 2161 } 2162 } 2163 2164 udelay(150); 2165 2166 /* Wait for write to complete. */ 2167 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2168 } 2169 2170 /** 2171 * qla2x00_erase_flash() - Erase the flash. 2172 * @ha: HA context 2173 * @man_id: Flash manufacturer ID 2174 * @flash_id: Flash ID 2175 * 2176 * Returns 0 on success, else non-zero. 2177 */ 2178 static int 2179 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2180 { 2181 /* Individual Sector Erase Command Sequence */ 2182 if (IS_OEM_001(ha)) { 2183 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2184 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2185 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2186 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2187 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2188 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2189 } else { 2190 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2191 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2192 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2193 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2194 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2195 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2196 } 2197 2198 udelay(150); 2199 2200 /* Wait for erase to complete. */ 2201 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2202 } 2203 2204 /** 2205 * qla2x00_erase_flash_sector() - Erase a flash sector. 2206 * @ha: HA context 2207 * @addr: Flash sector to erase 2208 * @sec_mask: Sector address mask 2209 * @man_id: Flash manufacturer ID 2210 * @flash_id: Flash ID 2211 * 2212 * Returns 0 on success, else non-zero. 2213 */ 2214 static int 2215 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2216 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2217 { 2218 /* Individual Sector Erase Command Sequence */ 2219 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2220 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2221 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2222 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2223 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2224 if (man_id == 0x1f && flash_id == 0x13) 2225 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2226 else 2227 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2228 2229 udelay(150); 2230 2231 /* Wait for erase to complete. */ 2232 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2233 } 2234 2235 /** 2236 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2237 * @ha: host adapter 2238 * @man_id: Flash manufacturer ID 2239 * @flash_id: Flash ID 2240 */ 2241 static void 2242 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2243 uint8_t *flash_id) 2244 { 2245 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2246 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2247 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2248 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2249 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2250 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2251 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2252 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2253 } 2254 2255 static void 2256 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2257 uint32_t saddr, uint32_t length) 2258 { 2259 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2260 uint32_t midpoint, ilength; 2261 uint8_t data; 2262 2263 midpoint = length / 2; 2264 2265 WRT_REG_WORD(®->nvram, 0); 2266 RD_REG_WORD(®->nvram); 2267 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2268 if (ilength == midpoint) { 2269 WRT_REG_WORD(®->nvram, NVR_SELECT); 2270 RD_REG_WORD(®->nvram); 2271 } 2272 data = qla2x00_read_flash_byte(ha, saddr); 2273 if (saddr % 100) 2274 udelay(10); 2275 *tmp_buf = data; 2276 cond_resched(); 2277 } 2278 } 2279 2280 static inline void 2281 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2282 { 2283 int cnt; 2284 unsigned long flags; 2285 struct qla_hw_data *ha = vha->hw; 2286 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2287 2288 /* Suspend HBA. */ 2289 scsi_block_requests(vha->host); 2290 ha->isp_ops->disable_intrs(ha); 2291 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2292 2293 /* Pause RISC. */ 2294 spin_lock_irqsave(&ha->hardware_lock, flags); 2295 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 2296 RD_REG_WORD(®->hccr); 2297 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2298 for (cnt = 0; cnt < 30000; cnt++) { 2299 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 2300 break; 2301 udelay(100); 2302 } 2303 } else { 2304 udelay(10); 2305 } 2306 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2307 } 2308 2309 static inline void 2310 qla2x00_resume_hba(struct scsi_qla_host *vha) 2311 { 2312 struct qla_hw_data *ha = vha->hw; 2313 2314 /* Resume HBA. */ 2315 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2316 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2317 qla2xxx_wake_dpc(vha); 2318 qla2x00_wait_for_chip_reset(vha); 2319 scsi_unblock_requests(vha->host); 2320 } 2321 2322 uint8_t * 2323 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2324 uint32_t offset, uint32_t length) 2325 { 2326 uint32_t addr, midpoint; 2327 uint8_t *data; 2328 struct qla_hw_data *ha = vha->hw; 2329 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2330 2331 /* Suspend HBA. */ 2332 qla2x00_suspend_hba(vha); 2333 2334 /* Go with read. */ 2335 midpoint = ha->optrom_size / 2; 2336 2337 qla2x00_flash_enable(ha); 2338 WRT_REG_WORD(®->nvram, 0); 2339 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2340 for (addr = offset, data = buf; addr < length; addr++, data++) { 2341 if (addr == midpoint) { 2342 WRT_REG_WORD(®->nvram, NVR_SELECT); 2343 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2344 } 2345 2346 *data = qla2x00_read_flash_byte(ha, addr); 2347 } 2348 qla2x00_flash_disable(ha); 2349 2350 /* Resume HBA. */ 2351 qla2x00_resume_hba(vha); 2352 2353 return buf; 2354 } 2355 2356 int 2357 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2358 uint32_t offset, uint32_t length) 2359 { 2360 2361 int rval; 2362 uint8_t man_id, flash_id, sec_number, data; 2363 uint16_t wd; 2364 uint32_t addr, liter, sec_mask, rest_addr; 2365 struct qla_hw_data *ha = vha->hw; 2366 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2367 2368 /* Suspend HBA. */ 2369 qla2x00_suspend_hba(vha); 2370 2371 rval = QLA_SUCCESS; 2372 sec_number = 0; 2373 2374 /* Reset ISP chip. */ 2375 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2376 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2377 2378 /* Go with write. */ 2379 qla2x00_flash_enable(ha); 2380 do { /* Loop once to provide quick error exit */ 2381 /* Structure of flash memory based on manufacturer */ 2382 if (IS_OEM_001(ha)) { 2383 /* OEM variant with special flash part. */ 2384 man_id = flash_id = 0; 2385 rest_addr = 0xffff; 2386 sec_mask = 0x10000; 2387 goto update_flash; 2388 } 2389 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2390 switch (man_id) { 2391 case 0x20: /* ST flash. */ 2392 if (flash_id == 0xd2 || flash_id == 0xe3) { 2393 /* 2394 * ST m29w008at part - 64kb sector size with 2395 * 32kb,8kb,8kb,16kb sectors at memory address 2396 * 0xf0000. 2397 */ 2398 rest_addr = 0xffff; 2399 sec_mask = 0x10000; 2400 break; 2401 } 2402 /* 2403 * ST m29w010b part - 16kb sector size 2404 * Default to 16kb sectors 2405 */ 2406 rest_addr = 0x3fff; 2407 sec_mask = 0x1c000; 2408 break; 2409 case 0x40: /* Mostel flash. */ 2410 /* Mostel v29c51001 part - 512 byte sector size. */ 2411 rest_addr = 0x1ff; 2412 sec_mask = 0x1fe00; 2413 break; 2414 case 0xbf: /* SST flash. */ 2415 /* SST39sf10 part - 4kb sector size. */ 2416 rest_addr = 0xfff; 2417 sec_mask = 0x1f000; 2418 break; 2419 case 0xda: /* Winbond flash. */ 2420 /* Winbond W29EE011 part - 256 byte sector size. */ 2421 rest_addr = 0x7f; 2422 sec_mask = 0x1ff80; 2423 break; 2424 case 0xc2: /* Macronix flash. */ 2425 /* 64k sector size. */ 2426 if (flash_id == 0x38 || flash_id == 0x4f) { 2427 rest_addr = 0xffff; 2428 sec_mask = 0x10000; 2429 break; 2430 } 2431 /* Fall through... */ 2432 2433 case 0x1f: /* Atmel flash. */ 2434 /* 512k sector size. */ 2435 if (flash_id == 0x13) { 2436 rest_addr = 0x7fffffff; 2437 sec_mask = 0x80000000; 2438 break; 2439 } 2440 /* Fall through... */ 2441 2442 case 0x01: /* AMD flash. */ 2443 if (flash_id == 0x38 || flash_id == 0x40 || 2444 flash_id == 0x4f) { 2445 /* Am29LV081 part - 64kb sector size. */ 2446 /* Am29LV002BT part - 64kb sector size. */ 2447 rest_addr = 0xffff; 2448 sec_mask = 0x10000; 2449 break; 2450 } else if (flash_id == 0x3e) { 2451 /* 2452 * Am29LV008b part - 64kb sector size with 2453 * 32kb,8kb,8kb,16kb sector at memory address 2454 * h0xf0000. 2455 */ 2456 rest_addr = 0xffff; 2457 sec_mask = 0x10000; 2458 break; 2459 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2460 /* 2461 * Am29LV010 part or AM29f010 - 16kb sector 2462 * size. 2463 */ 2464 rest_addr = 0x3fff; 2465 sec_mask = 0x1c000; 2466 break; 2467 } else if (flash_id == 0x6d) { 2468 /* Am29LV001 part - 8kb sector size. */ 2469 rest_addr = 0x1fff; 2470 sec_mask = 0x1e000; 2471 break; 2472 } 2473 /* fall through */ 2474 default: 2475 /* Default to 16 kb sector size. */ 2476 rest_addr = 0x3fff; 2477 sec_mask = 0x1c000; 2478 break; 2479 } 2480 2481 update_flash: 2482 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2483 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2484 rval = QLA_FUNCTION_FAILED; 2485 break; 2486 } 2487 } 2488 2489 for (addr = offset, liter = 0; liter < length; liter++, 2490 addr++) { 2491 data = buf[liter]; 2492 /* Are we at the beginning of a sector? */ 2493 if ((addr & rest_addr) == 0) { 2494 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2495 if (addr >= 0x10000UL) { 2496 if (((addr >> 12) & 0xf0) && 2497 ((man_id == 0x01 && 2498 flash_id == 0x3e) || 2499 (man_id == 0x20 && 2500 flash_id == 0xd2))) { 2501 sec_number++; 2502 if (sec_number == 1) { 2503 rest_addr = 2504 0x7fff; 2505 sec_mask = 2506 0x18000; 2507 } else if ( 2508 sec_number == 2 || 2509 sec_number == 3) { 2510 rest_addr = 2511 0x1fff; 2512 sec_mask = 2513 0x1e000; 2514 } else if ( 2515 sec_number == 4) { 2516 rest_addr = 2517 0x3fff; 2518 sec_mask = 2519 0x1c000; 2520 } 2521 } 2522 } 2523 } else if (addr == ha->optrom_size / 2) { 2524 WRT_REG_WORD(®->nvram, NVR_SELECT); 2525 RD_REG_WORD(®->nvram); 2526 } 2527 2528 if (flash_id == 0xda && man_id == 0xc1) { 2529 qla2x00_write_flash_byte(ha, 0x5555, 2530 0xaa); 2531 qla2x00_write_flash_byte(ha, 0x2aaa, 2532 0x55); 2533 qla2x00_write_flash_byte(ha, 0x5555, 2534 0xa0); 2535 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2536 /* Then erase it */ 2537 if (qla2x00_erase_flash_sector(ha, 2538 addr, sec_mask, man_id, 2539 flash_id)) { 2540 rval = QLA_FUNCTION_FAILED; 2541 break; 2542 } 2543 if (man_id == 0x01 && flash_id == 0x6d) 2544 sec_number++; 2545 } 2546 } 2547 2548 if (man_id == 0x01 && flash_id == 0x6d) { 2549 if (sec_number == 1 && 2550 addr == (rest_addr - 1)) { 2551 rest_addr = 0x0fff; 2552 sec_mask = 0x1f000; 2553 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2554 rest_addr = 0x3fff; 2555 sec_mask = 0x1c000; 2556 } 2557 } 2558 2559 if (qla2x00_program_flash_address(ha, addr, data, 2560 man_id, flash_id)) { 2561 rval = QLA_FUNCTION_FAILED; 2562 break; 2563 } 2564 cond_resched(); 2565 } 2566 } while (0); 2567 qla2x00_flash_disable(ha); 2568 2569 /* Resume HBA. */ 2570 qla2x00_resume_hba(vha); 2571 2572 return rval; 2573 } 2574 2575 uint8_t * 2576 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2577 uint32_t offset, uint32_t length) 2578 { 2579 struct qla_hw_data *ha = vha->hw; 2580 2581 /* Suspend HBA. */ 2582 scsi_block_requests(vha->host); 2583 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2584 2585 /* Go with read. */ 2586 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2); 2587 2588 /* Resume HBA. */ 2589 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2590 scsi_unblock_requests(vha->host); 2591 2592 return buf; 2593 } 2594 2595 int 2596 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2597 uint32_t offset, uint32_t length) 2598 { 2599 int rval; 2600 struct qla_hw_data *ha = vha->hw; 2601 2602 /* Suspend HBA. */ 2603 scsi_block_requests(vha->host); 2604 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2605 2606 /* Go with write. */ 2607 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2, 2608 length >> 2); 2609 2610 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2611 scsi_unblock_requests(vha->host); 2612 2613 return rval; 2614 } 2615 2616 uint8_t * 2617 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2618 uint32_t offset, uint32_t length) 2619 { 2620 int rval; 2621 dma_addr_t optrom_dma; 2622 void *optrom; 2623 uint8_t *pbuf; 2624 uint32_t faddr, left, burst; 2625 struct qla_hw_data *ha = vha->hw; 2626 2627 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 2628 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2629 goto try_fast; 2630 if (offset & 0xfff) 2631 goto slow_read; 2632 if (length < OPTROM_BURST_SIZE) 2633 goto slow_read; 2634 2635 try_fast: 2636 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2637 &optrom_dma, GFP_KERNEL); 2638 if (!optrom) { 2639 ql_log(ql_log_warn, vha, 0x00cc, 2640 "Unable to allocate memory for optrom burst read (%x KB).\n", 2641 OPTROM_BURST_SIZE / 1024); 2642 goto slow_read; 2643 } 2644 2645 pbuf = buf; 2646 faddr = offset >> 2; 2647 left = length >> 2; 2648 burst = OPTROM_BURST_DWORDS; 2649 while (left != 0) { 2650 if (burst > left) 2651 burst = left; 2652 2653 rval = qla2x00_dump_ram(vha, optrom_dma, 2654 flash_data_addr(ha, faddr), burst); 2655 if (rval) { 2656 ql_log(ql_log_warn, vha, 0x00f5, 2657 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 2658 rval, flash_data_addr(ha, faddr), 2659 (unsigned long long)optrom_dma); 2660 ql_log(ql_log_warn, vha, 0x00f6, 2661 "Reverting to slow-read.\n"); 2662 2663 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2664 optrom, optrom_dma); 2665 goto slow_read; 2666 } 2667 2668 memcpy(pbuf, optrom, burst * 4); 2669 2670 left -= burst; 2671 faddr += burst; 2672 pbuf += burst * 4; 2673 } 2674 2675 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 2676 optrom_dma); 2677 2678 return buf; 2679 2680 slow_read: 2681 return qla24xx_read_optrom_data(vha, buf, offset, length); 2682 } 2683 2684 /** 2685 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 2686 * @ha: HA context 2687 * @pcids: Pointer to the FCODE PCI data structure 2688 * 2689 * The process of retrieving the FCODE version information is at best 2690 * described as interesting. 2691 * 2692 * Within the first 100h bytes of the image an ASCII string is present 2693 * which contains several pieces of information including the FCODE 2694 * version. Unfortunately it seems the only reliable way to retrieve 2695 * the version is by scanning for another sentinel within the string, 2696 * the FCODE build date: 2697 * 2698 * ... 2.00.02 10/17/02 ... 2699 * 2700 * Returns QLA_SUCCESS on successful retrieval of version. 2701 */ 2702 static void 2703 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 2704 { 2705 int ret = QLA_FUNCTION_FAILED; 2706 uint32_t istart, iend, iter, vend; 2707 uint8_t do_next, rbyte, *vbyte; 2708 2709 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2710 2711 /* Skip the PCI data structure. */ 2712 istart = pcids + 2713 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 2714 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 2715 iend = istart + 0x100; 2716 do { 2717 /* Scan for the sentinel date string...eeewww. */ 2718 do_next = 0; 2719 iter = istart; 2720 while ((iter < iend) && !do_next) { 2721 iter++; 2722 if (qla2x00_read_flash_byte(ha, iter) == '/') { 2723 if (qla2x00_read_flash_byte(ha, iter + 2) == 2724 '/') 2725 do_next++; 2726 else if (qla2x00_read_flash_byte(ha, 2727 iter + 3) == '/') 2728 do_next++; 2729 } 2730 } 2731 if (!do_next) 2732 break; 2733 2734 /* Backtrack to previous ' ' (space). */ 2735 do_next = 0; 2736 while ((iter > istart) && !do_next) { 2737 iter--; 2738 if (qla2x00_read_flash_byte(ha, iter) == ' ') 2739 do_next++; 2740 } 2741 if (!do_next) 2742 break; 2743 2744 /* 2745 * Mark end of version tag, and find previous ' ' (space) or 2746 * string length (recent FCODE images -- major hack ahead!!!). 2747 */ 2748 vend = iter - 1; 2749 do_next = 0; 2750 while ((iter > istart) && !do_next) { 2751 iter--; 2752 rbyte = qla2x00_read_flash_byte(ha, iter); 2753 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 2754 do_next++; 2755 } 2756 if (!do_next) 2757 break; 2758 2759 /* Mark beginning of version tag, and copy data. */ 2760 iter++; 2761 if ((vend - iter) && 2762 ((vend - iter) < sizeof(ha->fcode_revision))) { 2763 vbyte = ha->fcode_revision; 2764 while (iter <= vend) { 2765 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 2766 iter++; 2767 } 2768 ret = QLA_SUCCESS; 2769 } 2770 } while (0); 2771 2772 if (ret != QLA_SUCCESS) 2773 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2774 } 2775 2776 int 2777 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2778 { 2779 int ret = QLA_SUCCESS; 2780 uint8_t code_type, last_image; 2781 uint32_t pcihdr, pcids; 2782 uint8_t *dbyte; 2783 uint16_t *dcode; 2784 struct qla_hw_data *ha = vha->hw; 2785 2786 if (!ha->pio_address || !mbuf) 2787 return QLA_FUNCTION_FAILED; 2788 2789 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2790 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2791 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2792 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2793 2794 qla2x00_flash_enable(ha); 2795 2796 /* Begin with first PCI expansion ROM header. */ 2797 pcihdr = 0; 2798 last_image = 1; 2799 do { 2800 /* Verify PCI expansion ROM header. */ 2801 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 2802 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 2803 /* No signature */ 2804 ql_log(ql_log_fatal, vha, 0x0050, 2805 "No matching ROM signature.\n"); 2806 ret = QLA_FUNCTION_FAILED; 2807 break; 2808 } 2809 2810 /* Locate PCI data structure. */ 2811 pcids = pcihdr + 2812 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 2813 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 2814 2815 /* Validate signature of PCI data structure. */ 2816 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 2817 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 2818 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 2819 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 2820 /* Incorrect header. */ 2821 ql_log(ql_log_fatal, vha, 0x0051, 2822 "PCI data struct not found pcir_adr=%x.\n", pcids); 2823 ret = QLA_FUNCTION_FAILED; 2824 break; 2825 } 2826 2827 /* Read version */ 2828 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 2829 switch (code_type) { 2830 case ROM_CODE_TYPE_BIOS: 2831 /* Intel x86, PC-AT compatible. */ 2832 ha->bios_revision[0] = 2833 qla2x00_read_flash_byte(ha, pcids + 0x12); 2834 ha->bios_revision[1] = 2835 qla2x00_read_flash_byte(ha, pcids + 0x13); 2836 ql_dbg(ql_dbg_init, vha, 0x0052, 2837 "Read BIOS %d.%d.\n", 2838 ha->bios_revision[1], ha->bios_revision[0]); 2839 break; 2840 case ROM_CODE_TYPE_FCODE: 2841 /* Open Firmware standard for PCI (FCode). */ 2842 /* Eeeewww... */ 2843 qla2x00_get_fcode_version(ha, pcids); 2844 break; 2845 case ROM_CODE_TYPE_EFI: 2846 /* Extensible Firmware Interface (EFI). */ 2847 ha->efi_revision[0] = 2848 qla2x00_read_flash_byte(ha, pcids + 0x12); 2849 ha->efi_revision[1] = 2850 qla2x00_read_flash_byte(ha, pcids + 0x13); 2851 ql_dbg(ql_dbg_init, vha, 0x0053, 2852 "Read EFI %d.%d.\n", 2853 ha->efi_revision[1], ha->efi_revision[0]); 2854 break; 2855 default: 2856 ql_log(ql_log_warn, vha, 0x0054, 2857 "Unrecognized code type %x at pcids %x.\n", 2858 code_type, pcids); 2859 break; 2860 } 2861 2862 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 2863 2864 /* Locate next PCI expansion ROM. */ 2865 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 2866 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 2867 } while (!last_image); 2868 2869 if (IS_QLA2322(ha)) { 2870 /* Read firmware image information. */ 2871 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2872 dbyte = mbuf; 2873 memset(dbyte, 0, 8); 2874 dcode = (uint16_t *)dbyte; 2875 2876 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 2877 8); 2878 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 2879 "Dumping fw " 2880 "ver from flash:.\n"); 2881 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 2882 (uint8_t *)dbyte, 8); 2883 2884 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 2885 dcode[2] == 0xffff && dcode[3] == 0xffff) || 2886 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2887 dcode[3] == 0)) { 2888 ql_log(ql_log_warn, vha, 0x0057, 2889 "Unrecognized fw revision at %x.\n", 2890 ha->flt_region_fw * 4); 2891 } else { 2892 /* values are in big endian */ 2893 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 2894 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 2895 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 2896 ql_dbg(ql_dbg_init, vha, 0x0058, 2897 "FW Version: " 2898 "%d.%d.%d.\n", ha->fw_revision[0], 2899 ha->fw_revision[1], ha->fw_revision[2]); 2900 } 2901 } 2902 2903 qla2x00_flash_disable(ha); 2904 2905 return ret; 2906 } 2907 2908 int 2909 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2910 { 2911 int ret = QLA_SUCCESS; 2912 uint32_t pcihdr, pcids; 2913 uint32_t *dcode; 2914 uint8_t *bcode; 2915 uint8_t code_type, last_image; 2916 struct qla_hw_data *ha = vha->hw; 2917 2918 if (!mbuf) 2919 return QLA_FUNCTION_FAILED; 2920 2921 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2922 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2923 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2924 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2925 2926 dcode = mbuf; 2927 2928 /* Begin with first PCI expansion ROM header. */ 2929 pcihdr = ha->flt_region_boot << 2; 2930 last_image = 1; 2931 do { 2932 /* Verify PCI expansion ROM header. */ 2933 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr, 2934 0x20 * 4); 2935 bcode = mbuf + (pcihdr % 4); 2936 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 2937 /* No signature */ 2938 ql_log(ql_log_fatal, vha, 0x0154, 2939 "No matching ROM signature.\n"); 2940 ret = QLA_FUNCTION_FAILED; 2941 break; 2942 } 2943 2944 /* Locate PCI data structure. */ 2945 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 2946 2947 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids, 2948 0x20 * 4); 2949 bcode = mbuf + (pcihdr % 4); 2950 2951 /* Validate signature of PCI data structure. */ 2952 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2953 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2954 /* Incorrect header. */ 2955 ql_log(ql_log_fatal, vha, 0x0155, 2956 "PCI data struct not found pcir_adr=%x.\n", pcids); 2957 ret = QLA_FUNCTION_FAILED; 2958 break; 2959 } 2960 2961 /* Read version */ 2962 code_type = bcode[0x14]; 2963 switch (code_type) { 2964 case ROM_CODE_TYPE_BIOS: 2965 /* Intel x86, PC-AT compatible. */ 2966 ha->bios_revision[0] = bcode[0x12]; 2967 ha->bios_revision[1] = bcode[0x13]; 2968 ql_dbg(ql_dbg_init, vha, 0x0156, 2969 "Read BIOS %d.%d.\n", 2970 ha->bios_revision[1], ha->bios_revision[0]); 2971 break; 2972 case ROM_CODE_TYPE_FCODE: 2973 /* Open Firmware standard for PCI (FCode). */ 2974 ha->fcode_revision[0] = bcode[0x12]; 2975 ha->fcode_revision[1] = bcode[0x13]; 2976 ql_dbg(ql_dbg_init, vha, 0x0157, 2977 "Read FCODE %d.%d.\n", 2978 ha->fcode_revision[1], ha->fcode_revision[0]); 2979 break; 2980 case ROM_CODE_TYPE_EFI: 2981 /* Extensible Firmware Interface (EFI). */ 2982 ha->efi_revision[0] = bcode[0x12]; 2983 ha->efi_revision[1] = bcode[0x13]; 2984 ql_dbg(ql_dbg_init, vha, 0x0158, 2985 "Read EFI %d.%d.\n", 2986 ha->efi_revision[1], ha->efi_revision[0]); 2987 break; 2988 default: 2989 ql_log(ql_log_warn, vha, 0x0159, 2990 "Unrecognized code type %x at pcids %x.\n", 2991 code_type, pcids); 2992 break; 2993 } 2994 2995 last_image = bcode[0x15] & BIT_7; 2996 2997 /* Locate next PCI expansion ROM. */ 2998 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2999 } while (!last_image); 3000 3001 /* Read firmware image information. */ 3002 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3003 dcode = mbuf; 3004 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2, 3005 0x20); 3006 bcode = mbuf + (pcihdr % 4); 3007 3008 /* Validate signature of PCI data structure. */ 3009 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3010 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3011 ha->fw_revision[0] = bcode[0x4]; 3012 ha->fw_revision[1] = bcode[0x5]; 3013 ha->fw_revision[2] = bcode[0x6]; 3014 ql_dbg(ql_dbg_init, vha, 0x0153, 3015 "Firmware revision %d.%d.%d\n", 3016 ha->fw_revision[0], ha->fw_revision[1], 3017 ha->fw_revision[2]); 3018 } 3019 3020 return ret; 3021 } 3022 3023 int 3024 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3025 { 3026 int ret = QLA_SUCCESS; 3027 uint32_t pcihdr, pcids; 3028 uint32_t *dcode; 3029 uint8_t *bcode; 3030 uint8_t code_type, last_image; 3031 int i; 3032 struct qla_hw_data *ha = vha->hw; 3033 uint32_t faddr = 0; 3034 3035 pcihdr = pcids = 0; 3036 3037 if (IS_P3P_TYPE(ha)) 3038 return ret; 3039 3040 if (!mbuf) 3041 return QLA_FUNCTION_FAILED; 3042 3043 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3044 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3045 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3046 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3047 3048 dcode = mbuf; 3049 pcihdr = ha->flt_region_boot << 2; 3050 if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3051 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE) 3052 pcihdr = ha->flt_region_boot_sec << 2; 3053 3054 last_image = 1; 3055 do { 3056 /* Verify PCI expansion ROM header. */ 3057 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3058 bcode = mbuf + (pcihdr % 4); 3059 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 3060 /* No signature */ 3061 ql_log(ql_log_fatal, vha, 0x0059, 3062 "No matching ROM signature.\n"); 3063 ret = QLA_FUNCTION_FAILED; 3064 break; 3065 } 3066 3067 /* Locate PCI data structure. */ 3068 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3069 3070 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3071 bcode = mbuf + (pcihdr % 4); 3072 3073 /* Validate signature of PCI data structure. */ 3074 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 3075 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 3076 /* Incorrect header. */ 3077 ql_log(ql_log_fatal, vha, 0x005a, 3078 "PCI data struct not found pcir_adr=%x.\n", pcids); 3079 ret = QLA_FUNCTION_FAILED; 3080 break; 3081 } 3082 3083 /* Read version */ 3084 code_type = bcode[0x14]; 3085 switch (code_type) { 3086 case ROM_CODE_TYPE_BIOS: 3087 /* Intel x86, PC-AT compatible. */ 3088 ha->bios_revision[0] = bcode[0x12]; 3089 ha->bios_revision[1] = bcode[0x13]; 3090 ql_dbg(ql_dbg_init, vha, 0x005b, 3091 "Read BIOS %d.%d.\n", 3092 ha->bios_revision[1], ha->bios_revision[0]); 3093 break; 3094 case ROM_CODE_TYPE_FCODE: 3095 /* Open Firmware standard for PCI (FCode). */ 3096 ha->fcode_revision[0] = bcode[0x12]; 3097 ha->fcode_revision[1] = bcode[0x13]; 3098 ql_dbg(ql_dbg_init, vha, 0x005c, 3099 "Read FCODE %d.%d.\n", 3100 ha->fcode_revision[1], ha->fcode_revision[0]); 3101 break; 3102 case ROM_CODE_TYPE_EFI: 3103 /* Extensible Firmware Interface (EFI). */ 3104 ha->efi_revision[0] = bcode[0x12]; 3105 ha->efi_revision[1] = bcode[0x13]; 3106 ql_dbg(ql_dbg_init, vha, 0x005d, 3107 "Read EFI %d.%d.\n", 3108 ha->efi_revision[1], ha->efi_revision[0]); 3109 break; 3110 default: 3111 ql_log(ql_log_warn, vha, 0x005e, 3112 "Unrecognized code type %x at pcids %x.\n", 3113 code_type, pcids); 3114 break; 3115 } 3116 3117 last_image = bcode[0x15] & BIT_7; 3118 3119 /* Locate next PCI expansion ROM. */ 3120 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3121 } while (!last_image); 3122 3123 /* Read firmware image information. */ 3124 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3125 dcode = mbuf; 3126 faddr = ha->flt_region_fw; 3127 if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3128 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE) 3129 faddr = ha->flt_region_fw_sec; 3130 3131 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); 3132 for (i = 0; i < 4; i++) 3133 dcode[i] = be32_to_cpu(dcode[i]); 3134 3135 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 3136 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 3137 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3138 dcode[3] == 0)) { 3139 ql_log(ql_log_warn, vha, 0x005f, 3140 "Unrecognized fw revision at %x.\n", 3141 ha->flt_region_fw * 4); 3142 } else { 3143 ha->fw_revision[0] = dcode[0]; 3144 ha->fw_revision[1] = dcode[1]; 3145 ha->fw_revision[2] = dcode[2]; 3146 ha->fw_revision[3] = dcode[3]; 3147 ql_dbg(ql_dbg_init, vha, 0x0060, 3148 "Firmware revision %d.%d.%d (%x).\n", 3149 ha->fw_revision[0], ha->fw_revision[1], 3150 ha->fw_revision[2], ha->fw_revision[3]); 3151 } 3152 3153 /* Check for golden firmware and get version if available */ 3154 if (!IS_QLA81XX(ha)) { 3155 /* Golden firmware is not present in non 81XX adapters */ 3156 return ret; 3157 } 3158 3159 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3160 dcode = mbuf; 3161 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, 3162 ha->flt_region_gold_fw << 2, 32); 3163 3164 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF && 3165 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) { 3166 ql_log(ql_log_warn, vha, 0x0056, 3167 "Unrecognized golden fw at 0x%x.\n", 3168 ha->flt_region_gold_fw * 4); 3169 return ret; 3170 } 3171 3172 for (i = 4; i < 8; i++) 3173 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]); 3174 3175 return ret; 3176 } 3177 3178 static int 3179 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3180 { 3181 if (pos >= end || *pos != 0x82) 3182 return 0; 3183 3184 pos += 3 + pos[1]; 3185 if (pos >= end || *pos != 0x90) 3186 return 0; 3187 3188 pos += 3 + pos[1]; 3189 if (pos >= end || *pos != 0x78) 3190 return 0; 3191 3192 return 1; 3193 } 3194 3195 int 3196 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3197 { 3198 struct qla_hw_data *ha = vha->hw; 3199 uint8_t *pos = ha->vpd; 3200 uint8_t *end = pos + ha->vpd_size; 3201 int len = 0; 3202 3203 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3204 return 0; 3205 3206 while (pos < end && *pos != 0x78) { 3207 len = (*pos == 0x82) ? pos[1] : pos[2]; 3208 3209 if (!strncmp(pos, key, strlen(key))) 3210 break; 3211 3212 if (*pos != 0x90 && *pos != 0x91) 3213 pos += len; 3214 3215 pos += 3; 3216 } 3217 3218 if (pos < end - len && *pos != 0x78) 3219 return scnprintf(str, size, "%.*s", len, pos + 3); 3220 3221 return 0; 3222 } 3223 3224 int 3225 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3226 { 3227 int len, max_len; 3228 uint32_t fcp_prio_addr; 3229 struct qla_hw_data *ha = vha->hw; 3230 3231 if (!ha->fcp_prio_cfg) { 3232 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3233 if (!ha->fcp_prio_cfg) { 3234 ql_log(ql_log_warn, vha, 0x00d5, 3235 "Unable to allocate memory for fcp priority data (%x).\n", 3236 FCP_PRIO_CFG_SIZE); 3237 return QLA_FUNCTION_FAILED; 3238 } 3239 } 3240 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3241 3242 fcp_prio_addr = ha->flt_region_fcp_prio; 3243 3244 /* first read the fcp priority data header from flash */ 3245 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg, 3246 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3247 3248 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3249 goto fail; 3250 3251 /* read remaining FCP CMD config data from flash */ 3252 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3253 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; 3254 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3255 3256 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0], 3257 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3258 3259 /* revalidate the entire FCP priority config data, including entries */ 3260 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3261 goto fail; 3262 3263 ha->flags.fcp_prio_enabled = 1; 3264 return QLA_SUCCESS; 3265 fail: 3266 vfree(ha->fcp_prio_cfg); 3267 ha->fcp_prio_cfg = NULL; 3268 return QLA_FUNCTION_FAILED; 3269 } 3270