xref: /linux/drivers/scsi/qla2xxx/qla_os.c (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * QLogic Fibre Channel HBA Driver
4  * Copyright (c)  2003-2014 QLogic Corporation
5  */
6 #include "qla_def.h"
7 
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20 
21 #include <scsi/scsi_tcq.h>
22 #include <scsi/scsicam.h>
23 #include <scsi/scsi_transport.h>
24 #include <scsi/scsi_transport_fc.h>
25 
26 #include "qla_target.h"
27 
28 /*
29  * Driver version
30  */
31 char qla2x00_version_str[40];
32 
33 static int apidev_major;
34 
35 /*
36  * SRB allocation cache
37  */
38 struct kmem_cache *srb_cachep;
39 
40 static struct trace_array *qla_trc_array;
41 
42 int ql2xfulldump_on_mpifail;
43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
45 		 "Set this to take full dump on MPI hang.");
46 
47 int ql2xenforce_iocb_limit = 2;
48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
50 		 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
51 		 "1: track usage per queue, 2: track usage per adapter");
52 
53 /*
54  * CT6 CTX allocation cache
55  */
56 static struct kmem_cache *ctx_cachep;
57 /*
58  * error level for logging
59  */
60 uint ql_errlev = 0x8001;
61 
62 int ql2xsecenable;
63 module_param(ql2xsecenable, int, S_IRUGO);
64 MODULE_PARM_DESC(ql2xsecenable,
65 	"Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
66 
67 static int ql2xenableclass2;
68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
69 MODULE_PARM_DESC(ql2xenableclass2,
70 		"Specify if Class 2 operations are supported from the very "
71 		"beginning. Default is 0 - class 2 not supported.");
72 
73 
74 int ql2xlogintimeout = 20;
75 module_param(ql2xlogintimeout, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xlogintimeout,
77 		"Login timeout value in seconds.");
78 
79 int qlport_down_retry;
80 module_param(qlport_down_retry, int, S_IRUGO);
81 MODULE_PARM_DESC(qlport_down_retry,
82 		"Maximum number of command retries to a port that returns "
83 		"a PORT-DOWN status.");
84 
85 int ql2xplogiabsentdevice;
86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xplogiabsentdevice,
88 		"Option to enable PLOGI to devices that are not present after "
89 		"a Fabric scan.  This is needed for several broken switches. "
90 		"Default is 0 - no PLOGI. 1 - perform PLOGI.");
91 
92 int ql2xloginretrycount;
93 module_param(ql2xloginretrycount, int, S_IRUGO);
94 MODULE_PARM_DESC(ql2xloginretrycount,
95 		"Specify an alternate value for the NVRAM login retry count.");
96 
97 int ql2xallocfwdump = 1;
98 module_param(ql2xallocfwdump, int, S_IRUGO);
99 MODULE_PARM_DESC(ql2xallocfwdump,
100 		"Option to enable allocation of memory for a firmware dump "
101 		"during HBA initialization.  Memory allocation requirements "
102 		"vary by ISP type.  Default is 1 - allocate memory.");
103 
104 int ql2xextended_error_logging;
105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 MODULE_PARM_DESC(ql2xextended_error_logging,
108 		"Option to enable extended error logging,\n"
109 		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
110 		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
112 		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
113 		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
114 		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
115 		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
116 		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
117 		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
118 		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
119 		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
120 		"\t\t0x1e400000 - Preferred value for capturing essential "
121 		"debug information (equivalent to old "
122 		"ql2xextended_error_logging=1).\n"
123 		"\t\tDo LOGICAL OR of the value to enable more than one level");
124 
125 int ql2xextended_error_logging_ktrace = 1;
126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
128 		"Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
129 
130 int ql2xshiftctondsd = 6;
131 module_param(ql2xshiftctondsd, int, S_IRUGO);
132 MODULE_PARM_DESC(ql2xshiftctondsd,
133 		"Set to control shifting of command type processing "
134 		"based on total number of SG elements.");
135 
136 int ql2xfdmienable = 1;
137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 MODULE_PARM_DESC(ql2xfdmienable,
140 		"Enables FDMI registrations. "
141 		"0 - no FDMI registrations. "
142 		"1 - provide FDMI registrations (default).");
143 
144 #define MAX_Q_DEPTH	64
145 static int ql2xmaxqdepth = MAX_Q_DEPTH;
146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
147 MODULE_PARM_DESC(ql2xmaxqdepth,
148 		"Maximum queue depth to set for each LUN. "
149 		"Default is 64.");
150 
151 int ql2xenabledif = 2;
152 module_param(ql2xenabledif, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xenabledif,
154 		" Enable T10-CRC-DIF:\n"
155 		" Default is 2.\n"
156 		"  0 -- No DIF Support\n"
157 		"  1 -- Enable DIF for all types\n"
158 		"  2 -- Enable DIF for all types, except Type 0.\n");
159 
160 #if (IS_ENABLED(CONFIG_NVME_FC))
161 int ql2xnvmeenable = 1;
162 #else
163 int ql2xnvmeenable;
164 #endif
165 module_param(ql2xnvmeenable, int, 0644);
166 MODULE_PARM_DESC(ql2xnvmeenable,
167     "Enables NVME support. "
168     "0 - no NVMe.  Default is Y");
169 
170 int ql2xenablehba_err_chk = 2;
171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xenablehba_err_chk,
173 		" Enable T10-CRC-DIF Error isolation by HBA:\n"
174 		" Default is 2.\n"
175 		"  0 -- Error isolation disabled\n"
176 		"  1 -- Error isolation enabled only for DIX Type 0\n"
177 		"  2 -- Error isolation enabled for all Types\n");
178 
179 int ql2xiidmaenable = 1;
180 module_param(ql2xiidmaenable, int, S_IRUGO);
181 MODULE_PARM_DESC(ql2xiidmaenable,
182 		"Enables iIDMA settings "
183 		"Default is 1 - perform iIDMA. 0 - no iIDMA.");
184 
185 int ql2xmqsupport = 1;
186 module_param(ql2xmqsupport, int, S_IRUGO);
187 MODULE_PARM_DESC(ql2xmqsupport,
188 		"Enable on demand multiple queue pairs support "
189 		"Default is 1 for supported. "
190 		"Set it to 0 to turn off mq qpair support.");
191 
192 int ql2xfwloadbin;
193 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
194 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
195 MODULE_PARM_DESC(ql2xfwloadbin,
196 		"Option to specify location from which to load ISP firmware:.\n"
197 		" 2 -- load firmware via the request_firmware() (hotplug).\n"
198 		"      interface.\n"
199 		" 1 -- load firmware from flash.\n"
200 		" 0 -- use default semantics.\n");
201 
202 int ql2xetsenable;
203 module_param(ql2xetsenable, int, S_IRUGO);
204 MODULE_PARM_DESC(ql2xetsenable,
205 		"Enables firmware ETS burst."
206 		"Default is 0 - skip ETS enablement.");
207 
208 int ql2xdbwr = 1;
209 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
210 MODULE_PARM_DESC(ql2xdbwr,
211 		"Option to specify scheme for request queue posting.\n"
212 		" 0 -- Regular doorbell.\n"
213 		" 1 -- CAMRAM doorbell (faster).\n");
214 
215 int ql2xgffidenable;
216 module_param(ql2xgffidenable, int, S_IRUGO);
217 MODULE_PARM_DESC(ql2xgffidenable,
218 		"Enables GFF_ID checks of port type. "
219 		"Default is 0 - Do not use GFF_ID information.");
220 
221 int ql2xasynctmfenable = 1;
222 module_param(ql2xasynctmfenable, int, S_IRUGO);
223 MODULE_PARM_DESC(ql2xasynctmfenable,
224 		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
225 		"Default is 1 - Issue TM IOCBs via mailbox mechanism.");
226 
227 int ql2xdontresethba;
228 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
229 MODULE_PARM_DESC(ql2xdontresethba,
230 		"Option to specify reset behaviour.\n"
231 		" 0 (Default) -- Reset on failure.\n"
232 		" 1 -- Do not reset on failure.\n");
233 
234 uint64_t ql2xmaxlun = MAX_LUNS;
235 module_param(ql2xmaxlun, ullong, S_IRUGO);
236 MODULE_PARM_DESC(ql2xmaxlun,
237 		"Defines the maximum LU number to register with the SCSI "
238 		"midlayer. Default is 65535.");
239 
240 int ql2xmdcapmask = 0x1F;
241 module_param(ql2xmdcapmask, int, S_IRUGO);
242 MODULE_PARM_DESC(ql2xmdcapmask,
243 		"Set the Minidump driver capture mask level. "
244 		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
245 
246 int ql2xmdenable = 1;
247 module_param(ql2xmdenable, int, S_IRUGO);
248 MODULE_PARM_DESC(ql2xmdenable,
249 		"Enable/disable MiniDump. "
250 		"0 - MiniDump disabled. "
251 		"1 (Default) - MiniDump enabled.");
252 
253 int ql2xexlogins;
254 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
255 MODULE_PARM_DESC(ql2xexlogins,
256 		 "Number of extended Logins. "
257 		 "0 (Default)- Disabled.");
258 
259 int ql2xexchoffld = 1024;
260 module_param(ql2xexchoffld, uint, 0644);
261 MODULE_PARM_DESC(ql2xexchoffld,
262 	"Number of target exchanges.");
263 
264 int ql2xiniexchg = 1024;
265 module_param(ql2xiniexchg, uint, 0644);
266 MODULE_PARM_DESC(ql2xiniexchg,
267 	"Number of initiator exchanges.");
268 
269 int ql2xfwholdabts;
270 module_param(ql2xfwholdabts, int, S_IRUGO);
271 MODULE_PARM_DESC(ql2xfwholdabts,
272 		"Allow FW to hold status IOCB until ABTS rsp received. "
273 		"0 (Default) Do not set fw option. "
274 		"1 - Set fw option to hold ABTS.");
275 
276 int ql2xmvasynctoatio = 1;
277 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
278 MODULE_PARM_DESC(ql2xmvasynctoatio,
279 		"Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
280 		"0 (Default). Do not move IOCBs"
281 		"1 - Move IOCBs.");
282 
283 int ql2xautodetectsfp = 1;
284 module_param(ql2xautodetectsfp, int, 0444);
285 MODULE_PARM_DESC(ql2xautodetectsfp,
286 		 "Detect SFP range and set appropriate distance.\n"
287 		 "1 (Default): Enable\n");
288 
289 int ql2xenablemsix = 1;
290 module_param(ql2xenablemsix, int, 0444);
291 MODULE_PARM_DESC(ql2xenablemsix,
292 		 "Set to enable MSI or MSI-X interrupt mechanism.\n"
293 		 " Default is 1, enable MSI-X interrupt mechanism.\n"
294 		 " 0 -- enable traditional pin-based mechanism.\n"
295 		 " 1 -- enable MSI-X interrupt mechanism.\n"
296 		 " 2 -- enable MSI interrupt mechanism.\n");
297 
298 int qla2xuseresexchforels;
299 module_param(qla2xuseresexchforels, int, 0444);
300 MODULE_PARM_DESC(qla2xuseresexchforels,
301 		 "Reserve 1/2 of emergency exchanges for ELS.\n"
302 		 " 0 (default): disabled");
303 
304 static int ql2xprotmask;
305 module_param(ql2xprotmask, int, 0644);
306 MODULE_PARM_DESC(ql2xprotmask,
307 		 "Override DIF/DIX protection capabilities mask\n"
308 		 "Default is 0 which sets protection mask based on "
309 		 "capabilities reported by HBA firmware.\n");
310 
311 static int ql2xprotguard;
312 module_param(ql2xprotguard, int, 0644);
313 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
314 		 "  0 -- Let HBA firmware decide\n"
315 		 "  1 -- Force T10 CRC\n"
316 		 "  2 -- Force IP checksum\n");
317 
318 int ql2xdifbundlinginternalbuffers;
319 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
320 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
321     "Force using internal buffers for DIF information\n"
322     "0 (Default). Based on check.\n"
323     "1 Force using internal buffers\n");
324 
325 int ql2xsmartsan;
326 module_param(ql2xsmartsan, int, 0444);
327 module_param_named(smartsan, ql2xsmartsan, int, 0444);
328 MODULE_PARM_DESC(ql2xsmartsan,
329 		"Send SmartSAN Management Attributes for FDMI Registration."
330 		" Default is 0 - No SmartSAN registration,"
331 		" 1 - Register SmartSAN Management Attributes.");
332 
333 int ql2xrdpenable;
334 module_param(ql2xrdpenable, int, 0444);
335 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
336 MODULE_PARM_DESC(ql2xrdpenable,
337 		"Enables RDP responses. "
338 		"0 - no RDP responses (default). "
339 		"1 - provide RDP responses.");
340 int ql2xabts_wait_nvme = 1;
341 module_param(ql2xabts_wait_nvme, int, 0444);
342 MODULE_PARM_DESC(ql2xabts_wait_nvme,
343 		 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
344 
345 
346 static u32 ql2xdelay_before_pci_error_handling = 5;
347 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
348 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
349 	"Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
350 
351 static void qla2x00_clear_drv_active(struct qla_hw_data *);
352 static void qla2x00_free_device(scsi_qla_host_t *);
353 static void qla2xxx_map_queues(struct Scsi_Host *shost);
354 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
355 
356 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
357 module_param(ql2xnvme_queues, uint, S_IRUGO);
358 MODULE_PARM_DESC(ql2xnvme_queues,
359 	"Number of NVMe Queues that can be configured.\n"
360 	"Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
361 	"1 - Minimum number of queues supported\n"
362 	"8 - Default value");
363 
364 int ql2xfc2target = 1;
365 module_param(ql2xfc2target, int, 0444);
366 MODULE_PARM_DESC(qla2xfc2target,
367 		  "Enables FC2 Target support. "
368 		  "0 - FC2 Target support is disabled. "
369 		  "1 - FC2 Target support is enabled (default).");
370 
371 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
372 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
373 
374 /* TODO Convert to inlines
375  *
376  * Timer routines
377  */
378 
379 __inline__ void
380 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
381 {
382 	timer_setup(&vha->timer, qla2x00_timer, 0);
383 	vha->timer.expires = jiffies + interval * HZ;
384 	add_timer(&vha->timer);
385 	vha->timer_active = 1;
386 }
387 
388 static inline void
389 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
390 {
391 	/* Currently used for 82XX only. */
392 	if (vha->device_flags & DFLG_DEV_FAILED) {
393 		ql_dbg(ql_dbg_timer, vha, 0x600d,
394 		    "Device in a failed state, returning.\n");
395 		return;
396 	}
397 
398 	mod_timer(&vha->timer, jiffies + interval * HZ);
399 }
400 
401 static __inline__ void
402 qla2x00_stop_timer(scsi_qla_host_t *vha)
403 {
404 	del_timer_sync(&vha->timer);
405 	vha->timer_active = 0;
406 }
407 
408 static int qla2x00_do_dpc(void *data);
409 
410 static void qla2x00_rst_aen(scsi_qla_host_t *);
411 
412 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
413 	struct req_que **, struct rsp_que **);
414 static void qla2x00_free_fw_dump(struct qla_hw_data *);
415 static void qla2x00_mem_free(struct qla_hw_data *);
416 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
417 	struct qla_qpair *qpair);
418 
419 /* -------------------------------------------------------------------------- */
420 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
421     struct rsp_que *rsp)
422 {
423 	struct qla_hw_data *ha = vha->hw;
424 
425 	rsp->qpair = ha->base_qpair;
426 	rsp->req = req;
427 	ha->base_qpair->hw = ha;
428 	ha->base_qpair->req = req;
429 	ha->base_qpair->rsp = rsp;
430 	ha->base_qpair->vha = vha;
431 	ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
432 	ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
433 	ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
434 	ha->base_qpair->srb_mempool = ha->srb_mempool;
435 	INIT_LIST_HEAD(&ha->base_qpair->hints_list);
436 	INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
437 	ha->base_qpair->enable_class_2 = ql2xenableclass2;
438 	/* init qpair to this cpu. Will adjust at run time. */
439 	qla_cpu_update(rsp->qpair, raw_smp_processor_id());
440 	ha->base_qpair->pdev = ha->pdev;
441 
442 	if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
443 		ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
444 }
445 
446 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
447 				struct rsp_que *rsp)
448 {
449 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
450 
451 	ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
452 				GFP_KERNEL);
453 	if (!ha->req_q_map) {
454 		ql_log(ql_log_fatal, vha, 0x003b,
455 		    "Unable to allocate memory for request queue ptrs.\n");
456 		goto fail_req_map;
457 	}
458 
459 	ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
460 				GFP_KERNEL);
461 	if (!ha->rsp_q_map) {
462 		ql_log(ql_log_fatal, vha, 0x003c,
463 		    "Unable to allocate memory for response queue ptrs.\n");
464 		goto fail_rsp_map;
465 	}
466 
467 	ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
468 	if (ha->base_qpair == NULL) {
469 		ql_log(ql_log_warn, vha, 0x00e0,
470 		    "Failed to allocate base queue pair memory.\n");
471 		goto fail_base_qpair;
472 	}
473 
474 	qla_init_base_qpair(vha, req, rsp);
475 
476 	if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
477 		ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
478 			GFP_KERNEL);
479 		if (!ha->queue_pair_map) {
480 			ql_log(ql_log_fatal, vha, 0x0180,
481 			    "Unable to allocate memory for queue pair ptrs.\n");
482 			goto fail_qpair_map;
483 		}
484 		if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
485 			kfree(ha->queue_pair_map);
486 			ha->queue_pair_map = NULL;
487 			goto fail_qpair_map;
488 		}
489 	}
490 
491 	/*
492 	 * Make sure we record at least the request and response queue zero in
493 	 * case we need to free them if part of the probe fails.
494 	 */
495 	ha->rsp_q_map[0] = rsp;
496 	ha->req_q_map[0] = req;
497 	set_bit(0, ha->rsp_qid_map);
498 	set_bit(0, ha->req_qid_map);
499 	return 0;
500 
501 fail_qpair_map:
502 	kfree(ha->base_qpair);
503 	ha->base_qpair = NULL;
504 fail_base_qpair:
505 	kfree(ha->rsp_q_map);
506 	ha->rsp_q_map = NULL;
507 fail_rsp_map:
508 	kfree(ha->req_q_map);
509 	ha->req_q_map = NULL;
510 fail_req_map:
511 	return -ENOMEM;
512 }
513 
514 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
515 {
516 	if (IS_QLAFX00(ha)) {
517 		if (req && req->ring_fx00)
518 			dma_free_coherent(&ha->pdev->dev,
519 			    (req->length_fx00 + 1) * sizeof(request_t),
520 			    req->ring_fx00, req->dma_fx00);
521 	} else if (req && req->ring)
522 		dma_free_coherent(&ha->pdev->dev,
523 		(req->length + 1) * sizeof(request_t),
524 		req->ring, req->dma);
525 
526 	if (req)
527 		kfree(req->outstanding_cmds);
528 
529 	kfree(req);
530 }
531 
532 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
533 {
534 	if (IS_QLAFX00(ha)) {
535 		if (rsp && rsp->ring_fx00)
536 			dma_free_coherent(&ha->pdev->dev,
537 			    (rsp->length_fx00 + 1) * sizeof(request_t),
538 			    rsp->ring_fx00, rsp->dma_fx00);
539 	} else if (rsp && rsp->ring) {
540 		dma_free_coherent(&ha->pdev->dev,
541 		(rsp->length + 1) * sizeof(response_t),
542 		rsp->ring, rsp->dma);
543 	}
544 	kfree(rsp);
545 }
546 
547 static void qla2x00_free_queues(struct qla_hw_data *ha)
548 {
549 	struct req_que *req;
550 	struct rsp_que *rsp;
551 	int cnt;
552 	unsigned long flags;
553 
554 	if (ha->queue_pair_map) {
555 		kfree(ha->queue_pair_map);
556 		ha->queue_pair_map = NULL;
557 	}
558 	if (ha->base_qpair) {
559 		kfree(ha->base_qpair);
560 		ha->base_qpair = NULL;
561 	}
562 
563 	qla_mapq_free_qp_cpu_map(ha);
564 	spin_lock_irqsave(&ha->hardware_lock, flags);
565 	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
566 		if (!test_bit(cnt, ha->req_qid_map))
567 			continue;
568 
569 		req = ha->req_q_map[cnt];
570 		clear_bit(cnt, ha->req_qid_map);
571 		ha->req_q_map[cnt] = NULL;
572 
573 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
574 		qla2x00_free_req_que(ha, req);
575 		spin_lock_irqsave(&ha->hardware_lock, flags);
576 	}
577 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
578 
579 	kfree(ha->req_q_map);
580 	ha->req_q_map = NULL;
581 
582 
583 	spin_lock_irqsave(&ha->hardware_lock, flags);
584 	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
585 		if (!test_bit(cnt, ha->rsp_qid_map))
586 			continue;
587 
588 		rsp = ha->rsp_q_map[cnt];
589 		clear_bit(cnt, ha->rsp_qid_map);
590 		ha->rsp_q_map[cnt] =  NULL;
591 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
592 		qla2x00_free_rsp_que(ha, rsp);
593 		spin_lock_irqsave(&ha->hardware_lock, flags);
594 	}
595 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
596 
597 	kfree(ha->rsp_q_map);
598 	ha->rsp_q_map = NULL;
599 }
600 
601 static char *
602 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
603 {
604 	struct qla_hw_data *ha = vha->hw;
605 	static const char *const pci_bus_modes[] = {
606 		"33", "66", "100", "133",
607 	};
608 	uint16_t pci_bus;
609 
610 	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
611 	if (pci_bus) {
612 		snprintf(str, str_len, "PCI-X (%s MHz)",
613 			 pci_bus_modes[pci_bus]);
614 	} else {
615 		pci_bus = (ha->pci_attr & BIT_8) >> 8;
616 		snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
617 	}
618 
619 	return str;
620 }
621 
622 static char *
623 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
624 {
625 	static const char *const pci_bus_modes[] = {
626 		"33", "66", "100", "133",
627 	};
628 	struct qla_hw_data *ha = vha->hw;
629 	uint32_t pci_bus;
630 
631 	if (pci_is_pcie(ha->pdev)) {
632 		uint32_t lstat, lspeed, lwidth;
633 		const char *speed_str;
634 
635 		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
636 		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
637 		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
638 
639 		switch (lspeed) {
640 		case 1:
641 			speed_str = "2.5GT/s";
642 			break;
643 		case 2:
644 			speed_str = "5.0GT/s";
645 			break;
646 		case 3:
647 			speed_str = "8.0GT/s";
648 			break;
649 		case 4:
650 			speed_str = "16.0GT/s";
651 			break;
652 		default:
653 			speed_str = "<unknown>";
654 			break;
655 		}
656 		snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
657 
658 		return str;
659 	}
660 
661 	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
662 	if (pci_bus == 0 || pci_bus == 8)
663 		snprintf(str, str_len, "PCI (%s MHz)",
664 			 pci_bus_modes[pci_bus >> 3]);
665 	else
666 		snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
667 			 pci_bus & 4 ? 2 : 1,
668 			 pci_bus_modes[pci_bus & 3]);
669 
670 	return str;
671 }
672 
673 static char *
674 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
675 {
676 	char un_str[10];
677 	struct qla_hw_data *ha = vha->hw;
678 
679 	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
680 	    ha->fw_minor_version, ha->fw_subminor_version);
681 
682 	if (ha->fw_attributes & BIT_9) {
683 		strcat(str, "FLX");
684 		return (str);
685 	}
686 
687 	switch (ha->fw_attributes & 0xFF) {
688 	case 0x7:
689 		strcat(str, "EF");
690 		break;
691 	case 0x17:
692 		strcat(str, "TP");
693 		break;
694 	case 0x37:
695 		strcat(str, "IP");
696 		break;
697 	case 0x77:
698 		strcat(str, "VI");
699 		break;
700 	default:
701 		sprintf(un_str, "(%x)", ha->fw_attributes);
702 		strcat(str, un_str);
703 		break;
704 	}
705 	if (ha->fw_attributes & 0x100)
706 		strcat(str, "X");
707 
708 	return (str);
709 }
710 
711 static char *
712 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
713 {
714 	struct qla_hw_data *ha = vha->hw;
715 
716 	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
717 	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
718 	return str;
719 }
720 
721 void qla2x00_sp_free_dma(srb_t *sp)
722 {
723 	struct qla_hw_data *ha = sp->vha->hw;
724 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
725 
726 	if (sp->flags & SRB_DMA_VALID) {
727 		scsi_dma_unmap(cmd);
728 		sp->flags &= ~SRB_DMA_VALID;
729 	}
730 
731 	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
732 		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
733 		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
734 		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
735 	}
736 
737 	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
738 		/* List assured to be having elements */
739 		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
740 		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
741 	}
742 
743 	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
744 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
745 
746 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
747 		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
748 	}
749 
750 	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
751 		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
752 
753 		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
754 		    ctx1->fcp_cmnd_dma);
755 		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
756 		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
757 		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
758 	}
759 
760 	if (sp->flags & SRB_GOT_BUF)
761 		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
762 }
763 
764 void qla2x00_sp_compl(srb_t *sp, int res)
765 {
766 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
767 	struct completion *comp = sp->comp;
768 
769 	/* kref: INIT */
770 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
771 	cmd->result = res;
772 	sp->type = 0;
773 	scsi_done(cmd);
774 	if (comp)
775 		complete(comp);
776 }
777 
778 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
779 {
780 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
781 	struct qla_hw_data *ha = sp->fcport->vha->hw;
782 
783 	if (sp->flags & SRB_DMA_VALID) {
784 		scsi_dma_unmap(cmd);
785 		sp->flags &= ~SRB_DMA_VALID;
786 	}
787 
788 	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
789 		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
790 		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
791 		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
792 	}
793 
794 	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
795 		/* List assured to be having elements */
796 		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
797 		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
798 	}
799 
800 	if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
801 		struct crc_context *difctx = sp->u.scmd.crc_ctx;
802 		struct dsd_dma *dif_dsd, *nxt_dsd;
803 
804 		list_for_each_entry_safe(dif_dsd, nxt_dsd,
805 		    &difctx->ldif_dma_hndl_list, list) {
806 			list_del(&dif_dsd->list);
807 			dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
808 			    dif_dsd->dsd_list_dma);
809 			kfree(dif_dsd);
810 			difctx->no_dif_bundl--;
811 		}
812 
813 		list_for_each_entry_safe(dif_dsd, nxt_dsd,
814 		    &difctx->ldif_dsd_list, list) {
815 			list_del(&dif_dsd->list);
816 			dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
817 			    dif_dsd->dsd_list_dma);
818 			kfree(dif_dsd);
819 			difctx->no_ldif_dsd--;
820 		}
821 
822 		if (difctx->no_ldif_dsd) {
823 			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
824 			    "%s: difctx->no_ldif_dsd=%x\n",
825 			    __func__, difctx->no_ldif_dsd);
826 		}
827 
828 		if (difctx->no_dif_bundl) {
829 			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
830 			    "%s: difctx->no_dif_bundl=%x\n",
831 			    __func__, difctx->no_dif_bundl);
832 		}
833 		sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
834 	}
835 
836 	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
837 		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
838 
839 		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
840 		    ctx1->fcp_cmnd_dma);
841 		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
842 		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
843 		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
844 		sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
845 	}
846 
847 	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
848 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
849 
850 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
851 		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
852 	}
853 
854 	if (sp->flags & SRB_GOT_BUF)
855 		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
856 }
857 
858 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
859 {
860 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
861 	struct completion *comp = sp->comp;
862 
863 	/* ref: INIT */
864 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
865 	cmd->result = res;
866 	sp->type = 0;
867 	scsi_done(cmd);
868 	if (comp)
869 		complete(comp);
870 }
871 
872 static int
873 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
874 {
875 	scsi_qla_host_t *vha = shost_priv(host);
876 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
877 	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
878 	struct qla_hw_data *ha = vha->hw;
879 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
880 	srb_t *sp;
881 	int rval;
882 
883 	if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
884 	    WARN_ON_ONCE(!rport)) {
885 		cmd->result = DID_NO_CONNECT << 16;
886 		goto qc24_fail_command;
887 	}
888 
889 	if (ha->mqenable) {
890 		uint32_t tag;
891 		uint16_t hwq;
892 		struct qla_qpair *qpair = NULL;
893 
894 		tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
895 		hwq = blk_mq_unique_tag_to_hwq(tag);
896 		qpair = ha->queue_pair_map[hwq];
897 
898 		if (qpair)
899 			return qla2xxx_mqueuecommand(host, cmd, qpair);
900 	}
901 
902 	if (ha->flags.eeh_busy) {
903 		if (ha->flags.pci_channel_io_perm_failure) {
904 			ql_dbg(ql_dbg_aer, vha, 0x9010,
905 			    "PCI Channel IO permanent failure, exiting "
906 			    "cmd=%p.\n", cmd);
907 			cmd->result = DID_NO_CONNECT << 16;
908 		} else {
909 			ql_dbg(ql_dbg_aer, vha, 0x9011,
910 			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
911 			cmd->result = DID_REQUEUE << 16;
912 		}
913 		goto qc24_fail_command;
914 	}
915 
916 	rval = fc_remote_port_chkready(rport);
917 	if (rval) {
918 		cmd->result = rval;
919 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
920 		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
921 		    cmd, rval);
922 		goto qc24_fail_command;
923 	}
924 
925 	if (!vha->flags.difdix_supported &&
926 		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
927 			ql_dbg(ql_dbg_io, vha, 0x3004,
928 			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
929 			    cmd);
930 			cmd->result = DID_NO_CONNECT << 16;
931 			goto qc24_fail_command;
932 	}
933 
934 	if (!fcport || fcport->deleted) {
935 		cmd->result = DID_IMM_RETRY << 16;
936 		goto qc24_fail_command;
937 	}
938 
939 	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
940 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
941 			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
942 			ql_dbg(ql_dbg_io, vha, 0x3005,
943 			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
944 			    atomic_read(&fcport->state),
945 			    atomic_read(&base_vha->loop_state));
946 			cmd->result = DID_NO_CONNECT << 16;
947 			goto qc24_fail_command;
948 		}
949 		goto qc24_target_busy;
950 	}
951 
952 	/*
953 	 * Return target busy if we've received a non-zero retry_delay_timer
954 	 * in a FCP_RSP.
955 	 */
956 	if (fcport->retry_delay_timestamp == 0) {
957 		/* retry delay not set */
958 	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
959 		fcport->retry_delay_timestamp = 0;
960 	else
961 		goto qc24_target_busy;
962 
963 	sp = scsi_cmd_priv(cmd);
964 	/* ref: INIT */
965 	qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
966 
967 	sp->u.scmd.cmd = cmd;
968 	sp->type = SRB_SCSI_CMD;
969 	sp->free = qla2x00_sp_free_dma;
970 	sp->done = qla2x00_sp_compl;
971 
972 	rval = ha->isp_ops->start_scsi(sp);
973 	if (rval != QLA_SUCCESS) {
974 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
975 		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
976 		goto qc24_host_busy_free_sp;
977 	}
978 
979 	return 0;
980 
981 qc24_host_busy_free_sp:
982 	/* ref: INIT */
983 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
984 
985 qc24_target_busy:
986 	return SCSI_MLQUEUE_TARGET_BUSY;
987 
988 qc24_fail_command:
989 	scsi_done(cmd);
990 
991 	return 0;
992 }
993 
994 /* For MQ supported I/O */
995 int
996 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
997     struct qla_qpair *qpair)
998 {
999 	scsi_qla_host_t *vha = shost_priv(host);
1000 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1001 	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
1002 	struct qla_hw_data *ha = vha->hw;
1003 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1004 	srb_t *sp;
1005 	int rval;
1006 
1007 	rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
1008 	if (rval) {
1009 		cmd->result = rval;
1010 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1011 		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1012 		    cmd, rval);
1013 		goto qc24_fail_command;
1014 	}
1015 
1016 	if (!qpair->online) {
1017 		ql_dbg(ql_dbg_io, vha, 0x3077,
1018 		       "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1019 		cmd->result = DID_NO_CONNECT << 16;
1020 		goto qc24_fail_command;
1021 	}
1022 
1023 	if (!fcport || fcport->deleted) {
1024 		cmd->result = DID_IMM_RETRY << 16;
1025 		goto qc24_fail_command;
1026 	}
1027 
1028 	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1029 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1030 			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1031 			ql_dbg(ql_dbg_io, vha, 0x3077,
1032 			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
1033 			    atomic_read(&fcport->state),
1034 			    atomic_read(&base_vha->loop_state));
1035 			cmd->result = DID_NO_CONNECT << 16;
1036 			goto qc24_fail_command;
1037 		}
1038 		goto qc24_target_busy;
1039 	}
1040 
1041 	/*
1042 	 * Return target busy if we've received a non-zero retry_delay_timer
1043 	 * in a FCP_RSP.
1044 	 */
1045 	if (fcport->retry_delay_timestamp == 0) {
1046 		/* retry delay not set */
1047 	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
1048 		fcport->retry_delay_timestamp = 0;
1049 	else
1050 		goto qc24_target_busy;
1051 
1052 	sp = scsi_cmd_priv(cmd);
1053 	/* ref: INIT */
1054 	qla2xxx_init_sp(sp, vha, qpair, fcport);
1055 
1056 	sp->u.scmd.cmd = cmd;
1057 	sp->type = SRB_SCSI_CMD;
1058 	sp->free = qla2xxx_qpair_sp_free_dma;
1059 	sp->done = qla2xxx_qpair_sp_compl;
1060 
1061 	rval = ha->isp_ops->start_scsi_mq(sp);
1062 	if (rval != QLA_SUCCESS) {
1063 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1064 		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1065 		goto qc24_host_busy_free_sp;
1066 	}
1067 
1068 	return 0;
1069 
1070 qc24_host_busy_free_sp:
1071 	/* ref: INIT */
1072 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
1073 
1074 qc24_target_busy:
1075 	return SCSI_MLQUEUE_TARGET_BUSY;
1076 
1077 qc24_fail_command:
1078 	scsi_done(cmd);
1079 
1080 	return 0;
1081 }
1082 
1083 /*
1084  * qla2x00_wait_for_hba_online
1085  *    Wait till the HBA is online after going through
1086  *    <= MAX_RETRIES_OF_ISP_ABORT  or
1087  *    finally HBA is disabled ie marked offline
1088  *
1089  * Input:
1090  *     ha - pointer to host adapter structure
1091  *
1092  * Note:
1093  *    Does context switching-Release SPIN_LOCK
1094  *    (if any) before calling this routine.
1095  *
1096  * Return:
1097  *    Success (Adapter is online) : 0
1098  *    Failed  (Adapter is offline/disabled) : 1
1099  */
1100 int
1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1102 {
1103 	int		return_status;
1104 	unsigned long	wait_online;
1105 	struct qla_hw_data *ha = vha->hw;
1106 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1107 
1108 	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1109 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1110 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1111 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1112 	    ha->dpc_active) && time_before(jiffies, wait_online)) {
1113 
1114 		msleep(1000);
1115 	}
1116 	if (base_vha->flags.online)
1117 		return_status = QLA_SUCCESS;
1118 	else
1119 		return_status = QLA_FUNCTION_FAILED;
1120 
1121 	return (return_status);
1122 }
1123 
1124 static inline int test_fcport_count(scsi_qla_host_t *vha)
1125 {
1126 	struct qla_hw_data *ha = vha->hw;
1127 	unsigned long flags;
1128 	int res;
1129 	/* Return 0 = sleep, x=wake */
1130 
1131 	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1132 	ql_dbg(ql_dbg_init, vha, 0x00ec,
1133 	    "tgt %p, fcport_count=%d\n",
1134 	    vha, vha->fcport_count);
1135 	res = (vha->fcport_count == 0);
1136 	if  (res) {
1137 		struct fc_port *fcport;
1138 
1139 		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1140 			if (fcport->deleted != QLA_SESS_DELETED) {
1141 				/* session(s) may not be fully logged in
1142 				 * (ie fcport_count=0), but session
1143 				 * deletion thread(s) may be inflight.
1144 				 */
1145 
1146 				res = 0;
1147 				break;
1148 			}
1149 		}
1150 	}
1151 	spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1152 
1153 	return res;
1154 }
1155 
1156 /*
1157  * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1158  * it has dependency on UNLOADING flag to stop device discovery
1159  */
1160 void
1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1162 {
1163 	u8 i;
1164 
1165 	qla2x00_mark_all_devices_lost(vha);
1166 
1167 	for (i = 0; i < 10; i++) {
1168 		if (wait_event_timeout(vha->fcport_waitQ,
1169 		    test_fcport_count(vha), HZ) > 0)
1170 			break;
1171 	}
1172 
1173 	flush_workqueue(vha->hw->wq);
1174 }
1175 
1176 /*
1177  * qla2x00_wait_for_hba_ready
1178  * Wait till the HBA is ready before doing driver unload
1179  *
1180  * Input:
1181  *     ha - pointer to host adapter structure
1182  *
1183  * Note:
1184  *    Does context switching-Release SPIN_LOCK
1185  *    (if any) before calling this routine.
1186  *
1187  */
1188 static void
1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1190 {
1191 	struct qla_hw_data *ha = vha->hw;
1192 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193 
1194 	while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1195 		ha->flags.mbox_busy) ||
1196 	       test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1197 	       test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1198 		if (test_bit(UNLOADING, &base_vha->dpc_flags))
1199 			break;
1200 		msleep(1000);
1201 	}
1202 }
1203 
1204 int
1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1206 {
1207 	int		return_status;
1208 	unsigned long	wait_reset;
1209 	struct qla_hw_data *ha = vha->hw;
1210 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1211 
1212 	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1213 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1214 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1215 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1216 	    ha->dpc_active) && time_before(jiffies, wait_reset)) {
1217 
1218 		msleep(1000);
1219 
1220 		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1221 		    ha->flags.chip_reset_done)
1222 			break;
1223 	}
1224 	if (ha->flags.chip_reset_done)
1225 		return_status = QLA_SUCCESS;
1226 	else
1227 		return_status = QLA_FUNCTION_FAILED;
1228 
1229 	return return_status;
1230 }
1231 
1232 /**************************************************************************
1233 * qla2xxx_eh_abort
1234 *
1235 * Description:
1236 *    The abort function will abort the specified command.
1237 *
1238 * Input:
1239 *    cmd = Linux SCSI command packet to be aborted.
1240 *
1241 * Returns:
1242 *    Either SUCCESS or FAILED.
1243 *
1244 * Note:
1245 *    Only return FAILED if command not returned by firmware.
1246 **************************************************************************/
1247 static int
1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1249 {
1250 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1251 	DECLARE_COMPLETION_ONSTACK(comp);
1252 	srb_t *sp;
1253 	int ret;
1254 	unsigned int id;
1255 	uint64_t lun;
1256 	int rval;
1257 	struct qla_hw_data *ha = vha->hw;
1258 	uint32_t ratov_j;
1259 	struct qla_qpair *qpair;
1260 	unsigned long flags;
1261 	int fast_fail_status = SUCCESS;
1262 
1263 	if (qla2x00_isp_reg_stat(ha)) {
1264 		ql_log(ql_log_info, vha, 0x8042,
1265 		    "PCI/Register disconnect, exiting.\n");
1266 		qla_pci_set_eeh_busy(vha);
1267 		return FAILED;
1268 	}
1269 
1270 	/* Save any FAST_IO_FAIL value to return later if abort succeeds */
1271 	ret = fc_block_scsi_eh(cmd);
1272 	if (ret != 0)
1273 		fast_fail_status = ret;
1274 
1275 	sp = scsi_cmd_priv(cmd);
1276 	qpair = sp->qpair;
1277 
1278 	vha->cmd_timeout_cnt++;
1279 
1280 	if ((sp->fcport && sp->fcport->deleted) || !qpair)
1281 		return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1282 
1283 	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1284 	sp->comp = &comp;
1285 	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1286 
1287 
1288 	id = cmd->device->id;
1289 	lun = cmd->device->lun;
1290 
1291 	ql_dbg(ql_dbg_taskm, vha, 0x8002,
1292 	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1293 	    vha->host_no, id, lun, sp, cmd, sp->handle);
1294 
1295 	/*
1296 	 * Abort will release the original Command/sp from FW. Let the
1297 	 * original command call scsi_done. In return, he will wakeup
1298 	 * this sleeping thread.
1299 	 */
1300 	rval = ha->isp_ops->abort_command(sp);
1301 
1302 	ql_dbg(ql_dbg_taskm, vha, 0x8003,
1303 	       "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1304 
1305 	/* Wait for the command completion. */
1306 	ratov_j = ha->r_a_tov/10 * 4 * 1000;
1307 	ratov_j = msecs_to_jiffies(ratov_j);
1308 	switch (rval) {
1309 	case QLA_SUCCESS:
1310 		if (!wait_for_completion_timeout(&comp, ratov_j)) {
1311 			ql_dbg(ql_dbg_taskm, vha, 0xffff,
1312 			    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1313 			    __func__, ha->r_a_tov/10);
1314 			ret = FAILED;
1315 		} else {
1316 			ret = fast_fail_status;
1317 		}
1318 		break;
1319 	default:
1320 		ret = FAILED;
1321 		break;
1322 	}
1323 
1324 	sp->comp = NULL;
1325 
1326 	ql_log(ql_log_info, vha, 0x801c,
1327 	    "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1328 	    vha->host_no, id, lun, ret);
1329 
1330 	return ret;
1331 }
1332 
1333 #define ABORT_POLLING_PERIOD	1000
1334 #define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
1335 
1336 /*
1337  * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1338  */
1339 static int
1340 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1341 				       uint64_t l, enum nexus_wait_type type)
1342 {
1343 	int cnt, match, status;
1344 	unsigned long flags;
1345 	scsi_qla_host_t *vha = qpair->vha;
1346 	struct req_que *req = qpair->req;
1347 	srb_t *sp;
1348 	struct scsi_cmnd *cmd;
1349 	unsigned long wait_iter = ABORT_WAIT_ITER;
1350 	bool found;
1351 	struct qla_hw_data *ha = vha->hw;
1352 
1353 	status = QLA_SUCCESS;
1354 
1355 	while (wait_iter--) {
1356 		found = false;
1357 
1358 		spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1359 		for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1360 			sp = req->outstanding_cmds[cnt];
1361 			if (!sp)
1362 				continue;
1363 			if (sp->type != SRB_SCSI_CMD)
1364 				continue;
1365 			if (vha->vp_idx != sp->vha->vp_idx)
1366 				continue;
1367 			match = 0;
1368 			cmd = GET_CMD_SP(sp);
1369 			switch (type) {
1370 			case WAIT_HOST:
1371 				match = 1;
1372 				break;
1373 			case WAIT_TARGET:
1374 				if (sp->fcport)
1375 					match = sp->fcport->d_id.b24 == t;
1376 				else
1377 					match = 0;
1378 				break;
1379 			case WAIT_LUN:
1380 				if (sp->fcport)
1381 					match = (sp->fcport->d_id.b24 == t &&
1382 						cmd->device->lun == l);
1383 				else
1384 					match = 0;
1385 				break;
1386 			}
1387 			if (!match)
1388 				continue;
1389 
1390 			spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1391 
1392 			if (unlikely(pci_channel_offline(ha->pdev)) ||
1393 			    ha->flags.eeh_busy) {
1394 				ql_dbg(ql_dbg_taskm, vha, 0x8005,
1395 				    "Return:eh_wait.\n");
1396 				return status;
1397 			}
1398 
1399 			/*
1400 			 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1401 			 * it means scsi_done has not called. Wait for it to
1402 			 * clear from outstanding_cmds.
1403 			 */
1404 			msleep(ABORT_POLLING_PERIOD);
1405 			spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1406 			found = true;
1407 		}
1408 		spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1409 
1410 		if (!found)
1411 			break;
1412 	}
1413 
1414 	if (wait_iter == -1)
1415 		status = QLA_FUNCTION_FAILED;
1416 
1417 	return status;
1418 }
1419 
1420 int
1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1422 				     uint64_t l, enum nexus_wait_type type)
1423 {
1424 	struct qla_qpair *qpair;
1425 	struct qla_hw_data *ha = vha->hw;
1426 	int i, status = QLA_SUCCESS;
1427 
1428 	status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1429 							type);
1430 	for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1431 		qpair = ha->queue_pair_map[i];
1432 		if (!qpair)
1433 			continue;
1434 		status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1435 								type);
1436 	}
1437 	return status;
1438 }
1439 
1440 static char *reset_errors[] = {
1441 	"HBA not online",
1442 	"HBA not ready",
1443 	"Task management failed",
1444 	"Waiting for command completions",
1445 };
1446 
1447 static int
1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1449 {
1450 	struct scsi_device *sdev = cmd->device;
1451 	scsi_qla_host_t *vha = shost_priv(sdev->host);
1452 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1453 	fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1454 	struct qla_hw_data *ha = vha->hw;
1455 	int err;
1456 
1457 	if (qla2x00_isp_reg_stat(ha)) {
1458 		ql_log(ql_log_info, vha, 0x803e,
1459 		    "PCI/Register disconnect, exiting.\n");
1460 		qla_pci_set_eeh_busy(vha);
1461 		return FAILED;
1462 	}
1463 
1464 	if (!fcport) {
1465 		return FAILED;
1466 	}
1467 
1468 	err = fc_block_rport(rport);
1469 	if (err != 0)
1470 		return err;
1471 
1472 	if (fcport->deleted)
1473 		return FAILED;
1474 
1475 	ql_log(ql_log_info, vha, 0x8009,
1476 	    "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1477 	    sdev->id, sdev->lun, cmd);
1478 
1479 	err = 0;
1480 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1481 		ql_log(ql_log_warn, vha, 0x800a,
1482 		    "Wait for hba online failed for cmd=%p.\n", cmd);
1483 		goto eh_reset_failed;
1484 	}
1485 	err = 2;
1486 	if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1487 		!= QLA_SUCCESS) {
1488 		ql_log(ql_log_warn, vha, 0x800c,
1489 		    "do_reset failed for cmd=%p.\n", cmd);
1490 		goto eh_reset_failed;
1491 	}
1492 	err = 3;
1493 	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1494 						 cmd->device->lun,
1495 						 WAIT_LUN) != QLA_SUCCESS) {
1496 		ql_log(ql_log_warn, vha, 0x800d,
1497 		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1498 		goto eh_reset_failed;
1499 	}
1500 
1501 	ql_log(ql_log_info, vha, 0x800e,
1502 	    "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1503 	    vha->host_no, sdev->id, sdev->lun, cmd);
1504 
1505 	return SUCCESS;
1506 
1507 eh_reset_failed:
1508 	ql_log(ql_log_info, vha, 0x800f,
1509 	    "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1510 	    reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1511 	    cmd);
1512 	vha->reset_cmd_err_cnt++;
1513 	return FAILED;
1514 }
1515 
1516 static int
1517 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1518 {
1519 	struct scsi_device *sdev = cmd->device;
1520 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1521 	scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1522 	struct qla_hw_data *ha = vha->hw;
1523 	fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1524 	int err;
1525 
1526 	if (qla2x00_isp_reg_stat(ha)) {
1527 		ql_log(ql_log_info, vha, 0x803f,
1528 		    "PCI/Register disconnect, exiting.\n");
1529 		qla_pci_set_eeh_busy(vha);
1530 		return FAILED;
1531 	}
1532 
1533 	if (!fcport) {
1534 		return FAILED;
1535 	}
1536 
1537 	err = fc_block_rport(rport);
1538 	if (err != 0)
1539 		return err;
1540 
1541 	if (fcport->deleted)
1542 		return FAILED;
1543 
1544 	ql_log(ql_log_info, vha, 0x8009,
1545 	    "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1546 	    sdev->id, cmd);
1547 
1548 	err = 0;
1549 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1550 		ql_log(ql_log_warn, vha, 0x800a,
1551 		    "Wait for hba online failed for cmd=%p.\n", cmd);
1552 		goto eh_reset_failed;
1553 	}
1554 	err = 2;
1555 	if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1556 		ql_log(ql_log_warn, vha, 0x800c,
1557 		    "target_reset failed for cmd=%p.\n", cmd);
1558 		goto eh_reset_failed;
1559 	}
1560 	err = 3;
1561 	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1562 						 WAIT_TARGET) != QLA_SUCCESS) {
1563 		ql_log(ql_log_warn, vha, 0x800d,
1564 		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1565 		goto eh_reset_failed;
1566 	}
1567 
1568 	ql_log(ql_log_info, vha, 0x800e,
1569 	    "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1570 	    vha->host_no, sdev->id, cmd);
1571 
1572 	return SUCCESS;
1573 
1574 eh_reset_failed:
1575 	ql_log(ql_log_info, vha, 0x800f,
1576 	    "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1577 	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1578 	    cmd);
1579 	vha->reset_cmd_err_cnt++;
1580 	return FAILED;
1581 }
1582 
1583 /**************************************************************************
1584 * qla2xxx_eh_bus_reset
1585 *
1586 * Description:
1587 *    The bus reset function will reset the bus and abort any executing
1588 *    commands.
1589 *
1590 * Input:
1591 *    cmd = Linux SCSI command packet of the command that cause the
1592 *          bus reset.
1593 *
1594 * Returns:
1595 *    SUCCESS/FAILURE (defined as macro in scsi.h).
1596 *
1597 **************************************************************************/
1598 static int
1599 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1600 {
1601 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1602 	int ret = FAILED;
1603 	unsigned int id;
1604 	uint64_t lun;
1605 	struct qla_hw_data *ha = vha->hw;
1606 
1607 	if (qla2x00_isp_reg_stat(ha)) {
1608 		ql_log(ql_log_info, vha, 0x8040,
1609 		    "PCI/Register disconnect, exiting.\n");
1610 		qla_pci_set_eeh_busy(vha);
1611 		return FAILED;
1612 	}
1613 
1614 	id = cmd->device->id;
1615 	lun = cmd->device->lun;
1616 
1617 	if (qla2x00_chip_is_down(vha))
1618 		return ret;
1619 
1620 	ql_log(ql_log_info, vha, 0x8012,
1621 	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1622 
1623 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1624 		ql_log(ql_log_fatal, vha, 0x8013,
1625 		    "Wait for hba online failed board disabled.\n");
1626 		goto eh_bus_reset_done;
1627 	}
1628 
1629 	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1630 		ret = SUCCESS;
1631 
1632 	if (ret == FAILED)
1633 		goto eh_bus_reset_done;
1634 
1635 	/* Flush outstanding commands. */
1636 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1637 	    QLA_SUCCESS) {
1638 		ql_log(ql_log_warn, vha, 0x8014,
1639 		    "Wait for pending commands failed.\n");
1640 		ret = FAILED;
1641 	}
1642 
1643 eh_bus_reset_done:
1644 	ql_log(ql_log_warn, vha, 0x802b,
1645 	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
1646 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1647 
1648 	return ret;
1649 }
1650 
1651 /**************************************************************************
1652 * qla2xxx_eh_host_reset
1653 *
1654 * Description:
1655 *    The reset function will reset the Adapter.
1656 *
1657 * Input:
1658 *      cmd = Linux SCSI command packet of the command that cause the
1659 *            adapter reset.
1660 *
1661 * Returns:
1662 *      Either SUCCESS or FAILED.
1663 *
1664 * Note:
1665 **************************************************************************/
1666 static int
1667 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1668 {
1669 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1670 	struct qla_hw_data *ha = vha->hw;
1671 	int ret = FAILED;
1672 	unsigned int id;
1673 	uint64_t lun;
1674 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1675 
1676 	if (qla2x00_isp_reg_stat(ha)) {
1677 		ql_log(ql_log_info, vha, 0x8041,
1678 		    "PCI/Register disconnect, exiting.\n");
1679 		qla_pci_set_eeh_busy(vha);
1680 		return SUCCESS;
1681 	}
1682 
1683 	id = cmd->device->id;
1684 	lun = cmd->device->lun;
1685 
1686 	ql_log(ql_log_info, vha, 0x8018,
1687 	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1688 
1689 	/*
1690 	 * No point in issuing another reset if one is active.  Also do not
1691 	 * attempt a reset if we are updating flash.
1692 	 */
1693 	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1694 		goto eh_host_reset_lock;
1695 
1696 	if (vha != base_vha) {
1697 		if (qla2x00_vp_abort_isp(vha))
1698 			goto eh_host_reset_lock;
1699 	} else {
1700 		if (IS_P3P_TYPE(vha->hw)) {
1701 			if (!qla82xx_fcoe_ctx_reset(vha)) {
1702 				/* Ctx reset success */
1703 				ret = SUCCESS;
1704 				goto eh_host_reset_lock;
1705 			}
1706 			/* fall thru if ctx reset failed */
1707 		}
1708 		if (ha->wq)
1709 			flush_workqueue(ha->wq);
1710 
1711 		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1712 		if (ha->isp_ops->abort_isp(base_vha)) {
1713 			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1714 			/* failed. schedule dpc to try */
1715 			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1716 
1717 			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1718 				ql_log(ql_log_warn, vha, 0x802a,
1719 				    "wait for hba online failed.\n");
1720 				goto eh_host_reset_lock;
1721 			}
1722 		}
1723 		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1724 	}
1725 
1726 	/* Waiting for command to be returned to OS.*/
1727 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1728 		QLA_SUCCESS)
1729 		ret = SUCCESS;
1730 
1731 eh_host_reset_lock:
1732 	ql_log(ql_log_info, vha, 0x8017,
1733 	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1734 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1735 
1736 	return ret;
1737 }
1738 
1739 /*
1740 * qla2x00_loop_reset
1741 *      Issue loop reset.
1742 *
1743 * Input:
1744 *      ha = adapter block pointer.
1745 *
1746 * Returns:
1747 *      0 = success
1748 */
1749 int
1750 qla2x00_loop_reset(scsi_qla_host_t *vha)
1751 {
1752 	int ret;
1753 	struct qla_hw_data *ha = vha->hw;
1754 
1755 	if (IS_QLAFX00(ha))
1756 		return QLA_SUCCESS;
1757 
1758 	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1759 		atomic_set(&vha->loop_state, LOOP_DOWN);
1760 		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1761 		qla2x00_mark_all_devices_lost(vha);
1762 		ret = qla2x00_full_login_lip(vha);
1763 		if (ret != QLA_SUCCESS) {
1764 			ql_dbg(ql_dbg_taskm, vha, 0x802d,
1765 			    "full_login_lip=%d.\n", ret);
1766 		}
1767 	}
1768 
1769 	if (ha->flags.enable_lip_reset) {
1770 		ret = qla2x00_lip_reset(vha);
1771 		if (ret != QLA_SUCCESS)
1772 			ql_dbg(ql_dbg_taskm, vha, 0x802e,
1773 			    "lip_reset failed (%d).\n", ret);
1774 	}
1775 
1776 	/* Issue marker command only when we are going to start the I/O */
1777 	vha->marker_needed = 1;
1778 
1779 	return QLA_SUCCESS;
1780 }
1781 
1782 /*
1783  * The caller must ensure that no completion interrupts will happen
1784  * while this function is in progress.
1785  */
1786 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1787 			      unsigned long *flags)
1788 	__releases(qp->qp_lock_ptr)
1789 	__acquires(qp->qp_lock_ptr)
1790 {
1791 	DECLARE_COMPLETION_ONSTACK(comp);
1792 	scsi_qla_host_t *vha = qp->vha;
1793 	struct qla_hw_data *ha = vha->hw;
1794 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1795 	int rval;
1796 	bool ret_cmd;
1797 	uint32_t ratov_j;
1798 
1799 	lockdep_assert_held(qp->qp_lock_ptr);
1800 
1801 	if (qla2x00_chip_is_down(vha)) {
1802 		sp->done(sp, res);
1803 		return;
1804 	}
1805 
1806 	if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1807 	    (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1808 	     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1809 	     !qla2x00_isp_reg_stat(ha))) {
1810 		if (sp->comp) {
1811 			sp->done(sp, res);
1812 			return;
1813 		}
1814 
1815 		sp->comp = &comp;
1816 		spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1817 
1818 		rval = ha->isp_ops->abort_command(sp);
1819 		/* Wait for command completion. */
1820 		ret_cmd = false;
1821 		ratov_j = ha->r_a_tov/10 * 4 * 1000;
1822 		ratov_j = msecs_to_jiffies(ratov_j);
1823 		switch (rval) {
1824 		case QLA_SUCCESS:
1825 			if (wait_for_completion_timeout(&comp, ratov_j)) {
1826 				ql_dbg(ql_dbg_taskm, vha, 0xffff,
1827 				    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1828 				    __func__, ha->r_a_tov/10);
1829 				ret_cmd = true;
1830 			}
1831 			/* else FW return SP to driver */
1832 			break;
1833 		default:
1834 			ret_cmd = true;
1835 			break;
1836 		}
1837 
1838 		spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1839 		if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1840 			sp->done(sp, res);
1841 	} else {
1842 		sp->done(sp, res);
1843 	}
1844 }
1845 
1846 /*
1847  * The caller must ensure that no completion interrupts will happen
1848  * while this function is in progress.
1849  */
1850 static void
1851 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1852 {
1853 	int cnt;
1854 	unsigned long flags;
1855 	srb_t *sp;
1856 	scsi_qla_host_t *vha = qp->vha;
1857 	struct qla_hw_data *ha = vha->hw;
1858 	struct req_que *req;
1859 	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1860 	struct qla_tgt_cmd *cmd;
1861 
1862 	if (!ha->req_q_map)
1863 		return;
1864 	spin_lock_irqsave(qp->qp_lock_ptr, flags);
1865 	req = qp->req;
1866 	for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1867 		sp = req->outstanding_cmds[cnt];
1868 		if (sp) {
1869 			/*
1870 			 * perform lockless completion during driver unload
1871 			 */
1872 			if (qla2x00_chip_is_down(vha)) {
1873 				req->outstanding_cmds[cnt] = NULL;
1874 				spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1875 				sp->done(sp, res);
1876 				spin_lock_irqsave(qp->qp_lock_ptr, flags);
1877 				continue;
1878 			}
1879 
1880 			switch (sp->cmd_type) {
1881 			case TYPE_SRB:
1882 				qla2x00_abort_srb(qp, sp, res, &flags);
1883 				break;
1884 			case TYPE_TGT_CMD:
1885 				if (!vha->hw->tgt.tgt_ops || !tgt ||
1886 				    qla_ini_mode_enabled(vha)) {
1887 					ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1888 					    "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1889 					    vha->dpc_flags);
1890 					continue;
1891 				}
1892 				cmd = (struct qla_tgt_cmd *)sp;
1893 				cmd->aborted = 1;
1894 				break;
1895 			case TYPE_TGT_TMCMD:
1896 				/* Skip task management functions. */
1897 				break;
1898 			default:
1899 				break;
1900 			}
1901 			req->outstanding_cmds[cnt] = NULL;
1902 		}
1903 	}
1904 	spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1905 }
1906 
1907 /*
1908  * The caller must ensure that no completion interrupts will happen
1909  * while this function is in progress.
1910  */
1911 void
1912 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1913 {
1914 	int que;
1915 	struct qla_hw_data *ha = vha->hw;
1916 
1917 	/* Continue only if initialization complete. */
1918 	if (!ha->base_qpair)
1919 		return;
1920 	__qla2x00_abort_all_cmds(ha->base_qpair, res);
1921 
1922 	if (!ha->queue_pair_map)
1923 		return;
1924 	for (que = 0; que < ha->max_qpairs; que++) {
1925 		if (!ha->queue_pair_map[que])
1926 			continue;
1927 
1928 		__qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1929 	}
1930 }
1931 
1932 static int
1933 qla2xxx_slave_alloc(struct scsi_device *sdev)
1934 {
1935 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1936 
1937 	if (!rport || fc_remote_port_chkready(rport))
1938 		return -ENXIO;
1939 
1940 	sdev->hostdata = *(fc_port_t **)rport->dd_data;
1941 
1942 	return 0;
1943 }
1944 
1945 static int
1946 qla2xxx_slave_configure(struct scsi_device *sdev)
1947 {
1948 	scsi_qla_host_t *vha = shost_priv(sdev->host);
1949 	struct req_que *req = vha->req;
1950 
1951 	if (IS_T10_PI_CAPABLE(vha->hw))
1952 		blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1953 
1954 	scsi_change_queue_depth(sdev, req->max_q_depth);
1955 	return 0;
1956 }
1957 
1958 static void
1959 qla2xxx_slave_destroy(struct scsi_device *sdev)
1960 {
1961 	sdev->hostdata = NULL;
1962 }
1963 
1964 /**
1965  * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1966  * @ha: HA context
1967  *
1968  * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1969  * supported addressing method.
1970  */
1971 static void
1972 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1973 {
1974 	/* Assume a 32bit DMA mask. */
1975 	ha->flags.enable_64bit_addressing = 0;
1976 
1977 	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1978 		/* Any upper-dword bits set? */
1979 		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1980 		    !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1981 			/* Ok, a 64bit DMA mask is applicable. */
1982 			ha->flags.enable_64bit_addressing = 1;
1983 			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1984 			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1985 			return;
1986 		}
1987 	}
1988 
1989 	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1990 	dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1991 }
1992 
1993 static void
1994 qla2x00_enable_intrs(struct qla_hw_data *ha)
1995 {
1996 	unsigned long flags = 0;
1997 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1998 
1999 	spin_lock_irqsave(&ha->hardware_lock, flags);
2000 	ha->interrupts_on = 1;
2001 	/* enable risc and host interrupts */
2002 	wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
2003 	rd_reg_word(&reg->ictrl);
2004 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2005 
2006 }
2007 
2008 static void
2009 qla2x00_disable_intrs(struct qla_hw_data *ha)
2010 {
2011 	unsigned long flags = 0;
2012 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2013 
2014 	spin_lock_irqsave(&ha->hardware_lock, flags);
2015 	ha->interrupts_on = 0;
2016 	/* disable risc and host interrupts */
2017 	wrt_reg_word(&reg->ictrl, 0);
2018 	rd_reg_word(&reg->ictrl);
2019 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2020 }
2021 
2022 static void
2023 qla24xx_enable_intrs(struct qla_hw_data *ha)
2024 {
2025 	unsigned long flags = 0;
2026 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2027 
2028 	spin_lock_irqsave(&ha->hardware_lock, flags);
2029 	ha->interrupts_on = 1;
2030 	wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
2031 	rd_reg_dword(&reg->ictrl);
2032 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2033 }
2034 
2035 static void
2036 qla24xx_disable_intrs(struct qla_hw_data *ha)
2037 {
2038 	unsigned long flags = 0;
2039 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2040 
2041 	if (IS_NOPOLLING_TYPE(ha))
2042 		return;
2043 	spin_lock_irqsave(&ha->hardware_lock, flags);
2044 	ha->interrupts_on = 0;
2045 	wrt_reg_dword(&reg->ictrl, 0);
2046 	rd_reg_dword(&reg->ictrl);
2047 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2048 }
2049 
2050 static int
2051 qla2x00_iospace_config(struct qla_hw_data *ha)
2052 {
2053 	resource_size_t pio;
2054 	uint16_t msix;
2055 
2056 	if (pci_request_selected_regions(ha->pdev, ha->bars,
2057 	    QLA2XXX_DRIVER_NAME)) {
2058 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2059 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2060 		    pci_name(ha->pdev));
2061 		goto iospace_error_exit;
2062 	}
2063 	if (!(ha->bars & 1))
2064 		goto skip_pio;
2065 
2066 	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
2067 	pio = pci_resource_start(ha->pdev, 0);
2068 	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2069 		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2070 			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2071 			    "Invalid pci I/O region size (%s).\n",
2072 			    pci_name(ha->pdev));
2073 			pio = 0;
2074 		}
2075 	} else {
2076 		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2077 		    "Region #0 no a PIO resource (%s).\n",
2078 		    pci_name(ha->pdev));
2079 		pio = 0;
2080 	}
2081 	ha->pio_address = pio;
2082 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2083 	    "PIO address=%llu.\n",
2084 	    (unsigned long long)ha->pio_address);
2085 
2086 skip_pio:
2087 	/* Use MMIO operations for all accesses. */
2088 	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2089 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2090 		    "Region #1 not an MMIO resource (%s), aborting.\n",
2091 		    pci_name(ha->pdev));
2092 		goto iospace_error_exit;
2093 	}
2094 	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2095 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2096 		    "Invalid PCI mem region size (%s), aborting.\n",
2097 		    pci_name(ha->pdev));
2098 		goto iospace_error_exit;
2099 	}
2100 
2101 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2102 	if (!ha->iobase) {
2103 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2104 		    "Cannot remap MMIO (%s), aborting.\n",
2105 		    pci_name(ha->pdev));
2106 		goto iospace_error_exit;
2107 	}
2108 
2109 	/* Determine queue resources */
2110 	ha->max_req_queues = ha->max_rsp_queues = 1;
2111 	ha->msix_count = QLA_BASE_VECTORS;
2112 
2113 	/* Check if FW supports MQ or not */
2114 	if (!(ha->fw_attributes & BIT_6))
2115 		goto mqiobase_exit;
2116 
2117 	if (!ql2xmqsupport || !ql2xnvmeenable ||
2118 	    (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2119 		goto mqiobase_exit;
2120 
2121 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2122 			pci_resource_len(ha->pdev, 3));
2123 	if (ha->mqiobase) {
2124 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2125 		    "MQIO Base=%p.\n", ha->mqiobase);
2126 		/* Read MSIX vector size of the board */
2127 		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2128 		ha->msix_count = msix + 1;
2129 		/* Max queues are bounded by available msix vectors */
2130 		/* MB interrupt uses 1 vector */
2131 		ha->max_req_queues = ha->msix_count - 1;
2132 		ha->max_rsp_queues = ha->max_req_queues;
2133 		/* Queue pairs is the max value minus the base queue pair */
2134 		ha->max_qpairs = ha->max_rsp_queues - 1;
2135 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2136 		    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2137 
2138 		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2139 		    "MSI-X vector count: %d.\n", ha->msix_count);
2140 	} else
2141 		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2142 		    "BAR 3 not enabled.\n");
2143 
2144 mqiobase_exit:
2145 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2146 	    "MSIX Count: %d.\n", ha->msix_count);
2147 	return (0);
2148 
2149 iospace_error_exit:
2150 	return (-ENOMEM);
2151 }
2152 
2153 
2154 static int
2155 qla83xx_iospace_config(struct qla_hw_data *ha)
2156 {
2157 	uint16_t msix;
2158 
2159 	if (pci_request_selected_regions(ha->pdev, ha->bars,
2160 	    QLA2XXX_DRIVER_NAME)) {
2161 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2162 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2163 		    pci_name(ha->pdev));
2164 
2165 		goto iospace_error_exit;
2166 	}
2167 
2168 	/* Use MMIO operations for all accesses. */
2169 	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2170 		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2171 		    "Invalid pci I/O region size (%s).\n",
2172 		    pci_name(ha->pdev));
2173 		goto iospace_error_exit;
2174 	}
2175 	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2176 		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2177 		    "Invalid PCI mem region size (%s), aborting\n",
2178 			pci_name(ha->pdev));
2179 		goto iospace_error_exit;
2180 	}
2181 
2182 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2183 	if (!ha->iobase) {
2184 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2185 		    "Cannot remap MMIO (%s), aborting.\n",
2186 		    pci_name(ha->pdev));
2187 		goto iospace_error_exit;
2188 	}
2189 
2190 	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2191 	/* 83XX 26XX always use MQ type access for queues
2192 	 * - mbar 2, a.k.a region 4 */
2193 	ha->max_req_queues = ha->max_rsp_queues = 1;
2194 	ha->msix_count = QLA_BASE_VECTORS;
2195 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2196 			pci_resource_len(ha->pdev, 4));
2197 
2198 	if (!ha->mqiobase) {
2199 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2200 		    "BAR2/region4 not enabled\n");
2201 		goto mqiobase_exit;
2202 	}
2203 
2204 	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2205 			pci_resource_len(ha->pdev, 2));
2206 	if (ha->msixbase) {
2207 		/* Read MSIX vector size of the board */
2208 		pci_read_config_word(ha->pdev,
2209 		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
2210 		ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE)  + 1;
2211 		/*
2212 		 * By default, driver uses at least two msix vectors
2213 		 * (default & rspq)
2214 		 */
2215 		if (ql2xmqsupport || ql2xnvmeenable) {
2216 			/* MB interrupt uses 1 vector */
2217 			ha->max_req_queues = ha->msix_count - 1;
2218 
2219 			/* ATIOQ needs 1 vector. That's 1 less QPair */
2220 			if (QLA_TGT_MODE_ENABLED())
2221 				ha->max_req_queues--;
2222 
2223 			ha->max_rsp_queues = ha->max_req_queues;
2224 
2225 			/* Queue pairs is the max value minus
2226 			 * the base queue pair */
2227 			ha->max_qpairs = ha->max_req_queues - 1;
2228 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2229 			    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2230 		}
2231 		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2232 		    "MSI-X vector count: %d.\n", ha->msix_count);
2233 	} else
2234 		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2235 		    "BAR 1 not enabled.\n");
2236 
2237 mqiobase_exit:
2238 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2239 	    "MSIX Count: %d.\n", ha->msix_count);
2240 	return 0;
2241 
2242 iospace_error_exit:
2243 	return -ENOMEM;
2244 }
2245 
2246 static struct isp_operations qla2100_isp_ops = {
2247 	.pci_config		= qla2100_pci_config,
2248 	.reset_chip		= qla2x00_reset_chip,
2249 	.chip_diag		= qla2x00_chip_diag,
2250 	.config_rings		= qla2x00_config_rings,
2251 	.reset_adapter		= qla2x00_reset_adapter,
2252 	.nvram_config		= qla2x00_nvram_config,
2253 	.update_fw_options	= qla2x00_update_fw_options,
2254 	.load_risc		= qla2x00_load_risc,
2255 	.pci_info_str		= qla2x00_pci_info_str,
2256 	.fw_version_str		= qla2x00_fw_version_str,
2257 	.intr_handler		= qla2100_intr_handler,
2258 	.enable_intrs		= qla2x00_enable_intrs,
2259 	.disable_intrs		= qla2x00_disable_intrs,
2260 	.abort_command		= qla2x00_abort_command,
2261 	.target_reset		= qla2x00_abort_target,
2262 	.lun_reset		= qla2x00_lun_reset,
2263 	.fabric_login		= qla2x00_login_fabric,
2264 	.fabric_logout		= qla2x00_fabric_logout,
2265 	.calc_req_entries	= qla2x00_calc_iocbs_32,
2266 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2267 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2268 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2269 	.read_nvram		= qla2x00_read_nvram_data,
2270 	.write_nvram		= qla2x00_write_nvram_data,
2271 	.fw_dump		= qla2100_fw_dump,
2272 	.beacon_on		= NULL,
2273 	.beacon_off		= NULL,
2274 	.beacon_blink		= NULL,
2275 	.read_optrom		= qla2x00_read_optrom_data,
2276 	.write_optrom		= qla2x00_write_optrom_data,
2277 	.get_flash_version	= qla2x00_get_flash_version,
2278 	.start_scsi		= qla2x00_start_scsi,
2279 	.start_scsi_mq          = NULL,
2280 	.abort_isp		= qla2x00_abort_isp,
2281 	.iospace_config     	= qla2x00_iospace_config,
2282 	.initialize_adapter	= qla2x00_initialize_adapter,
2283 };
2284 
2285 static struct isp_operations qla2300_isp_ops = {
2286 	.pci_config		= qla2300_pci_config,
2287 	.reset_chip		= qla2x00_reset_chip,
2288 	.chip_diag		= qla2x00_chip_diag,
2289 	.config_rings		= qla2x00_config_rings,
2290 	.reset_adapter		= qla2x00_reset_adapter,
2291 	.nvram_config		= qla2x00_nvram_config,
2292 	.update_fw_options	= qla2x00_update_fw_options,
2293 	.load_risc		= qla2x00_load_risc,
2294 	.pci_info_str		= qla2x00_pci_info_str,
2295 	.fw_version_str		= qla2x00_fw_version_str,
2296 	.intr_handler		= qla2300_intr_handler,
2297 	.enable_intrs		= qla2x00_enable_intrs,
2298 	.disable_intrs		= qla2x00_disable_intrs,
2299 	.abort_command		= qla2x00_abort_command,
2300 	.target_reset		= qla2x00_abort_target,
2301 	.lun_reset		= qla2x00_lun_reset,
2302 	.fabric_login		= qla2x00_login_fabric,
2303 	.fabric_logout		= qla2x00_fabric_logout,
2304 	.calc_req_entries	= qla2x00_calc_iocbs_32,
2305 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2306 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2307 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2308 	.read_nvram		= qla2x00_read_nvram_data,
2309 	.write_nvram		= qla2x00_write_nvram_data,
2310 	.fw_dump		= qla2300_fw_dump,
2311 	.beacon_on		= qla2x00_beacon_on,
2312 	.beacon_off		= qla2x00_beacon_off,
2313 	.beacon_blink		= qla2x00_beacon_blink,
2314 	.read_optrom		= qla2x00_read_optrom_data,
2315 	.write_optrom		= qla2x00_write_optrom_data,
2316 	.get_flash_version	= qla2x00_get_flash_version,
2317 	.start_scsi		= qla2x00_start_scsi,
2318 	.start_scsi_mq          = NULL,
2319 	.abort_isp		= qla2x00_abort_isp,
2320 	.iospace_config		= qla2x00_iospace_config,
2321 	.initialize_adapter	= qla2x00_initialize_adapter,
2322 };
2323 
2324 static struct isp_operations qla24xx_isp_ops = {
2325 	.pci_config		= qla24xx_pci_config,
2326 	.reset_chip		= qla24xx_reset_chip,
2327 	.chip_diag		= qla24xx_chip_diag,
2328 	.config_rings		= qla24xx_config_rings,
2329 	.reset_adapter		= qla24xx_reset_adapter,
2330 	.nvram_config		= qla24xx_nvram_config,
2331 	.update_fw_options	= qla24xx_update_fw_options,
2332 	.load_risc		= qla24xx_load_risc,
2333 	.pci_info_str		= qla24xx_pci_info_str,
2334 	.fw_version_str		= qla24xx_fw_version_str,
2335 	.intr_handler		= qla24xx_intr_handler,
2336 	.enable_intrs		= qla24xx_enable_intrs,
2337 	.disable_intrs		= qla24xx_disable_intrs,
2338 	.abort_command		= qla24xx_abort_command,
2339 	.target_reset		= qla24xx_abort_target,
2340 	.lun_reset		= qla24xx_lun_reset,
2341 	.fabric_login		= qla24xx_login_fabric,
2342 	.fabric_logout		= qla24xx_fabric_logout,
2343 	.calc_req_entries	= NULL,
2344 	.build_iocbs		= NULL,
2345 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2346 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2347 	.read_nvram		= qla24xx_read_nvram_data,
2348 	.write_nvram		= qla24xx_write_nvram_data,
2349 	.fw_dump		= qla24xx_fw_dump,
2350 	.beacon_on		= qla24xx_beacon_on,
2351 	.beacon_off		= qla24xx_beacon_off,
2352 	.beacon_blink		= qla24xx_beacon_blink,
2353 	.read_optrom		= qla24xx_read_optrom_data,
2354 	.write_optrom		= qla24xx_write_optrom_data,
2355 	.get_flash_version	= qla24xx_get_flash_version,
2356 	.start_scsi		= qla24xx_start_scsi,
2357 	.start_scsi_mq          = NULL,
2358 	.abort_isp		= qla2x00_abort_isp,
2359 	.iospace_config		= qla2x00_iospace_config,
2360 	.initialize_adapter	= qla2x00_initialize_adapter,
2361 };
2362 
2363 static struct isp_operations qla25xx_isp_ops = {
2364 	.pci_config		= qla25xx_pci_config,
2365 	.reset_chip		= qla24xx_reset_chip,
2366 	.chip_diag		= qla24xx_chip_diag,
2367 	.config_rings		= qla24xx_config_rings,
2368 	.reset_adapter		= qla24xx_reset_adapter,
2369 	.nvram_config		= qla24xx_nvram_config,
2370 	.update_fw_options	= qla24xx_update_fw_options,
2371 	.load_risc		= qla24xx_load_risc,
2372 	.pci_info_str		= qla24xx_pci_info_str,
2373 	.fw_version_str		= qla24xx_fw_version_str,
2374 	.intr_handler		= qla24xx_intr_handler,
2375 	.enable_intrs		= qla24xx_enable_intrs,
2376 	.disable_intrs		= qla24xx_disable_intrs,
2377 	.abort_command		= qla24xx_abort_command,
2378 	.target_reset		= qla24xx_abort_target,
2379 	.lun_reset		= qla24xx_lun_reset,
2380 	.fabric_login		= qla24xx_login_fabric,
2381 	.fabric_logout		= qla24xx_fabric_logout,
2382 	.calc_req_entries	= NULL,
2383 	.build_iocbs		= NULL,
2384 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2385 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2386 	.read_nvram		= qla25xx_read_nvram_data,
2387 	.write_nvram		= qla25xx_write_nvram_data,
2388 	.fw_dump		= qla25xx_fw_dump,
2389 	.beacon_on		= qla24xx_beacon_on,
2390 	.beacon_off		= qla24xx_beacon_off,
2391 	.beacon_blink		= qla24xx_beacon_blink,
2392 	.read_optrom		= qla25xx_read_optrom_data,
2393 	.write_optrom		= qla24xx_write_optrom_data,
2394 	.get_flash_version	= qla24xx_get_flash_version,
2395 	.start_scsi		= qla24xx_dif_start_scsi,
2396 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2397 	.abort_isp		= qla2x00_abort_isp,
2398 	.iospace_config		= qla2x00_iospace_config,
2399 	.initialize_adapter	= qla2x00_initialize_adapter,
2400 };
2401 
2402 static struct isp_operations qla81xx_isp_ops = {
2403 	.pci_config		= qla25xx_pci_config,
2404 	.reset_chip		= qla24xx_reset_chip,
2405 	.chip_diag		= qla24xx_chip_diag,
2406 	.config_rings		= qla24xx_config_rings,
2407 	.reset_adapter		= qla24xx_reset_adapter,
2408 	.nvram_config		= qla81xx_nvram_config,
2409 	.update_fw_options	= qla24xx_update_fw_options,
2410 	.load_risc		= qla81xx_load_risc,
2411 	.pci_info_str		= qla24xx_pci_info_str,
2412 	.fw_version_str		= qla24xx_fw_version_str,
2413 	.intr_handler		= qla24xx_intr_handler,
2414 	.enable_intrs		= qla24xx_enable_intrs,
2415 	.disable_intrs		= qla24xx_disable_intrs,
2416 	.abort_command		= qla24xx_abort_command,
2417 	.target_reset		= qla24xx_abort_target,
2418 	.lun_reset		= qla24xx_lun_reset,
2419 	.fabric_login		= qla24xx_login_fabric,
2420 	.fabric_logout		= qla24xx_fabric_logout,
2421 	.calc_req_entries	= NULL,
2422 	.build_iocbs		= NULL,
2423 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2424 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2425 	.read_nvram		= NULL,
2426 	.write_nvram		= NULL,
2427 	.fw_dump		= qla81xx_fw_dump,
2428 	.beacon_on		= qla24xx_beacon_on,
2429 	.beacon_off		= qla24xx_beacon_off,
2430 	.beacon_blink		= qla83xx_beacon_blink,
2431 	.read_optrom		= qla25xx_read_optrom_data,
2432 	.write_optrom		= qla24xx_write_optrom_data,
2433 	.get_flash_version	= qla24xx_get_flash_version,
2434 	.start_scsi		= qla24xx_dif_start_scsi,
2435 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2436 	.abort_isp		= qla2x00_abort_isp,
2437 	.iospace_config		= qla2x00_iospace_config,
2438 	.initialize_adapter	= qla2x00_initialize_adapter,
2439 };
2440 
2441 static struct isp_operations qla82xx_isp_ops = {
2442 	.pci_config		= qla82xx_pci_config,
2443 	.reset_chip		= qla82xx_reset_chip,
2444 	.chip_diag		= qla24xx_chip_diag,
2445 	.config_rings		= qla82xx_config_rings,
2446 	.reset_adapter		= qla24xx_reset_adapter,
2447 	.nvram_config		= qla81xx_nvram_config,
2448 	.update_fw_options	= qla24xx_update_fw_options,
2449 	.load_risc		= qla82xx_load_risc,
2450 	.pci_info_str		= qla24xx_pci_info_str,
2451 	.fw_version_str		= qla24xx_fw_version_str,
2452 	.intr_handler		= qla82xx_intr_handler,
2453 	.enable_intrs		= qla82xx_enable_intrs,
2454 	.disable_intrs		= qla82xx_disable_intrs,
2455 	.abort_command		= qla24xx_abort_command,
2456 	.target_reset		= qla24xx_abort_target,
2457 	.lun_reset		= qla24xx_lun_reset,
2458 	.fabric_login		= qla24xx_login_fabric,
2459 	.fabric_logout		= qla24xx_fabric_logout,
2460 	.calc_req_entries	= NULL,
2461 	.build_iocbs		= NULL,
2462 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2463 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2464 	.read_nvram		= qla24xx_read_nvram_data,
2465 	.write_nvram		= qla24xx_write_nvram_data,
2466 	.fw_dump		= qla82xx_fw_dump,
2467 	.beacon_on		= qla82xx_beacon_on,
2468 	.beacon_off		= qla82xx_beacon_off,
2469 	.beacon_blink		= NULL,
2470 	.read_optrom		= qla82xx_read_optrom_data,
2471 	.write_optrom		= qla82xx_write_optrom_data,
2472 	.get_flash_version	= qla82xx_get_flash_version,
2473 	.start_scsi             = qla82xx_start_scsi,
2474 	.start_scsi_mq          = NULL,
2475 	.abort_isp		= qla82xx_abort_isp,
2476 	.iospace_config     	= qla82xx_iospace_config,
2477 	.initialize_adapter	= qla2x00_initialize_adapter,
2478 };
2479 
2480 static struct isp_operations qla8044_isp_ops = {
2481 	.pci_config		= qla82xx_pci_config,
2482 	.reset_chip		= qla82xx_reset_chip,
2483 	.chip_diag		= qla24xx_chip_diag,
2484 	.config_rings		= qla82xx_config_rings,
2485 	.reset_adapter		= qla24xx_reset_adapter,
2486 	.nvram_config		= qla81xx_nvram_config,
2487 	.update_fw_options	= qla24xx_update_fw_options,
2488 	.load_risc		= qla82xx_load_risc,
2489 	.pci_info_str		= qla24xx_pci_info_str,
2490 	.fw_version_str		= qla24xx_fw_version_str,
2491 	.intr_handler		= qla8044_intr_handler,
2492 	.enable_intrs		= qla82xx_enable_intrs,
2493 	.disable_intrs		= qla82xx_disable_intrs,
2494 	.abort_command		= qla24xx_abort_command,
2495 	.target_reset		= qla24xx_abort_target,
2496 	.lun_reset		= qla24xx_lun_reset,
2497 	.fabric_login		= qla24xx_login_fabric,
2498 	.fabric_logout		= qla24xx_fabric_logout,
2499 	.calc_req_entries	= NULL,
2500 	.build_iocbs		= NULL,
2501 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2502 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2503 	.read_nvram		= NULL,
2504 	.write_nvram		= NULL,
2505 	.fw_dump		= qla8044_fw_dump,
2506 	.beacon_on		= qla82xx_beacon_on,
2507 	.beacon_off		= qla82xx_beacon_off,
2508 	.beacon_blink		= NULL,
2509 	.read_optrom		= qla8044_read_optrom_data,
2510 	.write_optrom		= qla8044_write_optrom_data,
2511 	.get_flash_version	= qla82xx_get_flash_version,
2512 	.start_scsi             = qla82xx_start_scsi,
2513 	.start_scsi_mq          = NULL,
2514 	.abort_isp		= qla8044_abort_isp,
2515 	.iospace_config		= qla82xx_iospace_config,
2516 	.initialize_adapter	= qla2x00_initialize_adapter,
2517 };
2518 
2519 static struct isp_operations qla83xx_isp_ops = {
2520 	.pci_config		= qla25xx_pci_config,
2521 	.reset_chip		= qla24xx_reset_chip,
2522 	.chip_diag		= qla24xx_chip_diag,
2523 	.config_rings		= qla24xx_config_rings,
2524 	.reset_adapter		= qla24xx_reset_adapter,
2525 	.nvram_config		= qla81xx_nvram_config,
2526 	.update_fw_options	= qla24xx_update_fw_options,
2527 	.load_risc		= qla81xx_load_risc,
2528 	.pci_info_str		= qla24xx_pci_info_str,
2529 	.fw_version_str		= qla24xx_fw_version_str,
2530 	.intr_handler		= qla24xx_intr_handler,
2531 	.enable_intrs		= qla24xx_enable_intrs,
2532 	.disable_intrs		= qla24xx_disable_intrs,
2533 	.abort_command		= qla24xx_abort_command,
2534 	.target_reset		= qla24xx_abort_target,
2535 	.lun_reset		= qla24xx_lun_reset,
2536 	.fabric_login		= qla24xx_login_fabric,
2537 	.fabric_logout		= qla24xx_fabric_logout,
2538 	.calc_req_entries	= NULL,
2539 	.build_iocbs		= NULL,
2540 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2541 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2542 	.read_nvram		= NULL,
2543 	.write_nvram		= NULL,
2544 	.fw_dump		= qla83xx_fw_dump,
2545 	.beacon_on		= qla24xx_beacon_on,
2546 	.beacon_off		= qla24xx_beacon_off,
2547 	.beacon_blink		= qla83xx_beacon_blink,
2548 	.read_optrom		= qla25xx_read_optrom_data,
2549 	.write_optrom		= qla24xx_write_optrom_data,
2550 	.get_flash_version	= qla24xx_get_flash_version,
2551 	.start_scsi		= qla24xx_dif_start_scsi,
2552 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2553 	.abort_isp		= qla2x00_abort_isp,
2554 	.iospace_config		= qla83xx_iospace_config,
2555 	.initialize_adapter	= qla2x00_initialize_adapter,
2556 };
2557 
2558 static struct isp_operations qlafx00_isp_ops = {
2559 	.pci_config		= qlafx00_pci_config,
2560 	.reset_chip		= qlafx00_soft_reset,
2561 	.chip_diag		= qlafx00_chip_diag,
2562 	.config_rings		= qlafx00_config_rings,
2563 	.reset_adapter		= qlafx00_soft_reset,
2564 	.nvram_config		= NULL,
2565 	.update_fw_options	= NULL,
2566 	.load_risc		= NULL,
2567 	.pci_info_str		= qlafx00_pci_info_str,
2568 	.fw_version_str		= qlafx00_fw_version_str,
2569 	.intr_handler		= qlafx00_intr_handler,
2570 	.enable_intrs		= qlafx00_enable_intrs,
2571 	.disable_intrs		= qlafx00_disable_intrs,
2572 	.abort_command		= qla24xx_async_abort_command,
2573 	.target_reset		= qlafx00_abort_target,
2574 	.lun_reset		= qlafx00_lun_reset,
2575 	.fabric_login		= NULL,
2576 	.fabric_logout		= NULL,
2577 	.calc_req_entries	= NULL,
2578 	.build_iocbs		= NULL,
2579 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2580 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2581 	.read_nvram		= qla24xx_read_nvram_data,
2582 	.write_nvram		= qla24xx_write_nvram_data,
2583 	.fw_dump		= NULL,
2584 	.beacon_on		= qla24xx_beacon_on,
2585 	.beacon_off		= qla24xx_beacon_off,
2586 	.beacon_blink		= NULL,
2587 	.read_optrom		= qla24xx_read_optrom_data,
2588 	.write_optrom		= qla24xx_write_optrom_data,
2589 	.get_flash_version	= qla24xx_get_flash_version,
2590 	.start_scsi		= qlafx00_start_scsi,
2591 	.start_scsi_mq          = NULL,
2592 	.abort_isp		= qlafx00_abort_isp,
2593 	.iospace_config		= qlafx00_iospace_config,
2594 	.initialize_adapter	= qlafx00_initialize_adapter,
2595 };
2596 
2597 static struct isp_operations qla27xx_isp_ops = {
2598 	.pci_config		= qla25xx_pci_config,
2599 	.reset_chip		= qla24xx_reset_chip,
2600 	.chip_diag		= qla24xx_chip_diag,
2601 	.config_rings		= qla24xx_config_rings,
2602 	.reset_adapter		= qla24xx_reset_adapter,
2603 	.nvram_config		= qla81xx_nvram_config,
2604 	.update_fw_options	= qla24xx_update_fw_options,
2605 	.load_risc		= qla81xx_load_risc,
2606 	.pci_info_str		= qla24xx_pci_info_str,
2607 	.fw_version_str		= qla24xx_fw_version_str,
2608 	.intr_handler		= qla24xx_intr_handler,
2609 	.enable_intrs		= qla24xx_enable_intrs,
2610 	.disable_intrs		= qla24xx_disable_intrs,
2611 	.abort_command		= qla24xx_abort_command,
2612 	.target_reset		= qla24xx_abort_target,
2613 	.lun_reset		= qla24xx_lun_reset,
2614 	.fabric_login		= qla24xx_login_fabric,
2615 	.fabric_logout		= qla24xx_fabric_logout,
2616 	.calc_req_entries	= NULL,
2617 	.build_iocbs		= NULL,
2618 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2619 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2620 	.read_nvram		= NULL,
2621 	.write_nvram		= NULL,
2622 	.fw_dump		= qla27xx_fwdump,
2623 	.mpi_fw_dump		= qla27xx_mpi_fwdump,
2624 	.beacon_on		= qla24xx_beacon_on,
2625 	.beacon_off		= qla24xx_beacon_off,
2626 	.beacon_blink		= qla83xx_beacon_blink,
2627 	.read_optrom		= qla25xx_read_optrom_data,
2628 	.write_optrom		= qla24xx_write_optrom_data,
2629 	.get_flash_version	= qla24xx_get_flash_version,
2630 	.start_scsi		= qla24xx_dif_start_scsi,
2631 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2632 	.abort_isp		= qla2x00_abort_isp,
2633 	.iospace_config		= qla83xx_iospace_config,
2634 	.initialize_adapter	= qla2x00_initialize_adapter,
2635 };
2636 
2637 static inline void
2638 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2639 {
2640 	ha->device_type = DT_EXTENDED_IDS;
2641 	switch (ha->pdev->device) {
2642 	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2643 		ha->isp_type |= DT_ISP2100;
2644 		ha->device_type &= ~DT_EXTENDED_IDS;
2645 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2646 		break;
2647 	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2648 		ha->isp_type |= DT_ISP2200;
2649 		ha->device_type &= ~DT_EXTENDED_IDS;
2650 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2651 		break;
2652 	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2653 		ha->isp_type |= DT_ISP2300;
2654 		ha->device_type |= DT_ZIO_SUPPORTED;
2655 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2656 		break;
2657 	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2658 		ha->isp_type |= DT_ISP2312;
2659 		ha->device_type |= DT_ZIO_SUPPORTED;
2660 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2661 		break;
2662 	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2663 		ha->isp_type |= DT_ISP2322;
2664 		ha->device_type |= DT_ZIO_SUPPORTED;
2665 		if (ha->pdev->subsystem_vendor == 0x1028 &&
2666 		    ha->pdev->subsystem_device == 0x0170)
2667 			ha->device_type |= DT_OEM_001;
2668 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2669 		break;
2670 	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2671 		ha->isp_type |= DT_ISP6312;
2672 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2673 		break;
2674 	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2675 		ha->isp_type |= DT_ISP6322;
2676 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2677 		break;
2678 	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2679 		ha->isp_type |= DT_ISP2422;
2680 		ha->device_type |= DT_ZIO_SUPPORTED;
2681 		ha->device_type |= DT_FWI2;
2682 		ha->device_type |= DT_IIDMA;
2683 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2684 		break;
2685 	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2686 		ha->isp_type |= DT_ISP2432;
2687 		ha->device_type |= DT_ZIO_SUPPORTED;
2688 		ha->device_type |= DT_FWI2;
2689 		ha->device_type |= DT_IIDMA;
2690 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2691 		break;
2692 	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2693 		ha->isp_type |= DT_ISP8432;
2694 		ha->device_type |= DT_ZIO_SUPPORTED;
2695 		ha->device_type |= DT_FWI2;
2696 		ha->device_type |= DT_IIDMA;
2697 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2698 		break;
2699 	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2700 		ha->isp_type |= DT_ISP5422;
2701 		ha->device_type |= DT_FWI2;
2702 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2703 		break;
2704 	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2705 		ha->isp_type |= DT_ISP5432;
2706 		ha->device_type |= DT_FWI2;
2707 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2708 		break;
2709 	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2710 		ha->isp_type |= DT_ISP2532;
2711 		ha->device_type |= DT_ZIO_SUPPORTED;
2712 		ha->device_type |= DT_FWI2;
2713 		ha->device_type |= DT_IIDMA;
2714 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2715 		break;
2716 	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2717 		ha->isp_type |= DT_ISP8001;
2718 		ha->device_type |= DT_ZIO_SUPPORTED;
2719 		ha->device_type |= DT_FWI2;
2720 		ha->device_type |= DT_IIDMA;
2721 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2722 		break;
2723 	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2724 		ha->isp_type |= DT_ISP8021;
2725 		ha->device_type |= DT_ZIO_SUPPORTED;
2726 		ha->device_type |= DT_FWI2;
2727 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2728 		/* Initialize 82XX ISP flags */
2729 		qla82xx_init_flags(ha);
2730 		break;
2731 	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2732 		ha->isp_type |= DT_ISP8044;
2733 		ha->device_type |= DT_ZIO_SUPPORTED;
2734 		ha->device_type |= DT_FWI2;
2735 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2736 		/* Initialize 82XX ISP flags */
2737 		qla82xx_init_flags(ha);
2738 		break;
2739 	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2740 		ha->isp_type |= DT_ISP2031;
2741 		ha->device_type |= DT_ZIO_SUPPORTED;
2742 		ha->device_type |= DT_FWI2;
2743 		ha->device_type |= DT_IIDMA;
2744 		ha->device_type |= DT_T10_PI;
2745 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2746 		break;
2747 	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2748 		ha->isp_type |= DT_ISP8031;
2749 		ha->device_type |= DT_ZIO_SUPPORTED;
2750 		ha->device_type |= DT_FWI2;
2751 		ha->device_type |= DT_IIDMA;
2752 		ha->device_type |= DT_T10_PI;
2753 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754 		break;
2755 	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2756 		ha->isp_type |= DT_ISPFX00;
2757 		break;
2758 	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2759 		ha->isp_type |= DT_ISP2071;
2760 		ha->device_type |= DT_ZIO_SUPPORTED;
2761 		ha->device_type |= DT_FWI2;
2762 		ha->device_type |= DT_IIDMA;
2763 		ha->device_type |= DT_T10_PI;
2764 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2765 		break;
2766 	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2767 		ha->isp_type |= DT_ISP2271;
2768 		ha->device_type |= DT_ZIO_SUPPORTED;
2769 		ha->device_type |= DT_FWI2;
2770 		ha->device_type |= DT_IIDMA;
2771 		ha->device_type |= DT_T10_PI;
2772 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2773 		break;
2774 	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2775 		ha->isp_type |= DT_ISP2261;
2776 		ha->device_type |= DT_ZIO_SUPPORTED;
2777 		ha->device_type |= DT_FWI2;
2778 		ha->device_type |= DT_IIDMA;
2779 		ha->device_type |= DT_T10_PI;
2780 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2781 		break;
2782 	case PCI_DEVICE_ID_QLOGIC_ISP2081:
2783 	case PCI_DEVICE_ID_QLOGIC_ISP2089:
2784 		ha->isp_type |= DT_ISP2081;
2785 		ha->device_type |= DT_ZIO_SUPPORTED;
2786 		ha->device_type |= DT_FWI2;
2787 		ha->device_type |= DT_IIDMA;
2788 		ha->device_type |= DT_T10_PI;
2789 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2790 		break;
2791 	case PCI_DEVICE_ID_QLOGIC_ISP2281:
2792 	case PCI_DEVICE_ID_QLOGIC_ISP2289:
2793 		ha->isp_type |= DT_ISP2281;
2794 		ha->device_type |= DT_ZIO_SUPPORTED;
2795 		ha->device_type |= DT_FWI2;
2796 		ha->device_type |= DT_IIDMA;
2797 		ha->device_type |= DT_T10_PI;
2798 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2799 		break;
2800 	}
2801 
2802 	if (IS_QLA82XX(ha))
2803 		ha->port_no = ha->portnum & 1;
2804 	else {
2805 		/* Get adapter physical port no from interrupt pin register. */
2806 		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2807 		if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2808 		    IS_QLA27XX(ha) || IS_QLA28XX(ha))
2809 			ha->port_no--;
2810 		else
2811 			ha->port_no = !(ha->port_no & 1);
2812 	}
2813 
2814 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2815 	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2816 	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2817 }
2818 
2819 static void
2820 qla2xxx_scan_start(struct Scsi_Host *shost)
2821 {
2822 	scsi_qla_host_t *vha = shost_priv(shost);
2823 
2824 	if (vha->hw->flags.running_gold_fw)
2825 		return;
2826 
2827 	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2828 	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2829 	set_bit(RSCN_UPDATE, &vha->dpc_flags);
2830 	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2831 }
2832 
2833 static int
2834 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2835 {
2836 	scsi_qla_host_t *vha = shost_priv(shost);
2837 
2838 	if (test_bit(UNLOADING, &vha->dpc_flags))
2839 		return 1;
2840 	if (!vha->host)
2841 		return 1;
2842 	if (time > vha->hw->loop_reset_delay * HZ)
2843 		return 1;
2844 
2845 	return atomic_read(&vha->loop_state) == LOOP_READY;
2846 }
2847 
2848 static void qla_heartbeat_work_fn(struct work_struct *work)
2849 {
2850 	struct qla_hw_data *ha = container_of(work,
2851 		struct qla_hw_data, heartbeat_work);
2852 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2853 
2854 	if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2855 		qla_no_op_mb(base_vha);
2856 }
2857 
2858 static void qla2x00_iocb_work_fn(struct work_struct *work)
2859 {
2860 	struct scsi_qla_host *vha = container_of(work,
2861 		struct scsi_qla_host, iocb_work);
2862 	struct qla_hw_data *ha = vha->hw;
2863 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2864 	int i = 2;
2865 	unsigned long flags;
2866 
2867 	if (test_bit(UNLOADING, &base_vha->dpc_flags))
2868 		return;
2869 
2870 	while (!list_empty(&vha->work_list) && i > 0) {
2871 		qla2x00_do_work(vha);
2872 		i--;
2873 	}
2874 
2875 	spin_lock_irqsave(&vha->work_lock, flags);
2876 	clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2877 	spin_unlock_irqrestore(&vha->work_lock, flags);
2878 }
2879 
2880 static void
2881 qla_trace_init(void)
2882 {
2883 	qla_trc_array = trace_array_get_by_name("qla2xxx");
2884 	if (!qla_trc_array) {
2885 		ql_log(ql_log_fatal, NULL, 0x0001,
2886 		       "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2887 		return;
2888 	}
2889 
2890 	QLA_TRACE_ENABLE(qla_trc_array);
2891 }
2892 
2893 static void
2894 qla_trace_uninit(void)
2895 {
2896 	if (!qla_trc_array)
2897 		return;
2898 	trace_array_put(qla_trc_array);
2899 }
2900 
2901 /*
2902  * PCI driver interface
2903  */
2904 static int
2905 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2906 {
2907 	int	ret = -ENODEV;
2908 	struct Scsi_Host *host;
2909 	scsi_qla_host_t *base_vha = NULL;
2910 	struct qla_hw_data *ha;
2911 	char pci_info[30];
2912 	char fw_str[30], wq_name[30];
2913 	struct scsi_host_template *sht;
2914 	int bars, mem_only = 0;
2915 	uint16_t req_length = 0, rsp_length = 0;
2916 	struct req_que *req = NULL;
2917 	struct rsp_que *rsp = NULL;
2918 	int i;
2919 
2920 	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2921 	sht = &qla2xxx_driver_template;
2922 	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2923 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2924 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2925 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2926 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2927 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2928 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2929 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2930 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2931 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2932 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2933 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2934 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2935 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2936 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2937 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2938 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2939 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2940 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2941 		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2942 		mem_only = 1;
2943 		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2944 		    "Mem only adapter.\n");
2945 	}
2946 	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2947 	    "Bars=%d.\n", bars);
2948 
2949 	if (mem_only) {
2950 		if (pci_enable_device_mem(pdev))
2951 			return ret;
2952 	} else {
2953 		if (pci_enable_device(pdev))
2954 			return ret;
2955 	}
2956 
2957 	if (is_kdump_kernel()) {
2958 		ql2xmqsupport = 0;
2959 		ql2xallocfwdump = 0;
2960 	}
2961 
2962 	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2963 	if (!ha) {
2964 		ql_log_pci(ql_log_fatal, pdev, 0x0009,
2965 		    "Unable to allocate memory for ha.\n");
2966 		goto disable_device;
2967 	}
2968 	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2969 	    "Memory allocated for ha=%p.\n", ha);
2970 	ha->pdev = pdev;
2971 	INIT_LIST_HEAD(&ha->tgt.q_full_list);
2972 	spin_lock_init(&ha->tgt.q_full_lock);
2973 	spin_lock_init(&ha->tgt.sess_lock);
2974 	spin_lock_init(&ha->tgt.atio_lock);
2975 
2976 	spin_lock_init(&ha->sadb_lock);
2977 	INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2978 	INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2979 
2980 	spin_lock_init(&ha->sadb_fp_lock);
2981 
2982 	if (qla_edif_sadb_build_free_pool(ha)) {
2983 		kfree(ha);
2984 		goto  disable_device;
2985 	}
2986 
2987 	atomic_set(&ha->nvme_active_aen_cnt, 0);
2988 
2989 	/* Clear our data area */
2990 	ha->bars = bars;
2991 	ha->mem_only = mem_only;
2992 	spin_lock_init(&ha->hardware_lock);
2993 	spin_lock_init(&ha->vport_slock);
2994 	mutex_init(&ha->selflogin_lock);
2995 	mutex_init(&ha->optrom_mutex);
2996 
2997 	/* Set ISP-type information. */
2998 	qla2x00_set_isp_flags(ha);
2999 
3000 	/* Set EEH reset type to fundamental if required by hba */
3001 	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3002 	    IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3003 		pdev->needs_freset = 1;
3004 
3005 	ha->prev_topology = 0;
3006 	ha->init_cb_size = sizeof(init_cb_t);
3007 	ha->link_data_rate = PORT_SPEED_UNKNOWN;
3008 	ha->optrom_size = OPTROM_SIZE_2300;
3009 	ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3010 	atomic_set(&ha->num_pend_mbx_stage1, 0);
3011 	atomic_set(&ha->num_pend_mbx_stage2, 0);
3012 	atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3013 	ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3014 	INIT_LIST_HEAD(&ha->tmf_pending);
3015 	INIT_LIST_HEAD(&ha->tmf_active);
3016 
3017 	/* Assign ISP specific operations. */
3018 	if (IS_QLA2100(ha)) {
3019 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3020 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3021 		req_length = REQUEST_ENTRY_CNT_2100;
3022 		rsp_length = RESPONSE_ENTRY_CNT_2100;
3023 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3024 		ha->gid_list_info_size = 4;
3025 		ha->flash_conf_off = ~0;
3026 		ha->flash_data_off = ~0;
3027 		ha->nvram_conf_off = ~0;
3028 		ha->nvram_data_off = ~0;
3029 		ha->isp_ops = &qla2100_isp_ops;
3030 	} else if (IS_QLA2200(ha)) {
3031 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3032 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3033 		req_length = REQUEST_ENTRY_CNT_2200;
3034 		rsp_length = RESPONSE_ENTRY_CNT_2100;
3035 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3036 		ha->gid_list_info_size = 4;
3037 		ha->flash_conf_off = ~0;
3038 		ha->flash_data_off = ~0;
3039 		ha->nvram_conf_off = ~0;
3040 		ha->nvram_data_off = ~0;
3041 		ha->isp_ops = &qla2100_isp_ops;
3042 	} else if (IS_QLA23XX(ha)) {
3043 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3044 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3045 		req_length = REQUEST_ENTRY_CNT_2200;
3046 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3047 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3048 		ha->gid_list_info_size = 6;
3049 		if (IS_QLA2322(ha) || IS_QLA6322(ha))
3050 			ha->optrom_size = OPTROM_SIZE_2322;
3051 		ha->flash_conf_off = ~0;
3052 		ha->flash_data_off = ~0;
3053 		ha->nvram_conf_off = ~0;
3054 		ha->nvram_data_off = ~0;
3055 		ha->isp_ops = &qla2300_isp_ops;
3056 	} else if (IS_QLA24XX_TYPE(ha)) {
3057 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3058 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3059 		req_length = REQUEST_ENTRY_CNT_24XX;
3060 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3061 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3062 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3063 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3064 		ha->gid_list_info_size = 8;
3065 		ha->optrom_size = OPTROM_SIZE_24XX;
3066 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3067 		ha->isp_ops = &qla24xx_isp_ops;
3068 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3069 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3070 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3071 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3072 	} else if (IS_QLA25XX(ha)) {
3073 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3074 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3075 		req_length = REQUEST_ENTRY_CNT_24XX;
3076 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3077 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3078 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3079 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3080 		ha->gid_list_info_size = 8;
3081 		ha->optrom_size = OPTROM_SIZE_25XX;
3082 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3083 		ha->isp_ops = &qla25xx_isp_ops;
3084 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3085 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3086 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3087 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3088 	} else if (IS_QLA81XX(ha)) {
3089 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3090 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3091 		req_length = REQUEST_ENTRY_CNT_24XX;
3092 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3093 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3094 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3095 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3096 		ha->gid_list_info_size = 8;
3097 		ha->optrom_size = OPTROM_SIZE_81XX;
3098 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3099 		ha->isp_ops = &qla81xx_isp_ops;
3100 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3101 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3102 		ha->nvram_conf_off = ~0;
3103 		ha->nvram_data_off = ~0;
3104 	} else if (IS_QLA82XX(ha)) {
3105 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3106 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3107 		req_length = REQUEST_ENTRY_CNT_82XX;
3108 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3109 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3110 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3111 		ha->gid_list_info_size = 8;
3112 		ha->optrom_size = OPTROM_SIZE_82XX;
3113 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3114 		ha->isp_ops = &qla82xx_isp_ops;
3115 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3116 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3117 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3118 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3119 	} else if (IS_QLA8044(ha)) {
3120 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3121 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3122 		req_length = REQUEST_ENTRY_CNT_82XX;
3123 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3124 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3125 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3126 		ha->gid_list_info_size = 8;
3127 		ha->optrom_size = OPTROM_SIZE_83XX;
3128 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3129 		ha->isp_ops = &qla8044_isp_ops;
3130 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3131 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3132 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3133 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3134 	} else if (IS_QLA83XX(ha)) {
3135 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3136 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3137 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3138 		req_length = REQUEST_ENTRY_CNT_83XX;
3139 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3140 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3141 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3142 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3143 		ha->gid_list_info_size = 8;
3144 		ha->optrom_size = OPTROM_SIZE_83XX;
3145 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3146 		ha->isp_ops = &qla83xx_isp_ops;
3147 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3148 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3149 		ha->nvram_conf_off = ~0;
3150 		ha->nvram_data_off = ~0;
3151 	}  else if (IS_QLAFX00(ha)) {
3152 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3153 		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3154 		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3155 		req_length = REQUEST_ENTRY_CNT_FX00;
3156 		rsp_length = RESPONSE_ENTRY_CNT_FX00;
3157 		ha->isp_ops = &qlafx00_isp_ops;
3158 		ha->port_down_retry_count = 30; /* default value */
3159 		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3160 		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3161 		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3162 		ha->mr.fw_hbt_en = 1;
3163 		ha->mr.host_info_resend = false;
3164 		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3165 	} else if (IS_QLA27XX(ha)) {
3166 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3167 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3168 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3169 		req_length = REQUEST_ENTRY_CNT_83XX;
3170 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3171 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3172 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3173 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3174 		ha->gid_list_info_size = 8;
3175 		ha->optrom_size = OPTROM_SIZE_83XX;
3176 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3177 		ha->isp_ops = &qla27xx_isp_ops;
3178 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3179 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3180 		ha->nvram_conf_off = ~0;
3181 		ha->nvram_data_off = ~0;
3182 	} else if (IS_QLA28XX(ha)) {
3183 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3184 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3185 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3186 		req_length = REQUEST_ENTRY_CNT_83XX;
3187 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3188 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3189 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3190 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3191 		ha->gid_list_info_size = 8;
3192 		ha->optrom_size = OPTROM_SIZE_28XX;
3193 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3194 		ha->isp_ops = &qla27xx_isp_ops;
3195 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3196 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3197 		ha->nvram_conf_off = ~0;
3198 		ha->nvram_data_off = ~0;
3199 	}
3200 
3201 	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3202 	    "mbx_count=%d, req_length=%d, "
3203 	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3204 	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3205 	    "max_fibre_devices=%d.\n",
3206 	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3207 	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3208 	    ha->nvram_npiv_size, ha->max_fibre_devices);
3209 	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3210 	    "isp_ops=%p, flash_conf_off=%d, "
3211 	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3212 	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3213 	    ha->nvram_conf_off, ha->nvram_data_off);
3214 
3215 	/* Configure PCI I/O space */
3216 	ret = ha->isp_ops->iospace_config(ha);
3217 	if (ret)
3218 		goto iospace_config_failed;
3219 
3220 	ql_log_pci(ql_log_info, pdev, 0x001d,
3221 	    "Found an ISP%04X irq %d iobase 0x%p.\n",
3222 	    pdev->device, pdev->irq, ha->iobase);
3223 	mutex_init(&ha->vport_lock);
3224 	mutex_init(&ha->mq_lock);
3225 	init_completion(&ha->mbx_cmd_comp);
3226 	complete(&ha->mbx_cmd_comp);
3227 	init_completion(&ha->mbx_intr_comp);
3228 	init_completion(&ha->dcbx_comp);
3229 	init_completion(&ha->lb_portup_comp);
3230 
3231 	set_bit(0, (unsigned long *) ha->vp_idx_map);
3232 
3233 	qla2x00_config_dma_addressing(ha);
3234 	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3235 	    "64 Bit addressing is %s.\n",
3236 	    ha->flags.enable_64bit_addressing ? "enable" :
3237 	    "disable");
3238 	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3239 	if (ret) {
3240 		ql_log_pci(ql_log_fatal, pdev, 0x0031,
3241 		    "Failed to allocate memory for adapter, aborting.\n");
3242 
3243 		goto probe_hw_failed;
3244 	}
3245 
3246 	req->max_q_depth = MAX_Q_DEPTH;
3247 	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3248 		req->max_q_depth = ql2xmaxqdepth;
3249 
3250 
3251 	base_vha = qla2x00_create_host(sht, ha);
3252 	if (!base_vha) {
3253 		ret = -ENOMEM;
3254 		goto probe_hw_failed;
3255 	}
3256 
3257 	pci_set_drvdata(pdev, base_vha);
3258 	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3259 
3260 	host = base_vha->host;
3261 	base_vha->req = req;
3262 	if (IS_QLA2XXX_MIDTYPE(ha))
3263 		base_vha->mgmt_svr_loop_id =
3264 			qla2x00_reserve_mgmt_server_loop_id(base_vha);
3265 	else
3266 		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3267 						base_vha->vp_idx;
3268 
3269 	/* Setup fcport template structure. */
3270 	ha->mr.fcport.vha = base_vha;
3271 	ha->mr.fcport.port_type = FCT_UNKNOWN;
3272 	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3273 	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3274 	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3275 	ha->mr.fcport.scan_state = 1;
3276 
3277 	qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3278 			    QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3279 			    QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3280 
3281 	/* Set the SG table size based on ISP type */
3282 	if (!IS_FWI2_CAPABLE(ha)) {
3283 		if (IS_QLA2100(ha))
3284 			host->sg_tablesize = 32;
3285 	} else {
3286 		if (!IS_QLA82XX(ha))
3287 			host->sg_tablesize = QLA_SG_ALL;
3288 	}
3289 	host->max_id = ha->max_fibre_devices;
3290 	host->cmd_per_lun = 3;
3291 	host->unique_id = host->host_no;
3292 
3293 	if (ql2xenabledif && ql2xenabledif != 2) {
3294 		ql_log(ql_log_warn, base_vha, 0x302d,
3295 		       "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3296 		ql2xenabledif = 2;
3297 	}
3298 
3299 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3300 		host->max_cmd_len = 32;
3301 	else
3302 		host->max_cmd_len = MAX_CMDSZ;
3303 	host->max_channel = MAX_BUSES - 1;
3304 	/* Older HBAs support only 16-bit LUNs */
3305 	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3306 	    ql2xmaxlun > 0xffff)
3307 		host->max_lun = 0xffff;
3308 	else
3309 		host->max_lun = ql2xmaxlun;
3310 	host->transportt = qla2xxx_transport_template;
3311 	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3312 
3313 	ql_dbg(ql_dbg_init, base_vha, 0x0033,
3314 	    "max_id=%d this_id=%d "
3315 	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3316 	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3317 	    host->this_id, host->cmd_per_lun, host->unique_id,
3318 	    host->max_cmd_len, host->max_channel, host->max_lun,
3319 	    host->transportt, sht->vendor_id);
3320 
3321 	INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3322 
3323 	/* Set up the irqs */
3324 	ret = qla2x00_request_irqs(ha, rsp);
3325 	if (ret)
3326 		goto probe_failed;
3327 
3328 	/* Alloc arrays of request and response ring ptrs */
3329 	ret = qla2x00_alloc_queues(ha, req, rsp);
3330 	if (ret) {
3331 		ql_log(ql_log_fatal, base_vha, 0x003d,
3332 		    "Failed to allocate memory for queue pointers..."
3333 		    "aborting.\n");
3334 		ret = -ENODEV;
3335 		goto probe_failed;
3336 	}
3337 
3338 	if (ha->mqenable) {
3339 		/* number of hardware queues supported by blk/scsi-mq*/
3340 		host->nr_hw_queues = ha->max_qpairs;
3341 
3342 		ql_dbg(ql_dbg_init, base_vha, 0x0192,
3343 			"blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3344 	} else {
3345 		if (ql2xnvmeenable) {
3346 			host->nr_hw_queues = ha->max_qpairs;
3347 			ql_dbg(ql_dbg_init, base_vha, 0x0194,
3348 			    "FC-NVMe support is enabled, HW queues=%d\n",
3349 			    host->nr_hw_queues);
3350 		} else {
3351 			ql_dbg(ql_dbg_init, base_vha, 0x0193,
3352 			    "blk/scsi-mq disabled.\n");
3353 		}
3354 	}
3355 
3356 	qlt_probe_one_stage1(base_vha, ha);
3357 
3358 	pci_save_state(pdev);
3359 
3360 	/* Assign back pointers */
3361 	rsp->req = req;
3362 	req->rsp = rsp;
3363 
3364 	if (IS_QLAFX00(ha)) {
3365 		ha->rsp_q_map[0] = rsp;
3366 		ha->req_q_map[0] = req;
3367 		set_bit(0, ha->req_qid_map);
3368 		set_bit(0, ha->rsp_qid_map);
3369 	}
3370 
3371 	/* FWI2-capable only. */
3372 	req->req_q_in = &ha->iobase->isp24.req_q_in;
3373 	req->req_q_out = &ha->iobase->isp24.req_q_out;
3374 	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3375 	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3376 	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3377 	    IS_QLA28XX(ha)) {
3378 		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3379 		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3380 		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3381 		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
3382 	}
3383 
3384 	if (IS_QLAFX00(ha)) {
3385 		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3386 		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3387 		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3388 		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3389 	}
3390 
3391 	if (IS_P3P_TYPE(ha)) {
3392 		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3393 		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3394 		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3395 	}
3396 
3397 	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3398 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3399 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3400 	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3401 	    "req->req_q_in=%p req->req_q_out=%p "
3402 	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3403 	    req->req_q_in, req->req_q_out,
3404 	    rsp->rsp_q_in, rsp->rsp_q_out);
3405 	ql_dbg(ql_dbg_init, base_vha, 0x003e,
3406 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3407 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3408 	ql_dbg(ql_dbg_init, base_vha, 0x003f,
3409 	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3410 	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3411 
3412 	ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3413 	if (unlikely(!ha->wq)) {
3414 		ret = -ENOMEM;
3415 		goto probe_failed;
3416 	}
3417 
3418 	if (ha->isp_ops->initialize_adapter(base_vha)) {
3419 		ql_log(ql_log_fatal, base_vha, 0x00d6,
3420 		    "Failed to initialize adapter - Adapter flags %x.\n",
3421 		    base_vha->device_flags);
3422 
3423 		if (IS_QLA82XX(ha)) {
3424 			qla82xx_idc_lock(ha);
3425 			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3426 				QLA8XXX_DEV_FAILED);
3427 			qla82xx_idc_unlock(ha);
3428 			ql_log(ql_log_fatal, base_vha, 0x00d7,
3429 			    "HW State: FAILED.\n");
3430 		} else if (IS_QLA8044(ha)) {
3431 			qla8044_idc_lock(ha);
3432 			qla8044_wr_direct(base_vha,
3433 				QLA8044_CRB_DEV_STATE_INDEX,
3434 				QLA8XXX_DEV_FAILED);
3435 			qla8044_idc_unlock(ha);
3436 			ql_log(ql_log_fatal, base_vha, 0x0150,
3437 			    "HW State: FAILED.\n");
3438 		}
3439 
3440 		ret = -ENODEV;
3441 		goto probe_failed;
3442 	}
3443 
3444 	if (IS_QLAFX00(ha))
3445 		host->can_queue = QLAFX00_MAX_CANQUEUE;
3446 	else
3447 		host->can_queue = req->num_outstanding_cmds - 10;
3448 
3449 	ql_dbg(ql_dbg_init, base_vha, 0x0032,
3450 	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3451 	    host->can_queue, base_vha->req,
3452 	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3453 
3454 	/* Check if FW supports MQ or not for ISP25xx */
3455 	if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3456 		ha->mqenable = 0;
3457 
3458 	if (ha->mqenable) {
3459 		bool startit = false;
3460 
3461 		if (QLA_TGT_MODE_ENABLED())
3462 			startit = false;
3463 
3464 		if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3465 			startit = true;
3466 
3467 		/* Create start of day qpairs for Block MQ */
3468 		for (i = 0; i < ha->max_qpairs; i++)
3469 			qla2xxx_create_qpair(base_vha, 5, 0, startit);
3470 	}
3471 	qla_init_iocb_limit(base_vha);
3472 
3473 	if (ha->flags.running_gold_fw)
3474 		goto skip_dpc;
3475 
3476 	/*
3477 	 * Startup the kernel thread for this host adapter
3478 	 */
3479 	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3480 	    "%s_dpc", base_vha->host_str);
3481 	if (IS_ERR(ha->dpc_thread)) {
3482 		ql_log(ql_log_fatal, base_vha, 0x00ed,
3483 		    "Failed to start DPC thread.\n");
3484 		ret = PTR_ERR(ha->dpc_thread);
3485 		ha->dpc_thread = NULL;
3486 		goto probe_failed;
3487 	}
3488 	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3489 	    "DPC thread started successfully.\n");
3490 
3491 	/*
3492 	 * If we're not coming up in initiator mode, we might sit for
3493 	 * a while without waking up the dpc thread, which leads to a
3494 	 * stuck process warning.  So just kick the dpc once here and
3495 	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3496 	 */
3497 	qla2xxx_wake_dpc(base_vha);
3498 
3499 	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3500 
3501 	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3502 		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3503 		ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3504 		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3505 
3506 		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3507 		ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3508 		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3509 		INIT_WORK(&ha->idc_state_handler,
3510 		    qla83xx_idc_state_handler_work);
3511 		INIT_WORK(&ha->nic_core_unrecoverable,
3512 		    qla83xx_nic_core_unrecoverable_work);
3513 	}
3514 
3515 skip_dpc:
3516 	list_add_tail(&base_vha->list, &ha->vp_list);
3517 	base_vha->host->irq = ha->pdev->irq;
3518 
3519 	/* Initialized the timer */
3520 	qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3521 	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3522 	    "Started qla2x00_timer with "
3523 	    "interval=%d.\n", WATCH_INTERVAL);
3524 	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3525 	    "Detected hba at address=%p.\n",
3526 	    ha);
3527 
3528 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3529 		if (ha->fw_attributes & BIT_4) {
3530 			int prot = 0, guard;
3531 
3532 			base_vha->flags.difdix_supported = 1;
3533 			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3534 			    "Registering for DIF/DIX type 1 and 3 protection.\n");
3535 			if (ql2xprotmask)
3536 				scsi_host_set_prot(host, ql2xprotmask);
3537 			else
3538 				scsi_host_set_prot(host,
3539 				    prot | SHOST_DIF_TYPE1_PROTECTION
3540 				    | SHOST_DIF_TYPE2_PROTECTION
3541 				    | SHOST_DIF_TYPE3_PROTECTION
3542 				    | SHOST_DIX_TYPE1_PROTECTION
3543 				    | SHOST_DIX_TYPE2_PROTECTION
3544 				    | SHOST_DIX_TYPE3_PROTECTION);
3545 
3546 			guard = SHOST_DIX_GUARD_CRC;
3547 
3548 			if (IS_PI_IPGUARD_CAPABLE(ha) &&
3549 			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3550 				guard |= SHOST_DIX_GUARD_IP;
3551 
3552 			if (ql2xprotguard)
3553 				scsi_host_set_guard(host, ql2xprotguard);
3554 			else
3555 				scsi_host_set_guard(host, guard);
3556 		} else
3557 			base_vha->flags.difdix_supported = 0;
3558 	}
3559 
3560 	ha->isp_ops->enable_intrs(ha);
3561 
3562 	if (IS_QLAFX00(ha)) {
3563 		ret = qlafx00_fx_disc(base_vha,
3564 			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3565 		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3566 		    QLA_SG_ALL : 128;
3567 	}
3568 
3569 	ret = scsi_add_host(host, &pdev->dev);
3570 	if (ret)
3571 		goto probe_failed;
3572 
3573 	base_vha->flags.init_done = 1;
3574 	base_vha->flags.online = 1;
3575 	ha->prev_minidump_failed = 0;
3576 
3577 	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3578 	    "Init done and hba is online.\n");
3579 
3580 	if (qla_ini_mode_enabled(base_vha) ||
3581 		qla_dual_mode_enabled(base_vha))
3582 		scsi_scan_host(host);
3583 	else
3584 		ql_log(ql_log_info, base_vha, 0x0122,
3585 			"skipping scsi_scan_host() for non-initiator port\n");
3586 
3587 	qla2x00_alloc_sysfs_attr(base_vha);
3588 
3589 	if (IS_QLAFX00(ha)) {
3590 		ret = qlafx00_fx_disc(base_vha,
3591 			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3592 
3593 		/* Register system information */
3594 		ret =  qlafx00_fx_disc(base_vha,
3595 			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3596 	}
3597 
3598 	qla2x00_init_host_attr(base_vha);
3599 
3600 	qla2x00_dfs_setup(base_vha);
3601 
3602 	ql_log(ql_log_info, base_vha, 0x00fb,
3603 	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3604 	ql_log(ql_log_info, base_vha, 0x00fc,
3605 	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3606 	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3607 						       sizeof(pci_info)),
3608 	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3609 	    base_vha->host_no,
3610 	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3611 
3612 	qlt_add_target(ha, base_vha);
3613 
3614 	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3615 
3616 	if (test_bit(UNLOADING, &base_vha->dpc_flags))
3617 		return -ENODEV;
3618 
3619 	return 0;
3620 
3621 probe_failed:
3622 	qla_enode_stop(base_vha);
3623 	qla_edb_stop(base_vha);
3624 	vfree(base_vha->scan.l);
3625 	if (base_vha->gnl.l) {
3626 		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3627 				base_vha->gnl.l, base_vha->gnl.ldma);
3628 		base_vha->gnl.l = NULL;
3629 	}
3630 
3631 	if (base_vha->timer_active)
3632 		qla2x00_stop_timer(base_vha);
3633 	base_vha->flags.online = 0;
3634 	if (ha->dpc_thread) {
3635 		struct task_struct *t = ha->dpc_thread;
3636 
3637 		ha->dpc_thread = NULL;
3638 		kthread_stop(t);
3639 	}
3640 
3641 	qla2x00_free_device(base_vha);
3642 	scsi_host_put(base_vha->host);
3643 	/*
3644 	 * Need to NULL out local req/rsp after
3645 	 * qla2x00_free_device => qla2x00_free_queues frees
3646 	 * what these are pointing to. Or else we'll
3647 	 * fall over below in qla2x00_free_req/rsp_que.
3648 	 */
3649 	req = NULL;
3650 	rsp = NULL;
3651 
3652 probe_hw_failed:
3653 	qla2x00_mem_free(ha);
3654 	qla2x00_free_req_que(ha, req);
3655 	qla2x00_free_rsp_que(ha, rsp);
3656 	qla2x00_clear_drv_active(ha);
3657 
3658 iospace_config_failed:
3659 	if (IS_P3P_TYPE(ha)) {
3660 		if (!ha->nx_pcibase)
3661 			iounmap((device_reg_t *)ha->nx_pcibase);
3662 		if (!ql2xdbwr)
3663 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3664 	} else {
3665 		if (ha->iobase)
3666 			iounmap(ha->iobase);
3667 		if (ha->cregbase)
3668 			iounmap(ha->cregbase);
3669 	}
3670 	pci_release_selected_regions(ha->pdev, ha->bars);
3671 	kfree(ha);
3672 
3673 disable_device:
3674 	pci_disable_device(pdev);
3675 	return ret;
3676 }
3677 
3678 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3679 {
3680 	scsi_qla_host_t *vp;
3681 	unsigned long flags;
3682 	struct qla_hw_data *ha;
3683 
3684 	if (!base_vha)
3685 		return;
3686 
3687 	ha = base_vha->hw;
3688 
3689 	spin_lock_irqsave(&ha->vport_slock, flags);
3690 	list_for_each_entry(vp, &ha->vp_list, list)
3691 		set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3692 
3693 	/*
3694 	 * Indicate device removal to prevent future board_disable
3695 	 * and wait until any pending board_disable has completed.
3696 	 */
3697 	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3698 	spin_unlock_irqrestore(&ha->vport_slock, flags);
3699 }
3700 
3701 static void
3702 qla2x00_shutdown(struct pci_dev *pdev)
3703 {
3704 	scsi_qla_host_t *vha;
3705 	struct qla_hw_data  *ha;
3706 
3707 	vha = pci_get_drvdata(pdev);
3708 	ha = vha->hw;
3709 
3710 	ql_log(ql_log_info, vha, 0xfffa,
3711 		"Adapter shutdown\n");
3712 
3713 	/*
3714 	 * Prevent future board_disable and wait
3715 	 * until any pending board_disable has completed.
3716 	 */
3717 	__qla_set_remove_flag(vha);
3718 	cancel_work_sync(&ha->board_disable);
3719 
3720 	if (!atomic_read(&pdev->enable_cnt))
3721 		return;
3722 
3723 	/* Notify ISPFX00 firmware */
3724 	if (IS_QLAFX00(ha))
3725 		qlafx00_driver_shutdown(vha, 20);
3726 
3727 	/* Turn-off FCE trace */
3728 	if (ha->flags.fce_enabled) {
3729 		qla2x00_disable_fce_trace(vha, NULL, NULL);
3730 		ha->flags.fce_enabled = 0;
3731 	}
3732 
3733 	/* Turn-off EFT trace */
3734 	if (ha->eft)
3735 		qla2x00_disable_eft_trace(vha);
3736 
3737 	if (IS_QLA25XX(ha) ||  IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3738 	    IS_QLA28XX(ha)) {
3739 		if (ha->flags.fw_started)
3740 			qla2x00_abort_isp_cleanup(vha);
3741 	} else {
3742 		/* Stop currently executing firmware. */
3743 		qla2x00_try_to_stop_firmware(vha);
3744 	}
3745 
3746 	/* Disable timer */
3747 	if (vha->timer_active)
3748 		qla2x00_stop_timer(vha);
3749 
3750 	/* Turn adapter off line */
3751 	vha->flags.online = 0;
3752 
3753 	/* turn-off interrupts on the card */
3754 	if (ha->interrupts_on) {
3755 		vha->flags.init_done = 0;
3756 		ha->isp_ops->disable_intrs(ha);
3757 	}
3758 
3759 	qla2x00_free_irqs(vha);
3760 
3761 	qla2x00_free_fw_dump(ha);
3762 
3763 	pci_disable_device(pdev);
3764 	ql_log(ql_log_info, vha, 0xfffe,
3765 		"Adapter shutdown successfully.\n");
3766 }
3767 
3768 /* Deletes all the virtual ports for a given ha */
3769 static void
3770 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3771 {
3772 	scsi_qla_host_t *vha;
3773 	unsigned long flags;
3774 
3775 	mutex_lock(&ha->vport_lock);
3776 	while (ha->cur_vport_count) {
3777 		spin_lock_irqsave(&ha->vport_slock, flags);
3778 
3779 		BUG_ON(base_vha->list.next == &ha->vp_list);
3780 		/* This assumes first entry in ha->vp_list is always base vha */
3781 		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3782 		scsi_host_get(vha->host);
3783 
3784 		spin_unlock_irqrestore(&ha->vport_slock, flags);
3785 		mutex_unlock(&ha->vport_lock);
3786 
3787 		qla_nvme_delete(vha);
3788 
3789 		fc_vport_terminate(vha->fc_vport);
3790 		scsi_host_put(vha->host);
3791 
3792 		mutex_lock(&ha->vport_lock);
3793 	}
3794 	mutex_unlock(&ha->vport_lock);
3795 }
3796 
3797 /* Stops all deferred work threads */
3798 static void
3799 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3800 {
3801 	/* Cancel all work and destroy DPC workqueues */
3802 	if (ha->dpc_lp_wq) {
3803 		cancel_work_sync(&ha->idc_aen);
3804 		destroy_workqueue(ha->dpc_lp_wq);
3805 		ha->dpc_lp_wq = NULL;
3806 	}
3807 
3808 	if (ha->dpc_hp_wq) {
3809 		cancel_work_sync(&ha->nic_core_reset);
3810 		cancel_work_sync(&ha->idc_state_handler);
3811 		cancel_work_sync(&ha->nic_core_unrecoverable);
3812 		destroy_workqueue(ha->dpc_hp_wq);
3813 		ha->dpc_hp_wq = NULL;
3814 	}
3815 
3816 	/* Kill the kernel thread for this host */
3817 	if (ha->dpc_thread) {
3818 		struct task_struct *t = ha->dpc_thread;
3819 
3820 		/*
3821 		 * qla2xxx_wake_dpc checks for ->dpc_thread
3822 		 * so we need to zero it out.
3823 		 */
3824 		ha->dpc_thread = NULL;
3825 		kthread_stop(t);
3826 	}
3827 }
3828 
3829 static void
3830 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3831 {
3832 	if (IS_QLA82XX(ha)) {
3833 
3834 		iounmap((device_reg_t *)ha->nx_pcibase);
3835 		if (!ql2xdbwr)
3836 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3837 	} else {
3838 		if (ha->iobase)
3839 			iounmap(ha->iobase);
3840 
3841 		if (ha->cregbase)
3842 			iounmap(ha->cregbase);
3843 
3844 		if (ha->mqiobase)
3845 			iounmap(ha->mqiobase);
3846 
3847 		if (ha->msixbase)
3848 			iounmap(ha->msixbase);
3849 	}
3850 }
3851 
3852 static void
3853 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3854 {
3855 	if (IS_QLA8044(ha)) {
3856 		qla8044_idc_lock(ha);
3857 		qla8044_clear_drv_active(ha);
3858 		qla8044_idc_unlock(ha);
3859 	} else if (IS_QLA82XX(ha)) {
3860 		qla82xx_idc_lock(ha);
3861 		qla82xx_clear_drv_active(ha);
3862 		qla82xx_idc_unlock(ha);
3863 	}
3864 }
3865 
3866 static void
3867 qla2x00_remove_one(struct pci_dev *pdev)
3868 {
3869 	scsi_qla_host_t *base_vha;
3870 	struct qla_hw_data  *ha;
3871 
3872 	base_vha = pci_get_drvdata(pdev);
3873 	ha = base_vha->hw;
3874 	ql_log(ql_log_info, base_vha, 0xb079,
3875 	    "Removing driver\n");
3876 	__qla_set_remove_flag(base_vha);
3877 	cancel_work_sync(&ha->board_disable);
3878 
3879 	/*
3880 	 * If the PCI device is disabled then there was a PCI-disconnect and
3881 	 * qla2x00_disable_board_on_pci_error has taken care of most of the
3882 	 * resources.
3883 	 */
3884 	if (!atomic_read(&pdev->enable_cnt)) {
3885 		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3886 		    base_vha->gnl.l, base_vha->gnl.ldma);
3887 		base_vha->gnl.l = NULL;
3888 		scsi_host_put(base_vha->host);
3889 		kfree(ha);
3890 		pci_set_drvdata(pdev, NULL);
3891 		return;
3892 	}
3893 	qla2x00_wait_for_hba_ready(base_vha);
3894 
3895 	/*
3896 	 * if UNLOADING flag is already set, then continue unload,
3897 	 * where it was set first.
3898 	 */
3899 	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3900 		return;
3901 
3902 	if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3903 	    IS_QLA28XX(ha)) {
3904 		if (ha->flags.fw_started)
3905 			qla2x00_abort_isp_cleanup(base_vha);
3906 	} else if (!IS_QLAFX00(ha)) {
3907 		if (IS_QLA8031(ha)) {
3908 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3909 			    "Clearing fcoe driver presence.\n");
3910 			if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3911 				ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3912 				    "Error while clearing DRV-Presence.\n");
3913 		}
3914 
3915 		qla2x00_try_to_stop_firmware(base_vha);
3916 	}
3917 
3918 	qla2x00_wait_for_sess_deletion(base_vha);
3919 
3920 	qla_nvme_delete(base_vha);
3921 
3922 	dma_free_coherent(&ha->pdev->dev,
3923 		base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3924 
3925 	base_vha->gnl.l = NULL;
3926 	qla_enode_stop(base_vha);
3927 	qla_edb_stop(base_vha);
3928 
3929 	vfree(base_vha->scan.l);
3930 
3931 	if (IS_QLAFX00(ha))
3932 		qlafx00_driver_shutdown(base_vha, 20);
3933 
3934 	qla2x00_delete_all_vps(ha, base_vha);
3935 
3936 	qla2x00_dfs_remove(base_vha);
3937 
3938 	qla84xx_put_chip(base_vha);
3939 
3940 	/* Disable timer */
3941 	if (base_vha->timer_active)
3942 		qla2x00_stop_timer(base_vha);
3943 
3944 	base_vha->flags.online = 0;
3945 
3946 	/* free DMA memory */
3947 	if (ha->exlogin_buf)
3948 		qla2x00_free_exlogin_buffer(ha);
3949 
3950 	/* free DMA memory */
3951 	if (ha->exchoffld_buf)
3952 		qla2x00_free_exchoffld_buffer(ha);
3953 
3954 	qla2x00_destroy_deferred_work(ha);
3955 
3956 	qlt_remove_target(ha, base_vha);
3957 
3958 	qla2x00_free_sysfs_attr(base_vha, true);
3959 
3960 	fc_remove_host(base_vha->host);
3961 
3962 	scsi_remove_host(base_vha->host);
3963 
3964 	qla2x00_free_device(base_vha);
3965 
3966 	qla2x00_clear_drv_active(ha);
3967 
3968 	scsi_host_put(base_vha->host);
3969 
3970 	qla2x00_unmap_iobases(ha);
3971 
3972 	pci_release_selected_regions(ha->pdev, ha->bars);
3973 	kfree(ha);
3974 
3975 	pci_disable_device(pdev);
3976 }
3977 
3978 static inline void
3979 qla24xx_free_purex_list(struct purex_list *list)
3980 {
3981 	struct purex_item *item, *next;
3982 	ulong flags;
3983 
3984 	spin_lock_irqsave(&list->lock, flags);
3985 	list_for_each_entry_safe(item, next, &list->head, list) {
3986 		list_del(&item->list);
3987 		if (item == &item->vha->default_item)
3988 			continue;
3989 		kfree(item);
3990 	}
3991 	spin_unlock_irqrestore(&list->lock, flags);
3992 }
3993 
3994 static void
3995 qla2x00_free_device(scsi_qla_host_t *vha)
3996 {
3997 	struct qla_hw_data *ha = vha->hw;
3998 
3999 	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4000 
4001 	/* Disable timer */
4002 	if (vha->timer_active)
4003 		qla2x00_stop_timer(vha);
4004 
4005 	qla25xx_delete_queues(vha);
4006 	vha->flags.online = 0;
4007 
4008 	/* turn-off interrupts on the card */
4009 	if (ha->interrupts_on) {
4010 		vha->flags.init_done = 0;
4011 		ha->isp_ops->disable_intrs(ha);
4012 	}
4013 
4014 	qla2x00_free_fcports(vha);
4015 
4016 	qla2x00_free_irqs(vha);
4017 
4018 	/* Flush the work queue and remove it */
4019 	if (ha->wq) {
4020 		destroy_workqueue(ha->wq);
4021 		ha->wq = NULL;
4022 	}
4023 
4024 
4025 	qla24xx_free_purex_list(&vha->purex_list);
4026 
4027 	qla2x00_mem_free(ha);
4028 
4029 	qla82xx_md_free(vha);
4030 
4031 	qla_edif_sadb_release_free_pool(ha);
4032 	qla_edif_sadb_release(ha);
4033 
4034 	qla2x00_free_queues(ha);
4035 }
4036 
4037 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4038 {
4039 	fc_port_t *fcport, *tfcport;
4040 
4041 	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4042 		qla2x00_free_fcport(fcport);
4043 }
4044 
4045 static inline void
4046 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4047 {
4048 	int now;
4049 
4050 	if (!fcport->rport)
4051 		return;
4052 
4053 	if (fcport->rport) {
4054 		ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4055 		    "%s %8phN. rport %p roles %x\n",
4056 		    __func__, fcport->port_name, fcport->rport,
4057 		    fcport->rport->roles);
4058 		fc_remote_port_delete(fcport->rport);
4059 	}
4060 	qlt_do_generation_tick(vha, &now);
4061 }
4062 
4063 /*
4064  * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4065  *
4066  * Input: ha = adapter block pointer.  fcport = port structure pointer.
4067  *
4068  * Return: None.
4069  *
4070  * Context:
4071  */
4072 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4073     int do_login)
4074 {
4075 	if (IS_QLAFX00(vha->hw)) {
4076 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4077 		qla2x00_schedule_rport_del(vha, fcport);
4078 		return;
4079 	}
4080 
4081 	if (atomic_read(&fcport->state) == FCS_ONLINE &&
4082 	    vha->vp_idx == fcport->vha->vp_idx) {
4083 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4084 		qla2x00_schedule_rport_del(vha, fcport);
4085 	}
4086 
4087 	/*
4088 	 * We may need to retry the login, so don't change the state of the
4089 	 * port but do the retries.
4090 	 */
4091 	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4092 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4093 
4094 	if (!do_login)
4095 		return;
4096 
4097 	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4098 }
4099 
4100 void
4101 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4102 {
4103 	fc_port_t *fcport;
4104 
4105 	ql_dbg(ql_dbg_disc, vha, 0x20f1,
4106 	    "Mark all dev lost\n");
4107 
4108 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
4109 		if (ql2xfc2target &&
4110 		    fcport->loop_id != FC_NO_LOOP_ID &&
4111 		    (fcport->flags & FCF_FCP2_DEVICE) &&
4112 		    fcport->port_type == FCT_TARGET &&
4113 		    !qla2x00_reset_active(vha)) {
4114 			ql_dbg(ql_dbg_disc, vha, 0x211a,
4115 			       "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4116 			       fcport->flags, fcport->port_type,
4117 			       fcport->d_id.b24, fcport->port_name);
4118 			continue;
4119 		}
4120 		fcport->scan_state = 0;
4121 		qlt_schedule_sess_for_deletion(fcport);
4122 	}
4123 }
4124 
4125 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4126 {
4127 	int i;
4128 
4129 	if (IS_FWI2_CAPABLE(ha))
4130 		return;
4131 
4132 	for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4133 		set_bit(i, ha->loop_id_map);
4134 	set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4135 	set_bit(BROADCAST, ha->loop_id_map);
4136 }
4137 
4138 /*
4139 * qla2x00_mem_alloc
4140 *      Allocates adapter memory.
4141 *
4142 * Returns:
4143 *      0  = success.
4144 *      !0  = failure.
4145 */
4146 static int
4147 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4148 	struct req_que **req, struct rsp_que **rsp)
4149 {
4150 	char	name[16];
4151 	int rc;
4152 
4153 	if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4154 		ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4155 		if (!ha->vp_map)
4156 			goto fail;
4157 	}
4158 
4159 	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4160 		&ha->init_cb_dma, GFP_KERNEL);
4161 	if (!ha->init_cb)
4162 		goto fail_free_vp_map;
4163 
4164 	rc = btree_init32(&ha->host_map);
4165 	if (rc)
4166 		goto fail_free_init_cb;
4167 
4168 	if (qlt_mem_alloc(ha) < 0)
4169 		goto fail_free_btree;
4170 
4171 	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4172 		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4173 	if (!ha->gid_list)
4174 		goto fail_free_tgt_mem;
4175 
4176 	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4177 	if (!ha->srb_mempool)
4178 		goto fail_free_gid_list;
4179 
4180 	if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4181 		/* Allocate cache for CT6 Ctx. */
4182 		if (!ctx_cachep) {
4183 			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4184 				sizeof(struct ct6_dsd), 0,
4185 				SLAB_HWCACHE_ALIGN, NULL);
4186 			if (!ctx_cachep)
4187 				goto fail_free_srb_mempool;
4188 		}
4189 		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4190 			ctx_cachep);
4191 		if (!ha->ctx_mempool)
4192 			goto fail_free_srb_mempool;
4193 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4194 		    "ctx_cachep=%p ctx_mempool=%p.\n",
4195 		    ctx_cachep, ha->ctx_mempool);
4196 	}
4197 
4198 	/* Get memory for cached NVRAM */
4199 	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4200 	if (!ha->nvram)
4201 		goto fail_free_ctx_mempool;
4202 
4203 	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4204 		ha->pdev->device);
4205 	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4206 		DMA_POOL_SIZE, 8, 0);
4207 	if (!ha->s_dma_pool)
4208 		goto fail_free_nvram;
4209 
4210 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4211 	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4212 	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4213 
4214 	if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4215 		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4216 			DSD_LIST_DMA_POOL_SIZE, 8, 0);
4217 		if (!ha->dl_dma_pool) {
4218 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4219 			    "Failed to allocate memory for dl_dma_pool.\n");
4220 			goto fail_s_dma_pool;
4221 		}
4222 
4223 		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4224 			FCP_CMND_DMA_POOL_SIZE, 8, 0);
4225 		if (!ha->fcp_cmnd_dma_pool) {
4226 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4227 			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4228 			goto fail_dl_dma_pool;
4229 		}
4230 
4231 		if (ql2xenabledif) {
4232 			u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4233 			struct dsd_dma *dsd, *nxt;
4234 			uint i;
4235 			/* Creata a DMA pool of buffers for DIF bundling */
4236 			ha->dif_bundl_pool = dma_pool_create(name,
4237 			    &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4238 			if (!ha->dif_bundl_pool) {
4239 				ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4240 				    "%s: failed create dif_bundl_pool\n",
4241 				    __func__);
4242 				goto fail_dif_bundl_dma_pool;
4243 			}
4244 
4245 			INIT_LIST_HEAD(&ha->pool.good.head);
4246 			INIT_LIST_HEAD(&ha->pool.unusable.head);
4247 			ha->pool.good.count = 0;
4248 			ha->pool.unusable.count = 0;
4249 			for (i = 0; i < 128; i++) {
4250 				dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4251 				if (!dsd) {
4252 					ql_dbg_pci(ql_dbg_init, ha->pdev,
4253 					    0xe0ee, "%s: failed alloc dsd\n",
4254 					    __func__);
4255 					return -ENOMEM;
4256 				}
4257 				ha->dif_bundle_kallocs++;
4258 
4259 				dsd->dsd_addr = dma_pool_alloc(
4260 				    ha->dif_bundl_pool, GFP_ATOMIC,
4261 				    &dsd->dsd_list_dma);
4262 				if (!dsd->dsd_addr) {
4263 					ql_dbg_pci(ql_dbg_init, ha->pdev,
4264 					    0xe0ee,
4265 					    "%s: failed alloc ->dsd_addr\n",
4266 					    __func__);
4267 					kfree(dsd);
4268 					ha->dif_bundle_kallocs--;
4269 					continue;
4270 				}
4271 				ha->dif_bundle_dma_allocs++;
4272 
4273 				/*
4274 				 * if DMA buffer crosses 4G boundary,
4275 				 * put it on bad list
4276 				 */
4277 				if (MSD(dsd->dsd_list_dma) ^
4278 				    MSD(dsd->dsd_list_dma + bufsize)) {
4279 					list_add_tail(&dsd->list,
4280 					    &ha->pool.unusable.head);
4281 					ha->pool.unusable.count++;
4282 				} else {
4283 					list_add_tail(&dsd->list,
4284 					    &ha->pool.good.head);
4285 					ha->pool.good.count++;
4286 				}
4287 			}
4288 
4289 			/* return the good ones back to the pool */
4290 			list_for_each_entry_safe(dsd, nxt,
4291 			    &ha->pool.good.head, list) {
4292 				list_del(&dsd->list);
4293 				dma_pool_free(ha->dif_bundl_pool,
4294 				    dsd->dsd_addr, dsd->dsd_list_dma);
4295 				ha->dif_bundle_dma_allocs--;
4296 				kfree(dsd);
4297 				ha->dif_bundle_kallocs--;
4298 			}
4299 
4300 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4301 			    "%s: dif dma pool (good=%u unusable=%u)\n",
4302 			    __func__, ha->pool.good.count,
4303 			    ha->pool.unusable.count);
4304 		}
4305 
4306 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4307 		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4308 		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4309 		    ha->dif_bundl_pool);
4310 	}
4311 
4312 	/* Allocate memory for SNS commands */
4313 	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4314 	/* Get consistent memory allocated for SNS commands */
4315 		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4316 		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4317 		if (!ha->sns_cmd)
4318 			goto fail_dma_pool;
4319 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4320 		    "sns_cmd: %p.\n", ha->sns_cmd);
4321 	} else {
4322 	/* Get consistent memory allocated for MS IOCB */
4323 		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4324 			&ha->ms_iocb_dma);
4325 		if (!ha->ms_iocb)
4326 			goto fail_dma_pool;
4327 	/* Get consistent memory allocated for CT SNS commands */
4328 		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4329 			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4330 		if (!ha->ct_sns)
4331 			goto fail_free_ms_iocb;
4332 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4333 		    "ms_iocb=%p ct_sns=%p.\n",
4334 		    ha->ms_iocb, ha->ct_sns);
4335 	}
4336 
4337 	/* Allocate memory for request ring */
4338 	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4339 	if (!*req) {
4340 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4341 		    "Failed to allocate memory for req.\n");
4342 		goto fail_req;
4343 	}
4344 	(*req)->length = req_len;
4345 	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4346 		((*req)->length + 1) * sizeof(request_t),
4347 		&(*req)->dma, GFP_KERNEL);
4348 	if (!(*req)->ring) {
4349 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4350 		    "Failed to allocate memory for req_ring.\n");
4351 		goto fail_req_ring;
4352 	}
4353 	/* Allocate memory for response ring */
4354 	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4355 	if (!*rsp) {
4356 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4357 		    "Failed to allocate memory for rsp.\n");
4358 		goto fail_rsp;
4359 	}
4360 	(*rsp)->hw = ha;
4361 	(*rsp)->length = rsp_len;
4362 	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4363 		((*rsp)->length + 1) * sizeof(response_t),
4364 		&(*rsp)->dma, GFP_KERNEL);
4365 	if (!(*rsp)->ring) {
4366 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4367 		    "Failed to allocate memory for rsp_ring.\n");
4368 		goto fail_rsp_ring;
4369 	}
4370 	(*req)->rsp = *rsp;
4371 	(*rsp)->req = *req;
4372 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4373 	    "req=%p req->length=%d req->ring=%p rsp=%p "
4374 	    "rsp->length=%d rsp->ring=%p.\n",
4375 	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4376 	    (*rsp)->ring);
4377 	/* Allocate memory for NVRAM data for vports */
4378 	if (ha->nvram_npiv_size) {
4379 		ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4380 					sizeof(struct qla_npiv_entry),
4381 					GFP_KERNEL);
4382 		if (!ha->npiv_info) {
4383 			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4384 			    "Failed to allocate memory for npiv_info.\n");
4385 			goto fail_npiv_info;
4386 		}
4387 	} else
4388 		ha->npiv_info = NULL;
4389 
4390 	/* Get consistent memory allocated for EX-INIT-CB. */
4391 	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4392 	    IS_QLA28XX(ha)) {
4393 		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4394 		    &ha->ex_init_cb_dma);
4395 		if (!ha->ex_init_cb)
4396 			goto fail_ex_init_cb;
4397 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4398 		    "ex_init_cb=%p.\n", ha->ex_init_cb);
4399 	}
4400 
4401 	/* Get consistent memory allocated for Special Features-CB. */
4402 	if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4403 		ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4404 						&ha->sf_init_cb_dma);
4405 		if (!ha->sf_init_cb)
4406 			goto fail_sf_init_cb;
4407 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4408 			   "sf_init_cb=%p.\n", ha->sf_init_cb);
4409 	}
4410 
4411 
4412 	/* Get consistent memory allocated for Async Port-Database. */
4413 	if (!IS_FWI2_CAPABLE(ha)) {
4414 		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4415 			&ha->async_pd_dma);
4416 		if (!ha->async_pd)
4417 			goto fail_async_pd;
4418 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4419 		    "async_pd=%p.\n", ha->async_pd);
4420 	}
4421 
4422 	INIT_LIST_HEAD(&ha->vp_list);
4423 
4424 	/* Allocate memory for our loop_id bitmap */
4425 	ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4426 				  sizeof(long),
4427 				  GFP_KERNEL);
4428 	if (!ha->loop_id_map)
4429 		goto fail_loop_id_map;
4430 	else {
4431 		qla2x00_set_reserved_loop_ids(ha);
4432 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4433 		    "loop_id_map=%p.\n", ha->loop_id_map);
4434 	}
4435 
4436 	ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4437 	    SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4438 	if (!ha->sfp_data) {
4439 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4440 		    "Unable to allocate memory for SFP read-data.\n");
4441 		goto fail_sfp_data;
4442 	}
4443 
4444 	ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4445 	    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4446 	    GFP_KERNEL);
4447 	if (!ha->flt) {
4448 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4449 		    "Unable to allocate memory for FLT.\n");
4450 		goto fail_flt_buffer;
4451 	}
4452 
4453 	/* allocate the purex dma pool */
4454 	ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4455 	    ELS_MAX_PAYLOAD, 8, 0);
4456 
4457 	if (!ha->purex_dma_pool) {
4458 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4459 		    "Unable to allocate purex_dma_pool.\n");
4460 		goto fail_flt;
4461 	}
4462 
4463 	ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4464 	ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4465 					  ha->elsrej.size,
4466 					  &ha->elsrej.cdma,
4467 					  GFP_KERNEL);
4468 	if (!ha->elsrej.c) {
4469 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4470 		    "Alloc failed for els reject cmd.\n");
4471 		goto fail_elsrej;
4472 	}
4473 	ha->elsrej.c->er_cmd = ELS_LS_RJT;
4474 	ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4475 	ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4476 
4477 	ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4478 	ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4479 			&ha->lsrjt.cdma, GFP_KERNEL);
4480 	if (!ha->lsrjt.c) {
4481 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4482 			   "Alloc failed for nvme fc reject cmd.\n");
4483 		goto fail_lsrjt;
4484 	}
4485 
4486 	return 0;
4487 
4488 fail_lsrjt:
4489 	dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4490 			  ha->elsrej.c, ha->elsrej.cdma);
4491 fail_elsrej:
4492 	dma_pool_destroy(ha->purex_dma_pool);
4493 fail_flt:
4494 	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4495 	    ha->flt, ha->flt_dma);
4496 
4497 fail_flt_buffer:
4498 	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4499 	    ha->sfp_data, ha->sfp_data_dma);
4500 fail_sfp_data:
4501 	kfree(ha->loop_id_map);
4502 fail_loop_id_map:
4503 	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4504 fail_async_pd:
4505 	dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4506 fail_sf_init_cb:
4507 	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4508 fail_ex_init_cb:
4509 	kfree(ha->npiv_info);
4510 fail_npiv_info:
4511 	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4512 		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4513 	(*rsp)->ring = NULL;
4514 	(*rsp)->dma = 0;
4515 fail_rsp_ring:
4516 	kfree(*rsp);
4517 	*rsp = NULL;
4518 fail_rsp:
4519 	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4520 		sizeof(request_t), (*req)->ring, (*req)->dma);
4521 	(*req)->ring = NULL;
4522 	(*req)->dma = 0;
4523 fail_req_ring:
4524 	kfree(*req);
4525 	*req = NULL;
4526 fail_req:
4527 	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4528 		ha->ct_sns, ha->ct_sns_dma);
4529 	ha->ct_sns = NULL;
4530 	ha->ct_sns_dma = 0;
4531 fail_free_ms_iocb:
4532 	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4533 	ha->ms_iocb = NULL;
4534 	ha->ms_iocb_dma = 0;
4535 
4536 	if (ha->sns_cmd)
4537 		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4538 		    ha->sns_cmd, ha->sns_cmd_dma);
4539 fail_dma_pool:
4540 	if (ql2xenabledif) {
4541 		struct dsd_dma *dsd, *nxt;
4542 
4543 		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4544 		    list) {
4545 			list_del(&dsd->list);
4546 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4547 			    dsd->dsd_list_dma);
4548 			ha->dif_bundle_dma_allocs--;
4549 			kfree(dsd);
4550 			ha->dif_bundle_kallocs--;
4551 			ha->pool.unusable.count--;
4552 		}
4553 		dma_pool_destroy(ha->dif_bundl_pool);
4554 		ha->dif_bundl_pool = NULL;
4555 	}
4556 
4557 fail_dif_bundl_dma_pool:
4558 	if (IS_QLA82XX(ha) || ql2xenabledif) {
4559 		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4560 		ha->fcp_cmnd_dma_pool = NULL;
4561 	}
4562 fail_dl_dma_pool:
4563 	if (IS_QLA82XX(ha) || ql2xenabledif) {
4564 		dma_pool_destroy(ha->dl_dma_pool);
4565 		ha->dl_dma_pool = NULL;
4566 	}
4567 fail_s_dma_pool:
4568 	dma_pool_destroy(ha->s_dma_pool);
4569 	ha->s_dma_pool = NULL;
4570 fail_free_nvram:
4571 	kfree(ha->nvram);
4572 	ha->nvram = NULL;
4573 fail_free_ctx_mempool:
4574 	mempool_destroy(ha->ctx_mempool);
4575 	ha->ctx_mempool = NULL;
4576 fail_free_srb_mempool:
4577 	mempool_destroy(ha->srb_mempool);
4578 	ha->srb_mempool = NULL;
4579 fail_free_gid_list:
4580 	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4581 	ha->gid_list,
4582 	ha->gid_list_dma);
4583 	ha->gid_list = NULL;
4584 	ha->gid_list_dma = 0;
4585 fail_free_tgt_mem:
4586 	qlt_mem_free(ha);
4587 fail_free_btree:
4588 	btree_destroy32(&ha->host_map);
4589 fail_free_init_cb:
4590 	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4591 	ha->init_cb_dma);
4592 	ha->init_cb = NULL;
4593 	ha->init_cb_dma = 0;
4594 fail_free_vp_map:
4595 	kfree(ha->vp_map);
4596 fail:
4597 	ql_log(ql_log_fatal, NULL, 0x0030,
4598 	    "Memory allocation failure.\n");
4599 	return -ENOMEM;
4600 }
4601 
4602 int
4603 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4604 {
4605 	int rval;
4606 	uint16_t	size, max_cnt;
4607 	uint32_t temp;
4608 	struct qla_hw_data *ha = vha->hw;
4609 
4610 	/* Return if we don't need to alloacate any extended logins */
4611 	if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4612 		return QLA_SUCCESS;
4613 
4614 	if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4615 		return QLA_SUCCESS;
4616 
4617 	ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4618 	max_cnt = 0;
4619 	rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4620 	if (rval != QLA_SUCCESS) {
4621 		ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4622 		    "Failed to get exlogin status.\n");
4623 		return rval;
4624 	}
4625 
4626 	temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4627 	temp *= size;
4628 
4629 	if (temp != ha->exlogin_size) {
4630 		qla2x00_free_exlogin_buffer(ha);
4631 		ha->exlogin_size = temp;
4632 
4633 		ql_log(ql_log_info, vha, 0xd024,
4634 		    "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4635 		    max_cnt, size, temp);
4636 
4637 		ql_log(ql_log_info, vha, 0xd025,
4638 		    "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4639 
4640 		/* Get consistent memory for extended logins */
4641 		ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4642 			ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4643 		if (!ha->exlogin_buf) {
4644 			ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4645 		    "Failed to allocate memory for exlogin_buf_dma.\n");
4646 			return -ENOMEM;
4647 		}
4648 	}
4649 
4650 	/* Now configure the dma buffer */
4651 	rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4652 	if (rval) {
4653 		ql_log(ql_log_fatal, vha, 0xd033,
4654 		    "Setup extended login buffer  ****FAILED****.\n");
4655 		qla2x00_free_exlogin_buffer(ha);
4656 	}
4657 
4658 	return rval;
4659 }
4660 
4661 /*
4662 * qla2x00_free_exlogin_buffer
4663 *
4664 * Input:
4665 *	ha = adapter block pointer
4666 */
4667 void
4668 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4669 {
4670 	if (ha->exlogin_buf) {
4671 		dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4672 		    ha->exlogin_buf, ha->exlogin_buf_dma);
4673 		ha->exlogin_buf = NULL;
4674 		ha->exlogin_size = 0;
4675 	}
4676 }
4677 
4678 static void
4679 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4680 {
4681 	u32 temp;
4682 	struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4683 	*ret_cnt = FW_DEF_EXCHANGES_CNT;
4684 
4685 	if (max_cnt > vha->hw->max_exchg)
4686 		max_cnt = vha->hw->max_exchg;
4687 
4688 	if (qla_ini_mode_enabled(vha)) {
4689 		if (vha->ql2xiniexchg > max_cnt)
4690 			vha->ql2xiniexchg = max_cnt;
4691 
4692 		if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4693 			*ret_cnt = vha->ql2xiniexchg;
4694 
4695 	} else if (qla_tgt_mode_enabled(vha)) {
4696 		if (vha->ql2xexchoffld > max_cnt) {
4697 			vha->ql2xexchoffld = max_cnt;
4698 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4699 		}
4700 
4701 		if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4702 			*ret_cnt = vha->ql2xexchoffld;
4703 	} else if (qla_dual_mode_enabled(vha)) {
4704 		temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4705 		if (temp > max_cnt) {
4706 			vha->ql2xiniexchg -= (temp - max_cnt)/2;
4707 			vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4708 			temp = max_cnt;
4709 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4710 		}
4711 
4712 		if (temp > FW_DEF_EXCHANGES_CNT)
4713 			*ret_cnt = temp;
4714 	}
4715 }
4716 
4717 int
4718 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4719 {
4720 	int rval;
4721 	u16	size, max_cnt;
4722 	u32 actual_cnt, totsz;
4723 	struct qla_hw_data *ha = vha->hw;
4724 
4725 	if (!ha->flags.exchoffld_enabled)
4726 		return QLA_SUCCESS;
4727 
4728 	if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4729 		return QLA_SUCCESS;
4730 
4731 	max_cnt = 0;
4732 	rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4733 	if (rval != QLA_SUCCESS) {
4734 		ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4735 		    "Failed to get exlogin status.\n");
4736 		return rval;
4737 	}
4738 
4739 	qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4740 	ql_log(ql_log_info, vha, 0xd014,
4741 	    "Actual exchange offload count: %d.\n", actual_cnt);
4742 
4743 	totsz = actual_cnt * size;
4744 
4745 	if (totsz != ha->exchoffld_size) {
4746 		qla2x00_free_exchoffld_buffer(ha);
4747 		if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4748 			ha->exchoffld_size = 0;
4749 			ha->flags.exchoffld_enabled = 0;
4750 			return QLA_SUCCESS;
4751 		}
4752 
4753 		ha->exchoffld_size = totsz;
4754 
4755 		ql_log(ql_log_info, vha, 0xd016,
4756 		    "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4757 		    max_cnt, actual_cnt, size, totsz);
4758 
4759 		ql_log(ql_log_info, vha, 0xd017,
4760 		    "Exchange Buffers requested size = 0x%x\n",
4761 		    ha->exchoffld_size);
4762 
4763 		/* Get consistent memory for extended logins */
4764 		ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4765 			ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4766 		if (!ha->exchoffld_buf) {
4767 			ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4768 			"Failed to allocate memory for Exchange Offload.\n");
4769 
4770 			if (ha->max_exchg >
4771 			    (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4772 				ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4773 			} else if (ha->max_exchg >
4774 			    (FW_DEF_EXCHANGES_CNT + 512)) {
4775 				ha->max_exchg -= 512;
4776 			} else {
4777 				ha->flags.exchoffld_enabled = 0;
4778 				ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4779 				    "Disabling Exchange offload due to lack of memory\n");
4780 			}
4781 			ha->exchoffld_size = 0;
4782 
4783 			return -ENOMEM;
4784 		}
4785 	} else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4786 		/* pathological case */
4787 		qla2x00_free_exchoffld_buffer(ha);
4788 		ha->exchoffld_size = 0;
4789 		ha->flags.exchoffld_enabled = 0;
4790 		ql_log(ql_log_info, vha, 0xd016,
4791 		    "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4792 		    ha->exchoffld_size, actual_cnt, size, totsz);
4793 		return 0;
4794 	}
4795 
4796 	/* Now configure the dma buffer */
4797 	rval = qla_set_exchoffld_mem_cfg(vha);
4798 	if (rval) {
4799 		ql_log(ql_log_fatal, vha, 0xd02e,
4800 		    "Setup exchange offload buffer ****FAILED****.\n");
4801 		qla2x00_free_exchoffld_buffer(ha);
4802 	} else {
4803 		/* re-adjust number of target exchange */
4804 		struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4805 
4806 		if (qla_ini_mode_enabled(vha))
4807 			icb->exchange_count = 0;
4808 		else
4809 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4810 	}
4811 
4812 	return rval;
4813 }
4814 
4815 /*
4816 * qla2x00_free_exchoffld_buffer
4817 *
4818 * Input:
4819 *	ha = adapter block pointer
4820 */
4821 void
4822 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4823 {
4824 	if (ha->exchoffld_buf) {
4825 		dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4826 		    ha->exchoffld_buf, ha->exchoffld_buf_dma);
4827 		ha->exchoffld_buf = NULL;
4828 		ha->exchoffld_size = 0;
4829 	}
4830 }
4831 
4832 /*
4833 * qla2x00_free_fw_dump
4834 *	Frees fw dump stuff.
4835 *
4836 * Input:
4837 *	ha = adapter block pointer
4838 */
4839 static void
4840 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4841 {
4842 	struct fwdt *fwdt = ha->fwdt;
4843 	uint j;
4844 
4845 	if (ha->fce)
4846 		dma_free_coherent(&ha->pdev->dev,
4847 		    FCE_SIZE, ha->fce, ha->fce_dma);
4848 
4849 	if (ha->eft)
4850 		dma_free_coherent(&ha->pdev->dev,
4851 		    EFT_SIZE, ha->eft, ha->eft_dma);
4852 
4853 	vfree(ha->fw_dump);
4854 
4855 	ha->fce = NULL;
4856 	ha->fce_dma = 0;
4857 	ha->flags.fce_enabled = 0;
4858 	ha->eft = NULL;
4859 	ha->eft_dma = 0;
4860 	ha->fw_dumped = false;
4861 	ha->fw_dump_cap_flags = 0;
4862 	ha->fw_dump_reading = 0;
4863 	ha->fw_dump = NULL;
4864 	ha->fw_dump_len = 0;
4865 
4866 	for (j = 0; j < 2; j++, fwdt++) {
4867 		vfree(fwdt->template);
4868 		fwdt->template = NULL;
4869 		fwdt->length = 0;
4870 	}
4871 }
4872 
4873 /*
4874 * qla2x00_mem_free
4875 *      Frees all adapter allocated memory.
4876 *
4877 * Input:
4878 *      ha = adapter block pointer.
4879 */
4880 static void
4881 qla2x00_mem_free(struct qla_hw_data *ha)
4882 {
4883 	qla2x00_free_fw_dump(ha);
4884 
4885 	if (ha->mctp_dump)
4886 		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4887 		    ha->mctp_dump_dma);
4888 	ha->mctp_dump = NULL;
4889 
4890 	mempool_destroy(ha->srb_mempool);
4891 	ha->srb_mempool = NULL;
4892 
4893 	if (ha->dcbx_tlv)
4894 		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4895 		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
4896 	ha->dcbx_tlv = NULL;
4897 
4898 	if (ha->xgmac_data)
4899 		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4900 		    ha->xgmac_data, ha->xgmac_data_dma);
4901 	ha->xgmac_data = NULL;
4902 
4903 	if (ha->sns_cmd)
4904 		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4905 		ha->sns_cmd, ha->sns_cmd_dma);
4906 	ha->sns_cmd = NULL;
4907 	ha->sns_cmd_dma = 0;
4908 
4909 	if (ha->ct_sns)
4910 		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4911 		ha->ct_sns, ha->ct_sns_dma);
4912 	ha->ct_sns = NULL;
4913 	ha->ct_sns_dma = 0;
4914 
4915 	if (ha->sfp_data)
4916 		dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4917 		    ha->sfp_data_dma);
4918 	ha->sfp_data = NULL;
4919 
4920 	if (ha->flt)
4921 		dma_free_coherent(&ha->pdev->dev,
4922 		    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4923 		    ha->flt, ha->flt_dma);
4924 	ha->flt = NULL;
4925 	ha->flt_dma = 0;
4926 
4927 	if (ha->ms_iocb)
4928 		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4929 	ha->ms_iocb = NULL;
4930 	ha->ms_iocb_dma = 0;
4931 
4932 	if (ha->sf_init_cb)
4933 		dma_pool_free(ha->s_dma_pool,
4934 			      ha->sf_init_cb, ha->sf_init_cb_dma);
4935 
4936 	if (ha->ex_init_cb)
4937 		dma_pool_free(ha->s_dma_pool,
4938 			ha->ex_init_cb, ha->ex_init_cb_dma);
4939 	ha->ex_init_cb = NULL;
4940 	ha->ex_init_cb_dma = 0;
4941 
4942 	if (ha->async_pd)
4943 		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4944 	ha->async_pd = NULL;
4945 	ha->async_pd_dma = 0;
4946 
4947 	dma_pool_destroy(ha->s_dma_pool);
4948 	ha->s_dma_pool = NULL;
4949 
4950 	if (ha->gid_list)
4951 		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4952 		ha->gid_list, ha->gid_list_dma);
4953 	ha->gid_list = NULL;
4954 	ha->gid_list_dma = 0;
4955 
4956 	if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4957 		struct dsd_dma *dsd_ptr, *tdsd_ptr;
4958 
4959 		/* clean up allocated prev pool */
4960 		list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4961 					 &ha->base_qpair->dsd_list, list) {
4962 			dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4963 				      dsd_ptr->dsd_list_dma);
4964 			list_del(&dsd_ptr->list);
4965 			kfree(dsd_ptr);
4966 		}
4967 	}
4968 
4969 	dma_pool_destroy(ha->dl_dma_pool);
4970 	ha->dl_dma_pool = NULL;
4971 
4972 	dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4973 	ha->fcp_cmnd_dma_pool = NULL;
4974 
4975 	mempool_destroy(ha->ctx_mempool);
4976 	ha->ctx_mempool = NULL;
4977 
4978 	if (ql2xenabledif && ha->dif_bundl_pool) {
4979 		struct dsd_dma *dsd, *nxt;
4980 
4981 		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4982 					 list) {
4983 			list_del(&dsd->list);
4984 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4985 				      dsd->dsd_list_dma);
4986 			ha->dif_bundle_dma_allocs--;
4987 			kfree(dsd);
4988 			ha->dif_bundle_kallocs--;
4989 			ha->pool.unusable.count--;
4990 		}
4991 		list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4992 			list_del(&dsd->list);
4993 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4994 				      dsd->dsd_list_dma);
4995 			ha->dif_bundle_dma_allocs--;
4996 			kfree(dsd);
4997 			ha->dif_bundle_kallocs--;
4998 		}
4999 	}
5000 
5001 	dma_pool_destroy(ha->dif_bundl_pool);
5002 	ha->dif_bundl_pool = NULL;
5003 
5004 	qlt_mem_free(ha);
5005 	qla_remove_hostmap(ha);
5006 
5007 	if (ha->init_cb)
5008 		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5009 			ha->init_cb, ha->init_cb_dma);
5010 
5011 	dma_pool_destroy(ha->purex_dma_pool);
5012 	ha->purex_dma_pool = NULL;
5013 
5014 	if (ha->elsrej.c) {
5015 		dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5016 		    ha->elsrej.c, ha->elsrej.cdma);
5017 		ha->elsrej.c = NULL;
5018 	}
5019 
5020 	if (ha->lsrjt.c) {
5021 		dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5022 				  ha->lsrjt.cdma);
5023 		ha->lsrjt.c = NULL;
5024 	}
5025 
5026 	ha->init_cb = NULL;
5027 	ha->init_cb_dma = 0;
5028 
5029 	vfree(ha->optrom_buffer);
5030 	ha->optrom_buffer = NULL;
5031 	kfree(ha->nvram);
5032 	ha->nvram = NULL;
5033 	kfree(ha->npiv_info);
5034 	ha->npiv_info = NULL;
5035 	kfree(ha->swl);
5036 	ha->swl = NULL;
5037 	kfree(ha->loop_id_map);
5038 	ha->sf_init_cb = NULL;
5039 	ha->sf_init_cb_dma = 0;
5040 	ha->loop_id_map = NULL;
5041 
5042 	kfree(ha->vp_map);
5043 	ha->vp_map = NULL;
5044 }
5045 
5046 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5047 					  struct qla_hw_data *ha)
5048 {
5049 	struct Scsi_Host *host;
5050 	struct scsi_qla_host *vha = NULL;
5051 
5052 	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5053 	if (!host) {
5054 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5055 		    "Failed to allocate host from the scsi layer, aborting.\n");
5056 		return NULL;
5057 	}
5058 
5059 	/* Clear our data area */
5060 	vha = shost_priv(host);
5061 	memset(vha, 0, sizeof(scsi_qla_host_t));
5062 
5063 	vha->host = host;
5064 	vha->host_no = host->host_no;
5065 	vha->hw = ha;
5066 
5067 	vha->qlini_mode = ql2x_ini_mode;
5068 	vha->ql2xexchoffld = ql2xexchoffld;
5069 	vha->ql2xiniexchg = ql2xiniexchg;
5070 
5071 	INIT_LIST_HEAD(&vha->vp_fcports);
5072 	INIT_LIST_HEAD(&vha->work_list);
5073 	INIT_LIST_HEAD(&vha->list);
5074 	INIT_LIST_HEAD(&vha->qla_cmd_list);
5075 	INIT_LIST_HEAD(&vha->logo_list);
5076 	INIT_LIST_HEAD(&vha->plogi_ack_list);
5077 	INIT_LIST_HEAD(&vha->qp_list);
5078 	INIT_LIST_HEAD(&vha->gnl.fcports);
5079 	INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5080 
5081 	INIT_LIST_HEAD(&vha->purex_list.head);
5082 	spin_lock_init(&vha->purex_list.lock);
5083 
5084 	spin_lock_init(&vha->work_lock);
5085 	spin_lock_init(&vha->cmd_list_lock);
5086 	init_waitqueue_head(&vha->fcport_waitQ);
5087 	init_waitqueue_head(&vha->vref_waitq);
5088 	qla_enode_init(vha);
5089 	qla_edb_init(vha);
5090 
5091 
5092 	vha->gnl.size = sizeof(struct get_name_list_extended) *
5093 			(ha->max_loop_id + 1);
5094 	vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5095 	    vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5096 	if (!vha->gnl.l) {
5097 		ql_log(ql_log_fatal, vha, 0xd04a,
5098 		    "Alloc failed for name list.\n");
5099 		scsi_host_put(vha->host);
5100 		return NULL;
5101 	}
5102 
5103 	/* todo: what about ext login? */
5104 	vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5105 	vha->scan.l = vmalloc(vha->scan.size);
5106 	if (!vha->scan.l) {
5107 		ql_log(ql_log_fatal, vha, 0xd04a,
5108 		    "Alloc failed for scan database.\n");
5109 		dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5110 		    vha->gnl.l, vha->gnl.ldma);
5111 		vha->gnl.l = NULL;
5112 		scsi_host_put(vha->host);
5113 		return NULL;
5114 	}
5115 	INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5116 
5117 	snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5118 		 QLA2XXX_DRIVER_NAME, vha->host_no);
5119 	ql_dbg(ql_dbg_init, vha, 0x0041,
5120 	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5121 	    vha->host, vha->hw, vha,
5122 	    dev_name(&(ha->pdev->dev)));
5123 
5124 	return vha;
5125 }
5126 
5127 struct qla_work_evt *
5128 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5129 {
5130 	struct qla_work_evt *e;
5131 
5132 	if (test_bit(UNLOADING, &vha->dpc_flags))
5133 		return NULL;
5134 
5135 	if (qla_vha_mark_busy(vha))
5136 		return NULL;
5137 
5138 	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5139 	if (!e) {
5140 		QLA_VHA_MARK_NOT_BUSY(vha);
5141 		return NULL;
5142 	}
5143 
5144 	INIT_LIST_HEAD(&e->list);
5145 	e->type = type;
5146 	e->flags = QLA_EVT_FLAG_FREE;
5147 	return e;
5148 }
5149 
5150 int
5151 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5152 {
5153 	unsigned long flags;
5154 	bool q = false;
5155 
5156 	spin_lock_irqsave(&vha->work_lock, flags);
5157 	list_add_tail(&e->list, &vha->work_list);
5158 
5159 	if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5160 		q = true;
5161 
5162 	spin_unlock_irqrestore(&vha->work_lock, flags);
5163 
5164 	if (q)
5165 		queue_work(vha->hw->wq, &vha->iocb_work);
5166 
5167 	return QLA_SUCCESS;
5168 }
5169 
5170 int
5171 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5172     u32 data)
5173 {
5174 	struct qla_work_evt *e;
5175 
5176 	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5177 	if (!e)
5178 		return QLA_FUNCTION_FAILED;
5179 
5180 	e->u.aen.code = code;
5181 	e->u.aen.data = data;
5182 	return qla2x00_post_work(vha, e);
5183 }
5184 
5185 int
5186 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5187 {
5188 	struct qla_work_evt *e;
5189 
5190 	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5191 	if (!e)
5192 		return QLA_FUNCTION_FAILED;
5193 
5194 	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5195 	return qla2x00_post_work(vha, e);
5196 }
5197 
5198 #define qla2x00_post_async_work(name, type)	\
5199 int qla2x00_post_async_##name##_work(		\
5200     struct scsi_qla_host *vha,			\
5201     fc_port_t *fcport, uint16_t *data)		\
5202 {						\
5203 	struct qla_work_evt *e;			\
5204 						\
5205 	e = qla2x00_alloc_work(vha, type);	\
5206 	if (!e)					\
5207 		return QLA_FUNCTION_FAILED;	\
5208 						\
5209 	e->u.logio.fcport = fcport;		\
5210 	if (data) {				\
5211 		e->u.logio.data[0] = data[0];	\
5212 		e->u.logio.data[1] = data[1];	\
5213 	}					\
5214 	fcport->flags |= FCF_ASYNC_ACTIVE;	\
5215 	return qla2x00_post_work(vha, e);	\
5216 }
5217 
5218 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5219 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5220 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5221 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5222 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5223 
5224 int
5225 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5226 {
5227 	struct qla_work_evt *e;
5228 
5229 	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5230 	if (!e)
5231 		return QLA_FUNCTION_FAILED;
5232 
5233 	e->u.uevent.code = code;
5234 	return qla2x00_post_work(vha, e);
5235 }
5236 
5237 static void
5238 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5239 {
5240 	char event_string[40];
5241 	char *envp[] = { event_string, NULL };
5242 
5243 	switch (code) {
5244 	case QLA_UEVENT_CODE_FW_DUMP:
5245 		snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5246 		    vha->host_no);
5247 		break;
5248 	default:
5249 		/* do nothing */
5250 		break;
5251 	}
5252 	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5253 }
5254 
5255 int
5256 qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
5257 			uint32_t *data, int cnt)
5258 {
5259 	struct qla_work_evt *e;
5260 
5261 	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5262 	if (!e)
5263 		return QLA_FUNCTION_FAILED;
5264 
5265 	e->u.aenfx.evtcode = evtcode;
5266 	e->u.aenfx.count = cnt;
5267 	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5268 	return qla2x00_post_work(vha, e);
5269 }
5270 
5271 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5272 {
5273 	unsigned long flags;
5274 
5275 	if (IS_SW_RESV_ADDR(fcport->d_id))
5276 		return;
5277 
5278 	spin_lock_irqsave(&fcport->vha->work_lock, flags);
5279 	if (fcport->disc_state == DSC_UPD_FCPORT) {
5280 		spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5281 		return;
5282 	}
5283 	fcport->jiffies_at_registration = jiffies;
5284 	fcport->sec_since_registration = 0;
5285 	fcport->next_disc_state = DSC_DELETED;
5286 	qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5287 	spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5288 
5289 	queue_work(system_unbound_wq, &fcport->reg_work);
5290 }
5291 
5292 static
5293 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5294 {
5295 	unsigned long flags;
5296 	fc_port_t *fcport =  NULL, *tfcp;
5297 	struct qlt_plogi_ack_t *pla =
5298 	    (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5299 	uint8_t free_fcport = 0;
5300 
5301 	ql_dbg(ql_dbg_disc, vha, 0xffff,
5302 	    "%s %d %8phC enter\n",
5303 	    __func__, __LINE__, e->u.new_sess.port_name);
5304 
5305 	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5306 	fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5307 	if (fcport) {
5308 		fcport->d_id = e->u.new_sess.id;
5309 		if (pla) {
5310 			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5311 			memcpy(fcport->node_name,
5312 			    pla->iocb.u.isp24.u.plogi.node_name,
5313 			    WWN_SIZE);
5314 			qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5315 			/* we took an extra ref_count to prevent PLOGI ACK when
5316 			 * fcport/sess has not been created.
5317 			 */
5318 			pla->ref_count--;
5319 		}
5320 	} else {
5321 		spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5322 		fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5323 		if (fcport) {
5324 			fcport->d_id = e->u.new_sess.id;
5325 			fcport->flags |= FCF_FABRIC_DEVICE;
5326 			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5327 			fcport->tgt_short_link_down_cnt = 0;
5328 
5329 			memcpy(fcport->port_name, e->u.new_sess.port_name,
5330 			    WWN_SIZE);
5331 
5332 			fcport->fc4_type = e->u.new_sess.fc4_type;
5333 			if (NVME_PRIORITY(vha->hw, fcport))
5334 				fcport->do_prli_nvme = 1;
5335 			else
5336 				fcport->do_prli_nvme = 0;
5337 
5338 			if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5339 				fcport->dm_login_expire = jiffies +
5340 					QLA_N2N_WAIT_TIME * HZ;
5341 				fcport->fc4_type = FS_FC4TYPE_FCP;
5342 				fcport->n2n_flag = 1;
5343 				if (vha->flags.nvme_enabled)
5344 					fcport->fc4_type |= FS_FC4TYPE_NVME;
5345 			}
5346 
5347 		} else {
5348 			ql_dbg(ql_dbg_disc, vha, 0xffff,
5349 				   "%s %8phC mem alloc fail.\n",
5350 				   __func__, e->u.new_sess.port_name);
5351 
5352 			if (pla) {
5353 				list_del(&pla->list);
5354 				kmem_cache_free(qla_tgt_plogi_cachep, pla);
5355 			}
5356 			return;
5357 		}
5358 
5359 		spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5360 		/* search again to make sure no one else got ahead */
5361 		tfcp = qla2x00_find_fcport_by_wwpn(vha,
5362 		    e->u.new_sess.port_name, 1);
5363 		if (tfcp) {
5364 			/* should rarily happen */
5365 			ql_dbg(ql_dbg_disc, vha, 0xffff,
5366 			    "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5367 			    __func__, tfcp->port_name, tfcp->disc_state,
5368 			    tfcp->fw_login_state);
5369 
5370 			free_fcport = 1;
5371 		} else {
5372 			list_add_tail(&fcport->list, &vha->vp_fcports);
5373 
5374 		}
5375 		if (pla) {
5376 			qlt_plogi_ack_link(vha, pla, fcport,
5377 			    QLT_PLOGI_LINK_SAME_WWN);
5378 			pla->ref_count--;
5379 		}
5380 	}
5381 	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5382 
5383 	if (fcport) {
5384 		fcport->id_changed = 1;
5385 		fcport->scan_state = QLA_FCPORT_FOUND;
5386 		fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5387 		memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5388 
5389 		if (pla) {
5390 			if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5391 				u16 wd3_lo;
5392 
5393 				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5394 				fcport->local = 0;
5395 				fcport->loop_id =
5396 					le16_to_cpu(
5397 					    pla->iocb.u.isp24.nport_handle);
5398 				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5399 				wd3_lo =
5400 				    le16_to_cpu(
5401 					pla->iocb.u.isp24.u.prli.wd3_lo);
5402 
5403 				if (wd3_lo & BIT_7)
5404 					fcport->conf_compl_supported = 1;
5405 
5406 				if ((wd3_lo & BIT_4) == 0)
5407 					fcport->port_type = FCT_INITIATOR;
5408 				else
5409 					fcport->port_type = FCT_TARGET;
5410 			}
5411 			qlt_plogi_ack_unref(vha, pla);
5412 		} else {
5413 			fc_port_t *dfcp = NULL;
5414 
5415 			spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5416 			tfcp = qla2x00_find_fcport_by_nportid(vha,
5417 			    &e->u.new_sess.id, 1);
5418 			if (tfcp && (tfcp != fcport)) {
5419 				/*
5420 				 * We have a conflict fcport with same NportID.
5421 				 */
5422 				ql_dbg(ql_dbg_disc, vha, 0xffff,
5423 				    "%s %8phC found conflict b4 add. DS %d LS %d\n",
5424 				    __func__, tfcp->port_name, tfcp->disc_state,
5425 				    tfcp->fw_login_state);
5426 
5427 				switch (tfcp->disc_state) {
5428 				case DSC_DELETED:
5429 					break;
5430 				case DSC_DELETE_PEND:
5431 					fcport->login_pause = 1;
5432 					tfcp->conflict = fcport;
5433 					break;
5434 				default:
5435 					fcport->login_pause = 1;
5436 					tfcp->conflict = fcport;
5437 					dfcp = tfcp;
5438 					break;
5439 				}
5440 			}
5441 			spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5442 			if (dfcp)
5443 				qlt_schedule_sess_for_deletion(tfcp);
5444 
5445 			if (N2N_TOPO(vha->hw)) {
5446 				fcport->flags &= ~FCF_FABRIC_DEVICE;
5447 				fcport->keep_nport_handle = 1;
5448 				if (vha->flags.nvme_enabled) {
5449 					fcport->fc4_type =
5450 					    (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5451 					fcport->n2n_flag = 1;
5452 				}
5453 				fcport->fw_login_state = 0;
5454 
5455 				schedule_delayed_work(&vha->scan.scan_work, 5);
5456 			} else {
5457 				qla24xx_fcport_handle_login(vha, fcport);
5458 			}
5459 		}
5460 	}
5461 
5462 	if (free_fcport) {
5463 		qla2x00_free_fcport(fcport);
5464 		if (pla) {
5465 			list_del(&pla->list);
5466 			kmem_cache_free(qla_tgt_plogi_cachep, pla);
5467 		}
5468 	}
5469 }
5470 
5471 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5472 {
5473 	struct srb *sp = e->u.iosb.sp;
5474 	int rval;
5475 
5476 	rval = qla2x00_start_sp(sp);
5477 	if (rval != QLA_SUCCESS) {
5478 		ql_dbg(ql_dbg_disc, vha, 0x2043,
5479 		    "%s: %s: Re-issue IOCB failed (%d).\n",
5480 		    __func__, sp->name, rval);
5481 		qla24xx_sp_unmap(vha, sp);
5482 	}
5483 }
5484 
5485 void
5486 qla2x00_do_work(struct scsi_qla_host *vha)
5487 {
5488 	struct qla_work_evt *e, *tmp;
5489 	unsigned long flags;
5490 	LIST_HEAD(work);
5491 	int rc;
5492 
5493 	spin_lock_irqsave(&vha->work_lock, flags);
5494 	list_splice_init(&vha->work_list, &work);
5495 	spin_unlock_irqrestore(&vha->work_lock, flags);
5496 
5497 	list_for_each_entry_safe(e, tmp, &work, list) {
5498 		rc = QLA_SUCCESS;
5499 		switch (e->type) {
5500 		case QLA_EVT_AEN:
5501 			fc_host_post_event(vha->host, fc_get_event_number(),
5502 			    e->u.aen.code, e->u.aen.data);
5503 			break;
5504 		case QLA_EVT_IDC_ACK:
5505 			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5506 			break;
5507 		case QLA_EVT_ASYNC_LOGIN:
5508 			qla2x00_async_login(vha, e->u.logio.fcport,
5509 			    e->u.logio.data);
5510 			break;
5511 		case QLA_EVT_ASYNC_LOGOUT:
5512 			rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5513 			break;
5514 		case QLA_EVT_ASYNC_ADISC:
5515 			qla2x00_async_adisc(vha, e->u.logio.fcport,
5516 			    e->u.logio.data);
5517 			break;
5518 		case QLA_EVT_UEVENT:
5519 			qla2x00_uevent_emit(vha, e->u.uevent.code);
5520 			break;
5521 		case QLA_EVT_AENFX:
5522 			qlafx00_process_aen(vha, e);
5523 			break;
5524 		case QLA_EVT_UNMAP:
5525 			qla24xx_sp_unmap(vha, e->u.iosb.sp);
5526 			break;
5527 		case QLA_EVT_RELOGIN:
5528 			qla2x00_relogin(vha);
5529 			break;
5530 		case QLA_EVT_NEW_SESS:
5531 			qla24xx_create_new_sess(vha, e);
5532 			break;
5533 		case QLA_EVT_GPDB:
5534 			qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5535 			    e->u.fcport.opt);
5536 			break;
5537 		case QLA_EVT_PRLI:
5538 			qla24xx_async_prli(vha, e->u.fcport.fcport);
5539 			break;
5540 		case QLA_EVT_GPSC:
5541 			qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5542 			break;
5543 		case QLA_EVT_GNL:
5544 			qla24xx_async_gnl(vha, e->u.fcport.fcport);
5545 			break;
5546 		case QLA_EVT_NACK:
5547 			qla24xx_do_nack_work(vha, e);
5548 			break;
5549 		case QLA_EVT_ASYNC_PRLO:
5550 			rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5551 			break;
5552 		case QLA_EVT_ASYNC_PRLO_DONE:
5553 			qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5554 			    e->u.logio.data);
5555 			break;
5556 		case QLA_EVT_GPNFT:
5557 			qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5558 			    e->u.gpnft.sp);
5559 			break;
5560 		case QLA_EVT_GPNFT_DONE:
5561 			qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5562 			break;
5563 		case QLA_EVT_GNNFT_DONE:
5564 			qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5565 			break;
5566 		case QLA_EVT_GFPNID:
5567 			qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5568 			break;
5569 		case QLA_EVT_SP_RETRY:
5570 			qla_sp_retry(vha, e);
5571 			break;
5572 		case QLA_EVT_IIDMA:
5573 			qla_do_iidma_work(vha, e->u.fcport.fcport);
5574 			break;
5575 		case QLA_EVT_ELS_PLOGI:
5576 			qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5577 			    e->u.fcport.fcport, false);
5578 			break;
5579 		case QLA_EVT_SA_REPLACE:
5580 			rc = qla24xx_issue_sa_replace_iocb(vha, e);
5581 			break;
5582 		}
5583 
5584 		if (rc == EAGAIN) {
5585 			/* put 'work' at head of 'vha->work_list' */
5586 			spin_lock_irqsave(&vha->work_lock, flags);
5587 			list_splice(&work, &vha->work_list);
5588 			spin_unlock_irqrestore(&vha->work_lock, flags);
5589 			break;
5590 		}
5591 		list_del_init(&e->list);
5592 		if (e->flags & QLA_EVT_FLAG_FREE)
5593 			kfree(e);
5594 
5595 		/* For each work completed decrement vha ref count */
5596 		QLA_VHA_MARK_NOT_BUSY(vha);
5597 	}
5598 }
5599 
5600 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5601 {
5602 	struct qla_work_evt *e;
5603 
5604 	e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5605 
5606 	if (!e) {
5607 		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5608 		return QLA_FUNCTION_FAILED;
5609 	}
5610 
5611 	return qla2x00_post_work(vha, e);
5612 }
5613 
5614 /* Relogins all the fcports of a vport
5615  * Context: dpc thread
5616  */
5617 void qla2x00_relogin(struct scsi_qla_host *vha)
5618 {
5619 	fc_port_t       *fcport;
5620 	int status, relogin_needed = 0;
5621 	struct event_arg ea;
5622 
5623 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
5624 		/*
5625 		 * If the port is not ONLINE then try to login
5626 		 * to it if we haven't run out of retries.
5627 		 */
5628 		if (atomic_read(&fcport->state) != FCS_ONLINE &&
5629 		    fcport->login_retry) {
5630 			if (fcport->scan_state != QLA_FCPORT_FOUND ||
5631 			    fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5632 			    fcport->disc_state == DSC_LOGIN_COMPLETE)
5633 				continue;
5634 
5635 			if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5636 				fcport->disc_state == DSC_DELETE_PEND) {
5637 				relogin_needed = 1;
5638 			} else {
5639 				if (vha->hw->current_topology != ISP_CFG_NL) {
5640 					memset(&ea, 0, sizeof(ea));
5641 					ea.fcport = fcport;
5642 					qla24xx_handle_relogin_event(vha, &ea);
5643 				} else if (vha->hw->current_topology ==
5644 					 ISP_CFG_NL &&
5645 					IS_QLA2XXX_MIDTYPE(vha->hw)) {
5646 					(void)qla24xx_fcport_handle_login(vha,
5647 									fcport);
5648 				} else if (vha->hw->current_topology ==
5649 				    ISP_CFG_NL) {
5650 					fcport->login_retry--;
5651 					status =
5652 					    qla2x00_local_device_login(vha,
5653 						fcport);
5654 					if (status == QLA_SUCCESS) {
5655 						fcport->old_loop_id =
5656 						    fcport->loop_id;
5657 						ql_dbg(ql_dbg_disc, vha, 0x2003,
5658 						    "Port login OK: logged in ID 0x%x.\n",
5659 						    fcport->loop_id);
5660 						qla2x00_update_fcport
5661 							(vha, fcport);
5662 					} else if (status == 1) {
5663 						set_bit(RELOGIN_NEEDED,
5664 						    &vha->dpc_flags);
5665 						/* retry the login again */
5666 						ql_dbg(ql_dbg_disc, vha, 0x2007,
5667 						    "Retrying %d login again loop_id 0x%x.\n",
5668 						    fcport->login_retry,
5669 						    fcport->loop_id);
5670 					} else {
5671 						fcport->login_retry = 0;
5672 					}
5673 
5674 					if (fcport->login_retry == 0 &&
5675 					    status != QLA_SUCCESS)
5676 						qla2x00_clear_loop_id(fcport);
5677 				}
5678 			}
5679 		}
5680 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5681 			break;
5682 	}
5683 
5684 	if (relogin_needed)
5685 		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5686 
5687 	ql_dbg(ql_dbg_disc, vha, 0x400e,
5688 	    "Relogin end.\n");
5689 }
5690 
5691 /* Schedule work on any of the dpc-workqueues */
5692 void
5693 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5694 {
5695 	struct qla_hw_data *ha = base_vha->hw;
5696 
5697 	switch (work_code) {
5698 	case MBA_IDC_AEN: /* 0x8200 */
5699 		if (ha->dpc_lp_wq)
5700 			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5701 		break;
5702 
5703 	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5704 		if (!ha->flags.nic_core_reset_hdlr_active) {
5705 			if (ha->dpc_hp_wq)
5706 				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5707 		} else
5708 			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5709 			    "NIC Core reset is already active. Skip "
5710 			    "scheduling it again.\n");
5711 		break;
5712 	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5713 		if (ha->dpc_hp_wq)
5714 			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5715 		break;
5716 	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5717 		if (ha->dpc_hp_wq)
5718 			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5719 		break;
5720 	default:
5721 		ql_log(ql_log_warn, base_vha, 0xb05f,
5722 		    "Unknown work-code=0x%x.\n", work_code);
5723 	}
5724 
5725 	return;
5726 }
5727 
5728 /* Work: Perform NIC Core Unrecoverable state handling */
5729 void
5730 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5731 {
5732 	struct qla_hw_data *ha =
5733 		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5734 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5735 	uint32_t dev_state = 0;
5736 
5737 	qla83xx_idc_lock(base_vha, 0);
5738 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5739 	qla83xx_reset_ownership(base_vha);
5740 	if (ha->flags.nic_core_reset_owner) {
5741 		ha->flags.nic_core_reset_owner = 0;
5742 		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5743 		    QLA8XXX_DEV_FAILED);
5744 		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5745 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5746 	}
5747 	qla83xx_idc_unlock(base_vha, 0);
5748 }
5749 
5750 /* Work: Execute IDC state handler */
5751 void
5752 qla83xx_idc_state_handler_work(struct work_struct *work)
5753 {
5754 	struct qla_hw_data *ha =
5755 		container_of(work, struct qla_hw_data, idc_state_handler);
5756 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5757 	uint32_t dev_state = 0;
5758 
5759 	qla83xx_idc_lock(base_vha, 0);
5760 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5761 	if (dev_state == QLA8XXX_DEV_FAILED ||
5762 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5763 		qla83xx_idc_state_handler(base_vha);
5764 	qla83xx_idc_unlock(base_vha, 0);
5765 }
5766 
5767 static int
5768 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5769 {
5770 	int rval = QLA_SUCCESS;
5771 	unsigned long heart_beat_wait = jiffies + (1 * HZ);
5772 	uint32_t heart_beat_counter1, heart_beat_counter2;
5773 
5774 	do {
5775 		if (time_after(jiffies, heart_beat_wait)) {
5776 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5777 			    "Nic Core f/w is not alive.\n");
5778 			rval = QLA_FUNCTION_FAILED;
5779 			break;
5780 		}
5781 
5782 		qla83xx_idc_lock(base_vha, 0);
5783 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5784 		    &heart_beat_counter1);
5785 		qla83xx_idc_unlock(base_vha, 0);
5786 		msleep(100);
5787 		qla83xx_idc_lock(base_vha, 0);
5788 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5789 		    &heart_beat_counter2);
5790 		qla83xx_idc_unlock(base_vha, 0);
5791 	} while (heart_beat_counter1 == heart_beat_counter2);
5792 
5793 	return rval;
5794 }
5795 
5796 /* Work: Perform NIC Core Reset handling */
5797 void
5798 qla83xx_nic_core_reset_work(struct work_struct *work)
5799 {
5800 	struct qla_hw_data *ha =
5801 		container_of(work, struct qla_hw_data, nic_core_reset);
5802 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5803 	uint32_t dev_state = 0;
5804 
5805 	if (IS_QLA2031(ha)) {
5806 		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5807 			ql_log(ql_log_warn, base_vha, 0xb081,
5808 			    "Failed to dump mctp\n");
5809 		return;
5810 	}
5811 
5812 	if (!ha->flags.nic_core_reset_hdlr_active) {
5813 		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5814 			qla83xx_idc_lock(base_vha, 0);
5815 			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5816 			    &dev_state);
5817 			qla83xx_idc_unlock(base_vha, 0);
5818 			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5819 				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5820 				    "Nic Core f/w is alive.\n");
5821 				return;
5822 			}
5823 		}
5824 
5825 		ha->flags.nic_core_reset_hdlr_active = 1;
5826 		if (qla83xx_nic_core_reset(base_vha)) {
5827 			/* NIC Core reset failed. */
5828 			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5829 			    "NIC Core reset failed.\n");
5830 		}
5831 		ha->flags.nic_core_reset_hdlr_active = 0;
5832 	}
5833 }
5834 
5835 /* Work: Handle 8200 IDC aens */
5836 void
5837 qla83xx_service_idc_aen(struct work_struct *work)
5838 {
5839 	struct qla_hw_data *ha =
5840 		container_of(work, struct qla_hw_data, idc_aen);
5841 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5842 	uint32_t dev_state, idc_control;
5843 
5844 	qla83xx_idc_lock(base_vha, 0);
5845 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5846 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5847 	qla83xx_idc_unlock(base_vha, 0);
5848 	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5849 		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5850 			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5851 			    "Application requested NIC Core Reset.\n");
5852 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5853 		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5854 		    QLA_SUCCESS) {
5855 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5856 			    "Other protocol driver requested NIC Core Reset.\n");
5857 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5858 		}
5859 	} else if (dev_state == QLA8XXX_DEV_FAILED ||
5860 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5861 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5862 	}
5863 }
5864 
5865 /*
5866  * Control the frequency of IDC lock retries
5867  */
5868 #define QLA83XX_WAIT_LOGIC_MS	100
5869 
5870 static int
5871 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5872 {
5873 	int rval;
5874 	uint32_t data;
5875 	uint32_t idc_lck_rcvry_stage_mask = 0x3;
5876 	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5877 	struct qla_hw_data *ha = base_vha->hw;
5878 
5879 	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5880 	    "Trying force recovery of the IDC lock.\n");
5881 
5882 	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5883 	if (rval)
5884 		return rval;
5885 
5886 	if ((data & idc_lck_rcvry_stage_mask) > 0) {
5887 		return QLA_SUCCESS;
5888 	} else {
5889 		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5890 		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5891 		    data);
5892 		if (rval)
5893 			return rval;
5894 
5895 		msleep(200);
5896 
5897 		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5898 		    &data);
5899 		if (rval)
5900 			return rval;
5901 
5902 		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5903 			data &= (IDC_LOCK_RECOVERY_STAGE2 |
5904 					~(idc_lck_rcvry_stage_mask));
5905 			rval = qla83xx_wr_reg(base_vha,
5906 			    QLA83XX_IDC_LOCK_RECOVERY, data);
5907 			if (rval)
5908 				return rval;
5909 
5910 			/* Forcefully perform IDC UnLock */
5911 			rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5912 			    &data);
5913 			if (rval)
5914 				return rval;
5915 			/* Clear lock-id by setting 0xff */
5916 			rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5917 			    0xff);
5918 			if (rval)
5919 				return rval;
5920 			/* Clear lock-recovery by setting 0x0 */
5921 			rval = qla83xx_wr_reg(base_vha,
5922 			    QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5923 			if (rval)
5924 				return rval;
5925 		} else
5926 			return QLA_SUCCESS;
5927 	}
5928 
5929 	return rval;
5930 }
5931 
5932 static int
5933 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5934 {
5935 	int rval = QLA_SUCCESS;
5936 	uint32_t o_drv_lockid, n_drv_lockid;
5937 	unsigned long lock_recovery_timeout;
5938 
5939 	lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5940 retry_lockid:
5941 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5942 	if (rval)
5943 		goto exit;
5944 
5945 	/* MAX wait time before forcing IDC Lock recovery = 2 secs */
5946 	if (time_after_eq(jiffies, lock_recovery_timeout)) {
5947 		if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5948 			return QLA_SUCCESS;
5949 		else
5950 			return QLA_FUNCTION_FAILED;
5951 	}
5952 
5953 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5954 	if (rval)
5955 		goto exit;
5956 
5957 	if (o_drv_lockid == n_drv_lockid) {
5958 		msleep(QLA83XX_WAIT_LOGIC_MS);
5959 		goto retry_lockid;
5960 	} else
5961 		return QLA_SUCCESS;
5962 
5963 exit:
5964 	return rval;
5965 }
5966 
5967 /*
5968  * Context: task, can sleep
5969  */
5970 void
5971 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5972 {
5973 	uint32_t data;
5974 	uint32_t lock_owner;
5975 	struct qla_hw_data *ha = base_vha->hw;
5976 
5977 	might_sleep();
5978 
5979 	/* IDC-lock implementation using driver-lock/lock-id remote registers */
5980 retry_lock:
5981 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5982 	    == QLA_SUCCESS) {
5983 		if (data) {
5984 			/* Setting lock-id to our function-number */
5985 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5986 			    ha->portnum);
5987 		} else {
5988 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5989 			    &lock_owner);
5990 			ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5991 			    "Failed to acquire IDC lock, acquired by %d, "
5992 			    "retrying...\n", lock_owner);
5993 
5994 			/* Retry/Perform IDC-Lock recovery */
5995 			if (qla83xx_idc_lock_recovery(base_vha)
5996 			    == QLA_SUCCESS) {
5997 				msleep(QLA83XX_WAIT_LOGIC_MS);
5998 				goto retry_lock;
5999 			} else
6000 				ql_log(ql_log_warn, base_vha, 0xb075,
6001 				    "IDC Lock recovery FAILED.\n");
6002 		}
6003 
6004 	}
6005 
6006 	return;
6007 }
6008 
6009 static bool
6010 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6011 	struct purex_entry_24xx *purex)
6012 {
6013 	char fwstr[16];
6014 	u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6015 	struct port_database_24xx *pdb;
6016 
6017 	/* Domain Controller is always logged-out. */
6018 	/* if RDP request is not from Domain Controller: */
6019 	if (sid != 0xfffc01)
6020 		return false;
6021 
6022 	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6023 
6024 	pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6025 	if (!pdb) {
6026 		ql_dbg(ql_dbg_init, vha, 0x0181,
6027 		    "%s: Failed allocate pdb\n", __func__);
6028 	} else if (qla24xx_get_port_database(vha,
6029 				le16_to_cpu(purex->nport_handle), pdb)) {
6030 		ql_dbg(ql_dbg_init, vha, 0x0181,
6031 		    "%s: Failed get pdb sid=%x\n", __func__, sid);
6032 	} else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6033 	    pdb->current_login_state != PDS_PRLI_COMPLETE) {
6034 		ql_dbg(ql_dbg_init, vha, 0x0181,
6035 		    "%s: Port not logged in sid=%#x\n", __func__, sid);
6036 	} else {
6037 		/* RDP request is from logged in port */
6038 		kfree(pdb);
6039 		return false;
6040 	}
6041 	kfree(pdb);
6042 
6043 	vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6044 	fwstr[strcspn(fwstr, " ")] = 0;
6045 	/* if FW version allows RDP response length upto 2048 bytes: */
6046 	if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6047 		return false;
6048 
6049 	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6050 
6051 	/* RDP response length is to be reduced to maximum 256 bytes */
6052 	return true;
6053 }
6054 
6055 /*
6056  * Function Name: qla24xx_process_purex_iocb
6057  *
6058  * Description:
6059  * Prepare a RDP response and send to Fabric switch
6060  *
6061  * PARAMETERS:
6062  * vha:	SCSI qla host
6063  * purex: RDP request received by HBA
6064  */
6065 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6066 			       struct purex_item *item)
6067 {
6068 	struct qla_hw_data *ha = vha->hw;
6069 	struct purex_entry_24xx *purex =
6070 	    (struct purex_entry_24xx *)&item->iocb;
6071 	dma_addr_t rsp_els_dma;
6072 	dma_addr_t rsp_payload_dma;
6073 	dma_addr_t stat_dma;
6074 	dma_addr_t sfp_dma;
6075 	struct els_entry_24xx *rsp_els = NULL;
6076 	struct rdp_rsp_payload *rsp_payload = NULL;
6077 	struct link_statistics *stat = NULL;
6078 	uint8_t *sfp = NULL;
6079 	uint16_t sfp_flags = 0;
6080 	uint rsp_payload_length = sizeof(*rsp_payload);
6081 	int rval;
6082 
6083 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6084 	    "%s: Enter\n", __func__);
6085 
6086 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6087 	    "-------- ELS REQ -------\n");
6088 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6089 	    purex, sizeof(*purex));
6090 
6091 	if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6092 		rsp_payload_length =
6093 		    offsetof(typeof(*rsp_payload), optical_elmt_desc);
6094 		ql_dbg(ql_dbg_init, vha, 0x0181,
6095 		    "Reducing RSP payload length to %u bytes...\n",
6096 		    rsp_payload_length);
6097 	}
6098 
6099 	rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6100 	    &rsp_els_dma, GFP_KERNEL);
6101 	if (!rsp_els) {
6102 		ql_log(ql_log_warn, vha, 0x0183,
6103 		    "Failed allocate dma buffer ELS RSP.\n");
6104 		goto dealloc;
6105 	}
6106 
6107 	rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6108 	    &rsp_payload_dma, GFP_KERNEL);
6109 	if (!rsp_payload) {
6110 		ql_log(ql_log_warn, vha, 0x0184,
6111 		    "Failed allocate dma buffer ELS RSP payload.\n");
6112 		goto dealloc;
6113 	}
6114 
6115 	sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6116 	    &sfp_dma, GFP_KERNEL);
6117 
6118 	stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6119 	    &stat_dma, GFP_KERNEL);
6120 
6121 	/* Prepare Response IOCB */
6122 	rsp_els->entry_type = ELS_IOCB_TYPE;
6123 	rsp_els->entry_count = 1;
6124 	rsp_els->sys_define = 0;
6125 	rsp_els->entry_status = 0;
6126 	rsp_els->handle = 0;
6127 	rsp_els->nport_handle = purex->nport_handle;
6128 	rsp_els->tx_dsd_count = cpu_to_le16(1);
6129 	rsp_els->vp_index = purex->vp_idx;
6130 	rsp_els->sof_type = EST_SOFI3;
6131 	rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6132 	rsp_els->rx_dsd_count = 0;
6133 	rsp_els->opcode = purex->els_frame_payload[0];
6134 
6135 	rsp_els->d_id[0] = purex->s_id[0];
6136 	rsp_els->d_id[1] = purex->s_id[1];
6137 	rsp_els->d_id[2] = purex->s_id[2];
6138 
6139 	rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6140 	rsp_els->rx_byte_count = 0;
6141 	rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6142 
6143 	put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6144 	rsp_els->tx_len = rsp_els->tx_byte_count;
6145 
6146 	rsp_els->rx_address = 0;
6147 	rsp_els->rx_len = 0;
6148 
6149 	/* Prepare Response Payload */
6150 	rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6151 	rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6152 					   sizeof(rsp_payload->hdr));
6153 
6154 	/* Link service Request Info Descriptor */
6155 	rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6156 	rsp_payload->ls_req_info_desc.desc_len =
6157 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6158 	rsp_payload->ls_req_info_desc.req_payload_word_0 =
6159 	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6160 
6161 	/* Link service Request Info Descriptor 2 */
6162 	rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6163 	rsp_payload->ls_req_info_desc2.desc_len =
6164 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6165 	rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6166 	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6167 
6168 
6169 	rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6170 	rsp_payload->sfp_diag_desc.desc_len =
6171 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6172 
6173 	if (sfp) {
6174 		/* SFP Flags */
6175 		memset(sfp, 0, SFP_RTDI_LEN);
6176 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6177 		if (!rval) {
6178 			/* SFP Flags bits 3-0: Port Tx Laser Type */
6179 			if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6180 				sfp_flags |= BIT_0; /* short wave */
6181 			else if (sfp[0] & BIT_1)
6182 				sfp_flags |= BIT_1; /* long wave 1310nm */
6183 			else if (sfp[1] & BIT_4)
6184 				sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6185 		}
6186 
6187 		/* SFP Type */
6188 		memset(sfp, 0, SFP_RTDI_LEN);
6189 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6190 		if (!rval) {
6191 			sfp_flags |= BIT_4; /* optical */
6192 			if (sfp[0] == 0x3)
6193 				sfp_flags |= BIT_6; /* sfp+ */
6194 		}
6195 
6196 		rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6197 
6198 		/* SFP Diagnostics */
6199 		memset(sfp, 0, SFP_RTDI_LEN);
6200 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6201 		if (!rval) {
6202 			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6203 			rsp_payload->sfp_diag_desc.temperature = trx[0];
6204 			rsp_payload->sfp_diag_desc.vcc = trx[1];
6205 			rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6206 			rsp_payload->sfp_diag_desc.tx_power = trx[3];
6207 			rsp_payload->sfp_diag_desc.rx_power = trx[4];
6208 		}
6209 	}
6210 
6211 	/* Port Speed Descriptor */
6212 	rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6213 	rsp_payload->port_speed_desc.desc_len =
6214 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6215 	rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6216 	    qla25xx_fdmi_port_speed_capability(ha));
6217 	rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6218 	    qla25xx_fdmi_port_speed_currently(ha));
6219 
6220 	/* Link Error Status Descriptor */
6221 	rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6222 	rsp_payload->ls_err_desc.desc_len =
6223 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6224 
6225 	if (stat) {
6226 		rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6227 		if (!rval) {
6228 			rsp_payload->ls_err_desc.link_fail_cnt =
6229 			    cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6230 			rsp_payload->ls_err_desc.loss_sync_cnt =
6231 			    cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6232 			rsp_payload->ls_err_desc.loss_sig_cnt =
6233 			    cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6234 			rsp_payload->ls_err_desc.prim_seq_err_cnt =
6235 			    cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6236 			rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6237 			    cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6238 			rsp_payload->ls_err_desc.inval_crc_cnt =
6239 			    cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6240 			rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6241 		}
6242 	}
6243 
6244 	/* Portname Descriptor */
6245 	rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6246 	rsp_payload->port_name_diag_desc.desc_len =
6247 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6248 	memcpy(rsp_payload->port_name_diag_desc.WWNN,
6249 	    vha->node_name,
6250 	    sizeof(rsp_payload->port_name_diag_desc.WWNN));
6251 	memcpy(rsp_payload->port_name_diag_desc.WWPN,
6252 	    vha->port_name,
6253 	    sizeof(rsp_payload->port_name_diag_desc.WWPN));
6254 
6255 	/* F-Port Portname Descriptor */
6256 	rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6257 	rsp_payload->port_name_direct_desc.desc_len =
6258 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6259 	memcpy(rsp_payload->port_name_direct_desc.WWNN,
6260 	    vha->fabric_node_name,
6261 	    sizeof(rsp_payload->port_name_direct_desc.WWNN));
6262 	memcpy(rsp_payload->port_name_direct_desc.WWPN,
6263 	    vha->fabric_port_name,
6264 	    sizeof(rsp_payload->port_name_direct_desc.WWPN));
6265 
6266 	/* Bufer Credit Descriptor */
6267 	rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6268 	rsp_payload->buffer_credit_desc.desc_len =
6269 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6270 	rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6271 	rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6272 	rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6273 
6274 	if (ha->flags.plogi_template_valid) {
6275 		uint32_t tmp =
6276 		be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6277 		rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6278 	}
6279 
6280 	if (rsp_payload_length < sizeof(*rsp_payload))
6281 		goto send;
6282 
6283 	/* Optical Element Descriptor, Temperature */
6284 	rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6285 	rsp_payload->optical_elmt_desc[0].desc_len =
6286 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6287 	/* Optical Element Descriptor, Voltage */
6288 	rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6289 	rsp_payload->optical_elmt_desc[1].desc_len =
6290 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6291 	/* Optical Element Descriptor, Tx Bias Current */
6292 	rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6293 	rsp_payload->optical_elmt_desc[2].desc_len =
6294 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6295 	/* Optical Element Descriptor, Tx Power */
6296 	rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6297 	rsp_payload->optical_elmt_desc[3].desc_len =
6298 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6299 	/* Optical Element Descriptor, Rx Power */
6300 	rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6301 	rsp_payload->optical_elmt_desc[4].desc_len =
6302 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6303 
6304 	if (sfp) {
6305 		memset(sfp, 0, SFP_RTDI_LEN);
6306 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6307 		if (!rval) {
6308 			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6309 
6310 			/* Optical Element Descriptor, Temperature */
6311 			rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6312 			rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6313 			rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6314 			rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6315 			rsp_payload->optical_elmt_desc[0].element_flags =
6316 			    cpu_to_be32(1 << 28);
6317 
6318 			/* Optical Element Descriptor, Voltage */
6319 			rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6320 			rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6321 			rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6322 			rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6323 			rsp_payload->optical_elmt_desc[1].element_flags =
6324 			    cpu_to_be32(2 << 28);
6325 
6326 			/* Optical Element Descriptor, Tx Bias Current */
6327 			rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6328 			rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6329 			rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6330 			rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6331 			rsp_payload->optical_elmt_desc[2].element_flags =
6332 			    cpu_to_be32(3 << 28);
6333 
6334 			/* Optical Element Descriptor, Tx Power */
6335 			rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6336 			rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6337 			rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6338 			rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6339 			rsp_payload->optical_elmt_desc[3].element_flags =
6340 			    cpu_to_be32(4 << 28);
6341 
6342 			/* Optical Element Descriptor, Rx Power */
6343 			rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6344 			rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6345 			rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6346 			rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6347 			rsp_payload->optical_elmt_desc[4].element_flags =
6348 			    cpu_to_be32(5 << 28);
6349 		}
6350 
6351 		memset(sfp, 0, SFP_RTDI_LEN);
6352 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6353 		if (!rval) {
6354 			/* Temperature high/low alarm/warning */
6355 			rsp_payload->optical_elmt_desc[0].element_flags |=
6356 			    cpu_to_be32(
6357 				(sfp[0] >> 7 & 1) << 3 |
6358 				(sfp[0] >> 6 & 1) << 2 |
6359 				(sfp[4] >> 7 & 1) << 1 |
6360 				(sfp[4] >> 6 & 1) << 0);
6361 
6362 			/* Voltage high/low alarm/warning */
6363 			rsp_payload->optical_elmt_desc[1].element_flags |=
6364 			    cpu_to_be32(
6365 				(sfp[0] >> 5 & 1) << 3 |
6366 				(sfp[0] >> 4 & 1) << 2 |
6367 				(sfp[4] >> 5 & 1) << 1 |
6368 				(sfp[4] >> 4 & 1) << 0);
6369 
6370 			/* Tx Bias Current high/low alarm/warning */
6371 			rsp_payload->optical_elmt_desc[2].element_flags |=
6372 			    cpu_to_be32(
6373 				(sfp[0] >> 3 & 1) << 3 |
6374 				(sfp[0] >> 2 & 1) << 2 |
6375 				(sfp[4] >> 3 & 1) << 1 |
6376 				(sfp[4] >> 2 & 1) << 0);
6377 
6378 			/* Tx Power high/low alarm/warning */
6379 			rsp_payload->optical_elmt_desc[3].element_flags |=
6380 			    cpu_to_be32(
6381 				(sfp[0] >> 1 & 1) << 3 |
6382 				(sfp[0] >> 0 & 1) << 2 |
6383 				(sfp[4] >> 1 & 1) << 1 |
6384 				(sfp[4] >> 0 & 1) << 0);
6385 
6386 			/* Rx Power high/low alarm/warning */
6387 			rsp_payload->optical_elmt_desc[4].element_flags |=
6388 			    cpu_to_be32(
6389 				(sfp[1] >> 7 & 1) << 3 |
6390 				(sfp[1] >> 6 & 1) << 2 |
6391 				(sfp[5] >> 7 & 1) << 1 |
6392 				(sfp[5] >> 6 & 1) << 0);
6393 		}
6394 	}
6395 
6396 	/* Optical Product Data Descriptor */
6397 	rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6398 	rsp_payload->optical_prod_desc.desc_len =
6399 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6400 
6401 	if (sfp) {
6402 		memset(sfp, 0, SFP_RTDI_LEN);
6403 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6404 		if (!rval) {
6405 			memcpy(rsp_payload->optical_prod_desc.vendor_name,
6406 			    sfp + 0,
6407 			    sizeof(rsp_payload->optical_prod_desc.vendor_name));
6408 			memcpy(rsp_payload->optical_prod_desc.part_number,
6409 			    sfp + 20,
6410 			    sizeof(rsp_payload->optical_prod_desc.part_number));
6411 			memcpy(rsp_payload->optical_prod_desc.revision,
6412 			    sfp + 36,
6413 			    sizeof(rsp_payload->optical_prod_desc.revision));
6414 			memcpy(rsp_payload->optical_prod_desc.serial_number,
6415 			    sfp + 48,
6416 			    sizeof(rsp_payload->optical_prod_desc.serial_number));
6417 		}
6418 
6419 		memset(sfp, 0, SFP_RTDI_LEN);
6420 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6421 		if (!rval) {
6422 			memcpy(rsp_payload->optical_prod_desc.date,
6423 			    sfp + 0,
6424 			    sizeof(rsp_payload->optical_prod_desc.date));
6425 		}
6426 	}
6427 
6428 send:
6429 	ql_dbg(ql_dbg_init, vha, 0x0183,
6430 	    "Sending ELS Response to RDP Request...\n");
6431 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6432 	    "-------- ELS RSP -------\n");
6433 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6434 	    rsp_els, sizeof(*rsp_els));
6435 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6436 	    "-------- ELS RSP PAYLOAD -------\n");
6437 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6438 	    rsp_payload, rsp_payload_length);
6439 
6440 	rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6441 
6442 	if (rval) {
6443 		ql_log(ql_log_warn, vha, 0x0188,
6444 		    "%s: iocb failed to execute -> %x\n", __func__, rval);
6445 	} else if (rsp_els->comp_status) {
6446 		ql_log(ql_log_warn, vha, 0x0189,
6447 		    "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6448 		    __func__, rsp_els->comp_status,
6449 		    rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6450 	} else {
6451 		ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6452 	}
6453 
6454 dealloc:
6455 	if (stat)
6456 		dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6457 		    stat, stat_dma);
6458 	if (sfp)
6459 		dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6460 		    sfp, sfp_dma);
6461 	if (rsp_payload)
6462 		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6463 		    rsp_payload, rsp_payload_dma);
6464 	if (rsp_els)
6465 		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6466 		    rsp_els, rsp_els_dma);
6467 }
6468 
6469 void
6470 qla24xx_free_purex_item(struct purex_item *item)
6471 {
6472 	if (item == &item->vha->default_item)
6473 		memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6474 	else
6475 		kfree(item);
6476 }
6477 
6478 void qla24xx_process_purex_list(struct purex_list *list)
6479 {
6480 	struct list_head head = LIST_HEAD_INIT(head);
6481 	struct purex_item *item, *next;
6482 	ulong flags;
6483 
6484 	spin_lock_irqsave(&list->lock, flags);
6485 	list_splice_init(&list->head, &head);
6486 	spin_unlock_irqrestore(&list->lock, flags);
6487 
6488 	list_for_each_entry_safe(item, next, &head, list) {
6489 		list_del(&item->list);
6490 		item->process_item(item->vha, item);
6491 		qla24xx_free_purex_item(item);
6492 	}
6493 }
6494 
6495 /*
6496  * Context: task, can sleep
6497  */
6498 void
6499 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6500 {
6501 #if 0
6502 	uint16_t options = (requester_id << 15) | BIT_7;
6503 #endif
6504 	uint16_t retry;
6505 	uint32_t data;
6506 	struct qla_hw_data *ha = base_vha->hw;
6507 
6508 	might_sleep();
6509 
6510 	/* IDC-unlock implementation using driver-unlock/lock-id
6511 	 * remote registers
6512 	 */
6513 	retry = 0;
6514 retry_unlock:
6515 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6516 	    == QLA_SUCCESS) {
6517 		if (data == ha->portnum) {
6518 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6519 			/* Clearing lock-id by setting 0xff */
6520 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6521 		} else if (retry < 10) {
6522 			/* SV: XXX: IDC unlock retrying needed here? */
6523 
6524 			/* Retry for IDC-unlock */
6525 			msleep(QLA83XX_WAIT_LOGIC_MS);
6526 			retry++;
6527 			ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6528 			    "Failed to release IDC lock, retrying=%d\n", retry);
6529 			goto retry_unlock;
6530 		}
6531 	} else if (retry < 10) {
6532 		/* Retry for IDC-unlock */
6533 		msleep(QLA83XX_WAIT_LOGIC_MS);
6534 		retry++;
6535 		ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6536 		    "Failed to read drv-lockid, retrying=%d\n", retry);
6537 		goto retry_unlock;
6538 	}
6539 
6540 	return;
6541 
6542 #if 0
6543 	/* XXX: IDC-unlock implementation using access-control mbx */
6544 	retry = 0;
6545 retry_unlock2:
6546 	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6547 		if (retry < 10) {
6548 			/* Retry for IDC-unlock */
6549 			msleep(QLA83XX_WAIT_LOGIC_MS);
6550 			retry++;
6551 			ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6552 			    "Failed to release IDC lock, retrying=%d\n", retry);
6553 			goto retry_unlock2;
6554 		}
6555 	}
6556 
6557 	return;
6558 #endif
6559 }
6560 
6561 int
6562 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6563 {
6564 	int rval = QLA_SUCCESS;
6565 	struct qla_hw_data *ha = vha->hw;
6566 	uint32_t drv_presence;
6567 
6568 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6569 	if (rval == QLA_SUCCESS) {
6570 		drv_presence |= (1 << ha->portnum);
6571 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6572 		    drv_presence);
6573 	}
6574 
6575 	return rval;
6576 }
6577 
6578 int
6579 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6580 {
6581 	int rval = QLA_SUCCESS;
6582 
6583 	qla83xx_idc_lock(vha, 0);
6584 	rval = __qla83xx_set_drv_presence(vha);
6585 	qla83xx_idc_unlock(vha, 0);
6586 
6587 	return rval;
6588 }
6589 
6590 int
6591 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6592 {
6593 	int rval = QLA_SUCCESS;
6594 	struct qla_hw_data *ha = vha->hw;
6595 	uint32_t drv_presence;
6596 
6597 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6598 	if (rval == QLA_SUCCESS) {
6599 		drv_presence &= ~(1 << ha->portnum);
6600 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6601 		    drv_presence);
6602 	}
6603 
6604 	return rval;
6605 }
6606 
6607 int
6608 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6609 {
6610 	int rval = QLA_SUCCESS;
6611 
6612 	qla83xx_idc_lock(vha, 0);
6613 	rval = __qla83xx_clear_drv_presence(vha);
6614 	qla83xx_idc_unlock(vha, 0);
6615 
6616 	return rval;
6617 }
6618 
6619 static void
6620 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6621 {
6622 	struct qla_hw_data *ha = vha->hw;
6623 	uint32_t drv_ack, drv_presence;
6624 	unsigned long ack_timeout;
6625 
6626 	/* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6627 	ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6628 	while (1) {
6629 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6630 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6631 		if ((drv_ack & drv_presence) == drv_presence)
6632 			break;
6633 
6634 		if (time_after_eq(jiffies, ack_timeout)) {
6635 			ql_log(ql_log_warn, vha, 0xb067,
6636 			    "RESET ACK TIMEOUT! drv_presence=0x%x "
6637 			    "drv_ack=0x%x\n", drv_presence, drv_ack);
6638 			/*
6639 			 * The function(s) which did not ack in time are forced
6640 			 * to withdraw any further participation in the IDC
6641 			 * reset.
6642 			 */
6643 			if (drv_ack != drv_presence)
6644 				qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6645 				    drv_ack);
6646 			break;
6647 		}
6648 
6649 		qla83xx_idc_unlock(vha, 0);
6650 		msleep(1000);
6651 		qla83xx_idc_lock(vha, 0);
6652 	}
6653 
6654 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6655 	ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6656 }
6657 
6658 static int
6659 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6660 {
6661 	int rval = QLA_SUCCESS;
6662 	uint32_t idc_control;
6663 
6664 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6665 	ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6666 
6667 	/* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6668 	__qla83xx_get_idc_control(vha, &idc_control);
6669 	idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6670 	__qla83xx_set_idc_control(vha, 0);
6671 
6672 	qla83xx_idc_unlock(vha, 0);
6673 	rval = qla83xx_restart_nic_firmware(vha);
6674 	qla83xx_idc_lock(vha, 0);
6675 
6676 	if (rval != QLA_SUCCESS) {
6677 		ql_log(ql_log_fatal, vha, 0xb06a,
6678 		    "Failed to restart NIC f/w.\n");
6679 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6680 		ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6681 	} else {
6682 		ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6683 		    "Success in restarting nic f/w.\n");
6684 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6685 		ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6686 	}
6687 
6688 	return rval;
6689 }
6690 
6691 /* Assumes idc_lock always held on entry */
6692 int
6693 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6694 {
6695 	struct qla_hw_data *ha = base_vha->hw;
6696 	int rval = QLA_SUCCESS;
6697 	unsigned long dev_init_timeout;
6698 	uint32_t dev_state;
6699 
6700 	/* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6701 	dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6702 
6703 	while (1) {
6704 
6705 		if (time_after_eq(jiffies, dev_init_timeout)) {
6706 			ql_log(ql_log_warn, base_vha, 0xb06e,
6707 			    "Initialization TIMEOUT!\n");
6708 			/* Init timeout. Disable further NIC Core
6709 			 * communication.
6710 			 */
6711 			qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6712 				QLA8XXX_DEV_FAILED);
6713 			ql_log(ql_log_info, base_vha, 0xb06f,
6714 			    "HW State: FAILED.\n");
6715 		}
6716 
6717 		qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6718 		switch (dev_state) {
6719 		case QLA8XXX_DEV_READY:
6720 			if (ha->flags.nic_core_reset_owner)
6721 				qla83xx_idc_audit(base_vha,
6722 				    IDC_AUDIT_COMPLETION);
6723 			ha->flags.nic_core_reset_owner = 0;
6724 			ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6725 			    "Reset_owner reset by 0x%x.\n",
6726 			    ha->portnum);
6727 			goto exit;
6728 		case QLA8XXX_DEV_COLD:
6729 			if (ha->flags.nic_core_reset_owner)
6730 				rval = qla83xx_device_bootstrap(base_vha);
6731 			else {
6732 			/* Wait for AEN to change device-state */
6733 				qla83xx_idc_unlock(base_vha, 0);
6734 				msleep(1000);
6735 				qla83xx_idc_lock(base_vha, 0);
6736 			}
6737 			break;
6738 		case QLA8XXX_DEV_INITIALIZING:
6739 			/* Wait for AEN to change device-state */
6740 			qla83xx_idc_unlock(base_vha, 0);
6741 			msleep(1000);
6742 			qla83xx_idc_lock(base_vha, 0);
6743 			break;
6744 		case QLA8XXX_DEV_NEED_RESET:
6745 			if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6746 				qla83xx_need_reset_handler(base_vha);
6747 			else {
6748 				/* Wait for AEN to change device-state */
6749 				qla83xx_idc_unlock(base_vha, 0);
6750 				msleep(1000);
6751 				qla83xx_idc_lock(base_vha, 0);
6752 			}
6753 			/* reset timeout value after need reset handler */
6754 			dev_init_timeout = jiffies +
6755 			    (ha->fcoe_dev_init_timeout * HZ);
6756 			break;
6757 		case QLA8XXX_DEV_NEED_QUIESCENT:
6758 			/* XXX: DEBUG for now */
6759 			qla83xx_idc_unlock(base_vha, 0);
6760 			msleep(1000);
6761 			qla83xx_idc_lock(base_vha, 0);
6762 			break;
6763 		case QLA8XXX_DEV_QUIESCENT:
6764 			/* XXX: DEBUG for now */
6765 			if (ha->flags.quiesce_owner)
6766 				goto exit;
6767 
6768 			qla83xx_idc_unlock(base_vha, 0);
6769 			msleep(1000);
6770 			qla83xx_idc_lock(base_vha, 0);
6771 			dev_init_timeout = jiffies +
6772 			    (ha->fcoe_dev_init_timeout * HZ);
6773 			break;
6774 		case QLA8XXX_DEV_FAILED:
6775 			if (ha->flags.nic_core_reset_owner)
6776 				qla83xx_idc_audit(base_vha,
6777 				    IDC_AUDIT_COMPLETION);
6778 			ha->flags.nic_core_reset_owner = 0;
6779 			__qla83xx_clear_drv_presence(base_vha);
6780 			qla83xx_idc_unlock(base_vha, 0);
6781 			qla8xxx_dev_failed_handler(base_vha);
6782 			rval = QLA_FUNCTION_FAILED;
6783 			qla83xx_idc_lock(base_vha, 0);
6784 			goto exit;
6785 		case QLA8XXX_BAD_VALUE:
6786 			qla83xx_idc_unlock(base_vha, 0);
6787 			msleep(1000);
6788 			qla83xx_idc_lock(base_vha, 0);
6789 			break;
6790 		default:
6791 			ql_log(ql_log_warn, base_vha, 0xb071,
6792 			    "Unknown Device State: %x.\n", dev_state);
6793 			qla83xx_idc_unlock(base_vha, 0);
6794 			qla8xxx_dev_failed_handler(base_vha);
6795 			rval = QLA_FUNCTION_FAILED;
6796 			qla83xx_idc_lock(base_vha, 0);
6797 			goto exit;
6798 		}
6799 	}
6800 
6801 exit:
6802 	return rval;
6803 }
6804 
6805 void
6806 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6807 {
6808 	struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6809 	    board_disable);
6810 	struct pci_dev *pdev = ha->pdev;
6811 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6812 
6813 	ql_log(ql_log_warn, base_vha, 0x015b,
6814 	    "Disabling adapter.\n");
6815 
6816 	if (!atomic_read(&pdev->enable_cnt)) {
6817 		ql_log(ql_log_info, base_vha, 0xfffc,
6818 		    "PCI device disabled, no action req for PCI error=%lx\n",
6819 		    base_vha->pci_flags);
6820 		return;
6821 	}
6822 
6823 	/*
6824 	 * if UNLOADING flag is already set, then continue unload,
6825 	 * where it was set first.
6826 	 */
6827 	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6828 		return;
6829 
6830 	qla2x00_wait_for_sess_deletion(base_vha);
6831 
6832 	qla2x00_delete_all_vps(ha, base_vha);
6833 
6834 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6835 
6836 	qla2x00_dfs_remove(base_vha);
6837 
6838 	qla84xx_put_chip(base_vha);
6839 
6840 	if (base_vha->timer_active)
6841 		qla2x00_stop_timer(base_vha);
6842 
6843 	base_vha->flags.online = 0;
6844 
6845 	qla2x00_destroy_deferred_work(ha);
6846 
6847 	/*
6848 	 * Do not try to stop beacon blink as it will issue a mailbox
6849 	 * command.
6850 	 */
6851 	qla2x00_free_sysfs_attr(base_vha, false);
6852 
6853 	fc_remove_host(base_vha->host);
6854 
6855 	scsi_remove_host(base_vha->host);
6856 
6857 	base_vha->flags.init_done = 0;
6858 	qla25xx_delete_queues(base_vha);
6859 	qla2x00_free_fcports(base_vha);
6860 	qla2x00_free_irqs(base_vha);
6861 	qla2x00_mem_free(ha);
6862 	qla82xx_md_free(base_vha);
6863 	qla2x00_free_queues(ha);
6864 
6865 	qla2x00_unmap_iobases(ha);
6866 
6867 	pci_release_selected_regions(ha->pdev, ha->bars);
6868 	pci_disable_device(pdev);
6869 
6870 	/*
6871 	 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6872 	 */
6873 }
6874 
6875 /**************************************************************************
6876 * qla2x00_do_dpc
6877 *   This kernel thread is a task that is schedule by the interrupt handler
6878 *   to perform the background processing for interrupts.
6879 *
6880 * Notes:
6881 * This task always run in the context of a kernel thread.  It
6882 * is kick-off by the driver's detect code and starts up
6883 * up one per adapter. It immediately goes to sleep and waits for
6884 * some fibre event.  When either the interrupt handler or
6885 * the timer routine detects a event it will one of the task
6886 * bits then wake us up.
6887 **************************************************************************/
6888 static int
6889 qla2x00_do_dpc(void *data)
6890 {
6891 	scsi_qla_host_t *base_vha;
6892 	struct qla_hw_data *ha;
6893 	uint32_t online;
6894 	struct qla_qpair *qpair;
6895 
6896 	ha = (struct qla_hw_data *)data;
6897 	base_vha = pci_get_drvdata(ha->pdev);
6898 
6899 	set_user_nice(current, MIN_NICE);
6900 
6901 	set_current_state(TASK_INTERRUPTIBLE);
6902 	while (!kthread_should_stop()) {
6903 		ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6904 		    "DPC handler sleeping.\n");
6905 
6906 		schedule();
6907 
6908 		if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6909 			qla_pci_set_eeh_busy(base_vha);
6910 
6911 		if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6912 			goto end_loop;
6913 
6914 		if (ha->flags.eeh_busy) {
6915 			ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6916 			    "eeh_busy=%d.\n", ha->flags.eeh_busy);
6917 			goto end_loop;
6918 		}
6919 
6920 		ha->dpc_active = 1;
6921 
6922 		ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6923 		    "DPC handler waking up, dpc_flags=0x%lx.\n",
6924 		    base_vha->dpc_flags);
6925 
6926 		if (test_bit(UNLOADING, &base_vha->dpc_flags))
6927 			break;
6928 
6929 		if (IS_P3P_TYPE(ha)) {
6930 			if (IS_QLA8044(ha)) {
6931 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6932 					&base_vha->dpc_flags)) {
6933 					qla8044_idc_lock(ha);
6934 					qla8044_wr_direct(base_vha,
6935 						QLA8044_CRB_DEV_STATE_INDEX,
6936 						QLA8XXX_DEV_FAILED);
6937 					qla8044_idc_unlock(ha);
6938 					ql_log(ql_log_info, base_vha, 0x4004,
6939 						"HW State: FAILED.\n");
6940 					qla8044_device_state_handler(base_vha);
6941 					continue;
6942 				}
6943 
6944 			} else {
6945 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6946 					&base_vha->dpc_flags)) {
6947 					qla82xx_idc_lock(ha);
6948 					qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6949 						QLA8XXX_DEV_FAILED);
6950 					qla82xx_idc_unlock(ha);
6951 					ql_log(ql_log_info, base_vha, 0x0151,
6952 						"HW State: FAILED.\n");
6953 					qla82xx_device_state_handler(base_vha);
6954 					continue;
6955 				}
6956 			}
6957 
6958 			if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6959 				&base_vha->dpc_flags)) {
6960 
6961 				ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6962 				    "FCoE context reset scheduled.\n");
6963 				if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6964 					&base_vha->dpc_flags))) {
6965 					if (qla82xx_fcoe_ctx_reset(base_vha)) {
6966 						/* FCoE-ctx reset failed.
6967 						 * Escalate to chip-reset
6968 						 */
6969 						set_bit(ISP_ABORT_NEEDED,
6970 							&base_vha->dpc_flags);
6971 					}
6972 					clear_bit(ABORT_ISP_ACTIVE,
6973 						&base_vha->dpc_flags);
6974 				}
6975 
6976 				ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6977 				    "FCoE context reset end.\n");
6978 			}
6979 		} else if (IS_QLAFX00(ha)) {
6980 			if (test_and_clear_bit(ISP_UNRECOVERABLE,
6981 				&base_vha->dpc_flags)) {
6982 				ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6983 				    "Firmware Reset Recovery\n");
6984 				if (qlafx00_reset_initialize(base_vha)) {
6985 					/* Failed. Abort isp later. */
6986 					if (!test_bit(UNLOADING,
6987 					    &base_vha->dpc_flags)) {
6988 						set_bit(ISP_UNRECOVERABLE,
6989 						    &base_vha->dpc_flags);
6990 						ql_dbg(ql_dbg_dpc, base_vha,
6991 						    0x4021,
6992 						    "Reset Recovery Failed\n");
6993 					}
6994 				}
6995 			}
6996 
6997 			if (test_and_clear_bit(FX00_TARGET_SCAN,
6998 				&base_vha->dpc_flags)) {
6999 				ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
7000 				    "ISPFx00 Target Scan scheduled\n");
7001 				if (qlafx00_rescan_isp(base_vha)) {
7002 					if (!test_bit(UNLOADING,
7003 					    &base_vha->dpc_flags))
7004 						set_bit(ISP_UNRECOVERABLE,
7005 						    &base_vha->dpc_flags);
7006 					ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7007 					    "ISPFx00 Target Scan Failed\n");
7008 				}
7009 				ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7010 				    "ISPFx00 Target Scan End\n");
7011 			}
7012 			if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7013 				&base_vha->dpc_flags)) {
7014 				ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7015 				    "ISPFx00 Host Info resend scheduled\n");
7016 				qlafx00_fx_disc(base_vha,
7017 				    &base_vha->hw->mr.fcport,
7018 				    FXDISC_REG_HOST_INFO);
7019 			}
7020 		}
7021 
7022 		if (test_and_clear_bit(DETECT_SFP_CHANGE,
7023 		    &base_vha->dpc_flags)) {
7024 			/* Semantic:
7025 			 *  - NO-OP -- await next ISP-ABORT. Preferred method
7026 			 *             to minimize disruptions that will occur
7027 			 *             when a forced chip-reset occurs.
7028 			 *  - Force -- ISP-ABORT scheduled.
7029 			 */
7030 			/* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7031 		}
7032 
7033 		if (test_and_clear_bit
7034 		    (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7035 		    !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7036 			bool do_reset = true;
7037 
7038 			switch (base_vha->qlini_mode) {
7039 			case QLA2XXX_INI_MODE_ENABLED:
7040 				break;
7041 			case QLA2XXX_INI_MODE_DISABLED:
7042 				if (!qla_tgt_mode_enabled(base_vha) &&
7043 				    !ha->flags.fw_started)
7044 					do_reset = false;
7045 				break;
7046 			case QLA2XXX_INI_MODE_DUAL:
7047 				if (!qla_dual_mode_enabled(base_vha) &&
7048 				    !ha->flags.fw_started)
7049 					do_reset = false;
7050 				break;
7051 			default:
7052 				break;
7053 			}
7054 
7055 			if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7056 			    &base_vha->dpc_flags))) {
7057 				base_vha->flags.online = 1;
7058 				ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7059 				    "ISP abort scheduled.\n");
7060 				if (ha->isp_ops->abort_isp(base_vha)) {
7061 					/* failed. retry later */
7062 					set_bit(ISP_ABORT_NEEDED,
7063 					    &base_vha->dpc_flags);
7064 				}
7065 				clear_bit(ABORT_ISP_ACTIVE,
7066 						&base_vha->dpc_flags);
7067 				ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7068 				    "ISP abort end.\n");
7069 			}
7070 		}
7071 
7072 		if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7073 			if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7074 				qla24xx_process_purex_list
7075 					(&base_vha->purex_list);
7076 				clear_bit(PROCESS_PUREX_IOCB,
7077 				    &base_vha->dpc_flags);
7078 			}
7079 		}
7080 
7081 		if (IS_QLAFX00(ha))
7082 			goto loop_resync_check;
7083 
7084 		if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7085 			ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7086 			    "Quiescence mode scheduled.\n");
7087 			if (IS_P3P_TYPE(ha)) {
7088 				if (IS_QLA82XX(ha))
7089 					qla82xx_device_state_handler(base_vha);
7090 				if (IS_QLA8044(ha))
7091 					qla8044_device_state_handler(base_vha);
7092 				clear_bit(ISP_QUIESCE_NEEDED,
7093 				    &base_vha->dpc_flags);
7094 				if (!ha->flags.quiesce_owner) {
7095 					qla2x00_perform_loop_resync(base_vha);
7096 					if (IS_QLA82XX(ha)) {
7097 						qla82xx_idc_lock(ha);
7098 						qla82xx_clear_qsnt_ready(
7099 						    base_vha);
7100 						qla82xx_idc_unlock(ha);
7101 					} else if (IS_QLA8044(ha)) {
7102 						qla8044_idc_lock(ha);
7103 						qla8044_clear_qsnt_ready(
7104 						    base_vha);
7105 						qla8044_idc_unlock(ha);
7106 					}
7107 				}
7108 			} else {
7109 				clear_bit(ISP_QUIESCE_NEEDED,
7110 				    &base_vha->dpc_flags);
7111 				qla2x00_quiesce_io(base_vha);
7112 			}
7113 			ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7114 			    "Quiescence mode end.\n");
7115 		}
7116 
7117 		if (test_and_clear_bit(RESET_MARKER_NEEDED,
7118 				&base_vha->dpc_flags) &&
7119 		    (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7120 
7121 			ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7122 			    "Reset marker scheduled.\n");
7123 			qla2x00_rst_aen(base_vha);
7124 			clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7125 			ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7126 			    "Reset marker end.\n");
7127 		}
7128 
7129 		/* Retry each device up to login retry count */
7130 		if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7131 		    !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7132 		    atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7133 
7134 			if (!base_vha->relogin_jif ||
7135 			    time_after_eq(jiffies, base_vha->relogin_jif)) {
7136 				base_vha->relogin_jif = jiffies + HZ;
7137 				clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7138 
7139 				ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7140 				    "Relogin scheduled.\n");
7141 				qla24xx_post_relogin_work(base_vha);
7142 			}
7143 		}
7144 loop_resync_check:
7145 		if (!qla2x00_reset_active(base_vha) &&
7146 		    test_and_clear_bit(LOOP_RESYNC_NEEDED,
7147 		    &base_vha->dpc_flags)) {
7148 			/*
7149 			 * Allow abort_isp to complete before moving on to scanning.
7150 			 */
7151 			ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7152 			    "Loop resync scheduled.\n");
7153 
7154 			if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7155 			    &base_vha->dpc_flags))) {
7156 
7157 				qla2x00_loop_resync(base_vha);
7158 
7159 				clear_bit(LOOP_RESYNC_ACTIVE,
7160 						&base_vha->dpc_flags);
7161 			}
7162 
7163 			ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7164 			    "Loop resync end.\n");
7165 		}
7166 
7167 		if (IS_QLAFX00(ha))
7168 			goto intr_on_check;
7169 
7170 		if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7171 		    atomic_read(&base_vha->loop_state) == LOOP_READY) {
7172 			clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7173 			qla2xxx_flash_npiv_conf(base_vha);
7174 		}
7175 
7176 intr_on_check:
7177 		if (!ha->interrupts_on)
7178 			ha->isp_ops->enable_intrs(ha);
7179 
7180 		if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7181 					&base_vha->dpc_flags)) {
7182 			if (ha->beacon_blink_led == 1)
7183 				ha->isp_ops->beacon_blink(base_vha);
7184 		}
7185 
7186 		/* qpair online check */
7187 		if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7188 		    &base_vha->dpc_flags)) {
7189 			if (ha->flags.eeh_busy ||
7190 			    ha->flags.pci_channel_io_perm_failure)
7191 				online = 0;
7192 			else
7193 				online = 1;
7194 
7195 			mutex_lock(&ha->mq_lock);
7196 			list_for_each_entry(qpair, &base_vha->qp_list,
7197 			    qp_list_elem)
7198 			qpair->online = online;
7199 			mutex_unlock(&ha->mq_lock);
7200 		}
7201 
7202 		if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7203 				       &base_vha->dpc_flags)) {
7204 			u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7205 
7206 			if (threshold > ha->orig_fw_xcb_count)
7207 				threshold = ha->orig_fw_xcb_count;
7208 
7209 			ql_log(ql_log_info, base_vha, 0xffffff,
7210 			       "SET ZIO Activity exchange threshold to %d.\n",
7211 			       threshold);
7212 			if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7213 				ql_log(ql_log_info, base_vha, 0xffffff,
7214 				       "Unable to SET ZIO Activity exchange threshold to %d.\n",
7215 				       threshold);
7216 			}
7217 		}
7218 
7219 		if (!IS_QLAFX00(ha))
7220 			qla2x00_do_dpc_all_vps(base_vha);
7221 
7222 		if (test_and_clear_bit(N2N_LINK_RESET,
7223 			&base_vha->dpc_flags)) {
7224 			qla2x00_lip_reset(base_vha);
7225 		}
7226 
7227 		ha->dpc_active = 0;
7228 end_loop:
7229 		set_current_state(TASK_INTERRUPTIBLE);
7230 	} /* End of while(1) */
7231 	__set_current_state(TASK_RUNNING);
7232 
7233 	ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7234 	    "DPC handler exiting.\n");
7235 
7236 	/*
7237 	 * Make sure that nobody tries to wake us up again.
7238 	 */
7239 	ha->dpc_active = 0;
7240 
7241 	/* Cleanup any residual CTX SRBs. */
7242 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7243 
7244 	return 0;
7245 }
7246 
7247 void
7248 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7249 {
7250 	struct qla_hw_data *ha = vha->hw;
7251 	struct task_struct *t = ha->dpc_thread;
7252 
7253 	if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7254 		wake_up_process(t);
7255 }
7256 
7257 /*
7258 *  qla2x00_rst_aen
7259 *      Processes asynchronous reset.
7260 *
7261 * Input:
7262 *      ha  = adapter block pointer.
7263 */
7264 static void
7265 qla2x00_rst_aen(scsi_qla_host_t *vha)
7266 {
7267 	if (vha->flags.online && !vha->flags.reset_active &&
7268 	    !atomic_read(&vha->loop_down_timer) &&
7269 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7270 		do {
7271 			clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7272 
7273 			/*
7274 			 * Issue marker command only when we are going to start
7275 			 * the I/O.
7276 			 */
7277 			vha->marker_needed = 1;
7278 		} while (!atomic_read(&vha->loop_down_timer) &&
7279 		    (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7280 	}
7281 }
7282 
7283 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7284 {
7285 	struct qla_hw_data *ha = vha->hw;
7286 	u32 cmpl_cnt;
7287 	u16 i;
7288 	bool do_heartbeat = false;
7289 
7290 	/*
7291 	 * Allow do_heartbeat only if we don’t have any active interrupts,
7292 	 * but there are still IOs outstanding with firmware.
7293 	 */
7294 	cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7295 	if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7296 	    cmpl_cnt != ha->base_qpair->cmd_cnt) {
7297 		do_heartbeat = true;
7298 		goto skip;
7299 	}
7300 	ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7301 
7302 	for (i = 0; i < ha->max_qpairs; i++) {
7303 		if (ha->queue_pair_map[i]) {
7304 			cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7305 			if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7306 			    cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7307 				do_heartbeat = true;
7308 				break;
7309 			}
7310 			ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7311 		}
7312 	}
7313 
7314 skip:
7315 	return do_heartbeat;
7316 }
7317 
7318 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7319 {
7320 	struct qla_hw_data *ha = vha->hw;
7321 
7322 	if (vha->vp_idx)
7323 		return;
7324 
7325 	if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7326 		return;
7327 
7328 	/*
7329 	 * dpc thread cannot run if heartbeat is running at the same time.
7330 	 * We also do not want to starve heartbeat task. Therefore, do
7331 	 * heartbeat task at least once every 5 seconds.
7332 	 */
7333 	if (dpc_started &&
7334 	    time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7335 		return;
7336 
7337 	if (qla_do_heartbeat(vha)) {
7338 		ha->last_heartbeat_run_jiffies = jiffies;
7339 		queue_work(ha->wq, &ha->heartbeat_work);
7340 	}
7341 }
7342 
7343 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7344 {
7345 	struct qla_hw_data *ha = vha->hw;
7346 
7347 	if (!ha->flags.eeh_busy)
7348 		return;
7349 	if (ha->pci_error_state)
7350 		/* system is trying to recover */
7351 		return;
7352 
7353 	/*
7354 	 * Current system is not handling PCIE error.  At this point, this is
7355 	 * best effort to wind down the adapter.
7356 	 */
7357 	if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7358 	    !ha->flags.eeh_flush) {
7359 		ql_log(ql_log_info, vha, 0x9009,
7360 		    "PCI Error detected, attempting to reset hardware.\n");
7361 
7362 		ha->isp_ops->reset_chip(vha);
7363 		ha->isp_ops->disable_intrs(ha);
7364 
7365 		ha->flags.eeh_flush = EEH_FLUSH_RDY;
7366 		ha->eeh_jif = jiffies;
7367 
7368 	} else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7369 	    time_after_eq(jiffies, ha->eeh_jif +  5 * HZ)) {
7370 		pci_clear_master(ha->pdev);
7371 
7372 		/* flush all command */
7373 		qla2x00_abort_isp_cleanup(vha);
7374 		ha->flags.eeh_flush = EEH_FLUSH_DONE;
7375 
7376 		ql_log(ql_log_info, vha, 0x900a,
7377 		    "PCI Error handling complete, all IOs aborted.\n");
7378 	}
7379 }
7380 
7381 /**************************************************************************
7382 *   qla2x00_timer
7383 *
7384 * Description:
7385 *   One second timer
7386 *
7387 * Context: Interrupt
7388 ***************************************************************************/
7389 void
7390 qla2x00_timer(struct timer_list *t)
7391 {
7392 	scsi_qla_host_t *vha = from_timer(vha, t, timer);
7393 	unsigned long	cpu_flags = 0;
7394 	int		start_dpc = 0;
7395 	int		index;
7396 	srb_t		*sp;
7397 	uint16_t        w;
7398 	struct qla_hw_data *ha = vha->hw;
7399 	struct req_que *req;
7400 	unsigned long flags;
7401 	fc_port_t *fcport = NULL;
7402 
7403 	if (ha->flags.eeh_busy) {
7404 		qla_wind_down_chip(vha);
7405 
7406 		ql_dbg(ql_dbg_timer, vha, 0x6000,
7407 		    "EEH = %d, restarting timer.\n",
7408 		    ha->flags.eeh_busy);
7409 		qla2x00_restart_timer(vha, WATCH_INTERVAL);
7410 		return;
7411 	}
7412 
7413 	/*
7414 	 * Hardware read to raise pending EEH errors during mailbox waits. If
7415 	 * the read returns -1 then disable the board.
7416 	 */
7417 	if (!pci_channel_offline(ha->pdev)) {
7418 		pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7419 		qla2x00_check_reg16_for_disconnect(vha, w);
7420 	}
7421 
7422 	/* Make sure qla82xx_watchdog is run only for physical port */
7423 	if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7424 		if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7425 			start_dpc++;
7426 		if (IS_QLA82XX(ha))
7427 			qla82xx_watchdog(vha);
7428 		else if (IS_QLA8044(ha))
7429 			qla8044_watchdog(vha);
7430 	}
7431 
7432 	if (!vha->vp_idx && IS_QLAFX00(ha))
7433 		qlafx00_timer_routine(vha);
7434 
7435 	if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7436 		vha->link_down_time++;
7437 
7438 	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7439 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
7440 		if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7441 			fcport->tgt_link_down_time++;
7442 	}
7443 	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7444 
7445 	/* Loop down handler. */
7446 	if (atomic_read(&vha->loop_down_timer) > 0 &&
7447 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7448 	    !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7449 		&& vha->flags.online) {
7450 
7451 		if (atomic_read(&vha->loop_down_timer) ==
7452 		    vha->loop_down_abort_time) {
7453 
7454 			ql_log(ql_log_info, vha, 0x6008,
7455 			    "Loop down - aborting the queues before time expires.\n");
7456 
7457 			if (!IS_QLA2100(ha) && vha->link_down_timeout)
7458 				atomic_set(&vha->loop_state, LOOP_DEAD);
7459 
7460 			/*
7461 			 * Schedule an ISP abort to return any FCP2-device
7462 			 * commands.
7463 			 */
7464 			/* NPIV - scan physical port only */
7465 			if (!vha->vp_idx) {
7466 				spin_lock_irqsave(&ha->hardware_lock,
7467 				    cpu_flags);
7468 				req = ha->req_q_map[0];
7469 				for (index = 1;
7470 				    index < req->num_outstanding_cmds;
7471 				    index++) {
7472 					fc_port_t *sfcp;
7473 
7474 					sp = req->outstanding_cmds[index];
7475 					if (!sp)
7476 						continue;
7477 					if (sp->cmd_type != TYPE_SRB)
7478 						continue;
7479 					if (sp->type != SRB_SCSI_CMD)
7480 						continue;
7481 					sfcp = sp->fcport;
7482 					if (!(sfcp->flags & FCF_FCP2_DEVICE))
7483 						continue;
7484 
7485 					if (IS_QLA82XX(ha))
7486 						set_bit(FCOE_CTX_RESET_NEEDED,
7487 							&vha->dpc_flags);
7488 					else
7489 						set_bit(ISP_ABORT_NEEDED,
7490 							&vha->dpc_flags);
7491 					break;
7492 				}
7493 				spin_unlock_irqrestore(&ha->hardware_lock,
7494 								cpu_flags);
7495 			}
7496 			start_dpc++;
7497 		}
7498 
7499 		/* if the loop has been down for 4 minutes, reinit adapter */
7500 		if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7501 			if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7502 				ql_log(ql_log_warn, vha, 0x6009,
7503 				    "Loop down - aborting ISP.\n");
7504 
7505 				if (IS_QLA82XX(ha))
7506 					set_bit(FCOE_CTX_RESET_NEEDED,
7507 						&vha->dpc_flags);
7508 				else
7509 					set_bit(ISP_ABORT_NEEDED,
7510 						&vha->dpc_flags);
7511 			}
7512 		}
7513 		ql_dbg(ql_dbg_timer, vha, 0x600a,
7514 		    "Loop down - seconds remaining %d.\n",
7515 		    atomic_read(&vha->loop_down_timer));
7516 	}
7517 	/* Check if beacon LED needs to be blinked for physical host only */
7518 	if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7519 		/* There is no beacon_blink function for ISP82xx */
7520 		if (!IS_P3P_TYPE(ha)) {
7521 			set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7522 			start_dpc++;
7523 		}
7524 	}
7525 
7526 	/* check if edif running */
7527 	if (vha->hw->flags.edif_enabled)
7528 		qla_edif_timer(vha);
7529 
7530 	/* Process any deferred work. */
7531 	if (!list_empty(&vha->work_list)) {
7532 		unsigned long flags;
7533 		bool q = false;
7534 
7535 		spin_lock_irqsave(&vha->work_lock, flags);
7536 		if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7537 			q = true;
7538 		spin_unlock_irqrestore(&vha->work_lock, flags);
7539 		if (q)
7540 			queue_work(vha->hw->wq, &vha->iocb_work);
7541 	}
7542 
7543 	/*
7544 	 * FC-NVME
7545 	 * see if the active AEN count has changed from what was last reported.
7546 	 */
7547 	index = atomic_read(&ha->nvme_active_aen_cnt);
7548 	if (!vha->vp_idx &&
7549 	    (index != ha->nvme_last_rptd_aen) &&
7550 	    ha->zio_mode == QLA_ZIO_MODE_6 &&
7551 	    !ha->flags.host_shutting_down) {
7552 		ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7553 		ql_log(ql_log_info, vha, 0x3002,
7554 		    "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7555 		    ha->nvme_last_rptd_aen);
7556 		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7557 		start_dpc++;
7558 	}
7559 
7560 	if (!vha->vp_idx &&
7561 	    atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7562 	    IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7563 		ql_log(ql_log_info, vha, 0x3002,
7564 		    "Sched: Set ZIO exchange threshold to %d.\n",
7565 		    ha->last_zio_threshold);
7566 		ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7567 		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7568 		start_dpc++;
7569 	}
7570 	qla_adjust_buf(vha);
7571 
7572 	/* borrowing w to signify dpc will run */
7573 	w = 0;
7574 	/* Schedule the DPC routine if needed */
7575 	if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7576 	    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7577 	    start_dpc ||
7578 	    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7579 	    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7580 	    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7581 	    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7582 	    test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7583 	    test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7584 	    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7585 		ql_dbg(ql_dbg_timer, vha, 0x600b,
7586 		    "isp_abort_needed=%d loop_resync_needed=%d "
7587 		    "start_dpc=%d reset_marker_needed=%d",
7588 		    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7589 		    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7590 		    start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7591 		ql_dbg(ql_dbg_timer, vha, 0x600c,
7592 		    "beacon_blink_needed=%d isp_unrecoverable=%d "
7593 		    "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7594 		    "relogin_needed=%d, Process_purex_iocb=%d.\n",
7595 		    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7596 		    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7597 		    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7598 		    test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7599 		    test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7600 		    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7601 		qla2xxx_wake_dpc(vha);
7602 		w = 1;
7603 	}
7604 
7605 	qla_heart_beat(vha, w);
7606 
7607 	qla2x00_restart_timer(vha, WATCH_INTERVAL);
7608 }
7609 
7610 /* Firmware interface routines. */
7611 
7612 #define FW_ISP21XX	0
7613 #define FW_ISP22XX	1
7614 #define FW_ISP2300	2
7615 #define FW_ISP2322	3
7616 #define FW_ISP24XX	4
7617 #define FW_ISP25XX	5
7618 #define FW_ISP81XX	6
7619 #define FW_ISP82XX	7
7620 #define FW_ISP2031	8
7621 #define FW_ISP8031	9
7622 #define FW_ISP27XX	10
7623 #define FW_ISP28XX	11
7624 
7625 #define FW_FILE_ISP21XX	"ql2100_fw.bin"
7626 #define FW_FILE_ISP22XX	"ql2200_fw.bin"
7627 #define FW_FILE_ISP2300	"ql2300_fw.bin"
7628 #define FW_FILE_ISP2322	"ql2322_fw.bin"
7629 #define FW_FILE_ISP24XX	"ql2400_fw.bin"
7630 #define FW_FILE_ISP25XX	"ql2500_fw.bin"
7631 #define FW_FILE_ISP81XX	"ql8100_fw.bin"
7632 #define FW_FILE_ISP82XX	"ql8200_fw.bin"
7633 #define FW_FILE_ISP2031	"ql2600_fw.bin"
7634 #define FW_FILE_ISP8031	"ql8300_fw.bin"
7635 #define FW_FILE_ISP27XX	"ql2700_fw.bin"
7636 #define FW_FILE_ISP28XX	"ql2800_fw.bin"
7637 
7638 
7639 static DEFINE_MUTEX(qla_fw_lock);
7640 
7641 static struct fw_blob qla_fw_blobs[] = {
7642 	{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7643 	{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7644 	{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7645 	{ .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7646 	{ .name = FW_FILE_ISP24XX, },
7647 	{ .name = FW_FILE_ISP25XX, },
7648 	{ .name = FW_FILE_ISP81XX, },
7649 	{ .name = FW_FILE_ISP82XX, },
7650 	{ .name = FW_FILE_ISP2031, },
7651 	{ .name = FW_FILE_ISP8031, },
7652 	{ .name = FW_FILE_ISP27XX, },
7653 	{ .name = FW_FILE_ISP28XX, },
7654 	{ .name = NULL, },
7655 };
7656 
7657 struct fw_blob *
7658 qla2x00_request_firmware(scsi_qla_host_t *vha)
7659 {
7660 	struct qla_hw_data *ha = vha->hw;
7661 	struct fw_blob *blob;
7662 
7663 	if (IS_QLA2100(ha)) {
7664 		blob = &qla_fw_blobs[FW_ISP21XX];
7665 	} else if (IS_QLA2200(ha)) {
7666 		blob = &qla_fw_blobs[FW_ISP22XX];
7667 	} else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7668 		blob = &qla_fw_blobs[FW_ISP2300];
7669 	} else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7670 		blob = &qla_fw_blobs[FW_ISP2322];
7671 	} else if (IS_QLA24XX_TYPE(ha)) {
7672 		blob = &qla_fw_blobs[FW_ISP24XX];
7673 	} else if (IS_QLA25XX(ha)) {
7674 		blob = &qla_fw_blobs[FW_ISP25XX];
7675 	} else if (IS_QLA81XX(ha)) {
7676 		blob = &qla_fw_blobs[FW_ISP81XX];
7677 	} else if (IS_QLA82XX(ha)) {
7678 		blob = &qla_fw_blobs[FW_ISP82XX];
7679 	} else if (IS_QLA2031(ha)) {
7680 		blob = &qla_fw_blobs[FW_ISP2031];
7681 	} else if (IS_QLA8031(ha)) {
7682 		blob = &qla_fw_blobs[FW_ISP8031];
7683 	} else if (IS_QLA27XX(ha)) {
7684 		blob = &qla_fw_blobs[FW_ISP27XX];
7685 	} else if (IS_QLA28XX(ha)) {
7686 		blob = &qla_fw_blobs[FW_ISP28XX];
7687 	} else {
7688 		return NULL;
7689 	}
7690 
7691 	if (!blob->name)
7692 		return NULL;
7693 
7694 	mutex_lock(&qla_fw_lock);
7695 	if (blob->fw)
7696 		goto out;
7697 
7698 	if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7699 		ql_log(ql_log_warn, vha, 0x0063,
7700 		    "Failed to load firmware image (%s).\n", blob->name);
7701 		blob->fw = NULL;
7702 		blob = NULL;
7703 	}
7704 
7705 out:
7706 	mutex_unlock(&qla_fw_lock);
7707 	return blob;
7708 }
7709 
7710 static void
7711 qla2x00_release_firmware(void)
7712 {
7713 	struct fw_blob *blob;
7714 
7715 	mutex_lock(&qla_fw_lock);
7716 	for (blob = qla_fw_blobs; blob->name; blob++)
7717 		release_firmware(blob->fw);
7718 	mutex_unlock(&qla_fw_lock);
7719 }
7720 
7721 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7722 {
7723 	struct qla_hw_data *ha = vha->hw;
7724 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7725 	struct qla_qpair *qpair = NULL;
7726 	struct scsi_qla_host *vp, *tvp;
7727 	fc_port_t *fcport;
7728 	int i;
7729 	unsigned long flags;
7730 
7731 	ql_dbg(ql_dbg_aer, vha, 0x9000,
7732 	       "%s\n", __func__);
7733 	ha->chip_reset++;
7734 
7735 	ha->base_qpair->chip_reset = ha->chip_reset;
7736 	for (i = 0; i < ha->max_qpairs; i++) {
7737 		if (ha->queue_pair_map[i])
7738 			ha->queue_pair_map[i]->chip_reset =
7739 			    ha->base_qpair->chip_reset;
7740 	}
7741 
7742 	/*
7743 	 * purge mailbox might take a while. Slot Reset/chip reset
7744 	 * will take care of the purge
7745 	 */
7746 
7747 	mutex_lock(&ha->mq_lock);
7748 	ha->base_qpair->online = 0;
7749 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7750 		qpair->online = 0;
7751 	wmb();
7752 	mutex_unlock(&ha->mq_lock);
7753 
7754 	qla2x00_mark_all_devices_lost(vha);
7755 
7756 	spin_lock_irqsave(&ha->vport_slock, flags);
7757 	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7758 		atomic_inc(&vp->vref_count);
7759 		spin_unlock_irqrestore(&ha->vport_slock, flags);
7760 		qla2x00_mark_all_devices_lost(vp);
7761 		spin_lock_irqsave(&ha->vport_slock, flags);
7762 		atomic_dec(&vp->vref_count);
7763 	}
7764 	spin_unlock_irqrestore(&ha->vport_slock, flags);
7765 
7766 	/* Clear all async request states across all VPs. */
7767 	list_for_each_entry(fcport, &vha->vp_fcports, list)
7768 		fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7769 
7770 	spin_lock_irqsave(&ha->vport_slock, flags);
7771 	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7772 		atomic_inc(&vp->vref_count);
7773 		spin_unlock_irqrestore(&ha->vport_slock, flags);
7774 		list_for_each_entry(fcport, &vp->vp_fcports, list)
7775 			fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7776 		spin_lock_irqsave(&ha->vport_slock, flags);
7777 		atomic_dec(&vp->vref_count);
7778 	}
7779 	spin_unlock_irqrestore(&ha->vport_slock, flags);
7780 }
7781 
7782 
7783 static pci_ers_result_t
7784 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7785 {
7786 	scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7787 	struct qla_hw_data *ha = vha->hw;
7788 	pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7789 
7790 	ql_log(ql_log_warn, vha, 0x9000,
7791 	       "PCI error detected, state %x.\n", state);
7792 	ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7793 
7794 	if (!atomic_read(&pdev->enable_cnt)) {
7795 		ql_log(ql_log_info, vha, 0xffff,
7796 			"PCI device is disabled,state %x\n", state);
7797 		ret = PCI_ERS_RESULT_NEED_RESET;
7798 		goto out;
7799 	}
7800 
7801 	switch (state) {
7802 	case pci_channel_io_normal:
7803 		qla_pci_set_eeh_busy(vha);
7804 		if (ql2xmqsupport || ql2xnvmeenable) {
7805 			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7806 			qla2xxx_wake_dpc(vha);
7807 		}
7808 		ret = PCI_ERS_RESULT_CAN_RECOVER;
7809 		break;
7810 	case pci_channel_io_frozen:
7811 		qla_pci_set_eeh_busy(vha);
7812 		ret = PCI_ERS_RESULT_NEED_RESET;
7813 		break;
7814 	case pci_channel_io_perm_failure:
7815 		ha->flags.pci_channel_io_perm_failure = 1;
7816 		qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7817 		if (ql2xmqsupport || ql2xnvmeenable) {
7818 			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7819 			qla2xxx_wake_dpc(vha);
7820 		}
7821 		ret = PCI_ERS_RESULT_DISCONNECT;
7822 	}
7823 out:
7824 	ql_dbg(ql_dbg_aer, vha, 0x600d,
7825 	       "PCI error detected returning [%x].\n", ret);
7826 	return ret;
7827 }
7828 
7829 static pci_ers_result_t
7830 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7831 {
7832 	int risc_paused = 0;
7833 	uint32_t stat;
7834 	unsigned long flags;
7835 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7836 	struct qla_hw_data *ha = base_vha->hw;
7837 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7838 	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7839 
7840 	ql_log(ql_log_warn, base_vha, 0x9000,
7841 	       "mmio enabled\n");
7842 
7843 	ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7844 
7845 	if (IS_QLA82XX(ha))
7846 		return PCI_ERS_RESULT_RECOVERED;
7847 
7848 	if (qla2x00_isp_reg_stat(ha)) {
7849 		ql_log(ql_log_info, base_vha, 0x803f,
7850 		    "During mmio enabled, PCI/Register disconnect still detected.\n");
7851 		goto out;
7852 	}
7853 
7854 	spin_lock_irqsave(&ha->hardware_lock, flags);
7855 	if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7856 		stat = rd_reg_word(&reg->hccr);
7857 		if (stat & HCCR_RISC_PAUSE)
7858 			risc_paused = 1;
7859 	} else if (IS_QLA23XX(ha)) {
7860 		stat = rd_reg_dword(&reg->u.isp2300.host_status);
7861 		if (stat & HSR_RISC_PAUSED)
7862 			risc_paused = 1;
7863 	} else if (IS_FWI2_CAPABLE(ha)) {
7864 		stat = rd_reg_dword(&reg24->host_status);
7865 		if (stat & HSRX_RISC_PAUSED)
7866 			risc_paused = 1;
7867 	}
7868 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
7869 
7870 	if (risc_paused) {
7871 		ql_log(ql_log_info, base_vha, 0x9003,
7872 		    "RISC paused -- mmio_enabled, Dumping firmware.\n");
7873 		qla2xxx_dump_fw(base_vha);
7874 	}
7875 out:
7876 	/* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7877 	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7878 	       "mmio enabled returning.\n");
7879 	return PCI_ERS_RESULT_NEED_RESET;
7880 }
7881 
7882 static pci_ers_result_t
7883 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7884 {
7885 	pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7886 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7887 	struct qla_hw_data *ha = base_vha->hw;
7888 	int rc;
7889 	struct qla_qpair *qpair = NULL;
7890 
7891 	ql_log(ql_log_warn, base_vha, 0x9004,
7892 	       "Slot Reset.\n");
7893 
7894 	ha->pci_error_state = QLA_PCI_SLOT_RESET;
7895 	/* Workaround: qla2xxx driver which access hardware earlier
7896 	 * needs error state to be pci_channel_io_online.
7897 	 * Otherwise mailbox command timesout.
7898 	 */
7899 	pdev->error_state = pci_channel_io_normal;
7900 
7901 	pci_restore_state(pdev);
7902 
7903 	/* pci_restore_state() clears the saved_state flag of the device
7904 	 * save restored state which resets saved_state flag
7905 	 */
7906 	pci_save_state(pdev);
7907 
7908 	if (ha->mem_only)
7909 		rc = pci_enable_device_mem(pdev);
7910 	else
7911 		rc = pci_enable_device(pdev);
7912 
7913 	if (rc) {
7914 		ql_log(ql_log_warn, base_vha, 0x9005,
7915 		    "Can't re-enable PCI device after reset.\n");
7916 		goto exit_slot_reset;
7917 	}
7918 
7919 
7920 	if (ha->isp_ops->pci_config(base_vha))
7921 		goto exit_slot_reset;
7922 
7923 	mutex_lock(&ha->mq_lock);
7924 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7925 		qpair->online = 1;
7926 	mutex_unlock(&ha->mq_lock);
7927 
7928 	ha->flags.eeh_busy = 0;
7929 	base_vha->flags.online = 1;
7930 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7931 	ha->isp_ops->abort_isp(base_vha);
7932 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7933 
7934 	if (qla2x00_isp_reg_stat(ha)) {
7935 		ha->flags.eeh_busy = 1;
7936 		qla_pci_error_cleanup(base_vha);
7937 		ql_log(ql_log_warn, base_vha, 0x9005,
7938 		       "Device unable to recover from PCI error.\n");
7939 	} else {
7940 		ret =  PCI_ERS_RESULT_RECOVERED;
7941 	}
7942 
7943 exit_slot_reset:
7944 	ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7945 	    "Slot Reset returning %x.\n", ret);
7946 
7947 	return ret;
7948 }
7949 
7950 static void
7951 qla2xxx_pci_resume(struct pci_dev *pdev)
7952 {
7953 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7954 	struct qla_hw_data *ha = base_vha->hw;
7955 	int ret;
7956 
7957 	ql_log(ql_log_warn, base_vha, 0x900f,
7958 	       "Pci Resume.\n");
7959 
7960 
7961 	ret = qla2x00_wait_for_hba_online(base_vha);
7962 	if (ret != QLA_SUCCESS) {
7963 		ql_log(ql_log_fatal, base_vha, 0x9002,
7964 		    "The device failed to resume I/O from slot/link_reset.\n");
7965 	}
7966 	ha->pci_error_state = QLA_PCI_RESUME;
7967 	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7968 	       "Pci Resume returning.\n");
7969 }
7970 
7971 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7972 {
7973 	struct qla_hw_data *ha = vha->hw;
7974 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7975 	bool do_cleanup = false;
7976 	unsigned long flags;
7977 
7978 	if (ha->flags.eeh_busy)
7979 		return;
7980 
7981 	spin_lock_irqsave(&base_vha->work_lock, flags);
7982 	if (!ha->flags.eeh_busy) {
7983 		ha->eeh_jif = jiffies;
7984 		ha->flags.eeh_flush = 0;
7985 
7986 		ha->flags.eeh_busy = 1;
7987 		do_cleanup = true;
7988 	}
7989 	spin_unlock_irqrestore(&base_vha->work_lock, flags);
7990 
7991 	if (do_cleanup)
7992 		qla_pci_error_cleanup(base_vha);
7993 }
7994 
7995 /*
7996  * this routine will schedule a task to pause IO from interrupt context
7997  * if caller sees a PCIE error event (register read = 0xf's)
7998  */
7999 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8000 {
8001 	struct qla_hw_data *ha = vha->hw;
8002 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8003 
8004 	if (ha->flags.eeh_busy)
8005 		return;
8006 
8007 	set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8008 	qla2xxx_wake_dpc(base_vha);
8009 }
8010 
8011 static void
8012 qla_pci_reset_prepare(struct pci_dev *pdev)
8013 {
8014 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8015 	struct qla_hw_data *ha = base_vha->hw;
8016 	struct qla_qpair *qpair;
8017 
8018 	ql_log(ql_log_warn, base_vha, 0xffff,
8019 	    "%s.\n", __func__);
8020 
8021 	/*
8022 	 * PCI FLR/function reset is about to reset the
8023 	 * slot. Stop the chip to stop all DMA access.
8024 	 * It is assumed that pci_reset_done will be called
8025 	 * after FLR to resume Chip operation.
8026 	 */
8027 	ha->flags.eeh_busy = 1;
8028 	mutex_lock(&ha->mq_lock);
8029 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8030 		qpair->online = 0;
8031 	mutex_unlock(&ha->mq_lock);
8032 
8033 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8034 	qla2x00_abort_isp_cleanup(base_vha);
8035 	qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8036 }
8037 
8038 static void
8039 qla_pci_reset_done(struct pci_dev *pdev)
8040 {
8041 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8042 	struct qla_hw_data *ha = base_vha->hw;
8043 	struct qla_qpair *qpair;
8044 
8045 	ql_log(ql_log_warn, base_vha, 0xffff,
8046 	    "%s.\n", __func__);
8047 
8048 	/*
8049 	 * FLR just completed by PCI layer. Resume adapter
8050 	 */
8051 	ha->flags.eeh_busy = 0;
8052 	mutex_lock(&ha->mq_lock);
8053 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8054 		qpair->online = 1;
8055 	mutex_unlock(&ha->mq_lock);
8056 
8057 	base_vha->flags.online = 1;
8058 	ha->isp_ops->abort_isp(base_vha);
8059 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8060 }
8061 
8062 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8063 {
8064 	scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8065 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8066 
8067 	if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8068 		blk_mq_map_queues(qmap);
8069 	else
8070 		blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
8071 }
8072 
8073 struct scsi_host_template qla2xxx_driver_template = {
8074 	.module			= THIS_MODULE,
8075 	.name			= QLA2XXX_DRIVER_NAME,
8076 	.queuecommand		= qla2xxx_queuecommand,
8077 
8078 	.eh_timed_out		= fc_eh_timed_out,
8079 	.eh_abort_handler	= qla2xxx_eh_abort,
8080 	.eh_should_retry_cmd	= fc_eh_should_retry_cmd,
8081 	.eh_device_reset_handler = qla2xxx_eh_device_reset,
8082 	.eh_target_reset_handler = qla2xxx_eh_target_reset,
8083 	.eh_bus_reset_handler	= qla2xxx_eh_bus_reset,
8084 	.eh_host_reset_handler	= qla2xxx_eh_host_reset,
8085 
8086 	.slave_configure	= qla2xxx_slave_configure,
8087 
8088 	.slave_alloc		= qla2xxx_slave_alloc,
8089 	.slave_destroy		= qla2xxx_slave_destroy,
8090 	.scan_finished		= qla2xxx_scan_finished,
8091 	.scan_start		= qla2xxx_scan_start,
8092 	.change_queue_depth	= scsi_change_queue_depth,
8093 	.map_queues             = qla2xxx_map_queues,
8094 	.this_id		= -1,
8095 	.cmd_per_lun		= 3,
8096 	.sg_tablesize		= SG_ALL,
8097 
8098 	.max_sectors		= 0xFFFF,
8099 	.shost_groups		= qla2x00_host_groups,
8100 
8101 	.supported_mode		= MODE_INITIATOR,
8102 	.track_queue_depth	= 1,
8103 	.cmd_size		= sizeof(srb_t),
8104 };
8105 
8106 static const struct pci_error_handlers qla2xxx_err_handler = {
8107 	.error_detected = qla2xxx_pci_error_detected,
8108 	.mmio_enabled = qla2xxx_pci_mmio_enabled,
8109 	.slot_reset = qla2xxx_pci_slot_reset,
8110 	.resume = qla2xxx_pci_resume,
8111 	.reset_prepare = qla_pci_reset_prepare,
8112 	.reset_done = qla_pci_reset_done,
8113 };
8114 
8115 static struct pci_device_id qla2xxx_pci_tbl[] = {
8116 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8117 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8118 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8119 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8120 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8121 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8122 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8123 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8124 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8125 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8126 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8127 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8128 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8129 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8130 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8131 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8132 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8133 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8134 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8135 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8136 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8137 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8138 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8139 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8140 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8141 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8142 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8143 	{ 0 },
8144 };
8145 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8146 
8147 static struct pci_driver qla2xxx_pci_driver = {
8148 	.name		= QLA2XXX_DRIVER_NAME,
8149 	.driver		= {
8150 		.owner		= THIS_MODULE,
8151 	},
8152 	.id_table	= qla2xxx_pci_tbl,
8153 	.probe		= qla2x00_probe_one,
8154 	.remove		= qla2x00_remove_one,
8155 	.shutdown	= qla2x00_shutdown,
8156 	.err_handler	= &qla2xxx_err_handler,
8157 };
8158 
8159 static const struct file_operations apidev_fops = {
8160 	.owner = THIS_MODULE,
8161 	.llseek = noop_llseek,
8162 };
8163 
8164 /**
8165  * qla2x00_module_init - Module initialization.
8166  **/
8167 static int __init
8168 qla2x00_module_init(void)
8169 {
8170 	int ret = 0;
8171 
8172 	BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8173 	BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8174 	BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8175 	BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8176 	BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8177 	BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8178 	BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8179 	BUILD_BUG_ON(sizeof(request_t) != 64);
8180 	BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8181 	BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8182 	BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8183 	BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8184 	BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8185 	BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8186 	BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8187 	BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8188 	BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8189 	BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8190 	BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8191 	BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8192 	BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8193 	BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8194 	BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8195 	BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8196 	BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8197 	BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8198 	BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8199 	BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8200 	BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8201 	BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8202 	BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8203 	BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8204 	BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8205 	BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8206 	BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8207 	BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8208 	BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8209 	BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8210 	BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8211 	BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8212 	BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8213 	BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8214 	BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8215 	BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8216 	BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8217 	BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8218 	BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8219 	BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8220 	BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8221 	BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8222 	BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8223 	BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8224 	BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8225 	BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8226 	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8227 	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8228 	BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8229 	BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8230 	BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8231 	BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8232 	BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8233 	BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8234 	BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8235 	BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8236 	BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8237 	BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8238 	BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8239 	BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8240 	BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8241 	BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8242 	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8243 	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8244 	BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8245 	BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8246 	BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8247 	BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8248 	BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8249 	BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8250 	BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8251 	BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8252 	BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8253 	BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8254 	BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8255 	BUILD_BUG_ON(sizeof(target_id_t) != 2);
8256 
8257 	qla_trace_init();
8258 
8259 	/* Allocate cache for SRBs. */
8260 	srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8261 	    SLAB_HWCACHE_ALIGN, NULL);
8262 	if (srb_cachep == NULL) {
8263 		ql_log(ql_log_fatal, NULL, 0x0001,
8264 		    "Unable to allocate SRB cache...Failing load!.\n");
8265 		return -ENOMEM;
8266 	}
8267 
8268 	/* Initialize target kmem_cache and mem_pools */
8269 	ret = qlt_init();
8270 	if (ret < 0) {
8271 		goto destroy_cache;
8272 	} else if (ret > 0) {
8273 		/*
8274 		 * If initiator mode is explictly disabled by qlt_init(),
8275 		 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8276 		 * performing scsi_scan_target() during LOOP UP event.
8277 		 */
8278 		qla2xxx_transport_functions.disable_target_scan = 1;
8279 		qla2xxx_transport_vport_functions.disable_target_scan = 1;
8280 	}
8281 
8282 	/* Derive version string. */
8283 	strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8284 	if (ql2xextended_error_logging)
8285 		strcat(qla2x00_version_str, "-debug");
8286 	if (ql2xextended_error_logging == 1)
8287 		ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8288 
8289 	qla2xxx_transport_template =
8290 	    fc_attach_transport(&qla2xxx_transport_functions);
8291 	if (!qla2xxx_transport_template) {
8292 		ql_log(ql_log_fatal, NULL, 0x0002,
8293 		    "fc_attach_transport failed...Failing load!.\n");
8294 		ret = -ENODEV;
8295 		goto qlt_exit;
8296 	}
8297 
8298 	apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8299 	if (apidev_major < 0) {
8300 		ql_log(ql_log_fatal, NULL, 0x0003,
8301 		    "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8302 	}
8303 
8304 	qla2xxx_transport_vport_template =
8305 	    fc_attach_transport(&qla2xxx_transport_vport_functions);
8306 	if (!qla2xxx_transport_vport_template) {
8307 		ql_log(ql_log_fatal, NULL, 0x0004,
8308 		    "fc_attach_transport vport failed...Failing load!.\n");
8309 		ret = -ENODEV;
8310 		goto unreg_chrdev;
8311 	}
8312 	ql_log(ql_log_info, NULL, 0x0005,
8313 	    "QLogic Fibre Channel HBA Driver: %s.\n",
8314 	    qla2x00_version_str);
8315 	ret = pci_register_driver(&qla2xxx_pci_driver);
8316 	if (ret) {
8317 		ql_log(ql_log_fatal, NULL, 0x0006,
8318 		    "pci_register_driver failed...ret=%d Failing load!.\n",
8319 		    ret);
8320 		goto release_vport_transport;
8321 	}
8322 	return ret;
8323 
8324 release_vport_transport:
8325 	fc_release_transport(qla2xxx_transport_vport_template);
8326 
8327 unreg_chrdev:
8328 	if (apidev_major >= 0)
8329 		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8330 	fc_release_transport(qla2xxx_transport_template);
8331 
8332 qlt_exit:
8333 	qlt_exit();
8334 
8335 destroy_cache:
8336 	kmem_cache_destroy(srb_cachep);
8337 
8338 	qla_trace_uninit();
8339 	return ret;
8340 }
8341 
8342 /**
8343  * qla2x00_module_exit - Module cleanup.
8344  **/
8345 static void __exit
8346 qla2x00_module_exit(void)
8347 {
8348 	pci_unregister_driver(&qla2xxx_pci_driver);
8349 	qla2x00_release_firmware();
8350 	kmem_cache_destroy(ctx_cachep);
8351 	fc_release_transport(qla2xxx_transport_vport_template);
8352 	if (apidev_major >= 0)
8353 		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8354 	fc_release_transport(qla2xxx_transport_template);
8355 	qlt_exit();
8356 	kmem_cache_destroy(srb_cachep);
8357 	qla_trace_uninit();
8358 }
8359 
8360 module_init(qla2x00_module_init);
8361 module_exit(qla2x00_module_exit);
8362 
8363 MODULE_AUTHOR("QLogic Corporation");
8364 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8365 MODULE_LICENSE("GPL");
8366 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8367 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8368 MODULE_FIRMWARE(FW_FILE_ISP2300);
8369 MODULE_FIRMWARE(FW_FILE_ISP2322);
8370 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8371 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8372