1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 /* 23 * Driver version 24 */ 25 char qla2x00_version_str[40]; 26 27 static int apidev_major; 28 29 /* 30 * SRB allocation cache 31 */ 32 static struct kmem_cache *srb_cachep; 33 34 /* 35 * CT6 CTX allocation cache 36 */ 37 static struct kmem_cache *ctx_cachep; 38 /* 39 * error level for logging 40 */ 41 int ql_errlev = ql_log_all; 42 43 int ql2xlogintimeout = 20; 44 module_param(ql2xlogintimeout, int, S_IRUGO); 45 MODULE_PARM_DESC(ql2xlogintimeout, 46 "Login timeout value in seconds."); 47 48 int qlport_down_retry; 49 module_param(qlport_down_retry, int, S_IRUGO); 50 MODULE_PARM_DESC(qlport_down_retry, 51 "Maximum number of command retries to a port that returns " 52 "a PORT-DOWN status."); 53 54 int ql2xplogiabsentdevice; 55 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 56 MODULE_PARM_DESC(ql2xplogiabsentdevice, 57 "Option to enable PLOGI to devices that are not present after " 58 "a Fabric scan. This is needed for several broken switches. " 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 60 61 int ql2xloginretrycount = 0; 62 module_param(ql2xloginretrycount, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xloginretrycount, 64 "Specify an alternate value for the NVRAM login retry count."); 65 66 int ql2xallocfwdump = 1; 67 module_param(ql2xallocfwdump, int, S_IRUGO); 68 MODULE_PARM_DESC(ql2xallocfwdump, 69 "Option to enable allocation of memory for a firmware dump " 70 "during HBA initialization. Memory allocation requirements " 71 "vary by ISP type. Default is 1 - allocate memory."); 72 73 int ql2xextended_error_logging; 74 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 75 MODULE_PARM_DESC(ql2xextended_error_logging, 76 "Option to enable extended error logging,\n" 77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 86 "\t\tDo LOGICAL OR of the value to enable more than one level"); 87 88 int ql2xshiftctondsd = 6; 89 module_param(ql2xshiftctondsd, int, S_IRUGO); 90 MODULE_PARM_DESC(ql2xshiftctondsd, 91 "Set to control shifting of command type processing " 92 "based on total number of SG elements."); 93 94 static void qla2x00_free_device(scsi_qla_host_t *); 95 96 int ql2xfdmienable=1; 97 module_param(ql2xfdmienable, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xfdmienable, 99 "Enables FDMI registrations. " 100 "0 - no FDMI. Default is 1 - perform FDMI."); 101 102 #define MAX_Q_DEPTH 32 103 static int ql2xmaxqdepth = MAX_Q_DEPTH; 104 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 105 MODULE_PARM_DESC(ql2xmaxqdepth, 106 "Maximum queue depth to report for target devices."); 107 108 /* Do not change the value of this after module load */ 109 int ql2xenabledif = 0; 110 module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); 111 MODULE_PARM_DESC(ql2xenabledif, 112 " Enable T10-CRC-DIF " 113 " Default is 0 - No DIF Support. 1 - Enable it" 114 ", 2 - Enable DIF for all types, except Type 0."); 115 116 int ql2xenablehba_err_chk = 2; 117 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 118 MODULE_PARM_DESC(ql2xenablehba_err_chk, 119 " Enable T10-CRC-DIF Error isolation by HBA:\n" 120 " Default is 1.\n" 121 " 0 -- Error isolation disabled\n" 122 " 1 -- Error isolation enabled only for DIX Type 0\n" 123 " 2 -- Error isolation enabled for all Types\n"); 124 125 int ql2xiidmaenable=1; 126 module_param(ql2xiidmaenable, int, S_IRUGO); 127 MODULE_PARM_DESC(ql2xiidmaenable, 128 "Enables iIDMA settings " 129 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 130 131 int ql2xmaxqueues = 1; 132 module_param(ql2xmaxqueues, int, S_IRUGO); 133 MODULE_PARM_DESC(ql2xmaxqueues, 134 "Enables MQ settings " 135 "Default is 1 for single queue. Set it to number " 136 "of queues in MQ mode."); 137 138 int ql2xmultique_tag; 139 module_param(ql2xmultique_tag, int, S_IRUGO); 140 MODULE_PARM_DESC(ql2xmultique_tag, 141 "Enables CPU affinity settings for the driver " 142 "Default is 0 for no affinity of request and response IO. " 143 "Set it to 1 to turn on the cpu affinity."); 144 145 int ql2xfwloadbin; 146 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 147 MODULE_PARM_DESC(ql2xfwloadbin, 148 "Option to specify location from which to load ISP firmware:.\n" 149 " 2 -- load firmware via the request_firmware() (hotplug).\n" 150 " interface.\n" 151 " 1 -- load firmware from flash.\n" 152 " 0 -- use default semantics.\n"); 153 154 int ql2xetsenable; 155 module_param(ql2xetsenable, int, S_IRUGO); 156 MODULE_PARM_DESC(ql2xetsenable, 157 "Enables firmware ETS burst." 158 "Default is 0 - skip ETS enablement."); 159 160 int ql2xdbwr = 1; 161 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 162 MODULE_PARM_DESC(ql2xdbwr, 163 "Option to specify scheme for request queue posting.\n" 164 " 0 -- Regular doorbell.\n" 165 " 1 -- CAMRAM doorbell (faster).\n"); 166 167 int ql2xtargetreset = 1; 168 module_param(ql2xtargetreset, int, S_IRUGO); 169 MODULE_PARM_DESC(ql2xtargetreset, 170 "Enable target reset." 171 "Default is 1 - use hw defaults."); 172 173 int ql2xgffidenable; 174 module_param(ql2xgffidenable, int, S_IRUGO); 175 MODULE_PARM_DESC(ql2xgffidenable, 176 "Enables GFF_ID checks of port type. " 177 "Default is 0 - Do not use GFF_ID information."); 178 179 int ql2xasynctmfenable; 180 module_param(ql2xasynctmfenable, int, S_IRUGO); 181 MODULE_PARM_DESC(ql2xasynctmfenable, 182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 183 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 184 185 int ql2xdontresethba; 186 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 187 MODULE_PARM_DESC(ql2xdontresethba, 188 "Option to specify reset behaviour.\n" 189 " 0 (Default) -- Reset on failure.\n" 190 " 1 -- Do not reset on failure.\n"); 191 192 uint ql2xmaxlun = MAX_LUNS; 193 module_param(ql2xmaxlun, uint, S_IRUGO); 194 MODULE_PARM_DESC(ql2xmaxlun, 195 "Defines the maximum LU number to register with the SCSI " 196 "midlayer. Default is 65535."); 197 198 int ql2xmdcapmask = 0x1F; 199 module_param(ql2xmdcapmask, int, S_IRUGO); 200 MODULE_PARM_DESC(ql2xmdcapmask, 201 "Set the Minidump driver capture mask level. " 202 "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 203 204 int ql2xmdenable; 205 module_param(ql2xmdenable, int, S_IRUGO); 206 MODULE_PARM_DESC(ql2xmdenable, 207 "Enable/disable MiniDump. " 208 "0 (Default) - MiniDump disabled. " 209 "1 - MiniDump enabled."); 210 211 /* 212 * SCSI host template entry points 213 */ 214 static int qla2xxx_slave_configure(struct scsi_device * device); 215 static int qla2xxx_slave_alloc(struct scsi_device *); 216 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 217 static void qla2xxx_scan_start(struct Scsi_Host *); 218 static void qla2xxx_slave_destroy(struct scsi_device *); 219 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 220 static int qla2xxx_eh_abort(struct scsi_cmnd *); 221 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 222 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 223 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 224 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 225 226 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 227 static int qla2x00_change_queue_type(struct scsi_device *, int); 228 229 struct scsi_host_template qla2xxx_driver_template = { 230 .module = THIS_MODULE, 231 .name = QLA2XXX_DRIVER_NAME, 232 .queuecommand = qla2xxx_queuecommand, 233 234 .eh_abort_handler = qla2xxx_eh_abort, 235 .eh_device_reset_handler = qla2xxx_eh_device_reset, 236 .eh_target_reset_handler = qla2xxx_eh_target_reset, 237 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 238 .eh_host_reset_handler = qla2xxx_eh_host_reset, 239 240 .slave_configure = qla2xxx_slave_configure, 241 242 .slave_alloc = qla2xxx_slave_alloc, 243 .slave_destroy = qla2xxx_slave_destroy, 244 .scan_finished = qla2xxx_scan_finished, 245 .scan_start = qla2xxx_scan_start, 246 .change_queue_depth = qla2x00_change_queue_depth, 247 .change_queue_type = qla2x00_change_queue_type, 248 .this_id = -1, 249 .cmd_per_lun = 3, 250 .use_clustering = ENABLE_CLUSTERING, 251 .sg_tablesize = SG_ALL, 252 253 .max_sectors = 0xFFFF, 254 .shost_attrs = qla2x00_host_attrs, 255 }; 256 257 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 258 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 259 260 /* TODO Convert to inlines 261 * 262 * Timer routines 263 */ 264 265 __inline__ void 266 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 267 { 268 init_timer(&vha->timer); 269 vha->timer.expires = jiffies + interval * HZ; 270 vha->timer.data = (unsigned long)vha; 271 vha->timer.function = (void (*)(unsigned long))func; 272 add_timer(&vha->timer); 273 vha->timer_active = 1; 274 } 275 276 static inline void 277 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 278 { 279 /* Currently used for 82XX only. */ 280 if (vha->device_flags & DFLG_DEV_FAILED) { 281 ql_dbg(ql_dbg_timer, vha, 0x600d, 282 "Device in a failed state, returning.\n"); 283 return; 284 } 285 286 mod_timer(&vha->timer, jiffies + interval * HZ); 287 } 288 289 static __inline__ void 290 qla2x00_stop_timer(scsi_qla_host_t *vha) 291 { 292 del_timer_sync(&vha->timer); 293 vha->timer_active = 0; 294 } 295 296 static int qla2x00_do_dpc(void *data); 297 298 static void qla2x00_rst_aen(scsi_qla_host_t *); 299 300 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 301 struct req_que **, struct rsp_que **); 302 static void qla2x00_free_fw_dump(struct qla_hw_data *); 303 static void qla2x00_mem_free(struct qla_hw_data *); 304 static void qla2x00_sp_free_dma(srb_t *); 305 306 /* -------------------------------------------------------------------------- */ 307 static int qla2x00_alloc_queues(struct qla_hw_data *ha) 308 { 309 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 310 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 311 GFP_KERNEL); 312 if (!ha->req_q_map) { 313 ql_log(ql_log_fatal, vha, 0x003b, 314 "Unable to allocate memory for request queue ptrs.\n"); 315 goto fail_req_map; 316 } 317 318 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 319 GFP_KERNEL); 320 if (!ha->rsp_q_map) { 321 ql_log(ql_log_fatal, vha, 0x003c, 322 "Unable to allocate memory for response queue ptrs.\n"); 323 goto fail_rsp_map; 324 } 325 set_bit(0, ha->rsp_qid_map); 326 set_bit(0, ha->req_qid_map); 327 return 1; 328 329 fail_rsp_map: 330 kfree(ha->req_q_map); 331 ha->req_q_map = NULL; 332 fail_req_map: 333 return -ENOMEM; 334 } 335 336 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 337 { 338 if (req && req->ring) 339 dma_free_coherent(&ha->pdev->dev, 340 (req->length + 1) * sizeof(request_t), 341 req->ring, req->dma); 342 343 kfree(req); 344 req = NULL; 345 } 346 347 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 348 { 349 if (rsp && rsp->ring) 350 dma_free_coherent(&ha->pdev->dev, 351 (rsp->length + 1) * sizeof(response_t), 352 rsp->ring, rsp->dma); 353 354 kfree(rsp); 355 rsp = NULL; 356 } 357 358 static void qla2x00_free_queues(struct qla_hw_data *ha) 359 { 360 struct req_que *req; 361 struct rsp_que *rsp; 362 int cnt; 363 364 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 365 req = ha->req_q_map[cnt]; 366 qla2x00_free_req_que(ha, req); 367 } 368 kfree(ha->req_q_map); 369 ha->req_q_map = NULL; 370 371 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 372 rsp = ha->rsp_q_map[cnt]; 373 qla2x00_free_rsp_que(ha, rsp); 374 } 375 kfree(ha->rsp_q_map); 376 ha->rsp_q_map = NULL; 377 } 378 379 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 380 { 381 uint16_t options = 0; 382 int ques, req, ret; 383 struct qla_hw_data *ha = vha->hw; 384 385 if (!(ha->fw_attributes & BIT_6)) { 386 ql_log(ql_log_warn, vha, 0x00d8, 387 "Firmware is not multi-queue capable.\n"); 388 goto fail; 389 } 390 if (ql2xmultique_tag) { 391 /* create a request queue for IO */ 392 options |= BIT_7; 393 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 394 QLA_DEFAULT_QUE_QOS); 395 if (!req) { 396 ql_log(ql_log_warn, vha, 0x00e0, 397 "Failed to create request queue.\n"); 398 goto fail; 399 } 400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 401 vha->req = ha->req_q_map[req]; 402 options |= BIT_1; 403 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 404 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 405 if (!ret) { 406 ql_log(ql_log_warn, vha, 0x00e8, 407 "Failed to create response queue.\n"); 408 goto fail2; 409 } 410 } 411 ha->flags.cpu_affinity_enabled = 1; 412 ql_dbg(ql_dbg_multiq, vha, 0xc007, 413 "CPU affinity mode enalbed, " 414 "no. of response queues:%d no. of request queues:%d.\n", 415 ha->max_rsp_queues, ha->max_req_queues); 416 ql_dbg(ql_dbg_init, vha, 0x00e9, 417 "CPU affinity mode enalbed, " 418 "no. of response queues:%d no. of request queues:%d.\n", 419 ha->max_rsp_queues, ha->max_req_queues); 420 } 421 return 0; 422 fail2: 423 qla25xx_delete_queues(vha); 424 destroy_workqueue(ha->wq); 425 ha->wq = NULL; 426 fail: 427 ha->mqenable = 0; 428 kfree(ha->req_q_map); 429 kfree(ha->rsp_q_map); 430 ha->max_req_queues = ha->max_rsp_queues = 1; 431 return 1; 432 } 433 434 static char * 435 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 436 { 437 struct qla_hw_data *ha = vha->hw; 438 static char *pci_bus_modes[] = { 439 "33", "66", "100", "133", 440 }; 441 uint16_t pci_bus; 442 443 strcpy(str, "PCI"); 444 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 445 if (pci_bus) { 446 strcat(str, "-X ("); 447 strcat(str, pci_bus_modes[pci_bus]); 448 } else { 449 pci_bus = (ha->pci_attr & BIT_8) >> 8; 450 strcat(str, " ("); 451 strcat(str, pci_bus_modes[pci_bus]); 452 } 453 strcat(str, " MHz)"); 454 455 return (str); 456 } 457 458 static char * 459 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 460 { 461 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 462 struct qla_hw_data *ha = vha->hw; 463 uint32_t pci_bus; 464 int pcie_reg; 465 466 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 467 if (pcie_reg) { 468 char lwstr[6]; 469 uint16_t pcie_lstat, lspeed, lwidth; 470 471 pcie_reg += 0x12; 472 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); 473 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); 474 lwidth = (pcie_lstat & 475 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; 476 477 strcpy(str, "PCIe ("); 478 if (lspeed == 1) 479 strcat(str, "2.5GT/s "); 480 else if (lspeed == 2) 481 strcat(str, "5.0GT/s "); 482 else 483 strcat(str, "<unknown> "); 484 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 485 strcat(str, lwstr); 486 487 return str; 488 } 489 490 strcpy(str, "PCI"); 491 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 492 if (pci_bus == 0 || pci_bus == 8) { 493 strcat(str, " ("); 494 strcat(str, pci_bus_modes[pci_bus >> 3]); 495 } else { 496 strcat(str, "-X "); 497 if (pci_bus & BIT_2) 498 strcat(str, "Mode 2"); 499 else 500 strcat(str, "Mode 1"); 501 strcat(str, " ("); 502 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 503 } 504 strcat(str, " MHz)"); 505 506 return str; 507 } 508 509 static char * 510 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 511 { 512 char un_str[10]; 513 struct qla_hw_data *ha = vha->hw; 514 515 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 516 ha->fw_minor_version, 517 ha->fw_subminor_version); 518 519 if (ha->fw_attributes & BIT_9) { 520 strcat(str, "FLX"); 521 return (str); 522 } 523 524 switch (ha->fw_attributes & 0xFF) { 525 case 0x7: 526 strcat(str, "EF"); 527 break; 528 case 0x17: 529 strcat(str, "TP"); 530 break; 531 case 0x37: 532 strcat(str, "IP"); 533 break; 534 case 0x77: 535 strcat(str, "VI"); 536 break; 537 default: 538 sprintf(un_str, "(%x)", ha->fw_attributes); 539 strcat(str, un_str); 540 break; 541 } 542 if (ha->fw_attributes & 0x100) 543 strcat(str, "X"); 544 545 return (str); 546 } 547 548 static char * 549 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 550 { 551 struct qla_hw_data *ha = vha->hw; 552 553 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 554 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 555 return str; 556 } 557 558 static inline srb_t * 559 qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport, 560 struct scsi_cmnd *cmd) 561 { 562 srb_t *sp; 563 struct qla_hw_data *ha = vha->hw; 564 565 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC); 566 if (!sp) { 567 ql_log(ql_log_warn, vha, 0x3006, 568 "Memory allocation failed for sp.\n"); 569 return sp; 570 } 571 572 atomic_set(&sp->ref_count, 1); 573 sp->fcport = fcport; 574 sp->cmd = cmd; 575 sp->flags = 0; 576 CMD_SP(cmd) = (void *)sp; 577 sp->ctx = NULL; 578 579 return sp; 580 } 581 582 static int 583 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 584 { 585 scsi_qla_host_t *vha = shost_priv(host); 586 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 587 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 588 struct qla_hw_data *ha = vha->hw; 589 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 590 srb_t *sp; 591 int rval; 592 593 if (ha->flags.eeh_busy) { 594 if (ha->flags.pci_channel_io_perm_failure) { 595 ql_dbg(ql_dbg_io, vha, 0x3001, 596 "PCI Channel IO permanent failure, exiting " 597 "cmd=%p.\n", cmd); 598 cmd->result = DID_NO_CONNECT << 16; 599 } else { 600 ql_dbg(ql_dbg_io, vha, 0x3002, 601 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 602 cmd->result = DID_REQUEUE << 16; 603 } 604 goto qc24_fail_command; 605 } 606 607 rval = fc_remote_port_chkready(rport); 608 if (rval) { 609 cmd->result = rval; 610 ql_dbg(ql_dbg_io, vha, 0x3003, 611 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 612 cmd, rval); 613 goto qc24_fail_command; 614 } 615 616 if (!vha->flags.difdix_supported && 617 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 618 ql_dbg(ql_dbg_io, vha, 0x3004, 619 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 620 cmd); 621 cmd->result = DID_NO_CONNECT << 16; 622 goto qc24_fail_command; 623 } 624 if (atomic_read(&fcport->state) != FCS_ONLINE) { 625 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 626 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 627 ql_dbg(ql_dbg_io, vha, 0x3005, 628 "Returning DNC, fcport_state=%d loop_state=%d.\n", 629 atomic_read(&fcport->state), 630 atomic_read(&base_vha->loop_state)); 631 cmd->result = DID_NO_CONNECT << 16; 632 goto qc24_fail_command; 633 } 634 goto qc24_target_busy; 635 } 636 637 sp = qla2x00_get_new_sp(base_vha, fcport, cmd); 638 if (!sp) 639 goto qc24_host_busy; 640 641 rval = ha->isp_ops->start_scsi(sp); 642 if (rval != QLA_SUCCESS) { 643 ql_dbg(ql_dbg_io, vha, 0x3013, 644 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 645 goto qc24_host_busy_free_sp; 646 } 647 648 return 0; 649 650 qc24_host_busy_free_sp: 651 qla2x00_sp_free_dma(sp); 652 mempool_free(sp, ha->srb_mempool); 653 654 qc24_host_busy: 655 return SCSI_MLQUEUE_HOST_BUSY; 656 657 qc24_target_busy: 658 return SCSI_MLQUEUE_TARGET_BUSY; 659 660 qc24_fail_command: 661 cmd->scsi_done(cmd); 662 663 return 0; 664 } 665 666 /* 667 * qla2x00_eh_wait_on_command 668 * Waits for the command to be returned by the Firmware for some 669 * max time. 670 * 671 * Input: 672 * cmd = Scsi Command to wait on. 673 * 674 * Return: 675 * Not Found : 0 676 * Found : 1 677 */ 678 static int 679 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 680 { 681 #define ABORT_POLLING_PERIOD 1000 682 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 683 unsigned long wait_iter = ABORT_WAIT_ITER; 684 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 685 struct qla_hw_data *ha = vha->hw; 686 int ret = QLA_SUCCESS; 687 688 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 689 ql_dbg(ql_dbg_taskm, vha, 0x8005, 690 "Return:eh_wait.\n"); 691 return ret; 692 } 693 694 while (CMD_SP(cmd) && wait_iter--) { 695 msleep(ABORT_POLLING_PERIOD); 696 } 697 if (CMD_SP(cmd)) 698 ret = QLA_FUNCTION_FAILED; 699 700 return ret; 701 } 702 703 /* 704 * qla2x00_wait_for_hba_online 705 * Wait till the HBA is online after going through 706 * <= MAX_RETRIES_OF_ISP_ABORT or 707 * finally HBA is disabled ie marked offline 708 * 709 * Input: 710 * ha - pointer to host adapter structure 711 * 712 * Note: 713 * Does context switching-Release SPIN_LOCK 714 * (if any) before calling this routine. 715 * 716 * Return: 717 * Success (Adapter is online) : 0 718 * Failed (Adapter is offline/disabled) : 1 719 */ 720 int 721 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 722 { 723 int return_status; 724 unsigned long wait_online; 725 struct qla_hw_data *ha = vha->hw; 726 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 727 728 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 729 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 730 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 731 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 732 ha->dpc_active) && time_before(jiffies, wait_online)) { 733 734 msleep(1000); 735 } 736 if (base_vha->flags.online) 737 return_status = QLA_SUCCESS; 738 else 739 return_status = QLA_FUNCTION_FAILED; 740 741 return (return_status); 742 } 743 744 /* 745 * qla2x00_wait_for_reset_ready 746 * Wait till the HBA is online after going through 747 * <= MAX_RETRIES_OF_ISP_ABORT or 748 * finally HBA is disabled ie marked offline or flash 749 * operations are in progress. 750 * 751 * Input: 752 * ha - pointer to host adapter structure 753 * 754 * Note: 755 * Does context switching-Release SPIN_LOCK 756 * (if any) before calling this routine. 757 * 758 * Return: 759 * Success (Adapter is online/no flash ops) : 0 760 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 761 */ 762 static int 763 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 764 { 765 int return_status; 766 unsigned long wait_online; 767 struct qla_hw_data *ha = vha->hw; 768 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 769 770 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 771 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 772 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 773 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 774 ha->optrom_state != QLA_SWAITING || 775 ha->dpc_active) && time_before(jiffies, wait_online)) 776 msleep(1000); 777 778 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 779 return_status = QLA_SUCCESS; 780 else 781 return_status = QLA_FUNCTION_FAILED; 782 783 ql_dbg(ql_dbg_taskm, vha, 0x8019, 784 "%s return status=%d.\n", __func__, return_status); 785 786 return return_status; 787 } 788 789 int 790 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 791 { 792 int return_status; 793 unsigned long wait_reset; 794 struct qla_hw_data *ha = vha->hw; 795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 796 797 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 798 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 799 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 800 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 801 ha->dpc_active) && time_before(jiffies, wait_reset)) { 802 803 msleep(1000); 804 805 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 806 ha->flags.chip_reset_done) 807 break; 808 } 809 if (ha->flags.chip_reset_done) 810 return_status = QLA_SUCCESS; 811 else 812 return_status = QLA_FUNCTION_FAILED; 813 814 return return_status; 815 } 816 817 /* 818 * qla2x00_wait_for_loop_ready 819 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop 820 * to be in LOOP_READY state. 821 * Input: 822 * ha - pointer to host adapter structure 823 * 824 * Note: 825 * Does context switching-Release SPIN_LOCK 826 * (if any) before calling this routine. 827 * 828 * 829 * Return: 830 * Success (LOOP_READY) : 0 831 * Failed (LOOP_NOT_READY) : 1 832 */ 833 static inline int 834 qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha) 835 { 836 int return_status = QLA_SUCCESS; 837 unsigned long loop_timeout ; 838 struct qla_hw_data *ha = vha->hw; 839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 840 841 /* wait for 5 min at the max for loop to be ready */ 842 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ); 843 844 while ((!atomic_read(&base_vha->loop_down_timer) && 845 atomic_read(&base_vha->loop_state) == LOOP_DOWN) || 846 atomic_read(&base_vha->loop_state) != LOOP_READY) { 847 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 848 return_status = QLA_FUNCTION_FAILED; 849 break; 850 } 851 msleep(1000); 852 if (time_after_eq(jiffies, loop_timeout)) { 853 return_status = QLA_FUNCTION_FAILED; 854 break; 855 } 856 } 857 return (return_status); 858 } 859 860 static void 861 sp_get(struct srb *sp) 862 { 863 atomic_inc(&sp->ref_count); 864 } 865 866 /************************************************************************** 867 * qla2xxx_eh_abort 868 * 869 * Description: 870 * The abort function will abort the specified command. 871 * 872 * Input: 873 * cmd = Linux SCSI command packet to be aborted. 874 * 875 * Returns: 876 * Either SUCCESS or FAILED. 877 * 878 * Note: 879 * Only return FAILED if command not returned by firmware. 880 **************************************************************************/ 881 static int 882 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 883 { 884 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 885 srb_t *sp; 886 int ret; 887 unsigned int id, lun; 888 unsigned long flags; 889 int wait = 0; 890 struct qla_hw_data *ha = vha->hw; 891 892 ql_dbg(ql_dbg_taskm, vha, 0x8000, 893 "Entered %s for cmd=%p.\n", __func__, cmd); 894 if (!CMD_SP(cmd)) 895 return SUCCESS; 896 897 ret = fc_block_scsi_eh(cmd); 898 ql_dbg(ql_dbg_taskm, vha, 0x8001, 899 "Return value of fc_block_scsi_eh=%d.\n", ret); 900 if (ret != 0) 901 return ret; 902 ret = SUCCESS; 903 904 id = cmd->device->id; 905 lun = cmd->device->lun; 906 907 spin_lock_irqsave(&ha->hardware_lock, flags); 908 sp = (srb_t *) CMD_SP(cmd); 909 if (!sp) { 910 spin_unlock_irqrestore(&ha->hardware_lock, flags); 911 return SUCCESS; 912 } 913 914 ql_dbg(ql_dbg_taskm, vha, 0x8002, 915 "Aborting sp=%p cmd=%p from RISC ", sp, cmd); 916 917 /* Get a reference to the sp and drop the lock.*/ 918 sp_get(sp); 919 920 spin_unlock_irqrestore(&ha->hardware_lock, flags); 921 if (ha->isp_ops->abort_command(sp)) { 922 ql_dbg(ql_dbg_taskm, vha, 0x8003, 923 "Abort command mbx failed for cmd=%p.\n", cmd); 924 } else { 925 ql_dbg(ql_dbg_taskm, vha, 0x8004, 926 "Abort command mbx success.\n"); 927 wait = 1; 928 } 929 930 spin_lock_irqsave(&ha->hardware_lock, flags); 931 qla2x00_sp_compl(ha, sp); 932 spin_unlock_irqrestore(&ha->hardware_lock, flags); 933 934 /* Did the command return during mailbox execution? */ 935 if (ret == FAILED && !CMD_SP(cmd)) 936 ret = SUCCESS; 937 938 /* Wait for the command to be returned. */ 939 if (wait) { 940 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 941 ql_log(ql_log_warn, vha, 0x8006, 942 "Abort handler timed out for cmd=%p.\n", cmd); 943 ret = FAILED; 944 } 945 } 946 947 ql_log(ql_log_info, vha, 0x801c, 948 "Abort command issued -- %d %x.\n", wait, ret); 949 950 return ret; 951 } 952 953 int 954 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 955 unsigned int l, enum nexus_wait_type type) 956 { 957 int cnt, match, status; 958 unsigned long flags; 959 struct qla_hw_data *ha = vha->hw; 960 struct req_que *req; 961 srb_t *sp; 962 963 status = QLA_SUCCESS; 964 965 spin_lock_irqsave(&ha->hardware_lock, flags); 966 req = vha->req; 967 for (cnt = 1; status == QLA_SUCCESS && 968 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 969 sp = req->outstanding_cmds[cnt]; 970 if (!sp) 971 continue; 972 if ((sp->ctx) && !IS_PROT_IO(sp)) 973 continue; 974 if (vha->vp_idx != sp->fcport->vha->vp_idx) 975 continue; 976 match = 0; 977 switch (type) { 978 case WAIT_HOST: 979 match = 1; 980 break; 981 case WAIT_TARGET: 982 match = sp->cmd->device->id == t; 983 break; 984 case WAIT_LUN: 985 match = (sp->cmd->device->id == t && 986 sp->cmd->device->lun == l); 987 break; 988 } 989 if (!match) 990 continue; 991 992 spin_unlock_irqrestore(&ha->hardware_lock, flags); 993 status = qla2x00_eh_wait_on_command(sp->cmd); 994 spin_lock_irqsave(&ha->hardware_lock, flags); 995 } 996 spin_unlock_irqrestore(&ha->hardware_lock, flags); 997 998 return status; 999 } 1000 1001 static char *reset_errors[] = { 1002 "HBA not online", 1003 "HBA not ready", 1004 "Task management failed", 1005 "Waiting for command completions", 1006 }; 1007 1008 static int 1009 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1010 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 1011 { 1012 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1013 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1014 int err; 1015 1016 if (!fcport) { 1017 ql_log(ql_log_warn, vha, 0x8007, 1018 "fcport is NULL.\n"); 1019 return FAILED; 1020 } 1021 1022 err = fc_block_scsi_eh(cmd); 1023 ql_dbg(ql_dbg_taskm, vha, 0x8008, 1024 "fc_block_scsi_eh ret=%d.\n", err); 1025 if (err != 0) 1026 return err; 1027 1028 ql_log(ql_log_info, vha, 0x8009, 1029 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name, 1030 cmd->device->id, cmd->device->lun, cmd); 1031 1032 err = 0; 1033 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1034 ql_log(ql_log_warn, vha, 0x800a, 1035 "Wait for hba online failed for cmd=%p.\n", cmd); 1036 goto eh_reset_failed; 1037 } 1038 err = 1; 1039 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) { 1040 ql_log(ql_log_warn, vha, 0x800b, 1041 "Wait for loop ready failed for cmd=%p.\n", cmd); 1042 goto eh_reset_failed; 1043 } 1044 err = 2; 1045 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1046 != QLA_SUCCESS) { 1047 ql_log(ql_log_warn, vha, 0x800c, 1048 "do_reset failed for cmd=%p.\n", cmd); 1049 goto eh_reset_failed; 1050 } 1051 err = 3; 1052 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1053 cmd->device->lun, type) != QLA_SUCCESS) { 1054 ql_log(ql_log_warn, vha, 0x800d, 1055 "wait for peding cmds failed for cmd=%p.\n", cmd); 1056 goto eh_reset_failed; 1057 } 1058 1059 ql_log(ql_log_info, vha, 0x800e, 1060 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name, 1061 cmd->device->id, cmd->device->lun, cmd); 1062 1063 return SUCCESS; 1064 1065 eh_reset_failed: 1066 ql_log(ql_log_info, vha, 0x800f, 1067 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name, 1068 reset_errors[err], cmd->device->id, cmd->device->lun); 1069 return FAILED; 1070 } 1071 1072 static int 1073 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1074 { 1075 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1076 struct qla_hw_data *ha = vha->hw; 1077 1078 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1079 ha->isp_ops->lun_reset); 1080 } 1081 1082 static int 1083 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1084 { 1085 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1086 struct qla_hw_data *ha = vha->hw; 1087 1088 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1089 ha->isp_ops->target_reset); 1090 } 1091 1092 /************************************************************************** 1093 * qla2xxx_eh_bus_reset 1094 * 1095 * Description: 1096 * The bus reset function will reset the bus and abort any executing 1097 * commands. 1098 * 1099 * Input: 1100 * cmd = Linux SCSI command packet of the command that cause the 1101 * bus reset. 1102 * 1103 * Returns: 1104 * SUCCESS/FAILURE (defined as macro in scsi.h). 1105 * 1106 **************************************************************************/ 1107 static int 1108 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1109 { 1110 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1111 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1112 int ret = FAILED; 1113 unsigned int id, lun; 1114 1115 id = cmd->device->id; 1116 lun = cmd->device->lun; 1117 1118 if (!fcport) { 1119 ql_log(ql_log_warn, vha, 0x8010, 1120 "fcport is NULL.\n"); 1121 return ret; 1122 } 1123 1124 ret = fc_block_scsi_eh(cmd); 1125 ql_dbg(ql_dbg_taskm, vha, 0x8011, 1126 "fc_block_scsi_eh ret=%d.\n", ret); 1127 if (ret != 0) 1128 return ret; 1129 ret = FAILED; 1130 1131 ql_log(ql_log_info, vha, 0x8012, 1132 "BUS RESET ISSUED for id %d lun %d.\n", id, lun); 1133 1134 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1135 ql_log(ql_log_fatal, vha, 0x8013, 1136 "Wait for hba online failed board disabled.\n"); 1137 goto eh_bus_reset_done; 1138 } 1139 1140 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) { 1141 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1142 ret = SUCCESS; 1143 } 1144 if (ret == FAILED) 1145 goto eh_bus_reset_done; 1146 1147 /* Flush outstanding commands. */ 1148 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1149 QLA_SUCCESS) { 1150 ql_log(ql_log_warn, vha, 0x8014, 1151 "Wait for pending commands failed.\n"); 1152 ret = FAILED; 1153 } 1154 1155 eh_bus_reset_done: 1156 ql_log(ql_log_warn, vha, 0x802b, 1157 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED"); 1158 1159 return ret; 1160 } 1161 1162 /************************************************************************** 1163 * qla2xxx_eh_host_reset 1164 * 1165 * Description: 1166 * The reset function will reset the Adapter. 1167 * 1168 * Input: 1169 * cmd = Linux SCSI command packet of the command that cause the 1170 * adapter reset. 1171 * 1172 * Returns: 1173 * Either SUCCESS or FAILED. 1174 * 1175 * Note: 1176 **************************************************************************/ 1177 static int 1178 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1179 { 1180 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1181 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1182 struct qla_hw_data *ha = vha->hw; 1183 int ret = FAILED; 1184 unsigned int id, lun; 1185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1186 1187 id = cmd->device->id; 1188 lun = cmd->device->lun; 1189 1190 if (!fcport) { 1191 ql_log(ql_log_warn, vha, 0x8016, 1192 "fcport is NULL.\n"); 1193 return ret; 1194 } 1195 1196 ret = fc_block_scsi_eh(cmd); 1197 ql_dbg(ql_dbg_taskm, vha, 0x8017, 1198 "fc_block_scsi_eh ret=%d.\n", ret); 1199 if (ret != 0) 1200 return ret; 1201 ret = FAILED; 1202 1203 ql_log(ql_log_info, vha, 0x8018, 1204 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun); 1205 1206 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1207 goto eh_host_reset_lock; 1208 1209 /* 1210 * Fixme-may be dpc thread is active and processing 1211 * loop_resync,so wait a while for it to 1212 * be completed and then issue big hammer.Otherwise 1213 * it may cause I/O failure as big hammer marks the 1214 * devices as lost kicking of the port_down_timer 1215 * while dpc is stuck for the mailbox to complete. 1216 */ 1217 qla2x00_wait_for_loop_ready(vha); 1218 if (vha != base_vha) { 1219 if (qla2x00_vp_abort_isp(vha)) 1220 goto eh_host_reset_lock; 1221 } else { 1222 if (IS_QLA82XX(vha->hw)) { 1223 if (!qla82xx_fcoe_ctx_reset(vha)) { 1224 /* Ctx reset success */ 1225 ret = SUCCESS; 1226 goto eh_host_reset_lock; 1227 } 1228 /* fall thru if ctx reset failed */ 1229 } 1230 if (ha->wq) 1231 flush_workqueue(ha->wq); 1232 1233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1234 if (ha->isp_ops->abort_isp(base_vha)) { 1235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1236 /* failed. schedule dpc to try */ 1237 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1238 1239 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1240 ql_log(ql_log_warn, vha, 0x802a, 1241 "wait for hba online failed.\n"); 1242 goto eh_host_reset_lock; 1243 } 1244 } 1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1246 } 1247 1248 /* Waiting for command to be returned to OS.*/ 1249 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1250 QLA_SUCCESS) 1251 ret = SUCCESS; 1252 1253 eh_host_reset_lock: 1254 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__, 1255 (ret == FAILED) ? "failed" : "succeeded"); 1256 1257 return ret; 1258 } 1259 1260 /* 1261 * qla2x00_loop_reset 1262 * Issue loop reset. 1263 * 1264 * Input: 1265 * ha = adapter block pointer. 1266 * 1267 * Returns: 1268 * 0 = success 1269 */ 1270 int 1271 qla2x00_loop_reset(scsi_qla_host_t *vha) 1272 { 1273 int ret; 1274 struct fc_port *fcport; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1278 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1279 if (fcport->port_type != FCT_TARGET) 1280 continue; 1281 1282 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1283 if (ret != QLA_SUCCESS) { 1284 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1285 "Bus Reset failed: Target Reset=%d " 1286 "d_id=%x.\n", ret, fcport->d_id.b24); 1287 } 1288 } 1289 } 1290 1291 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) { 1292 ret = qla2x00_full_login_lip(vha); 1293 if (ret != QLA_SUCCESS) { 1294 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1295 "full_login_lip=%d.\n", ret); 1296 } 1297 atomic_set(&vha->loop_state, LOOP_DOWN); 1298 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1299 qla2x00_mark_all_devices_lost(vha, 0); 1300 qla2x00_wait_for_loop_ready(vha); 1301 } 1302 1303 if (ha->flags.enable_lip_reset) { 1304 ret = qla2x00_lip_reset(vha); 1305 if (ret != QLA_SUCCESS) { 1306 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1307 "lip_reset failed (%d).\n", ret); 1308 } else 1309 qla2x00_wait_for_loop_ready(vha); 1310 } 1311 1312 /* Issue marker command only when we are going to start the I/O */ 1313 vha->marker_needed = 1; 1314 1315 return QLA_SUCCESS; 1316 } 1317 1318 void 1319 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1320 { 1321 int que, cnt; 1322 unsigned long flags; 1323 srb_t *sp; 1324 struct srb_ctx *ctx; 1325 struct qla_hw_data *ha = vha->hw; 1326 struct req_que *req; 1327 1328 spin_lock_irqsave(&ha->hardware_lock, flags); 1329 for (que = 0; que < ha->max_req_queues; que++) { 1330 req = ha->req_q_map[que]; 1331 if (!req) 1332 continue; 1333 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 1334 sp = req->outstanding_cmds[cnt]; 1335 if (sp) { 1336 req->outstanding_cmds[cnt] = NULL; 1337 if (!sp->ctx || 1338 (sp->flags & SRB_FCP_CMND_DMA_VALID) || 1339 IS_PROT_IO(sp)) { 1340 sp->cmd->result = res; 1341 qla2x00_sp_compl(ha, sp); 1342 } else { 1343 ctx = sp->ctx; 1344 if (ctx->type == SRB_ELS_CMD_RPT || 1345 ctx->type == SRB_ELS_CMD_HST || 1346 ctx->type == SRB_CT_CMD) { 1347 struct fc_bsg_job *bsg_job = 1348 ctx->u.bsg_job; 1349 if (bsg_job->request->msgcode 1350 == FC_BSG_HST_CT) 1351 kfree(sp->fcport); 1352 bsg_job->req->errors = 0; 1353 bsg_job->reply->result = res; 1354 bsg_job->job_done(bsg_job); 1355 kfree(sp->ctx); 1356 mempool_free(sp, 1357 ha->srb_mempool); 1358 } else { 1359 ctx->u.iocb_cmd->free(sp); 1360 } 1361 } 1362 } 1363 } 1364 } 1365 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1366 } 1367 1368 static int 1369 qla2xxx_slave_alloc(struct scsi_device *sdev) 1370 { 1371 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1372 1373 if (!rport || fc_remote_port_chkready(rport)) 1374 return -ENXIO; 1375 1376 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1377 1378 return 0; 1379 } 1380 1381 static int 1382 qla2xxx_slave_configure(struct scsi_device *sdev) 1383 { 1384 scsi_qla_host_t *vha = shost_priv(sdev->host); 1385 struct req_que *req = vha->req; 1386 1387 if (sdev->tagged_supported) 1388 scsi_activate_tcq(sdev, req->max_q_depth); 1389 else 1390 scsi_deactivate_tcq(sdev, req->max_q_depth); 1391 return 0; 1392 } 1393 1394 static void 1395 qla2xxx_slave_destroy(struct scsi_device *sdev) 1396 { 1397 sdev->hostdata = NULL; 1398 } 1399 1400 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1401 { 1402 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1403 1404 if (!scsi_track_queue_full(sdev, qdepth)) 1405 return; 1406 1407 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1408 "Queue depth adjusted-down " 1409 "to %d for scsi(%ld:%d:%d:%d).\n", 1410 sdev->queue_depth, fcport->vha->host_no, 1411 sdev->channel, sdev->id, sdev->lun); 1412 } 1413 1414 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1415 { 1416 fc_port_t *fcport = sdev->hostdata; 1417 struct scsi_qla_host *vha = fcport->vha; 1418 struct req_que *req = NULL; 1419 1420 req = vha->req; 1421 if (!req) 1422 return; 1423 1424 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1425 return; 1426 1427 if (sdev->ordered_tags) 1428 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1429 else 1430 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1431 1432 ql_dbg(ql_dbg_io, vha, 0x302a, 1433 "Queue depth adjusted-up to %d for " 1434 "scsi(%ld:%d:%d:%d).\n", 1435 sdev->queue_depth, fcport->vha->host_no, 1436 sdev->channel, sdev->id, sdev->lun); 1437 } 1438 1439 static int 1440 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1441 { 1442 switch (reason) { 1443 case SCSI_QDEPTH_DEFAULT: 1444 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1445 break; 1446 case SCSI_QDEPTH_QFULL: 1447 qla2x00_handle_queue_full(sdev, qdepth); 1448 break; 1449 case SCSI_QDEPTH_RAMP_UP: 1450 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1451 break; 1452 default: 1453 return -EOPNOTSUPP; 1454 } 1455 1456 return sdev->queue_depth; 1457 } 1458 1459 static int 1460 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1461 { 1462 if (sdev->tagged_supported) { 1463 scsi_set_tag_type(sdev, tag_type); 1464 if (tag_type) 1465 scsi_activate_tcq(sdev, sdev->queue_depth); 1466 else 1467 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1468 } else 1469 tag_type = 0; 1470 1471 return tag_type; 1472 } 1473 1474 /** 1475 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1476 * @ha: HA context 1477 * 1478 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1479 * supported addressing method. 1480 */ 1481 static void 1482 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1483 { 1484 /* Assume a 32bit DMA mask. */ 1485 ha->flags.enable_64bit_addressing = 0; 1486 1487 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1488 /* Any upper-dword bits set? */ 1489 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1490 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1491 /* Ok, a 64bit DMA mask is applicable. */ 1492 ha->flags.enable_64bit_addressing = 1; 1493 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1494 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1495 return; 1496 } 1497 } 1498 1499 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1500 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1501 } 1502 1503 static void 1504 qla2x00_enable_intrs(struct qla_hw_data *ha) 1505 { 1506 unsigned long flags = 0; 1507 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1508 1509 spin_lock_irqsave(&ha->hardware_lock, flags); 1510 ha->interrupts_on = 1; 1511 /* enable risc and host interrupts */ 1512 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1513 RD_REG_WORD(®->ictrl); 1514 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1515 1516 } 1517 1518 static void 1519 qla2x00_disable_intrs(struct qla_hw_data *ha) 1520 { 1521 unsigned long flags = 0; 1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1523 1524 spin_lock_irqsave(&ha->hardware_lock, flags); 1525 ha->interrupts_on = 0; 1526 /* disable risc and host interrupts */ 1527 WRT_REG_WORD(®->ictrl, 0); 1528 RD_REG_WORD(®->ictrl); 1529 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1530 } 1531 1532 static void 1533 qla24xx_enable_intrs(struct qla_hw_data *ha) 1534 { 1535 unsigned long flags = 0; 1536 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1537 1538 spin_lock_irqsave(&ha->hardware_lock, flags); 1539 ha->interrupts_on = 1; 1540 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1541 RD_REG_DWORD(®->ictrl); 1542 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1543 } 1544 1545 static void 1546 qla24xx_disable_intrs(struct qla_hw_data *ha) 1547 { 1548 unsigned long flags = 0; 1549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1550 1551 if (IS_NOPOLLING_TYPE(ha)) 1552 return; 1553 spin_lock_irqsave(&ha->hardware_lock, flags); 1554 ha->interrupts_on = 0; 1555 WRT_REG_DWORD(®->ictrl, 0); 1556 RD_REG_DWORD(®->ictrl); 1557 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1558 } 1559 1560 static struct isp_operations qla2100_isp_ops = { 1561 .pci_config = qla2100_pci_config, 1562 .reset_chip = qla2x00_reset_chip, 1563 .chip_diag = qla2x00_chip_diag, 1564 .config_rings = qla2x00_config_rings, 1565 .reset_adapter = qla2x00_reset_adapter, 1566 .nvram_config = qla2x00_nvram_config, 1567 .update_fw_options = qla2x00_update_fw_options, 1568 .load_risc = qla2x00_load_risc, 1569 .pci_info_str = qla2x00_pci_info_str, 1570 .fw_version_str = qla2x00_fw_version_str, 1571 .intr_handler = qla2100_intr_handler, 1572 .enable_intrs = qla2x00_enable_intrs, 1573 .disable_intrs = qla2x00_disable_intrs, 1574 .abort_command = qla2x00_abort_command, 1575 .target_reset = qla2x00_abort_target, 1576 .lun_reset = qla2x00_lun_reset, 1577 .fabric_login = qla2x00_login_fabric, 1578 .fabric_logout = qla2x00_fabric_logout, 1579 .calc_req_entries = qla2x00_calc_iocbs_32, 1580 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1581 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1582 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1583 .read_nvram = qla2x00_read_nvram_data, 1584 .write_nvram = qla2x00_write_nvram_data, 1585 .fw_dump = qla2100_fw_dump, 1586 .beacon_on = NULL, 1587 .beacon_off = NULL, 1588 .beacon_blink = NULL, 1589 .read_optrom = qla2x00_read_optrom_data, 1590 .write_optrom = qla2x00_write_optrom_data, 1591 .get_flash_version = qla2x00_get_flash_version, 1592 .start_scsi = qla2x00_start_scsi, 1593 .abort_isp = qla2x00_abort_isp, 1594 }; 1595 1596 static struct isp_operations qla2300_isp_ops = { 1597 .pci_config = qla2300_pci_config, 1598 .reset_chip = qla2x00_reset_chip, 1599 .chip_diag = qla2x00_chip_diag, 1600 .config_rings = qla2x00_config_rings, 1601 .reset_adapter = qla2x00_reset_adapter, 1602 .nvram_config = qla2x00_nvram_config, 1603 .update_fw_options = qla2x00_update_fw_options, 1604 .load_risc = qla2x00_load_risc, 1605 .pci_info_str = qla2x00_pci_info_str, 1606 .fw_version_str = qla2x00_fw_version_str, 1607 .intr_handler = qla2300_intr_handler, 1608 .enable_intrs = qla2x00_enable_intrs, 1609 .disable_intrs = qla2x00_disable_intrs, 1610 .abort_command = qla2x00_abort_command, 1611 .target_reset = qla2x00_abort_target, 1612 .lun_reset = qla2x00_lun_reset, 1613 .fabric_login = qla2x00_login_fabric, 1614 .fabric_logout = qla2x00_fabric_logout, 1615 .calc_req_entries = qla2x00_calc_iocbs_32, 1616 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1617 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1618 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1619 .read_nvram = qla2x00_read_nvram_data, 1620 .write_nvram = qla2x00_write_nvram_data, 1621 .fw_dump = qla2300_fw_dump, 1622 .beacon_on = qla2x00_beacon_on, 1623 .beacon_off = qla2x00_beacon_off, 1624 .beacon_blink = qla2x00_beacon_blink, 1625 .read_optrom = qla2x00_read_optrom_data, 1626 .write_optrom = qla2x00_write_optrom_data, 1627 .get_flash_version = qla2x00_get_flash_version, 1628 .start_scsi = qla2x00_start_scsi, 1629 .abort_isp = qla2x00_abort_isp, 1630 }; 1631 1632 static struct isp_operations qla24xx_isp_ops = { 1633 .pci_config = qla24xx_pci_config, 1634 .reset_chip = qla24xx_reset_chip, 1635 .chip_diag = qla24xx_chip_diag, 1636 .config_rings = qla24xx_config_rings, 1637 .reset_adapter = qla24xx_reset_adapter, 1638 .nvram_config = qla24xx_nvram_config, 1639 .update_fw_options = qla24xx_update_fw_options, 1640 .load_risc = qla24xx_load_risc, 1641 .pci_info_str = qla24xx_pci_info_str, 1642 .fw_version_str = qla24xx_fw_version_str, 1643 .intr_handler = qla24xx_intr_handler, 1644 .enable_intrs = qla24xx_enable_intrs, 1645 .disable_intrs = qla24xx_disable_intrs, 1646 .abort_command = qla24xx_abort_command, 1647 .target_reset = qla24xx_abort_target, 1648 .lun_reset = qla24xx_lun_reset, 1649 .fabric_login = qla24xx_login_fabric, 1650 .fabric_logout = qla24xx_fabric_logout, 1651 .calc_req_entries = NULL, 1652 .build_iocbs = NULL, 1653 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1654 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1655 .read_nvram = qla24xx_read_nvram_data, 1656 .write_nvram = qla24xx_write_nvram_data, 1657 .fw_dump = qla24xx_fw_dump, 1658 .beacon_on = qla24xx_beacon_on, 1659 .beacon_off = qla24xx_beacon_off, 1660 .beacon_blink = qla24xx_beacon_blink, 1661 .read_optrom = qla24xx_read_optrom_data, 1662 .write_optrom = qla24xx_write_optrom_data, 1663 .get_flash_version = qla24xx_get_flash_version, 1664 .start_scsi = qla24xx_start_scsi, 1665 .abort_isp = qla2x00_abort_isp, 1666 }; 1667 1668 static struct isp_operations qla25xx_isp_ops = { 1669 .pci_config = qla25xx_pci_config, 1670 .reset_chip = qla24xx_reset_chip, 1671 .chip_diag = qla24xx_chip_diag, 1672 .config_rings = qla24xx_config_rings, 1673 .reset_adapter = qla24xx_reset_adapter, 1674 .nvram_config = qla24xx_nvram_config, 1675 .update_fw_options = qla24xx_update_fw_options, 1676 .load_risc = qla24xx_load_risc, 1677 .pci_info_str = qla24xx_pci_info_str, 1678 .fw_version_str = qla24xx_fw_version_str, 1679 .intr_handler = qla24xx_intr_handler, 1680 .enable_intrs = qla24xx_enable_intrs, 1681 .disable_intrs = qla24xx_disable_intrs, 1682 .abort_command = qla24xx_abort_command, 1683 .target_reset = qla24xx_abort_target, 1684 .lun_reset = qla24xx_lun_reset, 1685 .fabric_login = qla24xx_login_fabric, 1686 .fabric_logout = qla24xx_fabric_logout, 1687 .calc_req_entries = NULL, 1688 .build_iocbs = NULL, 1689 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1690 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1691 .read_nvram = qla25xx_read_nvram_data, 1692 .write_nvram = qla25xx_write_nvram_data, 1693 .fw_dump = qla25xx_fw_dump, 1694 .beacon_on = qla24xx_beacon_on, 1695 .beacon_off = qla24xx_beacon_off, 1696 .beacon_blink = qla24xx_beacon_blink, 1697 .read_optrom = qla25xx_read_optrom_data, 1698 .write_optrom = qla24xx_write_optrom_data, 1699 .get_flash_version = qla24xx_get_flash_version, 1700 .start_scsi = qla24xx_dif_start_scsi, 1701 .abort_isp = qla2x00_abort_isp, 1702 }; 1703 1704 static struct isp_operations qla81xx_isp_ops = { 1705 .pci_config = qla25xx_pci_config, 1706 .reset_chip = qla24xx_reset_chip, 1707 .chip_diag = qla24xx_chip_diag, 1708 .config_rings = qla24xx_config_rings, 1709 .reset_adapter = qla24xx_reset_adapter, 1710 .nvram_config = qla81xx_nvram_config, 1711 .update_fw_options = qla81xx_update_fw_options, 1712 .load_risc = qla81xx_load_risc, 1713 .pci_info_str = qla24xx_pci_info_str, 1714 .fw_version_str = qla24xx_fw_version_str, 1715 .intr_handler = qla24xx_intr_handler, 1716 .enable_intrs = qla24xx_enable_intrs, 1717 .disable_intrs = qla24xx_disable_intrs, 1718 .abort_command = qla24xx_abort_command, 1719 .target_reset = qla24xx_abort_target, 1720 .lun_reset = qla24xx_lun_reset, 1721 .fabric_login = qla24xx_login_fabric, 1722 .fabric_logout = qla24xx_fabric_logout, 1723 .calc_req_entries = NULL, 1724 .build_iocbs = NULL, 1725 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1726 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1727 .read_nvram = NULL, 1728 .write_nvram = NULL, 1729 .fw_dump = qla81xx_fw_dump, 1730 .beacon_on = qla24xx_beacon_on, 1731 .beacon_off = qla24xx_beacon_off, 1732 .beacon_blink = qla24xx_beacon_blink, 1733 .read_optrom = qla25xx_read_optrom_data, 1734 .write_optrom = qla24xx_write_optrom_data, 1735 .get_flash_version = qla24xx_get_flash_version, 1736 .start_scsi = qla24xx_dif_start_scsi, 1737 .abort_isp = qla2x00_abort_isp, 1738 }; 1739 1740 static struct isp_operations qla82xx_isp_ops = { 1741 .pci_config = qla82xx_pci_config, 1742 .reset_chip = qla82xx_reset_chip, 1743 .chip_diag = qla24xx_chip_diag, 1744 .config_rings = qla82xx_config_rings, 1745 .reset_adapter = qla24xx_reset_adapter, 1746 .nvram_config = qla81xx_nvram_config, 1747 .update_fw_options = qla24xx_update_fw_options, 1748 .load_risc = qla82xx_load_risc, 1749 .pci_info_str = qla82xx_pci_info_str, 1750 .fw_version_str = qla24xx_fw_version_str, 1751 .intr_handler = qla82xx_intr_handler, 1752 .enable_intrs = qla82xx_enable_intrs, 1753 .disable_intrs = qla82xx_disable_intrs, 1754 .abort_command = qla24xx_abort_command, 1755 .target_reset = qla24xx_abort_target, 1756 .lun_reset = qla24xx_lun_reset, 1757 .fabric_login = qla24xx_login_fabric, 1758 .fabric_logout = qla24xx_fabric_logout, 1759 .calc_req_entries = NULL, 1760 .build_iocbs = NULL, 1761 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1762 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1763 .read_nvram = qla24xx_read_nvram_data, 1764 .write_nvram = qla24xx_write_nvram_data, 1765 .fw_dump = qla24xx_fw_dump, 1766 .beacon_on = qla82xx_beacon_on, 1767 .beacon_off = qla82xx_beacon_off, 1768 .beacon_blink = NULL, 1769 .read_optrom = qla82xx_read_optrom_data, 1770 .write_optrom = qla82xx_write_optrom_data, 1771 .get_flash_version = qla24xx_get_flash_version, 1772 .start_scsi = qla82xx_start_scsi, 1773 .abort_isp = qla82xx_abort_isp, 1774 }; 1775 1776 static inline void 1777 qla2x00_set_isp_flags(struct qla_hw_data *ha) 1778 { 1779 ha->device_type = DT_EXTENDED_IDS; 1780 switch (ha->pdev->device) { 1781 case PCI_DEVICE_ID_QLOGIC_ISP2100: 1782 ha->device_type |= DT_ISP2100; 1783 ha->device_type &= ~DT_EXTENDED_IDS; 1784 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1785 break; 1786 case PCI_DEVICE_ID_QLOGIC_ISP2200: 1787 ha->device_type |= DT_ISP2200; 1788 ha->device_type &= ~DT_EXTENDED_IDS; 1789 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1790 break; 1791 case PCI_DEVICE_ID_QLOGIC_ISP2300: 1792 ha->device_type |= DT_ISP2300; 1793 ha->device_type |= DT_ZIO_SUPPORTED; 1794 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1795 break; 1796 case PCI_DEVICE_ID_QLOGIC_ISP2312: 1797 ha->device_type |= DT_ISP2312; 1798 ha->device_type |= DT_ZIO_SUPPORTED; 1799 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1800 break; 1801 case PCI_DEVICE_ID_QLOGIC_ISP2322: 1802 ha->device_type |= DT_ISP2322; 1803 ha->device_type |= DT_ZIO_SUPPORTED; 1804 if (ha->pdev->subsystem_vendor == 0x1028 && 1805 ha->pdev->subsystem_device == 0x0170) 1806 ha->device_type |= DT_OEM_001; 1807 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1808 break; 1809 case PCI_DEVICE_ID_QLOGIC_ISP6312: 1810 ha->device_type |= DT_ISP6312; 1811 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1812 break; 1813 case PCI_DEVICE_ID_QLOGIC_ISP6322: 1814 ha->device_type |= DT_ISP6322; 1815 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1816 break; 1817 case PCI_DEVICE_ID_QLOGIC_ISP2422: 1818 ha->device_type |= DT_ISP2422; 1819 ha->device_type |= DT_ZIO_SUPPORTED; 1820 ha->device_type |= DT_FWI2; 1821 ha->device_type |= DT_IIDMA; 1822 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1823 break; 1824 case PCI_DEVICE_ID_QLOGIC_ISP2432: 1825 ha->device_type |= DT_ISP2432; 1826 ha->device_type |= DT_ZIO_SUPPORTED; 1827 ha->device_type |= DT_FWI2; 1828 ha->device_type |= DT_IIDMA; 1829 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1830 break; 1831 case PCI_DEVICE_ID_QLOGIC_ISP8432: 1832 ha->device_type |= DT_ISP8432; 1833 ha->device_type |= DT_ZIO_SUPPORTED; 1834 ha->device_type |= DT_FWI2; 1835 ha->device_type |= DT_IIDMA; 1836 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1837 break; 1838 case PCI_DEVICE_ID_QLOGIC_ISP5422: 1839 ha->device_type |= DT_ISP5422; 1840 ha->device_type |= DT_FWI2; 1841 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1842 break; 1843 case PCI_DEVICE_ID_QLOGIC_ISP5432: 1844 ha->device_type |= DT_ISP5432; 1845 ha->device_type |= DT_FWI2; 1846 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1847 break; 1848 case PCI_DEVICE_ID_QLOGIC_ISP2532: 1849 ha->device_type |= DT_ISP2532; 1850 ha->device_type |= DT_ZIO_SUPPORTED; 1851 ha->device_type |= DT_FWI2; 1852 ha->device_type |= DT_IIDMA; 1853 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1854 break; 1855 case PCI_DEVICE_ID_QLOGIC_ISP8001: 1856 ha->device_type |= DT_ISP8001; 1857 ha->device_type |= DT_ZIO_SUPPORTED; 1858 ha->device_type |= DT_FWI2; 1859 ha->device_type |= DT_IIDMA; 1860 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1861 break; 1862 case PCI_DEVICE_ID_QLOGIC_ISP8021: 1863 ha->device_type |= DT_ISP8021; 1864 ha->device_type |= DT_ZIO_SUPPORTED; 1865 ha->device_type |= DT_FWI2; 1866 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1867 /* Initialize 82XX ISP flags */ 1868 qla82xx_init_flags(ha); 1869 break; 1870 } 1871 1872 if (IS_QLA82XX(ha)) 1873 ha->port_no = !(ha->portnum & 1); 1874 else 1875 /* Get adapter physical port no from interrupt pin register. */ 1876 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 1877 1878 if (ha->port_no & 1) 1879 ha->flags.port0 = 1; 1880 else 1881 ha->flags.port0 = 0; 1882 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 1883 "device_type=0x%x port=%d fw_srisc_address=%p.\n", 1884 ha->device_type, ha->flags.port0, ha->fw_srisc_address); 1885 } 1886 1887 static int 1888 qla2x00_iospace_config(struct qla_hw_data *ha) 1889 { 1890 resource_size_t pio; 1891 uint16_t msix; 1892 int cpus; 1893 1894 if (IS_QLA82XX(ha)) 1895 return qla82xx_iospace_config(ha); 1896 1897 if (pci_request_selected_regions(ha->pdev, ha->bars, 1898 QLA2XXX_DRIVER_NAME)) { 1899 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1900 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1901 pci_name(ha->pdev)); 1902 goto iospace_error_exit; 1903 } 1904 if (!(ha->bars & 1)) 1905 goto skip_pio; 1906 1907 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1908 pio = pci_resource_start(ha->pdev, 0); 1909 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1910 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1912 "Invalid pci I/O region size (%s).\n", 1913 pci_name(ha->pdev)); 1914 pio = 0; 1915 } 1916 } else { 1917 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1918 "Region #0 no a PIO resource (%s).\n", 1919 pci_name(ha->pdev)); 1920 pio = 0; 1921 } 1922 ha->pio_address = pio; 1923 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1924 "PIO address=%p.\n", 1925 ha->pio_address); 1926 1927 skip_pio: 1928 /* Use MMIO operations for all accesses. */ 1929 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1931 "Region #1 not an MMIO resource (%s), aborting.\n", 1932 pci_name(ha->pdev)); 1933 goto iospace_error_exit; 1934 } 1935 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1936 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1937 "Invalid PCI mem region size (%s), aborting.\n", 1938 pci_name(ha->pdev)); 1939 goto iospace_error_exit; 1940 } 1941 1942 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1943 if (!ha->iobase) { 1944 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1945 "Cannot remap MMIO (%s), aborting.\n", 1946 pci_name(ha->pdev)); 1947 goto iospace_error_exit; 1948 } 1949 1950 /* Determine queue resources */ 1951 ha->max_req_queues = ha->max_rsp_queues = 1; 1952 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1953 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1954 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1955 goto mqiobase_exit; 1956 1957 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1958 pci_resource_len(ha->pdev, 3)); 1959 if (ha->mqiobase) { 1960 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1961 "MQIO Base=%p.\n", ha->mqiobase); 1962 /* Read MSIX vector size of the board */ 1963 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1964 ha->msix_count = msix; 1965 /* Max queues are bounded by available msix vectors */ 1966 /* queue 0 uses two msix vectors */ 1967 if (ql2xmultique_tag) { 1968 cpus = num_online_cpus(); 1969 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1970 (cpus + 1) : (ha->msix_count - 1); 1971 ha->max_req_queues = 2; 1972 } else if (ql2xmaxqueues > 1) { 1973 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1974 QLA_MQ_SIZE : ql2xmaxqueues; 1975 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1976 "QoS mode set, max no of request queues:%d.\n", 1977 ha->max_req_queues); 1978 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1979 "QoS mode set, max no of request queues:%d.\n", 1980 ha->max_req_queues); 1981 } 1982 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1983 "MSI-X vector count: %d.\n", msix); 1984 } else 1985 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1986 "BAR 3 not enabled.\n"); 1987 1988 mqiobase_exit: 1989 ha->msix_count = ha->max_rsp_queues + 1; 1990 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1991 "MSIX Count:%d.\n", ha->msix_count); 1992 return (0); 1993 1994 iospace_error_exit: 1995 return (-ENOMEM); 1996 } 1997 1998 static void 1999 qla2xxx_scan_start(struct Scsi_Host *shost) 2000 { 2001 scsi_qla_host_t *vha = shost_priv(shost); 2002 2003 if (vha->hw->flags.running_gold_fw) 2004 return; 2005 2006 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2007 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2008 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2009 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2010 } 2011 2012 static int 2013 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2014 { 2015 scsi_qla_host_t *vha = shost_priv(shost); 2016 2017 if (!vha->host) 2018 return 1; 2019 if (time > vha->hw->loop_reset_delay * HZ) 2020 return 1; 2021 2022 return atomic_read(&vha->loop_state) == LOOP_READY; 2023 } 2024 2025 /* 2026 * PCI driver interface 2027 */ 2028 static int __devinit 2029 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2030 { 2031 int ret = -ENODEV; 2032 struct Scsi_Host *host; 2033 scsi_qla_host_t *base_vha = NULL; 2034 struct qla_hw_data *ha; 2035 char pci_info[30]; 2036 char fw_str[30]; 2037 struct scsi_host_template *sht; 2038 int bars, max_id, mem_only = 0; 2039 uint16_t req_length = 0, rsp_length = 0; 2040 struct req_que *req = NULL; 2041 struct rsp_que *rsp = NULL; 2042 2043 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2044 sht = &qla2xxx_driver_template; 2045 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2046 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2047 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2048 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2049 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2050 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2051 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2052 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) { 2053 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2054 mem_only = 1; 2055 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2056 "Mem only adapter.\n"); 2057 } 2058 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2059 "Bars=%d.\n", bars); 2060 2061 if (mem_only) { 2062 if (pci_enable_device_mem(pdev)) 2063 goto probe_out; 2064 } else { 2065 if (pci_enable_device(pdev)) 2066 goto probe_out; 2067 } 2068 2069 /* This may fail but that's ok */ 2070 pci_enable_pcie_error_reporting(pdev); 2071 2072 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2073 if (!ha) { 2074 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2075 "Unable to allocate memory for ha.\n"); 2076 goto probe_out; 2077 } 2078 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2079 "Memory allocated for ha=%p.\n", ha); 2080 ha->pdev = pdev; 2081 2082 /* Clear our data area */ 2083 ha->bars = bars; 2084 ha->mem_only = mem_only; 2085 spin_lock_init(&ha->hardware_lock); 2086 spin_lock_init(&ha->vport_slock); 2087 2088 /* Set ISP-type information. */ 2089 qla2x00_set_isp_flags(ha); 2090 2091 /* Set EEH reset type to fundamental if required by hba */ 2092 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) { 2093 pdev->needs_freset = 1; 2094 } 2095 2096 /* Configure PCI I/O space */ 2097 ret = qla2x00_iospace_config(ha); 2098 if (ret) 2099 goto probe_hw_failed; 2100 2101 ql_log_pci(ql_log_info, pdev, 0x001d, 2102 "Found an ISP%04X irq %d iobase 0x%p.\n", 2103 pdev->device, pdev->irq, ha->iobase); 2104 ha->prev_topology = 0; 2105 ha->init_cb_size = sizeof(init_cb_t); 2106 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2107 ha->optrom_size = OPTROM_SIZE_2300; 2108 2109 /* Assign ISP specific operations. */ 2110 max_id = MAX_TARGETS_2200; 2111 if (IS_QLA2100(ha)) { 2112 max_id = MAX_TARGETS_2100; 2113 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2114 req_length = REQUEST_ENTRY_CNT_2100; 2115 rsp_length = RESPONSE_ENTRY_CNT_2100; 2116 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2117 ha->gid_list_info_size = 4; 2118 ha->flash_conf_off = ~0; 2119 ha->flash_data_off = ~0; 2120 ha->nvram_conf_off = ~0; 2121 ha->nvram_data_off = ~0; 2122 ha->isp_ops = &qla2100_isp_ops; 2123 } else if (IS_QLA2200(ha)) { 2124 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2125 req_length = REQUEST_ENTRY_CNT_2200; 2126 rsp_length = RESPONSE_ENTRY_CNT_2100; 2127 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2128 ha->gid_list_info_size = 4; 2129 ha->flash_conf_off = ~0; 2130 ha->flash_data_off = ~0; 2131 ha->nvram_conf_off = ~0; 2132 ha->nvram_data_off = ~0; 2133 ha->isp_ops = &qla2100_isp_ops; 2134 } else if (IS_QLA23XX(ha)) { 2135 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2136 req_length = REQUEST_ENTRY_CNT_2200; 2137 rsp_length = RESPONSE_ENTRY_CNT_2300; 2138 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2139 ha->gid_list_info_size = 6; 2140 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2141 ha->optrom_size = OPTROM_SIZE_2322; 2142 ha->flash_conf_off = ~0; 2143 ha->flash_data_off = ~0; 2144 ha->nvram_conf_off = ~0; 2145 ha->nvram_data_off = ~0; 2146 ha->isp_ops = &qla2300_isp_ops; 2147 } else if (IS_QLA24XX_TYPE(ha)) { 2148 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2149 req_length = REQUEST_ENTRY_CNT_24XX; 2150 rsp_length = RESPONSE_ENTRY_CNT_2300; 2151 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2152 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2153 ha->gid_list_info_size = 8; 2154 ha->optrom_size = OPTROM_SIZE_24XX; 2155 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2156 ha->isp_ops = &qla24xx_isp_ops; 2157 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2158 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2159 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2160 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2161 } else if (IS_QLA25XX(ha)) { 2162 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2163 req_length = REQUEST_ENTRY_CNT_24XX; 2164 rsp_length = RESPONSE_ENTRY_CNT_2300; 2165 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2166 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2167 ha->gid_list_info_size = 8; 2168 ha->optrom_size = OPTROM_SIZE_25XX; 2169 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2170 ha->isp_ops = &qla25xx_isp_ops; 2171 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2172 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2173 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2174 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2175 } else if (IS_QLA81XX(ha)) { 2176 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2177 req_length = REQUEST_ENTRY_CNT_24XX; 2178 rsp_length = RESPONSE_ENTRY_CNT_2300; 2179 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2180 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2181 ha->gid_list_info_size = 8; 2182 ha->optrom_size = OPTROM_SIZE_81XX; 2183 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2184 ha->isp_ops = &qla81xx_isp_ops; 2185 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2186 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2187 ha->nvram_conf_off = ~0; 2188 ha->nvram_data_off = ~0; 2189 } else if (IS_QLA82XX(ha)) { 2190 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2191 req_length = REQUEST_ENTRY_CNT_82XX; 2192 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2193 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2194 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2195 ha->gid_list_info_size = 8; 2196 ha->optrom_size = OPTROM_SIZE_82XX; 2197 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2198 ha->isp_ops = &qla82xx_isp_ops; 2199 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2200 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2201 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2202 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2203 } 2204 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2205 "mbx_count=%d, req_length=%d, " 2206 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2207 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n", 2208 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2209 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2210 ha->nvram_npiv_size); 2211 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2212 "isp_ops=%p, flash_conf_off=%d, " 2213 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2214 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2215 ha->nvram_conf_off, ha->nvram_data_off); 2216 mutex_init(&ha->vport_lock); 2217 init_completion(&ha->mbx_cmd_comp); 2218 complete(&ha->mbx_cmd_comp); 2219 init_completion(&ha->mbx_intr_comp); 2220 init_completion(&ha->dcbx_comp); 2221 2222 set_bit(0, (unsigned long *) ha->vp_idx_map); 2223 2224 qla2x00_config_dma_addressing(ha); 2225 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2226 "64 Bit addressing is %s.\n", 2227 ha->flags.enable_64bit_addressing ? "enable" : 2228 "disable"); 2229 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2230 if (!ret) { 2231 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2232 "Failed to allocate memory for adapter, aborting.\n"); 2233 2234 goto probe_hw_failed; 2235 } 2236 2237 req->max_q_depth = MAX_Q_DEPTH; 2238 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2239 req->max_q_depth = ql2xmaxqdepth; 2240 2241 2242 base_vha = qla2x00_create_host(sht, ha); 2243 if (!base_vha) { 2244 ret = -ENOMEM; 2245 qla2x00_mem_free(ha); 2246 qla2x00_free_req_que(ha, req); 2247 qla2x00_free_rsp_que(ha, rsp); 2248 goto probe_hw_failed; 2249 } 2250 2251 pci_set_drvdata(pdev, base_vha); 2252 2253 host = base_vha->host; 2254 base_vha->req = req; 2255 host->can_queue = req->length + 128; 2256 if (IS_QLA2XXX_MIDTYPE(ha)) 2257 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2258 else 2259 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2260 base_vha->vp_idx; 2261 2262 /* Set the SG table size based on ISP type */ 2263 if (!IS_FWI2_CAPABLE(ha)) { 2264 if (IS_QLA2100(ha)) 2265 host->sg_tablesize = 32; 2266 } else { 2267 if (!IS_QLA82XX(ha)) 2268 host->sg_tablesize = QLA_SG_ALL; 2269 } 2270 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2271 "can_queue=%d, req=%p, " 2272 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2273 host->can_queue, base_vha->req, 2274 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2275 host->max_id = max_id; 2276 host->this_id = 255; 2277 host->cmd_per_lun = 3; 2278 host->unique_id = host->host_no; 2279 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2280 host->max_cmd_len = 32; 2281 else 2282 host->max_cmd_len = MAX_CMDSZ; 2283 host->max_channel = MAX_BUSES - 1; 2284 host->max_lun = ql2xmaxlun; 2285 host->transportt = qla2xxx_transport_template; 2286 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2287 2288 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2289 "max_id=%d this_id=%d " 2290 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2291 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id, 2292 host->this_id, host->cmd_per_lun, host->unique_id, 2293 host->max_cmd_len, host->max_channel, host->max_lun, 2294 host->transportt, sht->vendor_id); 2295 2296 /* Set up the irqs */ 2297 ret = qla2x00_request_irqs(ha, rsp); 2298 if (ret) 2299 goto probe_init_failed; 2300 2301 pci_save_state(pdev); 2302 2303 /* Alloc arrays of request and response ring ptrs */ 2304 que_init: 2305 if (!qla2x00_alloc_queues(ha)) { 2306 ql_log(ql_log_fatal, base_vha, 0x003d, 2307 "Failed to allocate memory for queue pointers.. aborting.\n"); 2308 goto probe_init_failed; 2309 } 2310 2311 ha->rsp_q_map[0] = rsp; 2312 ha->req_q_map[0] = req; 2313 rsp->req = req; 2314 req->rsp = rsp; 2315 set_bit(0, ha->req_qid_map); 2316 set_bit(0, ha->rsp_qid_map); 2317 /* FWI2-capable only. */ 2318 req->req_q_in = &ha->iobase->isp24.req_q_in; 2319 req->req_q_out = &ha->iobase->isp24.req_q_out; 2320 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2321 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2322 if (ha->mqenable) { 2323 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2324 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2325 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2326 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2327 } 2328 2329 if (IS_QLA82XX(ha)) { 2330 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2331 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2332 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2333 } 2334 2335 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2336 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2337 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2338 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2339 "req->req_q_in=%p req->req_q_out=%p " 2340 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2341 req->req_q_in, req->req_q_out, 2342 rsp->rsp_q_in, rsp->rsp_q_out); 2343 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2344 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2345 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2346 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2347 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2348 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2349 2350 if (qla2x00_initialize_adapter(base_vha)) { 2351 ql_log(ql_log_fatal, base_vha, 0x00d6, 2352 "Failed to initialize adapter - Adapter flags %x.\n", 2353 base_vha->device_flags); 2354 2355 if (IS_QLA82XX(ha)) { 2356 qla82xx_idc_lock(ha); 2357 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2358 QLA82XX_DEV_FAILED); 2359 qla82xx_idc_unlock(ha); 2360 ql_log(ql_log_fatal, base_vha, 0x00d7, 2361 "HW State: FAILED.\n"); 2362 } 2363 2364 ret = -ENODEV; 2365 goto probe_failed; 2366 } 2367 2368 if (ha->mqenable) { 2369 if (qla25xx_setup_mode(base_vha)) { 2370 ql_log(ql_log_warn, base_vha, 0x00ec, 2371 "Failed to create queues, falling back to single queue mode.\n"); 2372 goto que_init; 2373 } 2374 } 2375 2376 if (ha->flags.running_gold_fw) 2377 goto skip_dpc; 2378 2379 /* 2380 * Startup the kernel thread for this host adapter 2381 */ 2382 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2383 "%s_dpc", base_vha->host_str); 2384 if (IS_ERR(ha->dpc_thread)) { 2385 ql_log(ql_log_fatal, base_vha, 0x00ed, 2386 "Failed to start DPC thread.\n"); 2387 ret = PTR_ERR(ha->dpc_thread); 2388 goto probe_failed; 2389 } 2390 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2391 "DPC thread started successfully.\n"); 2392 2393 skip_dpc: 2394 list_add_tail(&base_vha->list, &ha->vp_list); 2395 base_vha->host->irq = ha->pdev->irq; 2396 2397 /* Initialized the timer */ 2398 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2399 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2400 "Started qla2x00_timer with " 2401 "interval=%d.\n", WATCH_INTERVAL); 2402 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2403 "Detected hba at address=%p.\n", 2404 ha); 2405 2406 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2407 if (ha->fw_attributes & BIT_4) { 2408 int prot = 0; 2409 base_vha->flags.difdix_supported = 1; 2410 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2411 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2412 if (ql2xenabledif == 1) 2413 prot = SHOST_DIX_TYPE0_PROTECTION; 2414 scsi_host_set_prot(host, 2415 prot | SHOST_DIF_TYPE1_PROTECTION 2416 | SHOST_DIF_TYPE2_PROTECTION 2417 | SHOST_DIF_TYPE3_PROTECTION 2418 | SHOST_DIX_TYPE1_PROTECTION 2419 | SHOST_DIX_TYPE2_PROTECTION 2420 | SHOST_DIX_TYPE3_PROTECTION); 2421 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); 2422 } else 2423 base_vha->flags.difdix_supported = 0; 2424 } 2425 2426 ha->isp_ops->enable_intrs(ha); 2427 2428 ret = scsi_add_host(host, &pdev->dev); 2429 if (ret) 2430 goto probe_failed; 2431 2432 base_vha->flags.init_done = 1; 2433 base_vha->flags.online = 1; 2434 2435 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2436 "Init done and hba is online.\n"); 2437 2438 scsi_scan_host(host); 2439 2440 qla2x00_alloc_sysfs_attr(base_vha); 2441 2442 qla2x00_init_host_attr(base_vha); 2443 2444 qla2x00_dfs_setup(base_vha); 2445 2446 ql_log(ql_log_info, base_vha, 0x00fa, 2447 "QLogic Fibre Channed HBA Driver: %s.\n", 2448 qla2x00_version_str); 2449 ql_log(ql_log_info, base_vha, 0x00fb, 2450 "QLogic %s - %s.\n", 2451 ha->model_number, ha->model_desc ? ha->model_desc : ""); 2452 ql_log(ql_log_info, base_vha, 0x00fc, 2453 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2454 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2455 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2456 base_vha->host_no, 2457 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2458 2459 return 0; 2460 2461 probe_init_failed: 2462 qla2x00_free_req_que(ha, req); 2463 qla2x00_free_rsp_que(ha, rsp); 2464 ha->max_req_queues = ha->max_rsp_queues = 0; 2465 2466 probe_failed: 2467 if (base_vha->timer_active) 2468 qla2x00_stop_timer(base_vha); 2469 base_vha->flags.online = 0; 2470 if (ha->dpc_thread) { 2471 struct task_struct *t = ha->dpc_thread; 2472 2473 ha->dpc_thread = NULL; 2474 kthread_stop(t); 2475 } 2476 2477 qla2x00_free_device(base_vha); 2478 2479 scsi_host_put(base_vha->host); 2480 2481 probe_hw_failed: 2482 if (IS_QLA82XX(ha)) { 2483 qla82xx_idc_lock(ha); 2484 qla82xx_clear_drv_active(ha); 2485 qla82xx_idc_unlock(ha); 2486 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2487 if (!ql2xdbwr) 2488 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2489 } else { 2490 if (ha->iobase) 2491 iounmap(ha->iobase); 2492 } 2493 pci_release_selected_regions(ha->pdev, ha->bars); 2494 kfree(ha); 2495 ha = NULL; 2496 2497 probe_out: 2498 pci_disable_device(pdev); 2499 return ret; 2500 } 2501 2502 static void 2503 qla2x00_shutdown(struct pci_dev *pdev) 2504 { 2505 scsi_qla_host_t *vha; 2506 struct qla_hw_data *ha; 2507 2508 vha = pci_get_drvdata(pdev); 2509 ha = vha->hw; 2510 2511 /* Turn-off FCE trace */ 2512 if (ha->flags.fce_enabled) { 2513 qla2x00_disable_fce_trace(vha, NULL, NULL); 2514 ha->flags.fce_enabled = 0; 2515 } 2516 2517 /* Turn-off EFT trace */ 2518 if (ha->eft) 2519 qla2x00_disable_eft_trace(vha); 2520 2521 /* Stop currently executing firmware. */ 2522 qla2x00_try_to_stop_firmware(vha); 2523 2524 /* Turn adapter off line */ 2525 vha->flags.online = 0; 2526 2527 /* turn-off interrupts on the card */ 2528 if (ha->interrupts_on) { 2529 vha->flags.init_done = 0; 2530 ha->isp_ops->disable_intrs(ha); 2531 } 2532 2533 qla2x00_free_irqs(vha); 2534 2535 qla2x00_free_fw_dump(ha); 2536 } 2537 2538 static void 2539 qla2x00_remove_one(struct pci_dev *pdev) 2540 { 2541 scsi_qla_host_t *base_vha, *vha; 2542 struct qla_hw_data *ha; 2543 unsigned long flags; 2544 2545 base_vha = pci_get_drvdata(pdev); 2546 ha = base_vha->hw; 2547 2548 mutex_lock(&ha->vport_lock); 2549 while (ha->cur_vport_count) { 2550 struct Scsi_Host *scsi_host; 2551 2552 spin_lock_irqsave(&ha->vport_slock, flags); 2553 2554 BUG_ON(base_vha->list.next == &ha->vp_list); 2555 /* This assumes first entry in ha->vp_list is always base vha */ 2556 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2557 scsi_host = scsi_host_get(vha->host); 2558 2559 spin_unlock_irqrestore(&ha->vport_slock, flags); 2560 mutex_unlock(&ha->vport_lock); 2561 2562 fc_vport_terminate(vha->fc_vport); 2563 scsi_host_put(vha->host); 2564 2565 mutex_lock(&ha->vport_lock); 2566 } 2567 mutex_unlock(&ha->vport_lock); 2568 2569 set_bit(UNLOADING, &base_vha->dpc_flags); 2570 2571 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 2572 2573 qla2x00_dfs_remove(base_vha); 2574 2575 qla84xx_put_chip(base_vha); 2576 2577 /* Disable timer */ 2578 if (base_vha->timer_active) 2579 qla2x00_stop_timer(base_vha); 2580 2581 base_vha->flags.online = 0; 2582 2583 /* Flush the work queue and remove it */ 2584 if (ha->wq) { 2585 flush_workqueue(ha->wq); 2586 destroy_workqueue(ha->wq); 2587 ha->wq = NULL; 2588 } 2589 2590 /* Kill the kernel thread for this host */ 2591 if (ha->dpc_thread) { 2592 struct task_struct *t = ha->dpc_thread; 2593 2594 /* 2595 * qla2xxx_wake_dpc checks for ->dpc_thread 2596 * so we need to zero it out. 2597 */ 2598 ha->dpc_thread = NULL; 2599 kthread_stop(t); 2600 } 2601 2602 qla2x00_free_sysfs_attr(base_vha); 2603 2604 fc_remove_host(base_vha->host); 2605 2606 scsi_remove_host(base_vha->host); 2607 2608 qla2x00_free_device(base_vha); 2609 2610 scsi_host_put(base_vha->host); 2611 2612 if (IS_QLA82XX(ha)) { 2613 qla82xx_idc_lock(ha); 2614 qla82xx_clear_drv_active(ha); 2615 qla82xx_idc_unlock(ha); 2616 2617 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2618 if (!ql2xdbwr) 2619 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2620 } else { 2621 if (ha->iobase) 2622 iounmap(ha->iobase); 2623 2624 if (ha->mqiobase) 2625 iounmap(ha->mqiobase); 2626 } 2627 2628 pci_release_selected_regions(ha->pdev, ha->bars); 2629 kfree(ha); 2630 ha = NULL; 2631 2632 pci_disable_pcie_error_reporting(pdev); 2633 2634 pci_disable_device(pdev); 2635 pci_set_drvdata(pdev, NULL); 2636 } 2637 2638 static void 2639 qla2x00_free_device(scsi_qla_host_t *vha) 2640 { 2641 struct qla_hw_data *ha = vha->hw; 2642 2643 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2644 2645 /* Disable timer */ 2646 if (vha->timer_active) 2647 qla2x00_stop_timer(vha); 2648 2649 /* Kill the kernel thread for this host */ 2650 if (ha->dpc_thread) { 2651 struct task_struct *t = ha->dpc_thread; 2652 2653 /* 2654 * qla2xxx_wake_dpc checks for ->dpc_thread 2655 * so we need to zero it out. 2656 */ 2657 ha->dpc_thread = NULL; 2658 kthread_stop(t); 2659 } 2660 2661 qla25xx_delete_queues(vha); 2662 2663 if (ha->flags.fce_enabled) 2664 qla2x00_disable_fce_trace(vha, NULL, NULL); 2665 2666 if (ha->eft) 2667 qla2x00_disable_eft_trace(vha); 2668 2669 /* Stop currently executing firmware. */ 2670 qla2x00_try_to_stop_firmware(vha); 2671 2672 vha->flags.online = 0; 2673 2674 /* turn-off interrupts on the card */ 2675 if (ha->interrupts_on) { 2676 vha->flags.init_done = 0; 2677 ha->isp_ops->disable_intrs(ha); 2678 } 2679 2680 qla2x00_free_irqs(vha); 2681 2682 qla2x00_free_fcports(vha); 2683 2684 qla2x00_mem_free(ha); 2685 2686 qla82xx_md_free(vha); 2687 2688 qla2x00_free_queues(ha); 2689 } 2690 2691 void qla2x00_free_fcports(struct scsi_qla_host *vha) 2692 { 2693 fc_port_t *fcport, *tfcport; 2694 2695 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 2696 list_del(&fcport->list); 2697 kfree(fcport); 2698 fcport = NULL; 2699 } 2700 } 2701 2702 static inline void 2703 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 2704 int defer) 2705 { 2706 struct fc_rport *rport; 2707 scsi_qla_host_t *base_vha; 2708 unsigned long flags; 2709 2710 if (!fcport->rport) 2711 return; 2712 2713 rport = fcport->rport; 2714 if (defer) { 2715 base_vha = pci_get_drvdata(vha->hw->pdev); 2716 spin_lock_irqsave(vha->host->host_lock, flags); 2717 fcport->drport = rport; 2718 spin_unlock_irqrestore(vha->host->host_lock, flags); 2719 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 2720 qla2xxx_wake_dpc(base_vha); 2721 } else 2722 fc_remote_port_delete(rport); 2723 } 2724 2725 /* 2726 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 2727 * 2728 * Input: ha = adapter block pointer. fcport = port structure pointer. 2729 * 2730 * Return: None. 2731 * 2732 * Context: 2733 */ 2734 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 2735 int do_login, int defer) 2736 { 2737 if (atomic_read(&fcport->state) == FCS_ONLINE && 2738 vha->vp_idx == fcport->vp_idx) { 2739 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2740 qla2x00_schedule_rport_del(vha, fcport, defer); 2741 } 2742 /* 2743 * We may need to retry the login, so don't change the state of the 2744 * port but do the retries. 2745 */ 2746 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 2747 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2748 2749 if (!do_login) 2750 return; 2751 2752 if (fcport->login_retry == 0) { 2753 fcport->login_retry = vha->hw->login_retry_count; 2754 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2755 2756 ql_dbg(ql_dbg_disc, vha, 0x2067, 2757 "Port login retry " 2758 "%02x%02x%02x%02x%02x%02x%02x%02x, " 2759 "id = 0x%04x retry cnt=%d.\n", 2760 fcport->port_name[0], fcport->port_name[1], 2761 fcport->port_name[2], fcport->port_name[3], 2762 fcport->port_name[4], fcport->port_name[5], 2763 fcport->port_name[6], fcport->port_name[7], 2764 fcport->loop_id, fcport->login_retry); 2765 } 2766 } 2767 2768 /* 2769 * qla2x00_mark_all_devices_lost 2770 * Updates fcport state when device goes offline. 2771 * 2772 * Input: 2773 * ha = adapter block pointer. 2774 * fcport = port structure pointer. 2775 * 2776 * Return: 2777 * None. 2778 * 2779 * Context: 2780 */ 2781 void 2782 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 2783 { 2784 fc_port_t *fcport; 2785 2786 list_for_each_entry(fcport, &vha->vp_fcports, list) { 2787 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx) 2788 continue; 2789 2790 /* 2791 * No point in marking the device as lost, if the device is 2792 * already DEAD. 2793 */ 2794 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 2795 continue; 2796 if (atomic_read(&fcport->state) == FCS_ONLINE) { 2797 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2798 if (defer) 2799 qla2x00_schedule_rport_del(vha, fcport, defer); 2800 else if (vha->vp_idx == fcport->vp_idx) 2801 qla2x00_schedule_rport_del(vha, fcport, defer); 2802 } 2803 } 2804 } 2805 2806 /* 2807 * qla2x00_mem_alloc 2808 * Allocates adapter memory. 2809 * 2810 * Returns: 2811 * 0 = success. 2812 * !0 = failure. 2813 */ 2814 static int 2815 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 2816 struct req_que **req, struct rsp_que **rsp) 2817 { 2818 char name[16]; 2819 2820 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 2821 &ha->init_cb_dma, GFP_KERNEL); 2822 if (!ha->init_cb) 2823 goto fail; 2824 2825 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE, 2826 &ha->gid_list_dma, GFP_KERNEL); 2827 if (!ha->gid_list) 2828 goto fail_free_init_cb; 2829 2830 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 2831 if (!ha->srb_mempool) 2832 goto fail_free_gid_list; 2833 2834 if (IS_QLA82XX(ha)) { 2835 /* Allocate cache for CT6 Ctx. */ 2836 if (!ctx_cachep) { 2837 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 2838 sizeof(struct ct6_dsd), 0, 2839 SLAB_HWCACHE_ALIGN, NULL); 2840 if (!ctx_cachep) 2841 goto fail_free_gid_list; 2842 } 2843 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 2844 ctx_cachep); 2845 if (!ha->ctx_mempool) 2846 goto fail_free_srb_mempool; 2847 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 2848 "ctx_cachep=%p ctx_mempool=%p.\n", 2849 ctx_cachep, ha->ctx_mempool); 2850 } 2851 2852 /* Get memory for cached NVRAM */ 2853 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 2854 if (!ha->nvram) 2855 goto fail_free_ctx_mempool; 2856 2857 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 2858 ha->pdev->device); 2859 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2860 DMA_POOL_SIZE, 8, 0); 2861 if (!ha->s_dma_pool) 2862 goto fail_free_nvram; 2863 2864 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 2865 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 2866 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 2867 2868 if (IS_QLA82XX(ha) || ql2xenabledif) { 2869 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2870 DSD_LIST_DMA_POOL_SIZE, 8, 0); 2871 if (!ha->dl_dma_pool) { 2872 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 2873 "Failed to allocate memory for dl_dma_pool.\n"); 2874 goto fail_s_dma_pool; 2875 } 2876 2877 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2878 FCP_CMND_DMA_POOL_SIZE, 8, 0); 2879 if (!ha->fcp_cmnd_dma_pool) { 2880 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 2881 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 2882 goto fail_dl_dma_pool; 2883 } 2884 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 2885 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 2886 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 2887 } 2888 2889 /* Allocate memory for SNS commands */ 2890 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 2891 /* Get consistent memory allocated for SNS commands */ 2892 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 2893 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 2894 if (!ha->sns_cmd) 2895 goto fail_dma_pool; 2896 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 2897 "sns_cmd.\n", ha->sns_cmd); 2898 } else { 2899 /* Get consistent memory allocated for MS IOCB */ 2900 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2901 &ha->ms_iocb_dma); 2902 if (!ha->ms_iocb) 2903 goto fail_dma_pool; 2904 /* Get consistent memory allocated for CT SNS commands */ 2905 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 2906 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 2907 if (!ha->ct_sns) 2908 goto fail_free_ms_iocb; 2909 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 2910 "ms_iocb=%p ct_sns=%p.\n", 2911 ha->ms_iocb, ha->ct_sns); 2912 } 2913 2914 /* Allocate memory for request ring */ 2915 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 2916 if (!*req) { 2917 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 2918 "Failed to allocate memory for req.\n"); 2919 goto fail_req; 2920 } 2921 (*req)->length = req_len; 2922 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 2923 ((*req)->length + 1) * sizeof(request_t), 2924 &(*req)->dma, GFP_KERNEL); 2925 if (!(*req)->ring) { 2926 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 2927 "Failed to allocate memory for req_ring.\n"); 2928 goto fail_req_ring; 2929 } 2930 /* Allocate memory for response ring */ 2931 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 2932 if (!*rsp) { 2933 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 2934 "Failed to allocate memory for rsp.\n"); 2935 goto fail_rsp; 2936 } 2937 (*rsp)->hw = ha; 2938 (*rsp)->length = rsp_len; 2939 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 2940 ((*rsp)->length + 1) * sizeof(response_t), 2941 &(*rsp)->dma, GFP_KERNEL); 2942 if (!(*rsp)->ring) { 2943 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 2944 "Failed to allocate memory for rsp_ring.\n"); 2945 goto fail_rsp_ring; 2946 } 2947 (*req)->rsp = *rsp; 2948 (*rsp)->req = *req; 2949 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 2950 "req=%p req->length=%d req->ring=%p rsp=%p " 2951 "rsp->length=%d rsp->ring=%p.\n", 2952 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 2953 (*rsp)->ring); 2954 /* Allocate memory for NVRAM data for vports */ 2955 if (ha->nvram_npiv_size) { 2956 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 2957 ha->nvram_npiv_size, GFP_KERNEL); 2958 if (!ha->npiv_info) { 2959 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 2960 "Failed to allocate memory for npiv_info.\n"); 2961 goto fail_npiv_info; 2962 } 2963 } else 2964 ha->npiv_info = NULL; 2965 2966 /* Get consistent memory allocated for EX-INIT-CB. */ 2967 if (IS_QLA8XXX_TYPE(ha)) { 2968 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2969 &ha->ex_init_cb_dma); 2970 if (!ha->ex_init_cb) 2971 goto fail_ex_init_cb; 2972 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 2973 "ex_init_cb=%p.\n", ha->ex_init_cb); 2974 } 2975 2976 INIT_LIST_HEAD(&ha->gbl_dsd_list); 2977 2978 /* Get consistent memory allocated for Async Port-Database. */ 2979 if (!IS_FWI2_CAPABLE(ha)) { 2980 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2981 &ha->async_pd_dma); 2982 if (!ha->async_pd) 2983 goto fail_async_pd; 2984 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 2985 "async_pd=%p.\n", ha->async_pd); 2986 } 2987 2988 INIT_LIST_HEAD(&ha->vp_list); 2989 return 1; 2990 2991 fail_async_pd: 2992 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 2993 fail_ex_init_cb: 2994 kfree(ha->npiv_info); 2995 fail_npiv_info: 2996 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 2997 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 2998 (*rsp)->ring = NULL; 2999 (*rsp)->dma = 0; 3000 fail_rsp_ring: 3001 kfree(*rsp); 3002 fail_rsp: 3003 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3004 sizeof(request_t), (*req)->ring, (*req)->dma); 3005 (*req)->ring = NULL; 3006 (*req)->dma = 0; 3007 fail_req_ring: 3008 kfree(*req); 3009 fail_req: 3010 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3011 ha->ct_sns, ha->ct_sns_dma); 3012 ha->ct_sns = NULL; 3013 ha->ct_sns_dma = 0; 3014 fail_free_ms_iocb: 3015 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3016 ha->ms_iocb = NULL; 3017 ha->ms_iocb_dma = 0; 3018 fail_dma_pool: 3019 if (IS_QLA82XX(ha) || ql2xenabledif) { 3020 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3021 ha->fcp_cmnd_dma_pool = NULL; 3022 } 3023 fail_dl_dma_pool: 3024 if (IS_QLA82XX(ha) || ql2xenabledif) { 3025 dma_pool_destroy(ha->dl_dma_pool); 3026 ha->dl_dma_pool = NULL; 3027 } 3028 fail_s_dma_pool: 3029 dma_pool_destroy(ha->s_dma_pool); 3030 ha->s_dma_pool = NULL; 3031 fail_free_nvram: 3032 kfree(ha->nvram); 3033 ha->nvram = NULL; 3034 fail_free_ctx_mempool: 3035 mempool_destroy(ha->ctx_mempool); 3036 ha->ctx_mempool = NULL; 3037 fail_free_srb_mempool: 3038 mempool_destroy(ha->srb_mempool); 3039 ha->srb_mempool = NULL; 3040 fail_free_gid_list: 3041 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, 3042 ha->gid_list_dma); 3043 ha->gid_list = NULL; 3044 ha->gid_list_dma = 0; 3045 fail_free_init_cb: 3046 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3047 ha->init_cb_dma); 3048 ha->init_cb = NULL; 3049 ha->init_cb_dma = 0; 3050 fail: 3051 ql_log(ql_log_fatal, NULL, 0x0030, 3052 "Memory allocation failure.\n"); 3053 return -ENOMEM; 3054 } 3055 3056 /* 3057 * qla2x00_free_fw_dump 3058 * Frees fw dump stuff. 3059 * 3060 * Input: 3061 * ha = adapter block pointer. 3062 */ 3063 static void 3064 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3065 { 3066 if (ha->fce) 3067 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 3068 ha->fce_dma); 3069 3070 if (ha->fw_dump) { 3071 if (ha->eft) 3072 dma_free_coherent(&ha->pdev->dev, 3073 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); 3074 vfree(ha->fw_dump); 3075 } 3076 ha->fce = NULL; 3077 ha->fce_dma = 0; 3078 ha->eft = NULL; 3079 ha->eft_dma = 0; 3080 ha->fw_dump = NULL; 3081 ha->fw_dumped = 0; 3082 ha->fw_dump_reading = 0; 3083 } 3084 3085 /* 3086 * qla2x00_mem_free 3087 * Frees all adapter allocated memory. 3088 * 3089 * Input: 3090 * ha = adapter block pointer. 3091 */ 3092 static void 3093 qla2x00_mem_free(struct qla_hw_data *ha) 3094 { 3095 qla2x00_free_fw_dump(ha); 3096 3097 if (ha->srb_mempool) 3098 mempool_destroy(ha->srb_mempool); 3099 3100 if (ha->dcbx_tlv) 3101 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3102 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3103 3104 if (ha->xgmac_data) 3105 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3106 ha->xgmac_data, ha->xgmac_data_dma); 3107 3108 if (ha->sns_cmd) 3109 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3110 ha->sns_cmd, ha->sns_cmd_dma); 3111 3112 if (ha->ct_sns) 3113 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3114 ha->ct_sns, ha->ct_sns_dma); 3115 3116 if (ha->sfp_data) 3117 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3118 3119 if (ha->edc_data) 3120 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma); 3121 3122 if (ha->ms_iocb) 3123 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3124 3125 if (ha->ex_init_cb) 3126 dma_pool_free(ha->s_dma_pool, 3127 ha->ex_init_cb, ha->ex_init_cb_dma); 3128 3129 if (ha->async_pd) 3130 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3131 3132 if (ha->s_dma_pool) 3133 dma_pool_destroy(ha->s_dma_pool); 3134 3135 if (ha->gid_list) 3136 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, 3137 ha->gid_list_dma); 3138 3139 if (IS_QLA82XX(ha)) { 3140 if (!list_empty(&ha->gbl_dsd_list)) { 3141 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3142 3143 /* clean up allocated prev pool */ 3144 list_for_each_entry_safe(dsd_ptr, 3145 tdsd_ptr, &ha->gbl_dsd_list, list) { 3146 dma_pool_free(ha->dl_dma_pool, 3147 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3148 list_del(&dsd_ptr->list); 3149 kfree(dsd_ptr); 3150 } 3151 } 3152 } 3153 3154 if (ha->dl_dma_pool) 3155 dma_pool_destroy(ha->dl_dma_pool); 3156 3157 if (ha->fcp_cmnd_dma_pool) 3158 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3159 3160 if (ha->ctx_mempool) 3161 mempool_destroy(ha->ctx_mempool); 3162 3163 if (ha->init_cb) 3164 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3165 ha->init_cb, ha->init_cb_dma); 3166 vfree(ha->optrom_buffer); 3167 kfree(ha->nvram); 3168 kfree(ha->npiv_info); 3169 3170 ha->srb_mempool = NULL; 3171 ha->ctx_mempool = NULL; 3172 ha->sns_cmd = NULL; 3173 ha->sns_cmd_dma = 0; 3174 ha->ct_sns = NULL; 3175 ha->ct_sns_dma = 0; 3176 ha->ms_iocb = NULL; 3177 ha->ms_iocb_dma = 0; 3178 ha->init_cb = NULL; 3179 ha->init_cb_dma = 0; 3180 ha->ex_init_cb = NULL; 3181 ha->ex_init_cb_dma = 0; 3182 ha->async_pd = NULL; 3183 ha->async_pd_dma = 0; 3184 3185 ha->s_dma_pool = NULL; 3186 ha->dl_dma_pool = NULL; 3187 ha->fcp_cmnd_dma_pool = NULL; 3188 3189 ha->gid_list = NULL; 3190 ha->gid_list_dma = 0; 3191 } 3192 3193 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3194 struct qla_hw_data *ha) 3195 { 3196 struct Scsi_Host *host; 3197 struct scsi_qla_host *vha = NULL; 3198 3199 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3200 if (host == NULL) { 3201 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3202 "Failed to allocate host from the scsi layer, aborting.\n"); 3203 goto fail; 3204 } 3205 3206 /* Clear our data area */ 3207 vha = shost_priv(host); 3208 memset(vha, 0, sizeof(scsi_qla_host_t)); 3209 3210 vha->host = host; 3211 vha->host_no = host->host_no; 3212 vha->hw = ha; 3213 3214 INIT_LIST_HEAD(&vha->vp_fcports); 3215 INIT_LIST_HEAD(&vha->work_list); 3216 INIT_LIST_HEAD(&vha->list); 3217 3218 spin_lock_init(&vha->work_lock); 3219 3220 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3221 ql_dbg(ql_dbg_init, vha, 0x0041, 3222 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3223 vha->host, vha->hw, vha, 3224 dev_name(&(ha->pdev->dev))); 3225 3226 return vha; 3227 3228 fail: 3229 return vha; 3230 } 3231 3232 static struct qla_work_evt * 3233 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3234 { 3235 struct qla_work_evt *e; 3236 uint8_t bail; 3237 3238 QLA_VHA_MARK_BUSY(vha, bail); 3239 if (bail) 3240 return NULL; 3241 3242 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3243 if (!e) { 3244 QLA_VHA_MARK_NOT_BUSY(vha); 3245 return NULL; 3246 } 3247 3248 INIT_LIST_HEAD(&e->list); 3249 e->type = type; 3250 e->flags = QLA_EVT_FLAG_FREE; 3251 return e; 3252 } 3253 3254 static int 3255 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3256 { 3257 unsigned long flags; 3258 3259 spin_lock_irqsave(&vha->work_lock, flags); 3260 list_add_tail(&e->list, &vha->work_list); 3261 spin_unlock_irqrestore(&vha->work_lock, flags); 3262 qla2xxx_wake_dpc(vha); 3263 3264 return QLA_SUCCESS; 3265 } 3266 3267 int 3268 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3269 u32 data) 3270 { 3271 struct qla_work_evt *e; 3272 3273 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3274 if (!e) 3275 return QLA_FUNCTION_FAILED; 3276 3277 e->u.aen.code = code; 3278 e->u.aen.data = data; 3279 return qla2x00_post_work(vha, e); 3280 } 3281 3282 int 3283 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3284 { 3285 struct qla_work_evt *e; 3286 3287 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3288 if (!e) 3289 return QLA_FUNCTION_FAILED; 3290 3291 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3292 return qla2x00_post_work(vha, e); 3293 } 3294 3295 #define qla2x00_post_async_work(name, type) \ 3296 int qla2x00_post_async_##name##_work( \ 3297 struct scsi_qla_host *vha, \ 3298 fc_port_t *fcport, uint16_t *data) \ 3299 { \ 3300 struct qla_work_evt *e; \ 3301 \ 3302 e = qla2x00_alloc_work(vha, type); \ 3303 if (!e) \ 3304 return QLA_FUNCTION_FAILED; \ 3305 \ 3306 e->u.logio.fcport = fcport; \ 3307 if (data) { \ 3308 e->u.logio.data[0] = data[0]; \ 3309 e->u.logio.data[1] = data[1]; \ 3310 } \ 3311 return qla2x00_post_work(vha, e); \ 3312 } 3313 3314 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3315 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3316 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3317 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3318 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3319 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3320 3321 int 3322 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3323 { 3324 struct qla_work_evt *e; 3325 3326 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3327 if (!e) 3328 return QLA_FUNCTION_FAILED; 3329 3330 e->u.uevent.code = code; 3331 return qla2x00_post_work(vha, e); 3332 } 3333 3334 static void 3335 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3336 { 3337 char event_string[40]; 3338 char *envp[] = { event_string, NULL }; 3339 3340 switch (code) { 3341 case QLA_UEVENT_CODE_FW_DUMP: 3342 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3343 vha->host_no); 3344 break; 3345 default: 3346 /* do nothing */ 3347 break; 3348 } 3349 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3350 } 3351 3352 void 3353 qla2x00_do_work(struct scsi_qla_host *vha) 3354 { 3355 struct qla_work_evt *e, *tmp; 3356 unsigned long flags; 3357 LIST_HEAD(work); 3358 3359 spin_lock_irqsave(&vha->work_lock, flags); 3360 list_splice_init(&vha->work_list, &work); 3361 spin_unlock_irqrestore(&vha->work_lock, flags); 3362 3363 list_for_each_entry_safe(e, tmp, &work, list) { 3364 list_del_init(&e->list); 3365 3366 switch (e->type) { 3367 case QLA_EVT_AEN: 3368 fc_host_post_event(vha->host, fc_get_event_number(), 3369 e->u.aen.code, e->u.aen.data); 3370 break; 3371 case QLA_EVT_IDC_ACK: 3372 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3373 break; 3374 case QLA_EVT_ASYNC_LOGIN: 3375 qla2x00_async_login(vha, e->u.logio.fcport, 3376 e->u.logio.data); 3377 break; 3378 case QLA_EVT_ASYNC_LOGIN_DONE: 3379 qla2x00_async_login_done(vha, e->u.logio.fcport, 3380 e->u.logio.data); 3381 break; 3382 case QLA_EVT_ASYNC_LOGOUT: 3383 qla2x00_async_logout(vha, e->u.logio.fcport); 3384 break; 3385 case QLA_EVT_ASYNC_LOGOUT_DONE: 3386 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3387 e->u.logio.data); 3388 break; 3389 case QLA_EVT_ASYNC_ADISC: 3390 qla2x00_async_adisc(vha, e->u.logio.fcport, 3391 e->u.logio.data); 3392 break; 3393 case QLA_EVT_ASYNC_ADISC_DONE: 3394 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3395 e->u.logio.data); 3396 break; 3397 case QLA_EVT_UEVENT: 3398 qla2x00_uevent_emit(vha, e->u.uevent.code); 3399 break; 3400 } 3401 if (e->flags & QLA_EVT_FLAG_FREE) 3402 kfree(e); 3403 3404 /* For each work completed decrement vha ref count */ 3405 QLA_VHA_MARK_NOT_BUSY(vha); 3406 } 3407 } 3408 3409 /* Relogins all the fcports of a vport 3410 * Context: dpc thread 3411 */ 3412 void qla2x00_relogin(struct scsi_qla_host *vha) 3413 { 3414 fc_port_t *fcport; 3415 int status; 3416 uint16_t next_loopid = 0; 3417 struct qla_hw_data *ha = vha->hw; 3418 uint16_t data[2]; 3419 3420 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3421 /* 3422 * If the port is not ONLINE then try to login 3423 * to it if we haven't run out of retries. 3424 */ 3425 if (atomic_read(&fcport->state) != FCS_ONLINE && 3426 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3427 fcport->login_retry--; 3428 if (fcport->flags & FCF_FABRIC_DEVICE) { 3429 if (fcport->flags & FCF_FCP2_DEVICE) 3430 ha->isp_ops->fabric_logout(vha, 3431 fcport->loop_id, 3432 fcport->d_id.b.domain, 3433 fcport->d_id.b.area, 3434 fcport->d_id.b.al_pa); 3435 3436 if (fcport->loop_id == FC_NO_LOOP_ID) { 3437 fcport->loop_id = next_loopid = 3438 ha->min_external_loopid; 3439 status = qla2x00_find_new_loop_id( 3440 vha, fcport); 3441 if (status != QLA_SUCCESS) { 3442 /* Ran out of IDs to use */ 3443 break; 3444 } 3445 } 3446 3447 if (IS_ALOGIO_CAPABLE(ha)) { 3448 fcport->flags |= FCF_ASYNC_SENT; 3449 data[0] = 0; 3450 data[1] = QLA_LOGIO_LOGIN_RETRIED; 3451 status = qla2x00_post_async_login_work( 3452 vha, fcport, data); 3453 if (status == QLA_SUCCESS) 3454 continue; 3455 /* Attempt a retry. */ 3456 status = 1; 3457 } else 3458 status = qla2x00_fabric_login(vha, 3459 fcport, &next_loopid); 3460 } else 3461 status = qla2x00_local_device_login(vha, 3462 fcport); 3463 3464 if (status == QLA_SUCCESS) { 3465 fcport->old_loop_id = fcport->loop_id; 3466 3467 ql_dbg(ql_dbg_disc, vha, 0x2003, 3468 "Port login OK: logged in ID 0x%x.\n", 3469 fcport->loop_id); 3470 3471 qla2x00_update_fcport(vha, fcport); 3472 3473 } else if (status == 1) { 3474 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3475 /* retry the login again */ 3476 ql_dbg(ql_dbg_disc, vha, 0x2007, 3477 "Retrying %d login again loop_id 0x%x.\n", 3478 fcport->login_retry, fcport->loop_id); 3479 } else { 3480 fcport->login_retry = 0; 3481 } 3482 3483 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 3484 fcport->loop_id = FC_NO_LOOP_ID; 3485 } 3486 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3487 break; 3488 } 3489 } 3490 3491 /************************************************************************** 3492 * qla2x00_do_dpc 3493 * This kernel thread is a task that is schedule by the interrupt handler 3494 * to perform the background processing for interrupts. 3495 * 3496 * Notes: 3497 * This task always run in the context of a kernel thread. It 3498 * is kick-off by the driver's detect code and starts up 3499 * up one per adapter. It immediately goes to sleep and waits for 3500 * some fibre event. When either the interrupt handler or 3501 * the timer routine detects a event it will one of the task 3502 * bits then wake us up. 3503 **************************************************************************/ 3504 static int 3505 qla2x00_do_dpc(void *data) 3506 { 3507 int rval; 3508 scsi_qla_host_t *base_vha; 3509 struct qla_hw_data *ha; 3510 3511 ha = (struct qla_hw_data *)data; 3512 base_vha = pci_get_drvdata(ha->pdev); 3513 3514 set_user_nice(current, -20); 3515 3516 set_current_state(TASK_INTERRUPTIBLE); 3517 while (!kthread_should_stop()) { 3518 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 3519 "DPC handler sleeping.\n"); 3520 3521 schedule(); 3522 __set_current_state(TASK_RUNNING); 3523 3524 ql_dbg(ql_dbg_dpc, base_vha, 0x4001, 3525 "DPC handler waking up.\n"); 3526 ql_dbg(ql_dbg_dpc, base_vha, 0x4002, 3527 "dpc_flags=0x%lx.\n", base_vha->dpc_flags); 3528 3529 /* Initialization not yet finished. Don't do anything yet. */ 3530 if (!base_vha->flags.init_done) 3531 continue; 3532 3533 if (ha->flags.eeh_busy) { 3534 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 3535 "eeh_busy=%d.\n", ha->flags.eeh_busy); 3536 continue; 3537 } 3538 3539 ha->dpc_active = 1; 3540 3541 if (ha->flags.mbox_busy) { 3542 ha->dpc_active = 0; 3543 continue; 3544 } 3545 3546 qla2x00_do_work(base_vha); 3547 3548 if (IS_QLA82XX(ha)) { 3549 if (test_and_clear_bit(ISP_UNRECOVERABLE, 3550 &base_vha->dpc_flags)) { 3551 qla82xx_idc_lock(ha); 3552 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3553 QLA82XX_DEV_FAILED); 3554 qla82xx_idc_unlock(ha); 3555 ql_log(ql_log_info, base_vha, 0x4004, 3556 "HW State: FAILED.\n"); 3557 qla82xx_device_state_handler(base_vha); 3558 continue; 3559 } 3560 3561 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 3562 &base_vha->dpc_flags)) { 3563 3564 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 3565 "FCoE context reset scheduled.\n"); 3566 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3567 &base_vha->dpc_flags))) { 3568 if (qla82xx_fcoe_ctx_reset(base_vha)) { 3569 /* FCoE-ctx reset failed. 3570 * Escalate to chip-reset 3571 */ 3572 set_bit(ISP_ABORT_NEEDED, 3573 &base_vha->dpc_flags); 3574 } 3575 clear_bit(ABORT_ISP_ACTIVE, 3576 &base_vha->dpc_flags); 3577 } 3578 3579 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 3580 "FCoE context reset end.\n"); 3581 } 3582 } 3583 3584 if (test_and_clear_bit(ISP_ABORT_NEEDED, 3585 &base_vha->dpc_flags)) { 3586 3587 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 3588 "ISP abort scheduled.\n"); 3589 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3590 &base_vha->dpc_flags))) { 3591 3592 if (ha->isp_ops->abort_isp(base_vha)) { 3593 /* failed. retry later */ 3594 set_bit(ISP_ABORT_NEEDED, 3595 &base_vha->dpc_flags); 3596 } 3597 clear_bit(ABORT_ISP_ACTIVE, 3598 &base_vha->dpc_flags); 3599 } 3600 3601 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 3602 "ISP abort end.\n"); 3603 } 3604 3605 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { 3606 qla2x00_update_fcports(base_vha); 3607 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3608 } 3609 3610 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 3611 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 3612 "Quiescence mode scheduled.\n"); 3613 qla82xx_device_state_handler(base_vha); 3614 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); 3615 if (!ha->flags.quiesce_owner) { 3616 qla2x00_perform_loop_resync(base_vha); 3617 3618 qla82xx_idc_lock(ha); 3619 qla82xx_clear_qsnt_ready(base_vha); 3620 qla82xx_idc_unlock(ha); 3621 } 3622 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 3623 "Quiescence mode end.\n"); 3624 } 3625 3626 if (test_and_clear_bit(RESET_MARKER_NEEDED, 3627 &base_vha->dpc_flags) && 3628 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 3629 3630 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 3631 "Reset marker scheduled.\n"); 3632 qla2x00_rst_aen(base_vha); 3633 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 3634 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 3635 "Reset marker end.\n"); 3636 } 3637 3638 /* Retry each device up to login retry count */ 3639 if ((test_and_clear_bit(RELOGIN_NEEDED, 3640 &base_vha->dpc_flags)) && 3641 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 3642 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 3643 3644 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 3645 "Relogin scheduled.\n"); 3646 qla2x00_relogin(base_vha); 3647 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 3648 "Relogin end.\n"); 3649 } 3650 3651 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 3652 &base_vha->dpc_flags)) { 3653 3654 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 3655 "Loop resync scheduled.\n"); 3656 3657 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 3658 &base_vha->dpc_flags))) { 3659 3660 rval = qla2x00_loop_resync(base_vha); 3661 3662 clear_bit(LOOP_RESYNC_ACTIVE, 3663 &base_vha->dpc_flags); 3664 } 3665 3666 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 3667 "Loop resync end.\n"); 3668 } 3669 3670 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 3671 atomic_read(&base_vha->loop_state) == LOOP_READY) { 3672 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 3673 qla2xxx_flash_npiv_conf(base_vha); 3674 } 3675 3676 if (!ha->interrupts_on) 3677 ha->isp_ops->enable_intrs(ha); 3678 3679 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 3680 &base_vha->dpc_flags)) 3681 ha->isp_ops->beacon_blink(base_vha); 3682 3683 qla2x00_do_dpc_all_vps(base_vha); 3684 3685 ha->dpc_active = 0; 3686 set_current_state(TASK_INTERRUPTIBLE); 3687 } /* End of while(1) */ 3688 __set_current_state(TASK_RUNNING); 3689 3690 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 3691 "DPC handler exiting.\n"); 3692 3693 /* 3694 * Make sure that nobody tries to wake us up again. 3695 */ 3696 ha->dpc_active = 0; 3697 3698 /* Cleanup any residual CTX SRBs. */ 3699 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3700 3701 return 0; 3702 } 3703 3704 void 3705 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 3706 { 3707 struct qla_hw_data *ha = vha->hw; 3708 struct task_struct *t = ha->dpc_thread; 3709 3710 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 3711 wake_up_process(t); 3712 } 3713 3714 /* 3715 * qla2x00_rst_aen 3716 * Processes asynchronous reset. 3717 * 3718 * Input: 3719 * ha = adapter block pointer. 3720 */ 3721 static void 3722 qla2x00_rst_aen(scsi_qla_host_t *vha) 3723 { 3724 if (vha->flags.online && !vha->flags.reset_active && 3725 !atomic_read(&vha->loop_down_timer) && 3726 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 3727 do { 3728 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 3729 3730 /* 3731 * Issue marker command only when we are going to start 3732 * the I/O. 3733 */ 3734 vha->marker_needed = 1; 3735 } while (!atomic_read(&vha->loop_down_timer) && 3736 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 3737 } 3738 } 3739 3740 static void 3741 qla2x00_sp_free_dma(srb_t *sp) 3742 { 3743 struct scsi_cmnd *cmd = sp->cmd; 3744 struct qla_hw_data *ha = sp->fcport->vha->hw; 3745 3746 if (sp->flags & SRB_DMA_VALID) { 3747 scsi_dma_unmap(cmd); 3748 sp->flags &= ~SRB_DMA_VALID; 3749 } 3750 3751 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 3752 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 3753 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 3754 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 3755 } 3756 3757 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 3758 /* List assured to be having elements */ 3759 qla2x00_clean_dsd_pool(ha, sp); 3760 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 3761 } 3762 3763 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 3764 dma_pool_free(ha->dl_dma_pool, sp->ctx, 3765 ((struct crc_context *)sp->ctx)->crc_ctx_dma); 3766 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 3767 } 3768 3769 CMD_SP(cmd) = NULL; 3770 } 3771 3772 static void 3773 qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp) 3774 { 3775 struct scsi_cmnd *cmd = sp->cmd; 3776 3777 qla2x00_sp_free_dma(sp); 3778 3779 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 3780 struct ct6_dsd *ctx = sp->ctx; 3781 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, 3782 ctx->fcp_cmnd_dma); 3783 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list); 3784 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt; 3785 ha->gbl_dsd_avail += ctx->dsd_use_cnt; 3786 mempool_free(sp->ctx, ha->ctx_mempool); 3787 sp->ctx = NULL; 3788 } 3789 3790 mempool_free(sp, ha->srb_mempool); 3791 cmd->scsi_done(cmd); 3792 } 3793 3794 void 3795 qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp) 3796 { 3797 if (atomic_read(&sp->ref_count) == 0) { 3798 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 3799 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 3800 sp, sp->cmd); 3801 if (ql2xextended_error_logging & ql_dbg_io) 3802 BUG(); 3803 return; 3804 } 3805 if (!atomic_dec_and_test(&sp->ref_count)) 3806 return; 3807 qla2x00_sp_final_compl(ha, sp); 3808 } 3809 3810 /************************************************************************** 3811 * qla2x00_timer 3812 * 3813 * Description: 3814 * One second timer 3815 * 3816 * Context: Interrupt 3817 ***************************************************************************/ 3818 void 3819 qla2x00_timer(scsi_qla_host_t *vha) 3820 { 3821 unsigned long cpu_flags = 0; 3822 int start_dpc = 0; 3823 int index; 3824 srb_t *sp; 3825 uint16_t w; 3826 struct qla_hw_data *ha = vha->hw; 3827 struct req_que *req; 3828 3829 if (ha->flags.eeh_busy) { 3830 ql_dbg(ql_dbg_timer, vha, 0x6000, 3831 "EEH = %d, restarting timer.\n", 3832 ha->flags.eeh_busy); 3833 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3834 return; 3835 } 3836 3837 /* Hardware read to raise pending EEH errors during mailbox waits. */ 3838 if (!pci_channel_offline(ha->pdev)) 3839 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 3840 3841 /* Make sure qla82xx_watchdog is run only for physical port */ 3842 if (!vha->vp_idx && IS_QLA82XX(ha)) { 3843 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 3844 start_dpc++; 3845 qla82xx_watchdog(vha); 3846 } 3847 3848 /* Loop down handler. */ 3849 if (atomic_read(&vha->loop_down_timer) > 0 && 3850 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 3851 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 3852 && vha->flags.online) { 3853 3854 if (atomic_read(&vha->loop_down_timer) == 3855 vha->loop_down_abort_time) { 3856 3857 ql_log(ql_log_info, vha, 0x6008, 3858 "Loop down - aborting the queues before time expires.\n"); 3859 3860 if (!IS_QLA2100(ha) && vha->link_down_timeout) 3861 atomic_set(&vha->loop_state, LOOP_DEAD); 3862 3863 /* 3864 * Schedule an ISP abort to return any FCP2-device 3865 * commands. 3866 */ 3867 /* NPIV - scan physical port only */ 3868 if (!vha->vp_idx) { 3869 spin_lock_irqsave(&ha->hardware_lock, 3870 cpu_flags); 3871 req = ha->req_q_map[0]; 3872 for (index = 1; 3873 index < MAX_OUTSTANDING_COMMANDS; 3874 index++) { 3875 fc_port_t *sfcp; 3876 3877 sp = req->outstanding_cmds[index]; 3878 if (!sp) 3879 continue; 3880 if (sp->ctx && !IS_PROT_IO(sp)) 3881 continue; 3882 sfcp = sp->fcport; 3883 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 3884 continue; 3885 3886 if (IS_QLA82XX(ha)) 3887 set_bit(FCOE_CTX_RESET_NEEDED, 3888 &vha->dpc_flags); 3889 else 3890 set_bit(ISP_ABORT_NEEDED, 3891 &vha->dpc_flags); 3892 break; 3893 } 3894 spin_unlock_irqrestore(&ha->hardware_lock, 3895 cpu_flags); 3896 } 3897 start_dpc++; 3898 } 3899 3900 /* if the loop has been down for 4 minutes, reinit adapter */ 3901 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 3902 if (!(vha->device_flags & DFLG_NO_CABLE)) { 3903 ql_log(ql_log_warn, vha, 0x6009, 3904 "Loop down - aborting ISP.\n"); 3905 3906 if (IS_QLA82XX(ha)) 3907 set_bit(FCOE_CTX_RESET_NEEDED, 3908 &vha->dpc_flags); 3909 else 3910 set_bit(ISP_ABORT_NEEDED, 3911 &vha->dpc_flags); 3912 } 3913 } 3914 ql_dbg(ql_dbg_timer, vha, 0x600a, 3915 "Loop down - seconds remaining %d.\n", 3916 atomic_read(&vha->loop_down_timer)); 3917 } 3918 3919 /* Check if beacon LED needs to be blinked for physical host only */ 3920 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 3921 /* There is no beacon_blink function for ISP82xx */ 3922 if (!IS_QLA82XX(ha)) { 3923 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 3924 start_dpc++; 3925 } 3926 } 3927 3928 /* Process any deferred work. */ 3929 if (!list_empty(&vha->work_list)) 3930 start_dpc++; 3931 3932 /* Schedule the DPC routine if needed */ 3933 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 3934 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 3935 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 3936 start_dpc || 3937 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 3938 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 3939 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 3940 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3941 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 3942 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 3943 ql_dbg(ql_dbg_timer, vha, 0x600b, 3944 "isp_abort_needed=%d loop_resync_needed=%d " 3945 "fcport_update_needed=%d start_dpc=%d " 3946 "reset_marker_needed=%d", 3947 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 3948 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 3949 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 3950 start_dpc, 3951 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 3952 ql_dbg(ql_dbg_timer, vha, 0x600c, 3953 "beacon_blink_needed=%d isp_unrecoverable=%d " 3954 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 3955 "relogin_needed=%d.\n", 3956 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 3957 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 3958 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 3959 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 3960 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 3961 qla2xxx_wake_dpc(vha); 3962 } 3963 3964 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3965 } 3966 3967 /* Firmware interface routines. */ 3968 3969 #define FW_BLOBS 8 3970 #define FW_ISP21XX 0 3971 #define FW_ISP22XX 1 3972 #define FW_ISP2300 2 3973 #define FW_ISP2322 3 3974 #define FW_ISP24XX 4 3975 #define FW_ISP25XX 5 3976 #define FW_ISP81XX 6 3977 #define FW_ISP82XX 7 3978 3979 #define FW_FILE_ISP21XX "ql2100_fw.bin" 3980 #define FW_FILE_ISP22XX "ql2200_fw.bin" 3981 #define FW_FILE_ISP2300 "ql2300_fw.bin" 3982 #define FW_FILE_ISP2322 "ql2322_fw.bin" 3983 #define FW_FILE_ISP24XX "ql2400_fw.bin" 3984 #define FW_FILE_ISP25XX "ql2500_fw.bin" 3985 #define FW_FILE_ISP81XX "ql8100_fw.bin" 3986 #define FW_FILE_ISP82XX "ql8200_fw.bin" 3987 3988 static DEFINE_MUTEX(qla_fw_lock); 3989 3990 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 3991 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 3992 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 3993 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 3994 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 3995 { .name = FW_FILE_ISP24XX, }, 3996 { .name = FW_FILE_ISP25XX, }, 3997 { .name = FW_FILE_ISP81XX, }, 3998 { .name = FW_FILE_ISP82XX, }, 3999 }; 4000 4001 struct fw_blob * 4002 qla2x00_request_firmware(scsi_qla_host_t *vha) 4003 { 4004 struct qla_hw_data *ha = vha->hw; 4005 struct fw_blob *blob; 4006 4007 blob = NULL; 4008 if (IS_QLA2100(ha)) { 4009 blob = &qla_fw_blobs[FW_ISP21XX]; 4010 } else if (IS_QLA2200(ha)) { 4011 blob = &qla_fw_blobs[FW_ISP22XX]; 4012 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4013 blob = &qla_fw_blobs[FW_ISP2300]; 4014 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 4015 blob = &qla_fw_blobs[FW_ISP2322]; 4016 } else if (IS_QLA24XX_TYPE(ha)) { 4017 blob = &qla_fw_blobs[FW_ISP24XX]; 4018 } else if (IS_QLA25XX(ha)) { 4019 blob = &qla_fw_blobs[FW_ISP25XX]; 4020 } else if (IS_QLA81XX(ha)) { 4021 blob = &qla_fw_blobs[FW_ISP81XX]; 4022 } else if (IS_QLA82XX(ha)) { 4023 blob = &qla_fw_blobs[FW_ISP82XX]; 4024 } 4025 4026 mutex_lock(&qla_fw_lock); 4027 if (blob->fw) 4028 goto out; 4029 4030 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 4031 ql_log(ql_log_warn, vha, 0x0063, 4032 "Failed to load firmware image (%s).\n", blob->name); 4033 blob->fw = NULL; 4034 blob = NULL; 4035 goto out; 4036 } 4037 4038 out: 4039 mutex_unlock(&qla_fw_lock); 4040 return blob; 4041 } 4042 4043 static void 4044 qla2x00_release_firmware(void) 4045 { 4046 int idx; 4047 4048 mutex_lock(&qla_fw_lock); 4049 for (idx = 0; idx < FW_BLOBS; idx++) 4050 if (qla_fw_blobs[idx].fw) 4051 release_firmware(qla_fw_blobs[idx].fw); 4052 mutex_unlock(&qla_fw_lock); 4053 } 4054 4055 static pci_ers_result_t 4056 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 4057 { 4058 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 4059 struct qla_hw_data *ha = vha->hw; 4060 4061 ql_dbg(ql_dbg_aer, vha, 0x9000, 4062 "PCI error detected, state %x.\n", state); 4063 4064 switch (state) { 4065 case pci_channel_io_normal: 4066 ha->flags.eeh_busy = 0; 4067 return PCI_ERS_RESULT_CAN_RECOVER; 4068 case pci_channel_io_frozen: 4069 ha->flags.eeh_busy = 1; 4070 /* For ISP82XX complete any pending mailbox cmd */ 4071 if (IS_QLA82XX(ha)) { 4072 ha->flags.isp82xx_fw_hung = 1; 4073 if (ha->flags.mbox_busy) { 4074 ha->flags.mbox_int = 1; 4075 ql_dbg(ql_dbg_aer, vha, 0x9001, 4076 "Due to pci channel io frozen, doing premature " 4077 "completion of mbx command.\n"); 4078 complete(&ha->mbx_intr_comp); 4079 } 4080 } 4081 qla2x00_free_irqs(vha); 4082 pci_disable_device(pdev); 4083 /* Return back all IOs */ 4084 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4085 return PCI_ERS_RESULT_NEED_RESET; 4086 case pci_channel_io_perm_failure: 4087 ha->flags.pci_channel_io_perm_failure = 1; 4088 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4089 return PCI_ERS_RESULT_DISCONNECT; 4090 } 4091 return PCI_ERS_RESULT_NEED_RESET; 4092 } 4093 4094 static pci_ers_result_t 4095 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 4096 { 4097 int risc_paused = 0; 4098 uint32_t stat; 4099 unsigned long flags; 4100 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4101 struct qla_hw_data *ha = base_vha->hw; 4102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4103 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 4104 4105 if (IS_QLA82XX(ha)) 4106 return PCI_ERS_RESULT_RECOVERED; 4107 4108 spin_lock_irqsave(&ha->hardware_lock, flags); 4109 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 4110 stat = RD_REG_DWORD(®->hccr); 4111 if (stat & HCCR_RISC_PAUSE) 4112 risc_paused = 1; 4113 } else if (IS_QLA23XX(ha)) { 4114 stat = RD_REG_DWORD(®->u.isp2300.host_status); 4115 if (stat & HSR_RISC_PAUSED) 4116 risc_paused = 1; 4117 } else if (IS_FWI2_CAPABLE(ha)) { 4118 stat = RD_REG_DWORD(®24->host_status); 4119 if (stat & HSRX_RISC_PAUSED) 4120 risc_paused = 1; 4121 } 4122 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4123 4124 if (risc_paused) { 4125 ql_log(ql_log_info, base_vha, 0x9003, 4126 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 4127 ha->isp_ops->fw_dump(base_vha, 0); 4128 4129 return PCI_ERS_RESULT_NEED_RESET; 4130 } else 4131 return PCI_ERS_RESULT_RECOVERED; 4132 } 4133 4134 uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) 4135 { 4136 uint32_t rval = QLA_FUNCTION_FAILED; 4137 uint32_t drv_active = 0; 4138 struct qla_hw_data *ha = base_vha->hw; 4139 int fn; 4140 struct pci_dev *other_pdev = NULL; 4141 4142 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 4143 "Entered %s.\n", __func__); 4144 4145 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4146 4147 if (base_vha->flags.online) { 4148 /* Abort all outstanding commands, 4149 * so as to be requeued later */ 4150 qla2x00_abort_isp_cleanup(base_vha); 4151 } 4152 4153 4154 fn = PCI_FUNC(ha->pdev->devfn); 4155 while (fn > 0) { 4156 fn--; 4157 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 4158 "Finding pci device at function = 0x%x.\n", fn); 4159 other_pdev = 4160 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 4161 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 4162 fn)); 4163 4164 if (!other_pdev) 4165 continue; 4166 if (atomic_read(&other_pdev->enable_cnt)) { 4167 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 4168 "Found PCI func available and enable at 0x%x.\n", 4169 fn); 4170 pci_dev_put(other_pdev); 4171 break; 4172 } 4173 pci_dev_put(other_pdev); 4174 } 4175 4176 if (!fn) { 4177 /* Reset owner */ 4178 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 4179 "This devfn is reset owner = 0x%x.\n", 4180 ha->pdev->devfn); 4181 qla82xx_idc_lock(ha); 4182 4183 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4184 QLA82XX_DEV_INITIALIZING); 4185 4186 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 4187 QLA82XX_IDC_VERSION); 4188 4189 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 4190 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 4191 "drv_active = 0x%x.\n", drv_active); 4192 4193 qla82xx_idc_unlock(ha); 4194 /* Reset if device is not already reset 4195 * drv_active would be 0 if a reset has already been done 4196 */ 4197 if (drv_active) 4198 rval = qla82xx_start_firmware(base_vha); 4199 else 4200 rval = QLA_SUCCESS; 4201 qla82xx_idc_lock(ha); 4202 4203 if (rval != QLA_SUCCESS) { 4204 ql_log(ql_log_info, base_vha, 0x900b, 4205 "HW State: FAILED.\n"); 4206 qla82xx_clear_drv_active(ha); 4207 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4208 QLA82XX_DEV_FAILED); 4209 } else { 4210 ql_log(ql_log_info, base_vha, 0x900c, 4211 "HW State: READY.\n"); 4212 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4213 QLA82XX_DEV_READY); 4214 qla82xx_idc_unlock(ha); 4215 ha->flags.isp82xx_fw_hung = 0; 4216 rval = qla82xx_restart_isp(base_vha); 4217 qla82xx_idc_lock(ha); 4218 /* Clear driver state register */ 4219 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 4220 qla82xx_set_drv_active(base_vha); 4221 } 4222 qla82xx_idc_unlock(ha); 4223 } else { 4224 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 4225 "This devfn is not reset owner = 0x%x.\n", 4226 ha->pdev->devfn); 4227 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 4228 QLA82XX_DEV_READY)) { 4229 ha->flags.isp82xx_fw_hung = 0; 4230 rval = qla82xx_restart_isp(base_vha); 4231 qla82xx_idc_lock(ha); 4232 qla82xx_set_drv_active(base_vha); 4233 qla82xx_idc_unlock(ha); 4234 } 4235 } 4236 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4237 4238 return rval; 4239 } 4240 4241 static pci_ers_result_t 4242 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 4243 { 4244 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 4245 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4246 struct qla_hw_data *ha = base_vha->hw; 4247 struct rsp_que *rsp; 4248 int rc, retries = 10; 4249 4250 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 4251 "Slot Reset.\n"); 4252 4253 /* Workaround: qla2xxx driver which access hardware earlier 4254 * needs error state to be pci_channel_io_online. 4255 * Otherwise mailbox command timesout. 4256 */ 4257 pdev->error_state = pci_channel_io_normal; 4258 4259 pci_restore_state(pdev); 4260 4261 /* pci_restore_state() clears the saved_state flag of the device 4262 * save restored state which resets saved_state flag 4263 */ 4264 pci_save_state(pdev); 4265 4266 if (ha->mem_only) 4267 rc = pci_enable_device_mem(pdev); 4268 else 4269 rc = pci_enable_device(pdev); 4270 4271 if (rc) { 4272 ql_log(ql_log_warn, base_vha, 0x9005, 4273 "Can't re-enable PCI device after reset.\n"); 4274 goto exit_slot_reset; 4275 } 4276 4277 rsp = ha->rsp_q_map[0]; 4278 if (qla2x00_request_irqs(ha, rsp)) 4279 goto exit_slot_reset; 4280 4281 if (ha->isp_ops->pci_config(base_vha)) 4282 goto exit_slot_reset; 4283 4284 if (IS_QLA82XX(ha)) { 4285 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 4286 ret = PCI_ERS_RESULT_RECOVERED; 4287 goto exit_slot_reset; 4288 } else 4289 goto exit_slot_reset; 4290 } 4291 4292 while (ha->flags.mbox_busy && retries--) 4293 msleep(1000); 4294 4295 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4296 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 4297 ret = PCI_ERS_RESULT_RECOVERED; 4298 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4299 4300 4301 exit_slot_reset: 4302 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 4303 "slot_reset return %x.\n", ret); 4304 4305 return ret; 4306 } 4307 4308 static void 4309 qla2xxx_pci_resume(struct pci_dev *pdev) 4310 { 4311 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4312 struct qla_hw_data *ha = base_vha->hw; 4313 int ret; 4314 4315 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 4316 "pci_resume.\n"); 4317 4318 ret = qla2x00_wait_for_hba_online(base_vha); 4319 if (ret != QLA_SUCCESS) { 4320 ql_log(ql_log_fatal, base_vha, 0x9002, 4321 "The device failed to resume I/O from slot/link_reset.\n"); 4322 } 4323 4324 pci_cleanup_aer_uncorrect_error_status(pdev); 4325 4326 ha->flags.eeh_busy = 0; 4327 } 4328 4329 static struct pci_error_handlers qla2xxx_err_handler = { 4330 .error_detected = qla2xxx_pci_error_detected, 4331 .mmio_enabled = qla2xxx_pci_mmio_enabled, 4332 .slot_reset = qla2xxx_pci_slot_reset, 4333 .resume = qla2xxx_pci_resume, 4334 }; 4335 4336 static struct pci_device_id qla2xxx_pci_tbl[] = { 4337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 4338 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 4339 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 4340 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 4341 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 4342 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 4343 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 4344 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 4345 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 4346 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 4347 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 4348 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 4349 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 4350 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 4351 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 4352 { 0 }, 4353 }; 4354 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 4355 4356 static struct pci_driver qla2xxx_pci_driver = { 4357 .name = QLA2XXX_DRIVER_NAME, 4358 .driver = { 4359 .owner = THIS_MODULE, 4360 }, 4361 .id_table = qla2xxx_pci_tbl, 4362 .probe = qla2x00_probe_one, 4363 .remove = qla2x00_remove_one, 4364 .shutdown = qla2x00_shutdown, 4365 .err_handler = &qla2xxx_err_handler, 4366 }; 4367 4368 static struct file_operations apidev_fops = { 4369 .owner = THIS_MODULE, 4370 .llseek = noop_llseek, 4371 }; 4372 4373 /** 4374 * qla2x00_module_init - Module initialization. 4375 **/ 4376 static int __init 4377 qla2x00_module_init(void) 4378 { 4379 int ret = 0; 4380 4381 /* Allocate cache for SRBs. */ 4382 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 4383 SLAB_HWCACHE_ALIGN, NULL); 4384 if (srb_cachep == NULL) { 4385 ql_log(ql_log_fatal, NULL, 0x0001, 4386 "Unable to allocate SRB cache...Failing load!.\n"); 4387 return -ENOMEM; 4388 } 4389 4390 /* Derive version string. */ 4391 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 4392 if (ql2xextended_error_logging) 4393 strcat(qla2x00_version_str, "-debug"); 4394 4395 qla2xxx_transport_template = 4396 fc_attach_transport(&qla2xxx_transport_functions); 4397 if (!qla2xxx_transport_template) { 4398 kmem_cache_destroy(srb_cachep); 4399 ql_log(ql_log_fatal, NULL, 0x0002, 4400 "fc_attach_transport failed...Failing load!.\n"); 4401 return -ENODEV; 4402 } 4403 4404 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 4405 if (apidev_major < 0) { 4406 ql_log(ql_log_fatal, NULL, 0x0003, 4407 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 4408 } 4409 4410 qla2xxx_transport_vport_template = 4411 fc_attach_transport(&qla2xxx_transport_vport_functions); 4412 if (!qla2xxx_transport_vport_template) { 4413 kmem_cache_destroy(srb_cachep); 4414 fc_release_transport(qla2xxx_transport_template); 4415 ql_log(ql_log_fatal, NULL, 0x0004, 4416 "fc_attach_transport vport failed...Failing load!.\n"); 4417 return -ENODEV; 4418 } 4419 ql_log(ql_log_info, NULL, 0x0005, 4420 "QLogic Fibre Channel HBA Driver: %s.\n", 4421 qla2x00_version_str); 4422 ret = pci_register_driver(&qla2xxx_pci_driver); 4423 if (ret) { 4424 kmem_cache_destroy(srb_cachep); 4425 fc_release_transport(qla2xxx_transport_template); 4426 fc_release_transport(qla2xxx_transport_vport_template); 4427 ql_log(ql_log_fatal, NULL, 0x0006, 4428 "pci_register_driver failed...ret=%d Failing load!.\n", 4429 ret); 4430 } 4431 return ret; 4432 } 4433 4434 /** 4435 * qla2x00_module_exit - Module cleanup. 4436 **/ 4437 static void __exit 4438 qla2x00_module_exit(void) 4439 { 4440 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 4441 pci_unregister_driver(&qla2xxx_pci_driver); 4442 qla2x00_release_firmware(); 4443 kmem_cache_destroy(srb_cachep); 4444 if (ctx_cachep) 4445 kmem_cache_destroy(ctx_cachep); 4446 fc_release_transport(qla2xxx_transport_template); 4447 fc_release_transport(qla2xxx_transport_vport_template); 4448 } 4449 4450 module_init(qla2x00_module_init); 4451 module_exit(qla2x00_module_exit); 4452 4453 MODULE_AUTHOR("QLogic Corporation"); 4454 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 4455 MODULE_LICENSE("GPL"); 4456 MODULE_VERSION(QLA2XXX_VERSION); 4457 MODULE_FIRMWARE(FW_FILE_ISP21XX); 4458 MODULE_FIRMWARE(FW_FILE_ISP22XX); 4459 MODULE_FIRMWARE(FW_FILE_ISP2300); 4460 MODULE_FIRMWARE(FW_FILE_ISP2322); 4461 MODULE_FIRMWARE(FW_FILE_ISP24XX); 4462 MODULE_FIRMWARE(FW_FILE_ISP25XX); 4463