1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101 int ql2xshiftctondsd = 6; 102 module_param(ql2xshiftctondsd, int, S_IRUGO); 103 MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107 int ql2xfdmienable=1; 108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 109 MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113 #define MAX_Q_DEPTH 32 114 static int ql2xmaxqdepth = MAX_Q_DEPTH; 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116 MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120 int ql2xenabledif = 2; 121 module_param(ql2xenabledif, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF:\n" 124 " Default is 2.\n" 125 " 0 -- No DIF Support\n" 126 " 1 -- Enable DIF for all types\n" 127 " 2 -- Enable DIF for all types, except Type 0.\n"); 128 129 int ql2xenablehba_err_chk = 2; 130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xenablehba_err_chk, 132 " Enable T10-CRC-DIF Error isolation by HBA:\n" 133 " Default is 2.\n" 134 " 0 -- Error isolation disabled\n" 135 " 1 -- Error isolation enabled only for DIX Type 0\n" 136 " 2 -- Error isolation enabled for all Types\n"); 137 138 int ql2xiidmaenable=1; 139 module_param(ql2xiidmaenable, int, S_IRUGO); 140 MODULE_PARM_DESC(ql2xiidmaenable, 141 "Enables iIDMA settings " 142 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 143 144 int ql2xmaxqueues = 1; 145 module_param(ql2xmaxqueues, int, S_IRUGO); 146 MODULE_PARM_DESC(ql2xmaxqueues, 147 "Enables MQ settings " 148 "Default is 1 for single queue. Set it to number " 149 "of queues in MQ mode."); 150 151 int ql2xmultique_tag; 152 module_param(ql2xmultique_tag, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xmultique_tag, 154 "Enables CPU affinity settings for the driver " 155 "Default is 0 for no affinity of request and response IO. " 156 "Set it to 1 to turn on the cpu affinity."); 157 158 int ql2xfwloadbin; 159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 160 MODULE_PARM_DESC(ql2xfwloadbin, 161 "Option to specify location from which to load ISP firmware:.\n" 162 " 2 -- load firmware via the request_firmware() (hotplug).\n" 163 " interface.\n" 164 " 1 -- load firmware from flash.\n" 165 " 0 -- use default semantics.\n"); 166 167 int ql2xetsenable; 168 module_param(ql2xetsenable, int, S_IRUGO); 169 MODULE_PARM_DESC(ql2xetsenable, 170 "Enables firmware ETS burst." 171 "Default is 0 - skip ETS enablement."); 172 173 int ql2xdbwr = 1; 174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 175 MODULE_PARM_DESC(ql2xdbwr, 176 "Option to specify scheme for request queue posting.\n" 177 " 0 -- Regular doorbell.\n" 178 " 1 -- CAMRAM doorbell (faster).\n"); 179 180 int ql2xtargetreset = 1; 181 module_param(ql2xtargetreset, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xtargetreset, 183 "Enable target reset." 184 "Default is 1 - use hw defaults."); 185 186 int ql2xgffidenable; 187 module_param(ql2xgffidenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xgffidenable, 189 "Enables GFF_ID checks of port type. " 190 "Default is 0 - Do not use GFF_ID information."); 191 192 int ql2xasynctmfenable; 193 module_param(ql2xasynctmfenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xasynctmfenable, 195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 196 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 197 198 int ql2xdontresethba; 199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdontresethba, 201 "Option to specify reset behaviour.\n" 202 " 0 (Default) -- Reset on failure.\n" 203 " 1 -- Do not reset on failure.\n"); 204 205 uint64_t ql2xmaxlun = MAX_LUNS; 206 module_param(ql2xmaxlun, ullong, S_IRUGO); 207 MODULE_PARM_DESC(ql2xmaxlun, 208 "Defines the maximum LU number to register with the SCSI " 209 "midlayer. Default is 65535."); 210 211 int ql2xmdcapmask = 0x1F; 212 module_param(ql2xmdcapmask, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xmdcapmask, 214 "Set the Minidump driver capture mask level. " 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 216 217 int ql2xmdenable = 1; 218 module_param(ql2xmdenable, int, S_IRUGO); 219 MODULE_PARM_DESC(ql2xmdenable, 220 "Enable/disable MiniDump. " 221 "0 - MiniDump disabled. " 222 "1 (Default) - MiniDump enabled."); 223 224 /* 225 * SCSI host template entry points 226 */ 227 static int qla2xxx_slave_configure(struct scsi_device * device); 228 static int qla2xxx_slave_alloc(struct scsi_device *); 229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 230 static void qla2xxx_scan_start(struct Scsi_Host *); 231 static void qla2xxx_slave_destroy(struct scsi_device *); 232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 233 static int qla2xxx_eh_abort(struct scsi_cmnd *); 234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 238 239 static void qla2x00_clear_drv_active(struct qla_hw_data *); 240 static void qla2x00_free_device(scsi_qla_host_t *); 241 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 242 243 struct scsi_host_template qla2xxx_driver_template = { 244 .module = THIS_MODULE, 245 .name = QLA2XXX_DRIVER_NAME, 246 .queuecommand = qla2xxx_queuecommand, 247 248 .eh_abort_handler = qla2xxx_eh_abort, 249 .eh_device_reset_handler = qla2xxx_eh_device_reset, 250 .eh_target_reset_handler = qla2xxx_eh_target_reset, 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 252 .eh_host_reset_handler = qla2xxx_eh_host_reset, 253 254 .slave_configure = qla2xxx_slave_configure, 255 256 .slave_alloc = qla2xxx_slave_alloc, 257 .slave_destroy = qla2xxx_slave_destroy, 258 .scan_finished = qla2xxx_scan_finished, 259 .scan_start = qla2xxx_scan_start, 260 .change_queue_depth = scsi_change_queue_depth, 261 .this_id = -1, 262 .cmd_per_lun = 3, 263 .use_clustering = ENABLE_CLUSTERING, 264 .sg_tablesize = SG_ALL, 265 266 .max_sectors = 0xFFFF, 267 .shost_attrs = qla2x00_host_attrs, 268 269 .supported_mode = MODE_INITIATOR, 270 .use_blk_tags = 1, 271 .track_queue_depth = 1, 272 }; 273 274 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 275 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 276 277 /* TODO Convert to inlines 278 * 279 * Timer routines 280 */ 281 282 __inline__ void 283 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 284 { 285 init_timer(&vha->timer); 286 vha->timer.expires = jiffies + interval * HZ; 287 vha->timer.data = (unsigned long)vha; 288 vha->timer.function = (void (*)(unsigned long))func; 289 add_timer(&vha->timer); 290 vha->timer_active = 1; 291 } 292 293 static inline void 294 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 295 { 296 /* Currently used for 82XX only. */ 297 if (vha->device_flags & DFLG_DEV_FAILED) { 298 ql_dbg(ql_dbg_timer, vha, 0x600d, 299 "Device in a failed state, returning.\n"); 300 return; 301 } 302 303 mod_timer(&vha->timer, jiffies + interval * HZ); 304 } 305 306 static __inline__ void 307 qla2x00_stop_timer(scsi_qla_host_t *vha) 308 { 309 del_timer_sync(&vha->timer); 310 vha->timer_active = 0; 311 } 312 313 static int qla2x00_do_dpc(void *data); 314 315 static void qla2x00_rst_aen(scsi_qla_host_t *); 316 317 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 318 struct req_que **, struct rsp_que **); 319 static void qla2x00_free_fw_dump(struct qla_hw_data *); 320 static void qla2x00_mem_free(struct qla_hw_data *); 321 322 /* -------------------------------------------------------------------------- */ 323 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 324 struct rsp_que *rsp) 325 { 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 328 GFP_KERNEL); 329 if (!ha->req_q_map) { 330 ql_log(ql_log_fatal, vha, 0x003b, 331 "Unable to allocate memory for request queue ptrs.\n"); 332 goto fail_req_map; 333 } 334 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 336 GFP_KERNEL); 337 if (!ha->rsp_q_map) { 338 ql_log(ql_log_fatal, vha, 0x003c, 339 "Unable to allocate memory for response queue ptrs.\n"); 340 goto fail_rsp_map; 341 } 342 /* 343 * Make sure we record at least the request and response queue zero in 344 * case we need to free them if part of the probe fails. 345 */ 346 ha->rsp_q_map[0] = rsp; 347 ha->req_q_map[0] = req; 348 set_bit(0, ha->rsp_qid_map); 349 set_bit(0, ha->req_qid_map); 350 return 1; 351 352 fail_rsp_map: 353 kfree(ha->req_q_map); 354 ha->req_q_map = NULL; 355 fail_req_map: 356 return -ENOMEM; 357 } 358 359 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 360 { 361 if (IS_QLAFX00(ha)) { 362 if (req && req->ring_fx00) 363 dma_free_coherent(&ha->pdev->dev, 364 (req->length_fx00 + 1) * sizeof(request_t), 365 req->ring_fx00, req->dma_fx00); 366 } else if (req && req->ring) 367 dma_free_coherent(&ha->pdev->dev, 368 (req->length + 1) * sizeof(request_t), 369 req->ring, req->dma); 370 371 if (req) 372 kfree(req->outstanding_cmds); 373 374 kfree(req); 375 req = NULL; 376 } 377 378 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 379 { 380 if (IS_QLAFX00(ha)) { 381 if (rsp && rsp->ring) 382 dma_free_coherent(&ha->pdev->dev, 383 (rsp->length_fx00 + 1) * sizeof(request_t), 384 rsp->ring_fx00, rsp->dma_fx00); 385 } else if (rsp && rsp->ring) { 386 dma_free_coherent(&ha->pdev->dev, 387 (rsp->length + 1) * sizeof(response_t), 388 rsp->ring, rsp->dma); 389 } 390 kfree(rsp); 391 rsp = NULL; 392 } 393 394 static void qla2x00_free_queues(struct qla_hw_data *ha) 395 { 396 struct req_que *req; 397 struct rsp_que *rsp; 398 int cnt; 399 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 401 req = ha->req_q_map[cnt]; 402 qla2x00_free_req_que(ha, req); 403 } 404 kfree(ha->req_q_map); 405 ha->req_q_map = NULL; 406 407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 408 rsp = ha->rsp_q_map[cnt]; 409 qla2x00_free_rsp_que(ha, rsp); 410 } 411 kfree(ha->rsp_q_map); 412 ha->rsp_q_map = NULL; 413 } 414 415 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 416 { 417 uint16_t options = 0; 418 int ques, req, ret; 419 struct qla_hw_data *ha = vha->hw; 420 421 if (!(ha->fw_attributes & BIT_6)) { 422 ql_log(ql_log_warn, vha, 0x00d8, 423 "Firmware is not multi-queue capable.\n"); 424 goto fail; 425 } 426 if (ql2xmultique_tag) { 427 /* create a request queue for IO */ 428 options |= BIT_7; 429 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 430 QLA_DEFAULT_QUE_QOS); 431 if (!req) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to create request queue.\n"); 434 goto fail; 435 } 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 437 vha->req = ha->req_q_map[req]; 438 options |= BIT_1; 439 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 441 if (!ret) { 442 ql_log(ql_log_warn, vha, 0x00e8, 443 "Failed to create response queue.\n"); 444 goto fail2; 445 } 446 } 447 ha->flags.cpu_affinity_enabled = 1; 448 ql_dbg(ql_dbg_multiq, vha, 0xc007, 449 "CPU affinity mode enalbed, " 450 "no. of response queues:%d no. of request queues:%d.\n", 451 ha->max_rsp_queues, ha->max_req_queues); 452 ql_dbg(ql_dbg_init, vha, 0x00e9, 453 "CPU affinity mode enalbed, " 454 "no. of response queues:%d no. of request queues:%d.\n", 455 ha->max_rsp_queues, ha->max_req_queues); 456 } 457 return 0; 458 fail2: 459 qla25xx_delete_queues(vha); 460 destroy_workqueue(ha->wq); 461 ha->wq = NULL; 462 vha->req = ha->req_q_map[0]; 463 fail: 464 ha->mqenable = 0; 465 kfree(ha->req_q_map); 466 kfree(ha->rsp_q_map); 467 ha->max_req_queues = ha->max_rsp_queues = 1; 468 return 1; 469 } 470 471 static char * 472 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 473 { 474 struct qla_hw_data *ha = vha->hw; 475 static char *pci_bus_modes[] = { 476 "33", "66", "100", "133", 477 }; 478 uint16_t pci_bus; 479 480 strcpy(str, "PCI"); 481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 482 if (pci_bus) { 483 strcat(str, "-X ("); 484 strcat(str, pci_bus_modes[pci_bus]); 485 } else { 486 pci_bus = (ha->pci_attr & BIT_8) >> 8; 487 strcat(str, " ("); 488 strcat(str, pci_bus_modes[pci_bus]); 489 } 490 strcat(str, " MHz)"); 491 492 return (str); 493 } 494 495 static char * 496 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 497 { 498 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 499 struct qla_hw_data *ha = vha->hw; 500 uint32_t pci_bus; 501 502 if (pci_is_pcie(ha->pdev)) { 503 char lwstr[6]; 504 uint32_t lstat, lspeed, lwidth; 505 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 507 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 509 510 strcpy(str, "PCIe ("); 511 switch (lspeed) { 512 case 1: 513 strcat(str, "2.5GT/s "); 514 break; 515 case 2: 516 strcat(str, "5.0GT/s "); 517 break; 518 case 3: 519 strcat(str, "8.0GT/s "); 520 break; 521 default: 522 strcat(str, "<unknown> "); 523 break; 524 } 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 526 strcat(str, lwstr); 527 528 return str; 529 } 530 531 strcpy(str, "PCI"); 532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 533 if (pci_bus == 0 || pci_bus == 8) { 534 strcat(str, " ("); 535 strcat(str, pci_bus_modes[pci_bus >> 3]); 536 } else { 537 strcat(str, "-X "); 538 if (pci_bus & BIT_2) 539 strcat(str, "Mode 2"); 540 else 541 strcat(str, "Mode 1"); 542 strcat(str, " ("); 543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 544 } 545 strcat(str, " MHz)"); 546 547 return str; 548 } 549 550 static char * 551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 552 { 553 char un_str[10]; 554 struct qla_hw_data *ha = vha->hw; 555 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 557 ha->fw_minor_version, ha->fw_subminor_version); 558 559 if (ha->fw_attributes & BIT_9) { 560 strcat(str, "FLX"); 561 return (str); 562 } 563 564 switch (ha->fw_attributes & 0xFF) { 565 case 0x7: 566 strcat(str, "EF"); 567 break; 568 case 0x17: 569 strcat(str, "TP"); 570 break; 571 case 0x37: 572 strcat(str, "IP"); 573 break; 574 case 0x77: 575 strcat(str, "VI"); 576 break; 577 default: 578 sprintf(un_str, "(%x)", ha->fw_attributes); 579 strcat(str, un_str); 580 break; 581 } 582 if (ha->fw_attributes & 0x100) 583 strcat(str, "X"); 584 585 return (str); 586 } 587 588 static char * 589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 590 { 591 struct qla_hw_data *ha = vha->hw; 592 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 595 return str; 596 } 597 598 void 599 qla2x00_sp_free_dma(void *vha, void *ptr) 600 { 601 srb_t *sp = (srb_t *)ptr; 602 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 603 struct qla_hw_data *ha = sp->fcport->vha->hw; 604 void *ctx = GET_CMD_CTX_SP(sp); 605 606 if (sp->flags & SRB_DMA_VALID) { 607 scsi_dma_unmap(cmd); 608 sp->flags &= ~SRB_DMA_VALID; 609 } 610 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 613 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 615 } 616 617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 618 /* List assured to be having elements */ 619 qla2x00_clean_dsd_pool(ha, sp, NULL); 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 621 } 622 623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 624 dma_pool_free(ha->dl_dma_pool, ctx, 625 ((struct crc_context *)ctx)->crc_ctx_dma); 626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 627 } 628 629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 631 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 633 ctx1->fcp_cmnd_dma); 634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 637 mempool_free(ctx1, ha->ctx_mempool); 638 ctx1 = NULL; 639 } 640 641 CMD_SP(cmd) = NULL; 642 qla2x00_rel_sp(sp->fcport->vha, sp); 643 } 644 645 static void 646 qla2x00_sp_compl(void *data, void *ptr, int res) 647 { 648 struct qla_hw_data *ha = (struct qla_hw_data *)data; 649 srb_t *sp = (srb_t *)ptr; 650 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 651 652 cmd->result = res; 653 654 if (atomic_read(&sp->ref_count) == 0) { 655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 657 sp, GET_CMD_SP(sp)); 658 if (ql2xextended_error_logging & ql_dbg_io) 659 BUG(); 660 return; 661 } 662 if (!atomic_dec_and_test(&sp->ref_count)) 663 return; 664 665 qla2x00_sp_free_dma(ha, sp); 666 cmd->scsi_done(cmd); 667 } 668 669 /* If we are SP1 here, we need to still take and release the host_lock as SP1 670 * does not have the changes necessary to avoid taking host->host_lock. 671 */ 672 static int 673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 674 { 675 scsi_qla_host_t *vha = shost_priv(host); 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 678 struct qla_hw_data *ha = vha->hw; 679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 680 srb_t *sp; 681 int rval; 682 683 if (ha->flags.eeh_busy) { 684 if (ha->flags.pci_channel_io_perm_failure) { 685 ql_dbg(ql_dbg_aer, vha, 0x9010, 686 "PCI Channel IO permanent failure, exiting " 687 "cmd=%p.\n", cmd); 688 cmd->result = DID_NO_CONNECT << 16; 689 } else { 690 ql_dbg(ql_dbg_aer, vha, 0x9011, 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 692 cmd->result = DID_REQUEUE << 16; 693 } 694 goto qc24_fail_command; 695 } 696 697 rval = fc_remote_port_chkready(rport); 698 if (rval) { 699 cmd->result = rval; 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 702 cmd, rval); 703 goto qc24_fail_command; 704 } 705 706 if (!vha->flags.difdix_supported && 707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 708 ql_dbg(ql_dbg_io, vha, 0x3004, 709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 710 cmd); 711 cmd->result = DID_NO_CONNECT << 16; 712 goto qc24_fail_command; 713 } 714 715 if (!fcport) { 716 cmd->result = DID_NO_CONNECT << 16; 717 goto qc24_fail_command; 718 } 719 720 if (atomic_read(&fcport->state) != FCS_ONLINE) { 721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 723 ql_dbg(ql_dbg_io, vha, 0x3005, 724 "Returning DNC, fcport_state=%d loop_state=%d.\n", 725 atomic_read(&fcport->state), 726 atomic_read(&base_vha->loop_state)); 727 cmd->result = DID_NO_CONNECT << 16; 728 goto qc24_fail_command; 729 } 730 goto qc24_target_busy; 731 } 732 733 /* 734 * Return target busy if we've received a non-zero retry_delay_timer 735 * in a FCP_RSP. 736 */ 737 if (fcport->retry_delay_timestamp == 0) { 738 /* retry delay not set */ 739 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 740 fcport->retry_delay_timestamp = 0; 741 else 742 goto qc24_target_busy; 743 744 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 745 if (!sp) 746 goto qc24_host_busy; 747 748 sp->u.scmd.cmd = cmd; 749 sp->type = SRB_SCSI_CMD; 750 atomic_set(&sp->ref_count, 1); 751 CMD_SP(cmd) = (void *)sp; 752 sp->free = qla2x00_sp_free_dma; 753 sp->done = qla2x00_sp_compl; 754 755 rval = ha->isp_ops->start_scsi(sp); 756 if (rval != QLA_SUCCESS) { 757 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 758 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 759 goto qc24_host_busy_free_sp; 760 } 761 762 return 0; 763 764 qc24_host_busy_free_sp: 765 qla2x00_sp_free_dma(ha, sp); 766 767 qc24_host_busy: 768 return SCSI_MLQUEUE_HOST_BUSY; 769 770 qc24_target_busy: 771 return SCSI_MLQUEUE_TARGET_BUSY; 772 773 qc24_fail_command: 774 cmd->scsi_done(cmd); 775 776 return 0; 777 } 778 779 /* 780 * qla2x00_eh_wait_on_command 781 * Waits for the command to be returned by the Firmware for some 782 * max time. 783 * 784 * Input: 785 * cmd = Scsi Command to wait on. 786 * 787 * Return: 788 * Not Found : 0 789 * Found : 1 790 */ 791 static int 792 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 793 { 794 #define ABORT_POLLING_PERIOD 1000 795 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 796 unsigned long wait_iter = ABORT_WAIT_ITER; 797 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 798 struct qla_hw_data *ha = vha->hw; 799 int ret = QLA_SUCCESS; 800 801 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 802 ql_dbg(ql_dbg_taskm, vha, 0x8005, 803 "Return:eh_wait.\n"); 804 return ret; 805 } 806 807 while (CMD_SP(cmd) && wait_iter--) { 808 msleep(ABORT_POLLING_PERIOD); 809 } 810 if (CMD_SP(cmd)) 811 ret = QLA_FUNCTION_FAILED; 812 813 return ret; 814 } 815 816 /* 817 * qla2x00_wait_for_hba_online 818 * Wait till the HBA is online after going through 819 * <= MAX_RETRIES_OF_ISP_ABORT or 820 * finally HBA is disabled ie marked offline 821 * 822 * Input: 823 * ha - pointer to host adapter structure 824 * 825 * Note: 826 * Does context switching-Release SPIN_LOCK 827 * (if any) before calling this routine. 828 * 829 * Return: 830 * Success (Adapter is online) : 0 831 * Failed (Adapter is offline/disabled) : 1 832 */ 833 int 834 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 835 { 836 int return_status; 837 unsigned long wait_online; 838 struct qla_hw_data *ha = vha->hw; 839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 840 841 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 842 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 843 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 844 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 845 ha->dpc_active) && time_before(jiffies, wait_online)) { 846 847 msleep(1000); 848 } 849 if (base_vha->flags.online) 850 return_status = QLA_SUCCESS; 851 else 852 return_status = QLA_FUNCTION_FAILED; 853 854 return (return_status); 855 } 856 857 /* 858 * qla2x00_wait_for_hba_ready 859 * Wait till the HBA is ready before doing driver unload 860 * 861 * Input: 862 * ha - pointer to host adapter structure 863 * 864 * Note: 865 * Does context switching-Release SPIN_LOCK 866 * (if any) before calling this routine. 867 * 868 */ 869 static void 870 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 871 { 872 struct qla_hw_data *ha = vha->hw; 873 874 while (((qla2x00_reset_active(vha)) || ha->dpc_active || 875 ha->flags.mbox_busy) || 876 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 877 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) 878 msleep(1000); 879 } 880 881 int 882 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 883 { 884 int return_status; 885 unsigned long wait_reset; 886 struct qla_hw_data *ha = vha->hw; 887 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 888 889 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 890 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 891 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 892 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 893 ha->dpc_active) && time_before(jiffies, wait_reset)) { 894 895 msleep(1000); 896 897 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 898 ha->flags.chip_reset_done) 899 break; 900 } 901 if (ha->flags.chip_reset_done) 902 return_status = QLA_SUCCESS; 903 else 904 return_status = QLA_FUNCTION_FAILED; 905 906 return return_status; 907 } 908 909 static void 910 sp_get(struct srb *sp) 911 { 912 atomic_inc(&sp->ref_count); 913 } 914 915 /************************************************************************** 916 * qla2xxx_eh_abort 917 * 918 * Description: 919 * The abort function will abort the specified command. 920 * 921 * Input: 922 * cmd = Linux SCSI command packet to be aborted. 923 * 924 * Returns: 925 * Either SUCCESS or FAILED. 926 * 927 * Note: 928 * Only return FAILED if command not returned by firmware. 929 **************************************************************************/ 930 static int 931 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 932 { 933 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 934 srb_t *sp; 935 int ret; 936 unsigned int id; 937 uint64_t lun; 938 unsigned long flags; 939 int rval, wait = 0; 940 struct qla_hw_data *ha = vha->hw; 941 942 if (!CMD_SP(cmd)) 943 return SUCCESS; 944 945 ret = fc_block_scsi_eh(cmd); 946 if (ret != 0) 947 return ret; 948 ret = SUCCESS; 949 950 id = cmd->device->id; 951 lun = cmd->device->lun; 952 953 spin_lock_irqsave(&ha->hardware_lock, flags); 954 sp = (srb_t *) CMD_SP(cmd); 955 if (!sp) { 956 spin_unlock_irqrestore(&ha->hardware_lock, flags); 957 return SUCCESS; 958 } 959 960 ql_dbg(ql_dbg_taskm, vha, 0x8002, 961 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n", 962 vha->host_no, id, lun, sp, cmd); 963 964 /* Get a reference to the sp and drop the lock.*/ 965 sp_get(sp); 966 967 spin_unlock_irqrestore(&ha->hardware_lock, flags); 968 rval = ha->isp_ops->abort_command(sp); 969 if (rval) { 970 if (rval == QLA_FUNCTION_PARAMETER_ERROR) { 971 /* 972 * Decrement the ref_count since we can't find the 973 * command 974 */ 975 atomic_dec(&sp->ref_count); 976 ret = SUCCESS; 977 } else 978 ret = FAILED; 979 980 ql_dbg(ql_dbg_taskm, vha, 0x8003, 981 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 982 } else { 983 ql_dbg(ql_dbg_taskm, vha, 0x8004, 984 "Abort command mbx success cmd=%p.\n", cmd); 985 wait = 1; 986 } 987 988 spin_lock_irqsave(&ha->hardware_lock, flags); 989 /* 990 * Clear the slot in the oustanding_cmds array if we can't find the 991 * command to reclaim the resources. 992 */ 993 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 994 vha->req->outstanding_cmds[sp->handle] = NULL; 995 sp->done(ha, sp, 0); 996 spin_unlock_irqrestore(&ha->hardware_lock, flags); 997 998 /* Did the command return during mailbox execution? */ 999 if (ret == FAILED && !CMD_SP(cmd)) 1000 ret = SUCCESS; 1001 1002 /* Wait for the command to be returned. */ 1003 if (wait) { 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1005 ql_log(ql_log_warn, vha, 0x8006, 1006 "Abort handler timed out cmd=%p.\n", cmd); 1007 ret = FAILED; 1008 } 1009 } 1010 1011 ql_log(ql_log_info, vha, 0x801c, 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1013 vha->host_no, id, lun, wait, ret); 1014 1015 return ret; 1016 } 1017 1018 int 1019 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1020 uint64_t l, enum nexus_wait_type type) 1021 { 1022 int cnt, match, status; 1023 unsigned long flags; 1024 struct qla_hw_data *ha = vha->hw; 1025 struct req_que *req; 1026 srb_t *sp; 1027 struct scsi_cmnd *cmd; 1028 1029 status = QLA_SUCCESS; 1030 1031 spin_lock_irqsave(&ha->hardware_lock, flags); 1032 req = vha->req; 1033 for (cnt = 1; status == QLA_SUCCESS && 1034 cnt < req->num_outstanding_cmds; cnt++) { 1035 sp = req->outstanding_cmds[cnt]; 1036 if (!sp) 1037 continue; 1038 if (sp->type != SRB_SCSI_CMD) 1039 continue; 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1041 continue; 1042 match = 0; 1043 cmd = GET_CMD_SP(sp); 1044 switch (type) { 1045 case WAIT_HOST: 1046 match = 1; 1047 break; 1048 case WAIT_TARGET: 1049 match = cmd->device->id == t; 1050 break; 1051 case WAIT_LUN: 1052 match = (cmd->device->id == t && 1053 cmd->device->lun == l); 1054 break; 1055 } 1056 if (!match) 1057 continue; 1058 1059 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1060 status = qla2x00_eh_wait_on_command(cmd); 1061 spin_lock_irqsave(&ha->hardware_lock, flags); 1062 } 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1064 1065 return status; 1066 } 1067 1068 static char *reset_errors[] = { 1069 "HBA not online", 1070 "HBA not ready", 1071 "Task management failed", 1072 "Waiting for command completions", 1073 }; 1074 1075 static int 1076 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1078 { 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1081 int err; 1082 1083 if (!fcport) { 1084 return FAILED; 1085 } 1086 1087 err = fc_block_scsi_eh(cmd); 1088 if (err != 0) 1089 return err; 1090 1091 ql_log(ql_log_info, vha, 0x8009, 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1093 cmd->device->id, cmd->device->lun, cmd); 1094 1095 err = 0; 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1097 ql_log(ql_log_warn, vha, 0x800a, 1098 "Wait for hba online failed for cmd=%p.\n", cmd); 1099 goto eh_reset_failed; 1100 } 1101 err = 2; 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1103 != QLA_SUCCESS) { 1104 ql_log(ql_log_warn, vha, 0x800c, 1105 "do_reset failed for cmd=%p.\n", cmd); 1106 goto eh_reset_failed; 1107 } 1108 err = 3; 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1110 cmd->device->lun, type) != QLA_SUCCESS) { 1111 ql_log(ql_log_warn, vha, 0x800d, 1112 "wait for pending cmds failed for cmd=%p.\n", cmd); 1113 goto eh_reset_failed; 1114 } 1115 1116 ql_log(ql_log_info, vha, 0x800e, 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1119 1120 return SUCCESS; 1121 1122 eh_reset_failed: 1123 ql_log(ql_log_info, vha, 0x800f, 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1126 cmd); 1127 return FAILED; 1128 } 1129 1130 static int 1131 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1132 { 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1134 struct qla_hw_data *ha = vha->hw; 1135 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1137 ha->isp_ops->lun_reset); 1138 } 1139 1140 static int 1141 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1142 { 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1144 struct qla_hw_data *ha = vha->hw; 1145 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1147 ha->isp_ops->target_reset); 1148 } 1149 1150 /************************************************************************** 1151 * qla2xxx_eh_bus_reset 1152 * 1153 * Description: 1154 * The bus reset function will reset the bus and abort any executing 1155 * commands. 1156 * 1157 * Input: 1158 * cmd = Linux SCSI command packet of the command that cause the 1159 * bus reset. 1160 * 1161 * Returns: 1162 * SUCCESS/FAILURE (defined as macro in scsi.h). 1163 * 1164 **************************************************************************/ 1165 static int 1166 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1167 { 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1170 int ret = FAILED; 1171 unsigned int id; 1172 uint64_t lun; 1173 1174 id = cmd->device->id; 1175 lun = cmd->device->lun; 1176 1177 if (!fcport) { 1178 return ret; 1179 } 1180 1181 ret = fc_block_scsi_eh(cmd); 1182 if (ret != 0) 1183 return ret; 1184 ret = FAILED; 1185 1186 ql_log(ql_log_info, vha, 0x8012, 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1188 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1190 ql_log(ql_log_fatal, vha, 0x8013, 1191 "Wait for hba online failed board disabled.\n"); 1192 goto eh_bus_reset_done; 1193 } 1194 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1196 ret = SUCCESS; 1197 1198 if (ret == FAILED) 1199 goto eh_bus_reset_done; 1200 1201 /* Flush outstanding commands. */ 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1203 QLA_SUCCESS) { 1204 ql_log(ql_log_warn, vha, 0x8014, 1205 "Wait for pending commands failed.\n"); 1206 ret = FAILED; 1207 } 1208 1209 eh_bus_reset_done: 1210 ql_log(ql_log_warn, vha, 0x802b, 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1213 1214 return ret; 1215 } 1216 1217 /************************************************************************** 1218 * qla2xxx_eh_host_reset 1219 * 1220 * Description: 1221 * The reset function will reset the Adapter. 1222 * 1223 * Input: 1224 * cmd = Linux SCSI command packet of the command that cause the 1225 * adapter reset. 1226 * 1227 * Returns: 1228 * Either SUCCESS or FAILED. 1229 * 1230 * Note: 1231 **************************************************************************/ 1232 static int 1233 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1234 { 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1236 struct qla_hw_data *ha = vha->hw; 1237 int ret = FAILED; 1238 unsigned int id; 1239 uint64_t lun; 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1241 1242 id = cmd->device->id; 1243 lun = cmd->device->lun; 1244 1245 ql_log(ql_log_info, vha, 0x8018, 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1247 1248 /* 1249 * No point in issuing another reset if one is active. Also do not 1250 * attempt a reset if we are updating flash. 1251 */ 1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1253 goto eh_host_reset_lock; 1254 1255 if (vha != base_vha) { 1256 if (qla2x00_vp_abort_isp(vha)) 1257 goto eh_host_reset_lock; 1258 } else { 1259 if (IS_P3P_TYPE(vha->hw)) { 1260 if (!qla82xx_fcoe_ctx_reset(vha)) { 1261 /* Ctx reset success */ 1262 ret = SUCCESS; 1263 goto eh_host_reset_lock; 1264 } 1265 /* fall thru if ctx reset failed */ 1266 } 1267 if (ha->wq) 1268 flush_workqueue(ha->wq); 1269 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1271 if (ha->isp_ops->abort_isp(base_vha)) { 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1273 /* failed. schedule dpc to try */ 1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1275 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1277 ql_log(ql_log_warn, vha, 0x802a, 1278 "wait for hba online failed.\n"); 1279 goto eh_host_reset_lock; 1280 } 1281 } 1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1283 } 1284 1285 /* Waiting for command to be returned to OS.*/ 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1287 QLA_SUCCESS) 1288 ret = SUCCESS; 1289 1290 eh_host_reset_lock: 1291 ql_log(ql_log_info, vha, 0x8017, 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1294 1295 return ret; 1296 } 1297 1298 /* 1299 * qla2x00_loop_reset 1300 * Issue loop reset. 1301 * 1302 * Input: 1303 * ha = adapter block pointer. 1304 * 1305 * Returns: 1306 * 0 = success 1307 */ 1308 int 1309 qla2x00_loop_reset(scsi_qla_host_t *vha) 1310 { 1311 int ret; 1312 struct fc_port *fcport; 1313 struct qla_hw_data *ha = vha->hw; 1314 1315 if (IS_QLAFX00(ha)) { 1316 return qlafx00_loop_reset(vha); 1317 } 1318 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1321 if (fcport->port_type != FCT_TARGET) 1322 continue; 1323 1324 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1325 if (ret != QLA_SUCCESS) { 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1327 "Bus Reset failed: Reset=%d " 1328 "d_id=%x.\n", ret, fcport->d_id.b24); 1329 } 1330 } 1331 } 1332 1333 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1335 atomic_set(&vha->loop_state, LOOP_DOWN); 1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1337 qla2x00_mark_all_devices_lost(vha, 0); 1338 ret = qla2x00_full_login_lip(vha); 1339 if (ret != QLA_SUCCESS) { 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1341 "full_login_lip=%d.\n", ret); 1342 } 1343 } 1344 1345 if (ha->flags.enable_lip_reset) { 1346 ret = qla2x00_lip_reset(vha); 1347 if (ret != QLA_SUCCESS) 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1349 "lip_reset failed (%d).\n", ret); 1350 } 1351 1352 /* Issue marker command only when we are going to start the I/O */ 1353 vha->marker_needed = 1; 1354 1355 return QLA_SUCCESS; 1356 } 1357 1358 void 1359 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1360 { 1361 int que, cnt; 1362 unsigned long flags; 1363 srb_t *sp; 1364 struct qla_hw_data *ha = vha->hw; 1365 struct req_que *req; 1366 1367 qlt_host_reset_handler(ha); 1368 1369 spin_lock_irqsave(&ha->hardware_lock, flags); 1370 for (que = 0; que < ha->max_req_queues; que++) { 1371 req = ha->req_q_map[que]; 1372 if (!req) 1373 continue; 1374 if (!req->outstanding_cmds) 1375 continue; 1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1377 sp = req->outstanding_cmds[cnt]; 1378 if (sp) { 1379 req->outstanding_cmds[cnt] = NULL; 1380 sp->done(vha, sp, res); 1381 } 1382 } 1383 } 1384 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1385 } 1386 1387 static int 1388 qla2xxx_slave_alloc(struct scsi_device *sdev) 1389 { 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1391 1392 if (!rport || fc_remote_port_chkready(rport)) 1393 return -ENXIO; 1394 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1396 1397 return 0; 1398 } 1399 1400 static int 1401 qla2xxx_slave_configure(struct scsi_device *sdev) 1402 { 1403 scsi_qla_host_t *vha = shost_priv(sdev->host); 1404 struct req_que *req = vha->req; 1405 1406 if (IS_T10_PI_CAPABLE(vha->hw)) 1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1408 1409 scsi_change_queue_depth(sdev, req->max_q_depth); 1410 return 0; 1411 } 1412 1413 static void 1414 qla2xxx_slave_destroy(struct scsi_device *sdev) 1415 { 1416 sdev->hostdata = NULL; 1417 } 1418 1419 /** 1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1421 * @ha: HA context 1422 * 1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1424 * supported addressing method. 1425 */ 1426 static void 1427 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1428 { 1429 /* Assume a 32bit DMA mask. */ 1430 ha->flags.enable_64bit_addressing = 0; 1431 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1433 /* Any upper-dword bits set? */ 1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1436 /* Ok, a 64bit DMA mask is applicable. */ 1437 ha->flags.enable_64bit_addressing = 1; 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1440 return; 1441 } 1442 } 1443 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1446 } 1447 1448 static void 1449 qla2x00_enable_intrs(struct qla_hw_data *ha) 1450 { 1451 unsigned long flags = 0; 1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1453 1454 spin_lock_irqsave(&ha->hardware_lock, flags); 1455 ha->interrupts_on = 1; 1456 /* enable risc and host interrupts */ 1457 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1458 RD_REG_WORD(®->ictrl); 1459 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1460 1461 } 1462 1463 static void 1464 qla2x00_disable_intrs(struct qla_hw_data *ha) 1465 { 1466 unsigned long flags = 0; 1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1468 1469 spin_lock_irqsave(&ha->hardware_lock, flags); 1470 ha->interrupts_on = 0; 1471 /* disable risc and host interrupts */ 1472 WRT_REG_WORD(®->ictrl, 0); 1473 RD_REG_WORD(®->ictrl); 1474 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1475 } 1476 1477 static void 1478 qla24xx_enable_intrs(struct qla_hw_data *ha) 1479 { 1480 unsigned long flags = 0; 1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1482 1483 spin_lock_irqsave(&ha->hardware_lock, flags); 1484 ha->interrupts_on = 1; 1485 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1486 RD_REG_DWORD(®->ictrl); 1487 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1488 } 1489 1490 static void 1491 qla24xx_disable_intrs(struct qla_hw_data *ha) 1492 { 1493 unsigned long flags = 0; 1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1495 1496 if (IS_NOPOLLING_TYPE(ha)) 1497 return; 1498 spin_lock_irqsave(&ha->hardware_lock, flags); 1499 ha->interrupts_on = 0; 1500 WRT_REG_DWORD(®->ictrl, 0); 1501 RD_REG_DWORD(®->ictrl); 1502 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1503 } 1504 1505 static int 1506 qla2x00_iospace_config(struct qla_hw_data *ha) 1507 { 1508 resource_size_t pio; 1509 uint16_t msix; 1510 int cpus; 1511 1512 if (pci_request_selected_regions(ha->pdev, ha->bars, 1513 QLA2XXX_DRIVER_NAME)) { 1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1516 pci_name(ha->pdev)); 1517 goto iospace_error_exit; 1518 } 1519 if (!(ha->bars & 1)) 1520 goto skip_pio; 1521 1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1523 pio = pci_resource_start(ha->pdev, 0); 1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1527 "Invalid pci I/O region size (%s).\n", 1528 pci_name(ha->pdev)); 1529 pio = 0; 1530 } 1531 } else { 1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1533 "Region #0 no a PIO resource (%s).\n", 1534 pci_name(ha->pdev)); 1535 pio = 0; 1536 } 1537 ha->pio_address = pio; 1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1539 "PIO address=%llu.\n", 1540 (unsigned long long)ha->pio_address); 1541 1542 skip_pio: 1543 /* Use MMIO operations for all accesses. */ 1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1546 "Region #1 not an MMIO resource (%s), aborting.\n", 1547 pci_name(ha->pdev)); 1548 goto iospace_error_exit; 1549 } 1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1552 "Invalid PCI mem region size (%s), aborting.\n", 1553 pci_name(ha->pdev)); 1554 goto iospace_error_exit; 1555 } 1556 1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1558 if (!ha->iobase) { 1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1560 "Cannot remap MMIO (%s), aborting.\n", 1561 pci_name(ha->pdev)); 1562 goto iospace_error_exit; 1563 } 1564 1565 /* Determine queue resources */ 1566 ha->max_req_queues = ha->max_rsp_queues = 1; 1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1570 goto mqiobase_exit; 1571 1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1573 pci_resource_len(ha->pdev, 3)); 1574 if (ha->mqiobase) { 1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1576 "MQIO Base=%p.\n", ha->mqiobase); 1577 /* Read MSIX vector size of the board */ 1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1579 ha->msix_count = msix; 1580 /* Max queues are bounded by available msix vectors */ 1581 /* queue 0 uses two msix vectors */ 1582 if (ql2xmultique_tag) { 1583 cpus = num_online_cpus(); 1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1585 (cpus + 1) : (ha->msix_count - 1); 1586 ha->max_req_queues = 2; 1587 } else if (ql2xmaxqueues > 1) { 1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1589 QLA_MQ_SIZE : ql2xmaxqueues; 1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1591 "QoS mode set, max no of request queues:%d.\n", 1592 ha->max_req_queues); 1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1594 "QoS mode set, max no of request queues:%d.\n", 1595 ha->max_req_queues); 1596 } 1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1598 "MSI-X vector count: %d.\n", msix); 1599 } else 1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1601 "BAR 3 not enabled.\n"); 1602 1603 mqiobase_exit: 1604 ha->msix_count = ha->max_rsp_queues + 1; 1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1606 "MSIX Count:%d.\n", ha->msix_count); 1607 return (0); 1608 1609 iospace_error_exit: 1610 return (-ENOMEM); 1611 } 1612 1613 1614 static int 1615 qla83xx_iospace_config(struct qla_hw_data *ha) 1616 { 1617 uint16_t msix; 1618 int cpus; 1619 1620 if (pci_request_selected_regions(ha->pdev, ha->bars, 1621 QLA2XXX_DRIVER_NAME)) { 1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1624 pci_name(ha->pdev)); 1625 1626 goto iospace_error_exit; 1627 } 1628 1629 /* Use MMIO operations for all accesses. */ 1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1632 "Invalid pci I/O region size (%s).\n", 1633 pci_name(ha->pdev)); 1634 goto iospace_error_exit; 1635 } 1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1638 "Invalid PCI mem region size (%s), aborting\n", 1639 pci_name(ha->pdev)); 1640 goto iospace_error_exit; 1641 } 1642 1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1644 if (!ha->iobase) { 1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1646 "Cannot remap MMIO (%s), aborting.\n", 1647 pci_name(ha->pdev)); 1648 goto iospace_error_exit; 1649 } 1650 1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1652 /* 83XX 26XX always use MQ type access for queues 1653 * - mbar 2, a.k.a region 4 */ 1654 ha->max_req_queues = ha->max_rsp_queues = 1; 1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1656 pci_resource_len(ha->pdev, 4)); 1657 1658 if (!ha->mqiobase) { 1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1660 "BAR2/region4 not enabled\n"); 1661 goto mqiobase_exit; 1662 } 1663 1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1665 pci_resource_len(ha->pdev, 2)); 1666 if (ha->msixbase) { 1667 /* Read MSIX vector size of the board */ 1668 pci_read_config_word(ha->pdev, 1669 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1670 ha->msix_count = msix; 1671 /* Max queues are bounded by available msix vectors */ 1672 /* queue 0 uses two msix vectors */ 1673 if (ql2xmultique_tag) { 1674 cpus = num_online_cpus(); 1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1676 (cpus + 1) : (ha->msix_count - 1); 1677 ha->max_req_queues = 2; 1678 } else if (ql2xmaxqueues > 1) { 1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1680 QLA_MQ_SIZE : ql2xmaxqueues; 1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1682 "QoS mode set, max no of request queues:%d.\n", 1683 ha->max_req_queues); 1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1685 "QoS mode set, max no of request queues:%d.\n", 1686 ha->max_req_queues); 1687 } 1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1689 "MSI-X vector count: %d.\n", msix); 1690 } else 1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1692 "BAR 1 not enabled.\n"); 1693 1694 mqiobase_exit: 1695 ha->msix_count = ha->max_rsp_queues + 1; 1696 1697 qlt_83xx_iospace_config(ha); 1698 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1700 "MSIX Count:%d.\n", ha->msix_count); 1701 return 0; 1702 1703 iospace_error_exit: 1704 return -ENOMEM; 1705 } 1706 1707 static struct isp_operations qla2100_isp_ops = { 1708 .pci_config = qla2100_pci_config, 1709 .reset_chip = qla2x00_reset_chip, 1710 .chip_diag = qla2x00_chip_diag, 1711 .config_rings = qla2x00_config_rings, 1712 .reset_adapter = qla2x00_reset_adapter, 1713 .nvram_config = qla2x00_nvram_config, 1714 .update_fw_options = qla2x00_update_fw_options, 1715 .load_risc = qla2x00_load_risc, 1716 .pci_info_str = qla2x00_pci_info_str, 1717 .fw_version_str = qla2x00_fw_version_str, 1718 .intr_handler = qla2100_intr_handler, 1719 .enable_intrs = qla2x00_enable_intrs, 1720 .disable_intrs = qla2x00_disable_intrs, 1721 .abort_command = qla2x00_abort_command, 1722 .target_reset = qla2x00_abort_target, 1723 .lun_reset = qla2x00_lun_reset, 1724 .fabric_login = qla2x00_login_fabric, 1725 .fabric_logout = qla2x00_fabric_logout, 1726 .calc_req_entries = qla2x00_calc_iocbs_32, 1727 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1728 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1730 .read_nvram = qla2x00_read_nvram_data, 1731 .write_nvram = qla2x00_write_nvram_data, 1732 .fw_dump = qla2100_fw_dump, 1733 .beacon_on = NULL, 1734 .beacon_off = NULL, 1735 .beacon_blink = NULL, 1736 .read_optrom = qla2x00_read_optrom_data, 1737 .write_optrom = qla2x00_write_optrom_data, 1738 .get_flash_version = qla2x00_get_flash_version, 1739 .start_scsi = qla2x00_start_scsi, 1740 .abort_isp = qla2x00_abort_isp, 1741 .iospace_config = qla2x00_iospace_config, 1742 .initialize_adapter = qla2x00_initialize_adapter, 1743 }; 1744 1745 static struct isp_operations qla2300_isp_ops = { 1746 .pci_config = qla2300_pci_config, 1747 .reset_chip = qla2x00_reset_chip, 1748 .chip_diag = qla2x00_chip_diag, 1749 .config_rings = qla2x00_config_rings, 1750 .reset_adapter = qla2x00_reset_adapter, 1751 .nvram_config = qla2x00_nvram_config, 1752 .update_fw_options = qla2x00_update_fw_options, 1753 .load_risc = qla2x00_load_risc, 1754 .pci_info_str = qla2x00_pci_info_str, 1755 .fw_version_str = qla2x00_fw_version_str, 1756 .intr_handler = qla2300_intr_handler, 1757 .enable_intrs = qla2x00_enable_intrs, 1758 .disable_intrs = qla2x00_disable_intrs, 1759 .abort_command = qla2x00_abort_command, 1760 .target_reset = qla2x00_abort_target, 1761 .lun_reset = qla2x00_lun_reset, 1762 .fabric_login = qla2x00_login_fabric, 1763 .fabric_logout = qla2x00_fabric_logout, 1764 .calc_req_entries = qla2x00_calc_iocbs_32, 1765 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1766 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1768 .read_nvram = qla2x00_read_nvram_data, 1769 .write_nvram = qla2x00_write_nvram_data, 1770 .fw_dump = qla2300_fw_dump, 1771 .beacon_on = qla2x00_beacon_on, 1772 .beacon_off = qla2x00_beacon_off, 1773 .beacon_blink = qla2x00_beacon_blink, 1774 .read_optrom = qla2x00_read_optrom_data, 1775 .write_optrom = qla2x00_write_optrom_data, 1776 .get_flash_version = qla2x00_get_flash_version, 1777 .start_scsi = qla2x00_start_scsi, 1778 .abort_isp = qla2x00_abort_isp, 1779 .iospace_config = qla2x00_iospace_config, 1780 .initialize_adapter = qla2x00_initialize_adapter, 1781 }; 1782 1783 static struct isp_operations qla24xx_isp_ops = { 1784 .pci_config = qla24xx_pci_config, 1785 .reset_chip = qla24xx_reset_chip, 1786 .chip_diag = qla24xx_chip_diag, 1787 .config_rings = qla24xx_config_rings, 1788 .reset_adapter = qla24xx_reset_adapter, 1789 .nvram_config = qla24xx_nvram_config, 1790 .update_fw_options = qla24xx_update_fw_options, 1791 .load_risc = qla24xx_load_risc, 1792 .pci_info_str = qla24xx_pci_info_str, 1793 .fw_version_str = qla24xx_fw_version_str, 1794 .intr_handler = qla24xx_intr_handler, 1795 .enable_intrs = qla24xx_enable_intrs, 1796 .disable_intrs = qla24xx_disable_intrs, 1797 .abort_command = qla24xx_abort_command, 1798 .target_reset = qla24xx_abort_target, 1799 .lun_reset = qla24xx_lun_reset, 1800 .fabric_login = qla24xx_login_fabric, 1801 .fabric_logout = qla24xx_fabric_logout, 1802 .calc_req_entries = NULL, 1803 .build_iocbs = NULL, 1804 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1806 .read_nvram = qla24xx_read_nvram_data, 1807 .write_nvram = qla24xx_write_nvram_data, 1808 .fw_dump = qla24xx_fw_dump, 1809 .beacon_on = qla24xx_beacon_on, 1810 .beacon_off = qla24xx_beacon_off, 1811 .beacon_blink = qla24xx_beacon_blink, 1812 .read_optrom = qla24xx_read_optrom_data, 1813 .write_optrom = qla24xx_write_optrom_data, 1814 .get_flash_version = qla24xx_get_flash_version, 1815 .start_scsi = qla24xx_start_scsi, 1816 .abort_isp = qla2x00_abort_isp, 1817 .iospace_config = qla2x00_iospace_config, 1818 .initialize_adapter = qla2x00_initialize_adapter, 1819 }; 1820 1821 static struct isp_operations qla25xx_isp_ops = { 1822 .pci_config = qla25xx_pci_config, 1823 .reset_chip = qla24xx_reset_chip, 1824 .chip_diag = qla24xx_chip_diag, 1825 .config_rings = qla24xx_config_rings, 1826 .reset_adapter = qla24xx_reset_adapter, 1827 .nvram_config = qla24xx_nvram_config, 1828 .update_fw_options = qla24xx_update_fw_options, 1829 .load_risc = qla24xx_load_risc, 1830 .pci_info_str = qla24xx_pci_info_str, 1831 .fw_version_str = qla24xx_fw_version_str, 1832 .intr_handler = qla24xx_intr_handler, 1833 .enable_intrs = qla24xx_enable_intrs, 1834 .disable_intrs = qla24xx_disable_intrs, 1835 .abort_command = qla24xx_abort_command, 1836 .target_reset = qla24xx_abort_target, 1837 .lun_reset = qla24xx_lun_reset, 1838 .fabric_login = qla24xx_login_fabric, 1839 .fabric_logout = qla24xx_fabric_logout, 1840 .calc_req_entries = NULL, 1841 .build_iocbs = NULL, 1842 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1844 .read_nvram = qla25xx_read_nvram_data, 1845 .write_nvram = qla25xx_write_nvram_data, 1846 .fw_dump = qla25xx_fw_dump, 1847 .beacon_on = qla24xx_beacon_on, 1848 .beacon_off = qla24xx_beacon_off, 1849 .beacon_blink = qla24xx_beacon_blink, 1850 .read_optrom = qla25xx_read_optrom_data, 1851 .write_optrom = qla24xx_write_optrom_data, 1852 .get_flash_version = qla24xx_get_flash_version, 1853 .start_scsi = qla24xx_dif_start_scsi, 1854 .abort_isp = qla2x00_abort_isp, 1855 .iospace_config = qla2x00_iospace_config, 1856 .initialize_adapter = qla2x00_initialize_adapter, 1857 }; 1858 1859 static struct isp_operations qla81xx_isp_ops = { 1860 .pci_config = qla25xx_pci_config, 1861 .reset_chip = qla24xx_reset_chip, 1862 .chip_diag = qla24xx_chip_diag, 1863 .config_rings = qla24xx_config_rings, 1864 .reset_adapter = qla24xx_reset_adapter, 1865 .nvram_config = qla81xx_nvram_config, 1866 .update_fw_options = qla81xx_update_fw_options, 1867 .load_risc = qla81xx_load_risc, 1868 .pci_info_str = qla24xx_pci_info_str, 1869 .fw_version_str = qla24xx_fw_version_str, 1870 .intr_handler = qla24xx_intr_handler, 1871 .enable_intrs = qla24xx_enable_intrs, 1872 .disable_intrs = qla24xx_disable_intrs, 1873 .abort_command = qla24xx_abort_command, 1874 .target_reset = qla24xx_abort_target, 1875 .lun_reset = qla24xx_lun_reset, 1876 .fabric_login = qla24xx_login_fabric, 1877 .fabric_logout = qla24xx_fabric_logout, 1878 .calc_req_entries = NULL, 1879 .build_iocbs = NULL, 1880 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1882 .read_nvram = NULL, 1883 .write_nvram = NULL, 1884 .fw_dump = qla81xx_fw_dump, 1885 .beacon_on = qla24xx_beacon_on, 1886 .beacon_off = qla24xx_beacon_off, 1887 .beacon_blink = qla83xx_beacon_blink, 1888 .read_optrom = qla25xx_read_optrom_data, 1889 .write_optrom = qla24xx_write_optrom_data, 1890 .get_flash_version = qla24xx_get_flash_version, 1891 .start_scsi = qla24xx_dif_start_scsi, 1892 .abort_isp = qla2x00_abort_isp, 1893 .iospace_config = qla2x00_iospace_config, 1894 .initialize_adapter = qla2x00_initialize_adapter, 1895 }; 1896 1897 static struct isp_operations qla82xx_isp_ops = { 1898 .pci_config = qla82xx_pci_config, 1899 .reset_chip = qla82xx_reset_chip, 1900 .chip_diag = qla24xx_chip_diag, 1901 .config_rings = qla82xx_config_rings, 1902 .reset_adapter = qla24xx_reset_adapter, 1903 .nvram_config = qla81xx_nvram_config, 1904 .update_fw_options = qla24xx_update_fw_options, 1905 .load_risc = qla82xx_load_risc, 1906 .pci_info_str = qla24xx_pci_info_str, 1907 .fw_version_str = qla24xx_fw_version_str, 1908 .intr_handler = qla82xx_intr_handler, 1909 .enable_intrs = qla82xx_enable_intrs, 1910 .disable_intrs = qla82xx_disable_intrs, 1911 .abort_command = qla24xx_abort_command, 1912 .target_reset = qla24xx_abort_target, 1913 .lun_reset = qla24xx_lun_reset, 1914 .fabric_login = qla24xx_login_fabric, 1915 .fabric_logout = qla24xx_fabric_logout, 1916 .calc_req_entries = NULL, 1917 .build_iocbs = NULL, 1918 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1920 .read_nvram = qla24xx_read_nvram_data, 1921 .write_nvram = qla24xx_write_nvram_data, 1922 .fw_dump = qla82xx_fw_dump, 1923 .beacon_on = qla82xx_beacon_on, 1924 .beacon_off = qla82xx_beacon_off, 1925 .beacon_blink = NULL, 1926 .read_optrom = qla82xx_read_optrom_data, 1927 .write_optrom = qla82xx_write_optrom_data, 1928 .get_flash_version = qla82xx_get_flash_version, 1929 .start_scsi = qla82xx_start_scsi, 1930 .abort_isp = qla82xx_abort_isp, 1931 .iospace_config = qla82xx_iospace_config, 1932 .initialize_adapter = qla2x00_initialize_adapter, 1933 }; 1934 1935 static struct isp_operations qla8044_isp_ops = { 1936 .pci_config = qla82xx_pci_config, 1937 .reset_chip = qla82xx_reset_chip, 1938 .chip_diag = qla24xx_chip_diag, 1939 .config_rings = qla82xx_config_rings, 1940 .reset_adapter = qla24xx_reset_adapter, 1941 .nvram_config = qla81xx_nvram_config, 1942 .update_fw_options = qla24xx_update_fw_options, 1943 .load_risc = qla82xx_load_risc, 1944 .pci_info_str = qla24xx_pci_info_str, 1945 .fw_version_str = qla24xx_fw_version_str, 1946 .intr_handler = qla8044_intr_handler, 1947 .enable_intrs = qla82xx_enable_intrs, 1948 .disable_intrs = qla82xx_disable_intrs, 1949 .abort_command = qla24xx_abort_command, 1950 .target_reset = qla24xx_abort_target, 1951 .lun_reset = qla24xx_lun_reset, 1952 .fabric_login = qla24xx_login_fabric, 1953 .fabric_logout = qla24xx_fabric_logout, 1954 .calc_req_entries = NULL, 1955 .build_iocbs = NULL, 1956 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1958 .read_nvram = NULL, 1959 .write_nvram = NULL, 1960 .fw_dump = qla8044_fw_dump, 1961 .beacon_on = qla82xx_beacon_on, 1962 .beacon_off = qla82xx_beacon_off, 1963 .beacon_blink = NULL, 1964 .read_optrom = qla8044_read_optrom_data, 1965 .write_optrom = qla8044_write_optrom_data, 1966 .get_flash_version = qla82xx_get_flash_version, 1967 .start_scsi = qla82xx_start_scsi, 1968 .abort_isp = qla8044_abort_isp, 1969 .iospace_config = qla82xx_iospace_config, 1970 .initialize_adapter = qla2x00_initialize_adapter, 1971 }; 1972 1973 static struct isp_operations qla83xx_isp_ops = { 1974 .pci_config = qla25xx_pci_config, 1975 .reset_chip = qla24xx_reset_chip, 1976 .chip_diag = qla24xx_chip_diag, 1977 .config_rings = qla24xx_config_rings, 1978 .reset_adapter = qla24xx_reset_adapter, 1979 .nvram_config = qla81xx_nvram_config, 1980 .update_fw_options = qla81xx_update_fw_options, 1981 .load_risc = qla81xx_load_risc, 1982 .pci_info_str = qla24xx_pci_info_str, 1983 .fw_version_str = qla24xx_fw_version_str, 1984 .intr_handler = qla24xx_intr_handler, 1985 .enable_intrs = qla24xx_enable_intrs, 1986 .disable_intrs = qla24xx_disable_intrs, 1987 .abort_command = qla24xx_abort_command, 1988 .target_reset = qla24xx_abort_target, 1989 .lun_reset = qla24xx_lun_reset, 1990 .fabric_login = qla24xx_login_fabric, 1991 .fabric_logout = qla24xx_fabric_logout, 1992 .calc_req_entries = NULL, 1993 .build_iocbs = NULL, 1994 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1996 .read_nvram = NULL, 1997 .write_nvram = NULL, 1998 .fw_dump = qla83xx_fw_dump, 1999 .beacon_on = qla24xx_beacon_on, 2000 .beacon_off = qla24xx_beacon_off, 2001 .beacon_blink = qla83xx_beacon_blink, 2002 .read_optrom = qla25xx_read_optrom_data, 2003 .write_optrom = qla24xx_write_optrom_data, 2004 .get_flash_version = qla24xx_get_flash_version, 2005 .start_scsi = qla24xx_dif_start_scsi, 2006 .abort_isp = qla2x00_abort_isp, 2007 .iospace_config = qla83xx_iospace_config, 2008 .initialize_adapter = qla2x00_initialize_adapter, 2009 }; 2010 2011 static struct isp_operations qlafx00_isp_ops = { 2012 .pci_config = qlafx00_pci_config, 2013 .reset_chip = qlafx00_soft_reset, 2014 .chip_diag = qlafx00_chip_diag, 2015 .config_rings = qlafx00_config_rings, 2016 .reset_adapter = qlafx00_soft_reset, 2017 .nvram_config = NULL, 2018 .update_fw_options = NULL, 2019 .load_risc = NULL, 2020 .pci_info_str = qlafx00_pci_info_str, 2021 .fw_version_str = qlafx00_fw_version_str, 2022 .intr_handler = qlafx00_intr_handler, 2023 .enable_intrs = qlafx00_enable_intrs, 2024 .disable_intrs = qlafx00_disable_intrs, 2025 .abort_command = qla24xx_async_abort_command, 2026 .target_reset = qlafx00_abort_target, 2027 .lun_reset = qlafx00_lun_reset, 2028 .fabric_login = NULL, 2029 .fabric_logout = NULL, 2030 .calc_req_entries = NULL, 2031 .build_iocbs = NULL, 2032 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2034 .read_nvram = qla24xx_read_nvram_data, 2035 .write_nvram = qla24xx_write_nvram_data, 2036 .fw_dump = NULL, 2037 .beacon_on = qla24xx_beacon_on, 2038 .beacon_off = qla24xx_beacon_off, 2039 .beacon_blink = NULL, 2040 .read_optrom = qla24xx_read_optrom_data, 2041 .write_optrom = qla24xx_write_optrom_data, 2042 .get_flash_version = qla24xx_get_flash_version, 2043 .start_scsi = qlafx00_start_scsi, 2044 .abort_isp = qlafx00_abort_isp, 2045 .iospace_config = qlafx00_iospace_config, 2046 .initialize_adapter = qlafx00_initialize_adapter, 2047 }; 2048 2049 static struct isp_operations qla27xx_isp_ops = { 2050 .pci_config = qla25xx_pci_config, 2051 .reset_chip = qla24xx_reset_chip, 2052 .chip_diag = qla24xx_chip_diag, 2053 .config_rings = qla24xx_config_rings, 2054 .reset_adapter = qla24xx_reset_adapter, 2055 .nvram_config = qla81xx_nvram_config, 2056 .update_fw_options = qla81xx_update_fw_options, 2057 .load_risc = qla81xx_load_risc, 2058 .pci_info_str = qla24xx_pci_info_str, 2059 .fw_version_str = qla24xx_fw_version_str, 2060 .intr_handler = qla24xx_intr_handler, 2061 .enable_intrs = qla24xx_enable_intrs, 2062 .disable_intrs = qla24xx_disable_intrs, 2063 .abort_command = qla24xx_abort_command, 2064 .target_reset = qla24xx_abort_target, 2065 .lun_reset = qla24xx_lun_reset, 2066 .fabric_login = qla24xx_login_fabric, 2067 .fabric_logout = qla24xx_fabric_logout, 2068 .calc_req_entries = NULL, 2069 .build_iocbs = NULL, 2070 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2072 .read_nvram = NULL, 2073 .write_nvram = NULL, 2074 .fw_dump = qla27xx_fwdump, 2075 .beacon_on = qla24xx_beacon_on, 2076 .beacon_off = qla24xx_beacon_off, 2077 .beacon_blink = qla83xx_beacon_blink, 2078 .read_optrom = qla25xx_read_optrom_data, 2079 .write_optrom = qla24xx_write_optrom_data, 2080 .get_flash_version = qla24xx_get_flash_version, 2081 .start_scsi = qla24xx_dif_start_scsi, 2082 .abort_isp = qla2x00_abort_isp, 2083 .iospace_config = qla83xx_iospace_config, 2084 .initialize_adapter = qla2x00_initialize_adapter, 2085 }; 2086 2087 static inline void 2088 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2089 { 2090 ha->device_type = DT_EXTENDED_IDS; 2091 switch (ha->pdev->device) { 2092 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2093 ha->device_type |= DT_ISP2100; 2094 ha->device_type &= ~DT_EXTENDED_IDS; 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2096 break; 2097 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2098 ha->device_type |= DT_ISP2200; 2099 ha->device_type &= ~DT_EXTENDED_IDS; 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2101 break; 2102 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2103 ha->device_type |= DT_ISP2300; 2104 ha->device_type |= DT_ZIO_SUPPORTED; 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2106 break; 2107 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2108 ha->device_type |= DT_ISP2312; 2109 ha->device_type |= DT_ZIO_SUPPORTED; 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2111 break; 2112 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2113 ha->device_type |= DT_ISP2322; 2114 ha->device_type |= DT_ZIO_SUPPORTED; 2115 if (ha->pdev->subsystem_vendor == 0x1028 && 2116 ha->pdev->subsystem_device == 0x0170) 2117 ha->device_type |= DT_OEM_001; 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2119 break; 2120 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2121 ha->device_type |= DT_ISP6312; 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2123 break; 2124 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2125 ha->device_type |= DT_ISP6322; 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2127 break; 2128 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2129 ha->device_type |= DT_ISP2422; 2130 ha->device_type |= DT_ZIO_SUPPORTED; 2131 ha->device_type |= DT_FWI2; 2132 ha->device_type |= DT_IIDMA; 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2134 break; 2135 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2136 ha->device_type |= DT_ISP2432; 2137 ha->device_type |= DT_ZIO_SUPPORTED; 2138 ha->device_type |= DT_FWI2; 2139 ha->device_type |= DT_IIDMA; 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2141 break; 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2143 ha->device_type |= DT_ISP8432; 2144 ha->device_type |= DT_ZIO_SUPPORTED; 2145 ha->device_type |= DT_FWI2; 2146 ha->device_type |= DT_IIDMA; 2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2148 break; 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2150 ha->device_type |= DT_ISP5422; 2151 ha->device_type |= DT_FWI2; 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2153 break; 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2155 ha->device_type |= DT_ISP5432; 2156 ha->device_type |= DT_FWI2; 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2158 break; 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2160 ha->device_type |= DT_ISP2532; 2161 ha->device_type |= DT_ZIO_SUPPORTED; 2162 ha->device_type |= DT_FWI2; 2163 ha->device_type |= DT_IIDMA; 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2165 break; 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2167 ha->device_type |= DT_ISP8001; 2168 ha->device_type |= DT_ZIO_SUPPORTED; 2169 ha->device_type |= DT_FWI2; 2170 ha->device_type |= DT_IIDMA; 2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2172 break; 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2174 ha->device_type |= DT_ISP8021; 2175 ha->device_type |= DT_ZIO_SUPPORTED; 2176 ha->device_type |= DT_FWI2; 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2178 /* Initialize 82XX ISP flags */ 2179 qla82xx_init_flags(ha); 2180 break; 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2182 ha->device_type |= DT_ISP8044; 2183 ha->device_type |= DT_ZIO_SUPPORTED; 2184 ha->device_type |= DT_FWI2; 2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2186 /* Initialize 82XX ISP flags */ 2187 qla82xx_init_flags(ha); 2188 break; 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2190 ha->device_type |= DT_ISP2031; 2191 ha->device_type |= DT_ZIO_SUPPORTED; 2192 ha->device_type |= DT_FWI2; 2193 ha->device_type |= DT_IIDMA; 2194 ha->device_type |= DT_T10_PI; 2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2196 break; 2197 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2198 ha->device_type |= DT_ISP8031; 2199 ha->device_type |= DT_ZIO_SUPPORTED; 2200 ha->device_type |= DT_FWI2; 2201 ha->device_type |= DT_IIDMA; 2202 ha->device_type |= DT_T10_PI; 2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2204 break; 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2206 ha->device_type |= DT_ISPFX00; 2207 break; 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2209 ha->device_type |= DT_ISP2071; 2210 ha->device_type |= DT_ZIO_SUPPORTED; 2211 ha->device_type |= DT_FWI2; 2212 ha->device_type |= DT_IIDMA; 2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2214 break; 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2216 ha->device_type |= DT_ISP2271; 2217 ha->device_type |= DT_ZIO_SUPPORTED; 2218 ha->device_type |= DT_FWI2; 2219 ha->device_type |= DT_IIDMA; 2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2221 break; 2222 } 2223 2224 if (IS_QLA82XX(ha)) 2225 ha->port_no = ha->portnum & 1; 2226 else { 2227 /* Get adapter physical port no from interrupt pin register. */ 2228 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2229 if (IS_QLA27XX(ha)) 2230 ha->port_no--; 2231 else 2232 ha->port_no = !(ha->port_no & 1); 2233 } 2234 2235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2236 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2237 ha->device_type, ha->port_no, ha->fw_srisc_address); 2238 } 2239 2240 static void 2241 qla2xxx_scan_start(struct Scsi_Host *shost) 2242 { 2243 scsi_qla_host_t *vha = shost_priv(shost); 2244 2245 if (vha->hw->flags.running_gold_fw) 2246 return; 2247 2248 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2249 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2250 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2251 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2252 } 2253 2254 static int 2255 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2256 { 2257 scsi_qla_host_t *vha = shost_priv(shost); 2258 2259 if (!vha->host) 2260 return 1; 2261 if (time > vha->hw->loop_reset_delay * HZ) 2262 return 1; 2263 2264 return atomic_read(&vha->loop_state) == LOOP_READY; 2265 } 2266 2267 /* 2268 * PCI driver interface 2269 */ 2270 static int 2271 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2272 { 2273 int ret = -ENODEV; 2274 struct Scsi_Host *host; 2275 scsi_qla_host_t *base_vha = NULL; 2276 struct qla_hw_data *ha; 2277 char pci_info[30]; 2278 char fw_str[30], wq_name[30]; 2279 struct scsi_host_template *sht; 2280 int bars, mem_only = 0; 2281 uint16_t req_length = 0, rsp_length = 0; 2282 struct req_que *req = NULL; 2283 struct rsp_que *rsp = NULL; 2284 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2285 sht = &qla2xxx_driver_template; 2286 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) { 2300 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2301 mem_only = 1; 2302 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2303 "Mem only adapter.\n"); 2304 } 2305 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2306 "Bars=%d.\n", bars); 2307 2308 if (mem_only) { 2309 if (pci_enable_device_mem(pdev)) 2310 goto probe_out; 2311 } else { 2312 if (pci_enable_device(pdev)) 2313 goto probe_out; 2314 } 2315 2316 /* This may fail but that's ok */ 2317 pci_enable_pcie_error_reporting(pdev); 2318 2319 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2320 if (!ha) { 2321 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2322 "Unable to allocate memory for ha.\n"); 2323 goto probe_out; 2324 } 2325 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2326 "Memory allocated for ha=%p.\n", ha); 2327 ha->pdev = pdev; 2328 ha->tgt.enable_class_2 = ql2xenableclass2; 2329 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2330 spin_lock_init(&ha->tgt.q_full_lock); 2331 2332 /* Clear our data area */ 2333 ha->bars = bars; 2334 ha->mem_only = mem_only; 2335 spin_lock_init(&ha->hardware_lock); 2336 spin_lock_init(&ha->vport_slock); 2337 mutex_init(&ha->selflogin_lock); 2338 mutex_init(&ha->optrom_mutex); 2339 2340 /* Set ISP-type information. */ 2341 qla2x00_set_isp_flags(ha); 2342 2343 /* Set EEH reset type to fundamental if required by hba */ 2344 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2345 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2346 pdev->needs_freset = 1; 2347 2348 ha->prev_topology = 0; 2349 ha->init_cb_size = sizeof(init_cb_t); 2350 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2351 ha->optrom_size = OPTROM_SIZE_2300; 2352 2353 /* Assign ISP specific operations. */ 2354 if (IS_QLA2100(ha)) { 2355 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2356 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2357 req_length = REQUEST_ENTRY_CNT_2100; 2358 rsp_length = RESPONSE_ENTRY_CNT_2100; 2359 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2360 ha->gid_list_info_size = 4; 2361 ha->flash_conf_off = ~0; 2362 ha->flash_data_off = ~0; 2363 ha->nvram_conf_off = ~0; 2364 ha->nvram_data_off = ~0; 2365 ha->isp_ops = &qla2100_isp_ops; 2366 } else if (IS_QLA2200(ha)) { 2367 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2368 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2369 req_length = REQUEST_ENTRY_CNT_2200; 2370 rsp_length = RESPONSE_ENTRY_CNT_2100; 2371 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2372 ha->gid_list_info_size = 4; 2373 ha->flash_conf_off = ~0; 2374 ha->flash_data_off = ~0; 2375 ha->nvram_conf_off = ~0; 2376 ha->nvram_data_off = ~0; 2377 ha->isp_ops = &qla2100_isp_ops; 2378 } else if (IS_QLA23XX(ha)) { 2379 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2380 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2381 req_length = REQUEST_ENTRY_CNT_2200; 2382 rsp_length = RESPONSE_ENTRY_CNT_2300; 2383 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2384 ha->gid_list_info_size = 6; 2385 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2386 ha->optrom_size = OPTROM_SIZE_2322; 2387 ha->flash_conf_off = ~0; 2388 ha->flash_data_off = ~0; 2389 ha->nvram_conf_off = ~0; 2390 ha->nvram_data_off = ~0; 2391 ha->isp_ops = &qla2300_isp_ops; 2392 } else if (IS_QLA24XX_TYPE(ha)) { 2393 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2394 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2395 req_length = REQUEST_ENTRY_CNT_24XX; 2396 rsp_length = RESPONSE_ENTRY_CNT_2300; 2397 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2398 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2399 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2400 ha->gid_list_info_size = 8; 2401 ha->optrom_size = OPTROM_SIZE_24XX; 2402 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2403 ha->isp_ops = &qla24xx_isp_ops; 2404 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2405 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2406 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2407 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2408 } else if (IS_QLA25XX(ha)) { 2409 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2410 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2411 req_length = REQUEST_ENTRY_CNT_24XX; 2412 rsp_length = RESPONSE_ENTRY_CNT_2300; 2413 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2414 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2415 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2416 ha->gid_list_info_size = 8; 2417 ha->optrom_size = OPTROM_SIZE_25XX; 2418 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2419 ha->isp_ops = &qla25xx_isp_ops; 2420 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2421 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2422 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2423 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2424 } else if (IS_QLA81XX(ha)) { 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2427 req_length = REQUEST_ENTRY_CNT_24XX; 2428 rsp_length = RESPONSE_ENTRY_CNT_2300; 2429 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2430 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2431 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2432 ha->gid_list_info_size = 8; 2433 ha->optrom_size = OPTROM_SIZE_81XX; 2434 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2435 ha->isp_ops = &qla81xx_isp_ops; 2436 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2437 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2438 ha->nvram_conf_off = ~0; 2439 ha->nvram_data_off = ~0; 2440 } else if (IS_QLA82XX(ha)) { 2441 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2442 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2443 req_length = REQUEST_ENTRY_CNT_82XX; 2444 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2445 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2446 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2447 ha->gid_list_info_size = 8; 2448 ha->optrom_size = OPTROM_SIZE_82XX; 2449 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2450 ha->isp_ops = &qla82xx_isp_ops; 2451 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2452 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2453 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2454 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2455 } else if (IS_QLA8044(ha)) { 2456 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2457 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2458 req_length = REQUEST_ENTRY_CNT_82XX; 2459 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2460 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2461 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2462 ha->gid_list_info_size = 8; 2463 ha->optrom_size = OPTROM_SIZE_83XX; 2464 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2465 ha->isp_ops = &qla8044_isp_ops; 2466 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2467 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2468 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2469 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2470 } else if (IS_QLA83XX(ha)) { 2471 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2472 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2473 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2474 req_length = REQUEST_ENTRY_CNT_83XX; 2475 rsp_length = RESPONSE_ENTRY_CNT_2300; 2476 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2477 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2478 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2479 ha->gid_list_info_size = 8; 2480 ha->optrom_size = OPTROM_SIZE_83XX; 2481 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2482 ha->isp_ops = &qla83xx_isp_ops; 2483 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2484 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2485 ha->nvram_conf_off = ~0; 2486 ha->nvram_data_off = ~0; 2487 } else if (IS_QLAFX00(ha)) { 2488 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2489 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2490 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2491 req_length = REQUEST_ENTRY_CNT_FX00; 2492 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2493 ha->isp_ops = &qlafx00_isp_ops; 2494 ha->port_down_retry_count = 30; /* default value */ 2495 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2496 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2497 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2498 ha->mr.fw_hbt_en = 1; 2499 ha->mr.host_info_resend = false; 2500 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2501 } else if (IS_QLA27XX(ha)) { 2502 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2503 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2504 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2505 req_length = REQUEST_ENTRY_CNT_24XX; 2506 rsp_length = RESPONSE_ENTRY_CNT_2300; 2507 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2508 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2509 ha->gid_list_info_size = 8; 2510 ha->optrom_size = OPTROM_SIZE_83XX; 2511 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2512 ha->isp_ops = &qla27xx_isp_ops; 2513 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2514 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2515 ha->nvram_conf_off = ~0; 2516 ha->nvram_data_off = ~0; 2517 } 2518 2519 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2520 "mbx_count=%d, req_length=%d, " 2521 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2522 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2523 "max_fibre_devices=%d.\n", 2524 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2525 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2526 ha->nvram_npiv_size, ha->max_fibre_devices); 2527 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2528 "isp_ops=%p, flash_conf_off=%d, " 2529 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2530 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2531 ha->nvram_conf_off, ha->nvram_data_off); 2532 2533 /* Configure PCI I/O space */ 2534 ret = ha->isp_ops->iospace_config(ha); 2535 if (ret) 2536 goto iospace_config_failed; 2537 2538 ql_log_pci(ql_log_info, pdev, 0x001d, 2539 "Found an ISP%04X irq %d iobase 0x%p.\n", 2540 pdev->device, pdev->irq, ha->iobase); 2541 mutex_init(&ha->vport_lock); 2542 init_completion(&ha->mbx_cmd_comp); 2543 complete(&ha->mbx_cmd_comp); 2544 init_completion(&ha->mbx_intr_comp); 2545 init_completion(&ha->dcbx_comp); 2546 init_completion(&ha->lb_portup_comp); 2547 2548 set_bit(0, (unsigned long *) ha->vp_idx_map); 2549 2550 qla2x00_config_dma_addressing(ha); 2551 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2552 "64 Bit addressing is %s.\n", 2553 ha->flags.enable_64bit_addressing ? "enable" : 2554 "disable"); 2555 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2556 if (ret) { 2557 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2558 "Failed to allocate memory for adapter, aborting.\n"); 2559 2560 goto probe_hw_failed; 2561 } 2562 2563 req->max_q_depth = MAX_Q_DEPTH; 2564 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2565 req->max_q_depth = ql2xmaxqdepth; 2566 2567 2568 base_vha = qla2x00_create_host(sht, ha); 2569 if (!base_vha) { 2570 ret = -ENOMEM; 2571 qla2x00_mem_free(ha); 2572 qla2x00_free_req_que(ha, req); 2573 qla2x00_free_rsp_que(ha, rsp); 2574 goto probe_hw_failed; 2575 } 2576 2577 pci_set_drvdata(pdev, base_vha); 2578 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2579 2580 host = base_vha->host; 2581 base_vha->req = req; 2582 if (IS_QLA2XXX_MIDTYPE(ha)) 2583 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2584 else 2585 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2586 base_vha->vp_idx; 2587 2588 /* Setup fcport template structure. */ 2589 ha->mr.fcport.vha = base_vha; 2590 ha->mr.fcport.port_type = FCT_UNKNOWN; 2591 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2592 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2593 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2594 ha->mr.fcport.scan_state = 1; 2595 2596 /* Set the SG table size based on ISP type */ 2597 if (!IS_FWI2_CAPABLE(ha)) { 2598 if (IS_QLA2100(ha)) 2599 host->sg_tablesize = 32; 2600 } else { 2601 if (!IS_QLA82XX(ha)) 2602 host->sg_tablesize = QLA_SG_ALL; 2603 } 2604 host->max_id = ha->max_fibre_devices; 2605 host->cmd_per_lun = 3; 2606 host->unique_id = host->host_no; 2607 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2608 host->max_cmd_len = 32; 2609 else 2610 host->max_cmd_len = MAX_CMDSZ; 2611 host->max_channel = MAX_BUSES - 1; 2612 /* Older HBAs support only 16-bit LUNs */ 2613 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2614 ql2xmaxlun > 0xffff) 2615 host->max_lun = 0xffff; 2616 else 2617 host->max_lun = ql2xmaxlun; 2618 host->transportt = qla2xxx_transport_template; 2619 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2620 2621 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2622 "max_id=%d this_id=%d " 2623 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2624 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2625 host->this_id, host->cmd_per_lun, host->unique_id, 2626 host->max_cmd_len, host->max_channel, host->max_lun, 2627 host->transportt, sht->vendor_id); 2628 2629 que_init: 2630 /* Alloc arrays of request and response ring ptrs */ 2631 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2632 ql_log(ql_log_fatal, base_vha, 0x003d, 2633 "Failed to allocate memory for queue pointers..." 2634 "aborting.\n"); 2635 goto probe_init_failed; 2636 } 2637 2638 qlt_probe_one_stage1(base_vha, ha); 2639 2640 /* Set up the irqs */ 2641 ret = qla2x00_request_irqs(ha, rsp); 2642 if (ret) 2643 goto probe_init_failed; 2644 2645 pci_save_state(pdev); 2646 2647 /* Assign back pointers */ 2648 rsp->req = req; 2649 req->rsp = rsp; 2650 2651 if (IS_QLAFX00(ha)) { 2652 ha->rsp_q_map[0] = rsp; 2653 ha->req_q_map[0] = req; 2654 set_bit(0, ha->req_qid_map); 2655 set_bit(0, ha->rsp_qid_map); 2656 } 2657 2658 /* FWI2-capable only. */ 2659 req->req_q_in = &ha->iobase->isp24.req_q_in; 2660 req->req_q_out = &ha->iobase->isp24.req_q_out; 2661 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2662 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2663 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2664 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2665 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2666 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2667 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2668 } 2669 2670 if (IS_QLAFX00(ha)) { 2671 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2672 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2673 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2674 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2675 } 2676 2677 if (IS_P3P_TYPE(ha)) { 2678 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2679 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2680 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2681 } 2682 2683 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2684 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2685 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2686 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2687 "req->req_q_in=%p req->req_q_out=%p " 2688 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2689 req->req_q_in, req->req_q_out, 2690 rsp->rsp_q_in, rsp->rsp_q_out); 2691 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2692 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2693 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2694 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2695 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2696 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2697 2698 if (ha->isp_ops->initialize_adapter(base_vha)) { 2699 ql_log(ql_log_fatal, base_vha, 0x00d6, 2700 "Failed to initialize adapter - Adapter flags %x.\n", 2701 base_vha->device_flags); 2702 2703 if (IS_QLA82XX(ha)) { 2704 qla82xx_idc_lock(ha); 2705 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2706 QLA8XXX_DEV_FAILED); 2707 qla82xx_idc_unlock(ha); 2708 ql_log(ql_log_fatal, base_vha, 0x00d7, 2709 "HW State: FAILED.\n"); 2710 } else if (IS_QLA8044(ha)) { 2711 qla8044_idc_lock(ha); 2712 qla8044_wr_direct(base_vha, 2713 QLA8044_CRB_DEV_STATE_INDEX, 2714 QLA8XXX_DEV_FAILED); 2715 qla8044_idc_unlock(ha); 2716 ql_log(ql_log_fatal, base_vha, 0x0150, 2717 "HW State: FAILED.\n"); 2718 } 2719 2720 ret = -ENODEV; 2721 goto probe_failed; 2722 } 2723 2724 if (IS_QLAFX00(ha)) 2725 host->can_queue = QLAFX00_MAX_CANQUEUE; 2726 else 2727 host->can_queue = req->num_outstanding_cmds - 10; 2728 2729 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2730 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2731 host->can_queue, base_vha->req, 2732 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2733 2734 if (ha->mqenable) { 2735 if (qla25xx_setup_mode(base_vha)) { 2736 ql_log(ql_log_warn, base_vha, 0x00ec, 2737 "Failed to create queues, falling back to single queue mode.\n"); 2738 goto que_init; 2739 } 2740 } 2741 2742 if (ha->flags.running_gold_fw) 2743 goto skip_dpc; 2744 2745 /* 2746 * Startup the kernel thread for this host adapter 2747 */ 2748 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2749 "%s_dpc", base_vha->host_str); 2750 if (IS_ERR(ha->dpc_thread)) { 2751 ql_log(ql_log_fatal, base_vha, 0x00ed, 2752 "Failed to start DPC thread.\n"); 2753 ret = PTR_ERR(ha->dpc_thread); 2754 goto probe_failed; 2755 } 2756 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2757 "DPC thread started successfully.\n"); 2758 2759 /* 2760 * If we're not coming up in initiator mode, we might sit for 2761 * a while without waking up the dpc thread, which leads to a 2762 * stuck process warning. So just kick the dpc once here and 2763 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2764 */ 2765 qla2xxx_wake_dpc(base_vha); 2766 2767 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2768 2769 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2770 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2771 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2772 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2773 2774 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2775 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2776 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2777 INIT_WORK(&ha->idc_state_handler, 2778 qla83xx_idc_state_handler_work); 2779 INIT_WORK(&ha->nic_core_unrecoverable, 2780 qla83xx_nic_core_unrecoverable_work); 2781 } 2782 2783 skip_dpc: 2784 list_add_tail(&base_vha->list, &ha->vp_list); 2785 base_vha->host->irq = ha->pdev->irq; 2786 2787 /* Initialized the timer */ 2788 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2789 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2790 "Started qla2x00_timer with " 2791 "interval=%d.\n", WATCH_INTERVAL); 2792 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2793 "Detected hba at address=%p.\n", 2794 ha); 2795 2796 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2797 if (ha->fw_attributes & BIT_4) { 2798 int prot = 0, guard; 2799 base_vha->flags.difdix_supported = 1; 2800 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2801 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2802 if (ql2xenabledif == 1) 2803 prot = SHOST_DIX_TYPE0_PROTECTION; 2804 scsi_host_set_prot(host, 2805 prot | SHOST_DIF_TYPE1_PROTECTION 2806 | SHOST_DIF_TYPE2_PROTECTION 2807 | SHOST_DIF_TYPE3_PROTECTION 2808 | SHOST_DIX_TYPE1_PROTECTION 2809 | SHOST_DIX_TYPE2_PROTECTION 2810 | SHOST_DIX_TYPE3_PROTECTION); 2811 2812 guard = SHOST_DIX_GUARD_CRC; 2813 2814 if (IS_PI_IPGUARD_CAPABLE(ha) && 2815 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2816 guard |= SHOST_DIX_GUARD_IP; 2817 2818 scsi_host_set_guard(host, guard); 2819 } else 2820 base_vha->flags.difdix_supported = 0; 2821 } 2822 2823 ha->isp_ops->enable_intrs(ha); 2824 2825 if (IS_QLAFX00(ha)) { 2826 ret = qlafx00_fx_disc(base_vha, 2827 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2828 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2829 QLA_SG_ALL : 128; 2830 } 2831 2832 ret = scsi_add_host(host, &pdev->dev); 2833 if (ret) 2834 goto probe_failed; 2835 2836 base_vha->flags.init_done = 1; 2837 base_vha->flags.online = 1; 2838 ha->prev_minidump_failed = 0; 2839 2840 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2841 "Init done and hba is online.\n"); 2842 2843 if (qla_ini_mode_enabled(base_vha)) 2844 scsi_scan_host(host); 2845 else 2846 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2847 "skipping scsi_scan_host() for non-initiator port\n"); 2848 2849 qla2x00_alloc_sysfs_attr(base_vha); 2850 2851 if (IS_QLAFX00(ha)) { 2852 ret = qlafx00_fx_disc(base_vha, 2853 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2854 2855 /* Register system information */ 2856 ret = qlafx00_fx_disc(base_vha, 2857 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2858 } 2859 2860 qla2x00_init_host_attr(base_vha); 2861 2862 qla2x00_dfs_setup(base_vha); 2863 2864 ql_log(ql_log_info, base_vha, 0x00fb, 2865 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2866 ql_log(ql_log_info, base_vha, 0x00fc, 2867 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2868 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2869 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2870 base_vha->host_no, 2871 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2872 2873 qlt_add_target(ha, base_vha); 2874 2875 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2876 return 0; 2877 2878 probe_init_failed: 2879 qla2x00_free_req_que(ha, req); 2880 ha->req_q_map[0] = NULL; 2881 clear_bit(0, ha->req_qid_map); 2882 qla2x00_free_rsp_que(ha, rsp); 2883 ha->rsp_q_map[0] = NULL; 2884 clear_bit(0, ha->rsp_qid_map); 2885 ha->max_req_queues = ha->max_rsp_queues = 0; 2886 2887 probe_failed: 2888 if (base_vha->timer_active) 2889 qla2x00_stop_timer(base_vha); 2890 base_vha->flags.online = 0; 2891 if (ha->dpc_thread) { 2892 struct task_struct *t = ha->dpc_thread; 2893 2894 ha->dpc_thread = NULL; 2895 kthread_stop(t); 2896 } 2897 2898 qla2x00_free_device(base_vha); 2899 2900 scsi_host_put(base_vha->host); 2901 2902 probe_hw_failed: 2903 qla2x00_clear_drv_active(ha); 2904 2905 iospace_config_failed: 2906 if (IS_P3P_TYPE(ha)) { 2907 if (!ha->nx_pcibase) 2908 iounmap((device_reg_t *)ha->nx_pcibase); 2909 if (!ql2xdbwr) 2910 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 2911 } else { 2912 if (ha->iobase) 2913 iounmap(ha->iobase); 2914 if (ha->cregbase) 2915 iounmap(ha->cregbase); 2916 } 2917 pci_release_selected_regions(ha->pdev, ha->bars); 2918 kfree(ha); 2919 ha = NULL; 2920 2921 probe_out: 2922 pci_disable_device(pdev); 2923 return ret; 2924 } 2925 2926 static void 2927 qla2x00_shutdown(struct pci_dev *pdev) 2928 { 2929 scsi_qla_host_t *vha; 2930 struct qla_hw_data *ha; 2931 2932 if (!atomic_read(&pdev->enable_cnt)) 2933 return; 2934 2935 vha = pci_get_drvdata(pdev); 2936 ha = vha->hw; 2937 2938 /* Notify ISPFX00 firmware */ 2939 if (IS_QLAFX00(ha)) 2940 qlafx00_driver_shutdown(vha, 20); 2941 2942 /* Turn-off FCE trace */ 2943 if (ha->flags.fce_enabled) { 2944 qla2x00_disable_fce_trace(vha, NULL, NULL); 2945 ha->flags.fce_enabled = 0; 2946 } 2947 2948 /* Turn-off EFT trace */ 2949 if (ha->eft) 2950 qla2x00_disable_eft_trace(vha); 2951 2952 /* Stop currently executing firmware. */ 2953 qla2x00_try_to_stop_firmware(vha); 2954 2955 /* Turn adapter off line */ 2956 vha->flags.online = 0; 2957 2958 /* turn-off interrupts on the card */ 2959 if (ha->interrupts_on) { 2960 vha->flags.init_done = 0; 2961 ha->isp_ops->disable_intrs(ha); 2962 } 2963 2964 qla2x00_free_irqs(vha); 2965 2966 qla2x00_free_fw_dump(ha); 2967 2968 pci_disable_pcie_error_reporting(pdev); 2969 pci_disable_device(pdev); 2970 } 2971 2972 /* Deletes all the virtual ports for a given ha */ 2973 static void 2974 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 2975 { 2976 struct Scsi_Host *scsi_host; 2977 scsi_qla_host_t *vha; 2978 unsigned long flags; 2979 2980 mutex_lock(&ha->vport_lock); 2981 while (ha->cur_vport_count) { 2982 spin_lock_irqsave(&ha->vport_slock, flags); 2983 2984 BUG_ON(base_vha->list.next == &ha->vp_list); 2985 /* This assumes first entry in ha->vp_list is always base vha */ 2986 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2987 scsi_host = scsi_host_get(vha->host); 2988 2989 spin_unlock_irqrestore(&ha->vport_slock, flags); 2990 mutex_unlock(&ha->vport_lock); 2991 2992 fc_vport_terminate(vha->fc_vport); 2993 scsi_host_put(vha->host); 2994 2995 mutex_lock(&ha->vport_lock); 2996 } 2997 mutex_unlock(&ha->vport_lock); 2998 } 2999 3000 /* Stops all deferred work threads */ 3001 static void 3002 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3003 { 3004 /* Flush the work queue and remove it */ 3005 if (ha->wq) { 3006 flush_workqueue(ha->wq); 3007 destroy_workqueue(ha->wq); 3008 ha->wq = NULL; 3009 } 3010 3011 /* Cancel all work and destroy DPC workqueues */ 3012 if (ha->dpc_lp_wq) { 3013 cancel_work_sync(&ha->idc_aen); 3014 destroy_workqueue(ha->dpc_lp_wq); 3015 ha->dpc_lp_wq = NULL; 3016 } 3017 3018 if (ha->dpc_hp_wq) { 3019 cancel_work_sync(&ha->nic_core_reset); 3020 cancel_work_sync(&ha->idc_state_handler); 3021 cancel_work_sync(&ha->nic_core_unrecoverable); 3022 destroy_workqueue(ha->dpc_hp_wq); 3023 ha->dpc_hp_wq = NULL; 3024 } 3025 3026 /* Kill the kernel thread for this host */ 3027 if (ha->dpc_thread) { 3028 struct task_struct *t = ha->dpc_thread; 3029 3030 /* 3031 * qla2xxx_wake_dpc checks for ->dpc_thread 3032 * so we need to zero it out. 3033 */ 3034 ha->dpc_thread = NULL; 3035 kthread_stop(t); 3036 } 3037 } 3038 3039 static void 3040 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3041 { 3042 if (IS_QLA82XX(ha)) { 3043 3044 iounmap((device_reg_t *)ha->nx_pcibase); 3045 if (!ql2xdbwr) 3046 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3047 } else { 3048 if (ha->iobase) 3049 iounmap(ha->iobase); 3050 3051 if (ha->cregbase) 3052 iounmap(ha->cregbase); 3053 3054 if (ha->mqiobase) 3055 iounmap(ha->mqiobase); 3056 3057 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3058 iounmap(ha->msixbase); 3059 } 3060 } 3061 3062 static void 3063 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3064 { 3065 if (IS_QLA8044(ha)) { 3066 qla8044_idc_lock(ha); 3067 qla8044_clear_drv_active(ha); 3068 qla8044_idc_unlock(ha); 3069 } else if (IS_QLA82XX(ha)) { 3070 qla82xx_idc_lock(ha); 3071 qla82xx_clear_drv_active(ha); 3072 qla82xx_idc_unlock(ha); 3073 } 3074 } 3075 3076 static void 3077 qla2x00_remove_one(struct pci_dev *pdev) 3078 { 3079 scsi_qla_host_t *base_vha; 3080 struct qla_hw_data *ha; 3081 3082 base_vha = pci_get_drvdata(pdev); 3083 ha = base_vha->hw; 3084 3085 /* Indicate device removal to prevent future board_disable and wait 3086 * until any pending board_disable has completed. */ 3087 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3088 cancel_work_sync(&ha->board_disable); 3089 3090 /* 3091 * If the PCI device is disabled then there was a PCI-disconnect and 3092 * qla2x00_disable_board_on_pci_error has taken care of most of the 3093 * resources. 3094 */ 3095 if (!atomic_read(&pdev->enable_cnt)) { 3096 scsi_host_put(base_vha->host); 3097 kfree(ha); 3098 pci_set_drvdata(pdev, NULL); 3099 return; 3100 } 3101 3102 qla2x00_wait_for_hba_ready(base_vha); 3103 3104 set_bit(UNLOADING, &base_vha->dpc_flags); 3105 3106 if (IS_QLAFX00(ha)) 3107 qlafx00_driver_shutdown(base_vha, 20); 3108 3109 qla2x00_delete_all_vps(ha, base_vha); 3110 3111 if (IS_QLA8031(ha)) { 3112 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3113 "Clearing fcoe driver presence.\n"); 3114 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3115 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3116 "Error while clearing DRV-Presence.\n"); 3117 } 3118 3119 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3120 3121 qla2x00_dfs_remove(base_vha); 3122 3123 qla84xx_put_chip(base_vha); 3124 3125 /* Laser should be disabled only for ISP2031 */ 3126 if (IS_QLA2031(ha)) 3127 qla83xx_disable_laser(base_vha); 3128 3129 /* Disable timer */ 3130 if (base_vha->timer_active) 3131 qla2x00_stop_timer(base_vha); 3132 3133 base_vha->flags.online = 0; 3134 3135 qla2x00_destroy_deferred_work(ha); 3136 3137 qlt_remove_target(ha, base_vha); 3138 3139 qla2x00_free_sysfs_attr(base_vha, true); 3140 3141 fc_remove_host(base_vha->host); 3142 3143 scsi_remove_host(base_vha->host); 3144 3145 qla2x00_free_device(base_vha); 3146 3147 qla2x00_clear_drv_active(ha); 3148 3149 scsi_host_put(base_vha->host); 3150 3151 qla2x00_unmap_iobases(ha); 3152 3153 pci_release_selected_regions(ha->pdev, ha->bars); 3154 kfree(ha); 3155 ha = NULL; 3156 3157 pci_disable_pcie_error_reporting(pdev); 3158 3159 pci_disable_device(pdev); 3160 } 3161 3162 static void 3163 qla2x00_free_device(scsi_qla_host_t *vha) 3164 { 3165 struct qla_hw_data *ha = vha->hw; 3166 3167 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3168 3169 /* Disable timer */ 3170 if (vha->timer_active) 3171 qla2x00_stop_timer(vha); 3172 3173 qla25xx_delete_queues(vha); 3174 3175 if (ha->flags.fce_enabled) 3176 qla2x00_disable_fce_trace(vha, NULL, NULL); 3177 3178 if (ha->eft) 3179 qla2x00_disable_eft_trace(vha); 3180 3181 /* Stop currently executing firmware. */ 3182 qla2x00_try_to_stop_firmware(vha); 3183 3184 vha->flags.online = 0; 3185 3186 /* turn-off interrupts on the card */ 3187 if (ha->interrupts_on) { 3188 vha->flags.init_done = 0; 3189 ha->isp_ops->disable_intrs(ha); 3190 } 3191 3192 qla2x00_free_irqs(vha); 3193 3194 qla2x00_free_fcports(vha); 3195 3196 qla2x00_mem_free(ha); 3197 3198 qla82xx_md_free(vha); 3199 3200 qla2x00_free_queues(ha); 3201 } 3202 3203 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3204 { 3205 fc_port_t *fcport, *tfcport; 3206 3207 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3208 list_del(&fcport->list); 3209 qla2x00_clear_loop_id(fcport); 3210 kfree(fcport); 3211 fcport = NULL; 3212 } 3213 } 3214 3215 static inline void 3216 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3217 int defer) 3218 { 3219 struct fc_rport *rport; 3220 scsi_qla_host_t *base_vha; 3221 unsigned long flags; 3222 3223 if (!fcport->rport) 3224 return; 3225 3226 rport = fcport->rport; 3227 if (defer) { 3228 base_vha = pci_get_drvdata(vha->hw->pdev); 3229 spin_lock_irqsave(vha->host->host_lock, flags); 3230 fcport->drport = rport; 3231 spin_unlock_irqrestore(vha->host->host_lock, flags); 3232 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3233 qla2xxx_wake_dpc(base_vha); 3234 } else { 3235 fc_remote_port_delete(rport); 3236 qlt_fc_port_deleted(vha, fcport); 3237 } 3238 } 3239 3240 /* 3241 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3242 * 3243 * Input: ha = adapter block pointer. fcport = port structure pointer. 3244 * 3245 * Return: None. 3246 * 3247 * Context: 3248 */ 3249 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3250 int do_login, int defer) 3251 { 3252 if (IS_QLAFX00(vha->hw)) { 3253 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3254 qla2x00_schedule_rport_del(vha, fcport, defer); 3255 return; 3256 } 3257 3258 if (atomic_read(&fcport->state) == FCS_ONLINE && 3259 vha->vp_idx == fcport->vha->vp_idx) { 3260 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3261 qla2x00_schedule_rport_del(vha, fcport, defer); 3262 } 3263 /* 3264 * We may need to retry the login, so don't change the state of the 3265 * port but do the retries. 3266 */ 3267 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3268 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3269 3270 if (!do_login) 3271 return; 3272 3273 if (fcport->login_retry == 0) { 3274 fcport->login_retry = vha->hw->login_retry_count; 3275 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3276 3277 ql_dbg(ql_dbg_disc, vha, 0x2067, 3278 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3279 fcport->port_name, fcport->loop_id, fcport->login_retry); 3280 } 3281 } 3282 3283 /* 3284 * qla2x00_mark_all_devices_lost 3285 * Updates fcport state when device goes offline. 3286 * 3287 * Input: 3288 * ha = adapter block pointer. 3289 * fcport = port structure pointer. 3290 * 3291 * Return: 3292 * None. 3293 * 3294 * Context: 3295 */ 3296 void 3297 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3298 { 3299 fc_port_t *fcport; 3300 3301 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3302 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3303 continue; 3304 3305 /* 3306 * No point in marking the device as lost, if the device is 3307 * already DEAD. 3308 */ 3309 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3310 continue; 3311 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3312 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3313 if (defer) 3314 qla2x00_schedule_rport_del(vha, fcport, defer); 3315 else if (vha->vp_idx == fcport->vha->vp_idx) 3316 qla2x00_schedule_rport_del(vha, fcport, defer); 3317 } 3318 } 3319 } 3320 3321 /* 3322 * qla2x00_mem_alloc 3323 * Allocates adapter memory. 3324 * 3325 * Returns: 3326 * 0 = success. 3327 * !0 = failure. 3328 */ 3329 static int 3330 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3331 struct req_que **req, struct rsp_que **rsp) 3332 { 3333 char name[16]; 3334 3335 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3336 &ha->init_cb_dma, GFP_KERNEL); 3337 if (!ha->init_cb) 3338 goto fail; 3339 3340 if (qlt_mem_alloc(ha) < 0) 3341 goto fail_free_init_cb; 3342 3343 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3344 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3345 if (!ha->gid_list) 3346 goto fail_free_tgt_mem; 3347 3348 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3349 if (!ha->srb_mempool) 3350 goto fail_free_gid_list; 3351 3352 if (IS_P3P_TYPE(ha)) { 3353 /* Allocate cache for CT6 Ctx. */ 3354 if (!ctx_cachep) { 3355 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3356 sizeof(struct ct6_dsd), 0, 3357 SLAB_HWCACHE_ALIGN, NULL); 3358 if (!ctx_cachep) 3359 goto fail_free_gid_list; 3360 } 3361 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3362 ctx_cachep); 3363 if (!ha->ctx_mempool) 3364 goto fail_free_srb_mempool; 3365 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3366 "ctx_cachep=%p ctx_mempool=%p.\n", 3367 ctx_cachep, ha->ctx_mempool); 3368 } 3369 3370 /* Get memory for cached NVRAM */ 3371 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3372 if (!ha->nvram) 3373 goto fail_free_ctx_mempool; 3374 3375 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3376 ha->pdev->device); 3377 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3378 DMA_POOL_SIZE, 8, 0); 3379 if (!ha->s_dma_pool) 3380 goto fail_free_nvram; 3381 3382 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3383 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3384 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3385 3386 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3387 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3388 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3389 if (!ha->dl_dma_pool) { 3390 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3391 "Failed to allocate memory for dl_dma_pool.\n"); 3392 goto fail_s_dma_pool; 3393 } 3394 3395 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3396 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3397 if (!ha->fcp_cmnd_dma_pool) { 3398 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3399 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3400 goto fail_dl_dma_pool; 3401 } 3402 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3403 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3404 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3405 } 3406 3407 /* Allocate memory for SNS commands */ 3408 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3409 /* Get consistent memory allocated for SNS commands */ 3410 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3411 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3412 if (!ha->sns_cmd) 3413 goto fail_dma_pool; 3414 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3415 "sns_cmd: %p.\n", ha->sns_cmd); 3416 } else { 3417 /* Get consistent memory allocated for MS IOCB */ 3418 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3419 &ha->ms_iocb_dma); 3420 if (!ha->ms_iocb) 3421 goto fail_dma_pool; 3422 /* Get consistent memory allocated for CT SNS commands */ 3423 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3424 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3425 if (!ha->ct_sns) 3426 goto fail_free_ms_iocb; 3427 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3428 "ms_iocb=%p ct_sns=%p.\n", 3429 ha->ms_iocb, ha->ct_sns); 3430 } 3431 3432 /* Allocate memory for request ring */ 3433 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3434 if (!*req) { 3435 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3436 "Failed to allocate memory for req.\n"); 3437 goto fail_req; 3438 } 3439 (*req)->length = req_len; 3440 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3441 ((*req)->length + 1) * sizeof(request_t), 3442 &(*req)->dma, GFP_KERNEL); 3443 if (!(*req)->ring) { 3444 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3445 "Failed to allocate memory for req_ring.\n"); 3446 goto fail_req_ring; 3447 } 3448 /* Allocate memory for response ring */ 3449 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3450 if (!*rsp) { 3451 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3452 "Failed to allocate memory for rsp.\n"); 3453 goto fail_rsp; 3454 } 3455 (*rsp)->hw = ha; 3456 (*rsp)->length = rsp_len; 3457 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3458 ((*rsp)->length + 1) * sizeof(response_t), 3459 &(*rsp)->dma, GFP_KERNEL); 3460 if (!(*rsp)->ring) { 3461 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3462 "Failed to allocate memory for rsp_ring.\n"); 3463 goto fail_rsp_ring; 3464 } 3465 (*req)->rsp = *rsp; 3466 (*rsp)->req = *req; 3467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3468 "req=%p req->length=%d req->ring=%p rsp=%p " 3469 "rsp->length=%d rsp->ring=%p.\n", 3470 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3471 (*rsp)->ring); 3472 /* Allocate memory for NVRAM data for vports */ 3473 if (ha->nvram_npiv_size) { 3474 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3475 ha->nvram_npiv_size, GFP_KERNEL); 3476 if (!ha->npiv_info) { 3477 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3478 "Failed to allocate memory for npiv_info.\n"); 3479 goto fail_npiv_info; 3480 } 3481 } else 3482 ha->npiv_info = NULL; 3483 3484 /* Get consistent memory allocated for EX-INIT-CB. */ 3485 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3486 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3487 &ha->ex_init_cb_dma); 3488 if (!ha->ex_init_cb) 3489 goto fail_ex_init_cb; 3490 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3491 "ex_init_cb=%p.\n", ha->ex_init_cb); 3492 } 3493 3494 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3495 3496 /* Get consistent memory allocated for Async Port-Database. */ 3497 if (!IS_FWI2_CAPABLE(ha)) { 3498 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3499 &ha->async_pd_dma); 3500 if (!ha->async_pd) 3501 goto fail_async_pd; 3502 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3503 "async_pd=%p.\n", ha->async_pd); 3504 } 3505 3506 INIT_LIST_HEAD(&ha->vp_list); 3507 3508 /* Allocate memory for our loop_id bitmap */ 3509 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3510 GFP_KERNEL); 3511 if (!ha->loop_id_map) 3512 goto fail_async_pd; 3513 else { 3514 qla2x00_set_reserved_loop_ids(ha); 3515 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3516 "loop_id_map=%p.\n", ha->loop_id_map); 3517 } 3518 3519 return 0; 3520 3521 fail_async_pd: 3522 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3523 fail_ex_init_cb: 3524 kfree(ha->npiv_info); 3525 fail_npiv_info: 3526 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3527 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3528 (*rsp)->ring = NULL; 3529 (*rsp)->dma = 0; 3530 fail_rsp_ring: 3531 kfree(*rsp); 3532 fail_rsp: 3533 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3534 sizeof(request_t), (*req)->ring, (*req)->dma); 3535 (*req)->ring = NULL; 3536 (*req)->dma = 0; 3537 fail_req_ring: 3538 kfree(*req); 3539 fail_req: 3540 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3541 ha->ct_sns, ha->ct_sns_dma); 3542 ha->ct_sns = NULL; 3543 ha->ct_sns_dma = 0; 3544 fail_free_ms_iocb: 3545 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3546 ha->ms_iocb = NULL; 3547 ha->ms_iocb_dma = 0; 3548 fail_dma_pool: 3549 if (IS_QLA82XX(ha) || ql2xenabledif) { 3550 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3551 ha->fcp_cmnd_dma_pool = NULL; 3552 } 3553 fail_dl_dma_pool: 3554 if (IS_QLA82XX(ha) || ql2xenabledif) { 3555 dma_pool_destroy(ha->dl_dma_pool); 3556 ha->dl_dma_pool = NULL; 3557 } 3558 fail_s_dma_pool: 3559 dma_pool_destroy(ha->s_dma_pool); 3560 ha->s_dma_pool = NULL; 3561 fail_free_nvram: 3562 kfree(ha->nvram); 3563 ha->nvram = NULL; 3564 fail_free_ctx_mempool: 3565 mempool_destroy(ha->ctx_mempool); 3566 ha->ctx_mempool = NULL; 3567 fail_free_srb_mempool: 3568 mempool_destroy(ha->srb_mempool); 3569 ha->srb_mempool = NULL; 3570 fail_free_gid_list: 3571 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3572 ha->gid_list, 3573 ha->gid_list_dma); 3574 ha->gid_list = NULL; 3575 ha->gid_list_dma = 0; 3576 fail_free_tgt_mem: 3577 qlt_mem_free(ha); 3578 fail_free_init_cb: 3579 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3580 ha->init_cb_dma); 3581 ha->init_cb = NULL; 3582 ha->init_cb_dma = 0; 3583 fail: 3584 ql_log(ql_log_fatal, NULL, 0x0030, 3585 "Memory allocation failure.\n"); 3586 return -ENOMEM; 3587 } 3588 3589 /* 3590 * qla2x00_free_fw_dump 3591 * Frees fw dump stuff. 3592 * 3593 * Input: 3594 * ha = adapter block pointer 3595 */ 3596 static void 3597 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3598 { 3599 if (ha->fce) 3600 dma_free_coherent(&ha->pdev->dev, 3601 FCE_SIZE, ha->fce, ha->fce_dma); 3602 3603 if (ha->eft) 3604 dma_free_coherent(&ha->pdev->dev, 3605 EFT_SIZE, ha->eft, ha->eft_dma); 3606 3607 if (ha->fw_dump) 3608 vfree(ha->fw_dump); 3609 if (ha->fw_dump_template) 3610 vfree(ha->fw_dump_template); 3611 3612 ha->fce = NULL; 3613 ha->fce_dma = 0; 3614 ha->eft = NULL; 3615 ha->eft_dma = 0; 3616 ha->fw_dumped = 0; 3617 ha->fw_dump_cap_flags = 0; 3618 ha->fw_dump_reading = 0; 3619 ha->fw_dump = NULL; 3620 ha->fw_dump_len = 0; 3621 ha->fw_dump_template = NULL; 3622 ha->fw_dump_template_len = 0; 3623 } 3624 3625 /* 3626 * qla2x00_mem_free 3627 * Frees all adapter allocated memory. 3628 * 3629 * Input: 3630 * ha = adapter block pointer. 3631 */ 3632 static void 3633 qla2x00_mem_free(struct qla_hw_data *ha) 3634 { 3635 qla2x00_free_fw_dump(ha); 3636 3637 if (ha->mctp_dump) 3638 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3639 ha->mctp_dump_dma); 3640 3641 if (ha->srb_mempool) 3642 mempool_destroy(ha->srb_mempool); 3643 3644 if (ha->dcbx_tlv) 3645 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3646 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3647 3648 if (ha->xgmac_data) 3649 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3650 ha->xgmac_data, ha->xgmac_data_dma); 3651 3652 if (ha->sns_cmd) 3653 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3654 ha->sns_cmd, ha->sns_cmd_dma); 3655 3656 if (ha->ct_sns) 3657 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3658 ha->ct_sns, ha->ct_sns_dma); 3659 3660 if (ha->sfp_data) 3661 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3662 3663 if (ha->ms_iocb) 3664 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3665 3666 if (ha->ex_init_cb) 3667 dma_pool_free(ha->s_dma_pool, 3668 ha->ex_init_cb, ha->ex_init_cb_dma); 3669 3670 if (ha->async_pd) 3671 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3672 3673 if (ha->s_dma_pool) 3674 dma_pool_destroy(ha->s_dma_pool); 3675 3676 if (ha->gid_list) 3677 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3678 ha->gid_list, ha->gid_list_dma); 3679 3680 if (IS_QLA82XX(ha)) { 3681 if (!list_empty(&ha->gbl_dsd_list)) { 3682 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3683 3684 /* clean up allocated prev pool */ 3685 list_for_each_entry_safe(dsd_ptr, 3686 tdsd_ptr, &ha->gbl_dsd_list, list) { 3687 dma_pool_free(ha->dl_dma_pool, 3688 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3689 list_del(&dsd_ptr->list); 3690 kfree(dsd_ptr); 3691 } 3692 } 3693 } 3694 3695 if (ha->dl_dma_pool) 3696 dma_pool_destroy(ha->dl_dma_pool); 3697 3698 if (ha->fcp_cmnd_dma_pool) 3699 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3700 3701 if (ha->ctx_mempool) 3702 mempool_destroy(ha->ctx_mempool); 3703 3704 qlt_mem_free(ha); 3705 3706 if (ha->init_cb) 3707 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3708 ha->init_cb, ha->init_cb_dma); 3709 vfree(ha->optrom_buffer); 3710 kfree(ha->nvram); 3711 kfree(ha->npiv_info); 3712 kfree(ha->swl); 3713 kfree(ha->loop_id_map); 3714 3715 ha->srb_mempool = NULL; 3716 ha->ctx_mempool = NULL; 3717 ha->sns_cmd = NULL; 3718 ha->sns_cmd_dma = 0; 3719 ha->ct_sns = NULL; 3720 ha->ct_sns_dma = 0; 3721 ha->ms_iocb = NULL; 3722 ha->ms_iocb_dma = 0; 3723 ha->init_cb = NULL; 3724 ha->init_cb_dma = 0; 3725 ha->ex_init_cb = NULL; 3726 ha->ex_init_cb_dma = 0; 3727 ha->async_pd = NULL; 3728 ha->async_pd_dma = 0; 3729 3730 ha->s_dma_pool = NULL; 3731 ha->dl_dma_pool = NULL; 3732 ha->fcp_cmnd_dma_pool = NULL; 3733 3734 ha->gid_list = NULL; 3735 ha->gid_list_dma = 0; 3736 3737 ha->tgt.atio_ring = NULL; 3738 ha->tgt.atio_dma = 0; 3739 ha->tgt.tgt_vp_map = NULL; 3740 } 3741 3742 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3743 struct qla_hw_data *ha) 3744 { 3745 struct Scsi_Host *host; 3746 struct scsi_qla_host *vha = NULL; 3747 3748 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3749 if (host == NULL) { 3750 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3751 "Failed to allocate host from the scsi layer, aborting.\n"); 3752 goto fail; 3753 } 3754 3755 /* Clear our data area */ 3756 vha = shost_priv(host); 3757 memset(vha, 0, sizeof(scsi_qla_host_t)); 3758 3759 vha->host = host; 3760 vha->host_no = host->host_no; 3761 vha->hw = ha; 3762 3763 INIT_LIST_HEAD(&vha->vp_fcports); 3764 INIT_LIST_HEAD(&vha->work_list); 3765 INIT_LIST_HEAD(&vha->list); 3766 3767 spin_lock_init(&vha->work_lock); 3768 3769 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3770 ql_dbg(ql_dbg_init, vha, 0x0041, 3771 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3772 vha->host, vha->hw, vha, 3773 dev_name(&(ha->pdev->dev))); 3774 3775 return vha; 3776 3777 fail: 3778 return vha; 3779 } 3780 3781 static struct qla_work_evt * 3782 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3783 { 3784 struct qla_work_evt *e; 3785 uint8_t bail; 3786 3787 QLA_VHA_MARK_BUSY(vha, bail); 3788 if (bail) 3789 return NULL; 3790 3791 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3792 if (!e) { 3793 QLA_VHA_MARK_NOT_BUSY(vha); 3794 return NULL; 3795 } 3796 3797 INIT_LIST_HEAD(&e->list); 3798 e->type = type; 3799 e->flags = QLA_EVT_FLAG_FREE; 3800 return e; 3801 } 3802 3803 static int 3804 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3805 { 3806 unsigned long flags; 3807 3808 spin_lock_irqsave(&vha->work_lock, flags); 3809 list_add_tail(&e->list, &vha->work_list); 3810 spin_unlock_irqrestore(&vha->work_lock, flags); 3811 qla2xxx_wake_dpc(vha); 3812 3813 return QLA_SUCCESS; 3814 } 3815 3816 int 3817 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3818 u32 data) 3819 { 3820 struct qla_work_evt *e; 3821 3822 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3823 if (!e) 3824 return QLA_FUNCTION_FAILED; 3825 3826 e->u.aen.code = code; 3827 e->u.aen.data = data; 3828 return qla2x00_post_work(vha, e); 3829 } 3830 3831 int 3832 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3833 { 3834 struct qla_work_evt *e; 3835 3836 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3837 if (!e) 3838 return QLA_FUNCTION_FAILED; 3839 3840 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3841 return qla2x00_post_work(vha, e); 3842 } 3843 3844 #define qla2x00_post_async_work(name, type) \ 3845 int qla2x00_post_async_##name##_work( \ 3846 struct scsi_qla_host *vha, \ 3847 fc_port_t *fcport, uint16_t *data) \ 3848 { \ 3849 struct qla_work_evt *e; \ 3850 \ 3851 e = qla2x00_alloc_work(vha, type); \ 3852 if (!e) \ 3853 return QLA_FUNCTION_FAILED; \ 3854 \ 3855 e->u.logio.fcport = fcport; \ 3856 if (data) { \ 3857 e->u.logio.data[0] = data[0]; \ 3858 e->u.logio.data[1] = data[1]; \ 3859 } \ 3860 return qla2x00_post_work(vha, e); \ 3861 } 3862 3863 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3864 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3865 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3866 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3867 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3868 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3869 3870 int 3871 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3872 { 3873 struct qla_work_evt *e; 3874 3875 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3876 if (!e) 3877 return QLA_FUNCTION_FAILED; 3878 3879 e->u.uevent.code = code; 3880 return qla2x00_post_work(vha, e); 3881 } 3882 3883 static void 3884 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3885 { 3886 char event_string[40]; 3887 char *envp[] = { event_string, NULL }; 3888 3889 switch (code) { 3890 case QLA_UEVENT_CODE_FW_DUMP: 3891 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3892 vha->host_no); 3893 break; 3894 default: 3895 /* do nothing */ 3896 break; 3897 } 3898 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3899 } 3900 3901 int 3902 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 3903 uint32_t *data, int cnt) 3904 { 3905 struct qla_work_evt *e; 3906 3907 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 3908 if (!e) 3909 return QLA_FUNCTION_FAILED; 3910 3911 e->u.aenfx.evtcode = evtcode; 3912 e->u.aenfx.count = cnt; 3913 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 3914 return qla2x00_post_work(vha, e); 3915 } 3916 3917 void 3918 qla2x00_do_work(struct scsi_qla_host *vha) 3919 { 3920 struct qla_work_evt *e, *tmp; 3921 unsigned long flags; 3922 LIST_HEAD(work); 3923 3924 spin_lock_irqsave(&vha->work_lock, flags); 3925 list_splice_init(&vha->work_list, &work); 3926 spin_unlock_irqrestore(&vha->work_lock, flags); 3927 3928 list_for_each_entry_safe(e, tmp, &work, list) { 3929 list_del_init(&e->list); 3930 3931 switch (e->type) { 3932 case QLA_EVT_AEN: 3933 fc_host_post_event(vha->host, fc_get_event_number(), 3934 e->u.aen.code, e->u.aen.data); 3935 break; 3936 case QLA_EVT_IDC_ACK: 3937 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3938 break; 3939 case QLA_EVT_ASYNC_LOGIN: 3940 qla2x00_async_login(vha, e->u.logio.fcport, 3941 e->u.logio.data); 3942 break; 3943 case QLA_EVT_ASYNC_LOGIN_DONE: 3944 qla2x00_async_login_done(vha, e->u.logio.fcport, 3945 e->u.logio.data); 3946 break; 3947 case QLA_EVT_ASYNC_LOGOUT: 3948 qla2x00_async_logout(vha, e->u.logio.fcport); 3949 break; 3950 case QLA_EVT_ASYNC_LOGOUT_DONE: 3951 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3952 e->u.logio.data); 3953 break; 3954 case QLA_EVT_ASYNC_ADISC: 3955 qla2x00_async_adisc(vha, e->u.logio.fcport, 3956 e->u.logio.data); 3957 break; 3958 case QLA_EVT_ASYNC_ADISC_DONE: 3959 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3960 e->u.logio.data); 3961 break; 3962 case QLA_EVT_UEVENT: 3963 qla2x00_uevent_emit(vha, e->u.uevent.code); 3964 break; 3965 case QLA_EVT_AENFX: 3966 qlafx00_process_aen(vha, e); 3967 break; 3968 } 3969 if (e->flags & QLA_EVT_FLAG_FREE) 3970 kfree(e); 3971 3972 /* For each work completed decrement vha ref count */ 3973 QLA_VHA_MARK_NOT_BUSY(vha); 3974 } 3975 } 3976 3977 /* Relogins all the fcports of a vport 3978 * Context: dpc thread 3979 */ 3980 void qla2x00_relogin(struct scsi_qla_host *vha) 3981 { 3982 fc_port_t *fcport; 3983 int status; 3984 uint16_t next_loopid = 0; 3985 struct qla_hw_data *ha = vha->hw; 3986 uint16_t data[2]; 3987 3988 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3989 /* 3990 * If the port is not ONLINE then try to login 3991 * to it if we haven't run out of retries. 3992 */ 3993 if (atomic_read(&fcport->state) != FCS_ONLINE && 3994 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3995 fcport->login_retry--; 3996 if (fcport->flags & FCF_FABRIC_DEVICE) { 3997 if (fcport->flags & FCF_FCP2_DEVICE) 3998 ha->isp_ops->fabric_logout(vha, 3999 fcport->loop_id, 4000 fcport->d_id.b.domain, 4001 fcport->d_id.b.area, 4002 fcport->d_id.b.al_pa); 4003 4004 if (fcport->loop_id == FC_NO_LOOP_ID) { 4005 fcport->loop_id = next_loopid = 4006 ha->min_external_loopid; 4007 status = qla2x00_find_new_loop_id( 4008 vha, fcport); 4009 if (status != QLA_SUCCESS) { 4010 /* Ran out of IDs to use */ 4011 break; 4012 } 4013 } 4014 4015 if (IS_ALOGIO_CAPABLE(ha)) { 4016 fcport->flags |= FCF_ASYNC_SENT; 4017 data[0] = 0; 4018 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4019 status = qla2x00_post_async_login_work( 4020 vha, fcport, data); 4021 if (status == QLA_SUCCESS) 4022 continue; 4023 /* Attempt a retry. */ 4024 status = 1; 4025 } else { 4026 status = qla2x00_fabric_login(vha, 4027 fcport, &next_loopid); 4028 if (status == QLA_SUCCESS) { 4029 int status2; 4030 uint8_t opts; 4031 4032 opts = 0; 4033 if (fcport->flags & 4034 FCF_FCP2_DEVICE) 4035 opts |= BIT_1; 4036 status2 = 4037 qla2x00_get_port_database( 4038 vha, fcport, opts); 4039 if (status2 != QLA_SUCCESS) 4040 status = 1; 4041 } 4042 } 4043 } else 4044 status = qla2x00_local_device_login(vha, 4045 fcport); 4046 4047 if (status == QLA_SUCCESS) { 4048 fcport->old_loop_id = fcport->loop_id; 4049 4050 ql_dbg(ql_dbg_disc, vha, 0x2003, 4051 "Port login OK: logged in ID 0x%x.\n", 4052 fcport->loop_id); 4053 4054 qla2x00_update_fcport(vha, fcport); 4055 4056 } else if (status == 1) { 4057 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4058 /* retry the login again */ 4059 ql_dbg(ql_dbg_disc, vha, 0x2007, 4060 "Retrying %d login again loop_id 0x%x.\n", 4061 fcport->login_retry, fcport->loop_id); 4062 } else { 4063 fcport->login_retry = 0; 4064 } 4065 4066 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4067 qla2x00_clear_loop_id(fcport); 4068 } 4069 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4070 break; 4071 } 4072 } 4073 4074 /* Schedule work on any of the dpc-workqueues */ 4075 void 4076 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4077 { 4078 struct qla_hw_data *ha = base_vha->hw; 4079 4080 switch (work_code) { 4081 case MBA_IDC_AEN: /* 0x8200 */ 4082 if (ha->dpc_lp_wq) 4083 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4084 break; 4085 4086 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4087 if (!ha->flags.nic_core_reset_hdlr_active) { 4088 if (ha->dpc_hp_wq) 4089 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4090 } else 4091 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4092 "NIC Core reset is already active. Skip " 4093 "scheduling it again.\n"); 4094 break; 4095 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4096 if (ha->dpc_hp_wq) 4097 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4098 break; 4099 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4100 if (ha->dpc_hp_wq) 4101 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4102 break; 4103 default: 4104 ql_log(ql_log_warn, base_vha, 0xb05f, 4105 "Unknow work-code=0x%x.\n", work_code); 4106 } 4107 4108 return; 4109 } 4110 4111 /* Work: Perform NIC Core Unrecoverable state handling */ 4112 void 4113 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4114 { 4115 struct qla_hw_data *ha = 4116 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4117 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4118 uint32_t dev_state = 0; 4119 4120 qla83xx_idc_lock(base_vha, 0); 4121 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4122 qla83xx_reset_ownership(base_vha); 4123 if (ha->flags.nic_core_reset_owner) { 4124 ha->flags.nic_core_reset_owner = 0; 4125 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4126 QLA8XXX_DEV_FAILED); 4127 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4128 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4129 } 4130 qla83xx_idc_unlock(base_vha, 0); 4131 } 4132 4133 /* Work: Execute IDC state handler */ 4134 void 4135 qla83xx_idc_state_handler_work(struct work_struct *work) 4136 { 4137 struct qla_hw_data *ha = 4138 container_of(work, struct qla_hw_data, idc_state_handler); 4139 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4140 uint32_t dev_state = 0; 4141 4142 qla83xx_idc_lock(base_vha, 0); 4143 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4144 if (dev_state == QLA8XXX_DEV_FAILED || 4145 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4146 qla83xx_idc_state_handler(base_vha); 4147 qla83xx_idc_unlock(base_vha, 0); 4148 } 4149 4150 static int 4151 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4152 { 4153 int rval = QLA_SUCCESS; 4154 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4155 uint32_t heart_beat_counter1, heart_beat_counter2; 4156 4157 do { 4158 if (time_after(jiffies, heart_beat_wait)) { 4159 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4160 "Nic Core f/w is not alive.\n"); 4161 rval = QLA_FUNCTION_FAILED; 4162 break; 4163 } 4164 4165 qla83xx_idc_lock(base_vha, 0); 4166 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4167 &heart_beat_counter1); 4168 qla83xx_idc_unlock(base_vha, 0); 4169 msleep(100); 4170 qla83xx_idc_lock(base_vha, 0); 4171 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4172 &heart_beat_counter2); 4173 qla83xx_idc_unlock(base_vha, 0); 4174 } while (heart_beat_counter1 == heart_beat_counter2); 4175 4176 return rval; 4177 } 4178 4179 /* Work: Perform NIC Core Reset handling */ 4180 void 4181 qla83xx_nic_core_reset_work(struct work_struct *work) 4182 { 4183 struct qla_hw_data *ha = 4184 container_of(work, struct qla_hw_data, nic_core_reset); 4185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4186 uint32_t dev_state = 0; 4187 4188 if (IS_QLA2031(ha)) { 4189 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4190 ql_log(ql_log_warn, base_vha, 0xb081, 4191 "Failed to dump mctp\n"); 4192 return; 4193 } 4194 4195 if (!ha->flags.nic_core_reset_hdlr_active) { 4196 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4197 qla83xx_idc_lock(base_vha, 0); 4198 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4199 &dev_state); 4200 qla83xx_idc_unlock(base_vha, 0); 4201 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4202 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4203 "Nic Core f/w is alive.\n"); 4204 return; 4205 } 4206 } 4207 4208 ha->flags.nic_core_reset_hdlr_active = 1; 4209 if (qla83xx_nic_core_reset(base_vha)) { 4210 /* NIC Core reset failed. */ 4211 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4212 "NIC Core reset failed.\n"); 4213 } 4214 ha->flags.nic_core_reset_hdlr_active = 0; 4215 } 4216 } 4217 4218 /* Work: Handle 8200 IDC aens */ 4219 void 4220 qla83xx_service_idc_aen(struct work_struct *work) 4221 { 4222 struct qla_hw_data *ha = 4223 container_of(work, struct qla_hw_data, idc_aen); 4224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4225 uint32_t dev_state, idc_control; 4226 4227 qla83xx_idc_lock(base_vha, 0); 4228 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4229 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4230 qla83xx_idc_unlock(base_vha, 0); 4231 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4232 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4233 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4234 "Application requested NIC Core Reset.\n"); 4235 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4236 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4237 QLA_SUCCESS) { 4238 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4239 "Other protocol driver requested NIC Core Reset.\n"); 4240 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4241 } 4242 } else if (dev_state == QLA8XXX_DEV_FAILED || 4243 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4244 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4245 } 4246 } 4247 4248 static void 4249 qla83xx_wait_logic(void) 4250 { 4251 int i; 4252 4253 /* Yield CPU */ 4254 if (!in_interrupt()) { 4255 /* 4256 * Wait about 200ms before retrying again. 4257 * This controls the number of retries for single 4258 * lock operation. 4259 */ 4260 msleep(100); 4261 schedule(); 4262 } else { 4263 for (i = 0; i < 20; i++) 4264 cpu_relax(); /* This a nop instr on i386 */ 4265 } 4266 } 4267 4268 static int 4269 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4270 { 4271 int rval; 4272 uint32_t data; 4273 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4274 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4275 struct qla_hw_data *ha = base_vha->hw; 4276 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4277 "Trying force recovery of the IDC lock.\n"); 4278 4279 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4280 if (rval) 4281 return rval; 4282 4283 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4284 return QLA_SUCCESS; 4285 } else { 4286 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4287 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4288 data); 4289 if (rval) 4290 return rval; 4291 4292 msleep(200); 4293 4294 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4295 &data); 4296 if (rval) 4297 return rval; 4298 4299 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4300 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4301 ~(idc_lck_rcvry_stage_mask)); 4302 rval = qla83xx_wr_reg(base_vha, 4303 QLA83XX_IDC_LOCK_RECOVERY, data); 4304 if (rval) 4305 return rval; 4306 4307 /* Forcefully perform IDC UnLock */ 4308 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4309 &data); 4310 if (rval) 4311 return rval; 4312 /* Clear lock-id by setting 0xff */ 4313 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4314 0xff); 4315 if (rval) 4316 return rval; 4317 /* Clear lock-recovery by setting 0x0 */ 4318 rval = qla83xx_wr_reg(base_vha, 4319 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4320 if (rval) 4321 return rval; 4322 } else 4323 return QLA_SUCCESS; 4324 } 4325 4326 return rval; 4327 } 4328 4329 static int 4330 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4331 { 4332 int rval = QLA_SUCCESS; 4333 uint32_t o_drv_lockid, n_drv_lockid; 4334 unsigned long lock_recovery_timeout; 4335 4336 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4337 retry_lockid: 4338 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4339 if (rval) 4340 goto exit; 4341 4342 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4343 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4344 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4345 return QLA_SUCCESS; 4346 else 4347 return QLA_FUNCTION_FAILED; 4348 } 4349 4350 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4351 if (rval) 4352 goto exit; 4353 4354 if (o_drv_lockid == n_drv_lockid) { 4355 qla83xx_wait_logic(); 4356 goto retry_lockid; 4357 } else 4358 return QLA_SUCCESS; 4359 4360 exit: 4361 return rval; 4362 } 4363 4364 void 4365 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4366 { 4367 uint16_t options = (requester_id << 15) | BIT_6; 4368 uint32_t data; 4369 uint32_t lock_owner; 4370 struct qla_hw_data *ha = base_vha->hw; 4371 4372 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4373 retry_lock: 4374 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4375 == QLA_SUCCESS) { 4376 if (data) { 4377 /* Setting lock-id to our function-number */ 4378 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4379 ha->portnum); 4380 } else { 4381 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4382 &lock_owner); 4383 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4384 "Failed to acquire IDC lock, acquired by %d, " 4385 "retrying...\n", lock_owner); 4386 4387 /* Retry/Perform IDC-Lock recovery */ 4388 if (qla83xx_idc_lock_recovery(base_vha) 4389 == QLA_SUCCESS) { 4390 qla83xx_wait_logic(); 4391 goto retry_lock; 4392 } else 4393 ql_log(ql_log_warn, base_vha, 0xb075, 4394 "IDC Lock recovery FAILED.\n"); 4395 } 4396 4397 } 4398 4399 return; 4400 4401 /* XXX: IDC-lock implementation using access-control mbx */ 4402 retry_lock2: 4403 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4404 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4405 "Failed to acquire IDC lock. retrying...\n"); 4406 /* Retry/Perform IDC-Lock recovery */ 4407 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4408 qla83xx_wait_logic(); 4409 goto retry_lock2; 4410 } else 4411 ql_log(ql_log_warn, base_vha, 0xb076, 4412 "IDC Lock recovery FAILED.\n"); 4413 } 4414 4415 return; 4416 } 4417 4418 void 4419 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4420 { 4421 uint16_t options = (requester_id << 15) | BIT_7, retry; 4422 uint32_t data; 4423 struct qla_hw_data *ha = base_vha->hw; 4424 4425 /* IDC-unlock implementation using driver-unlock/lock-id 4426 * remote registers 4427 */ 4428 retry = 0; 4429 retry_unlock: 4430 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4431 == QLA_SUCCESS) { 4432 if (data == ha->portnum) { 4433 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4434 /* Clearing lock-id by setting 0xff */ 4435 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4436 } else if (retry < 10) { 4437 /* SV: XXX: IDC unlock retrying needed here? */ 4438 4439 /* Retry for IDC-unlock */ 4440 qla83xx_wait_logic(); 4441 retry++; 4442 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4443 "Failed to release IDC lock, retyring=%d\n", retry); 4444 goto retry_unlock; 4445 } 4446 } else if (retry < 10) { 4447 /* Retry for IDC-unlock */ 4448 qla83xx_wait_logic(); 4449 retry++; 4450 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4451 "Failed to read drv-lockid, retyring=%d\n", retry); 4452 goto retry_unlock; 4453 } 4454 4455 return; 4456 4457 /* XXX: IDC-unlock implementation using access-control mbx */ 4458 retry = 0; 4459 retry_unlock2: 4460 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4461 if (retry < 10) { 4462 /* Retry for IDC-unlock */ 4463 qla83xx_wait_logic(); 4464 retry++; 4465 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4466 "Failed to release IDC lock, retyring=%d\n", retry); 4467 goto retry_unlock2; 4468 } 4469 } 4470 4471 return; 4472 } 4473 4474 int 4475 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4476 { 4477 int rval = QLA_SUCCESS; 4478 struct qla_hw_data *ha = vha->hw; 4479 uint32_t drv_presence; 4480 4481 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4482 if (rval == QLA_SUCCESS) { 4483 drv_presence |= (1 << ha->portnum); 4484 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4485 drv_presence); 4486 } 4487 4488 return rval; 4489 } 4490 4491 int 4492 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4493 { 4494 int rval = QLA_SUCCESS; 4495 4496 qla83xx_idc_lock(vha, 0); 4497 rval = __qla83xx_set_drv_presence(vha); 4498 qla83xx_idc_unlock(vha, 0); 4499 4500 return rval; 4501 } 4502 4503 int 4504 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4505 { 4506 int rval = QLA_SUCCESS; 4507 struct qla_hw_data *ha = vha->hw; 4508 uint32_t drv_presence; 4509 4510 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4511 if (rval == QLA_SUCCESS) { 4512 drv_presence &= ~(1 << ha->portnum); 4513 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4514 drv_presence); 4515 } 4516 4517 return rval; 4518 } 4519 4520 int 4521 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4522 { 4523 int rval = QLA_SUCCESS; 4524 4525 qla83xx_idc_lock(vha, 0); 4526 rval = __qla83xx_clear_drv_presence(vha); 4527 qla83xx_idc_unlock(vha, 0); 4528 4529 return rval; 4530 } 4531 4532 static void 4533 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4534 { 4535 struct qla_hw_data *ha = vha->hw; 4536 uint32_t drv_ack, drv_presence; 4537 unsigned long ack_timeout; 4538 4539 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4540 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4541 while (1) { 4542 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4543 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4544 if ((drv_ack & drv_presence) == drv_presence) 4545 break; 4546 4547 if (time_after_eq(jiffies, ack_timeout)) { 4548 ql_log(ql_log_warn, vha, 0xb067, 4549 "RESET ACK TIMEOUT! drv_presence=0x%x " 4550 "drv_ack=0x%x\n", drv_presence, drv_ack); 4551 /* 4552 * The function(s) which did not ack in time are forced 4553 * to withdraw any further participation in the IDC 4554 * reset. 4555 */ 4556 if (drv_ack != drv_presence) 4557 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4558 drv_ack); 4559 break; 4560 } 4561 4562 qla83xx_idc_unlock(vha, 0); 4563 msleep(1000); 4564 qla83xx_idc_lock(vha, 0); 4565 } 4566 4567 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4568 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4569 } 4570 4571 static int 4572 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4573 { 4574 int rval = QLA_SUCCESS; 4575 uint32_t idc_control; 4576 4577 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4578 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4579 4580 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4581 __qla83xx_get_idc_control(vha, &idc_control); 4582 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4583 __qla83xx_set_idc_control(vha, 0); 4584 4585 qla83xx_idc_unlock(vha, 0); 4586 rval = qla83xx_restart_nic_firmware(vha); 4587 qla83xx_idc_lock(vha, 0); 4588 4589 if (rval != QLA_SUCCESS) { 4590 ql_log(ql_log_fatal, vha, 0xb06a, 4591 "Failed to restart NIC f/w.\n"); 4592 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4593 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4594 } else { 4595 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4596 "Success in restarting nic f/w.\n"); 4597 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4598 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4599 } 4600 4601 return rval; 4602 } 4603 4604 /* Assumes idc_lock always held on entry */ 4605 int 4606 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4607 { 4608 struct qla_hw_data *ha = base_vha->hw; 4609 int rval = QLA_SUCCESS; 4610 unsigned long dev_init_timeout; 4611 uint32_t dev_state; 4612 4613 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4614 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4615 4616 while (1) { 4617 4618 if (time_after_eq(jiffies, dev_init_timeout)) { 4619 ql_log(ql_log_warn, base_vha, 0xb06e, 4620 "Initialization TIMEOUT!\n"); 4621 /* Init timeout. Disable further NIC Core 4622 * communication. 4623 */ 4624 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4625 QLA8XXX_DEV_FAILED); 4626 ql_log(ql_log_info, base_vha, 0xb06f, 4627 "HW State: FAILED.\n"); 4628 } 4629 4630 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4631 switch (dev_state) { 4632 case QLA8XXX_DEV_READY: 4633 if (ha->flags.nic_core_reset_owner) 4634 qla83xx_idc_audit(base_vha, 4635 IDC_AUDIT_COMPLETION); 4636 ha->flags.nic_core_reset_owner = 0; 4637 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4638 "Reset_owner reset by 0x%x.\n", 4639 ha->portnum); 4640 goto exit; 4641 case QLA8XXX_DEV_COLD: 4642 if (ha->flags.nic_core_reset_owner) 4643 rval = qla83xx_device_bootstrap(base_vha); 4644 else { 4645 /* Wait for AEN to change device-state */ 4646 qla83xx_idc_unlock(base_vha, 0); 4647 msleep(1000); 4648 qla83xx_idc_lock(base_vha, 0); 4649 } 4650 break; 4651 case QLA8XXX_DEV_INITIALIZING: 4652 /* Wait for AEN to change device-state */ 4653 qla83xx_idc_unlock(base_vha, 0); 4654 msleep(1000); 4655 qla83xx_idc_lock(base_vha, 0); 4656 break; 4657 case QLA8XXX_DEV_NEED_RESET: 4658 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4659 qla83xx_need_reset_handler(base_vha); 4660 else { 4661 /* Wait for AEN to change device-state */ 4662 qla83xx_idc_unlock(base_vha, 0); 4663 msleep(1000); 4664 qla83xx_idc_lock(base_vha, 0); 4665 } 4666 /* reset timeout value after need reset handler */ 4667 dev_init_timeout = jiffies + 4668 (ha->fcoe_dev_init_timeout * HZ); 4669 break; 4670 case QLA8XXX_DEV_NEED_QUIESCENT: 4671 /* XXX: DEBUG for now */ 4672 qla83xx_idc_unlock(base_vha, 0); 4673 msleep(1000); 4674 qla83xx_idc_lock(base_vha, 0); 4675 break; 4676 case QLA8XXX_DEV_QUIESCENT: 4677 /* XXX: DEBUG for now */ 4678 if (ha->flags.quiesce_owner) 4679 goto exit; 4680 4681 qla83xx_idc_unlock(base_vha, 0); 4682 msleep(1000); 4683 qla83xx_idc_lock(base_vha, 0); 4684 dev_init_timeout = jiffies + 4685 (ha->fcoe_dev_init_timeout * HZ); 4686 break; 4687 case QLA8XXX_DEV_FAILED: 4688 if (ha->flags.nic_core_reset_owner) 4689 qla83xx_idc_audit(base_vha, 4690 IDC_AUDIT_COMPLETION); 4691 ha->flags.nic_core_reset_owner = 0; 4692 __qla83xx_clear_drv_presence(base_vha); 4693 qla83xx_idc_unlock(base_vha, 0); 4694 qla8xxx_dev_failed_handler(base_vha); 4695 rval = QLA_FUNCTION_FAILED; 4696 qla83xx_idc_lock(base_vha, 0); 4697 goto exit; 4698 case QLA8XXX_BAD_VALUE: 4699 qla83xx_idc_unlock(base_vha, 0); 4700 msleep(1000); 4701 qla83xx_idc_lock(base_vha, 0); 4702 break; 4703 default: 4704 ql_log(ql_log_warn, base_vha, 0xb071, 4705 "Unknow Device State: %x.\n", dev_state); 4706 qla83xx_idc_unlock(base_vha, 0); 4707 qla8xxx_dev_failed_handler(base_vha); 4708 rval = QLA_FUNCTION_FAILED; 4709 qla83xx_idc_lock(base_vha, 0); 4710 goto exit; 4711 } 4712 } 4713 4714 exit: 4715 return rval; 4716 } 4717 4718 void 4719 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4720 { 4721 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4722 board_disable); 4723 struct pci_dev *pdev = ha->pdev; 4724 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4725 4726 ql_log(ql_log_warn, base_vha, 0x015b, 4727 "Disabling adapter.\n"); 4728 4729 set_bit(UNLOADING, &base_vha->dpc_flags); 4730 4731 qla2x00_delete_all_vps(ha, base_vha); 4732 4733 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4734 4735 qla2x00_dfs_remove(base_vha); 4736 4737 qla84xx_put_chip(base_vha); 4738 4739 if (base_vha->timer_active) 4740 qla2x00_stop_timer(base_vha); 4741 4742 base_vha->flags.online = 0; 4743 4744 qla2x00_destroy_deferred_work(ha); 4745 4746 /* 4747 * Do not try to stop beacon blink as it will issue a mailbox 4748 * command. 4749 */ 4750 qla2x00_free_sysfs_attr(base_vha, false); 4751 4752 fc_remove_host(base_vha->host); 4753 4754 scsi_remove_host(base_vha->host); 4755 4756 base_vha->flags.init_done = 0; 4757 qla25xx_delete_queues(base_vha); 4758 qla2x00_free_irqs(base_vha); 4759 qla2x00_free_fcports(base_vha); 4760 qla2x00_mem_free(ha); 4761 qla82xx_md_free(base_vha); 4762 qla2x00_free_queues(ha); 4763 4764 qla2x00_unmap_iobases(ha); 4765 4766 pci_release_selected_regions(ha->pdev, ha->bars); 4767 pci_disable_pcie_error_reporting(pdev); 4768 pci_disable_device(pdev); 4769 4770 /* 4771 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 4772 */ 4773 } 4774 4775 /************************************************************************** 4776 * qla2x00_do_dpc 4777 * This kernel thread is a task that is schedule by the interrupt handler 4778 * to perform the background processing for interrupts. 4779 * 4780 * Notes: 4781 * This task always run in the context of a kernel thread. It 4782 * is kick-off by the driver's detect code and starts up 4783 * up one per adapter. It immediately goes to sleep and waits for 4784 * some fibre event. When either the interrupt handler or 4785 * the timer routine detects a event it will one of the task 4786 * bits then wake us up. 4787 **************************************************************************/ 4788 static int 4789 qla2x00_do_dpc(void *data) 4790 { 4791 int rval; 4792 scsi_qla_host_t *base_vha; 4793 struct qla_hw_data *ha; 4794 4795 ha = (struct qla_hw_data *)data; 4796 base_vha = pci_get_drvdata(ha->pdev); 4797 4798 set_user_nice(current, MIN_NICE); 4799 4800 set_current_state(TASK_INTERRUPTIBLE); 4801 while (!kthread_should_stop()) { 4802 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4803 "DPC handler sleeping.\n"); 4804 4805 schedule(); 4806 4807 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4808 goto end_loop; 4809 4810 if (ha->flags.eeh_busy) { 4811 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4812 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4813 goto end_loop; 4814 } 4815 4816 ha->dpc_active = 1; 4817 4818 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4819 "DPC handler waking up, dpc_flags=0x%lx.\n", 4820 base_vha->dpc_flags); 4821 4822 qla2x00_do_work(base_vha); 4823 4824 if (IS_P3P_TYPE(ha)) { 4825 if (IS_QLA8044(ha)) { 4826 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4827 &base_vha->dpc_flags)) { 4828 qla8044_idc_lock(ha); 4829 qla8044_wr_direct(base_vha, 4830 QLA8044_CRB_DEV_STATE_INDEX, 4831 QLA8XXX_DEV_FAILED); 4832 qla8044_idc_unlock(ha); 4833 ql_log(ql_log_info, base_vha, 0x4004, 4834 "HW State: FAILED.\n"); 4835 qla8044_device_state_handler(base_vha); 4836 continue; 4837 } 4838 4839 } else { 4840 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4841 &base_vha->dpc_flags)) { 4842 qla82xx_idc_lock(ha); 4843 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4844 QLA8XXX_DEV_FAILED); 4845 qla82xx_idc_unlock(ha); 4846 ql_log(ql_log_info, base_vha, 0x0151, 4847 "HW State: FAILED.\n"); 4848 qla82xx_device_state_handler(base_vha); 4849 continue; 4850 } 4851 } 4852 4853 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 4854 &base_vha->dpc_flags)) { 4855 4856 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 4857 "FCoE context reset scheduled.\n"); 4858 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4859 &base_vha->dpc_flags))) { 4860 if (qla82xx_fcoe_ctx_reset(base_vha)) { 4861 /* FCoE-ctx reset failed. 4862 * Escalate to chip-reset 4863 */ 4864 set_bit(ISP_ABORT_NEEDED, 4865 &base_vha->dpc_flags); 4866 } 4867 clear_bit(ABORT_ISP_ACTIVE, 4868 &base_vha->dpc_flags); 4869 } 4870 4871 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 4872 "FCoE context reset end.\n"); 4873 } 4874 } else if (IS_QLAFX00(ha)) { 4875 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4876 &base_vha->dpc_flags)) { 4877 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 4878 "Firmware Reset Recovery\n"); 4879 if (qlafx00_reset_initialize(base_vha)) { 4880 /* Failed. Abort isp later. */ 4881 if (!test_bit(UNLOADING, 4882 &base_vha->dpc_flags)) { 4883 set_bit(ISP_UNRECOVERABLE, 4884 &base_vha->dpc_flags); 4885 ql_dbg(ql_dbg_dpc, base_vha, 4886 0x4021, 4887 "Reset Recovery Failed\n"); 4888 } 4889 } 4890 } 4891 4892 if (test_and_clear_bit(FX00_TARGET_SCAN, 4893 &base_vha->dpc_flags)) { 4894 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 4895 "ISPFx00 Target Scan scheduled\n"); 4896 if (qlafx00_rescan_isp(base_vha)) { 4897 if (!test_bit(UNLOADING, 4898 &base_vha->dpc_flags)) 4899 set_bit(ISP_UNRECOVERABLE, 4900 &base_vha->dpc_flags); 4901 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 4902 "ISPFx00 Target Scan Failed\n"); 4903 } 4904 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 4905 "ISPFx00 Target Scan End\n"); 4906 } 4907 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 4908 &base_vha->dpc_flags)) { 4909 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 4910 "ISPFx00 Host Info resend scheduled\n"); 4911 qlafx00_fx_disc(base_vha, 4912 &base_vha->hw->mr.fcport, 4913 FXDISC_REG_HOST_INFO); 4914 } 4915 } 4916 4917 if (test_and_clear_bit(ISP_ABORT_NEEDED, 4918 &base_vha->dpc_flags)) { 4919 4920 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 4921 "ISP abort scheduled.\n"); 4922 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4923 &base_vha->dpc_flags))) { 4924 4925 if (ha->isp_ops->abort_isp(base_vha)) { 4926 /* failed. retry later */ 4927 set_bit(ISP_ABORT_NEEDED, 4928 &base_vha->dpc_flags); 4929 } 4930 clear_bit(ABORT_ISP_ACTIVE, 4931 &base_vha->dpc_flags); 4932 } 4933 4934 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 4935 "ISP abort end.\n"); 4936 } 4937 4938 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 4939 &base_vha->dpc_flags)) { 4940 qla2x00_update_fcports(base_vha); 4941 } 4942 4943 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 4944 int ret; 4945 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 4946 if (ret != QLA_SUCCESS) 4947 ql_log(ql_log_warn, base_vha, 0x121, 4948 "Failed to enable receiving of RSCN " 4949 "requests: 0x%x.\n", ret); 4950 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 4951 } 4952 4953 if (IS_QLAFX00(ha)) 4954 goto loop_resync_check; 4955 4956 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 4957 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 4958 "Quiescence mode scheduled.\n"); 4959 if (IS_P3P_TYPE(ha)) { 4960 if (IS_QLA82XX(ha)) 4961 qla82xx_device_state_handler(base_vha); 4962 if (IS_QLA8044(ha)) 4963 qla8044_device_state_handler(base_vha); 4964 clear_bit(ISP_QUIESCE_NEEDED, 4965 &base_vha->dpc_flags); 4966 if (!ha->flags.quiesce_owner) { 4967 qla2x00_perform_loop_resync(base_vha); 4968 if (IS_QLA82XX(ha)) { 4969 qla82xx_idc_lock(ha); 4970 qla82xx_clear_qsnt_ready( 4971 base_vha); 4972 qla82xx_idc_unlock(ha); 4973 } else if (IS_QLA8044(ha)) { 4974 qla8044_idc_lock(ha); 4975 qla8044_clear_qsnt_ready( 4976 base_vha); 4977 qla8044_idc_unlock(ha); 4978 } 4979 } 4980 } else { 4981 clear_bit(ISP_QUIESCE_NEEDED, 4982 &base_vha->dpc_flags); 4983 qla2x00_quiesce_io(base_vha); 4984 } 4985 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 4986 "Quiescence mode end.\n"); 4987 } 4988 4989 if (test_and_clear_bit(RESET_MARKER_NEEDED, 4990 &base_vha->dpc_flags) && 4991 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 4992 4993 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 4994 "Reset marker scheduled.\n"); 4995 qla2x00_rst_aen(base_vha); 4996 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 4997 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 4998 "Reset marker end.\n"); 4999 } 5000 5001 /* Retry each device up to login retry count */ 5002 if ((test_and_clear_bit(RELOGIN_NEEDED, 5003 &base_vha->dpc_flags)) && 5004 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5005 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5006 5007 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5008 "Relogin scheduled.\n"); 5009 qla2x00_relogin(base_vha); 5010 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5011 "Relogin end.\n"); 5012 } 5013 loop_resync_check: 5014 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5015 &base_vha->dpc_flags)) { 5016 5017 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5018 "Loop resync scheduled.\n"); 5019 5020 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5021 &base_vha->dpc_flags))) { 5022 5023 rval = qla2x00_loop_resync(base_vha); 5024 5025 clear_bit(LOOP_RESYNC_ACTIVE, 5026 &base_vha->dpc_flags); 5027 } 5028 5029 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5030 "Loop resync end.\n"); 5031 } 5032 5033 if (IS_QLAFX00(ha)) 5034 goto intr_on_check; 5035 5036 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5037 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5038 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5039 qla2xxx_flash_npiv_conf(base_vha); 5040 } 5041 5042 intr_on_check: 5043 if (!ha->interrupts_on) 5044 ha->isp_ops->enable_intrs(ha); 5045 5046 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5047 &base_vha->dpc_flags)) { 5048 if (ha->beacon_blink_led == 1) 5049 ha->isp_ops->beacon_blink(base_vha); 5050 } 5051 5052 if (!IS_QLAFX00(ha)) 5053 qla2x00_do_dpc_all_vps(base_vha); 5054 5055 ha->dpc_active = 0; 5056 end_loop: 5057 set_current_state(TASK_INTERRUPTIBLE); 5058 } /* End of while(1) */ 5059 __set_current_state(TASK_RUNNING); 5060 5061 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5062 "DPC handler exiting.\n"); 5063 5064 /* 5065 * Make sure that nobody tries to wake us up again. 5066 */ 5067 ha->dpc_active = 0; 5068 5069 /* Cleanup any residual CTX SRBs. */ 5070 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5071 5072 return 0; 5073 } 5074 5075 void 5076 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5077 { 5078 struct qla_hw_data *ha = vha->hw; 5079 struct task_struct *t = ha->dpc_thread; 5080 5081 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5082 wake_up_process(t); 5083 } 5084 5085 /* 5086 * qla2x00_rst_aen 5087 * Processes asynchronous reset. 5088 * 5089 * Input: 5090 * ha = adapter block pointer. 5091 */ 5092 static void 5093 qla2x00_rst_aen(scsi_qla_host_t *vha) 5094 { 5095 if (vha->flags.online && !vha->flags.reset_active && 5096 !atomic_read(&vha->loop_down_timer) && 5097 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5098 do { 5099 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5100 5101 /* 5102 * Issue marker command only when we are going to start 5103 * the I/O. 5104 */ 5105 vha->marker_needed = 1; 5106 } while (!atomic_read(&vha->loop_down_timer) && 5107 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5108 } 5109 } 5110 5111 /************************************************************************** 5112 * qla2x00_timer 5113 * 5114 * Description: 5115 * One second timer 5116 * 5117 * Context: Interrupt 5118 ***************************************************************************/ 5119 void 5120 qla2x00_timer(scsi_qla_host_t *vha) 5121 { 5122 unsigned long cpu_flags = 0; 5123 int start_dpc = 0; 5124 int index; 5125 srb_t *sp; 5126 uint16_t w; 5127 struct qla_hw_data *ha = vha->hw; 5128 struct req_que *req; 5129 5130 if (ha->flags.eeh_busy) { 5131 ql_dbg(ql_dbg_timer, vha, 0x6000, 5132 "EEH = %d, restarting timer.\n", 5133 ha->flags.eeh_busy); 5134 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5135 return; 5136 } 5137 5138 /* 5139 * Hardware read to raise pending EEH errors during mailbox waits. If 5140 * the read returns -1 then disable the board. 5141 */ 5142 if (!pci_channel_offline(ha->pdev)) { 5143 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5144 qla2x00_check_reg16_for_disconnect(vha, w); 5145 } 5146 5147 /* Make sure qla82xx_watchdog is run only for physical port */ 5148 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5149 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5150 start_dpc++; 5151 if (IS_QLA82XX(ha)) 5152 qla82xx_watchdog(vha); 5153 else if (IS_QLA8044(ha)) 5154 qla8044_watchdog(vha); 5155 } 5156 5157 if (!vha->vp_idx && IS_QLAFX00(ha)) 5158 qlafx00_timer_routine(vha); 5159 5160 /* Loop down handler. */ 5161 if (atomic_read(&vha->loop_down_timer) > 0 && 5162 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5163 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5164 && vha->flags.online) { 5165 5166 if (atomic_read(&vha->loop_down_timer) == 5167 vha->loop_down_abort_time) { 5168 5169 ql_log(ql_log_info, vha, 0x6008, 5170 "Loop down - aborting the queues before time expires.\n"); 5171 5172 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5173 atomic_set(&vha->loop_state, LOOP_DEAD); 5174 5175 /* 5176 * Schedule an ISP abort to return any FCP2-device 5177 * commands. 5178 */ 5179 /* NPIV - scan physical port only */ 5180 if (!vha->vp_idx) { 5181 spin_lock_irqsave(&ha->hardware_lock, 5182 cpu_flags); 5183 req = ha->req_q_map[0]; 5184 for (index = 1; 5185 index < req->num_outstanding_cmds; 5186 index++) { 5187 fc_port_t *sfcp; 5188 5189 sp = req->outstanding_cmds[index]; 5190 if (!sp) 5191 continue; 5192 if (sp->type != SRB_SCSI_CMD) 5193 continue; 5194 sfcp = sp->fcport; 5195 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5196 continue; 5197 5198 if (IS_QLA82XX(ha)) 5199 set_bit(FCOE_CTX_RESET_NEEDED, 5200 &vha->dpc_flags); 5201 else 5202 set_bit(ISP_ABORT_NEEDED, 5203 &vha->dpc_flags); 5204 break; 5205 } 5206 spin_unlock_irqrestore(&ha->hardware_lock, 5207 cpu_flags); 5208 } 5209 start_dpc++; 5210 } 5211 5212 /* if the loop has been down for 4 minutes, reinit adapter */ 5213 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5214 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5215 ql_log(ql_log_warn, vha, 0x6009, 5216 "Loop down - aborting ISP.\n"); 5217 5218 if (IS_QLA82XX(ha)) 5219 set_bit(FCOE_CTX_RESET_NEEDED, 5220 &vha->dpc_flags); 5221 else 5222 set_bit(ISP_ABORT_NEEDED, 5223 &vha->dpc_flags); 5224 } 5225 } 5226 ql_dbg(ql_dbg_timer, vha, 0x600a, 5227 "Loop down - seconds remaining %d.\n", 5228 atomic_read(&vha->loop_down_timer)); 5229 } 5230 /* Check if beacon LED needs to be blinked for physical host only */ 5231 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5232 /* There is no beacon_blink function for ISP82xx */ 5233 if (!IS_P3P_TYPE(ha)) { 5234 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5235 start_dpc++; 5236 } 5237 } 5238 5239 /* Process any deferred work. */ 5240 if (!list_empty(&vha->work_list)) 5241 start_dpc++; 5242 5243 /* Schedule the DPC routine if needed */ 5244 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5245 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5246 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5247 start_dpc || 5248 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5249 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5250 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5251 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5252 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5253 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5254 ql_dbg(ql_dbg_timer, vha, 0x600b, 5255 "isp_abort_needed=%d loop_resync_needed=%d " 5256 "fcport_update_needed=%d start_dpc=%d " 5257 "reset_marker_needed=%d", 5258 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5259 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5260 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5261 start_dpc, 5262 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5263 ql_dbg(ql_dbg_timer, vha, 0x600c, 5264 "beacon_blink_needed=%d isp_unrecoverable=%d " 5265 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5266 "relogin_needed=%d.\n", 5267 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5268 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5269 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5270 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5271 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5272 qla2xxx_wake_dpc(vha); 5273 } 5274 5275 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5276 } 5277 5278 /* Firmware interface routines. */ 5279 5280 #define FW_BLOBS 11 5281 #define FW_ISP21XX 0 5282 #define FW_ISP22XX 1 5283 #define FW_ISP2300 2 5284 #define FW_ISP2322 3 5285 #define FW_ISP24XX 4 5286 #define FW_ISP25XX 5 5287 #define FW_ISP81XX 6 5288 #define FW_ISP82XX 7 5289 #define FW_ISP2031 8 5290 #define FW_ISP8031 9 5291 #define FW_ISP27XX 10 5292 5293 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5294 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5295 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5296 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5297 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5298 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5299 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5300 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5301 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5302 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5303 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5304 5305 5306 static DEFINE_MUTEX(qla_fw_lock); 5307 5308 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5309 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5310 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5311 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5312 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5313 { .name = FW_FILE_ISP24XX, }, 5314 { .name = FW_FILE_ISP25XX, }, 5315 { .name = FW_FILE_ISP81XX, }, 5316 { .name = FW_FILE_ISP82XX, }, 5317 { .name = FW_FILE_ISP2031, }, 5318 { .name = FW_FILE_ISP8031, }, 5319 { .name = FW_FILE_ISP27XX, }, 5320 }; 5321 5322 struct fw_blob * 5323 qla2x00_request_firmware(scsi_qla_host_t *vha) 5324 { 5325 struct qla_hw_data *ha = vha->hw; 5326 struct fw_blob *blob; 5327 5328 if (IS_QLA2100(ha)) { 5329 blob = &qla_fw_blobs[FW_ISP21XX]; 5330 } else if (IS_QLA2200(ha)) { 5331 blob = &qla_fw_blobs[FW_ISP22XX]; 5332 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5333 blob = &qla_fw_blobs[FW_ISP2300]; 5334 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5335 blob = &qla_fw_blobs[FW_ISP2322]; 5336 } else if (IS_QLA24XX_TYPE(ha)) { 5337 blob = &qla_fw_blobs[FW_ISP24XX]; 5338 } else if (IS_QLA25XX(ha)) { 5339 blob = &qla_fw_blobs[FW_ISP25XX]; 5340 } else if (IS_QLA81XX(ha)) { 5341 blob = &qla_fw_blobs[FW_ISP81XX]; 5342 } else if (IS_QLA82XX(ha)) { 5343 blob = &qla_fw_blobs[FW_ISP82XX]; 5344 } else if (IS_QLA2031(ha)) { 5345 blob = &qla_fw_blobs[FW_ISP2031]; 5346 } else if (IS_QLA8031(ha)) { 5347 blob = &qla_fw_blobs[FW_ISP8031]; 5348 } else if (IS_QLA27XX(ha)) { 5349 blob = &qla_fw_blobs[FW_ISP27XX]; 5350 } else { 5351 return NULL; 5352 } 5353 5354 mutex_lock(&qla_fw_lock); 5355 if (blob->fw) 5356 goto out; 5357 5358 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5359 ql_log(ql_log_warn, vha, 0x0063, 5360 "Failed to load firmware image (%s).\n", blob->name); 5361 blob->fw = NULL; 5362 blob = NULL; 5363 goto out; 5364 } 5365 5366 out: 5367 mutex_unlock(&qla_fw_lock); 5368 return blob; 5369 } 5370 5371 static void 5372 qla2x00_release_firmware(void) 5373 { 5374 int idx; 5375 5376 mutex_lock(&qla_fw_lock); 5377 for (idx = 0; idx < FW_BLOBS; idx++) 5378 release_firmware(qla_fw_blobs[idx].fw); 5379 mutex_unlock(&qla_fw_lock); 5380 } 5381 5382 static pci_ers_result_t 5383 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5384 { 5385 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5386 struct qla_hw_data *ha = vha->hw; 5387 5388 ql_dbg(ql_dbg_aer, vha, 0x9000, 5389 "PCI error detected, state %x.\n", state); 5390 5391 switch (state) { 5392 case pci_channel_io_normal: 5393 ha->flags.eeh_busy = 0; 5394 return PCI_ERS_RESULT_CAN_RECOVER; 5395 case pci_channel_io_frozen: 5396 ha->flags.eeh_busy = 1; 5397 /* For ISP82XX complete any pending mailbox cmd */ 5398 if (IS_QLA82XX(ha)) { 5399 ha->flags.isp82xx_fw_hung = 1; 5400 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5401 qla82xx_clear_pending_mbx(vha); 5402 } 5403 qla2x00_free_irqs(vha); 5404 pci_disable_device(pdev); 5405 /* Return back all IOs */ 5406 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5407 return PCI_ERS_RESULT_NEED_RESET; 5408 case pci_channel_io_perm_failure: 5409 ha->flags.pci_channel_io_perm_failure = 1; 5410 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5411 return PCI_ERS_RESULT_DISCONNECT; 5412 } 5413 return PCI_ERS_RESULT_NEED_RESET; 5414 } 5415 5416 static pci_ers_result_t 5417 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5418 { 5419 int risc_paused = 0; 5420 uint32_t stat; 5421 unsigned long flags; 5422 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5423 struct qla_hw_data *ha = base_vha->hw; 5424 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5425 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5426 5427 if (IS_QLA82XX(ha)) 5428 return PCI_ERS_RESULT_RECOVERED; 5429 5430 spin_lock_irqsave(&ha->hardware_lock, flags); 5431 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5432 stat = RD_REG_DWORD(®->hccr); 5433 if (stat & HCCR_RISC_PAUSE) 5434 risc_paused = 1; 5435 } else if (IS_QLA23XX(ha)) { 5436 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5437 if (stat & HSR_RISC_PAUSED) 5438 risc_paused = 1; 5439 } else if (IS_FWI2_CAPABLE(ha)) { 5440 stat = RD_REG_DWORD(®24->host_status); 5441 if (stat & HSRX_RISC_PAUSED) 5442 risc_paused = 1; 5443 } 5444 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5445 5446 if (risc_paused) { 5447 ql_log(ql_log_info, base_vha, 0x9003, 5448 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5449 ha->isp_ops->fw_dump(base_vha, 0); 5450 5451 return PCI_ERS_RESULT_NEED_RESET; 5452 } else 5453 return PCI_ERS_RESULT_RECOVERED; 5454 } 5455 5456 static uint32_t 5457 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5458 { 5459 uint32_t rval = QLA_FUNCTION_FAILED; 5460 uint32_t drv_active = 0; 5461 struct qla_hw_data *ha = base_vha->hw; 5462 int fn; 5463 struct pci_dev *other_pdev = NULL; 5464 5465 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5466 "Entered %s.\n", __func__); 5467 5468 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5469 5470 if (base_vha->flags.online) { 5471 /* Abort all outstanding commands, 5472 * so as to be requeued later */ 5473 qla2x00_abort_isp_cleanup(base_vha); 5474 } 5475 5476 5477 fn = PCI_FUNC(ha->pdev->devfn); 5478 while (fn > 0) { 5479 fn--; 5480 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5481 "Finding pci device at function = 0x%x.\n", fn); 5482 other_pdev = 5483 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5484 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5485 fn)); 5486 5487 if (!other_pdev) 5488 continue; 5489 if (atomic_read(&other_pdev->enable_cnt)) { 5490 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5491 "Found PCI func available and enable at 0x%x.\n", 5492 fn); 5493 pci_dev_put(other_pdev); 5494 break; 5495 } 5496 pci_dev_put(other_pdev); 5497 } 5498 5499 if (!fn) { 5500 /* Reset owner */ 5501 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5502 "This devfn is reset owner = 0x%x.\n", 5503 ha->pdev->devfn); 5504 qla82xx_idc_lock(ha); 5505 5506 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5507 QLA8XXX_DEV_INITIALIZING); 5508 5509 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5510 QLA82XX_IDC_VERSION); 5511 5512 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5513 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5514 "drv_active = 0x%x.\n", drv_active); 5515 5516 qla82xx_idc_unlock(ha); 5517 /* Reset if device is not already reset 5518 * drv_active would be 0 if a reset has already been done 5519 */ 5520 if (drv_active) 5521 rval = qla82xx_start_firmware(base_vha); 5522 else 5523 rval = QLA_SUCCESS; 5524 qla82xx_idc_lock(ha); 5525 5526 if (rval != QLA_SUCCESS) { 5527 ql_log(ql_log_info, base_vha, 0x900b, 5528 "HW State: FAILED.\n"); 5529 qla82xx_clear_drv_active(ha); 5530 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5531 QLA8XXX_DEV_FAILED); 5532 } else { 5533 ql_log(ql_log_info, base_vha, 0x900c, 5534 "HW State: READY.\n"); 5535 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5536 QLA8XXX_DEV_READY); 5537 qla82xx_idc_unlock(ha); 5538 ha->flags.isp82xx_fw_hung = 0; 5539 rval = qla82xx_restart_isp(base_vha); 5540 qla82xx_idc_lock(ha); 5541 /* Clear driver state register */ 5542 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5543 qla82xx_set_drv_active(base_vha); 5544 } 5545 qla82xx_idc_unlock(ha); 5546 } else { 5547 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5548 "This devfn is not reset owner = 0x%x.\n", 5549 ha->pdev->devfn); 5550 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5551 QLA8XXX_DEV_READY)) { 5552 ha->flags.isp82xx_fw_hung = 0; 5553 rval = qla82xx_restart_isp(base_vha); 5554 qla82xx_idc_lock(ha); 5555 qla82xx_set_drv_active(base_vha); 5556 qla82xx_idc_unlock(ha); 5557 } 5558 } 5559 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5560 5561 return rval; 5562 } 5563 5564 static pci_ers_result_t 5565 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5566 { 5567 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5568 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5569 struct qla_hw_data *ha = base_vha->hw; 5570 struct rsp_que *rsp; 5571 int rc, retries = 10; 5572 5573 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5574 "Slot Reset.\n"); 5575 5576 /* Workaround: qla2xxx driver which access hardware earlier 5577 * needs error state to be pci_channel_io_online. 5578 * Otherwise mailbox command timesout. 5579 */ 5580 pdev->error_state = pci_channel_io_normal; 5581 5582 pci_restore_state(pdev); 5583 5584 /* pci_restore_state() clears the saved_state flag of the device 5585 * save restored state which resets saved_state flag 5586 */ 5587 pci_save_state(pdev); 5588 5589 if (ha->mem_only) 5590 rc = pci_enable_device_mem(pdev); 5591 else 5592 rc = pci_enable_device(pdev); 5593 5594 if (rc) { 5595 ql_log(ql_log_warn, base_vha, 0x9005, 5596 "Can't re-enable PCI device after reset.\n"); 5597 goto exit_slot_reset; 5598 } 5599 5600 rsp = ha->rsp_q_map[0]; 5601 if (qla2x00_request_irqs(ha, rsp)) 5602 goto exit_slot_reset; 5603 5604 if (ha->isp_ops->pci_config(base_vha)) 5605 goto exit_slot_reset; 5606 5607 if (IS_QLA82XX(ha)) { 5608 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5609 ret = PCI_ERS_RESULT_RECOVERED; 5610 goto exit_slot_reset; 5611 } else 5612 goto exit_slot_reset; 5613 } 5614 5615 while (ha->flags.mbox_busy && retries--) 5616 msleep(1000); 5617 5618 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5619 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5620 ret = PCI_ERS_RESULT_RECOVERED; 5621 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5622 5623 5624 exit_slot_reset: 5625 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5626 "slot_reset return %x.\n", ret); 5627 5628 return ret; 5629 } 5630 5631 static void 5632 qla2xxx_pci_resume(struct pci_dev *pdev) 5633 { 5634 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5635 struct qla_hw_data *ha = base_vha->hw; 5636 int ret; 5637 5638 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5639 "pci_resume.\n"); 5640 5641 ret = qla2x00_wait_for_hba_online(base_vha); 5642 if (ret != QLA_SUCCESS) { 5643 ql_log(ql_log_fatal, base_vha, 0x9002, 5644 "The device failed to resume I/O from slot/link_reset.\n"); 5645 } 5646 5647 pci_cleanup_aer_uncorrect_error_status(pdev); 5648 5649 ha->flags.eeh_busy = 0; 5650 } 5651 5652 static void 5653 qla83xx_disable_laser(scsi_qla_host_t *vha) 5654 { 5655 uint32_t reg, data, fn; 5656 struct qla_hw_data *ha = vha->hw; 5657 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5658 5659 /* pci func #/port # */ 5660 ql_dbg(ql_dbg_init, vha, 0x004b, 5661 "Disabling Laser for hba: %p\n", vha); 5662 5663 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5664 (BIT_15|BIT_14|BIT_13|BIT_12)); 5665 5666 fn = (fn >> 12); 5667 5668 if (fn & 1) 5669 reg = PORT_1_2031; 5670 else 5671 reg = PORT_0_2031; 5672 5673 data = LASER_OFF_2031; 5674 5675 qla83xx_wr_reg(vha, reg, data); 5676 } 5677 5678 static const struct pci_error_handlers qla2xxx_err_handler = { 5679 .error_detected = qla2xxx_pci_error_detected, 5680 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5681 .slot_reset = qla2xxx_pci_slot_reset, 5682 .resume = qla2xxx_pci_resume, 5683 }; 5684 5685 static struct pci_device_id qla2xxx_pci_tbl[] = { 5686 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5687 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5688 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5689 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5690 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5691 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5692 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5693 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5694 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5707 { 0 }, 5708 }; 5709 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5710 5711 static struct pci_driver qla2xxx_pci_driver = { 5712 .name = QLA2XXX_DRIVER_NAME, 5713 .driver = { 5714 .owner = THIS_MODULE, 5715 }, 5716 .id_table = qla2xxx_pci_tbl, 5717 .probe = qla2x00_probe_one, 5718 .remove = qla2x00_remove_one, 5719 .shutdown = qla2x00_shutdown, 5720 .err_handler = &qla2xxx_err_handler, 5721 }; 5722 5723 static const struct file_operations apidev_fops = { 5724 .owner = THIS_MODULE, 5725 .llseek = noop_llseek, 5726 }; 5727 5728 /** 5729 * qla2x00_module_init - Module initialization. 5730 **/ 5731 static int __init 5732 qla2x00_module_init(void) 5733 { 5734 int ret = 0; 5735 5736 /* Allocate cache for SRBs. */ 5737 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5738 SLAB_HWCACHE_ALIGN, NULL); 5739 if (srb_cachep == NULL) { 5740 ql_log(ql_log_fatal, NULL, 0x0001, 5741 "Unable to allocate SRB cache...Failing load!.\n"); 5742 return -ENOMEM; 5743 } 5744 5745 /* Initialize target kmem_cache and mem_pools */ 5746 ret = qlt_init(); 5747 if (ret < 0) { 5748 kmem_cache_destroy(srb_cachep); 5749 return ret; 5750 } else if (ret > 0) { 5751 /* 5752 * If initiator mode is explictly disabled by qlt_init(), 5753 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5754 * performing scsi_scan_target() during LOOP UP event. 5755 */ 5756 qla2xxx_transport_functions.disable_target_scan = 1; 5757 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5758 } 5759 5760 /* Derive version string. */ 5761 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5762 if (ql2xextended_error_logging) 5763 strcat(qla2x00_version_str, "-debug"); 5764 5765 qla2xxx_transport_template = 5766 fc_attach_transport(&qla2xxx_transport_functions); 5767 if (!qla2xxx_transport_template) { 5768 kmem_cache_destroy(srb_cachep); 5769 ql_log(ql_log_fatal, NULL, 0x0002, 5770 "fc_attach_transport failed...Failing load!.\n"); 5771 qlt_exit(); 5772 return -ENODEV; 5773 } 5774 5775 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5776 if (apidev_major < 0) { 5777 ql_log(ql_log_fatal, NULL, 0x0003, 5778 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5779 } 5780 5781 qla2xxx_transport_vport_template = 5782 fc_attach_transport(&qla2xxx_transport_vport_functions); 5783 if (!qla2xxx_transport_vport_template) { 5784 kmem_cache_destroy(srb_cachep); 5785 qlt_exit(); 5786 fc_release_transport(qla2xxx_transport_template); 5787 ql_log(ql_log_fatal, NULL, 0x0004, 5788 "fc_attach_transport vport failed...Failing load!.\n"); 5789 return -ENODEV; 5790 } 5791 ql_log(ql_log_info, NULL, 0x0005, 5792 "QLogic Fibre Channel HBA Driver: %s.\n", 5793 qla2x00_version_str); 5794 ret = pci_register_driver(&qla2xxx_pci_driver); 5795 if (ret) { 5796 kmem_cache_destroy(srb_cachep); 5797 qlt_exit(); 5798 fc_release_transport(qla2xxx_transport_template); 5799 fc_release_transport(qla2xxx_transport_vport_template); 5800 ql_log(ql_log_fatal, NULL, 0x0006, 5801 "pci_register_driver failed...ret=%d Failing load!.\n", 5802 ret); 5803 } 5804 return ret; 5805 } 5806 5807 /** 5808 * qla2x00_module_exit - Module cleanup. 5809 **/ 5810 static void __exit 5811 qla2x00_module_exit(void) 5812 { 5813 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5814 pci_unregister_driver(&qla2xxx_pci_driver); 5815 qla2x00_release_firmware(); 5816 kmem_cache_destroy(srb_cachep); 5817 qlt_exit(); 5818 if (ctx_cachep) 5819 kmem_cache_destroy(ctx_cachep); 5820 fc_release_transport(qla2xxx_transport_template); 5821 fc_release_transport(qla2xxx_transport_vport_template); 5822 } 5823 5824 module_init(qla2x00_module_init); 5825 module_exit(qla2x00_module_exit); 5826 5827 MODULE_AUTHOR("QLogic Corporation"); 5828 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5829 MODULE_LICENSE("GPL"); 5830 MODULE_VERSION(QLA2XXX_VERSION); 5831 MODULE_FIRMWARE(FW_FILE_ISP21XX); 5832 MODULE_FIRMWARE(FW_FILE_ISP22XX); 5833 MODULE_FIRMWARE(FW_FILE_ISP2300); 5834 MODULE_FIRMWARE(FW_FILE_ISP2322); 5835 MODULE_FIRMWARE(FW_FILE_ISP24XX); 5836 MODULE_FIRMWARE(FW_FILE_ISP25XX); 5837