1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 307 struct scsi_host_template qla2xxx_driver_template = { 308 .module = THIS_MODULE, 309 .name = QLA2XXX_DRIVER_NAME, 310 .queuecommand = qla2xxx_queuecommand, 311 312 .eh_timed_out = fc_eh_timed_out, 313 .eh_abort_handler = qla2xxx_eh_abort, 314 .eh_device_reset_handler = qla2xxx_eh_device_reset, 315 .eh_target_reset_handler = qla2xxx_eh_target_reset, 316 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 317 .eh_host_reset_handler = qla2xxx_eh_host_reset, 318 319 .slave_configure = qla2xxx_slave_configure, 320 321 .slave_alloc = qla2xxx_slave_alloc, 322 .slave_destroy = qla2xxx_slave_destroy, 323 .scan_finished = qla2xxx_scan_finished, 324 .scan_start = qla2xxx_scan_start, 325 .change_queue_depth = scsi_change_queue_depth, 326 .map_queues = qla2xxx_map_queues, 327 .this_id = -1, 328 .cmd_per_lun = 3, 329 .use_clustering = ENABLE_CLUSTERING, 330 .sg_tablesize = SG_ALL, 331 332 .max_sectors = 0xFFFF, 333 .shost_attrs = qla2x00_host_attrs, 334 335 .supported_mode = MODE_INITIATOR, 336 .track_queue_depth = 1, 337 }; 338 339 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 340 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 341 342 /* TODO Convert to inlines 343 * 344 * Timer routines 345 */ 346 347 __inline__ void 348 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 349 { 350 timer_setup(&vha->timer, qla2x00_timer, 0); 351 vha->timer.expires = jiffies + interval * HZ; 352 add_timer(&vha->timer); 353 vha->timer_active = 1; 354 } 355 356 static inline void 357 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 358 { 359 /* Currently used for 82XX only. */ 360 if (vha->device_flags & DFLG_DEV_FAILED) { 361 ql_dbg(ql_dbg_timer, vha, 0x600d, 362 "Device in a failed state, returning.\n"); 363 return; 364 } 365 366 mod_timer(&vha->timer, jiffies + interval * HZ); 367 } 368 369 static __inline__ void 370 qla2x00_stop_timer(scsi_qla_host_t *vha) 371 { 372 del_timer_sync(&vha->timer); 373 vha->timer_active = 0; 374 } 375 376 static int qla2x00_do_dpc(void *data); 377 378 static void qla2x00_rst_aen(scsi_qla_host_t *); 379 380 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 381 struct req_que **, struct rsp_que **); 382 static void qla2x00_free_fw_dump(struct qla_hw_data *); 383 static void qla2x00_mem_free(struct qla_hw_data *); 384 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 385 struct qla_qpair *qpair); 386 387 /* -------------------------------------------------------------------------- */ 388 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 389 struct rsp_que *rsp) 390 { 391 struct qla_hw_data *ha = vha->hw; 392 rsp->qpair = ha->base_qpair; 393 rsp->req = req; 394 ha->base_qpair->req = req; 395 ha->base_qpair->rsp = rsp; 396 ha->base_qpair->vha = vha; 397 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 398 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 399 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 400 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 401 ha->base_qpair->enable_class_2 = ql2xenableclass2; 402 /* init qpair to this cpu. Will adjust at run time. */ 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 404 ha->base_qpair->pdev = ha->pdev; 405 406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 408 } 409 410 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 414 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 415 GFP_KERNEL); 416 if (!ha->req_q_map) { 417 ql_log(ql_log_fatal, vha, 0x003b, 418 "Unable to allocate memory for request queue ptrs.\n"); 419 goto fail_req_map; 420 } 421 422 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 423 GFP_KERNEL); 424 if (!ha->rsp_q_map) { 425 ql_log(ql_log_fatal, vha, 0x003c, 426 "Unable to allocate memory for response queue ptrs.\n"); 427 goto fail_rsp_map; 428 } 429 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 431 if (ha->base_qpair == NULL) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to allocate base queue pair memory.\n"); 434 goto fail_base_qpair; 435 } 436 437 qla_init_base_qpair(vha, req, rsp); 438 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 441 GFP_KERNEL); 442 if (!ha->queue_pair_map) { 443 ql_log(ql_log_fatal, vha, 0x0180, 444 "Unable to allocate memory for queue pair ptrs.\n"); 445 goto fail_qpair_map; 446 } 447 } 448 449 /* 450 * Make sure we record at least the request and response queue zero in 451 * case we need to free them if part of the probe fails. 452 */ 453 ha->rsp_q_map[0] = rsp; 454 ha->req_q_map[0] = req; 455 set_bit(0, ha->rsp_qid_map); 456 set_bit(0, ha->req_qid_map); 457 return 0; 458 459 fail_qpair_map: 460 kfree(ha->base_qpair); 461 ha->base_qpair = NULL; 462 fail_base_qpair: 463 kfree(ha->rsp_q_map); 464 ha->rsp_q_map = NULL; 465 fail_rsp_map: 466 kfree(ha->req_q_map); 467 ha->req_q_map = NULL; 468 fail_req_map: 469 return -ENOMEM; 470 } 471 472 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 473 { 474 if (IS_QLAFX00(ha)) { 475 if (req && req->ring_fx00) 476 dma_free_coherent(&ha->pdev->dev, 477 (req->length_fx00 + 1) * sizeof(request_t), 478 req->ring_fx00, req->dma_fx00); 479 } else if (req && req->ring) 480 dma_free_coherent(&ha->pdev->dev, 481 (req->length + 1) * sizeof(request_t), 482 req->ring, req->dma); 483 484 if (req) 485 kfree(req->outstanding_cmds); 486 487 kfree(req); 488 } 489 490 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 491 { 492 if (IS_QLAFX00(ha)) { 493 if (rsp && rsp->ring_fx00) 494 dma_free_coherent(&ha->pdev->dev, 495 (rsp->length_fx00 + 1) * sizeof(request_t), 496 rsp->ring_fx00, rsp->dma_fx00); 497 } else if (rsp && rsp->ring) { 498 dma_free_coherent(&ha->pdev->dev, 499 (rsp->length + 1) * sizeof(response_t), 500 rsp->ring, rsp->dma); 501 } 502 kfree(rsp); 503 } 504 505 static void qla2x00_free_queues(struct qla_hw_data *ha) 506 { 507 struct req_que *req; 508 struct rsp_que *rsp; 509 int cnt; 510 unsigned long flags; 511 512 if (ha->queue_pair_map) { 513 kfree(ha->queue_pair_map); 514 ha->queue_pair_map = NULL; 515 } 516 if (ha->base_qpair) { 517 kfree(ha->base_qpair); 518 ha->base_qpair = NULL; 519 } 520 521 spin_lock_irqsave(&ha->hardware_lock, flags); 522 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 523 if (!test_bit(cnt, ha->req_qid_map)) 524 continue; 525 526 req = ha->req_q_map[cnt]; 527 clear_bit(cnt, ha->req_qid_map); 528 ha->req_q_map[cnt] = NULL; 529 530 spin_unlock_irqrestore(&ha->hardware_lock, flags); 531 qla2x00_free_req_que(ha, req); 532 spin_lock_irqsave(&ha->hardware_lock, flags); 533 } 534 spin_unlock_irqrestore(&ha->hardware_lock, flags); 535 536 kfree(ha->req_q_map); 537 ha->req_q_map = NULL; 538 539 540 spin_lock_irqsave(&ha->hardware_lock, flags); 541 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 542 if (!test_bit(cnt, ha->rsp_qid_map)) 543 continue; 544 545 rsp = ha->rsp_q_map[cnt]; 546 clear_bit(cnt, ha->rsp_qid_map); 547 ha->rsp_q_map[cnt] = NULL; 548 spin_unlock_irqrestore(&ha->hardware_lock, flags); 549 qla2x00_free_rsp_que(ha, rsp); 550 spin_lock_irqsave(&ha->hardware_lock, flags); 551 } 552 spin_unlock_irqrestore(&ha->hardware_lock, flags); 553 554 kfree(ha->rsp_q_map); 555 ha->rsp_q_map = NULL; 556 } 557 558 static char * 559 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 560 { 561 struct qla_hw_data *ha = vha->hw; 562 static char *pci_bus_modes[] = { 563 "33", "66", "100", "133", 564 }; 565 uint16_t pci_bus; 566 567 strcpy(str, "PCI"); 568 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 569 if (pci_bus) { 570 strcat(str, "-X ("); 571 strcat(str, pci_bus_modes[pci_bus]); 572 } else { 573 pci_bus = (ha->pci_attr & BIT_8) >> 8; 574 strcat(str, " ("); 575 strcat(str, pci_bus_modes[pci_bus]); 576 } 577 strcat(str, " MHz)"); 578 579 return (str); 580 } 581 582 static char * 583 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 584 { 585 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 586 struct qla_hw_data *ha = vha->hw; 587 uint32_t pci_bus; 588 589 if (pci_is_pcie(ha->pdev)) { 590 char lwstr[6]; 591 uint32_t lstat, lspeed, lwidth; 592 593 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 594 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 595 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 596 597 strcpy(str, "PCIe ("); 598 switch (lspeed) { 599 case 1: 600 strcat(str, "2.5GT/s "); 601 break; 602 case 2: 603 strcat(str, "5.0GT/s "); 604 break; 605 case 3: 606 strcat(str, "8.0GT/s "); 607 break; 608 default: 609 strcat(str, "<unknown> "); 610 break; 611 } 612 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 613 strcat(str, lwstr); 614 615 return str; 616 } 617 618 strcpy(str, "PCI"); 619 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 620 if (pci_bus == 0 || pci_bus == 8) { 621 strcat(str, " ("); 622 strcat(str, pci_bus_modes[pci_bus >> 3]); 623 } else { 624 strcat(str, "-X "); 625 if (pci_bus & BIT_2) 626 strcat(str, "Mode 2"); 627 else 628 strcat(str, "Mode 1"); 629 strcat(str, " ("); 630 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 631 } 632 strcat(str, " MHz)"); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void 686 qla2x00_sp_free_dma(void *ptr) 687 { 688 srb_t *sp = ptr; 689 struct qla_hw_data *ha = sp->vha->hw; 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 691 void *ctx = GET_CMD_CTX_SP(sp); 692 693 if (sp->flags & SRB_DMA_VALID) { 694 scsi_dma_unmap(cmd); 695 sp->flags &= ~SRB_DMA_VALID; 696 } 697 698 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 699 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 700 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 701 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 702 } 703 704 if (!ctx) 705 goto end; 706 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 708 /* List assured to be having elements */ 709 qla2x00_clean_dsd_pool(ha, ctx); 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 711 } 712 713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 714 struct crc_context *ctx0 = ctx; 715 716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 718 } 719 720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 721 struct ct6_dsd *ctx1 = ctx; 722 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 724 ctx1->fcp_cmnd_dma); 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 728 mempool_free(ctx1, ha->ctx_mempool); 729 } 730 731 end: 732 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 733 CMD_SP(cmd) = NULL; 734 qla2x00_rel_sp(sp); 735 } 736 } 737 738 void 739 qla2x00_sp_compl(void *ptr, int res) 740 { 741 srb_t *sp = ptr; 742 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 743 744 cmd->result = res; 745 746 if (atomic_read(&sp->ref_count) == 0) { 747 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 748 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 749 sp, GET_CMD_SP(sp)); 750 if (ql2xextended_error_logging & ql_dbg_io) 751 WARN_ON(atomic_read(&sp->ref_count) == 0); 752 return; 753 } 754 if (!atomic_dec_and_test(&sp->ref_count)) 755 return; 756 757 sp->free(sp); 758 cmd->scsi_done(cmd); 759 } 760 761 void 762 qla2xxx_qpair_sp_free_dma(void *ptr) 763 { 764 srb_t *sp = (srb_t *)ptr; 765 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 766 struct qla_hw_data *ha = sp->fcport->vha->hw; 767 void *ctx = GET_CMD_CTX_SP(sp); 768 769 if (sp->flags & SRB_DMA_VALID) { 770 scsi_dma_unmap(cmd); 771 sp->flags &= ~SRB_DMA_VALID; 772 } 773 774 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 775 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 776 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 777 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 778 } 779 780 if (!ctx) 781 goto end; 782 783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 784 /* List assured to be having elements */ 785 qla2x00_clean_dsd_pool(ha, ctx); 786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 787 } 788 789 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 790 struct crc_context *ctx0 = ctx; 791 792 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 793 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 794 } 795 796 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 797 struct ct6_dsd *ctx1 = ctx; 798 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 799 ctx1->fcp_cmnd_dma); 800 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 801 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 802 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 803 mempool_free(ctx1, ha->ctx_mempool); 804 } 805 end: 806 CMD_SP(cmd) = NULL; 807 qla2xxx_rel_qpair_sp(sp->qpair, sp); 808 } 809 810 void 811 qla2xxx_qpair_sp_compl(void *ptr, int res) 812 { 813 srb_t *sp = ptr; 814 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 815 816 cmd->result = res; 817 818 if (atomic_read(&sp->ref_count) == 0) { 819 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 820 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 821 sp, GET_CMD_SP(sp)); 822 if (ql2xextended_error_logging & ql_dbg_io) 823 WARN_ON(atomic_read(&sp->ref_count) == 0); 824 return; 825 } 826 if (!atomic_dec_and_test(&sp->ref_count)) 827 return; 828 829 sp->free(sp); 830 cmd->scsi_done(cmd); 831 } 832 833 /* If we are SP1 here, we need to still take and release the host_lock as SP1 834 * does not have the changes necessary to avoid taking host->host_lock. 835 */ 836 static int 837 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 838 { 839 scsi_qla_host_t *vha = shost_priv(host); 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 842 struct qla_hw_data *ha = vha->hw; 843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 844 srb_t *sp; 845 int rval; 846 struct qla_qpair *qpair = NULL; 847 uint32_t tag; 848 uint16_t hwq; 849 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 851 cmd->result = DID_NO_CONNECT << 16; 852 goto qc24_fail_command; 853 } 854 855 if (ha->mqenable) { 856 if (shost_use_blk_mq(vha->host)) { 857 tag = blk_mq_unique_tag(cmd->request); 858 hwq = blk_mq_unique_tag_to_hwq(tag); 859 qpair = ha->queue_pair_map[hwq]; 860 } else if (vha->vp_idx && vha->qpair) { 861 qpair = vha->qpair; 862 } 863 864 if (qpair) 865 return qla2xxx_mqueuecommand(host, cmd, qpair); 866 } 867 868 if (ha->flags.eeh_busy) { 869 if (ha->flags.pci_channel_io_perm_failure) { 870 ql_dbg(ql_dbg_aer, vha, 0x9010, 871 "PCI Channel IO permanent failure, exiting " 872 "cmd=%p.\n", cmd); 873 cmd->result = DID_NO_CONNECT << 16; 874 } else { 875 ql_dbg(ql_dbg_aer, vha, 0x9011, 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 877 cmd->result = DID_REQUEUE << 16; 878 } 879 goto qc24_fail_command; 880 } 881 882 rval = fc_remote_port_chkready(rport); 883 if (rval) { 884 cmd->result = rval; 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 887 cmd, rval); 888 goto qc24_fail_command; 889 } 890 891 if (!vha->flags.difdix_supported && 892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 893 ql_dbg(ql_dbg_io, vha, 0x3004, 894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 895 cmd); 896 cmd->result = DID_NO_CONNECT << 16; 897 goto qc24_fail_command; 898 } 899 900 if (!fcport) { 901 cmd->result = DID_NO_CONNECT << 16; 902 goto qc24_fail_command; 903 } 904 905 if (atomic_read(&fcport->state) != FCS_ONLINE) { 906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 908 ql_dbg(ql_dbg_io, vha, 0x3005, 909 "Returning DNC, fcport_state=%d loop_state=%d.\n", 910 atomic_read(&fcport->state), 911 atomic_read(&base_vha->loop_state)); 912 cmd->result = DID_NO_CONNECT << 16; 913 goto qc24_fail_command; 914 } 915 goto qc24_target_busy; 916 } 917 918 /* 919 * Return target busy if we've received a non-zero retry_delay_timer 920 * in a FCP_RSP. 921 */ 922 if (fcport->retry_delay_timestamp == 0) { 923 /* retry delay not set */ 924 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 925 fcport->retry_delay_timestamp = 0; 926 else 927 goto qc24_target_busy; 928 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 930 if (!sp) 931 goto qc24_host_busy; 932 933 sp->u.scmd.cmd = cmd; 934 sp->type = SRB_SCSI_CMD; 935 atomic_set(&sp->ref_count, 1); 936 CMD_SP(cmd) = (void *)sp; 937 sp->free = qla2x00_sp_free_dma; 938 sp->done = qla2x00_sp_compl; 939 940 rval = ha->isp_ops->start_scsi(sp); 941 if (rval != QLA_SUCCESS) { 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 944 goto qc24_host_busy_free_sp; 945 } 946 947 return 0; 948 949 qc24_host_busy_free_sp: 950 sp->free(sp); 951 952 qc24_host_busy: 953 return SCSI_MLQUEUE_HOST_BUSY; 954 955 qc24_target_busy: 956 return SCSI_MLQUEUE_TARGET_BUSY; 957 958 qc24_fail_command: 959 cmd->scsi_done(cmd); 960 961 return 0; 962 } 963 964 /* For MQ supported I/O */ 965 int 966 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 967 struct qla_qpair *qpair) 968 { 969 scsi_qla_host_t *vha = shost_priv(host); 970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 972 struct qla_hw_data *ha = vha->hw; 973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 974 srb_t *sp; 975 int rval; 976 977 rval = fc_remote_port_chkready(rport); 978 if (rval) { 979 cmd->result = rval; 980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 982 cmd, rval); 983 goto qc24_fail_command; 984 } 985 986 if (!fcport) { 987 cmd->result = DID_NO_CONNECT << 16; 988 goto qc24_fail_command; 989 } 990 991 if (atomic_read(&fcport->state) != FCS_ONLINE) { 992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 994 ql_dbg(ql_dbg_io, vha, 0x3077, 995 "Returning DNC, fcport_state=%d loop_state=%d.\n", 996 atomic_read(&fcport->state), 997 atomic_read(&base_vha->loop_state)); 998 cmd->result = DID_NO_CONNECT << 16; 999 goto qc24_fail_command; 1000 } 1001 goto qc24_target_busy; 1002 } 1003 1004 /* 1005 * Return target busy if we've received a non-zero retry_delay_timer 1006 * in a FCP_RSP. 1007 */ 1008 if (fcport->retry_delay_timestamp == 0) { 1009 /* retry delay not set */ 1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1011 fcport->retry_delay_timestamp = 0; 1012 else 1013 goto qc24_target_busy; 1014 1015 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1016 if (!sp) 1017 goto qc24_host_busy; 1018 1019 sp->u.scmd.cmd = cmd; 1020 sp->type = SRB_SCSI_CMD; 1021 atomic_set(&sp->ref_count, 1); 1022 CMD_SP(cmd) = (void *)sp; 1023 sp->free = qla2xxx_qpair_sp_free_dma; 1024 sp->done = qla2xxx_qpair_sp_compl; 1025 sp->qpair = qpair; 1026 1027 rval = ha->isp_ops->start_scsi_mq(sp); 1028 if (rval != QLA_SUCCESS) { 1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1031 if (rval == QLA_INTERFACE_ERROR) 1032 goto qc24_fail_command; 1033 goto qc24_host_busy_free_sp; 1034 } 1035 1036 return 0; 1037 1038 qc24_host_busy_free_sp: 1039 sp->free(sp); 1040 1041 qc24_host_busy: 1042 return SCSI_MLQUEUE_HOST_BUSY; 1043 1044 qc24_target_busy: 1045 return SCSI_MLQUEUE_TARGET_BUSY; 1046 1047 qc24_fail_command: 1048 cmd->scsi_done(cmd); 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * qla2x00_eh_wait_on_command 1055 * Waits for the command to be returned by the Firmware for some 1056 * max time. 1057 * 1058 * Input: 1059 * cmd = Scsi Command to wait on. 1060 * 1061 * Return: 1062 * Not Found : 0 1063 * Found : 1 1064 */ 1065 static int 1066 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1067 { 1068 #define ABORT_POLLING_PERIOD 1000 1069 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1070 unsigned long wait_iter = ABORT_WAIT_ITER; 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1072 struct qla_hw_data *ha = vha->hw; 1073 int ret = QLA_SUCCESS; 1074 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1077 "Return:eh_wait.\n"); 1078 return ret; 1079 } 1080 1081 while (CMD_SP(cmd) && wait_iter--) { 1082 msleep(ABORT_POLLING_PERIOD); 1083 } 1084 if (CMD_SP(cmd)) 1085 ret = QLA_FUNCTION_FAILED; 1086 1087 return ret; 1088 } 1089 1090 /* 1091 * qla2x00_wait_for_hba_online 1092 * Wait till the HBA is online after going through 1093 * <= MAX_RETRIES_OF_ISP_ABORT or 1094 * finally HBA is disabled ie marked offline 1095 * 1096 * Input: 1097 * ha - pointer to host adapter structure 1098 * 1099 * Note: 1100 * Does context switching-Release SPIN_LOCK 1101 * (if any) before calling this routine. 1102 * 1103 * Return: 1104 * Success (Adapter is online) : 0 1105 * Failed (Adapter is offline/disabled) : 1 1106 */ 1107 int 1108 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1109 { 1110 int return_status; 1111 unsigned long wait_online; 1112 struct qla_hw_data *ha = vha->hw; 1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1114 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1119 ha->dpc_active) && time_before(jiffies, wait_online)) { 1120 1121 msleep(1000); 1122 } 1123 if (base_vha->flags.online) 1124 return_status = QLA_SUCCESS; 1125 else 1126 return_status = QLA_FUNCTION_FAILED; 1127 1128 return (return_status); 1129 } 1130 1131 static inline int test_fcport_count(scsi_qla_host_t *vha) 1132 { 1133 struct qla_hw_data *ha = vha->hw; 1134 unsigned long flags; 1135 int res; 1136 1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1138 ql_dbg(ql_dbg_init, vha, 0x00ec, 1139 "tgt %p, fcport_count=%d\n", 1140 vha, vha->fcport_count); 1141 res = (vha->fcport_count == 0); 1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1143 1144 return res; 1145 } 1146 1147 /* 1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1149 * it has dependency on UNLOADING flag to stop device discovery 1150 */ 1151 void 1152 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1153 { 1154 qla2x00_mark_all_devices_lost(vha, 0); 1155 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1157 } 1158 1159 /* 1160 * qla2x00_wait_for_hba_ready 1161 * Wait till the HBA is ready before doing driver unload 1162 * 1163 * Input: 1164 * ha - pointer to host adapter structure 1165 * 1166 * Note: 1167 * Does context switching-Release SPIN_LOCK 1168 * (if any) before calling this routine. 1169 * 1170 */ 1171 static void 1172 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1173 { 1174 struct qla_hw_data *ha = vha->hw; 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1176 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1178 ha->flags.mbox_busy) || 1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1181 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1182 break; 1183 msleep(1000); 1184 } 1185 } 1186 1187 int 1188 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1189 { 1190 int return_status; 1191 unsigned long wait_reset; 1192 struct qla_hw_data *ha = vha->hw; 1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1194 1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1199 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1200 1201 msleep(1000); 1202 1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1204 ha->flags.chip_reset_done) 1205 break; 1206 } 1207 if (ha->flags.chip_reset_done) 1208 return_status = QLA_SUCCESS; 1209 else 1210 return_status = QLA_FUNCTION_FAILED; 1211 1212 return return_status; 1213 } 1214 1215 static void 1216 sp_get(struct srb *sp) 1217 { 1218 atomic_inc(&sp->ref_count); 1219 } 1220 1221 #define ISP_REG_DISCONNECT 0xffffffffU 1222 /************************************************************************** 1223 * qla2x00_isp_reg_stat 1224 * 1225 * Description: 1226 * Read the host status register of ISP before aborting the command. 1227 * 1228 * Input: 1229 * ha = pointer to host adapter structure. 1230 * 1231 * 1232 * Returns: 1233 * Either true or false. 1234 * 1235 * Note: Return true if there is register disconnect. 1236 **************************************************************************/ 1237 static inline 1238 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1239 { 1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1241 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1242 1243 if (IS_P3P_TYPE(ha)) 1244 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1245 else 1246 return ((RD_REG_DWORD(®->host_status)) == 1247 ISP_REG_DISCONNECT); 1248 } 1249 1250 /************************************************************************** 1251 * qla2xxx_eh_abort 1252 * 1253 * Description: 1254 * The abort function will abort the specified command. 1255 * 1256 * Input: 1257 * cmd = Linux SCSI command packet to be aborted. 1258 * 1259 * Returns: 1260 * Either SUCCESS or FAILED. 1261 * 1262 * Note: 1263 * Only return FAILED if command not returned by firmware. 1264 **************************************************************************/ 1265 static int 1266 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1267 { 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1269 srb_t *sp; 1270 int ret; 1271 unsigned int id; 1272 uint64_t lun; 1273 unsigned long flags; 1274 int rval, wait = 0; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 if (qla2x00_isp_reg_stat(ha)) { 1278 ql_log(ql_log_info, vha, 0x8042, 1279 "PCI/Register disconnect, exiting.\n"); 1280 return FAILED; 1281 } 1282 if (!CMD_SP(cmd)) 1283 return SUCCESS; 1284 1285 ret = fc_block_scsi_eh(cmd); 1286 if (ret != 0) 1287 return ret; 1288 ret = SUCCESS; 1289 1290 id = cmd->device->id; 1291 lun = cmd->device->lun; 1292 1293 spin_lock_irqsave(&ha->hardware_lock, flags); 1294 sp = (srb_t *) CMD_SP(cmd); 1295 if (!sp) { 1296 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1297 return SUCCESS; 1298 } 1299 1300 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1302 vha->host_no, id, lun, sp, cmd, sp->handle); 1303 1304 /* Get a reference to the sp and drop the lock.*/ 1305 sp_get(sp); 1306 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1308 rval = ha->isp_ops->abort_command(sp); 1309 if (rval) { 1310 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1311 ret = SUCCESS; 1312 else 1313 ret = FAILED; 1314 1315 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1316 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1317 } else { 1318 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1319 "Abort command mbx success cmd=%p.\n", cmd); 1320 wait = 1; 1321 } 1322 1323 spin_lock_irqsave(&ha->hardware_lock, flags); 1324 sp->done(sp, 0); 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1326 1327 /* Did the command return during mailbox execution? */ 1328 if (ret == FAILED && !CMD_SP(cmd)) 1329 ret = SUCCESS; 1330 1331 /* Wait for the command to be returned. */ 1332 if (wait) { 1333 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1334 ql_log(ql_log_warn, vha, 0x8006, 1335 "Abort handler timed out cmd=%p.\n", cmd); 1336 ret = FAILED; 1337 } 1338 } 1339 1340 ql_log(ql_log_info, vha, 0x801c, 1341 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1342 vha->host_no, id, lun, wait, ret); 1343 1344 return ret; 1345 } 1346 1347 int 1348 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1349 uint64_t l, enum nexus_wait_type type) 1350 { 1351 int cnt, match, status; 1352 unsigned long flags; 1353 struct qla_hw_data *ha = vha->hw; 1354 struct req_que *req; 1355 srb_t *sp; 1356 struct scsi_cmnd *cmd; 1357 1358 status = QLA_SUCCESS; 1359 1360 spin_lock_irqsave(&ha->hardware_lock, flags); 1361 req = vha->req; 1362 for (cnt = 1; status == QLA_SUCCESS && 1363 cnt < req->num_outstanding_cmds; cnt++) { 1364 sp = req->outstanding_cmds[cnt]; 1365 if (!sp) 1366 continue; 1367 if (sp->type != SRB_SCSI_CMD) 1368 continue; 1369 if (vha->vp_idx != sp->vha->vp_idx) 1370 continue; 1371 match = 0; 1372 cmd = GET_CMD_SP(sp); 1373 switch (type) { 1374 case WAIT_HOST: 1375 match = 1; 1376 break; 1377 case WAIT_TARGET: 1378 match = cmd->device->id == t; 1379 break; 1380 case WAIT_LUN: 1381 match = (cmd->device->id == t && 1382 cmd->device->lun == l); 1383 break; 1384 } 1385 if (!match) 1386 continue; 1387 1388 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1389 status = qla2x00_eh_wait_on_command(cmd); 1390 spin_lock_irqsave(&ha->hardware_lock, flags); 1391 } 1392 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1393 1394 return status; 1395 } 1396 1397 static char *reset_errors[] = { 1398 "HBA not online", 1399 "HBA not ready", 1400 "Task management failed", 1401 "Waiting for command completions", 1402 }; 1403 1404 static int 1405 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1406 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1407 { 1408 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1409 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1410 int err; 1411 1412 if (!fcport) { 1413 return FAILED; 1414 } 1415 1416 err = fc_block_scsi_eh(cmd); 1417 if (err != 0) 1418 return err; 1419 1420 ql_log(ql_log_info, vha, 0x8009, 1421 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1422 cmd->device->id, cmd->device->lun, cmd); 1423 1424 err = 0; 1425 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1426 ql_log(ql_log_warn, vha, 0x800a, 1427 "Wait for hba online failed for cmd=%p.\n", cmd); 1428 goto eh_reset_failed; 1429 } 1430 err = 2; 1431 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1432 != QLA_SUCCESS) { 1433 ql_log(ql_log_warn, vha, 0x800c, 1434 "do_reset failed for cmd=%p.\n", cmd); 1435 goto eh_reset_failed; 1436 } 1437 err = 3; 1438 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1439 cmd->device->lun, type) != QLA_SUCCESS) { 1440 ql_log(ql_log_warn, vha, 0x800d, 1441 "wait for pending cmds failed for cmd=%p.\n", cmd); 1442 goto eh_reset_failed; 1443 } 1444 1445 ql_log(ql_log_info, vha, 0x800e, 1446 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1447 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1448 1449 return SUCCESS; 1450 1451 eh_reset_failed: 1452 ql_log(ql_log_info, vha, 0x800f, 1453 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1454 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1455 cmd); 1456 return FAILED; 1457 } 1458 1459 static int 1460 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1461 { 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1463 struct qla_hw_data *ha = vha->hw; 1464 1465 if (qla2x00_isp_reg_stat(ha)) { 1466 ql_log(ql_log_info, vha, 0x803e, 1467 "PCI/Register disconnect, exiting.\n"); 1468 return FAILED; 1469 } 1470 1471 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1472 ha->isp_ops->lun_reset); 1473 } 1474 1475 static int 1476 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1477 { 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1479 struct qla_hw_data *ha = vha->hw; 1480 1481 if (qla2x00_isp_reg_stat(ha)) { 1482 ql_log(ql_log_info, vha, 0x803f, 1483 "PCI/Register disconnect, exiting.\n"); 1484 return FAILED; 1485 } 1486 1487 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1488 ha->isp_ops->target_reset); 1489 } 1490 1491 /************************************************************************** 1492 * qla2xxx_eh_bus_reset 1493 * 1494 * Description: 1495 * The bus reset function will reset the bus and abort any executing 1496 * commands. 1497 * 1498 * Input: 1499 * cmd = Linux SCSI command packet of the command that cause the 1500 * bus reset. 1501 * 1502 * Returns: 1503 * SUCCESS/FAILURE (defined as macro in scsi.h). 1504 * 1505 **************************************************************************/ 1506 static int 1507 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1508 { 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1510 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1511 int ret = FAILED; 1512 unsigned int id; 1513 uint64_t lun; 1514 struct qla_hw_data *ha = vha->hw; 1515 1516 if (qla2x00_isp_reg_stat(ha)) { 1517 ql_log(ql_log_info, vha, 0x8040, 1518 "PCI/Register disconnect, exiting.\n"); 1519 return FAILED; 1520 } 1521 1522 id = cmd->device->id; 1523 lun = cmd->device->lun; 1524 1525 if (!fcport) { 1526 return ret; 1527 } 1528 1529 ret = fc_block_scsi_eh(cmd); 1530 if (ret != 0) 1531 return ret; 1532 ret = FAILED; 1533 1534 ql_log(ql_log_info, vha, 0x8012, 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1536 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1538 ql_log(ql_log_fatal, vha, 0x8013, 1539 "Wait for hba online failed board disabled.\n"); 1540 goto eh_bus_reset_done; 1541 } 1542 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1544 ret = SUCCESS; 1545 1546 if (ret == FAILED) 1547 goto eh_bus_reset_done; 1548 1549 /* Flush outstanding commands. */ 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1551 QLA_SUCCESS) { 1552 ql_log(ql_log_warn, vha, 0x8014, 1553 "Wait for pending commands failed.\n"); 1554 ret = FAILED; 1555 } 1556 1557 eh_bus_reset_done: 1558 ql_log(ql_log_warn, vha, 0x802b, 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1561 1562 return ret; 1563 } 1564 1565 /************************************************************************** 1566 * qla2xxx_eh_host_reset 1567 * 1568 * Description: 1569 * The reset function will reset the Adapter. 1570 * 1571 * Input: 1572 * cmd = Linux SCSI command packet of the command that cause the 1573 * adapter reset. 1574 * 1575 * Returns: 1576 * Either SUCCESS or FAILED. 1577 * 1578 * Note: 1579 **************************************************************************/ 1580 static int 1581 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1582 { 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1584 struct qla_hw_data *ha = vha->hw; 1585 int ret = FAILED; 1586 unsigned int id; 1587 uint64_t lun; 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1589 1590 if (qla2x00_isp_reg_stat(ha)) { 1591 ql_log(ql_log_info, vha, 0x8041, 1592 "PCI/Register disconnect, exiting.\n"); 1593 schedule_work(&ha->board_disable); 1594 return SUCCESS; 1595 } 1596 1597 id = cmd->device->id; 1598 lun = cmd->device->lun; 1599 1600 ql_log(ql_log_info, vha, 0x8018, 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1602 1603 /* 1604 * No point in issuing another reset if one is active. Also do not 1605 * attempt a reset if we are updating flash. 1606 */ 1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1608 goto eh_host_reset_lock; 1609 1610 if (vha != base_vha) { 1611 if (qla2x00_vp_abort_isp(vha)) 1612 goto eh_host_reset_lock; 1613 } else { 1614 if (IS_P3P_TYPE(vha->hw)) { 1615 if (!qla82xx_fcoe_ctx_reset(vha)) { 1616 /* Ctx reset success */ 1617 ret = SUCCESS; 1618 goto eh_host_reset_lock; 1619 } 1620 /* fall thru if ctx reset failed */ 1621 } 1622 if (ha->wq) 1623 flush_workqueue(ha->wq); 1624 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 if (ha->isp_ops->abort_isp(base_vha)) { 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1628 /* failed. schedule dpc to try */ 1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1630 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1632 ql_log(ql_log_warn, vha, 0x802a, 1633 "wait for hba online failed.\n"); 1634 goto eh_host_reset_lock; 1635 } 1636 } 1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1638 } 1639 1640 /* Waiting for command to be returned to OS.*/ 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1642 QLA_SUCCESS) 1643 ret = SUCCESS; 1644 1645 eh_host_reset_lock: 1646 ql_log(ql_log_info, vha, 0x8017, 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1649 1650 return ret; 1651 } 1652 1653 /* 1654 * qla2x00_loop_reset 1655 * Issue loop reset. 1656 * 1657 * Input: 1658 * ha = adapter block pointer. 1659 * 1660 * Returns: 1661 * 0 = success 1662 */ 1663 int 1664 qla2x00_loop_reset(scsi_qla_host_t *vha) 1665 { 1666 int ret; 1667 struct fc_port *fcport; 1668 struct qla_hw_data *ha = vha->hw; 1669 1670 if (IS_QLAFX00(ha)) { 1671 return qlafx00_loop_reset(vha); 1672 } 1673 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1676 if (fcport->port_type != FCT_TARGET) 1677 continue; 1678 1679 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1680 if (ret != QLA_SUCCESS) { 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1682 "Bus Reset failed: Reset=%d " 1683 "d_id=%x.\n", ret, fcport->d_id.b24); 1684 } 1685 } 1686 } 1687 1688 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1690 atomic_set(&vha->loop_state, LOOP_DOWN); 1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1692 qla2x00_mark_all_devices_lost(vha, 0); 1693 ret = qla2x00_full_login_lip(vha); 1694 if (ret != QLA_SUCCESS) { 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1696 "full_login_lip=%d.\n", ret); 1697 } 1698 } 1699 1700 if (ha->flags.enable_lip_reset) { 1701 ret = qla2x00_lip_reset(vha); 1702 if (ret != QLA_SUCCESS) 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1704 "lip_reset failed (%d).\n", ret); 1705 } 1706 1707 /* Issue marker command only when we are going to start the I/O */ 1708 vha->marker_needed = 1; 1709 1710 return QLA_SUCCESS; 1711 } 1712 1713 static void 1714 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1715 { 1716 int cnt, status; 1717 unsigned long flags; 1718 srb_t *sp; 1719 scsi_qla_host_t *vha = qp->vha; 1720 struct qla_hw_data *ha = vha->hw; 1721 struct req_que *req; 1722 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1723 struct qla_tgt_cmd *cmd; 1724 uint8_t trace = 0; 1725 1726 if (!ha->req_q_map) 1727 return; 1728 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1729 req = qp->req; 1730 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1731 sp = req->outstanding_cmds[cnt]; 1732 if (sp) { 1733 req->outstanding_cmds[cnt] = NULL; 1734 if (sp->cmd_type == TYPE_SRB) { 1735 if (sp->type == SRB_NVME_CMD || 1736 sp->type == SRB_NVME_LS) { 1737 sp_get(sp); 1738 spin_unlock_irqrestore(qp->qp_lock_ptr, 1739 flags); 1740 qla_nvme_abort(ha, sp, res); 1741 spin_lock_irqsave(qp->qp_lock_ptr, 1742 flags); 1743 } else if (GET_CMD_SP(sp) && 1744 !ha->flags.eeh_busy && 1745 (!test_bit(ABORT_ISP_ACTIVE, 1746 &vha->dpc_flags)) && 1747 (sp->type == SRB_SCSI_CMD)) { 1748 /* 1749 * Don't abort commands in 1750 * adapter during EEH 1751 * recovery as it's not 1752 * accessible/responding. 1753 * 1754 * Get a reference to the sp 1755 * and drop the lock. The 1756 * reference ensures this 1757 * sp->done() call and not the 1758 * call in qla2xxx_eh_abort() 1759 * ends the SCSI command (with 1760 * result 'res'). 1761 */ 1762 sp_get(sp); 1763 spin_unlock_irqrestore(qp->qp_lock_ptr, 1764 flags); 1765 status = qla2xxx_eh_abort( 1766 GET_CMD_SP(sp)); 1767 spin_lock_irqsave(qp->qp_lock_ptr, 1768 flags); 1769 /* 1770 * Get rid of extra reference 1771 * if immediate exit from 1772 * ql2xxx_eh_abort 1773 */ 1774 if (status == FAILED && 1775 (qla2x00_isp_reg_stat(ha))) 1776 atomic_dec( 1777 &sp->ref_count); 1778 } 1779 sp->done(sp, res); 1780 } else { 1781 if (!vha->hw->tgt.tgt_ops || !tgt || 1782 qla_ini_mode_enabled(vha)) { 1783 if (!trace) 1784 ql_dbg(ql_dbg_tgt_mgt, 1785 vha, 0xf003, 1786 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1787 vha->dpc_flags); 1788 continue; 1789 } 1790 cmd = (struct qla_tgt_cmd *)sp; 1791 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1792 } 1793 } 1794 } 1795 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1796 } 1797 1798 void 1799 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1800 { 1801 int que; 1802 struct qla_hw_data *ha = vha->hw; 1803 1804 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1805 1806 for (que = 0; que < ha->max_qpairs; que++) { 1807 if (!ha->queue_pair_map[que]) 1808 continue; 1809 1810 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1811 } 1812 } 1813 1814 static int 1815 qla2xxx_slave_alloc(struct scsi_device *sdev) 1816 { 1817 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1818 1819 if (!rport || fc_remote_port_chkready(rport)) 1820 return -ENXIO; 1821 1822 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1823 1824 return 0; 1825 } 1826 1827 static int 1828 qla2xxx_slave_configure(struct scsi_device *sdev) 1829 { 1830 scsi_qla_host_t *vha = shost_priv(sdev->host); 1831 struct req_que *req = vha->req; 1832 1833 if (IS_T10_PI_CAPABLE(vha->hw)) 1834 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1835 1836 scsi_change_queue_depth(sdev, req->max_q_depth); 1837 return 0; 1838 } 1839 1840 static void 1841 qla2xxx_slave_destroy(struct scsi_device *sdev) 1842 { 1843 sdev->hostdata = NULL; 1844 } 1845 1846 /** 1847 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1848 * @ha: HA context 1849 * 1850 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1851 * supported addressing method. 1852 */ 1853 static void 1854 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1855 { 1856 /* Assume a 32bit DMA mask. */ 1857 ha->flags.enable_64bit_addressing = 0; 1858 1859 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1860 /* Any upper-dword bits set? */ 1861 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1862 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1863 /* Ok, a 64bit DMA mask is applicable. */ 1864 ha->flags.enable_64bit_addressing = 1; 1865 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1866 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1867 return; 1868 } 1869 } 1870 1871 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1872 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1873 } 1874 1875 static void 1876 qla2x00_enable_intrs(struct qla_hw_data *ha) 1877 { 1878 unsigned long flags = 0; 1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1880 1881 spin_lock_irqsave(&ha->hardware_lock, flags); 1882 ha->interrupts_on = 1; 1883 /* enable risc and host interrupts */ 1884 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1885 RD_REG_WORD(®->ictrl); 1886 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1887 1888 } 1889 1890 static void 1891 qla2x00_disable_intrs(struct qla_hw_data *ha) 1892 { 1893 unsigned long flags = 0; 1894 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1895 1896 spin_lock_irqsave(&ha->hardware_lock, flags); 1897 ha->interrupts_on = 0; 1898 /* disable risc and host interrupts */ 1899 WRT_REG_WORD(®->ictrl, 0); 1900 RD_REG_WORD(®->ictrl); 1901 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1902 } 1903 1904 static void 1905 qla24xx_enable_intrs(struct qla_hw_data *ha) 1906 { 1907 unsigned long flags = 0; 1908 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1909 1910 spin_lock_irqsave(&ha->hardware_lock, flags); 1911 ha->interrupts_on = 1; 1912 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1913 RD_REG_DWORD(®->ictrl); 1914 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1915 } 1916 1917 static void 1918 qla24xx_disable_intrs(struct qla_hw_data *ha) 1919 { 1920 unsigned long flags = 0; 1921 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1922 1923 if (IS_NOPOLLING_TYPE(ha)) 1924 return; 1925 spin_lock_irqsave(&ha->hardware_lock, flags); 1926 ha->interrupts_on = 0; 1927 WRT_REG_DWORD(®->ictrl, 0); 1928 RD_REG_DWORD(®->ictrl); 1929 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1930 } 1931 1932 static int 1933 qla2x00_iospace_config(struct qla_hw_data *ha) 1934 { 1935 resource_size_t pio; 1936 uint16_t msix; 1937 1938 if (pci_request_selected_regions(ha->pdev, ha->bars, 1939 QLA2XXX_DRIVER_NAME)) { 1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1941 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1942 pci_name(ha->pdev)); 1943 goto iospace_error_exit; 1944 } 1945 if (!(ha->bars & 1)) 1946 goto skip_pio; 1947 1948 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1949 pio = pci_resource_start(ha->pdev, 0); 1950 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1951 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1952 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1953 "Invalid pci I/O region size (%s).\n", 1954 pci_name(ha->pdev)); 1955 pio = 0; 1956 } 1957 } else { 1958 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1959 "Region #0 no a PIO resource (%s).\n", 1960 pci_name(ha->pdev)); 1961 pio = 0; 1962 } 1963 ha->pio_address = pio; 1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1965 "PIO address=%llu.\n", 1966 (unsigned long long)ha->pio_address); 1967 1968 skip_pio: 1969 /* Use MMIO operations for all accesses. */ 1970 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1972 "Region #1 not an MMIO resource (%s), aborting.\n", 1973 pci_name(ha->pdev)); 1974 goto iospace_error_exit; 1975 } 1976 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1978 "Invalid PCI mem region size (%s), aborting.\n", 1979 pci_name(ha->pdev)); 1980 goto iospace_error_exit; 1981 } 1982 1983 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1984 if (!ha->iobase) { 1985 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1986 "Cannot remap MMIO (%s), aborting.\n", 1987 pci_name(ha->pdev)); 1988 goto iospace_error_exit; 1989 } 1990 1991 /* Determine queue resources */ 1992 ha->max_req_queues = ha->max_rsp_queues = 1; 1993 ha->msix_count = QLA_BASE_VECTORS; 1994 if (!ql2xmqsupport || !ql2xnvmeenable || 1995 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1996 goto mqiobase_exit; 1997 1998 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1999 pci_resource_len(ha->pdev, 3)); 2000 if (ha->mqiobase) { 2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2002 "MQIO Base=%p.\n", ha->mqiobase); 2003 /* Read MSIX vector size of the board */ 2004 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2005 ha->msix_count = msix + 1; 2006 /* Max queues are bounded by available msix vectors */ 2007 /* MB interrupt uses 1 vector */ 2008 ha->max_req_queues = ha->msix_count - 1; 2009 ha->max_rsp_queues = ha->max_req_queues; 2010 /* Queue pairs is the max value minus the base queue pair */ 2011 ha->max_qpairs = ha->max_rsp_queues - 1; 2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2013 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2014 2015 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2016 "MSI-X vector count: %d.\n", ha->msix_count); 2017 } else 2018 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2019 "BAR 3 not enabled.\n"); 2020 2021 mqiobase_exit: 2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2023 "MSIX Count: %d.\n", ha->msix_count); 2024 return (0); 2025 2026 iospace_error_exit: 2027 return (-ENOMEM); 2028 } 2029 2030 2031 static int 2032 qla83xx_iospace_config(struct qla_hw_data *ha) 2033 { 2034 uint16_t msix; 2035 2036 if (pci_request_selected_regions(ha->pdev, ha->bars, 2037 QLA2XXX_DRIVER_NAME)) { 2038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2039 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2040 pci_name(ha->pdev)); 2041 2042 goto iospace_error_exit; 2043 } 2044 2045 /* Use MMIO operations for all accesses. */ 2046 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2047 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2048 "Invalid pci I/O region size (%s).\n", 2049 pci_name(ha->pdev)); 2050 goto iospace_error_exit; 2051 } 2052 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2053 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2054 "Invalid PCI mem region size (%s), aborting\n", 2055 pci_name(ha->pdev)); 2056 goto iospace_error_exit; 2057 } 2058 2059 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2060 if (!ha->iobase) { 2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2062 "Cannot remap MMIO (%s), aborting.\n", 2063 pci_name(ha->pdev)); 2064 goto iospace_error_exit; 2065 } 2066 2067 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2068 /* 83XX 26XX always use MQ type access for queues 2069 * - mbar 2, a.k.a region 4 */ 2070 ha->max_req_queues = ha->max_rsp_queues = 1; 2071 ha->msix_count = QLA_BASE_VECTORS; 2072 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2073 pci_resource_len(ha->pdev, 4)); 2074 2075 if (!ha->mqiobase) { 2076 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2077 "BAR2/region4 not enabled\n"); 2078 goto mqiobase_exit; 2079 } 2080 2081 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2082 pci_resource_len(ha->pdev, 2)); 2083 if (ha->msixbase) { 2084 /* Read MSIX vector size of the board */ 2085 pci_read_config_word(ha->pdev, 2086 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2087 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2088 /* 2089 * By default, driver uses at least two msix vectors 2090 * (default & rspq) 2091 */ 2092 if (ql2xmqsupport || ql2xnvmeenable) { 2093 /* MB interrupt uses 1 vector */ 2094 ha->max_req_queues = ha->msix_count - 1; 2095 2096 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2097 if (QLA_TGT_MODE_ENABLED()) 2098 ha->max_req_queues--; 2099 2100 ha->max_rsp_queues = ha->max_req_queues; 2101 2102 /* Queue pairs is the max value minus 2103 * the base queue pair */ 2104 ha->max_qpairs = ha->max_req_queues - 1; 2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2106 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2107 } 2108 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2109 "MSI-X vector count: %d.\n", ha->msix_count); 2110 } else 2111 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2112 "BAR 1 not enabled.\n"); 2113 2114 mqiobase_exit: 2115 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2116 "MSIX Count: %d.\n", ha->msix_count); 2117 return 0; 2118 2119 iospace_error_exit: 2120 return -ENOMEM; 2121 } 2122 2123 static struct isp_operations qla2100_isp_ops = { 2124 .pci_config = qla2100_pci_config, 2125 .reset_chip = qla2x00_reset_chip, 2126 .chip_diag = qla2x00_chip_diag, 2127 .config_rings = qla2x00_config_rings, 2128 .reset_adapter = qla2x00_reset_adapter, 2129 .nvram_config = qla2x00_nvram_config, 2130 .update_fw_options = qla2x00_update_fw_options, 2131 .load_risc = qla2x00_load_risc, 2132 .pci_info_str = qla2x00_pci_info_str, 2133 .fw_version_str = qla2x00_fw_version_str, 2134 .intr_handler = qla2100_intr_handler, 2135 .enable_intrs = qla2x00_enable_intrs, 2136 .disable_intrs = qla2x00_disable_intrs, 2137 .abort_command = qla2x00_abort_command, 2138 .target_reset = qla2x00_abort_target, 2139 .lun_reset = qla2x00_lun_reset, 2140 .fabric_login = qla2x00_login_fabric, 2141 .fabric_logout = qla2x00_fabric_logout, 2142 .calc_req_entries = qla2x00_calc_iocbs_32, 2143 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2144 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2145 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2146 .read_nvram = qla2x00_read_nvram_data, 2147 .write_nvram = qla2x00_write_nvram_data, 2148 .fw_dump = qla2100_fw_dump, 2149 .beacon_on = NULL, 2150 .beacon_off = NULL, 2151 .beacon_blink = NULL, 2152 .read_optrom = qla2x00_read_optrom_data, 2153 .write_optrom = qla2x00_write_optrom_data, 2154 .get_flash_version = qla2x00_get_flash_version, 2155 .start_scsi = qla2x00_start_scsi, 2156 .start_scsi_mq = NULL, 2157 .abort_isp = qla2x00_abort_isp, 2158 .iospace_config = qla2x00_iospace_config, 2159 .initialize_adapter = qla2x00_initialize_adapter, 2160 }; 2161 2162 static struct isp_operations qla2300_isp_ops = { 2163 .pci_config = qla2300_pci_config, 2164 .reset_chip = qla2x00_reset_chip, 2165 .chip_diag = qla2x00_chip_diag, 2166 .config_rings = qla2x00_config_rings, 2167 .reset_adapter = qla2x00_reset_adapter, 2168 .nvram_config = qla2x00_nvram_config, 2169 .update_fw_options = qla2x00_update_fw_options, 2170 .load_risc = qla2x00_load_risc, 2171 .pci_info_str = qla2x00_pci_info_str, 2172 .fw_version_str = qla2x00_fw_version_str, 2173 .intr_handler = qla2300_intr_handler, 2174 .enable_intrs = qla2x00_enable_intrs, 2175 .disable_intrs = qla2x00_disable_intrs, 2176 .abort_command = qla2x00_abort_command, 2177 .target_reset = qla2x00_abort_target, 2178 .lun_reset = qla2x00_lun_reset, 2179 .fabric_login = qla2x00_login_fabric, 2180 .fabric_logout = qla2x00_fabric_logout, 2181 .calc_req_entries = qla2x00_calc_iocbs_32, 2182 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2183 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2184 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2185 .read_nvram = qla2x00_read_nvram_data, 2186 .write_nvram = qla2x00_write_nvram_data, 2187 .fw_dump = qla2300_fw_dump, 2188 .beacon_on = qla2x00_beacon_on, 2189 .beacon_off = qla2x00_beacon_off, 2190 .beacon_blink = qla2x00_beacon_blink, 2191 .read_optrom = qla2x00_read_optrom_data, 2192 .write_optrom = qla2x00_write_optrom_data, 2193 .get_flash_version = qla2x00_get_flash_version, 2194 .start_scsi = qla2x00_start_scsi, 2195 .start_scsi_mq = NULL, 2196 .abort_isp = qla2x00_abort_isp, 2197 .iospace_config = qla2x00_iospace_config, 2198 .initialize_adapter = qla2x00_initialize_adapter, 2199 }; 2200 2201 static struct isp_operations qla24xx_isp_ops = { 2202 .pci_config = qla24xx_pci_config, 2203 .reset_chip = qla24xx_reset_chip, 2204 .chip_diag = qla24xx_chip_diag, 2205 .config_rings = qla24xx_config_rings, 2206 .reset_adapter = qla24xx_reset_adapter, 2207 .nvram_config = qla24xx_nvram_config, 2208 .update_fw_options = qla24xx_update_fw_options, 2209 .load_risc = qla24xx_load_risc, 2210 .pci_info_str = qla24xx_pci_info_str, 2211 .fw_version_str = qla24xx_fw_version_str, 2212 .intr_handler = qla24xx_intr_handler, 2213 .enable_intrs = qla24xx_enable_intrs, 2214 .disable_intrs = qla24xx_disable_intrs, 2215 .abort_command = qla24xx_abort_command, 2216 .target_reset = qla24xx_abort_target, 2217 .lun_reset = qla24xx_lun_reset, 2218 .fabric_login = qla24xx_login_fabric, 2219 .fabric_logout = qla24xx_fabric_logout, 2220 .calc_req_entries = NULL, 2221 .build_iocbs = NULL, 2222 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2223 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2224 .read_nvram = qla24xx_read_nvram_data, 2225 .write_nvram = qla24xx_write_nvram_data, 2226 .fw_dump = qla24xx_fw_dump, 2227 .beacon_on = qla24xx_beacon_on, 2228 .beacon_off = qla24xx_beacon_off, 2229 .beacon_blink = qla24xx_beacon_blink, 2230 .read_optrom = qla24xx_read_optrom_data, 2231 .write_optrom = qla24xx_write_optrom_data, 2232 .get_flash_version = qla24xx_get_flash_version, 2233 .start_scsi = qla24xx_start_scsi, 2234 .start_scsi_mq = NULL, 2235 .abort_isp = qla2x00_abort_isp, 2236 .iospace_config = qla2x00_iospace_config, 2237 .initialize_adapter = qla2x00_initialize_adapter, 2238 }; 2239 2240 static struct isp_operations qla25xx_isp_ops = { 2241 .pci_config = qla25xx_pci_config, 2242 .reset_chip = qla24xx_reset_chip, 2243 .chip_diag = qla24xx_chip_diag, 2244 .config_rings = qla24xx_config_rings, 2245 .reset_adapter = qla24xx_reset_adapter, 2246 .nvram_config = qla24xx_nvram_config, 2247 .update_fw_options = qla24xx_update_fw_options, 2248 .load_risc = qla24xx_load_risc, 2249 .pci_info_str = qla24xx_pci_info_str, 2250 .fw_version_str = qla24xx_fw_version_str, 2251 .intr_handler = qla24xx_intr_handler, 2252 .enable_intrs = qla24xx_enable_intrs, 2253 .disable_intrs = qla24xx_disable_intrs, 2254 .abort_command = qla24xx_abort_command, 2255 .target_reset = qla24xx_abort_target, 2256 .lun_reset = qla24xx_lun_reset, 2257 .fabric_login = qla24xx_login_fabric, 2258 .fabric_logout = qla24xx_fabric_logout, 2259 .calc_req_entries = NULL, 2260 .build_iocbs = NULL, 2261 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2262 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2263 .read_nvram = qla25xx_read_nvram_data, 2264 .write_nvram = qla25xx_write_nvram_data, 2265 .fw_dump = qla25xx_fw_dump, 2266 .beacon_on = qla24xx_beacon_on, 2267 .beacon_off = qla24xx_beacon_off, 2268 .beacon_blink = qla24xx_beacon_blink, 2269 .read_optrom = qla25xx_read_optrom_data, 2270 .write_optrom = qla24xx_write_optrom_data, 2271 .get_flash_version = qla24xx_get_flash_version, 2272 .start_scsi = qla24xx_dif_start_scsi, 2273 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2274 .abort_isp = qla2x00_abort_isp, 2275 .iospace_config = qla2x00_iospace_config, 2276 .initialize_adapter = qla2x00_initialize_adapter, 2277 }; 2278 2279 static struct isp_operations qla81xx_isp_ops = { 2280 .pci_config = qla25xx_pci_config, 2281 .reset_chip = qla24xx_reset_chip, 2282 .chip_diag = qla24xx_chip_diag, 2283 .config_rings = qla24xx_config_rings, 2284 .reset_adapter = qla24xx_reset_adapter, 2285 .nvram_config = qla81xx_nvram_config, 2286 .update_fw_options = qla81xx_update_fw_options, 2287 .load_risc = qla81xx_load_risc, 2288 .pci_info_str = qla24xx_pci_info_str, 2289 .fw_version_str = qla24xx_fw_version_str, 2290 .intr_handler = qla24xx_intr_handler, 2291 .enable_intrs = qla24xx_enable_intrs, 2292 .disable_intrs = qla24xx_disable_intrs, 2293 .abort_command = qla24xx_abort_command, 2294 .target_reset = qla24xx_abort_target, 2295 .lun_reset = qla24xx_lun_reset, 2296 .fabric_login = qla24xx_login_fabric, 2297 .fabric_logout = qla24xx_fabric_logout, 2298 .calc_req_entries = NULL, 2299 .build_iocbs = NULL, 2300 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2301 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2302 .read_nvram = NULL, 2303 .write_nvram = NULL, 2304 .fw_dump = qla81xx_fw_dump, 2305 .beacon_on = qla24xx_beacon_on, 2306 .beacon_off = qla24xx_beacon_off, 2307 .beacon_blink = qla83xx_beacon_blink, 2308 .read_optrom = qla25xx_read_optrom_data, 2309 .write_optrom = qla24xx_write_optrom_data, 2310 .get_flash_version = qla24xx_get_flash_version, 2311 .start_scsi = qla24xx_dif_start_scsi, 2312 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2313 .abort_isp = qla2x00_abort_isp, 2314 .iospace_config = qla2x00_iospace_config, 2315 .initialize_adapter = qla2x00_initialize_adapter, 2316 }; 2317 2318 static struct isp_operations qla82xx_isp_ops = { 2319 .pci_config = qla82xx_pci_config, 2320 .reset_chip = qla82xx_reset_chip, 2321 .chip_diag = qla24xx_chip_diag, 2322 .config_rings = qla82xx_config_rings, 2323 .reset_adapter = qla24xx_reset_adapter, 2324 .nvram_config = qla81xx_nvram_config, 2325 .update_fw_options = qla24xx_update_fw_options, 2326 .load_risc = qla82xx_load_risc, 2327 .pci_info_str = qla24xx_pci_info_str, 2328 .fw_version_str = qla24xx_fw_version_str, 2329 .intr_handler = qla82xx_intr_handler, 2330 .enable_intrs = qla82xx_enable_intrs, 2331 .disable_intrs = qla82xx_disable_intrs, 2332 .abort_command = qla24xx_abort_command, 2333 .target_reset = qla24xx_abort_target, 2334 .lun_reset = qla24xx_lun_reset, 2335 .fabric_login = qla24xx_login_fabric, 2336 .fabric_logout = qla24xx_fabric_logout, 2337 .calc_req_entries = NULL, 2338 .build_iocbs = NULL, 2339 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2340 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2341 .read_nvram = qla24xx_read_nvram_data, 2342 .write_nvram = qla24xx_write_nvram_data, 2343 .fw_dump = qla82xx_fw_dump, 2344 .beacon_on = qla82xx_beacon_on, 2345 .beacon_off = qla82xx_beacon_off, 2346 .beacon_blink = NULL, 2347 .read_optrom = qla82xx_read_optrom_data, 2348 .write_optrom = qla82xx_write_optrom_data, 2349 .get_flash_version = qla82xx_get_flash_version, 2350 .start_scsi = qla82xx_start_scsi, 2351 .start_scsi_mq = NULL, 2352 .abort_isp = qla82xx_abort_isp, 2353 .iospace_config = qla82xx_iospace_config, 2354 .initialize_adapter = qla2x00_initialize_adapter, 2355 }; 2356 2357 static struct isp_operations qla8044_isp_ops = { 2358 .pci_config = qla82xx_pci_config, 2359 .reset_chip = qla82xx_reset_chip, 2360 .chip_diag = qla24xx_chip_diag, 2361 .config_rings = qla82xx_config_rings, 2362 .reset_adapter = qla24xx_reset_adapter, 2363 .nvram_config = qla81xx_nvram_config, 2364 .update_fw_options = qla24xx_update_fw_options, 2365 .load_risc = qla82xx_load_risc, 2366 .pci_info_str = qla24xx_pci_info_str, 2367 .fw_version_str = qla24xx_fw_version_str, 2368 .intr_handler = qla8044_intr_handler, 2369 .enable_intrs = qla82xx_enable_intrs, 2370 .disable_intrs = qla82xx_disable_intrs, 2371 .abort_command = qla24xx_abort_command, 2372 .target_reset = qla24xx_abort_target, 2373 .lun_reset = qla24xx_lun_reset, 2374 .fabric_login = qla24xx_login_fabric, 2375 .fabric_logout = qla24xx_fabric_logout, 2376 .calc_req_entries = NULL, 2377 .build_iocbs = NULL, 2378 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2379 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2380 .read_nvram = NULL, 2381 .write_nvram = NULL, 2382 .fw_dump = qla8044_fw_dump, 2383 .beacon_on = qla82xx_beacon_on, 2384 .beacon_off = qla82xx_beacon_off, 2385 .beacon_blink = NULL, 2386 .read_optrom = qla8044_read_optrom_data, 2387 .write_optrom = qla8044_write_optrom_data, 2388 .get_flash_version = qla82xx_get_flash_version, 2389 .start_scsi = qla82xx_start_scsi, 2390 .start_scsi_mq = NULL, 2391 .abort_isp = qla8044_abort_isp, 2392 .iospace_config = qla82xx_iospace_config, 2393 .initialize_adapter = qla2x00_initialize_adapter, 2394 }; 2395 2396 static struct isp_operations qla83xx_isp_ops = { 2397 .pci_config = qla25xx_pci_config, 2398 .reset_chip = qla24xx_reset_chip, 2399 .chip_diag = qla24xx_chip_diag, 2400 .config_rings = qla24xx_config_rings, 2401 .reset_adapter = qla24xx_reset_adapter, 2402 .nvram_config = qla81xx_nvram_config, 2403 .update_fw_options = qla81xx_update_fw_options, 2404 .load_risc = qla81xx_load_risc, 2405 .pci_info_str = qla24xx_pci_info_str, 2406 .fw_version_str = qla24xx_fw_version_str, 2407 .intr_handler = qla24xx_intr_handler, 2408 .enable_intrs = qla24xx_enable_intrs, 2409 .disable_intrs = qla24xx_disable_intrs, 2410 .abort_command = qla24xx_abort_command, 2411 .target_reset = qla24xx_abort_target, 2412 .lun_reset = qla24xx_lun_reset, 2413 .fabric_login = qla24xx_login_fabric, 2414 .fabric_logout = qla24xx_fabric_logout, 2415 .calc_req_entries = NULL, 2416 .build_iocbs = NULL, 2417 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2418 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2419 .read_nvram = NULL, 2420 .write_nvram = NULL, 2421 .fw_dump = qla83xx_fw_dump, 2422 .beacon_on = qla24xx_beacon_on, 2423 .beacon_off = qla24xx_beacon_off, 2424 .beacon_blink = qla83xx_beacon_blink, 2425 .read_optrom = qla25xx_read_optrom_data, 2426 .write_optrom = qla24xx_write_optrom_data, 2427 .get_flash_version = qla24xx_get_flash_version, 2428 .start_scsi = qla24xx_dif_start_scsi, 2429 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2430 .abort_isp = qla2x00_abort_isp, 2431 .iospace_config = qla83xx_iospace_config, 2432 .initialize_adapter = qla2x00_initialize_adapter, 2433 }; 2434 2435 static struct isp_operations qlafx00_isp_ops = { 2436 .pci_config = qlafx00_pci_config, 2437 .reset_chip = qlafx00_soft_reset, 2438 .chip_diag = qlafx00_chip_diag, 2439 .config_rings = qlafx00_config_rings, 2440 .reset_adapter = qlafx00_soft_reset, 2441 .nvram_config = NULL, 2442 .update_fw_options = NULL, 2443 .load_risc = NULL, 2444 .pci_info_str = qlafx00_pci_info_str, 2445 .fw_version_str = qlafx00_fw_version_str, 2446 .intr_handler = qlafx00_intr_handler, 2447 .enable_intrs = qlafx00_enable_intrs, 2448 .disable_intrs = qlafx00_disable_intrs, 2449 .abort_command = qla24xx_async_abort_command, 2450 .target_reset = qlafx00_abort_target, 2451 .lun_reset = qlafx00_lun_reset, 2452 .fabric_login = NULL, 2453 .fabric_logout = NULL, 2454 .calc_req_entries = NULL, 2455 .build_iocbs = NULL, 2456 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2457 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2458 .read_nvram = qla24xx_read_nvram_data, 2459 .write_nvram = qla24xx_write_nvram_data, 2460 .fw_dump = NULL, 2461 .beacon_on = qla24xx_beacon_on, 2462 .beacon_off = qla24xx_beacon_off, 2463 .beacon_blink = NULL, 2464 .read_optrom = qla24xx_read_optrom_data, 2465 .write_optrom = qla24xx_write_optrom_data, 2466 .get_flash_version = qla24xx_get_flash_version, 2467 .start_scsi = qlafx00_start_scsi, 2468 .start_scsi_mq = NULL, 2469 .abort_isp = qlafx00_abort_isp, 2470 .iospace_config = qlafx00_iospace_config, 2471 .initialize_adapter = qlafx00_initialize_adapter, 2472 }; 2473 2474 static struct isp_operations qla27xx_isp_ops = { 2475 .pci_config = qla25xx_pci_config, 2476 .reset_chip = qla24xx_reset_chip, 2477 .chip_diag = qla24xx_chip_diag, 2478 .config_rings = qla24xx_config_rings, 2479 .reset_adapter = qla24xx_reset_adapter, 2480 .nvram_config = qla81xx_nvram_config, 2481 .update_fw_options = qla81xx_update_fw_options, 2482 .load_risc = qla81xx_load_risc, 2483 .pci_info_str = qla24xx_pci_info_str, 2484 .fw_version_str = qla24xx_fw_version_str, 2485 .intr_handler = qla24xx_intr_handler, 2486 .enable_intrs = qla24xx_enable_intrs, 2487 .disable_intrs = qla24xx_disable_intrs, 2488 .abort_command = qla24xx_abort_command, 2489 .target_reset = qla24xx_abort_target, 2490 .lun_reset = qla24xx_lun_reset, 2491 .fabric_login = qla24xx_login_fabric, 2492 .fabric_logout = qla24xx_fabric_logout, 2493 .calc_req_entries = NULL, 2494 .build_iocbs = NULL, 2495 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2496 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2497 .read_nvram = NULL, 2498 .write_nvram = NULL, 2499 .fw_dump = qla27xx_fwdump, 2500 .beacon_on = qla24xx_beacon_on, 2501 .beacon_off = qla24xx_beacon_off, 2502 .beacon_blink = qla83xx_beacon_blink, 2503 .read_optrom = qla25xx_read_optrom_data, 2504 .write_optrom = qla24xx_write_optrom_data, 2505 .get_flash_version = qla24xx_get_flash_version, 2506 .start_scsi = qla24xx_dif_start_scsi, 2507 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2508 .abort_isp = qla2x00_abort_isp, 2509 .iospace_config = qla83xx_iospace_config, 2510 .initialize_adapter = qla2x00_initialize_adapter, 2511 }; 2512 2513 static inline void 2514 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2515 { 2516 ha->device_type = DT_EXTENDED_IDS; 2517 switch (ha->pdev->device) { 2518 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2519 ha->isp_type |= DT_ISP2100; 2520 ha->device_type &= ~DT_EXTENDED_IDS; 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2522 break; 2523 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2524 ha->isp_type |= DT_ISP2200; 2525 ha->device_type &= ~DT_EXTENDED_IDS; 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2527 break; 2528 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2529 ha->isp_type |= DT_ISP2300; 2530 ha->device_type |= DT_ZIO_SUPPORTED; 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2532 break; 2533 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2534 ha->isp_type |= DT_ISP2312; 2535 ha->device_type |= DT_ZIO_SUPPORTED; 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2537 break; 2538 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2539 ha->isp_type |= DT_ISP2322; 2540 ha->device_type |= DT_ZIO_SUPPORTED; 2541 if (ha->pdev->subsystem_vendor == 0x1028 && 2542 ha->pdev->subsystem_device == 0x0170) 2543 ha->device_type |= DT_OEM_001; 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2545 break; 2546 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2547 ha->isp_type |= DT_ISP6312; 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2549 break; 2550 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2551 ha->isp_type |= DT_ISP6322; 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2553 break; 2554 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2555 ha->isp_type |= DT_ISP2422; 2556 ha->device_type |= DT_ZIO_SUPPORTED; 2557 ha->device_type |= DT_FWI2; 2558 ha->device_type |= DT_IIDMA; 2559 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2560 break; 2561 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2562 ha->isp_type |= DT_ISP2432; 2563 ha->device_type |= DT_ZIO_SUPPORTED; 2564 ha->device_type |= DT_FWI2; 2565 ha->device_type |= DT_IIDMA; 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2567 break; 2568 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2569 ha->isp_type |= DT_ISP8432; 2570 ha->device_type |= DT_ZIO_SUPPORTED; 2571 ha->device_type |= DT_FWI2; 2572 ha->device_type |= DT_IIDMA; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2576 ha->isp_type |= DT_ISP5422; 2577 ha->device_type |= DT_FWI2; 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2579 break; 2580 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2581 ha->isp_type |= DT_ISP5432; 2582 ha->device_type |= DT_FWI2; 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2584 break; 2585 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2586 ha->isp_type |= DT_ISP2532; 2587 ha->device_type |= DT_ZIO_SUPPORTED; 2588 ha->device_type |= DT_FWI2; 2589 ha->device_type |= DT_IIDMA; 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2591 break; 2592 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2593 ha->isp_type |= DT_ISP8001; 2594 ha->device_type |= DT_ZIO_SUPPORTED; 2595 ha->device_type |= DT_FWI2; 2596 ha->device_type |= DT_IIDMA; 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2600 ha->isp_type |= DT_ISP8021; 2601 ha->device_type |= DT_ZIO_SUPPORTED; 2602 ha->device_type |= DT_FWI2; 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2604 /* Initialize 82XX ISP flags */ 2605 qla82xx_init_flags(ha); 2606 break; 2607 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2608 ha->isp_type |= DT_ISP8044; 2609 ha->device_type |= DT_ZIO_SUPPORTED; 2610 ha->device_type |= DT_FWI2; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 /* Initialize 82XX ISP flags */ 2613 qla82xx_init_flags(ha); 2614 break; 2615 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2616 ha->isp_type |= DT_ISP2031; 2617 ha->device_type |= DT_ZIO_SUPPORTED; 2618 ha->device_type |= DT_FWI2; 2619 ha->device_type |= DT_IIDMA; 2620 ha->device_type |= DT_T10_PI; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2622 break; 2623 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2624 ha->isp_type |= DT_ISP8031; 2625 ha->device_type |= DT_ZIO_SUPPORTED; 2626 ha->device_type |= DT_FWI2; 2627 ha->device_type |= DT_IIDMA; 2628 ha->device_type |= DT_T10_PI; 2629 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2630 break; 2631 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2632 ha->isp_type |= DT_ISPFX00; 2633 break; 2634 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2635 ha->isp_type |= DT_ISP2071; 2636 ha->device_type |= DT_ZIO_SUPPORTED; 2637 ha->device_type |= DT_FWI2; 2638 ha->device_type |= DT_IIDMA; 2639 ha->device_type |= DT_T10_PI; 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2643 ha->isp_type |= DT_ISP2271; 2644 ha->device_type |= DT_ZIO_SUPPORTED; 2645 ha->device_type |= DT_FWI2; 2646 ha->device_type |= DT_IIDMA; 2647 ha->device_type |= DT_T10_PI; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2651 ha->isp_type |= DT_ISP2261; 2652 ha->device_type |= DT_ZIO_SUPPORTED; 2653 ha->device_type |= DT_FWI2; 2654 ha->device_type |= DT_IIDMA; 2655 ha->device_type |= DT_T10_PI; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2657 break; 2658 } 2659 2660 if (IS_QLA82XX(ha)) 2661 ha->port_no = ha->portnum & 1; 2662 else { 2663 /* Get adapter physical port no from interrupt pin register. */ 2664 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2665 if (IS_QLA27XX(ha)) 2666 ha->port_no--; 2667 else 2668 ha->port_no = !(ha->port_no & 1); 2669 } 2670 2671 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2672 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2673 ha->device_type, ha->port_no, ha->fw_srisc_address); 2674 } 2675 2676 static void 2677 qla2xxx_scan_start(struct Scsi_Host *shost) 2678 { 2679 scsi_qla_host_t *vha = shost_priv(shost); 2680 2681 if (vha->hw->flags.running_gold_fw) 2682 return; 2683 2684 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2685 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2686 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2687 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2688 } 2689 2690 static int 2691 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2692 { 2693 scsi_qla_host_t *vha = shost_priv(shost); 2694 2695 if (test_bit(UNLOADING, &vha->dpc_flags)) 2696 return 1; 2697 if (!vha->host) 2698 return 1; 2699 if (time > vha->hw->loop_reset_delay * HZ) 2700 return 1; 2701 2702 return atomic_read(&vha->loop_state) == LOOP_READY; 2703 } 2704 2705 static void qla2x00_iocb_work_fn(struct work_struct *work) 2706 { 2707 struct scsi_qla_host *vha = container_of(work, 2708 struct scsi_qla_host, iocb_work); 2709 struct qla_hw_data *ha = vha->hw; 2710 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2711 int i = 20; 2712 unsigned long flags; 2713 2714 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2715 return; 2716 2717 while (!list_empty(&vha->work_list) && i > 0) { 2718 qla2x00_do_work(vha); 2719 i--; 2720 } 2721 2722 spin_lock_irqsave(&vha->work_lock, flags); 2723 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2724 spin_unlock_irqrestore(&vha->work_lock, flags); 2725 } 2726 2727 /* 2728 * PCI driver interface 2729 */ 2730 static int 2731 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2732 { 2733 int ret = -ENODEV; 2734 struct Scsi_Host *host; 2735 scsi_qla_host_t *base_vha = NULL; 2736 struct qla_hw_data *ha; 2737 char pci_info[30]; 2738 char fw_str[30], wq_name[30]; 2739 struct scsi_host_template *sht; 2740 int bars, mem_only = 0; 2741 uint16_t req_length = 0, rsp_length = 0; 2742 struct req_que *req = NULL; 2743 struct rsp_que *rsp = NULL; 2744 int i; 2745 2746 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2747 sht = &qla2xxx_driver_template; 2748 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2763 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2764 mem_only = 1; 2765 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2766 "Mem only adapter.\n"); 2767 } 2768 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2769 "Bars=%d.\n", bars); 2770 2771 if (mem_only) { 2772 if (pci_enable_device_mem(pdev)) 2773 return ret; 2774 } else { 2775 if (pci_enable_device(pdev)) 2776 return ret; 2777 } 2778 2779 /* This may fail but that's ok */ 2780 pci_enable_pcie_error_reporting(pdev); 2781 2782 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2783 if (!ha) { 2784 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2785 "Unable to allocate memory for ha.\n"); 2786 goto disable_device; 2787 } 2788 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2789 "Memory allocated for ha=%p.\n", ha); 2790 ha->pdev = pdev; 2791 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2792 spin_lock_init(&ha->tgt.q_full_lock); 2793 spin_lock_init(&ha->tgt.sess_lock); 2794 spin_lock_init(&ha->tgt.atio_lock); 2795 2796 atomic_set(&ha->nvme_active_aen_cnt, 0); 2797 2798 /* Clear our data area */ 2799 ha->bars = bars; 2800 ha->mem_only = mem_only; 2801 spin_lock_init(&ha->hardware_lock); 2802 spin_lock_init(&ha->vport_slock); 2803 mutex_init(&ha->selflogin_lock); 2804 mutex_init(&ha->optrom_mutex); 2805 2806 /* Set ISP-type information. */ 2807 qla2x00_set_isp_flags(ha); 2808 2809 /* Set EEH reset type to fundamental if required by hba */ 2810 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2811 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2812 pdev->needs_freset = 1; 2813 2814 ha->prev_topology = 0; 2815 ha->init_cb_size = sizeof(init_cb_t); 2816 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2817 ha->optrom_size = OPTROM_SIZE_2300; 2818 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2819 2820 /* Assign ISP specific operations. */ 2821 if (IS_QLA2100(ha)) { 2822 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2823 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2824 req_length = REQUEST_ENTRY_CNT_2100; 2825 rsp_length = RESPONSE_ENTRY_CNT_2100; 2826 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2827 ha->gid_list_info_size = 4; 2828 ha->flash_conf_off = ~0; 2829 ha->flash_data_off = ~0; 2830 ha->nvram_conf_off = ~0; 2831 ha->nvram_data_off = ~0; 2832 ha->isp_ops = &qla2100_isp_ops; 2833 } else if (IS_QLA2200(ha)) { 2834 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2835 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2836 req_length = REQUEST_ENTRY_CNT_2200; 2837 rsp_length = RESPONSE_ENTRY_CNT_2100; 2838 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2839 ha->gid_list_info_size = 4; 2840 ha->flash_conf_off = ~0; 2841 ha->flash_data_off = ~0; 2842 ha->nvram_conf_off = ~0; 2843 ha->nvram_data_off = ~0; 2844 ha->isp_ops = &qla2100_isp_ops; 2845 } else if (IS_QLA23XX(ha)) { 2846 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2847 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2848 req_length = REQUEST_ENTRY_CNT_2200; 2849 rsp_length = RESPONSE_ENTRY_CNT_2300; 2850 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2851 ha->gid_list_info_size = 6; 2852 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2853 ha->optrom_size = OPTROM_SIZE_2322; 2854 ha->flash_conf_off = ~0; 2855 ha->flash_data_off = ~0; 2856 ha->nvram_conf_off = ~0; 2857 ha->nvram_data_off = ~0; 2858 ha->isp_ops = &qla2300_isp_ops; 2859 } else if (IS_QLA24XX_TYPE(ha)) { 2860 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2861 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2862 req_length = REQUEST_ENTRY_CNT_24XX; 2863 rsp_length = RESPONSE_ENTRY_CNT_2300; 2864 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2865 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2866 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2867 ha->gid_list_info_size = 8; 2868 ha->optrom_size = OPTROM_SIZE_24XX; 2869 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2870 ha->isp_ops = &qla24xx_isp_ops; 2871 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2872 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2873 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2874 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2875 } else if (IS_QLA25XX(ha)) { 2876 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2877 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2878 req_length = REQUEST_ENTRY_CNT_24XX; 2879 rsp_length = RESPONSE_ENTRY_CNT_2300; 2880 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2881 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2882 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2883 ha->gid_list_info_size = 8; 2884 ha->optrom_size = OPTROM_SIZE_25XX; 2885 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2886 ha->isp_ops = &qla25xx_isp_ops; 2887 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2888 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2889 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2890 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2891 } else if (IS_QLA81XX(ha)) { 2892 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2893 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2894 req_length = REQUEST_ENTRY_CNT_24XX; 2895 rsp_length = RESPONSE_ENTRY_CNT_2300; 2896 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2897 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2898 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2899 ha->gid_list_info_size = 8; 2900 ha->optrom_size = OPTROM_SIZE_81XX; 2901 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2902 ha->isp_ops = &qla81xx_isp_ops; 2903 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2904 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2905 ha->nvram_conf_off = ~0; 2906 ha->nvram_data_off = ~0; 2907 } else if (IS_QLA82XX(ha)) { 2908 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2909 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2910 req_length = REQUEST_ENTRY_CNT_82XX; 2911 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2912 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2913 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2914 ha->gid_list_info_size = 8; 2915 ha->optrom_size = OPTROM_SIZE_82XX; 2916 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2917 ha->isp_ops = &qla82xx_isp_ops; 2918 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2919 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2920 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2921 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2922 } else if (IS_QLA8044(ha)) { 2923 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2924 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2925 req_length = REQUEST_ENTRY_CNT_82XX; 2926 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2927 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2928 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2929 ha->gid_list_info_size = 8; 2930 ha->optrom_size = OPTROM_SIZE_83XX; 2931 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2932 ha->isp_ops = &qla8044_isp_ops; 2933 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2934 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2935 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2936 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2937 } else if (IS_QLA83XX(ha)) { 2938 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2939 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2940 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2941 req_length = REQUEST_ENTRY_CNT_83XX; 2942 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2943 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2944 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2945 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2946 ha->gid_list_info_size = 8; 2947 ha->optrom_size = OPTROM_SIZE_83XX; 2948 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2949 ha->isp_ops = &qla83xx_isp_ops; 2950 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2951 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2952 ha->nvram_conf_off = ~0; 2953 ha->nvram_data_off = ~0; 2954 } else if (IS_QLAFX00(ha)) { 2955 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2956 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2957 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2958 req_length = REQUEST_ENTRY_CNT_FX00; 2959 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2960 ha->isp_ops = &qlafx00_isp_ops; 2961 ha->port_down_retry_count = 30; /* default value */ 2962 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2963 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2964 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2965 ha->mr.fw_hbt_en = 1; 2966 ha->mr.host_info_resend = false; 2967 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2968 } else if (IS_QLA27XX(ha)) { 2969 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2970 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2971 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2972 req_length = REQUEST_ENTRY_CNT_83XX; 2973 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2974 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2975 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2976 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2977 ha->gid_list_info_size = 8; 2978 ha->optrom_size = OPTROM_SIZE_83XX; 2979 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2980 ha->isp_ops = &qla27xx_isp_ops; 2981 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2982 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2983 ha->nvram_conf_off = ~0; 2984 ha->nvram_data_off = ~0; 2985 } 2986 2987 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2988 "mbx_count=%d, req_length=%d, " 2989 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2990 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2991 "max_fibre_devices=%d.\n", 2992 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2993 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2994 ha->nvram_npiv_size, ha->max_fibre_devices); 2995 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2996 "isp_ops=%p, flash_conf_off=%d, " 2997 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2998 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2999 ha->nvram_conf_off, ha->nvram_data_off); 3000 3001 /* Configure PCI I/O space */ 3002 ret = ha->isp_ops->iospace_config(ha); 3003 if (ret) 3004 goto iospace_config_failed; 3005 3006 ql_log_pci(ql_log_info, pdev, 0x001d, 3007 "Found an ISP%04X irq %d iobase 0x%p.\n", 3008 pdev->device, pdev->irq, ha->iobase); 3009 mutex_init(&ha->vport_lock); 3010 mutex_init(&ha->mq_lock); 3011 init_completion(&ha->mbx_cmd_comp); 3012 complete(&ha->mbx_cmd_comp); 3013 init_completion(&ha->mbx_intr_comp); 3014 init_completion(&ha->dcbx_comp); 3015 init_completion(&ha->lb_portup_comp); 3016 3017 set_bit(0, (unsigned long *) ha->vp_idx_map); 3018 3019 qla2x00_config_dma_addressing(ha); 3020 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3021 "64 Bit addressing is %s.\n", 3022 ha->flags.enable_64bit_addressing ? "enable" : 3023 "disable"); 3024 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3025 if (ret) { 3026 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3027 "Failed to allocate memory for adapter, aborting.\n"); 3028 3029 goto probe_hw_failed; 3030 } 3031 3032 req->max_q_depth = MAX_Q_DEPTH; 3033 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3034 req->max_q_depth = ql2xmaxqdepth; 3035 3036 3037 base_vha = qla2x00_create_host(sht, ha); 3038 if (!base_vha) { 3039 ret = -ENOMEM; 3040 goto probe_hw_failed; 3041 } 3042 3043 pci_set_drvdata(pdev, base_vha); 3044 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3045 3046 host = base_vha->host; 3047 base_vha->req = req; 3048 if (IS_QLA2XXX_MIDTYPE(ha)) 3049 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER; 3050 else 3051 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3052 base_vha->vp_idx; 3053 3054 /* Setup fcport template structure. */ 3055 ha->mr.fcport.vha = base_vha; 3056 ha->mr.fcport.port_type = FCT_UNKNOWN; 3057 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3058 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3059 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3060 ha->mr.fcport.scan_state = 1; 3061 3062 /* Set the SG table size based on ISP type */ 3063 if (!IS_FWI2_CAPABLE(ha)) { 3064 if (IS_QLA2100(ha)) 3065 host->sg_tablesize = 32; 3066 } else { 3067 if (!IS_QLA82XX(ha)) 3068 host->sg_tablesize = QLA_SG_ALL; 3069 } 3070 host->max_id = ha->max_fibre_devices; 3071 host->cmd_per_lun = 3; 3072 host->unique_id = host->host_no; 3073 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3074 host->max_cmd_len = 32; 3075 else 3076 host->max_cmd_len = MAX_CMDSZ; 3077 host->max_channel = MAX_BUSES - 1; 3078 /* Older HBAs support only 16-bit LUNs */ 3079 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3080 ql2xmaxlun > 0xffff) 3081 host->max_lun = 0xffff; 3082 else 3083 host->max_lun = ql2xmaxlun; 3084 host->transportt = qla2xxx_transport_template; 3085 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3086 3087 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3088 "max_id=%d this_id=%d " 3089 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3090 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3091 host->this_id, host->cmd_per_lun, host->unique_id, 3092 host->max_cmd_len, host->max_channel, host->max_lun, 3093 host->transportt, sht->vendor_id); 3094 3095 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3096 3097 /* Set up the irqs */ 3098 ret = qla2x00_request_irqs(ha, rsp); 3099 if (ret) 3100 goto probe_failed; 3101 3102 /* Alloc arrays of request and response ring ptrs */ 3103 ret = qla2x00_alloc_queues(ha, req, rsp); 3104 if (ret) { 3105 ql_log(ql_log_fatal, base_vha, 0x003d, 3106 "Failed to allocate memory for queue pointers..." 3107 "aborting.\n"); 3108 goto probe_failed; 3109 } 3110 3111 if (ha->mqenable && shost_use_blk_mq(host)) { 3112 /* number of hardware queues supported by blk/scsi-mq*/ 3113 host->nr_hw_queues = ha->max_qpairs; 3114 3115 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3116 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3117 } else { 3118 if (ql2xnvmeenable) { 3119 host->nr_hw_queues = ha->max_qpairs; 3120 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3121 "FC-NVMe support is enabled, HW queues=%d\n", 3122 host->nr_hw_queues); 3123 } else { 3124 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3125 "blk/scsi-mq disabled.\n"); 3126 } 3127 } 3128 3129 qlt_probe_one_stage1(base_vha, ha); 3130 3131 pci_save_state(pdev); 3132 3133 /* Assign back pointers */ 3134 rsp->req = req; 3135 req->rsp = rsp; 3136 3137 if (IS_QLAFX00(ha)) { 3138 ha->rsp_q_map[0] = rsp; 3139 ha->req_q_map[0] = req; 3140 set_bit(0, ha->req_qid_map); 3141 set_bit(0, ha->rsp_qid_map); 3142 } 3143 3144 /* FWI2-capable only. */ 3145 req->req_q_in = &ha->iobase->isp24.req_q_in; 3146 req->req_q_out = &ha->iobase->isp24.req_q_out; 3147 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3148 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3149 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3150 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3151 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3152 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3153 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3154 } 3155 3156 if (IS_QLAFX00(ha)) { 3157 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3158 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3159 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3160 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3161 } 3162 3163 if (IS_P3P_TYPE(ha)) { 3164 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3165 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3166 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3167 } 3168 3169 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3170 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3171 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3172 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3173 "req->req_q_in=%p req->req_q_out=%p " 3174 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3175 req->req_q_in, req->req_q_out, 3176 rsp->rsp_q_in, rsp->rsp_q_out); 3177 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3178 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3179 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3180 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3181 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3182 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3183 3184 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3185 3186 if (ha->isp_ops->initialize_adapter(base_vha)) { 3187 ql_log(ql_log_fatal, base_vha, 0x00d6, 3188 "Failed to initialize adapter - Adapter flags %x.\n", 3189 base_vha->device_flags); 3190 3191 if (IS_QLA82XX(ha)) { 3192 qla82xx_idc_lock(ha); 3193 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3194 QLA8XXX_DEV_FAILED); 3195 qla82xx_idc_unlock(ha); 3196 ql_log(ql_log_fatal, base_vha, 0x00d7, 3197 "HW State: FAILED.\n"); 3198 } else if (IS_QLA8044(ha)) { 3199 qla8044_idc_lock(ha); 3200 qla8044_wr_direct(base_vha, 3201 QLA8044_CRB_DEV_STATE_INDEX, 3202 QLA8XXX_DEV_FAILED); 3203 qla8044_idc_unlock(ha); 3204 ql_log(ql_log_fatal, base_vha, 0x0150, 3205 "HW State: FAILED.\n"); 3206 } 3207 3208 ret = -ENODEV; 3209 goto probe_failed; 3210 } 3211 3212 if (IS_QLAFX00(ha)) 3213 host->can_queue = QLAFX00_MAX_CANQUEUE; 3214 else 3215 host->can_queue = req->num_outstanding_cmds - 10; 3216 3217 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3218 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3219 host->can_queue, base_vha->req, 3220 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3221 3222 if (ha->mqenable) { 3223 bool mq = false; 3224 bool startit = false; 3225 3226 if (QLA_TGT_MODE_ENABLED()) { 3227 mq = true; 3228 startit = false; 3229 } 3230 3231 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3232 shost_use_blk_mq(host)) { 3233 mq = true; 3234 startit = true; 3235 } 3236 3237 if (mq) { 3238 /* Create start of day qpairs for Block MQ */ 3239 for (i = 0; i < ha->max_qpairs; i++) 3240 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3241 } 3242 } 3243 3244 if (ha->flags.running_gold_fw) 3245 goto skip_dpc; 3246 3247 /* 3248 * Startup the kernel thread for this host adapter 3249 */ 3250 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3251 "%s_dpc", base_vha->host_str); 3252 if (IS_ERR(ha->dpc_thread)) { 3253 ql_log(ql_log_fatal, base_vha, 0x00ed, 3254 "Failed to start DPC thread.\n"); 3255 ret = PTR_ERR(ha->dpc_thread); 3256 ha->dpc_thread = NULL; 3257 goto probe_failed; 3258 } 3259 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3260 "DPC thread started successfully.\n"); 3261 3262 /* 3263 * If we're not coming up in initiator mode, we might sit for 3264 * a while without waking up the dpc thread, which leads to a 3265 * stuck process warning. So just kick the dpc once here and 3266 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3267 */ 3268 qla2xxx_wake_dpc(base_vha); 3269 3270 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3271 3272 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3273 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3274 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3275 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3276 3277 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3278 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3279 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3280 INIT_WORK(&ha->idc_state_handler, 3281 qla83xx_idc_state_handler_work); 3282 INIT_WORK(&ha->nic_core_unrecoverable, 3283 qla83xx_nic_core_unrecoverable_work); 3284 } 3285 3286 skip_dpc: 3287 list_add_tail(&base_vha->list, &ha->vp_list); 3288 base_vha->host->irq = ha->pdev->irq; 3289 3290 /* Initialized the timer */ 3291 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3292 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3293 "Started qla2x00_timer with " 3294 "interval=%d.\n", WATCH_INTERVAL); 3295 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3296 "Detected hba at address=%p.\n", 3297 ha); 3298 3299 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3300 if (ha->fw_attributes & BIT_4) { 3301 int prot = 0, guard; 3302 base_vha->flags.difdix_supported = 1; 3303 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3304 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3305 if (ql2xenabledif == 1) 3306 prot = SHOST_DIX_TYPE0_PROTECTION; 3307 scsi_host_set_prot(host, 3308 prot | SHOST_DIF_TYPE1_PROTECTION 3309 | SHOST_DIF_TYPE2_PROTECTION 3310 | SHOST_DIF_TYPE3_PROTECTION 3311 | SHOST_DIX_TYPE1_PROTECTION 3312 | SHOST_DIX_TYPE2_PROTECTION 3313 | SHOST_DIX_TYPE3_PROTECTION); 3314 3315 guard = SHOST_DIX_GUARD_CRC; 3316 3317 if (IS_PI_IPGUARD_CAPABLE(ha) && 3318 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3319 guard |= SHOST_DIX_GUARD_IP; 3320 3321 scsi_host_set_guard(host, guard); 3322 } else 3323 base_vha->flags.difdix_supported = 0; 3324 } 3325 3326 ha->isp_ops->enable_intrs(ha); 3327 3328 if (IS_QLAFX00(ha)) { 3329 ret = qlafx00_fx_disc(base_vha, 3330 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3331 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3332 QLA_SG_ALL : 128; 3333 } 3334 3335 ret = scsi_add_host(host, &pdev->dev); 3336 if (ret) 3337 goto probe_failed; 3338 3339 base_vha->flags.init_done = 1; 3340 base_vha->flags.online = 1; 3341 ha->prev_minidump_failed = 0; 3342 3343 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3344 "Init done and hba is online.\n"); 3345 3346 if (qla_ini_mode_enabled(base_vha) || 3347 qla_dual_mode_enabled(base_vha)) 3348 scsi_scan_host(host); 3349 else 3350 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3351 "skipping scsi_scan_host() for non-initiator port\n"); 3352 3353 qla2x00_alloc_sysfs_attr(base_vha); 3354 3355 if (IS_QLAFX00(ha)) { 3356 ret = qlafx00_fx_disc(base_vha, 3357 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3358 3359 /* Register system information */ 3360 ret = qlafx00_fx_disc(base_vha, 3361 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3362 } 3363 3364 qla2x00_init_host_attr(base_vha); 3365 3366 qla2x00_dfs_setup(base_vha); 3367 3368 ql_log(ql_log_info, base_vha, 0x00fb, 3369 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3370 ql_log(ql_log_info, base_vha, 0x00fc, 3371 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3372 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3373 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3374 base_vha->host_no, 3375 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3376 3377 qlt_add_target(ha, base_vha); 3378 3379 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3380 3381 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3382 return -ENODEV; 3383 3384 if (ha->flags.detected_lr_sfp) { 3385 ql_log(ql_log_info, base_vha, 0xffff, 3386 "Reset chip to pick up LR SFP setting\n"); 3387 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3388 qla2xxx_wake_dpc(base_vha); 3389 } 3390 3391 return 0; 3392 3393 probe_failed: 3394 if (base_vha->timer_active) 3395 qla2x00_stop_timer(base_vha); 3396 base_vha->flags.online = 0; 3397 if (ha->dpc_thread) { 3398 struct task_struct *t = ha->dpc_thread; 3399 3400 ha->dpc_thread = NULL; 3401 kthread_stop(t); 3402 } 3403 3404 qla2x00_free_device(base_vha); 3405 scsi_host_put(base_vha->host); 3406 /* 3407 * Need to NULL out local req/rsp after 3408 * qla2x00_free_device => qla2x00_free_queues frees 3409 * what these are pointing to. Or else we'll 3410 * fall over below in qla2x00_free_req/rsp_que. 3411 */ 3412 req = NULL; 3413 rsp = NULL; 3414 3415 probe_hw_failed: 3416 qla2x00_mem_free(ha); 3417 qla2x00_free_req_que(ha, req); 3418 qla2x00_free_rsp_que(ha, rsp); 3419 qla2x00_clear_drv_active(ha); 3420 3421 iospace_config_failed: 3422 if (IS_P3P_TYPE(ha)) { 3423 if (!ha->nx_pcibase) 3424 iounmap((device_reg_t *)ha->nx_pcibase); 3425 if (!ql2xdbwr) 3426 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3427 } else { 3428 if (ha->iobase) 3429 iounmap(ha->iobase); 3430 if (ha->cregbase) 3431 iounmap(ha->cregbase); 3432 } 3433 pci_release_selected_regions(ha->pdev, ha->bars); 3434 kfree(ha); 3435 3436 disable_device: 3437 pci_disable_device(pdev); 3438 return ret; 3439 } 3440 3441 static void 3442 qla2x00_shutdown(struct pci_dev *pdev) 3443 { 3444 scsi_qla_host_t *vha; 3445 struct qla_hw_data *ha; 3446 3447 vha = pci_get_drvdata(pdev); 3448 ha = vha->hw; 3449 3450 ql_log(ql_log_info, vha, 0xfffa, 3451 "Adapter shutdown\n"); 3452 3453 /* 3454 * Prevent future board_disable and wait 3455 * until any pending board_disable has completed. 3456 */ 3457 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3458 cancel_work_sync(&ha->board_disable); 3459 3460 if (!atomic_read(&pdev->enable_cnt)) 3461 return; 3462 3463 /* Notify ISPFX00 firmware */ 3464 if (IS_QLAFX00(ha)) 3465 qlafx00_driver_shutdown(vha, 20); 3466 3467 /* Turn-off FCE trace */ 3468 if (ha->flags.fce_enabled) { 3469 qla2x00_disable_fce_trace(vha, NULL, NULL); 3470 ha->flags.fce_enabled = 0; 3471 } 3472 3473 /* Turn-off EFT trace */ 3474 if (ha->eft) 3475 qla2x00_disable_eft_trace(vha); 3476 3477 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3478 if (ha->flags.fw_started) 3479 qla2x00_abort_isp_cleanup(vha); 3480 } else { 3481 /* Stop currently executing firmware. */ 3482 qla2x00_try_to_stop_firmware(vha); 3483 } 3484 3485 /* Turn adapter off line */ 3486 vha->flags.online = 0; 3487 3488 /* turn-off interrupts on the card */ 3489 if (ha->interrupts_on) { 3490 vha->flags.init_done = 0; 3491 ha->isp_ops->disable_intrs(ha); 3492 } 3493 3494 qla2x00_free_irqs(vha); 3495 3496 qla2x00_free_fw_dump(ha); 3497 3498 pci_disable_device(pdev); 3499 ql_log(ql_log_info, vha, 0xfffe, 3500 "Adapter shutdown successfully.\n"); 3501 } 3502 3503 /* Deletes all the virtual ports for a given ha */ 3504 static void 3505 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3506 { 3507 scsi_qla_host_t *vha; 3508 unsigned long flags; 3509 3510 mutex_lock(&ha->vport_lock); 3511 while (ha->cur_vport_count) { 3512 spin_lock_irqsave(&ha->vport_slock, flags); 3513 3514 BUG_ON(base_vha->list.next == &ha->vp_list); 3515 /* This assumes first entry in ha->vp_list is always base vha */ 3516 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3517 scsi_host_get(vha->host); 3518 3519 spin_unlock_irqrestore(&ha->vport_slock, flags); 3520 mutex_unlock(&ha->vport_lock); 3521 3522 fc_vport_terminate(vha->fc_vport); 3523 scsi_host_put(vha->host); 3524 3525 mutex_lock(&ha->vport_lock); 3526 } 3527 mutex_unlock(&ha->vport_lock); 3528 } 3529 3530 /* Stops all deferred work threads */ 3531 static void 3532 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3533 { 3534 /* Cancel all work and destroy DPC workqueues */ 3535 if (ha->dpc_lp_wq) { 3536 cancel_work_sync(&ha->idc_aen); 3537 destroy_workqueue(ha->dpc_lp_wq); 3538 ha->dpc_lp_wq = NULL; 3539 } 3540 3541 if (ha->dpc_hp_wq) { 3542 cancel_work_sync(&ha->nic_core_reset); 3543 cancel_work_sync(&ha->idc_state_handler); 3544 cancel_work_sync(&ha->nic_core_unrecoverable); 3545 destroy_workqueue(ha->dpc_hp_wq); 3546 ha->dpc_hp_wq = NULL; 3547 } 3548 3549 /* Kill the kernel thread for this host */ 3550 if (ha->dpc_thread) { 3551 struct task_struct *t = ha->dpc_thread; 3552 3553 /* 3554 * qla2xxx_wake_dpc checks for ->dpc_thread 3555 * so we need to zero it out. 3556 */ 3557 ha->dpc_thread = NULL; 3558 kthread_stop(t); 3559 } 3560 } 3561 3562 static void 3563 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3564 { 3565 if (IS_QLA82XX(ha)) { 3566 3567 iounmap((device_reg_t *)ha->nx_pcibase); 3568 if (!ql2xdbwr) 3569 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3570 } else { 3571 if (ha->iobase) 3572 iounmap(ha->iobase); 3573 3574 if (ha->cregbase) 3575 iounmap(ha->cregbase); 3576 3577 if (ha->mqiobase) 3578 iounmap(ha->mqiobase); 3579 3580 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3581 iounmap(ha->msixbase); 3582 } 3583 } 3584 3585 static void 3586 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3587 { 3588 if (IS_QLA8044(ha)) { 3589 qla8044_idc_lock(ha); 3590 qla8044_clear_drv_active(ha); 3591 qla8044_idc_unlock(ha); 3592 } else if (IS_QLA82XX(ha)) { 3593 qla82xx_idc_lock(ha); 3594 qla82xx_clear_drv_active(ha); 3595 qla82xx_idc_unlock(ha); 3596 } 3597 } 3598 3599 static void 3600 qla2x00_remove_one(struct pci_dev *pdev) 3601 { 3602 scsi_qla_host_t *base_vha; 3603 struct qla_hw_data *ha; 3604 3605 base_vha = pci_get_drvdata(pdev); 3606 ha = base_vha->hw; 3607 ql_log(ql_log_info, base_vha, 0xb079, 3608 "Removing driver\n"); 3609 3610 /* Indicate device removal to prevent future board_disable and wait 3611 * until any pending board_disable has completed. */ 3612 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3613 cancel_work_sync(&ha->board_disable); 3614 3615 /* 3616 * If the PCI device is disabled then there was a PCI-disconnect and 3617 * qla2x00_disable_board_on_pci_error has taken care of most of the 3618 * resources. 3619 */ 3620 if (!atomic_read(&pdev->enable_cnt)) { 3621 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3622 base_vha->gnl.l, base_vha->gnl.ldma); 3623 3624 scsi_host_put(base_vha->host); 3625 kfree(ha); 3626 pci_set_drvdata(pdev, NULL); 3627 return; 3628 } 3629 qla2x00_wait_for_hba_ready(base_vha); 3630 3631 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3632 if (ha->flags.fw_started) 3633 qla2x00_abort_isp_cleanup(base_vha); 3634 } else if (!IS_QLAFX00(ha)) { 3635 if (IS_QLA8031(ha)) { 3636 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3637 "Clearing fcoe driver presence.\n"); 3638 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3639 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3640 "Error while clearing DRV-Presence.\n"); 3641 } 3642 3643 qla2x00_try_to_stop_firmware(base_vha); 3644 } 3645 3646 qla2x00_wait_for_sess_deletion(base_vha); 3647 3648 /* 3649 * if UNLOAD flag is already set, then continue unload, 3650 * where it was set first. 3651 */ 3652 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3653 return; 3654 3655 set_bit(UNLOADING, &base_vha->dpc_flags); 3656 3657 qla_nvme_delete(base_vha); 3658 3659 dma_free_coherent(&ha->pdev->dev, 3660 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3661 3662 vfree(base_vha->scan.l); 3663 3664 if (IS_QLAFX00(ha)) 3665 qlafx00_driver_shutdown(base_vha, 20); 3666 3667 qla2x00_delete_all_vps(ha, base_vha); 3668 3669 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3670 3671 qla2x00_dfs_remove(base_vha); 3672 3673 qla84xx_put_chip(base_vha); 3674 3675 /* Disable timer */ 3676 if (base_vha->timer_active) 3677 qla2x00_stop_timer(base_vha); 3678 3679 base_vha->flags.online = 0; 3680 3681 /* free DMA memory */ 3682 if (ha->exlogin_buf) 3683 qla2x00_free_exlogin_buffer(ha); 3684 3685 /* free DMA memory */ 3686 if (ha->exchoffld_buf) 3687 qla2x00_free_exchoffld_buffer(ha); 3688 3689 qla2x00_destroy_deferred_work(ha); 3690 3691 qlt_remove_target(ha, base_vha); 3692 3693 qla2x00_free_sysfs_attr(base_vha, true); 3694 3695 fc_remove_host(base_vha->host); 3696 qlt_remove_target_resources(ha); 3697 3698 scsi_remove_host(base_vha->host); 3699 3700 qla2x00_free_device(base_vha); 3701 3702 qla2x00_clear_drv_active(ha); 3703 3704 scsi_host_put(base_vha->host); 3705 3706 qla2x00_unmap_iobases(ha); 3707 3708 pci_release_selected_regions(ha->pdev, ha->bars); 3709 kfree(ha); 3710 3711 pci_disable_pcie_error_reporting(pdev); 3712 3713 pci_disable_device(pdev); 3714 } 3715 3716 static void 3717 qla2x00_free_device(scsi_qla_host_t *vha) 3718 { 3719 struct qla_hw_data *ha = vha->hw; 3720 3721 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3722 3723 /* Disable timer */ 3724 if (vha->timer_active) 3725 qla2x00_stop_timer(vha); 3726 3727 qla25xx_delete_queues(vha); 3728 vha->flags.online = 0; 3729 3730 /* turn-off interrupts on the card */ 3731 if (ha->interrupts_on) { 3732 vha->flags.init_done = 0; 3733 ha->isp_ops->disable_intrs(ha); 3734 } 3735 3736 qla2x00_free_fcports(vha); 3737 3738 qla2x00_free_irqs(vha); 3739 3740 /* Flush the work queue and remove it */ 3741 if (ha->wq) { 3742 flush_workqueue(ha->wq); 3743 destroy_workqueue(ha->wq); 3744 ha->wq = NULL; 3745 } 3746 3747 3748 qla2x00_mem_free(ha); 3749 3750 qla82xx_md_free(vha); 3751 3752 qla2x00_free_queues(ha); 3753 } 3754 3755 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3756 { 3757 fc_port_t *fcport, *tfcport; 3758 3759 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3760 list_del(&fcport->list); 3761 qla2x00_clear_loop_id(fcport); 3762 kfree(fcport); 3763 } 3764 } 3765 3766 static inline void 3767 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3768 int defer) 3769 { 3770 struct fc_rport *rport; 3771 scsi_qla_host_t *base_vha; 3772 unsigned long flags; 3773 3774 if (!fcport->rport) 3775 return; 3776 3777 rport = fcport->rport; 3778 if (defer) { 3779 base_vha = pci_get_drvdata(vha->hw->pdev); 3780 spin_lock_irqsave(vha->host->host_lock, flags); 3781 fcport->drport = rport; 3782 spin_unlock_irqrestore(vha->host->host_lock, flags); 3783 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3784 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3785 qla2xxx_wake_dpc(base_vha); 3786 } else { 3787 int now; 3788 if (rport) { 3789 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3790 "%s %8phN. rport %p roles %x\n", 3791 __func__, fcport->port_name, rport, 3792 rport->roles); 3793 fc_remote_port_delete(rport); 3794 } 3795 qlt_do_generation_tick(vha, &now); 3796 } 3797 } 3798 3799 /* 3800 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3801 * 3802 * Input: ha = adapter block pointer. fcport = port structure pointer. 3803 * 3804 * Return: None. 3805 * 3806 * Context: 3807 */ 3808 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3809 int do_login, int defer) 3810 { 3811 if (IS_QLAFX00(vha->hw)) { 3812 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3813 qla2x00_schedule_rport_del(vha, fcport, defer); 3814 return; 3815 } 3816 3817 if (atomic_read(&fcport->state) == FCS_ONLINE && 3818 vha->vp_idx == fcport->vha->vp_idx) { 3819 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3820 qla2x00_schedule_rport_del(vha, fcport, defer); 3821 } 3822 /* 3823 * We may need to retry the login, so don't change the state of the 3824 * port but do the retries. 3825 */ 3826 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3827 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3828 3829 if (!do_login) 3830 return; 3831 3832 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3833 3834 if (fcport->login_retry == 0) { 3835 fcport->login_retry = vha->hw->login_retry_count; 3836 3837 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3838 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3839 fcport->port_name, fcport->loop_id, fcport->login_retry); 3840 } 3841 } 3842 3843 /* 3844 * qla2x00_mark_all_devices_lost 3845 * Updates fcport state when device goes offline. 3846 * 3847 * Input: 3848 * ha = adapter block pointer. 3849 * fcport = port structure pointer. 3850 * 3851 * Return: 3852 * None. 3853 * 3854 * Context: 3855 */ 3856 void 3857 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3858 { 3859 fc_port_t *fcport; 3860 3861 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3862 "Mark all dev lost\n"); 3863 3864 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3865 fcport->scan_state = 0; 3866 qlt_schedule_sess_for_deletion(fcport); 3867 3868 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3869 continue; 3870 3871 /* 3872 * No point in marking the device as lost, if the device is 3873 * already DEAD. 3874 */ 3875 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3876 continue; 3877 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3878 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3879 if (defer) 3880 qla2x00_schedule_rport_del(vha, fcport, defer); 3881 else if (vha->vp_idx == fcport->vha->vp_idx) 3882 qla2x00_schedule_rport_del(vha, fcport, defer); 3883 } 3884 } 3885 } 3886 3887 /* 3888 * qla2x00_mem_alloc 3889 * Allocates adapter memory. 3890 * 3891 * Returns: 3892 * 0 = success. 3893 * !0 = failure. 3894 */ 3895 static int 3896 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3897 struct req_que **req, struct rsp_que **rsp) 3898 { 3899 char name[16]; 3900 3901 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3902 &ha->init_cb_dma, GFP_KERNEL); 3903 if (!ha->init_cb) 3904 goto fail; 3905 3906 if (qlt_mem_alloc(ha) < 0) 3907 goto fail_free_init_cb; 3908 3909 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3910 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3911 if (!ha->gid_list) 3912 goto fail_free_tgt_mem; 3913 3914 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3915 if (!ha->srb_mempool) 3916 goto fail_free_gid_list; 3917 3918 if (IS_P3P_TYPE(ha)) { 3919 /* Allocate cache for CT6 Ctx. */ 3920 if (!ctx_cachep) { 3921 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3922 sizeof(struct ct6_dsd), 0, 3923 SLAB_HWCACHE_ALIGN, NULL); 3924 if (!ctx_cachep) 3925 goto fail_free_srb_mempool; 3926 } 3927 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3928 ctx_cachep); 3929 if (!ha->ctx_mempool) 3930 goto fail_free_srb_mempool; 3931 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3932 "ctx_cachep=%p ctx_mempool=%p.\n", 3933 ctx_cachep, ha->ctx_mempool); 3934 } 3935 3936 /* Get memory for cached NVRAM */ 3937 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3938 if (!ha->nvram) 3939 goto fail_free_ctx_mempool; 3940 3941 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3942 ha->pdev->device); 3943 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3944 DMA_POOL_SIZE, 8, 0); 3945 if (!ha->s_dma_pool) 3946 goto fail_free_nvram; 3947 3948 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3949 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3950 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3951 3952 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3953 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3954 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3955 if (!ha->dl_dma_pool) { 3956 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3957 "Failed to allocate memory for dl_dma_pool.\n"); 3958 goto fail_s_dma_pool; 3959 } 3960 3961 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3962 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3963 if (!ha->fcp_cmnd_dma_pool) { 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3965 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3966 goto fail_dl_dma_pool; 3967 } 3968 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3969 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3970 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3971 } 3972 3973 /* Allocate memory for SNS commands */ 3974 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3975 /* Get consistent memory allocated for SNS commands */ 3976 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3977 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3978 if (!ha->sns_cmd) 3979 goto fail_dma_pool; 3980 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3981 "sns_cmd: %p.\n", ha->sns_cmd); 3982 } else { 3983 /* Get consistent memory allocated for MS IOCB */ 3984 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3985 &ha->ms_iocb_dma); 3986 if (!ha->ms_iocb) 3987 goto fail_dma_pool; 3988 /* Get consistent memory allocated for CT SNS commands */ 3989 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3990 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3991 if (!ha->ct_sns) 3992 goto fail_free_ms_iocb; 3993 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3994 "ms_iocb=%p ct_sns=%p.\n", 3995 ha->ms_iocb, ha->ct_sns); 3996 } 3997 3998 /* Allocate memory for request ring */ 3999 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4000 if (!*req) { 4001 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4002 "Failed to allocate memory for req.\n"); 4003 goto fail_req; 4004 } 4005 (*req)->length = req_len; 4006 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4007 ((*req)->length + 1) * sizeof(request_t), 4008 &(*req)->dma, GFP_KERNEL); 4009 if (!(*req)->ring) { 4010 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4011 "Failed to allocate memory for req_ring.\n"); 4012 goto fail_req_ring; 4013 } 4014 /* Allocate memory for response ring */ 4015 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4016 if (!*rsp) { 4017 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4018 "Failed to allocate memory for rsp.\n"); 4019 goto fail_rsp; 4020 } 4021 (*rsp)->hw = ha; 4022 (*rsp)->length = rsp_len; 4023 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4024 ((*rsp)->length + 1) * sizeof(response_t), 4025 &(*rsp)->dma, GFP_KERNEL); 4026 if (!(*rsp)->ring) { 4027 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4028 "Failed to allocate memory for rsp_ring.\n"); 4029 goto fail_rsp_ring; 4030 } 4031 (*req)->rsp = *rsp; 4032 (*rsp)->req = *req; 4033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4034 "req=%p req->length=%d req->ring=%p rsp=%p " 4035 "rsp->length=%d rsp->ring=%p.\n", 4036 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4037 (*rsp)->ring); 4038 /* Allocate memory for NVRAM data for vports */ 4039 if (ha->nvram_npiv_size) { 4040 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4041 sizeof(struct qla_npiv_entry), 4042 GFP_KERNEL); 4043 if (!ha->npiv_info) { 4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4045 "Failed to allocate memory for npiv_info.\n"); 4046 goto fail_npiv_info; 4047 } 4048 } else 4049 ha->npiv_info = NULL; 4050 4051 /* Get consistent memory allocated for EX-INIT-CB. */ 4052 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4053 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4054 &ha->ex_init_cb_dma); 4055 if (!ha->ex_init_cb) 4056 goto fail_ex_init_cb; 4057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4058 "ex_init_cb=%p.\n", ha->ex_init_cb); 4059 } 4060 4061 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4062 4063 /* Get consistent memory allocated for Async Port-Database. */ 4064 if (!IS_FWI2_CAPABLE(ha)) { 4065 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4066 &ha->async_pd_dma); 4067 if (!ha->async_pd) 4068 goto fail_async_pd; 4069 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4070 "async_pd=%p.\n", ha->async_pd); 4071 } 4072 4073 INIT_LIST_HEAD(&ha->vp_list); 4074 4075 /* Allocate memory for our loop_id bitmap */ 4076 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4077 sizeof(long), 4078 GFP_KERNEL); 4079 if (!ha->loop_id_map) 4080 goto fail_loop_id_map; 4081 else { 4082 qla2x00_set_reserved_loop_ids(ha); 4083 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4084 "loop_id_map=%p.\n", ha->loop_id_map); 4085 } 4086 4087 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4088 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4089 if (!ha->sfp_data) { 4090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4091 "Unable to allocate memory for SFP read-data.\n"); 4092 goto fail_sfp_data; 4093 } 4094 4095 return 0; 4096 4097 fail_sfp_data: 4098 kfree(ha->loop_id_map); 4099 fail_loop_id_map: 4100 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4101 fail_async_pd: 4102 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4103 fail_ex_init_cb: 4104 kfree(ha->npiv_info); 4105 fail_npiv_info: 4106 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4107 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4108 (*rsp)->ring = NULL; 4109 (*rsp)->dma = 0; 4110 fail_rsp_ring: 4111 kfree(*rsp); 4112 *rsp = NULL; 4113 fail_rsp: 4114 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4115 sizeof(request_t), (*req)->ring, (*req)->dma); 4116 (*req)->ring = NULL; 4117 (*req)->dma = 0; 4118 fail_req_ring: 4119 kfree(*req); 4120 *req = NULL; 4121 fail_req: 4122 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4123 ha->ct_sns, ha->ct_sns_dma); 4124 ha->ct_sns = NULL; 4125 ha->ct_sns_dma = 0; 4126 fail_free_ms_iocb: 4127 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4128 ha->ms_iocb = NULL; 4129 ha->ms_iocb_dma = 0; 4130 4131 if (ha->sns_cmd) 4132 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4133 ha->sns_cmd, ha->sns_cmd_dma); 4134 fail_dma_pool: 4135 if (IS_QLA82XX(ha) || ql2xenabledif) { 4136 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4137 ha->fcp_cmnd_dma_pool = NULL; 4138 } 4139 fail_dl_dma_pool: 4140 if (IS_QLA82XX(ha) || ql2xenabledif) { 4141 dma_pool_destroy(ha->dl_dma_pool); 4142 ha->dl_dma_pool = NULL; 4143 } 4144 fail_s_dma_pool: 4145 dma_pool_destroy(ha->s_dma_pool); 4146 ha->s_dma_pool = NULL; 4147 fail_free_nvram: 4148 kfree(ha->nvram); 4149 ha->nvram = NULL; 4150 fail_free_ctx_mempool: 4151 if (ha->ctx_mempool) 4152 mempool_destroy(ha->ctx_mempool); 4153 ha->ctx_mempool = NULL; 4154 fail_free_srb_mempool: 4155 if (ha->srb_mempool) 4156 mempool_destroy(ha->srb_mempool); 4157 ha->srb_mempool = NULL; 4158 fail_free_gid_list: 4159 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4160 ha->gid_list, 4161 ha->gid_list_dma); 4162 ha->gid_list = NULL; 4163 ha->gid_list_dma = 0; 4164 fail_free_tgt_mem: 4165 qlt_mem_free(ha); 4166 fail_free_init_cb: 4167 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4168 ha->init_cb_dma); 4169 ha->init_cb = NULL; 4170 ha->init_cb_dma = 0; 4171 fail: 4172 ql_log(ql_log_fatal, NULL, 0x0030, 4173 "Memory allocation failure.\n"); 4174 return -ENOMEM; 4175 } 4176 4177 int 4178 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4179 { 4180 int rval; 4181 uint16_t size, max_cnt, temp; 4182 struct qla_hw_data *ha = vha->hw; 4183 4184 /* Return if we don't need to alloacate any extended logins */ 4185 if (!ql2xexlogins) 4186 return QLA_SUCCESS; 4187 4188 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4189 return QLA_SUCCESS; 4190 4191 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4192 max_cnt = 0; 4193 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4194 if (rval != QLA_SUCCESS) { 4195 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4196 "Failed to get exlogin status.\n"); 4197 return rval; 4198 } 4199 4200 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4201 temp *= size; 4202 4203 if (temp != ha->exlogin_size) { 4204 qla2x00_free_exlogin_buffer(ha); 4205 ha->exlogin_size = temp; 4206 4207 ql_log(ql_log_info, vha, 0xd024, 4208 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4209 max_cnt, size, temp); 4210 4211 ql_log(ql_log_info, vha, 0xd025, 4212 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4213 4214 /* Get consistent memory for extended logins */ 4215 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4216 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4217 if (!ha->exlogin_buf) { 4218 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4219 "Failed to allocate memory for exlogin_buf_dma.\n"); 4220 return -ENOMEM; 4221 } 4222 } 4223 4224 /* Now configure the dma buffer */ 4225 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4226 if (rval) { 4227 ql_log(ql_log_fatal, vha, 0xd033, 4228 "Setup extended login buffer ****FAILED****.\n"); 4229 qla2x00_free_exlogin_buffer(ha); 4230 } 4231 4232 return rval; 4233 } 4234 4235 /* 4236 * qla2x00_free_exlogin_buffer 4237 * 4238 * Input: 4239 * ha = adapter block pointer 4240 */ 4241 void 4242 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4243 { 4244 if (ha->exlogin_buf) { 4245 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4246 ha->exlogin_buf, ha->exlogin_buf_dma); 4247 ha->exlogin_buf = NULL; 4248 ha->exlogin_size = 0; 4249 } 4250 } 4251 4252 static void 4253 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4254 { 4255 u32 temp; 4256 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4257 4258 if (max_cnt > vha->hw->max_exchg) 4259 max_cnt = vha->hw->max_exchg; 4260 4261 if (qla_ini_mode_enabled(vha)) { 4262 if (ql2xiniexchg > max_cnt) 4263 ql2xiniexchg = max_cnt; 4264 4265 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4266 *ret_cnt = ql2xiniexchg; 4267 } else if (qla_tgt_mode_enabled(vha)) { 4268 if (ql2xexchoffld > max_cnt) 4269 ql2xexchoffld = max_cnt; 4270 4271 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4272 *ret_cnt = ql2xexchoffld; 4273 } else if (qla_dual_mode_enabled(vha)) { 4274 temp = ql2xiniexchg + ql2xexchoffld; 4275 if (temp > max_cnt) { 4276 ql2xiniexchg -= (temp - max_cnt)/2; 4277 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4278 temp = max_cnt; 4279 } 4280 4281 if (temp > FW_DEF_EXCHANGES_CNT) 4282 *ret_cnt = temp; 4283 } 4284 } 4285 4286 int 4287 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4288 { 4289 int rval; 4290 u16 size, max_cnt; 4291 u32 actual_cnt, totsz; 4292 struct qla_hw_data *ha = vha->hw; 4293 4294 if (!ha->flags.exchoffld_enabled) 4295 return QLA_SUCCESS; 4296 4297 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4298 return QLA_SUCCESS; 4299 4300 max_cnt = 0; 4301 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4302 if (rval != QLA_SUCCESS) { 4303 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4304 "Failed to get exlogin status.\n"); 4305 return rval; 4306 } 4307 4308 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4309 ql_log(ql_log_info, vha, 0xd014, 4310 "Actual exchange offload count: %d.\n", actual_cnt); 4311 4312 totsz = actual_cnt * size; 4313 4314 if (totsz != ha->exchoffld_size) { 4315 qla2x00_free_exchoffld_buffer(ha); 4316 ha->exchoffld_size = totsz; 4317 4318 ql_log(ql_log_info, vha, 0xd016, 4319 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4320 max_cnt, actual_cnt, size, totsz); 4321 4322 ql_log(ql_log_info, vha, 0xd017, 4323 "Exchange Buffers requested size = 0x%x\n", 4324 ha->exchoffld_size); 4325 4326 /* Get consistent memory for extended logins */ 4327 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4328 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4329 if (!ha->exchoffld_buf) { 4330 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4331 "Failed to allocate memory for Exchange Offload.\n"); 4332 4333 if (ha->max_exchg > 4334 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4335 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4336 } else if (ha->max_exchg > 4337 (FW_DEF_EXCHANGES_CNT + 512)) { 4338 ha->max_exchg -= 512; 4339 } else { 4340 ha->flags.exchoffld_enabled = 0; 4341 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4342 "Disabling Exchange offload due to lack of memory\n"); 4343 } 4344 ha->exchoffld_size = 0; 4345 4346 return -ENOMEM; 4347 } 4348 } 4349 4350 /* Now configure the dma buffer */ 4351 rval = qla_set_exchoffld_mem_cfg(vha); 4352 if (rval) { 4353 ql_log(ql_log_fatal, vha, 0xd02e, 4354 "Setup exchange offload buffer ****FAILED****.\n"); 4355 qla2x00_free_exchoffld_buffer(ha); 4356 } else { 4357 /* re-adjust number of target exchange */ 4358 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4359 4360 if (qla_ini_mode_enabled(vha)) 4361 icb->exchange_count = 0; 4362 else 4363 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4364 } 4365 4366 return rval; 4367 } 4368 4369 /* 4370 * qla2x00_free_exchoffld_buffer 4371 * 4372 * Input: 4373 * ha = adapter block pointer 4374 */ 4375 void 4376 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4377 { 4378 if (ha->exchoffld_buf) { 4379 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4380 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4381 ha->exchoffld_buf = NULL; 4382 ha->exchoffld_size = 0; 4383 } 4384 } 4385 4386 /* 4387 * qla2x00_free_fw_dump 4388 * Frees fw dump stuff. 4389 * 4390 * Input: 4391 * ha = adapter block pointer 4392 */ 4393 static void 4394 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4395 { 4396 if (ha->fce) 4397 dma_free_coherent(&ha->pdev->dev, 4398 FCE_SIZE, ha->fce, ha->fce_dma); 4399 4400 if (ha->eft) 4401 dma_free_coherent(&ha->pdev->dev, 4402 EFT_SIZE, ha->eft, ha->eft_dma); 4403 4404 if (ha->fw_dump) 4405 vfree(ha->fw_dump); 4406 if (ha->fw_dump_template) 4407 vfree(ha->fw_dump_template); 4408 4409 ha->fce = NULL; 4410 ha->fce_dma = 0; 4411 ha->eft = NULL; 4412 ha->eft_dma = 0; 4413 ha->fw_dumped = 0; 4414 ha->fw_dump_cap_flags = 0; 4415 ha->fw_dump_reading = 0; 4416 ha->fw_dump = NULL; 4417 ha->fw_dump_len = 0; 4418 ha->fw_dump_template = NULL; 4419 ha->fw_dump_template_len = 0; 4420 } 4421 4422 /* 4423 * qla2x00_mem_free 4424 * Frees all adapter allocated memory. 4425 * 4426 * Input: 4427 * ha = adapter block pointer. 4428 */ 4429 static void 4430 qla2x00_mem_free(struct qla_hw_data *ha) 4431 { 4432 qla2x00_free_fw_dump(ha); 4433 4434 if (ha->mctp_dump) 4435 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4436 ha->mctp_dump_dma); 4437 4438 if (ha->srb_mempool) 4439 mempool_destroy(ha->srb_mempool); 4440 4441 if (ha->dcbx_tlv) 4442 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4443 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4444 4445 if (ha->xgmac_data) 4446 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4447 ha->xgmac_data, ha->xgmac_data_dma); 4448 4449 if (ha->sns_cmd) 4450 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4451 ha->sns_cmd, ha->sns_cmd_dma); 4452 4453 if (ha->ct_sns) 4454 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4455 ha->ct_sns, ha->ct_sns_dma); 4456 4457 if (ha->sfp_data) 4458 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4459 ha->sfp_data_dma); 4460 4461 if (ha->ms_iocb) 4462 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4463 4464 if (ha->ex_init_cb) 4465 dma_pool_free(ha->s_dma_pool, 4466 ha->ex_init_cb, ha->ex_init_cb_dma); 4467 4468 if (ha->async_pd) 4469 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4470 4471 if (ha->s_dma_pool) 4472 dma_pool_destroy(ha->s_dma_pool); 4473 4474 if (ha->gid_list) 4475 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4476 ha->gid_list, ha->gid_list_dma); 4477 4478 if (IS_QLA82XX(ha)) { 4479 if (!list_empty(&ha->gbl_dsd_list)) { 4480 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4481 4482 /* clean up allocated prev pool */ 4483 list_for_each_entry_safe(dsd_ptr, 4484 tdsd_ptr, &ha->gbl_dsd_list, list) { 4485 dma_pool_free(ha->dl_dma_pool, 4486 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4487 list_del(&dsd_ptr->list); 4488 kfree(dsd_ptr); 4489 } 4490 } 4491 } 4492 4493 if (ha->dl_dma_pool) 4494 dma_pool_destroy(ha->dl_dma_pool); 4495 4496 if (ha->fcp_cmnd_dma_pool) 4497 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4498 4499 if (ha->ctx_mempool) 4500 mempool_destroy(ha->ctx_mempool); 4501 4502 qlt_mem_free(ha); 4503 4504 if (ha->init_cb) 4505 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4506 ha->init_cb, ha->init_cb_dma); 4507 4508 vfree(ha->optrom_buffer); 4509 kfree(ha->nvram); 4510 kfree(ha->npiv_info); 4511 kfree(ha->swl); 4512 kfree(ha->loop_id_map); 4513 4514 ha->srb_mempool = NULL; 4515 ha->ctx_mempool = NULL; 4516 ha->sns_cmd = NULL; 4517 ha->sns_cmd_dma = 0; 4518 ha->ct_sns = NULL; 4519 ha->ct_sns_dma = 0; 4520 ha->ms_iocb = NULL; 4521 ha->ms_iocb_dma = 0; 4522 ha->init_cb = NULL; 4523 ha->init_cb_dma = 0; 4524 ha->ex_init_cb = NULL; 4525 ha->ex_init_cb_dma = 0; 4526 ha->async_pd = NULL; 4527 ha->async_pd_dma = 0; 4528 ha->loop_id_map = NULL; 4529 ha->npiv_info = NULL; 4530 ha->optrom_buffer = NULL; 4531 ha->swl = NULL; 4532 ha->nvram = NULL; 4533 ha->mctp_dump = NULL; 4534 ha->dcbx_tlv = NULL; 4535 ha->xgmac_data = NULL; 4536 ha->sfp_data = NULL; 4537 4538 ha->s_dma_pool = NULL; 4539 ha->dl_dma_pool = NULL; 4540 ha->fcp_cmnd_dma_pool = NULL; 4541 4542 ha->gid_list = NULL; 4543 ha->gid_list_dma = 0; 4544 4545 ha->tgt.atio_ring = NULL; 4546 ha->tgt.atio_dma = 0; 4547 ha->tgt.tgt_vp_map = NULL; 4548 } 4549 4550 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4551 struct qla_hw_data *ha) 4552 { 4553 struct Scsi_Host *host; 4554 struct scsi_qla_host *vha = NULL; 4555 4556 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4557 if (!host) { 4558 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4559 "Failed to allocate host from the scsi layer, aborting.\n"); 4560 return NULL; 4561 } 4562 4563 /* Clear our data area */ 4564 vha = shost_priv(host); 4565 memset(vha, 0, sizeof(scsi_qla_host_t)); 4566 4567 vha->host = host; 4568 vha->host_no = host->host_no; 4569 vha->hw = ha; 4570 4571 INIT_LIST_HEAD(&vha->vp_fcports); 4572 INIT_LIST_HEAD(&vha->work_list); 4573 INIT_LIST_HEAD(&vha->list); 4574 INIT_LIST_HEAD(&vha->qla_cmd_list); 4575 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4576 INIT_LIST_HEAD(&vha->logo_list); 4577 INIT_LIST_HEAD(&vha->plogi_ack_list); 4578 INIT_LIST_HEAD(&vha->qp_list); 4579 INIT_LIST_HEAD(&vha->gnl.fcports); 4580 INIT_LIST_HEAD(&vha->nvme_rport_list); 4581 INIT_LIST_HEAD(&vha->gpnid_list); 4582 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4583 4584 spin_lock_init(&vha->work_lock); 4585 spin_lock_init(&vha->cmd_list_lock); 4586 spin_lock_init(&vha->gnl.fcports_lock); 4587 init_waitqueue_head(&vha->fcport_waitQ); 4588 init_waitqueue_head(&vha->vref_waitq); 4589 4590 vha->gnl.size = sizeof(struct get_name_list_extended) * 4591 (ha->max_loop_id + 1); 4592 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4593 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4594 if (!vha->gnl.l) { 4595 ql_log(ql_log_fatal, vha, 0xd04a, 4596 "Alloc failed for name list.\n"); 4597 scsi_remove_host(vha->host); 4598 return NULL; 4599 } 4600 4601 /* todo: what about ext login? */ 4602 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4603 vha->scan.l = vmalloc(vha->scan.size); 4604 if (!vha->scan.l) { 4605 ql_log(ql_log_fatal, vha, 0xd04a, 4606 "Alloc failed for scan database.\n"); 4607 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4608 vha->gnl.l, vha->gnl.ldma); 4609 scsi_remove_host(vha->host); 4610 return NULL; 4611 } 4612 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4613 4614 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4615 ql_dbg(ql_dbg_init, vha, 0x0041, 4616 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4617 vha->host, vha->hw, vha, 4618 dev_name(&(ha->pdev->dev))); 4619 4620 return vha; 4621 } 4622 4623 struct qla_work_evt * 4624 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4625 { 4626 struct qla_work_evt *e; 4627 uint8_t bail; 4628 4629 QLA_VHA_MARK_BUSY(vha, bail); 4630 if (bail) 4631 return NULL; 4632 4633 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4634 if (!e) { 4635 QLA_VHA_MARK_NOT_BUSY(vha); 4636 return NULL; 4637 } 4638 4639 INIT_LIST_HEAD(&e->list); 4640 e->type = type; 4641 e->flags = QLA_EVT_FLAG_FREE; 4642 return e; 4643 } 4644 4645 int 4646 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4647 { 4648 unsigned long flags; 4649 bool q = false; 4650 4651 spin_lock_irqsave(&vha->work_lock, flags); 4652 list_add_tail(&e->list, &vha->work_list); 4653 4654 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4655 q = true; 4656 4657 spin_unlock_irqrestore(&vha->work_lock, flags); 4658 4659 if (q) 4660 queue_work(vha->hw->wq, &vha->iocb_work); 4661 4662 return QLA_SUCCESS; 4663 } 4664 4665 int 4666 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4667 u32 data) 4668 { 4669 struct qla_work_evt *e; 4670 4671 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4672 if (!e) 4673 return QLA_FUNCTION_FAILED; 4674 4675 e->u.aen.code = code; 4676 e->u.aen.data = data; 4677 return qla2x00_post_work(vha, e); 4678 } 4679 4680 int 4681 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4682 { 4683 struct qla_work_evt *e; 4684 4685 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4686 if (!e) 4687 return QLA_FUNCTION_FAILED; 4688 4689 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4690 return qla2x00_post_work(vha, e); 4691 } 4692 4693 #define qla2x00_post_async_work(name, type) \ 4694 int qla2x00_post_async_##name##_work( \ 4695 struct scsi_qla_host *vha, \ 4696 fc_port_t *fcport, uint16_t *data) \ 4697 { \ 4698 struct qla_work_evt *e; \ 4699 \ 4700 e = qla2x00_alloc_work(vha, type); \ 4701 if (!e) \ 4702 return QLA_FUNCTION_FAILED; \ 4703 \ 4704 e->u.logio.fcport = fcport; \ 4705 if (data) { \ 4706 e->u.logio.data[0] = data[0]; \ 4707 e->u.logio.data[1] = data[1]; \ 4708 } \ 4709 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4710 return qla2x00_post_work(vha, e); \ 4711 } 4712 4713 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4714 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4715 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4716 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4717 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4718 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4719 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4720 4721 int 4722 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4723 { 4724 struct qla_work_evt *e; 4725 4726 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4727 if (!e) 4728 return QLA_FUNCTION_FAILED; 4729 4730 e->u.uevent.code = code; 4731 return qla2x00_post_work(vha, e); 4732 } 4733 4734 static void 4735 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4736 { 4737 char event_string[40]; 4738 char *envp[] = { event_string, NULL }; 4739 4740 switch (code) { 4741 case QLA_UEVENT_CODE_FW_DUMP: 4742 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4743 vha->host_no); 4744 break; 4745 default: 4746 /* do nothing */ 4747 break; 4748 } 4749 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4750 } 4751 4752 int 4753 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4754 uint32_t *data, int cnt) 4755 { 4756 struct qla_work_evt *e; 4757 4758 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4759 if (!e) 4760 return QLA_FUNCTION_FAILED; 4761 4762 e->u.aenfx.evtcode = evtcode; 4763 e->u.aenfx.count = cnt; 4764 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4765 return qla2x00_post_work(vha, e); 4766 } 4767 4768 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4769 { 4770 struct qla_work_evt *e; 4771 4772 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4773 if (!e) 4774 return QLA_FUNCTION_FAILED; 4775 4776 e->u.fcport.fcport = fcport; 4777 return qla2x00_post_work(vha, e); 4778 } 4779 4780 static 4781 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4782 { 4783 unsigned long flags; 4784 fc_port_t *fcport = NULL, *tfcp; 4785 struct qlt_plogi_ack_t *pla = 4786 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4787 uint8_t free_fcport = 0; 4788 u64 wwn; 4789 4790 ql_dbg(ql_dbg_disc, vha, 0xffff, 4791 "%s %d %8phC enter\n", 4792 __func__, __LINE__, e->u.new_sess.port_name); 4793 4794 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4795 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4796 if (fcport) { 4797 fcport->d_id = e->u.new_sess.id; 4798 if (pla) { 4799 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4800 memcpy(fcport->node_name, 4801 pla->iocb.u.isp24.u.plogi.node_name, 4802 WWN_SIZE); 4803 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4804 /* we took an extra ref_count to prevent PLOGI ACK when 4805 * fcport/sess has not been created. 4806 */ 4807 pla->ref_count--; 4808 } 4809 } else { 4810 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4811 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4812 if (fcport) { 4813 fcport->d_id = e->u.new_sess.id; 4814 fcport->flags |= FCF_FABRIC_DEVICE; 4815 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4816 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP) 4817 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4818 4819 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) { 4820 fcport->fc4_type = FC4_TYPE_OTHER; 4821 fcport->fc4f_nvme = FC4_TYPE_NVME; 4822 } 4823 4824 memcpy(fcport->port_name, e->u.new_sess.port_name, 4825 WWN_SIZE); 4826 } else { 4827 ql_dbg(ql_dbg_disc, vha, 0xffff, 4828 "%s %8phC mem alloc fail.\n", 4829 __func__, e->u.new_sess.port_name); 4830 4831 if (pla) 4832 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4833 return; 4834 } 4835 4836 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4837 /* search again to make sure no one else got ahead */ 4838 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4839 e->u.new_sess.port_name, 1); 4840 if (tfcp) { 4841 /* should rarily happen */ 4842 ql_dbg(ql_dbg_disc, vha, 0xffff, 4843 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4844 __func__, tfcp->port_name, tfcp->disc_state, 4845 tfcp->fw_login_state); 4846 4847 free_fcport = 1; 4848 } else { 4849 list_add_tail(&fcport->list, &vha->vp_fcports); 4850 4851 } 4852 if (pla) { 4853 qlt_plogi_ack_link(vha, pla, fcport, 4854 QLT_PLOGI_LINK_SAME_WWN); 4855 pla->ref_count--; 4856 } 4857 } 4858 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4859 4860 if (fcport) { 4861 if (N2N_TOPO(vha->hw)) 4862 fcport->flags &= ~FCF_FABRIC_DEVICE; 4863 4864 fcport->id_changed = 1; 4865 fcport->scan_state = QLA_FCPORT_FOUND; 4866 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4867 4868 if (pla) { 4869 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4870 u16 wd3_lo; 4871 4872 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4873 fcport->local = 0; 4874 fcport->loop_id = 4875 le16_to_cpu( 4876 pla->iocb.u.isp24.nport_handle); 4877 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4878 wd3_lo = 4879 le16_to_cpu( 4880 pla->iocb.u.isp24.u.prli.wd3_lo); 4881 4882 if (wd3_lo & BIT_7) 4883 fcport->conf_compl_supported = 1; 4884 4885 if ((wd3_lo & BIT_4) == 0) 4886 fcport->port_type = FCT_INITIATOR; 4887 else 4888 fcport->port_type = FCT_TARGET; 4889 } 4890 qlt_plogi_ack_unref(vha, pla); 4891 } else { 4892 fc_port_t *dfcp = NULL; 4893 4894 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4895 tfcp = qla2x00_find_fcport_by_nportid(vha, 4896 &e->u.new_sess.id, 1); 4897 if (tfcp && (tfcp != fcport)) { 4898 /* 4899 * We have a conflict fcport with same NportID. 4900 */ 4901 ql_dbg(ql_dbg_disc, vha, 0xffff, 4902 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4903 __func__, tfcp->port_name, tfcp->disc_state, 4904 tfcp->fw_login_state); 4905 4906 switch (tfcp->disc_state) { 4907 case DSC_DELETED: 4908 break; 4909 case DSC_DELETE_PEND: 4910 fcport->login_pause = 1; 4911 tfcp->conflict = fcport; 4912 break; 4913 default: 4914 fcport->login_pause = 1; 4915 tfcp->conflict = fcport; 4916 dfcp = tfcp; 4917 break; 4918 } 4919 } 4920 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4921 if (dfcp) 4922 qlt_schedule_sess_for_deletion(tfcp); 4923 4924 wwn = wwn_to_u64(fcport->node_name); 4925 4926 if (!wwn) 4927 qla24xx_async_gnnid(vha, fcport); 4928 else 4929 qla24xx_async_gnl(vha, fcport); 4930 } 4931 } 4932 4933 if (free_fcport) { 4934 qla2x00_free_fcport(fcport); 4935 if (pla) 4936 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4937 } 4938 } 4939 4940 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4941 { 4942 struct srb *sp = e->u.iosb.sp; 4943 int rval; 4944 4945 rval = qla2x00_start_sp(sp); 4946 if (rval != QLA_SUCCESS) { 4947 ql_dbg(ql_dbg_disc, vha, 0x2043, 4948 "%s: %s: Re-issue IOCB failed (%d).\n", 4949 __func__, sp->name, rval); 4950 qla24xx_sp_unmap(vha, sp); 4951 } 4952 } 4953 4954 void 4955 qla2x00_do_work(struct scsi_qla_host *vha) 4956 { 4957 struct qla_work_evt *e, *tmp; 4958 unsigned long flags; 4959 LIST_HEAD(work); 4960 4961 spin_lock_irqsave(&vha->work_lock, flags); 4962 list_splice_init(&vha->work_list, &work); 4963 spin_unlock_irqrestore(&vha->work_lock, flags); 4964 4965 list_for_each_entry_safe(e, tmp, &work, list) { 4966 list_del_init(&e->list); 4967 4968 switch (e->type) { 4969 case QLA_EVT_AEN: 4970 fc_host_post_event(vha->host, fc_get_event_number(), 4971 e->u.aen.code, e->u.aen.data); 4972 break; 4973 case QLA_EVT_IDC_ACK: 4974 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4975 break; 4976 case QLA_EVT_ASYNC_LOGIN: 4977 qla2x00_async_login(vha, e->u.logio.fcport, 4978 e->u.logio.data); 4979 break; 4980 case QLA_EVT_ASYNC_LOGOUT: 4981 qla2x00_async_logout(vha, e->u.logio.fcport); 4982 break; 4983 case QLA_EVT_ASYNC_LOGOUT_DONE: 4984 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4985 e->u.logio.data); 4986 break; 4987 case QLA_EVT_ASYNC_ADISC: 4988 qla2x00_async_adisc(vha, e->u.logio.fcport, 4989 e->u.logio.data); 4990 break; 4991 case QLA_EVT_ASYNC_ADISC_DONE: 4992 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4993 e->u.logio.data); 4994 break; 4995 case QLA_EVT_UEVENT: 4996 qla2x00_uevent_emit(vha, e->u.uevent.code); 4997 break; 4998 case QLA_EVT_AENFX: 4999 qlafx00_process_aen(vha, e); 5000 break; 5001 case QLA_EVT_GIDPN: 5002 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 5003 break; 5004 case QLA_EVT_GPNID: 5005 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5006 break; 5007 case QLA_EVT_UNMAP: 5008 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5009 break; 5010 case QLA_EVT_RELOGIN: 5011 qla2x00_relogin(vha); 5012 break; 5013 case QLA_EVT_NEW_SESS: 5014 qla24xx_create_new_sess(vha, e); 5015 break; 5016 case QLA_EVT_GPDB: 5017 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5018 e->u.fcport.opt); 5019 break; 5020 case QLA_EVT_PRLI: 5021 qla24xx_async_prli(vha, e->u.fcport.fcport); 5022 break; 5023 case QLA_EVT_GPSC: 5024 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5025 break; 5026 case QLA_EVT_UPD_FCPORT: 5027 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5028 break; 5029 case QLA_EVT_GNL: 5030 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5031 break; 5032 case QLA_EVT_NACK: 5033 qla24xx_do_nack_work(vha, e); 5034 break; 5035 case QLA_EVT_ASYNC_PRLO: 5036 qla2x00_async_prlo(vha, e->u.logio.fcport); 5037 break; 5038 case QLA_EVT_ASYNC_PRLO_DONE: 5039 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5040 e->u.logio.data); 5041 break; 5042 case QLA_EVT_GPNFT: 5043 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5044 e->u.gpnft.sp); 5045 break; 5046 case QLA_EVT_GPNFT_DONE: 5047 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5048 break; 5049 case QLA_EVT_GNNFT_DONE: 5050 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5051 break; 5052 case QLA_EVT_GNNID: 5053 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5054 break; 5055 case QLA_EVT_GFPNID: 5056 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5057 break; 5058 case QLA_EVT_SP_RETRY: 5059 qla_sp_retry(vha, e); 5060 break; 5061 case QLA_EVT_IIDMA: 5062 qla_do_iidma_work(vha, e->u.fcport.fcport); 5063 break; 5064 } 5065 if (e->flags & QLA_EVT_FLAG_FREE) 5066 kfree(e); 5067 5068 /* For each work completed decrement vha ref count */ 5069 QLA_VHA_MARK_NOT_BUSY(vha); 5070 } 5071 } 5072 5073 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5074 { 5075 struct qla_work_evt *e; 5076 5077 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5078 5079 if (!e) { 5080 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5081 return QLA_FUNCTION_FAILED; 5082 } 5083 5084 return qla2x00_post_work(vha, e); 5085 } 5086 5087 /* Relogins all the fcports of a vport 5088 * Context: dpc thread 5089 */ 5090 void qla2x00_relogin(struct scsi_qla_host *vha) 5091 { 5092 fc_port_t *fcport; 5093 int status; 5094 struct event_arg ea; 5095 5096 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5097 /* 5098 * If the port is not ONLINE then try to login 5099 * to it if we haven't run out of retries. 5100 */ 5101 if (atomic_read(&fcport->state) != FCS_ONLINE && 5102 fcport->login_retry && 5103 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) { 5104 if (vha->hw->current_topology != ISP_CFG_NL) { 5105 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 5106 "%s %8phC DS %d LS %d\n", __func__, 5107 fcport->port_name, fcport->disc_state, 5108 fcport->fw_login_state); 5109 memset(&ea, 0, sizeof(ea)); 5110 ea.event = FCME_RELOGIN; 5111 ea.fcport = fcport; 5112 qla2x00_fcport_event_handler(vha, &ea); 5113 } else if (vha->hw->current_topology == ISP_CFG_NL) { 5114 fcport->login_retry--; 5115 status = qla2x00_local_device_login(vha, 5116 fcport); 5117 if (status == QLA_SUCCESS) { 5118 fcport->old_loop_id = fcport->loop_id; 5119 ql_dbg(ql_dbg_disc, vha, 0x2003, 5120 "Port login OK: logged in ID 0x%x.\n", 5121 fcport->loop_id); 5122 qla2x00_update_fcport(vha, fcport); 5123 } else if (status == 1) { 5124 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5125 /* retry the login again */ 5126 ql_dbg(ql_dbg_disc, vha, 0x2007, 5127 "Retrying %d login again loop_id 0x%x.\n", 5128 fcport->login_retry, 5129 fcport->loop_id); 5130 } else { 5131 fcport->login_retry = 0; 5132 } 5133 5134 if (fcport->login_retry == 0 && 5135 status != QLA_SUCCESS) 5136 qla2x00_clear_loop_id(fcport); 5137 } 5138 } 5139 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5140 break; 5141 } 5142 5143 ql_dbg(ql_dbg_disc, vha, 0x400e, 5144 "Relogin end.\n"); 5145 } 5146 5147 /* Schedule work on any of the dpc-workqueues */ 5148 void 5149 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5150 { 5151 struct qla_hw_data *ha = base_vha->hw; 5152 5153 switch (work_code) { 5154 case MBA_IDC_AEN: /* 0x8200 */ 5155 if (ha->dpc_lp_wq) 5156 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5157 break; 5158 5159 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5160 if (!ha->flags.nic_core_reset_hdlr_active) { 5161 if (ha->dpc_hp_wq) 5162 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5163 } else 5164 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5165 "NIC Core reset is already active. Skip " 5166 "scheduling it again.\n"); 5167 break; 5168 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5169 if (ha->dpc_hp_wq) 5170 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5171 break; 5172 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5173 if (ha->dpc_hp_wq) 5174 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5175 break; 5176 default: 5177 ql_log(ql_log_warn, base_vha, 0xb05f, 5178 "Unknown work-code=0x%x.\n", work_code); 5179 } 5180 5181 return; 5182 } 5183 5184 /* Work: Perform NIC Core Unrecoverable state handling */ 5185 void 5186 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5187 { 5188 struct qla_hw_data *ha = 5189 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5191 uint32_t dev_state = 0; 5192 5193 qla83xx_idc_lock(base_vha, 0); 5194 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5195 qla83xx_reset_ownership(base_vha); 5196 if (ha->flags.nic_core_reset_owner) { 5197 ha->flags.nic_core_reset_owner = 0; 5198 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5199 QLA8XXX_DEV_FAILED); 5200 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5201 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5202 } 5203 qla83xx_idc_unlock(base_vha, 0); 5204 } 5205 5206 /* Work: Execute IDC state handler */ 5207 void 5208 qla83xx_idc_state_handler_work(struct work_struct *work) 5209 { 5210 struct qla_hw_data *ha = 5211 container_of(work, struct qla_hw_data, idc_state_handler); 5212 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5213 uint32_t dev_state = 0; 5214 5215 qla83xx_idc_lock(base_vha, 0); 5216 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5217 if (dev_state == QLA8XXX_DEV_FAILED || 5218 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5219 qla83xx_idc_state_handler(base_vha); 5220 qla83xx_idc_unlock(base_vha, 0); 5221 } 5222 5223 static int 5224 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5225 { 5226 int rval = QLA_SUCCESS; 5227 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5228 uint32_t heart_beat_counter1, heart_beat_counter2; 5229 5230 do { 5231 if (time_after(jiffies, heart_beat_wait)) { 5232 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5233 "Nic Core f/w is not alive.\n"); 5234 rval = QLA_FUNCTION_FAILED; 5235 break; 5236 } 5237 5238 qla83xx_idc_lock(base_vha, 0); 5239 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5240 &heart_beat_counter1); 5241 qla83xx_idc_unlock(base_vha, 0); 5242 msleep(100); 5243 qla83xx_idc_lock(base_vha, 0); 5244 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5245 &heart_beat_counter2); 5246 qla83xx_idc_unlock(base_vha, 0); 5247 } while (heart_beat_counter1 == heart_beat_counter2); 5248 5249 return rval; 5250 } 5251 5252 /* Work: Perform NIC Core Reset handling */ 5253 void 5254 qla83xx_nic_core_reset_work(struct work_struct *work) 5255 { 5256 struct qla_hw_data *ha = 5257 container_of(work, struct qla_hw_data, nic_core_reset); 5258 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5259 uint32_t dev_state = 0; 5260 5261 if (IS_QLA2031(ha)) { 5262 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5263 ql_log(ql_log_warn, base_vha, 0xb081, 5264 "Failed to dump mctp\n"); 5265 return; 5266 } 5267 5268 if (!ha->flags.nic_core_reset_hdlr_active) { 5269 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5270 qla83xx_idc_lock(base_vha, 0); 5271 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5272 &dev_state); 5273 qla83xx_idc_unlock(base_vha, 0); 5274 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5275 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5276 "Nic Core f/w is alive.\n"); 5277 return; 5278 } 5279 } 5280 5281 ha->flags.nic_core_reset_hdlr_active = 1; 5282 if (qla83xx_nic_core_reset(base_vha)) { 5283 /* NIC Core reset failed. */ 5284 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5285 "NIC Core reset failed.\n"); 5286 } 5287 ha->flags.nic_core_reset_hdlr_active = 0; 5288 } 5289 } 5290 5291 /* Work: Handle 8200 IDC aens */ 5292 void 5293 qla83xx_service_idc_aen(struct work_struct *work) 5294 { 5295 struct qla_hw_data *ha = 5296 container_of(work, struct qla_hw_data, idc_aen); 5297 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5298 uint32_t dev_state, idc_control; 5299 5300 qla83xx_idc_lock(base_vha, 0); 5301 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5302 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5303 qla83xx_idc_unlock(base_vha, 0); 5304 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5305 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5306 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5307 "Application requested NIC Core Reset.\n"); 5308 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5309 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5310 QLA_SUCCESS) { 5311 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5312 "Other protocol driver requested NIC Core Reset.\n"); 5313 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5314 } 5315 } else if (dev_state == QLA8XXX_DEV_FAILED || 5316 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5317 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5318 } 5319 } 5320 5321 static void 5322 qla83xx_wait_logic(void) 5323 { 5324 int i; 5325 5326 /* Yield CPU */ 5327 if (!in_interrupt()) { 5328 /* 5329 * Wait about 200ms before retrying again. 5330 * This controls the number of retries for single 5331 * lock operation. 5332 */ 5333 msleep(100); 5334 schedule(); 5335 } else { 5336 for (i = 0; i < 20; i++) 5337 cpu_relax(); /* This a nop instr on i386 */ 5338 } 5339 } 5340 5341 static int 5342 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5343 { 5344 int rval; 5345 uint32_t data; 5346 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5347 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5348 struct qla_hw_data *ha = base_vha->hw; 5349 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5350 "Trying force recovery of the IDC lock.\n"); 5351 5352 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5353 if (rval) 5354 return rval; 5355 5356 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5357 return QLA_SUCCESS; 5358 } else { 5359 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5360 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5361 data); 5362 if (rval) 5363 return rval; 5364 5365 msleep(200); 5366 5367 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5368 &data); 5369 if (rval) 5370 return rval; 5371 5372 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5373 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5374 ~(idc_lck_rcvry_stage_mask)); 5375 rval = qla83xx_wr_reg(base_vha, 5376 QLA83XX_IDC_LOCK_RECOVERY, data); 5377 if (rval) 5378 return rval; 5379 5380 /* Forcefully perform IDC UnLock */ 5381 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5382 &data); 5383 if (rval) 5384 return rval; 5385 /* Clear lock-id by setting 0xff */ 5386 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5387 0xff); 5388 if (rval) 5389 return rval; 5390 /* Clear lock-recovery by setting 0x0 */ 5391 rval = qla83xx_wr_reg(base_vha, 5392 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5393 if (rval) 5394 return rval; 5395 } else 5396 return QLA_SUCCESS; 5397 } 5398 5399 return rval; 5400 } 5401 5402 static int 5403 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5404 { 5405 int rval = QLA_SUCCESS; 5406 uint32_t o_drv_lockid, n_drv_lockid; 5407 unsigned long lock_recovery_timeout; 5408 5409 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5410 retry_lockid: 5411 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5412 if (rval) 5413 goto exit; 5414 5415 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5416 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5417 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5418 return QLA_SUCCESS; 5419 else 5420 return QLA_FUNCTION_FAILED; 5421 } 5422 5423 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5424 if (rval) 5425 goto exit; 5426 5427 if (o_drv_lockid == n_drv_lockid) { 5428 qla83xx_wait_logic(); 5429 goto retry_lockid; 5430 } else 5431 return QLA_SUCCESS; 5432 5433 exit: 5434 return rval; 5435 } 5436 5437 void 5438 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5439 { 5440 uint16_t options = (requester_id << 15) | BIT_6; 5441 uint32_t data; 5442 uint32_t lock_owner; 5443 struct qla_hw_data *ha = base_vha->hw; 5444 5445 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5446 retry_lock: 5447 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5448 == QLA_SUCCESS) { 5449 if (data) { 5450 /* Setting lock-id to our function-number */ 5451 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5452 ha->portnum); 5453 } else { 5454 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5455 &lock_owner); 5456 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5457 "Failed to acquire IDC lock, acquired by %d, " 5458 "retrying...\n", lock_owner); 5459 5460 /* Retry/Perform IDC-Lock recovery */ 5461 if (qla83xx_idc_lock_recovery(base_vha) 5462 == QLA_SUCCESS) { 5463 qla83xx_wait_logic(); 5464 goto retry_lock; 5465 } else 5466 ql_log(ql_log_warn, base_vha, 0xb075, 5467 "IDC Lock recovery FAILED.\n"); 5468 } 5469 5470 } 5471 5472 return; 5473 5474 /* XXX: IDC-lock implementation using access-control mbx */ 5475 retry_lock2: 5476 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5477 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5478 "Failed to acquire IDC lock. retrying...\n"); 5479 /* Retry/Perform IDC-Lock recovery */ 5480 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5481 qla83xx_wait_logic(); 5482 goto retry_lock2; 5483 } else 5484 ql_log(ql_log_warn, base_vha, 0xb076, 5485 "IDC Lock recovery FAILED.\n"); 5486 } 5487 5488 return; 5489 } 5490 5491 void 5492 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5493 { 5494 #if 0 5495 uint16_t options = (requester_id << 15) | BIT_7; 5496 #endif 5497 uint16_t retry; 5498 uint32_t data; 5499 struct qla_hw_data *ha = base_vha->hw; 5500 5501 /* IDC-unlock implementation using driver-unlock/lock-id 5502 * remote registers 5503 */ 5504 retry = 0; 5505 retry_unlock: 5506 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5507 == QLA_SUCCESS) { 5508 if (data == ha->portnum) { 5509 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5510 /* Clearing lock-id by setting 0xff */ 5511 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5512 } else if (retry < 10) { 5513 /* SV: XXX: IDC unlock retrying needed here? */ 5514 5515 /* Retry for IDC-unlock */ 5516 qla83xx_wait_logic(); 5517 retry++; 5518 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5519 "Failed to release IDC lock, retrying=%d\n", retry); 5520 goto retry_unlock; 5521 } 5522 } else if (retry < 10) { 5523 /* Retry for IDC-unlock */ 5524 qla83xx_wait_logic(); 5525 retry++; 5526 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5527 "Failed to read drv-lockid, retrying=%d\n", retry); 5528 goto retry_unlock; 5529 } 5530 5531 return; 5532 5533 #if 0 5534 /* XXX: IDC-unlock implementation using access-control mbx */ 5535 retry = 0; 5536 retry_unlock2: 5537 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5538 if (retry < 10) { 5539 /* Retry for IDC-unlock */ 5540 qla83xx_wait_logic(); 5541 retry++; 5542 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5543 "Failed to release IDC lock, retrying=%d\n", retry); 5544 goto retry_unlock2; 5545 } 5546 } 5547 5548 return; 5549 #endif 5550 } 5551 5552 int 5553 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5554 { 5555 int rval = QLA_SUCCESS; 5556 struct qla_hw_data *ha = vha->hw; 5557 uint32_t drv_presence; 5558 5559 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5560 if (rval == QLA_SUCCESS) { 5561 drv_presence |= (1 << ha->portnum); 5562 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5563 drv_presence); 5564 } 5565 5566 return rval; 5567 } 5568 5569 int 5570 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5571 { 5572 int rval = QLA_SUCCESS; 5573 5574 qla83xx_idc_lock(vha, 0); 5575 rval = __qla83xx_set_drv_presence(vha); 5576 qla83xx_idc_unlock(vha, 0); 5577 5578 return rval; 5579 } 5580 5581 int 5582 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5583 { 5584 int rval = QLA_SUCCESS; 5585 struct qla_hw_data *ha = vha->hw; 5586 uint32_t drv_presence; 5587 5588 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5589 if (rval == QLA_SUCCESS) { 5590 drv_presence &= ~(1 << ha->portnum); 5591 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5592 drv_presence); 5593 } 5594 5595 return rval; 5596 } 5597 5598 int 5599 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5600 { 5601 int rval = QLA_SUCCESS; 5602 5603 qla83xx_idc_lock(vha, 0); 5604 rval = __qla83xx_clear_drv_presence(vha); 5605 qla83xx_idc_unlock(vha, 0); 5606 5607 return rval; 5608 } 5609 5610 static void 5611 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5612 { 5613 struct qla_hw_data *ha = vha->hw; 5614 uint32_t drv_ack, drv_presence; 5615 unsigned long ack_timeout; 5616 5617 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5618 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5619 while (1) { 5620 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5621 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5622 if ((drv_ack & drv_presence) == drv_presence) 5623 break; 5624 5625 if (time_after_eq(jiffies, ack_timeout)) { 5626 ql_log(ql_log_warn, vha, 0xb067, 5627 "RESET ACK TIMEOUT! drv_presence=0x%x " 5628 "drv_ack=0x%x\n", drv_presence, drv_ack); 5629 /* 5630 * The function(s) which did not ack in time are forced 5631 * to withdraw any further participation in the IDC 5632 * reset. 5633 */ 5634 if (drv_ack != drv_presence) 5635 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5636 drv_ack); 5637 break; 5638 } 5639 5640 qla83xx_idc_unlock(vha, 0); 5641 msleep(1000); 5642 qla83xx_idc_lock(vha, 0); 5643 } 5644 5645 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5646 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5647 } 5648 5649 static int 5650 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5651 { 5652 int rval = QLA_SUCCESS; 5653 uint32_t idc_control; 5654 5655 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5656 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5657 5658 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5659 __qla83xx_get_idc_control(vha, &idc_control); 5660 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5661 __qla83xx_set_idc_control(vha, 0); 5662 5663 qla83xx_idc_unlock(vha, 0); 5664 rval = qla83xx_restart_nic_firmware(vha); 5665 qla83xx_idc_lock(vha, 0); 5666 5667 if (rval != QLA_SUCCESS) { 5668 ql_log(ql_log_fatal, vha, 0xb06a, 5669 "Failed to restart NIC f/w.\n"); 5670 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5671 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5672 } else { 5673 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5674 "Success in restarting nic f/w.\n"); 5675 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5676 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5677 } 5678 5679 return rval; 5680 } 5681 5682 /* Assumes idc_lock always held on entry */ 5683 int 5684 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5685 { 5686 struct qla_hw_data *ha = base_vha->hw; 5687 int rval = QLA_SUCCESS; 5688 unsigned long dev_init_timeout; 5689 uint32_t dev_state; 5690 5691 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5692 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5693 5694 while (1) { 5695 5696 if (time_after_eq(jiffies, dev_init_timeout)) { 5697 ql_log(ql_log_warn, base_vha, 0xb06e, 5698 "Initialization TIMEOUT!\n"); 5699 /* Init timeout. Disable further NIC Core 5700 * communication. 5701 */ 5702 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5703 QLA8XXX_DEV_FAILED); 5704 ql_log(ql_log_info, base_vha, 0xb06f, 5705 "HW State: FAILED.\n"); 5706 } 5707 5708 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5709 switch (dev_state) { 5710 case QLA8XXX_DEV_READY: 5711 if (ha->flags.nic_core_reset_owner) 5712 qla83xx_idc_audit(base_vha, 5713 IDC_AUDIT_COMPLETION); 5714 ha->flags.nic_core_reset_owner = 0; 5715 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5716 "Reset_owner reset by 0x%x.\n", 5717 ha->portnum); 5718 goto exit; 5719 case QLA8XXX_DEV_COLD: 5720 if (ha->flags.nic_core_reset_owner) 5721 rval = qla83xx_device_bootstrap(base_vha); 5722 else { 5723 /* Wait for AEN to change device-state */ 5724 qla83xx_idc_unlock(base_vha, 0); 5725 msleep(1000); 5726 qla83xx_idc_lock(base_vha, 0); 5727 } 5728 break; 5729 case QLA8XXX_DEV_INITIALIZING: 5730 /* Wait for AEN to change device-state */ 5731 qla83xx_idc_unlock(base_vha, 0); 5732 msleep(1000); 5733 qla83xx_idc_lock(base_vha, 0); 5734 break; 5735 case QLA8XXX_DEV_NEED_RESET: 5736 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5737 qla83xx_need_reset_handler(base_vha); 5738 else { 5739 /* Wait for AEN to change device-state */ 5740 qla83xx_idc_unlock(base_vha, 0); 5741 msleep(1000); 5742 qla83xx_idc_lock(base_vha, 0); 5743 } 5744 /* reset timeout value after need reset handler */ 5745 dev_init_timeout = jiffies + 5746 (ha->fcoe_dev_init_timeout * HZ); 5747 break; 5748 case QLA8XXX_DEV_NEED_QUIESCENT: 5749 /* XXX: DEBUG for now */ 5750 qla83xx_idc_unlock(base_vha, 0); 5751 msleep(1000); 5752 qla83xx_idc_lock(base_vha, 0); 5753 break; 5754 case QLA8XXX_DEV_QUIESCENT: 5755 /* XXX: DEBUG for now */ 5756 if (ha->flags.quiesce_owner) 5757 goto exit; 5758 5759 qla83xx_idc_unlock(base_vha, 0); 5760 msleep(1000); 5761 qla83xx_idc_lock(base_vha, 0); 5762 dev_init_timeout = jiffies + 5763 (ha->fcoe_dev_init_timeout * HZ); 5764 break; 5765 case QLA8XXX_DEV_FAILED: 5766 if (ha->flags.nic_core_reset_owner) 5767 qla83xx_idc_audit(base_vha, 5768 IDC_AUDIT_COMPLETION); 5769 ha->flags.nic_core_reset_owner = 0; 5770 __qla83xx_clear_drv_presence(base_vha); 5771 qla83xx_idc_unlock(base_vha, 0); 5772 qla8xxx_dev_failed_handler(base_vha); 5773 rval = QLA_FUNCTION_FAILED; 5774 qla83xx_idc_lock(base_vha, 0); 5775 goto exit; 5776 case QLA8XXX_BAD_VALUE: 5777 qla83xx_idc_unlock(base_vha, 0); 5778 msleep(1000); 5779 qla83xx_idc_lock(base_vha, 0); 5780 break; 5781 default: 5782 ql_log(ql_log_warn, base_vha, 0xb071, 5783 "Unknown Device State: %x.\n", dev_state); 5784 qla83xx_idc_unlock(base_vha, 0); 5785 qla8xxx_dev_failed_handler(base_vha); 5786 rval = QLA_FUNCTION_FAILED; 5787 qla83xx_idc_lock(base_vha, 0); 5788 goto exit; 5789 } 5790 } 5791 5792 exit: 5793 return rval; 5794 } 5795 5796 void 5797 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5798 { 5799 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5800 board_disable); 5801 struct pci_dev *pdev = ha->pdev; 5802 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5803 5804 /* 5805 * if UNLOAD flag is already set, then continue unload, 5806 * where it was set first. 5807 */ 5808 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5809 return; 5810 5811 ql_log(ql_log_warn, base_vha, 0x015b, 5812 "Disabling adapter.\n"); 5813 5814 if (!atomic_read(&pdev->enable_cnt)) { 5815 ql_log(ql_log_info, base_vha, 0xfffc, 5816 "PCI device disabled, no action req for PCI error=%lx\n", 5817 base_vha->pci_flags); 5818 return; 5819 } 5820 5821 qla2x00_wait_for_sess_deletion(base_vha); 5822 5823 set_bit(UNLOADING, &base_vha->dpc_flags); 5824 5825 qla2x00_delete_all_vps(ha, base_vha); 5826 5827 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5828 5829 qla2x00_dfs_remove(base_vha); 5830 5831 qla84xx_put_chip(base_vha); 5832 5833 if (base_vha->timer_active) 5834 qla2x00_stop_timer(base_vha); 5835 5836 base_vha->flags.online = 0; 5837 5838 qla2x00_destroy_deferred_work(ha); 5839 5840 /* 5841 * Do not try to stop beacon blink as it will issue a mailbox 5842 * command. 5843 */ 5844 qla2x00_free_sysfs_attr(base_vha, false); 5845 5846 fc_remove_host(base_vha->host); 5847 5848 scsi_remove_host(base_vha->host); 5849 5850 base_vha->flags.init_done = 0; 5851 qla25xx_delete_queues(base_vha); 5852 qla2x00_free_fcports(base_vha); 5853 qla2x00_free_irqs(base_vha); 5854 qla2x00_mem_free(ha); 5855 qla82xx_md_free(base_vha); 5856 qla2x00_free_queues(ha); 5857 5858 qla2x00_unmap_iobases(ha); 5859 5860 pci_release_selected_regions(ha->pdev, ha->bars); 5861 pci_disable_pcie_error_reporting(pdev); 5862 pci_disable_device(pdev); 5863 5864 /* 5865 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5866 */ 5867 } 5868 5869 /************************************************************************** 5870 * qla2x00_do_dpc 5871 * This kernel thread is a task that is schedule by the interrupt handler 5872 * to perform the background processing for interrupts. 5873 * 5874 * Notes: 5875 * This task always run in the context of a kernel thread. It 5876 * is kick-off by the driver's detect code and starts up 5877 * up one per adapter. It immediately goes to sleep and waits for 5878 * some fibre event. When either the interrupt handler or 5879 * the timer routine detects a event it will one of the task 5880 * bits then wake us up. 5881 **************************************************************************/ 5882 static int 5883 qla2x00_do_dpc(void *data) 5884 { 5885 scsi_qla_host_t *base_vha; 5886 struct qla_hw_data *ha; 5887 uint32_t online; 5888 struct qla_qpair *qpair; 5889 5890 ha = (struct qla_hw_data *)data; 5891 base_vha = pci_get_drvdata(ha->pdev); 5892 5893 set_user_nice(current, MIN_NICE); 5894 5895 set_current_state(TASK_INTERRUPTIBLE); 5896 while (!kthread_should_stop()) { 5897 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5898 "DPC handler sleeping.\n"); 5899 5900 schedule(); 5901 5902 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5903 goto end_loop; 5904 5905 if (ha->flags.eeh_busy) { 5906 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5907 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5908 goto end_loop; 5909 } 5910 5911 ha->dpc_active = 1; 5912 5913 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5914 "DPC handler waking up, dpc_flags=0x%lx.\n", 5915 base_vha->dpc_flags); 5916 5917 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5918 break; 5919 5920 if (IS_P3P_TYPE(ha)) { 5921 if (IS_QLA8044(ha)) { 5922 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5923 &base_vha->dpc_flags)) { 5924 qla8044_idc_lock(ha); 5925 qla8044_wr_direct(base_vha, 5926 QLA8044_CRB_DEV_STATE_INDEX, 5927 QLA8XXX_DEV_FAILED); 5928 qla8044_idc_unlock(ha); 5929 ql_log(ql_log_info, base_vha, 0x4004, 5930 "HW State: FAILED.\n"); 5931 qla8044_device_state_handler(base_vha); 5932 continue; 5933 } 5934 5935 } else { 5936 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5937 &base_vha->dpc_flags)) { 5938 qla82xx_idc_lock(ha); 5939 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5940 QLA8XXX_DEV_FAILED); 5941 qla82xx_idc_unlock(ha); 5942 ql_log(ql_log_info, base_vha, 0x0151, 5943 "HW State: FAILED.\n"); 5944 qla82xx_device_state_handler(base_vha); 5945 continue; 5946 } 5947 } 5948 5949 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5950 &base_vha->dpc_flags)) { 5951 5952 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5953 "FCoE context reset scheduled.\n"); 5954 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5955 &base_vha->dpc_flags))) { 5956 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5957 /* FCoE-ctx reset failed. 5958 * Escalate to chip-reset 5959 */ 5960 set_bit(ISP_ABORT_NEEDED, 5961 &base_vha->dpc_flags); 5962 } 5963 clear_bit(ABORT_ISP_ACTIVE, 5964 &base_vha->dpc_flags); 5965 } 5966 5967 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5968 "FCoE context reset end.\n"); 5969 } 5970 } else if (IS_QLAFX00(ha)) { 5971 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5972 &base_vha->dpc_flags)) { 5973 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5974 "Firmware Reset Recovery\n"); 5975 if (qlafx00_reset_initialize(base_vha)) { 5976 /* Failed. Abort isp later. */ 5977 if (!test_bit(UNLOADING, 5978 &base_vha->dpc_flags)) { 5979 set_bit(ISP_UNRECOVERABLE, 5980 &base_vha->dpc_flags); 5981 ql_dbg(ql_dbg_dpc, base_vha, 5982 0x4021, 5983 "Reset Recovery Failed\n"); 5984 } 5985 } 5986 } 5987 5988 if (test_and_clear_bit(FX00_TARGET_SCAN, 5989 &base_vha->dpc_flags)) { 5990 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5991 "ISPFx00 Target Scan scheduled\n"); 5992 if (qlafx00_rescan_isp(base_vha)) { 5993 if (!test_bit(UNLOADING, 5994 &base_vha->dpc_flags)) 5995 set_bit(ISP_UNRECOVERABLE, 5996 &base_vha->dpc_flags); 5997 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5998 "ISPFx00 Target Scan Failed\n"); 5999 } 6000 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6001 "ISPFx00 Target Scan End\n"); 6002 } 6003 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6004 &base_vha->dpc_flags)) { 6005 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6006 "ISPFx00 Host Info resend scheduled\n"); 6007 qlafx00_fx_disc(base_vha, 6008 &base_vha->hw->mr.fcport, 6009 FXDISC_REG_HOST_INFO); 6010 } 6011 } 6012 6013 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6014 &base_vha->dpc_flags) && 6015 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6016 qla24xx_detect_sfp(base_vha); 6017 6018 if (ha->flags.detected_lr_sfp != 6019 ha->flags.using_lr_setting) 6020 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6021 } 6022 6023 if (test_and_clear_bit 6024 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6025 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6026 6027 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6028 "ISP abort scheduled.\n"); 6029 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6030 &base_vha->dpc_flags))) { 6031 6032 if (ha->isp_ops->abort_isp(base_vha)) { 6033 /* failed. retry later */ 6034 set_bit(ISP_ABORT_NEEDED, 6035 &base_vha->dpc_flags); 6036 } 6037 clear_bit(ABORT_ISP_ACTIVE, 6038 &base_vha->dpc_flags); 6039 } 6040 6041 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6042 "ISP abort end.\n"); 6043 } 6044 6045 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6046 &base_vha->dpc_flags)) { 6047 qla2x00_update_fcports(base_vha); 6048 } 6049 6050 if (IS_QLAFX00(ha)) 6051 goto loop_resync_check; 6052 6053 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6054 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6055 "Quiescence mode scheduled.\n"); 6056 if (IS_P3P_TYPE(ha)) { 6057 if (IS_QLA82XX(ha)) 6058 qla82xx_device_state_handler(base_vha); 6059 if (IS_QLA8044(ha)) 6060 qla8044_device_state_handler(base_vha); 6061 clear_bit(ISP_QUIESCE_NEEDED, 6062 &base_vha->dpc_flags); 6063 if (!ha->flags.quiesce_owner) { 6064 qla2x00_perform_loop_resync(base_vha); 6065 if (IS_QLA82XX(ha)) { 6066 qla82xx_idc_lock(ha); 6067 qla82xx_clear_qsnt_ready( 6068 base_vha); 6069 qla82xx_idc_unlock(ha); 6070 } else if (IS_QLA8044(ha)) { 6071 qla8044_idc_lock(ha); 6072 qla8044_clear_qsnt_ready( 6073 base_vha); 6074 qla8044_idc_unlock(ha); 6075 } 6076 } 6077 } else { 6078 clear_bit(ISP_QUIESCE_NEEDED, 6079 &base_vha->dpc_flags); 6080 qla2x00_quiesce_io(base_vha); 6081 } 6082 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6083 "Quiescence mode end.\n"); 6084 } 6085 6086 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6087 &base_vha->dpc_flags) && 6088 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6089 6090 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6091 "Reset marker scheduled.\n"); 6092 qla2x00_rst_aen(base_vha); 6093 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6094 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6095 "Reset marker end.\n"); 6096 } 6097 6098 /* Retry each device up to login retry count */ 6099 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6100 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6101 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6102 6103 if (!base_vha->relogin_jif || 6104 time_after_eq(jiffies, base_vha->relogin_jif)) { 6105 base_vha->relogin_jif = jiffies + HZ; 6106 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6107 6108 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6109 "Relogin scheduled.\n"); 6110 qla24xx_post_relogin_work(base_vha); 6111 } 6112 } 6113 loop_resync_check: 6114 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6115 &base_vha->dpc_flags)) { 6116 6117 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6118 "Loop resync scheduled.\n"); 6119 6120 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6121 &base_vha->dpc_flags))) { 6122 6123 qla2x00_loop_resync(base_vha); 6124 6125 clear_bit(LOOP_RESYNC_ACTIVE, 6126 &base_vha->dpc_flags); 6127 } 6128 6129 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6130 "Loop resync end.\n"); 6131 } 6132 6133 if (IS_QLAFX00(ha)) 6134 goto intr_on_check; 6135 6136 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6137 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6138 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6139 qla2xxx_flash_npiv_conf(base_vha); 6140 } 6141 6142 intr_on_check: 6143 if (!ha->interrupts_on) 6144 ha->isp_ops->enable_intrs(ha); 6145 6146 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6147 &base_vha->dpc_flags)) { 6148 if (ha->beacon_blink_led == 1) 6149 ha->isp_ops->beacon_blink(base_vha); 6150 } 6151 6152 /* qpair online check */ 6153 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6154 &base_vha->dpc_flags)) { 6155 if (ha->flags.eeh_busy || 6156 ha->flags.pci_channel_io_perm_failure) 6157 online = 0; 6158 else 6159 online = 1; 6160 6161 mutex_lock(&ha->mq_lock); 6162 list_for_each_entry(qpair, &base_vha->qp_list, 6163 qp_list_elem) 6164 qpair->online = online; 6165 mutex_unlock(&ha->mq_lock); 6166 } 6167 6168 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6169 ql_log(ql_log_info, base_vha, 0xffffff, 6170 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6171 ha->nvme_last_rptd_aen); 6172 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6173 ql_log(ql_log_info, base_vha, 0xffffff, 6174 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6175 ha->nvme_last_rptd_aen); 6176 } 6177 } 6178 6179 if (!IS_QLAFX00(ha)) 6180 qla2x00_do_dpc_all_vps(base_vha); 6181 6182 ha->dpc_active = 0; 6183 end_loop: 6184 set_current_state(TASK_INTERRUPTIBLE); 6185 } /* End of while(1) */ 6186 __set_current_state(TASK_RUNNING); 6187 6188 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6189 "DPC handler exiting.\n"); 6190 6191 /* 6192 * Make sure that nobody tries to wake us up again. 6193 */ 6194 ha->dpc_active = 0; 6195 6196 /* Cleanup any residual CTX SRBs. */ 6197 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6198 6199 return 0; 6200 } 6201 6202 void 6203 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6204 { 6205 struct qla_hw_data *ha = vha->hw; 6206 struct task_struct *t = ha->dpc_thread; 6207 6208 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6209 wake_up_process(t); 6210 } 6211 6212 /* 6213 * qla2x00_rst_aen 6214 * Processes asynchronous reset. 6215 * 6216 * Input: 6217 * ha = adapter block pointer. 6218 */ 6219 static void 6220 qla2x00_rst_aen(scsi_qla_host_t *vha) 6221 { 6222 if (vha->flags.online && !vha->flags.reset_active && 6223 !atomic_read(&vha->loop_down_timer) && 6224 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6225 do { 6226 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6227 6228 /* 6229 * Issue marker command only when we are going to start 6230 * the I/O. 6231 */ 6232 vha->marker_needed = 1; 6233 } while (!atomic_read(&vha->loop_down_timer) && 6234 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6235 } 6236 } 6237 6238 /************************************************************************** 6239 * qla2x00_timer 6240 * 6241 * Description: 6242 * One second timer 6243 * 6244 * Context: Interrupt 6245 ***************************************************************************/ 6246 void 6247 qla2x00_timer(struct timer_list *t) 6248 { 6249 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6250 unsigned long cpu_flags = 0; 6251 int start_dpc = 0; 6252 int index; 6253 srb_t *sp; 6254 uint16_t w; 6255 struct qla_hw_data *ha = vha->hw; 6256 struct req_que *req; 6257 6258 if (ha->flags.eeh_busy) { 6259 ql_dbg(ql_dbg_timer, vha, 0x6000, 6260 "EEH = %d, restarting timer.\n", 6261 ha->flags.eeh_busy); 6262 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6263 return; 6264 } 6265 6266 /* 6267 * Hardware read to raise pending EEH errors during mailbox waits. If 6268 * the read returns -1 then disable the board. 6269 */ 6270 if (!pci_channel_offline(ha->pdev)) { 6271 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6272 qla2x00_check_reg16_for_disconnect(vha, w); 6273 } 6274 6275 /* Make sure qla82xx_watchdog is run only for physical port */ 6276 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6277 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6278 start_dpc++; 6279 if (IS_QLA82XX(ha)) 6280 qla82xx_watchdog(vha); 6281 else if (IS_QLA8044(ha)) 6282 qla8044_watchdog(vha); 6283 } 6284 6285 if (!vha->vp_idx && IS_QLAFX00(ha)) 6286 qlafx00_timer_routine(vha); 6287 6288 /* Loop down handler. */ 6289 if (atomic_read(&vha->loop_down_timer) > 0 && 6290 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6291 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6292 && vha->flags.online) { 6293 6294 if (atomic_read(&vha->loop_down_timer) == 6295 vha->loop_down_abort_time) { 6296 6297 ql_log(ql_log_info, vha, 0x6008, 6298 "Loop down - aborting the queues before time expires.\n"); 6299 6300 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6301 atomic_set(&vha->loop_state, LOOP_DEAD); 6302 6303 /* 6304 * Schedule an ISP abort to return any FCP2-device 6305 * commands. 6306 */ 6307 /* NPIV - scan physical port only */ 6308 if (!vha->vp_idx) { 6309 spin_lock_irqsave(&ha->hardware_lock, 6310 cpu_flags); 6311 req = ha->req_q_map[0]; 6312 for (index = 1; 6313 index < req->num_outstanding_cmds; 6314 index++) { 6315 fc_port_t *sfcp; 6316 6317 sp = req->outstanding_cmds[index]; 6318 if (!sp) 6319 continue; 6320 if (sp->cmd_type != TYPE_SRB) 6321 continue; 6322 if (sp->type != SRB_SCSI_CMD) 6323 continue; 6324 sfcp = sp->fcport; 6325 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6326 continue; 6327 6328 if (IS_QLA82XX(ha)) 6329 set_bit(FCOE_CTX_RESET_NEEDED, 6330 &vha->dpc_flags); 6331 else 6332 set_bit(ISP_ABORT_NEEDED, 6333 &vha->dpc_flags); 6334 break; 6335 } 6336 spin_unlock_irqrestore(&ha->hardware_lock, 6337 cpu_flags); 6338 } 6339 start_dpc++; 6340 } 6341 6342 /* if the loop has been down for 4 minutes, reinit adapter */ 6343 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6344 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6345 ql_log(ql_log_warn, vha, 0x6009, 6346 "Loop down - aborting ISP.\n"); 6347 6348 if (IS_QLA82XX(ha)) 6349 set_bit(FCOE_CTX_RESET_NEEDED, 6350 &vha->dpc_flags); 6351 else 6352 set_bit(ISP_ABORT_NEEDED, 6353 &vha->dpc_flags); 6354 } 6355 } 6356 ql_dbg(ql_dbg_timer, vha, 0x600a, 6357 "Loop down - seconds remaining %d.\n", 6358 atomic_read(&vha->loop_down_timer)); 6359 } 6360 /* Check if beacon LED needs to be blinked for physical host only */ 6361 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6362 /* There is no beacon_blink function for ISP82xx */ 6363 if (!IS_P3P_TYPE(ha)) { 6364 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6365 start_dpc++; 6366 } 6367 } 6368 6369 /* Process any deferred work. */ 6370 if (!list_empty(&vha->work_list)) { 6371 unsigned long flags; 6372 bool q = false; 6373 6374 spin_lock_irqsave(&vha->work_lock, flags); 6375 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6376 q = true; 6377 spin_unlock_irqrestore(&vha->work_lock, flags); 6378 if (q) 6379 queue_work(vha->hw->wq, &vha->iocb_work); 6380 } 6381 6382 /* 6383 * FC-NVME 6384 * see if the active AEN count has changed from what was last reported. 6385 */ 6386 if (!vha->vp_idx && 6387 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6388 ha->zio_mode == QLA_ZIO_MODE_6) { 6389 ql_log(ql_log_info, vha, 0x3002, 6390 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6391 ha->nvme_last_rptd_aen); 6392 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6393 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6394 start_dpc++; 6395 } 6396 6397 /* Schedule the DPC routine if needed */ 6398 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6399 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6400 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6401 start_dpc || 6402 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6403 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6404 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6405 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6406 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6407 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6408 ql_dbg(ql_dbg_timer, vha, 0x600b, 6409 "isp_abort_needed=%d loop_resync_needed=%d " 6410 "fcport_update_needed=%d start_dpc=%d " 6411 "reset_marker_needed=%d", 6412 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6413 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6414 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6415 start_dpc, 6416 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6417 ql_dbg(ql_dbg_timer, vha, 0x600c, 6418 "beacon_blink_needed=%d isp_unrecoverable=%d " 6419 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6420 "relogin_needed=%d.\n", 6421 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6422 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6423 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6424 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6425 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6426 qla2xxx_wake_dpc(vha); 6427 } 6428 6429 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6430 } 6431 6432 /* Firmware interface routines. */ 6433 6434 #define FW_BLOBS 11 6435 #define FW_ISP21XX 0 6436 #define FW_ISP22XX 1 6437 #define FW_ISP2300 2 6438 #define FW_ISP2322 3 6439 #define FW_ISP24XX 4 6440 #define FW_ISP25XX 5 6441 #define FW_ISP81XX 6 6442 #define FW_ISP82XX 7 6443 #define FW_ISP2031 8 6444 #define FW_ISP8031 9 6445 #define FW_ISP27XX 10 6446 6447 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6448 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6449 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6450 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6451 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6452 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6453 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6454 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6455 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6456 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6457 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6458 6459 6460 static DEFINE_MUTEX(qla_fw_lock); 6461 6462 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6463 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6464 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6465 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6466 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6467 { .name = FW_FILE_ISP24XX, }, 6468 { .name = FW_FILE_ISP25XX, }, 6469 { .name = FW_FILE_ISP81XX, }, 6470 { .name = FW_FILE_ISP82XX, }, 6471 { .name = FW_FILE_ISP2031, }, 6472 { .name = FW_FILE_ISP8031, }, 6473 { .name = FW_FILE_ISP27XX, }, 6474 }; 6475 6476 struct fw_blob * 6477 qla2x00_request_firmware(scsi_qla_host_t *vha) 6478 { 6479 struct qla_hw_data *ha = vha->hw; 6480 struct fw_blob *blob; 6481 6482 if (IS_QLA2100(ha)) { 6483 blob = &qla_fw_blobs[FW_ISP21XX]; 6484 } else if (IS_QLA2200(ha)) { 6485 blob = &qla_fw_blobs[FW_ISP22XX]; 6486 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6487 blob = &qla_fw_blobs[FW_ISP2300]; 6488 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6489 blob = &qla_fw_blobs[FW_ISP2322]; 6490 } else if (IS_QLA24XX_TYPE(ha)) { 6491 blob = &qla_fw_blobs[FW_ISP24XX]; 6492 } else if (IS_QLA25XX(ha)) { 6493 blob = &qla_fw_blobs[FW_ISP25XX]; 6494 } else if (IS_QLA81XX(ha)) { 6495 blob = &qla_fw_blobs[FW_ISP81XX]; 6496 } else if (IS_QLA82XX(ha)) { 6497 blob = &qla_fw_blobs[FW_ISP82XX]; 6498 } else if (IS_QLA2031(ha)) { 6499 blob = &qla_fw_blobs[FW_ISP2031]; 6500 } else if (IS_QLA8031(ha)) { 6501 blob = &qla_fw_blobs[FW_ISP8031]; 6502 } else if (IS_QLA27XX(ha)) { 6503 blob = &qla_fw_blobs[FW_ISP27XX]; 6504 } else { 6505 return NULL; 6506 } 6507 6508 mutex_lock(&qla_fw_lock); 6509 if (blob->fw) 6510 goto out; 6511 6512 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6513 ql_log(ql_log_warn, vha, 0x0063, 6514 "Failed to load firmware image (%s).\n", blob->name); 6515 blob->fw = NULL; 6516 blob = NULL; 6517 goto out; 6518 } 6519 6520 out: 6521 mutex_unlock(&qla_fw_lock); 6522 return blob; 6523 } 6524 6525 static void 6526 qla2x00_release_firmware(void) 6527 { 6528 int idx; 6529 6530 mutex_lock(&qla_fw_lock); 6531 for (idx = 0; idx < FW_BLOBS; idx++) 6532 release_firmware(qla_fw_blobs[idx].fw); 6533 mutex_unlock(&qla_fw_lock); 6534 } 6535 6536 static pci_ers_result_t 6537 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6538 { 6539 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6540 struct qla_hw_data *ha = vha->hw; 6541 6542 ql_dbg(ql_dbg_aer, vha, 0x9000, 6543 "PCI error detected, state %x.\n", state); 6544 6545 if (!atomic_read(&pdev->enable_cnt)) { 6546 ql_log(ql_log_info, vha, 0xffff, 6547 "PCI device is disabled,state %x\n", state); 6548 return PCI_ERS_RESULT_NEED_RESET; 6549 } 6550 6551 switch (state) { 6552 case pci_channel_io_normal: 6553 ha->flags.eeh_busy = 0; 6554 if (ql2xmqsupport || ql2xnvmeenable) { 6555 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6556 qla2xxx_wake_dpc(vha); 6557 } 6558 return PCI_ERS_RESULT_CAN_RECOVER; 6559 case pci_channel_io_frozen: 6560 ha->flags.eeh_busy = 1; 6561 /* For ISP82XX complete any pending mailbox cmd */ 6562 if (IS_QLA82XX(ha)) { 6563 ha->flags.isp82xx_fw_hung = 1; 6564 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6565 qla82xx_clear_pending_mbx(vha); 6566 } 6567 qla2x00_free_irqs(vha); 6568 pci_disable_device(pdev); 6569 /* Return back all IOs */ 6570 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6571 if (ql2xmqsupport || ql2xnvmeenable) { 6572 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6573 qla2xxx_wake_dpc(vha); 6574 } 6575 return PCI_ERS_RESULT_NEED_RESET; 6576 case pci_channel_io_perm_failure: 6577 ha->flags.pci_channel_io_perm_failure = 1; 6578 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6579 if (ql2xmqsupport || ql2xnvmeenable) { 6580 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6581 qla2xxx_wake_dpc(vha); 6582 } 6583 return PCI_ERS_RESULT_DISCONNECT; 6584 } 6585 return PCI_ERS_RESULT_NEED_RESET; 6586 } 6587 6588 static pci_ers_result_t 6589 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6590 { 6591 int risc_paused = 0; 6592 uint32_t stat; 6593 unsigned long flags; 6594 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6595 struct qla_hw_data *ha = base_vha->hw; 6596 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6597 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6598 6599 if (IS_QLA82XX(ha)) 6600 return PCI_ERS_RESULT_RECOVERED; 6601 6602 spin_lock_irqsave(&ha->hardware_lock, flags); 6603 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6604 stat = RD_REG_DWORD(®->hccr); 6605 if (stat & HCCR_RISC_PAUSE) 6606 risc_paused = 1; 6607 } else if (IS_QLA23XX(ha)) { 6608 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6609 if (stat & HSR_RISC_PAUSED) 6610 risc_paused = 1; 6611 } else if (IS_FWI2_CAPABLE(ha)) { 6612 stat = RD_REG_DWORD(®24->host_status); 6613 if (stat & HSRX_RISC_PAUSED) 6614 risc_paused = 1; 6615 } 6616 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6617 6618 if (risc_paused) { 6619 ql_log(ql_log_info, base_vha, 0x9003, 6620 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6621 ha->isp_ops->fw_dump(base_vha, 0); 6622 6623 return PCI_ERS_RESULT_NEED_RESET; 6624 } else 6625 return PCI_ERS_RESULT_RECOVERED; 6626 } 6627 6628 static uint32_t 6629 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6630 { 6631 uint32_t rval = QLA_FUNCTION_FAILED; 6632 uint32_t drv_active = 0; 6633 struct qla_hw_data *ha = base_vha->hw; 6634 int fn; 6635 struct pci_dev *other_pdev = NULL; 6636 6637 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6638 "Entered %s.\n", __func__); 6639 6640 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6641 6642 if (base_vha->flags.online) { 6643 /* Abort all outstanding commands, 6644 * so as to be requeued later */ 6645 qla2x00_abort_isp_cleanup(base_vha); 6646 } 6647 6648 6649 fn = PCI_FUNC(ha->pdev->devfn); 6650 while (fn > 0) { 6651 fn--; 6652 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6653 "Finding pci device at function = 0x%x.\n", fn); 6654 other_pdev = 6655 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6656 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6657 fn)); 6658 6659 if (!other_pdev) 6660 continue; 6661 if (atomic_read(&other_pdev->enable_cnt)) { 6662 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6663 "Found PCI func available and enable at 0x%x.\n", 6664 fn); 6665 pci_dev_put(other_pdev); 6666 break; 6667 } 6668 pci_dev_put(other_pdev); 6669 } 6670 6671 if (!fn) { 6672 /* Reset owner */ 6673 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6674 "This devfn is reset owner = 0x%x.\n", 6675 ha->pdev->devfn); 6676 qla82xx_idc_lock(ha); 6677 6678 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6679 QLA8XXX_DEV_INITIALIZING); 6680 6681 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6682 QLA82XX_IDC_VERSION); 6683 6684 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6685 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6686 "drv_active = 0x%x.\n", drv_active); 6687 6688 qla82xx_idc_unlock(ha); 6689 /* Reset if device is not already reset 6690 * drv_active would be 0 if a reset has already been done 6691 */ 6692 if (drv_active) 6693 rval = qla82xx_start_firmware(base_vha); 6694 else 6695 rval = QLA_SUCCESS; 6696 qla82xx_idc_lock(ha); 6697 6698 if (rval != QLA_SUCCESS) { 6699 ql_log(ql_log_info, base_vha, 0x900b, 6700 "HW State: FAILED.\n"); 6701 qla82xx_clear_drv_active(ha); 6702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6703 QLA8XXX_DEV_FAILED); 6704 } else { 6705 ql_log(ql_log_info, base_vha, 0x900c, 6706 "HW State: READY.\n"); 6707 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6708 QLA8XXX_DEV_READY); 6709 qla82xx_idc_unlock(ha); 6710 ha->flags.isp82xx_fw_hung = 0; 6711 rval = qla82xx_restart_isp(base_vha); 6712 qla82xx_idc_lock(ha); 6713 /* Clear driver state register */ 6714 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6715 qla82xx_set_drv_active(base_vha); 6716 } 6717 qla82xx_idc_unlock(ha); 6718 } else { 6719 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6720 "This devfn is not reset owner = 0x%x.\n", 6721 ha->pdev->devfn); 6722 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6723 QLA8XXX_DEV_READY)) { 6724 ha->flags.isp82xx_fw_hung = 0; 6725 rval = qla82xx_restart_isp(base_vha); 6726 qla82xx_idc_lock(ha); 6727 qla82xx_set_drv_active(base_vha); 6728 qla82xx_idc_unlock(ha); 6729 } 6730 } 6731 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6732 6733 return rval; 6734 } 6735 6736 static pci_ers_result_t 6737 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6738 { 6739 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6740 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6741 struct qla_hw_data *ha = base_vha->hw; 6742 struct rsp_que *rsp; 6743 int rc, retries = 10; 6744 6745 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6746 "Slot Reset.\n"); 6747 6748 /* Workaround: qla2xxx driver which access hardware earlier 6749 * needs error state to be pci_channel_io_online. 6750 * Otherwise mailbox command timesout. 6751 */ 6752 pdev->error_state = pci_channel_io_normal; 6753 6754 pci_restore_state(pdev); 6755 6756 /* pci_restore_state() clears the saved_state flag of the device 6757 * save restored state which resets saved_state flag 6758 */ 6759 pci_save_state(pdev); 6760 6761 if (ha->mem_only) 6762 rc = pci_enable_device_mem(pdev); 6763 else 6764 rc = pci_enable_device(pdev); 6765 6766 if (rc) { 6767 ql_log(ql_log_warn, base_vha, 0x9005, 6768 "Can't re-enable PCI device after reset.\n"); 6769 goto exit_slot_reset; 6770 } 6771 6772 rsp = ha->rsp_q_map[0]; 6773 if (qla2x00_request_irqs(ha, rsp)) 6774 goto exit_slot_reset; 6775 6776 if (ha->isp_ops->pci_config(base_vha)) 6777 goto exit_slot_reset; 6778 6779 if (IS_QLA82XX(ha)) { 6780 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6781 ret = PCI_ERS_RESULT_RECOVERED; 6782 goto exit_slot_reset; 6783 } else 6784 goto exit_slot_reset; 6785 } 6786 6787 while (ha->flags.mbox_busy && retries--) 6788 msleep(1000); 6789 6790 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6791 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6792 ret = PCI_ERS_RESULT_RECOVERED; 6793 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6794 6795 6796 exit_slot_reset: 6797 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6798 "slot_reset return %x.\n", ret); 6799 6800 return ret; 6801 } 6802 6803 static void 6804 qla2xxx_pci_resume(struct pci_dev *pdev) 6805 { 6806 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6807 struct qla_hw_data *ha = base_vha->hw; 6808 int ret; 6809 6810 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6811 "pci_resume.\n"); 6812 6813 ret = qla2x00_wait_for_hba_online(base_vha); 6814 if (ret != QLA_SUCCESS) { 6815 ql_log(ql_log_fatal, base_vha, 0x9002, 6816 "The device failed to resume I/O from slot/link_reset.\n"); 6817 } 6818 6819 pci_cleanup_aer_uncorrect_error_status(pdev); 6820 6821 ha->flags.eeh_busy = 0; 6822 } 6823 6824 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6825 { 6826 int rc; 6827 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6828 6829 if (USER_CTRL_IRQ(vha->hw)) 6830 rc = blk_mq_map_queues(&shost->tag_set); 6831 else 6832 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); 6833 return rc; 6834 } 6835 6836 static const struct pci_error_handlers qla2xxx_err_handler = { 6837 .error_detected = qla2xxx_pci_error_detected, 6838 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6839 .slot_reset = qla2xxx_pci_slot_reset, 6840 .resume = qla2xxx_pci_resume, 6841 }; 6842 6843 static struct pci_device_id qla2xxx_pci_tbl[] = { 6844 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6845 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6846 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6847 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6848 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6849 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6850 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6866 { 0 }, 6867 }; 6868 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6869 6870 static struct pci_driver qla2xxx_pci_driver = { 6871 .name = QLA2XXX_DRIVER_NAME, 6872 .driver = { 6873 .owner = THIS_MODULE, 6874 }, 6875 .id_table = qla2xxx_pci_tbl, 6876 .probe = qla2x00_probe_one, 6877 .remove = qla2x00_remove_one, 6878 .shutdown = qla2x00_shutdown, 6879 .err_handler = &qla2xxx_err_handler, 6880 }; 6881 6882 static const struct file_operations apidev_fops = { 6883 .owner = THIS_MODULE, 6884 .llseek = noop_llseek, 6885 }; 6886 6887 /** 6888 * qla2x00_module_init - Module initialization. 6889 **/ 6890 static int __init 6891 qla2x00_module_init(void) 6892 { 6893 int ret = 0; 6894 6895 /* Allocate cache for SRBs. */ 6896 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6897 SLAB_HWCACHE_ALIGN, NULL); 6898 if (srb_cachep == NULL) { 6899 ql_log(ql_log_fatal, NULL, 0x0001, 6900 "Unable to allocate SRB cache...Failing load!.\n"); 6901 return -ENOMEM; 6902 } 6903 6904 /* Initialize target kmem_cache and mem_pools */ 6905 ret = qlt_init(); 6906 if (ret < 0) { 6907 kmem_cache_destroy(srb_cachep); 6908 return ret; 6909 } else if (ret > 0) { 6910 /* 6911 * If initiator mode is explictly disabled by qlt_init(), 6912 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6913 * performing scsi_scan_target() during LOOP UP event. 6914 */ 6915 qla2xxx_transport_functions.disable_target_scan = 1; 6916 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6917 } 6918 6919 /* Derive version string. */ 6920 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6921 if (ql2xextended_error_logging) 6922 strcat(qla2x00_version_str, "-debug"); 6923 if (ql2xextended_error_logging == 1) 6924 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6925 6926 qla2xxx_transport_template = 6927 fc_attach_transport(&qla2xxx_transport_functions); 6928 if (!qla2xxx_transport_template) { 6929 kmem_cache_destroy(srb_cachep); 6930 ql_log(ql_log_fatal, NULL, 0x0002, 6931 "fc_attach_transport failed...Failing load!.\n"); 6932 qlt_exit(); 6933 return -ENODEV; 6934 } 6935 6936 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6937 if (apidev_major < 0) { 6938 ql_log(ql_log_fatal, NULL, 0x0003, 6939 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6940 } 6941 6942 qla2xxx_transport_vport_template = 6943 fc_attach_transport(&qla2xxx_transport_vport_functions); 6944 if (!qla2xxx_transport_vport_template) { 6945 kmem_cache_destroy(srb_cachep); 6946 qlt_exit(); 6947 fc_release_transport(qla2xxx_transport_template); 6948 ql_log(ql_log_fatal, NULL, 0x0004, 6949 "fc_attach_transport vport failed...Failing load!.\n"); 6950 return -ENODEV; 6951 } 6952 ql_log(ql_log_info, NULL, 0x0005, 6953 "QLogic Fibre Channel HBA Driver: %s.\n", 6954 qla2x00_version_str); 6955 ret = pci_register_driver(&qla2xxx_pci_driver); 6956 if (ret) { 6957 kmem_cache_destroy(srb_cachep); 6958 qlt_exit(); 6959 fc_release_transport(qla2xxx_transport_template); 6960 fc_release_transport(qla2xxx_transport_vport_template); 6961 ql_log(ql_log_fatal, NULL, 0x0006, 6962 "pci_register_driver failed...ret=%d Failing load!.\n", 6963 ret); 6964 } 6965 return ret; 6966 } 6967 6968 /** 6969 * qla2x00_module_exit - Module cleanup. 6970 **/ 6971 static void __exit 6972 qla2x00_module_exit(void) 6973 { 6974 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6975 pci_unregister_driver(&qla2xxx_pci_driver); 6976 qla2x00_release_firmware(); 6977 kmem_cache_destroy(srb_cachep); 6978 qlt_exit(); 6979 if (ctx_cachep) 6980 kmem_cache_destroy(ctx_cachep); 6981 fc_release_transport(qla2xxx_transport_template); 6982 fc_release_transport(qla2xxx_transport_vport_template); 6983 } 6984 6985 module_init(qla2x00_module_init); 6986 module_exit(qla2x00_module_exit); 6987 6988 MODULE_AUTHOR("QLogic Corporation"); 6989 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6990 MODULE_LICENSE("GPL"); 6991 MODULE_VERSION(QLA2XXX_VERSION); 6992 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6993 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6994 MODULE_FIRMWARE(FW_FILE_ISP2300); 6995 MODULE_FIRMWARE(FW_FILE_ISP2322); 6996 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6997 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6998