1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 /* 23 * Driver version 24 */ 25 char qla2x00_version_str[40]; 26 27 static int apidev_major; 28 29 /* 30 * SRB allocation cache 31 */ 32 static struct kmem_cache *srb_cachep; 33 34 /* 35 * CT6 CTX allocation cache 36 */ 37 static struct kmem_cache *ctx_cachep; 38 /* 39 * error level for logging 40 */ 41 int ql_errlev = ql_log_all; 42 43 int ql2xlogintimeout = 20; 44 module_param(ql2xlogintimeout, int, S_IRUGO); 45 MODULE_PARM_DESC(ql2xlogintimeout, 46 "Login timeout value in seconds."); 47 48 int qlport_down_retry; 49 module_param(qlport_down_retry, int, S_IRUGO); 50 MODULE_PARM_DESC(qlport_down_retry, 51 "Maximum number of command retries to a port that returns " 52 "a PORT-DOWN status."); 53 54 int ql2xplogiabsentdevice; 55 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 56 MODULE_PARM_DESC(ql2xplogiabsentdevice, 57 "Option to enable PLOGI to devices that are not present after " 58 "a Fabric scan. This is needed for several broken switches. " 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 60 61 int ql2xloginretrycount = 0; 62 module_param(ql2xloginretrycount, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xloginretrycount, 64 "Specify an alternate value for the NVRAM login retry count."); 65 66 int ql2xallocfwdump = 1; 67 module_param(ql2xallocfwdump, int, S_IRUGO); 68 MODULE_PARM_DESC(ql2xallocfwdump, 69 "Option to enable allocation of memory for a firmware dump " 70 "during HBA initialization. Memory allocation requirements " 71 "vary by ISP type. Default is 1 - allocate memory."); 72 73 int ql2xextended_error_logging; 74 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 75 MODULE_PARM_DESC(ql2xextended_error_logging, 76 "Option to enable extended error logging,\n" 77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 86 "\t\t0x1e400000 - Preferred value for capturing essential " 87 "debug information (equivalent to old " 88 "ql2xextended_error_logging=1).\n" 89 "\t\tDo LOGICAL OR of the value to enable more than one level"); 90 91 int ql2xshiftctondsd = 6; 92 module_param(ql2xshiftctondsd, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xshiftctondsd, 94 "Set to control shifting of command type processing " 95 "based on total number of SG elements."); 96 97 static void qla2x00_free_device(scsi_qla_host_t *); 98 99 int ql2xfdmienable=1; 100 module_param(ql2xfdmienable, int, S_IRUGO); 101 MODULE_PARM_DESC(ql2xfdmienable, 102 "Enables FDMI registrations. " 103 "0 - no FDMI. Default is 1 - perform FDMI."); 104 105 #define MAX_Q_DEPTH 32 106 static int ql2xmaxqdepth = MAX_Q_DEPTH; 107 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 108 MODULE_PARM_DESC(ql2xmaxqdepth, 109 "Maximum queue depth to report for target devices."); 110 111 /* Do not change the value of this after module load */ 112 int ql2xenabledif = 0; 113 module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xenabledif, 115 " Enable T10-CRC-DIF " 116 " Default is 0 - No DIF Support. 1 - Enable it" 117 ", 2 - Enable DIF for all types, except Type 0."); 118 119 int ql2xenablehba_err_chk = 2; 120 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xenablehba_err_chk, 122 " Enable T10-CRC-DIF Error isolation by HBA:\n" 123 " Default is 1.\n" 124 " 0 -- Error isolation disabled\n" 125 " 1 -- Error isolation enabled only for DIX Type 0\n" 126 " 2 -- Error isolation enabled for all Types\n"); 127 128 int ql2xiidmaenable=1; 129 module_param(ql2xiidmaenable, int, S_IRUGO); 130 MODULE_PARM_DESC(ql2xiidmaenable, 131 "Enables iIDMA settings " 132 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 133 134 int ql2xmaxqueues = 1; 135 module_param(ql2xmaxqueues, int, S_IRUGO); 136 MODULE_PARM_DESC(ql2xmaxqueues, 137 "Enables MQ settings " 138 "Default is 1 for single queue. Set it to number " 139 "of queues in MQ mode."); 140 141 int ql2xmultique_tag; 142 module_param(ql2xmultique_tag, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xmultique_tag, 144 "Enables CPU affinity settings for the driver " 145 "Default is 0 for no affinity of request and response IO. " 146 "Set it to 1 to turn on the cpu affinity."); 147 148 int ql2xfwloadbin; 149 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xfwloadbin, 151 "Option to specify location from which to load ISP firmware:.\n" 152 " 2 -- load firmware via the request_firmware() (hotplug).\n" 153 " interface.\n" 154 " 1 -- load firmware from flash.\n" 155 " 0 -- use default semantics.\n"); 156 157 int ql2xetsenable; 158 module_param(ql2xetsenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xetsenable, 160 "Enables firmware ETS burst." 161 "Default is 0 - skip ETS enablement."); 162 163 int ql2xdbwr = 1; 164 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 165 MODULE_PARM_DESC(ql2xdbwr, 166 "Option to specify scheme for request queue posting.\n" 167 " 0 -- Regular doorbell.\n" 168 " 1 -- CAMRAM doorbell (faster).\n"); 169 170 int ql2xtargetreset = 1; 171 module_param(ql2xtargetreset, int, S_IRUGO); 172 MODULE_PARM_DESC(ql2xtargetreset, 173 "Enable target reset." 174 "Default is 1 - use hw defaults."); 175 176 int ql2xgffidenable; 177 module_param(ql2xgffidenable, int, S_IRUGO); 178 MODULE_PARM_DESC(ql2xgffidenable, 179 "Enables GFF_ID checks of port type. " 180 "Default is 0 - Do not use GFF_ID information."); 181 182 int ql2xasynctmfenable; 183 module_param(ql2xasynctmfenable, int, S_IRUGO); 184 MODULE_PARM_DESC(ql2xasynctmfenable, 185 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 186 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 187 188 int ql2xdontresethba; 189 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 190 MODULE_PARM_DESC(ql2xdontresethba, 191 "Option to specify reset behaviour.\n" 192 " 0 (Default) -- Reset on failure.\n" 193 " 1 -- Do not reset on failure.\n"); 194 195 uint ql2xmaxlun = MAX_LUNS; 196 module_param(ql2xmaxlun, uint, S_IRUGO); 197 MODULE_PARM_DESC(ql2xmaxlun, 198 "Defines the maximum LU number to register with the SCSI " 199 "midlayer. Default is 65535."); 200 201 int ql2xmdcapmask = 0x1F; 202 module_param(ql2xmdcapmask, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xmdcapmask, 204 "Set the Minidump driver capture mask level. " 205 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 206 207 int ql2xmdenable = 1; 208 module_param(ql2xmdenable, int, S_IRUGO); 209 MODULE_PARM_DESC(ql2xmdenable, 210 "Enable/disable MiniDump. " 211 "0 - MiniDump disabled. " 212 "1 (Default) - MiniDump enabled."); 213 214 /* 215 * SCSI host template entry points 216 */ 217 static int qla2xxx_slave_configure(struct scsi_device * device); 218 static int qla2xxx_slave_alloc(struct scsi_device *); 219 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 220 static void qla2xxx_scan_start(struct Scsi_Host *); 221 static void qla2xxx_slave_destroy(struct scsi_device *); 222 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 223 static int qla2xxx_eh_abort(struct scsi_cmnd *); 224 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 225 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 226 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 227 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 228 229 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 230 static int qla2x00_change_queue_type(struct scsi_device *, int); 231 232 struct scsi_host_template qla2xxx_driver_template = { 233 .module = THIS_MODULE, 234 .name = QLA2XXX_DRIVER_NAME, 235 .queuecommand = qla2xxx_queuecommand, 236 237 .eh_abort_handler = qla2xxx_eh_abort, 238 .eh_device_reset_handler = qla2xxx_eh_device_reset, 239 .eh_target_reset_handler = qla2xxx_eh_target_reset, 240 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 241 .eh_host_reset_handler = qla2xxx_eh_host_reset, 242 243 .slave_configure = qla2xxx_slave_configure, 244 245 .slave_alloc = qla2xxx_slave_alloc, 246 .slave_destroy = qla2xxx_slave_destroy, 247 .scan_finished = qla2xxx_scan_finished, 248 .scan_start = qla2xxx_scan_start, 249 .change_queue_depth = qla2x00_change_queue_depth, 250 .change_queue_type = qla2x00_change_queue_type, 251 .this_id = -1, 252 .cmd_per_lun = 3, 253 .use_clustering = ENABLE_CLUSTERING, 254 .sg_tablesize = SG_ALL, 255 256 .max_sectors = 0xFFFF, 257 .shost_attrs = qla2x00_host_attrs, 258 }; 259 260 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 261 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 262 263 /* TODO Convert to inlines 264 * 265 * Timer routines 266 */ 267 268 __inline__ void 269 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 270 { 271 init_timer(&vha->timer); 272 vha->timer.expires = jiffies + interval * HZ; 273 vha->timer.data = (unsigned long)vha; 274 vha->timer.function = (void (*)(unsigned long))func; 275 add_timer(&vha->timer); 276 vha->timer_active = 1; 277 } 278 279 static inline void 280 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 281 { 282 /* Currently used for 82XX only. */ 283 if (vha->device_flags & DFLG_DEV_FAILED) { 284 ql_dbg(ql_dbg_timer, vha, 0x600d, 285 "Device in a failed state, returning.\n"); 286 return; 287 } 288 289 mod_timer(&vha->timer, jiffies + interval * HZ); 290 } 291 292 static __inline__ void 293 qla2x00_stop_timer(scsi_qla_host_t *vha) 294 { 295 del_timer_sync(&vha->timer); 296 vha->timer_active = 0; 297 } 298 299 static int qla2x00_do_dpc(void *data); 300 301 static void qla2x00_rst_aen(scsi_qla_host_t *); 302 303 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 304 struct req_que **, struct rsp_que **); 305 static void qla2x00_free_fw_dump(struct qla_hw_data *); 306 static void qla2x00_mem_free(struct qla_hw_data *); 307 static void qla2x00_sp_free_dma(srb_t *); 308 309 /* -------------------------------------------------------------------------- */ 310 static int qla2x00_alloc_queues(struct qla_hw_data *ha) 311 { 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 313 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 314 GFP_KERNEL); 315 if (!ha->req_q_map) { 316 ql_log(ql_log_fatal, vha, 0x003b, 317 "Unable to allocate memory for request queue ptrs.\n"); 318 goto fail_req_map; 319 } 320 321 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 322 GFP_KERNEL); 323 if (!ha->rsp_q_map) { 324 ql_log(ql_log_fatal, vha, 0x003c, 325 "Unable to allocate memory for response queue ptrs.\n"); 326 goto fail_rsp_map; 327 } 328 set_bit(0, ha->rsp_qid_map); 329 set_bit(0, ha->req_qid_map); 330 return 1; 331 332 fail_rsp_map: 333 kfree(ha->req_q_map); 334 ha->req_q_map = NULL; 335 fail_req_map: 336 return -ENOMEM; 337 } 338 339 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 340 { 341 if (req && req->ring) 342 dma_free_coherent(&ha->pdev->dev, 343 (req->length + 1) * sizeof(request_t), 344 req->ring, req->dma); 345 346 kfree(req); 347 req = NULL; 348 } 349 350 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 351 { 352 if (rsp && rsp->ring) 353 dma_free_coherent(&ha->pdev->dev, 354 (rsp->length + 1) * sizeof(response_t), 355 rsp->ring, rsp->dma); 356 357 kfree(rsp); 358 rsp = NULL; 359 } 360 361 static void qla2x00_free_queues(struct qla_hw_data *ha) 362 { 363 struct req_que *req; 364 struct rsp_que *rsp; 365 int cnt; 366 367 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 368 req = ha->req_q_map[cnt]; 369 qla2x00_free_req_que(ha, req); 370 } 371 kfree(ha->req_q_map); 372 ha->req_q_map = NULL; 373 374 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 375 rsp = ha->rsp_q_map[cnt]; 376 qla2x00_free_rsp_que(ha, rsp); 377 } 378 kfree(ha->rsp_q_map); 379 ha->rsp_q_map = NULL; 380 } 381 382 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 383 { 384 uint16_t options = 0; 385 int ques, req, ret; 386 struct qla_hw_data *ha = vha->hw; 387 388 if (!(ha->fw_attributes & BIT_6)) { 389 ql_log(ql_log_warn, vha, 0x00d8, 390 "Firmware is not multi-queue capable.\n"); 391 goto fail; 392 } 393 if (ql2xmultique_tag) { 394 /* create a request queue for IO */ 395 options |= BIT_7; 396 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 397 QLA_DEFAULT_QUE_QOS); 398 if (!req) { 399 ql_log(ql_log_warn, vha, 0x00e0, 400 "Failed to create request queue.\n"); 401 goto fail; 402 } 403 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 404 vha->req = ha->req_q_map[req]; 405 options |= BIT_1; 406 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 407 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 408 if (!ret) { 409 ql_log(ql_log_warn, vha, 0x00e8, 410 "Failed to create response queue.\n"); 411 goto fail2; 412 } 413 } 414 ha->flags.cpu_affinity_enabled = 1; 415 ql_dbg(ql_dbg_multiq, vha, 0xc007, 416 "CPU affinity mode enalbed, " 417 "no. of response queues:%d no. of request queues:%d.\n", 418 ha->max_rsp_queues, ha->max_req_queues); 419 ql_dbg(ql_dbg_init, vha, 0x00e9, 420 "CPU affinity mode enalbed, " 421 "no. of response queues:%d no. of request queues:%d.\n", 422 ha->max_rsp_queues, ha->max_req_queues); 423 } 424 return 0; 425 fail2: 426 qla25xx_delete_queues(vha); 427 destroy_workqueue(ha->wq); 428 ha->wq = NULL; 429 vha->req = ha->req_q_map[0]; 430 fail: 431 ha->mqenable = 0; 432 kfree(ha->req_q_map); 433 kfree(ha->rsp_q_map); 434 ha->max_req_queues = ha->max_rsp_queues = 1; 435 return 1; 436 } 437 438 static char * 439 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 440 { 441 struct qla_hw_data *ha = vha->hw; 442 static char *pci_bus_modes[] = { 443 "33", "66", "100", "133", 444 }; 445 uint16_t pci_bus; 446 447 strcpy(str, "PCI"); 448 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 449 if (pci_bus) { 450 strcat(str, "-X ("); 451 strcat(str, pci_bus_modes[pci_bus]); 452 } else { 453 pci_bus = (ha->pci_attr & BIT_8) >> 8; 454 strcat(str, " ("); 455 strcat(str, pci_bus_modes[pci_bus]); 456 } 457 strcat(str, " MHz)"); 458 459 return (str); 460 } 461 462 static char * 463 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 464 { 465 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 466 struct qla_hw_data *ha = vha->hw; 467 uint32_t pci_bus; 468 int pcie_reg; 469 470 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 471 if (pcie_reg) { 472 char lwstr[6]; 473 uint16_t pcie_lstat, lspeed, lwidth; 474 475 pcie_reg += 0x12; 476 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); 477 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); 478 lwidth = (pcie_lstat & 479 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; 480 481 strcpy(str, "PCIe ("); 482 if (lspeed == 1) 483 strcat(str, "2.5GT/s "); 484 else if (lspeed == 2) 485 strcat(str, "5.0GT/s "); 486 else 487 strcat(str, "<unknown> "); 488 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 489 strcat(str, lwstr); 490 491 return str; 492 } 493 494 strcpy(str, "PCI"); 495 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 496 if (pci_bus == 0 || pci_bus == 8) { 497 strcat(str, " ("); 498 strcat(str, pci_bus_modes[pci_bus >> 3]); 499 } else { 500 strcat(str, "-X "); 501 if (pci_bus & BIT_2) 502 strcat(str, "Mode 2"); 503 else 504 strcat(str, "Mode 1"); 505 strcat(str, " ("); 506 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 507 } 508 strcat(str, " MHz)"); 509 510 return str; 511 } 512 513 static char * 514 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 515 { 516 char un_str[10]; 517 struct qla_hw_data *ha = vha->hw; 518 519 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 520 ha->fw_minor_version, 521 ha->fw_subminor_version); 522 523 if (ha->fw_attributes & BIT_9) { 524 strcat(str, "FLX"); 525 return (str); 526 } 527 528 switch (ha->fw_attributes & 0xFF) { 529 case 0x7: 530 strcat(str, "EF"); 531 break; 532 case 0x17: 533 strcat(str, "TP"); 534 break; 535 case 0x37: 536 strcat(str, "IP"); 537 break; 538 case 0x77: 539 strcat(str, "VI"); 540 break; 541 default: 542 sprintf(un_str, "(%x)", ha->fw_attributes); 543 strcat(str, un_str); 544 break; 545 } 546 if (ha->fw_attributes & 0x100) 547 strcat(str, "X"); 548 549 return (str); 550 } 551 552 static char * 553 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 554 { 555 struct qla_hw_data *ha = vha->hw; 556 557 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 558 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 559 return str; 560 } 561 562 static inline srb_t * 563 qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport, 564 struct scsi_cmnd *cmd) 565 { 566 srb_t *sp; 567 struct qla_hw_data *ha = vha->hw; 568 569 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC); 570 if (!sp) { 571 ql_log(ql_log_warn, vha, 0x3006, 572 "Memory allocation failed for sp.\n"); 573 return sp; 574 } 575 576 atomic_set(&sp->ref_count, 1); 577 sp->fcport = fcport; 578 sp->cmd = cmd; 579 sp->flags = 0; 580 CMD_SP(cmd) = (void *)sp; 581 sp->ctx = NULL; 582 583 return sp; 584 } 585 586 static int 587 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 588 { 589 scsi_qla_host_t *vha = shost_priv(host); 590 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 591 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 592 struct qla_hw_data *ha = vha->hw; 593 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 594 srb_t *sp; 595 int rval; 596 597 if (ha->flags.eeh_busy) { 598 if (ha->flags.pci_channel_io_perm_failure) { 599 ql_dbg(ql_dbg_io, vha, 0x3001, 600 "PCI Channel IO permanent failure, exiting " 601 "cmd=%p.\n", cmd); 602 cmd->result = DID_NO_CONNECT << 16; 603 } else { 604 ql_dbg(ql_dbg_io, vha, 0x3002, 605 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 606 cmd->result = DID_REQUEUE << 16; 607 } 608 goto qc24_fail_command; 609 } 610 611 rval = fc_remote_port_chkready(rport); 612 if (rval) { 613 cmd->result = rval; 614 ql_dbg(ql_dbg_io, vha, 0x3003, 615 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 616 cmd, rval); 617 goto qc24_fail_command; 618 } 619 620 if (!vha->flags.difdix_supported && 621 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 622 ql_dbg(ql_dbg_io, vha, 0x3004, 623 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 624 cmd); 625 cmd->result = DID_NO_CONNECT << 16; 626 goto qc24_fail_command; 627 } 628 if (atomic_read(&fcport->state) != FCS_ONLINE) { 629 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 630 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 631 ql_dbg(ql_dbg_io, vha, 0x3005, 632 "Returning DNC, fcport_state=%d loop_state=%d.\n", 633 atomic_read(&fcport->state), 634 atomic_read(&base_vha->loop_state)); 635 cmd->result = DID_NO_CONNECT << 16; 636 goto qc24_fail_command; 637 } 638 goto qc24_target_busy; 639 } 640 641 sp = qla2x00_get_new_sp(base_vha, fcport, cmd); 642 if (!sp) 643 goto qc24_host_busy; 644 645 rval = ha->isp_ops->start_scsi(sp); 646 if (rval != QLA_SUCCESS) { 647 ql_dbg(ql_dbg_io, vha, 0x3013, 648 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 649 goto qc24_host_busy_free_sp; 650 } 651 652 return 0; 653 654 qc24_host_busy_free_sp: 655 qla2x00_sp_free_dma(sp); 656 mempool_free(sp, ha->srb_mempool); 657 658 qc24_host_busy: 659 return SCSI_MLQUEUE_HOST_BUSY; 660 661 qc24_target_busy: 662 return SCSI_MLQUEUE_TARGET_BUSY; 663 664 qc24_fail_command: 665 cmd->scsi_done(cmd); 666 667 return 0; 668 } 669 670 /* 671 * qla2x00_eh_wait_on_command 672 * Waits for the command to be returned by the Firmware for some 673 * max time. 674 * 675 * Input: 676 * cmd = Scsi Command to wait on. 677 * 678 * Return: 679 * Not Found : 0 680 * Found : 1 681 */ 682 static int 683 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 684 { 685 #define ABORT_POLLING_PERIOD 1000 686 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 687 unsigned long wait_iter = ABORT_WAIT_ITER; 688 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 689 struct qla_hw_data *ha = vha->hw; 690 int ret = QLA_SUCCESS; 691 692 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 693 ql_dbg(ql_dbg_taskm, vha, 0x8005, 694 "Return:eh_wait.\n"); 695 return ret; 696 } 697 698 while (CMD_SP(cmd) && wait_iter--) { 699 msleep(ABORT_POLLING_PERIOD); 700 } 701 if (CMD_SP(cmd)) 702 ret = QLA_FUNCTION_FAILED; 703 704 return ret; 705 } 706 707 /* 708 * qla2x00_wait_for_hba_online 709 * Wait till the HBA is online after going through 710 * <= MAX_RETRIES_OF_ISP_ABORT or 711 * finally HBA is disabled ie marked offline 712 * 713 * Input: 714 * ha - pointer to host adapter structure 715 * 716 * Note: 717 * Does context switching-Release SPIN_LOCK 718 * (if any) before calling this routine. 719 * 720 * Return: 721 * Success (Adapter is online) : 0 722 * Failed (Adapter is offline/disabled) : 1 723 */ 724 int 725 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 726 { 727 int return_status; 728 unsigned long wait_online; 729 struct qla_hw_data *ha = vha->hw; 730 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 731 732 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 733 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 734 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 735 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 736 ha->dpc_active) && time_before(jiffies, wait_online)) { 737 738 msleep(1000); 739 } 740 if (base_vha->flags.online) 741 return_status = QLA_SUCCESS; 742 else 743 return_status = QLA_FUNCTION_FAILED; 744 745 return (return_status); 746 } 747 748 /* 749 * qla2x00_wait_for_reset_ready 750 * Wait till the HBA is online after going through 751 * <= MAX_RETRIES_OF_ISP_ABORT or 752 * finally HBA is disabled ie marked offline or flash 753 * operations are in progress. 754 * 755 * Input: 756 * ha - pointer to host adapter structure 757 * 758 * Note: 759 * Does context switching-Release SPIN_LOCK 760 * (if any) before calling this routine. 761 * 762 * Return: 763 * Success (Adapter is online/no flash ops) : 0 764 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 765 */ 766 static int 767 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 768 { 769 int return_status; 770 unsigned long wait_online; 771 struct qla_hw_data *ha = vha->hw; 772 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 773 774 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 775 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 776 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 777 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 778 ha->optrom_state != QLA_SWAITING || 779 ha->dpc_active) && time_before(jiffies, wait_online)) 780 msleep(1000); 781 782 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 783 return_status = QLA_SUCCESS; 784 else 785 return_status = QLA_FUNCTION_FAILED; 786 787 ql_dbg(ql_dbg_taskm, vha, 0x8019, 788 "%s return status=%d.\n", __func__, return_status); 789 790 return return_status; 791 } 792 793 int 794 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 795 { 796 int return_status; 797 unsigned long wait_reset; 798 struct qla_hw_data *ha = vha->hw; 799 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 800 801 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 802 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 803 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 804 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 805 ha->dpc_active) && time_before(jiffies, wait_reset)) { 806 807 msleep(1000); 808 809 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 810 ha->flags.chip_reset_done) 811 break; 812 } 813 if (ha->flags.chip_reset_done) 814 return_status = QLA_SUCCESS; 815 else 816 return_status = QLA_FUNCTION_FAILED; 817 818 return return_status; 819 } 820 821 static void 822 sp_get(struct srb *sp) 823 { 824 atomic_inc(&sp->ref_count); 825 } 826 827 /************************************************************************** 828 * qla2xxx_eh_abort 829 * 830 * Description: 831 * The abort function will abort the specified command. 832 * 833 * Input: 834 * cmd = Linux SCSI command packet to be aborted. 835 * 836 * Returns: 837 * Either SUCCESS or FAILED. 838 * 839 * Note: 840 * Only return FAILED if command not returned by firmware. 841 **************************************************************************/ 842 static int 843 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 844 { 845 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 846 srb_t *sp; 847 int ret; 848 unsigned int id, lun; 849 unsigned long flags; 850 int wait = 0; 851 struct qla_hw_data *ha = vha->hw; 852 853 if (!CMD_SP(cmd)) 854 return SUCCESS; 855 856 ret = fc_block_scsi_eh(cmd); 857 if (ret != 0) 858 return ret; 859 ret = SUCCESS; 860 861 id = cmd->device->id; 862 lun = cmd->device->lun; 863 864 spin_lock_irqsave(&ha->hardware_lock, flags); 865 sp = (srb_t *) CMD_SP(cmd); 866 if (!sp) { 867 spin_unlock_irqrestore(&ha->hardware_lock, flags); 868 return SUCCESS; 869 } 870 871 ql_dbg(ql_dbg_taskm, vha, 0x8002, 872 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", 873 vha->host_no, id, lun, sp, cmd); 874 875 /* Get a reference to the sp and drop the lock.*/ 876 sp_get(sp); 877 878 spin_unlock_irqrestore(&ha->hardware_lock, flags); 879 if (ha->isp_ops->abort_command(sp)) { 880 ql_dbg(ql_dbg_taskm, vha, 0x8003, 881 "Abort command mbx failed cmd=%p.\n", cmd); 882 } else { 883 ql_dbg(ql_dbg_taskm, vha, 0x8004, 884 "Abort command mbx success cmd=%p.\n", cmd); 885 wait = 1; 886 } 887 888 spin_lock_irqsave(&ha->hardware_lock, flags); 889 qla2x00_sp_compl(ha, sp); 890 spin_unlock_irqrestore(&ha->hardware_lock, flags); 891 892 /* Did the command return during mailbox execution? */ 893 if (ret == FAILED && !CMD_SP(cmd)) 894 ret = SUCCESS; 895 896 /* Wait for the command to be returned. */ 897 if (wait) { 898 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 899 ql_log(ql_log_warn, vha, 0x8006, 900 "Abort handler timed out cmd=%p.\n", cmd); 901 ret = FAILED; 902 } 903 } 904 905 ql_log(ql_log_info, vha, 0x801c, 906 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", 907 vha->host_no, id, lun, wait, ret); 908 909 return ret; 910 } 911 912 int 913 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 914 unsigned int l, enum nexus_wait_type type) 915 { 916 int cnt, match, status; 917 unsigned long flags; 918 struct qla_hw_data *ha = vha->hw; 919 struct req_que *req; 920 srb_t *sp; 921 922 status = QLA_SUCCESS; 923 924 spin_lock_irqsave(&ha->hardware_lock, flags); 925 req = vha->req; 926 for (cnt = 1; status == QLA_SUCCESS && 927 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 928 sp = req->outstanding_cmds[cnt]; 929 if (!sp) 930 continue; 931 if ((sp->ctx) && !IS_PROT_IO(sp)) 932 continue; 933 if (vha->vp_idx != sp->fcport->vha->vp_idx) 934 continue; 935 match = 0; 936 switch (type) { 937 case WAIT_HOST: 938 match = 1; 939 break; 940 case WAIT_TARGET: 941 match = sp->cmd->device->id == t; 942 break; 943 case WAIT_LUN: 944 match = (sp->cmd->device->id == t && 945 sp->cmd->device->lun == l); 946 break; 947 } 948 if (!match) 949 continue; 950 951 spin_unlock_irqrestore(&ha->hardware_lock, flags); 952 status = qla2x00_eh_wait_on_command(sp->cmd); 953 spin_lock_irqsave(&ha->hardware_lock, flags); 954 } 955 spin_unlock_irqrestore(&ha->hardware_lock, flags); 956 957 return status; 958 } 959 960 static char *reset_errors[] = { 961 "HBA not online", 962 "HBA not ready", 963 "Task management failed", 964 "Waiting for command completions", 965 }; 966 967 static int 968 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 969 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 970 { 971 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 972 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 973 int err; 974 975 if (!fcport) { 976 return FAILED; 977 } 978 979 err = fc_block_scsi_eh(cmd); 980 if (err != 0) 981 return err; 982 983 ql_log(ql_log_info, vha, 0x8009, 984 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, 985 cmd->device->id, cmd->device->lun, cmd); 986 987 err = 0; 988 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 989 ql_log(ql_log_warn, vha, 0x800a, 990 "Wait for hba online failed for cmd=%p.\n", cmd); 991 goto eh_reset_failed; 992 } 993 err = 2; 994 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 995 != QLA_SUCCESS) { 996 ql_log(ql_log_warn, vha, 0x800c, 997 "do_reset failed for cmd=%p.\n", cmd); 998 goto eh_reset_failed; 999 } 1000 err = 3; 1001 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1002 cmd->device->lun, type) != QLA_SUCCESS) { 1003 ql_log(ql_log_warn, vha, 0x800d, 1004 "wait for peding cmds failed for cmd=%p.\n", cmd); 1005 goto eh_reset_failed; 1006 } 1007 1008 ql_log(ql_log_info, vha, 0x800e, 1009 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, 1010 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1011 1012 return SUCCESS; 1013 1014 eh_reset_failed: 1015 ql_log(ql_log_info, vha, 0x800f, 1016 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, 1017 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1018 cmd); 1019 return FAILED; 1020 } 1021 1022 static int 1023 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1024 { 1025 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1026 struct qla_hw_data *ha = vha->hw; 1027 1028 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1029 ha->isp_ops->lun_reset); 1030 } 1031 1032 static int 1033 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1034 { 1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1036 struct qla_hw_data *ha = vha->hw; 1037 1038 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1039 ha->isp_ops->target_reset); 1040 } 1041 1042 /************************************************************************** 1043 * qla2xxx_eh_bus_reset 1044 * 1045 * Description: 1046 * The bus reset function will reset the bus and abort any executing 1047 * commands. 1048 * 1049 * Input: 1050 * cmd = Linux SCSI command packet of the command that cause the 1051 * bus reset. 1052 * 1053 * Returns: 1054 * SUCCESS/FAILURE (defined as macro in scsi.h). 1055 * 1056 **************************************************************************/ 1057 static int 1058 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1059 { 1060 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1061 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1062 int ret = FAILED; 1063 unsigned int id, lun; 1064 1065 id = cmd->device->id; 1066 lun = cmd->device->lun; 1067 1068 if (!fcport) { 1069 return ret; 1070 } 1071 1072 ret = fc_block_scsi_eh(cmd); 1073 if (ret != 0) 1074 return ret; 1075 ret = FAILED; 1076 1077 ql_log(ql_log_info, vha, 0x8012, 1078 "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun); 1079 1080 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1081 ql_log(ql_log_fatal, vha, 0x8013, 1082 "Wait for hba online failed board disabled.\n"); 1083 goto eh_bus_reset_done; 1084 } 1085 1086 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1087 ret = SUCCESS; 1088 1089 if (ret == FAILED) 1090 goto eh_bus_reset_done; 1091 1092 /* Flush outstanding commands. */ 1093 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1094 QLA_SUCCESS) { 1095 ql_log(ql_log_warn, vha, 0x8014, 1096 "Wait for pending commands failed.\n"); 1097 ret = FAILED; 1098 } 1099 1100 eh_bus_reset_done: 1101 ql_log(ql_log_warn, vha, 0x802b, 1102 "BUS RESET %s nexus=%ld:%d:%d.\n", 1103 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun); 1104 1105 return ret; 1106 } 1107 1108 /************************************************************************** 1109 * qla2xxx_eh_host_reset 1110 * 1111 * Description: 1112 * The reset function will reset the Adapter. 1113 * 1114 * Input: 1115 * cmd = Linux SCSI command packet of the command that cause the 1116 * adapter reset. 1117 * 1118 * Returns: 1119 * Either SUCCESS or FAILED. 1120 * 1121 * Note: 1122 **************************************************************************/ 1123 static int 1124 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1125 { 1126 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1127 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1128 struct qla_hw_data *ha = vha->hw; 1129 int ret = FAILED; 1130 unsigned int id, lun; 1131 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1132 1133 id = cmd->device->id; 1134 lun = cmd->device->lun; 1135 1136 if (!fcport) { 1137 return ret; 1138 } 1139 1140 ret = fc_block_scsi_eh(cmd); 1141 if (ret != 0) 1142 return ret; 1143 ret = FAILED; 1144 1145 ql_log(ql_log_info, vha, 0x8018, 1146 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1147 1148 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1149 goto eh_host_reset_lock; 1150 1151 if (vha != base_vha) { 1152 if (qla2x00_vp_abort_isp(vha)) 1153 goto eh_host_reset_lock; 1154 } else { 1155 if (IS_QLA82XX(vha->hw)) { 1156 if (!qla82xx_fcoe_ctx_reset(vha)) { 1157 /* Ctx reset success */ 1158 ret = SUCCESS; 1159 goto eh_host_reset_lock; 1160 } 1161 /* fall thru if ctx reset failed */ 1162 } 1163 if (ha->wq) 1164 flush_workqueue(ha->wq); 1165 1166 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1167 if (ha->isp_ops->abort_isp(base_vha)) { 1168 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1169 /* failed. schedule dpc to try */ 1170 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1171 1172 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1173 ql_log(ql_log_warn, vha, 0x802a, 1174 "wait for hba online failed.\n"); 1175 goto eh_host_reset_lock; 1176 } 1177 } 1178 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1179 } 1180 1181 /* Waiting for command to be returned to OS.*/ 1182 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1183 QLA_SUCCESS) 1184 ret = SUCCESS; 1185 1186 eh_host_reset_lock: 1187 ql_log(ql_log_info, vha, 0x8017, 1188 "ADAPTER RESET %s nexus=%ld:%d:%d.\n", 1189 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1190 1191 return ret; 1192 } 1193 1194 /* 1195 * qla2x00_loop_reset 1196 * Issue loop reset. 1197 * 1198 * Input: 1199 * ha = adapter block pointer. 1200 * 1201 * Returns: 1202 * 0 = success 1203 */ 1204 int 1205 qla2x00_loop_reset(scsi_qla_host_t *vha) 1206 { 1207 int ret; 1208 struct fc_port *fcport; 1209 struct qla_hw_data *ha = vha->hw; 1210 1211 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1212 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1213 if (fcport->port_type != FCT_TARGET) 1214 continue; 1215 1216 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1217 if (ret != QLA_SUCCESS) { 1218 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1219 "Bus Reset failed: Target Reset=%d " 1220 "d_id=%x.\n", ret, fcport->d_id.b24); 1221 } 1222 } 1223 } 1224 1225 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) { 1226 ret = qla2x00_full_login_lip(vha); 1227 if (ret != QLA_SUCCESS) { 1228 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1229 "full_login_lip=%d.\n", ret); 1230 } 1231 atomic_set(&vha->loop_state, LOOP_DOWN); 1232 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1233 qla2x00_mark_all_devices_lost(vha, 0); 1234 } 1235 1236 if (ha->flags.enable_lip_reset) { 1237 ret = qla2x00_lip_reset(vha); 1238 if (ret != QLA_SUCCESS) 1239 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1240 "lip_reset failed (%d).\n", ret); 1241 } 1242 1243 /* Issue marker command only when we are going to start the I/O */ 1244 vha->marker_needed = 1; 1245 1246 return QLA_SUCCESS; 1247 } 1248 1249 void 1250 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1251 { 1252 int que, cnt; 1253 unsigned long flags; 1254 srb_t *sp; 1255 struct srb_ctx *ctx; 1256 struct qla_hw_data *ha = vha->hw; 1257 struct req_que *req; 1258 1259 spin_lock_irqsave(&ha->hardware_lock, flags); 1260 for (que = 0; que < ha->max_req_queues; que++) { 1261 req = ha->req_q_map[que]; 1262 if (!req) 1263 continue; 1264 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 1265 sp = req->outstanding_cmds[cnt]; 1266 if (sp) { 1267 req->outstanding_cmds[cnt] = NULL; 1268 if (!sp->ctx || 1269 (sp->flags & SRB_FCP_CMND_DMA_VALID) || 1270 IS_PROT_IO(sp)) { 1271 sp->cmd->result = res; 1272 qla2x00_sp_compl(ha, sp); 1273 } else { 1274 ctx = sp->ctx; 1275 if (ctx->type == SRB_ELS_CMD_RPT || 1276 ctx->type == SRB_ELS_CMD_HST || 1277 ctx->type == SRB_CT_CMD) { 1278 struct fc_bsg_job *bsg_job = 1279 ctx->u.bsg_job; 1280 if (bsg_job->request->msgcode 1281 == FC_BSG_HST_CT) 1282 kfree(sp->fcport); 1283 bsg_job->req->errors = 0; 1284 bsg_job->reply->result = res; 1285 bsg_job->job_done(bsg_job); 1286 kfree(sp->ctx); 1287 mempool_free(sp, 1288 ha->srb_mempool); 1289 } else { 1290 ctx->u.iocb_cmd->free(sp); 1291 } 1292 } 1293 } 1294 } 1295 } 1296 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1297 } 1298 1299 static int 1300 qla2xxx_slave_alloc(struct scsi_device *sdev) 1301 { 1302 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1303 1304 if (!rport || fc_remote_port_chkready(rport)) 1305 return -ENXIO; 1306 1307 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1308 1309 return 0; 1310 } 1311 1312 static int 1313 qla2xxx_slave_configure(struct scsi_device *sdev) 1314 { 1315 scsi_qla_host_t *vha = shost_priv(sdev->host); 1316 struct req_que *req = vha->req; 1317 1318 if (sdev->tagged_supported) 1319 scsi_activate_tcq(sdev, req->max_q_depth); 1320 else 1321 scsi_deactivate_tcq(sdev, req->max_q_depth); 1322 return 0; 1323 } 1324 1325 static void 1326 qla2xxx_slave_destroy(struct scsi_device *sdev) 1327 { 1328 sdev->hostdata = NULL; 1329 } 1330 1331 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1332 { 1333 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1334 1335 if (!scsi_track_queue_full(sdev, qdepth)) 1336 return; 1337 1338 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1339 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", 1340 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1341 } 1342 1343 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1344 { 1345 fc_port_t *fcport = sdev->hostdata; 1346 struct scsi_qla_host *vha = fcport->vha; 1347 struct req_que *req = NULL; 1348 1349 req = vha->req; 1350 if (!req) 1351 return; 1352 1353 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1354 return; 1355 1356 if (sdev->ordered_tags) 1357 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1358 else 1359 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1360 1361 ql_dbg(ql_dbg_io, vha, 0x302a, 1362 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", 1363 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1364 } 1365 1366 static int 1367 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1368 { 1369 switch (reason) { 1370 case SCSI_QDEPTH_DEFAULT: 1371 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1372 break; 1373 case SCSI_QDEPTH_QFULL: 1374 qla2x00_handle_queue_full(sdev, qdepth); 1375 break; 1376 case SCSI_QDEPTH_RAMP_UP: 1377 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1378 break; 1379 default: 1380 return -EOPNOTSUPP; 1381 } 1382 1383 return sdev->queue_depth; 1384 } 1385 1386 static int 1387 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1388 { 1389 if (sdev->tagged_supported) { 1390 scsi_set_tag_type(sdev, tag_type); 1391 if (tag_type) 1392 scsi_activate_tcq(sdev, sdev->queue_depth); 1393 else 1394 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1395 } else 1396 tag_type = 0; 1397 1398 return tag_type; 1399 } 1400 1401 /** 1402 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1403 * @ha: HA context 1404 * 1405 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1406 * supported addressing method. 1407 */ 1408 static void 1409 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1410 { 1411 /* Assume a 32bit DMA mask. */ 1412 ha->flags.enable_64bit_addressing = 0; 1413 1414 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1415 /* Any upper-dword bits set? */ 1416 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1417 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1418 /* Ok, a 64bit DMA mask is applicable. */ 1419 ha->flags.enable_64bit_addressing = 1; 1420 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1421 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1422 return; 1423 } 1424 } 1425 1426 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1427 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1428 } 1429 1430 static void 1431 qla2x00_enable_intrs(struct qla_hw_data *ha) 1432 { 1433 unsigned long flags = 0; 1434 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1435 1436 spin_lock_irqsave(&ha->hardware_lock, flags); 1437 ha->interrupts_on = 1; 1438 /* enable risc and host interrupts */ 1439 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1440 RD_REG_WORD(®->ictrl); 1441 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1442 1443 } 1444 1445 static void 1446 qla2x00_disable_intrs(struct qla_hw_data *ha) 1447 { 1448 unsigned long flags = 0; 1449 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1450 1451 spin_lock_irqsave(&ha->hardware_lock, flags); 1452 ha->interrupts_on = 0; 1453 /* disable risc and host interrupts */ 1454 WRT_REG_WORD(®->ictrl, 0); 1455 RD_REG_WORD(®->ictrl); 1456 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1457 } 1458 1459 static void 1460 qla24xx_enable_intrs(struct qla_hw_data *ha) 1461 { 1462 unsigned long flags = 0; 1463 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1464 1465 spin_lock_irqsave(&ha->hardware_lock, flags); 1466 ha->interrupts_on = 1; 1467 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1468 RD_REG_DWORD(®->ictrl); 1469 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1470 } 1471 1472 static void 1473 qla24xx_disable_intrs(struct qla_hw_data *ha) 1474 { 1475 unsigned long flags = 0; 1476 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1477 1478 if (IS_NOPOLLING_TYPE(ha)) 1479 return; 1480 spin_lock_irqsave(&ha->hardware_lock, flags); 1481 ha->interrupts_on = 0; 1482 WRT_REG_DWORD(®->ictrl, 0); 1483 RD_REG_DWORD(®->ictrl); 1484 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1485 } 1486 1487 static int 1488 qla2x00_iospace_config(struct qla_hw_data *ha) 1489 { 1490 resource_size_t pio; 1491 uint16_t msix; 1492 int cpus; 1493 1494 if (IS_QLA82XX(ha)) 1495 return qla82xx_iospace_config(ha); 1496 1497 if (pci_request_selected_regions(ha->pdev, ha->bars, 1498 QLA2XXX_DRIVER_NAME)) { 1499 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1500 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1501 pci_name(ha->pdev)); 1502 goto iospace_error_exit; 1503 } 1504 if (!(ha->bars & 1)) 1505 goto skip_pio; 1506 1507 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1508 pio = pci_resource_start(ha->pdev, 0); 1509 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1510 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1511 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1512 "Invalid pci I/O region size (%s).\n", 1513 pci_name(ha->pdev)); 1514 pio = 0; 1515 } 1516 } else { 1517 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1518 "Region #0 no a PIO resource (%s).\n", 1519 pci_name(ha->pdev)); 1520 pio = 0; 1521 } 1522 ha->pio_address = pio; 1523 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1524 "PIO address=%llu.\n", 1525 (unsigned long long)ha->pio_address); 1526 1527 skip_pio: 1528 /* Use MMIO operations for all accesses. */ 1529 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1530 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1531 "Region #1 not an MMIO resource (%s), aborting.\n", 1532 pci_name(ha->pdev)); 1533 goto iospace_error_exit; 1534 } 1535 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1536 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1537 "Invalid PCI mem region size (%s), aborting.\n", 1538 pci_name(ha->pdev)); 1539 goto iospace_error_exit; 1540 } 1541 1542 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1543 if (!ha->iobase) { 1544 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1545 "Cannot remap MMIO (%s), aborting.\n", 1546 pci_name(ha->pdev)); 1547 goto iospace_error_exit; 1548 } 1549 1550 /* Determine queue resources */ 1551 ha->max_req_queues = ha->max_rsp_queues = 1; 1552 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1553 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1554 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1555 goto mqiobase_exit; 1556 1557 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1558 pci_resource_len(ha->pdev, 3)); 1559 if (ha->mqiobase) { 1560 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1561 "MQIO Base=%p.\n", ha->mqiobase); 1562 /* Read MSIX vector size of the board */ 1563 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1564 ha->msix_count = msix; 1565 /* Max queues are bounded by available msix vectors */ 1566 /* queue 0 uses two msix vectors */ 1567 if (ql2xmultique_tag) { 1568 cpus = num_online_cpus(); 1569 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1570 (cpus + 1) : (ha->msix_count - 1); 1571 ha->max_req_queues = 2; 1572 } else if (ql2xmaxqueues > 1) { 1573 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1574 QLA_MQ_SIZE : ql2xmaxqueues; 1575 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1576 "QoS mode set, max no of request queues:%d.\n", 1577 ha->max_req_queues); 1578 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1579 "QoS mode set, max no of request queues:%d.\n", 1580 ha->max_req_queues); 1581 } 1582 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1583 "MSI-X vector count: %d.\n", msix); 1584 } else 1585 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1586 "BAR 3 not enabled.\n"); 1587 1588 mqiobase_exit: 1589 ha->msix_count = ha->max_rsp_queues + 1; 1590 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1591 "MSIX Count:%d.\n", ha->msix_count); 1592 return (0); 1593 1594 iospace_error_exit: 1595 return (-ENOMEM); 1596 } 1597 1598 1599 static struct isp_operations qla2100_isp_ops = { 1600 .pci_config = qla2100_pci_config, 1601 .reset_chip = qla2x00_reset_chip, 1602 .chip_diag = qla2x00_chip_diag, 1603 .config_rings = qla2x00_config_rings, 1604 .reset_adapter = qla2x00_reset_adapter, 1605 .nvram_config = qla2x00_nvram_config, 1606 .update_fw_options = qla2x00_update_fw_options, 1607 .load_risc = qla2x00_load_risc, 1608 .pci_info_str = qla2x00_pci_info_str, 1609 .fw_version_str = qla2x00_fw_version_str, 1610 .intr_handler = qla2100_intr_handler, 1611 .enable_intrs = qla2x00_enable_intrs, 1612 .disable_intrs = qla2x00_disable_intrs, 1613 .abort_command = qla2x00_abort_command, 1614 .target_reset = qla2x00_abort_target, 1615 .lun_reset = qla2x00_lun_reset, 1616 .fabric_login = qla2x00_login_fabric, 1617 .fabric_logout = qla2x00_fabric_logout, 1618 .calc_req_entries = qla2x00_calc_iocbs_32, 1619 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1620 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1621 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1622 .read_nvram = qla2x00_read_nvram_data, 1623 .write_nvram = qla2x00_write_nvram_data, 1624 .fw_dump = qla2100_fw_dump, 1625 .beacon_on = NULL, 1626 .beacon_off = NULL, 1627 .beacon_blink = NULL, 1628 .read_optrom = qla2x00_read_optrom_data, 1629 .write_optrom = qla2x00_write_optrom_data, 1630 .get_flash_version = qla2x00_get_flash_version, 1631 .start_scsi = qla2x00_start_scsi, 1632 .abort_isp = qla2x00_abort_isp, 1633 .iospace_config = qla2x00_iospace_config, 1634 }; 1635 1636 static struct isp_operations qla2300_isp_ops = { 1637 .pci_config = qla2300_pci_config, 1638 .reset_chip = qla2x00_reset_chip, 1639 .chip_diag = qla2x00_chip_diag, 1640 .config_rings = qla2x00_config_rings, 1641 .reset_adapter = qla2x00_reset_adapter, 1642 .nvram_config = qla2x00_nvram_config, 1643 .update_fw_options = qla2x00_update_fw_options, 1644 .load_risc = qla2x00_load_risc, 1645 .pci_info_str = qla2x00_pci_info_str, 1646 .fw_version_str = qla2x00_fw_version_str, 1647 .intr_handler = qla2300_intr_handler, 1648 .enable_intrs = qla2x00_enable_intrs, 1649 .disable_intrs = qla2x00_disable_intrs, 1650 .abort_command = qla2x00_abort_command, 1651 .target_reset = qla2x00_abort_target, 1652 .lun_reset = qla2x00_lun_reset, 1653 .fabric_login = qla2x00_login_fabric, 1654 .fabric_logout = qla2x00_fabric_logout, 1655 .calc_req_entries = qla2x00_calc_iocbs_32, 1656 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1657 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1658 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1659 .read_nvram = qla2x00_read_nvram_data, 1660 .write_nvram = qla2x00_write_nvram_data, 1661 .fw_dump = qla2300_fw_dump, 1662 .beacon_on = qla2x00_beacon_on, 1663 .beacon_off = qla2x00_beacon_off, 1664 .beacon_blink = qla2x00_beacon_blink, 1665 .read_optrom = qla2x00_read_optrom_data, 1666 .write_optrom = qla2x00_write_optrom_data, 1667 .get_flash_version = qla2x00_get_flash_version, 1668 .start_scsi = qla2x00_start_scsi, 1669 .abort_isp = qla2x00_abort_isp, 1670 .iospace_config = qla2x00_iospace_config, 1671 }; 1672 1673 static struct isp_operations qla24xx_isp_ops = { 1674 .pci_config = qla24xx_pci_config, 1675 .reset_chip = qla24xx_reset_chip, 1676 .chip_diag = qla24xx_chip_diag, 1677 .config_rings = qla24xx_config_rings, 1678 .reset_adapter = qla24xx_reset_adapter, 1679 .nvram_config = qla24xx_nvram_config, 1680 .update_fw_options = qla24xx_update_fw_options, 1681 .load_risc = qla24xx_load_risc, 1682 .pci_info_str = qla24xx_pci_info_str, 1683 .fw_version_str = qla24xx_fw_version_str, 1684 .intr_handler = qla24xx_intr_handler, 1685 .enable_intrs = qla24xx_enable_intrs, 1686 .disable_intrs = qla24xx_disable_intrs, 1687 .abort_command = qla24xx_abort_command, 1688 .target_reset = qla24xx_abort_target, 1689 .lun_reset = qla24xx_lun_reset, 1690 .fabric_login = qla24xx_login_fabric, 1691 .fabric_logout = qla24xx_fabric_logout, 1692 .calc_req_entries = NULL, 1693 .build_iocbs = NULL, 1694 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1695 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1696 .read_nvram = qla24xx_read_nvram_data, 1697 .write_nvram = qla24xx_write_nvram_data, 1698 .fw_dump = qla24xx_fw_dump, 1699 .beacon_on = qla24xx_beacon_on, 1700 .beacon_off = qla24xx_beacon_off, 1701 .beacon_blink = qla24xx_beacon_blink, 1702 .read_optrom = qla24xx_read_optrom_data, 1703 .write_optrom = qla24xx_write_optrom_data, 1704 .get_flash_version = qla24xx_get_flash_version, 1705 .start_scsi = qla24xx_start_scsi, 1706 .abort_isp = qla2x00_abort_isp, 1707 .iospace_config = qla2x00_iospace_config, 1708 }; 1709 1710 static struct isp_operations qla25xx_isp_ops = { 1711 .pci_config = qla25xx_pci_config, 1712 .reset_chip = qla24xx_reset_chip, 1713 .chip_diag = qla24xx_chip_diag, 1714 .config_rings = qla24xx_config_rings, 1715 .reset_adapter = qla24xx_reset_adapter, 1716 .nvram_config = qla24xx_nvram_config, 1717 .update_fw_options = qla24xx_update_fw_options, 1718 .load_risc = qla24xx_load_risc, 1719 .pci_info_str = qla24xx_pci_info_str, 1720 .fw_version_str = qla24xx_fw_version_str, 1721 .intr_handler = qla24xx_intr_handler, 1722 .enable_intrs = qla24xx_enable_intrs, 1723 .disable_intrs = qla24xx_disable_intrs, 1724 .abort_command = qla24xx_abort_command, 1725 .target_reset = qla24xx_abort_target, 1726 .lun_reset = qla24xx_lun_reset, 1727 .fabric_login = qla24xx_login_fabric, 1728 .fabric_logout = qla24xx_fabric_logout, 1729 .calc_req_entries = NULL, 1730 .build_iocbs = NULL, 1731 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1732 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1733 .read_nvram = qla25xx_read_nvram_data, 1734 .write_nvram = qla25xx_write_nvram_data, 1735 .fw_dump = qla25xx_fw_dump, 1736 .beacon_on = qla24xx_beacon_on, 1737 .beacon_off = qla24xx_beacon_off, 1738 .beacon_blink = qla24xx_beacon_blink, 1739 .read_optrom = qla25xx_read_optrom_data, 1740 .write_optrom = qla24xx_write_optrom_data, 1741 .get_flash_version = qla24xx_get_flash_version, 1742 .start_scsi = qla24xx_dif_start_scsi, 1743 .abort_isp = qla2x00_abort_isp, 1744 .iospace_config = qla2x00_iospace_config, 1745 }; 1746 1747 static struct isp_operations qla81xx_isp_ops = { 1748 .pci_config = qla25xx_pci_config, 1749 .reset_chip = qla24xx_reset_chip, 1750 .chip_diag = qla24xx_chip_diag, 1751 .config_rings = qla24xx_config_rings, 1752 .reset_adapter = qla24xx_reset_adapter, 1753 .nvram_config = qla81xx_nvram_config, 1754 .update_fw_options = qla81xx_update_fw_options, 1755 .load_risc = qla81xx_load_risc, 1756 .pci_info_str = qla24xx_pci_info_str, 1757 .fw_version_str = qla24xx_fw_version_str, 1758 .intr_handler = qla24xx_intr_handler, 1759 .enable_intrs = qla24xx_enable_intrs, 1760 .disable_intrs = qla24xx_disable_intrs, 1761 .abort_command = qla24xx_abort_command, 1762 .target_reset = qla24xx_abort_target, 1763 .lun_reset = qla24xx_lun_reset, 1764 .fabric_login = qla24xx_login_fabric, 1765 .fabric_logout = qla24xx_fabric_logout, 1766 .calc_req_entries = NULL, 1767 .build_iocbs = NULL, 1768 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1769 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1770 .read_nvram = NULL, 1771 .write_nvram = NULL, 1772 .fw_dump = qla81xx_fw_dump, 1773 .beacon_on = qla24xx_beacon_on, 1774 .beacon_off = qla24xx_beacon_off, 1775 .beacon_blink = qla24xx_beacon_blink, 1776 .read_optrom = qla25xx_read_optrom_data, 1777 .write_optrom = qla24xx_write_optrom_data, 1778 .get_flash_version = qla24xx_get_flash_version, 1779 .start_scsi = qla24xx_dif_start_scsi, 1780 .abort_isp = qla2x00_abort_isp, 1781 .iospace_config = qla2x00_iospace_config, 1782 }; 1783 1784 static struct isp_operations qla82xx_isp_ops = { 1785 .pci_config = qla82xx_pci_config, 1786 .reset_chip = qla82xx_reset_chip, 1787 .chip_diag = qla24xx_chip_diag, 1788 .config_rings = qla82xx_config_rings, 1789 .reset_adapter = qla24xx_reset_adapter, 1790 .nvram_config = qla81xx_nvram_config, 1791 .update_fw_options = qla24xx_update_fw_options, 1792 .load_risc = qla82xx_load_risc, 1793 .pci_info_str = qla82xx_pci_info_str, 1794 .fw_version_str = qla24xx_fw_version_str, 1795 .intr_handler = qla82xx_intr_handler, 1796 .enable_intrs = qla82xx_enable_intrs, 1797 .disable_intrs = qla82xx_disable_intrs, 1798 .abort_command = qla24xx_abort_command, 1799 .target_reset = qla24xx_abort_target, 1800 .lun_reset = qla24xx_lun_reset, 1801 .fabric_login = qla24xx_login_fabric, 1802 .fabric_logout = qla24xx_fabric_logout, 1803 .calc_req_entries = NULL, 1804 .build_iocbs = NULL, 1805 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1806 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1807 .read_nvram = qla24xx_read_nvram_data, 1808 .write_nvram = qla24xx_write_nvram_data, 1809 .fw_dump = qla24xx_fw_dump, 1810 .beacon_on = qla82xx_beacon_on, 1811 .beacon_off = qla82xx_beacon_off, 1812 .beacon_blink = NULL, 1813 .read_optrom = qla82xx_read_optrom_data, 1814 .write_optrom = qla82xx_write_optrom_data, 1815 .get_flash_version = qla24xx_get_flash_version, 1816 .start_scsi = qla82xx_start_scsi, 1817 .abort_isp = qla82xx_abort_isp, 1818 .iospace_config = qla82xx_iospace_config, 1819 }; 1820 1821 static inline void 1822 qla2x00_set_isp_flags(struct qla_hw_data *ha) 1823 { 1824 ha->device_type = DT_EXTENDED_IDS; 1825 switch (ha->pdev->device) { 1826 case PCI_DEVICE_ID_QLOGIC_ISP2100: 1827 ha->device_type |= DT_ISP2100; 1828 ha->device_type &= ~DT_EXTENDED_IDS; 1829 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1830 break; 1831 case PCI_DEVICE_ID_QLOGIC_ISP2200: 1832 ha->device_type |= DT_ISP2200; 1833 ha->device_type &= ~DT_EXTENDED_IDS; 1834 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1835 break; 1836 case PCI_DEVICE_ID_QLOGIC_ISP2300: 1837 ha->device_type |= DT_ISP2300; 1838 ha->device_type |= DT_ZIO_SUPPORTED; 1839 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1840 break; 1841 case PCI_DEVICE_ID_QLOGIC_ISP2312: 1842 ha->device_type |= DT_ISP2312; 1843 ha->device_type |= DT_ZIO_SUPPORTED; 1844 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1845 break; 1846 case PCI_DEVICE_ID_QLOGIC_ISP2322: 1847 ha->device_type |= DT_ISP2322; 1848 ha->device_type |= DT_ZIO_SUPPORTED; 1849 if (ha->pdev->subsystem_vendor == 0x1028 && 1850 ha->pdev->subsystem_device == 0x0170) 1851 ha->device_type |= DT_OEM_001; 1852 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1853 break; 1854 case PCI_DEVICE_ID_QLOGIC_ISP6312: 1855 ha->device_type |= DT_ISP6312; 1856 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1857 break; 1858 case PCI_DEVICE_ID_QLOGIC_ISP6322: 1859 ha->device_type |= DT_ISP6322; 1860 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1861 break; 1862 case PCI_DEVICE_ID_QLOGIC_ISP2422: 1863 ha->device_type |= DT_ISP2422; 1864 ha->device_type |= DT_ZIO_SUPPORTED; 1865 ha->device_type |= DT_FWI2; 1866 ha->device_type |= DT_IIDMA; 1867 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1868 break; 1869 case PCI_DEVICE_ID_QLOGIC_ISP2432: 1870 ha->device_type |= DT_ISP2432; 1871 ha->device_type |= DT_ZIO_SUPPORTED; 1872 ha->device_type |= DT_FWI2; 1873 ha->device_type |= DT_IIDMA; 1874 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1875 break; 1876 case PCI_DEVICE_ID_QLOGIC_ISP8432: 1877 ha->device_type |= DT_ISP8432; 1878 ha->device_type |= DT_ZIO_SUPPORTED; 1879 ha->device_type |= DT_FWI2; 1880 ha->device_type |= DT_IIDMA; 1881 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1882 break; 1883 case PCI_DEVICE_ID_QLOGIC_ISP5422: 1884 ha->device_type |= DT_ISP5422; 1885 ha->device_type |= DT_FWI2; 1886 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1887 break; 1888 case PCI_DEVICE_ID_QLOGIC_ISP5432: 1889 ha->device_type |= DT_ISP5432; 1890 ha->device_type |= DT_FWI2; 1891 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1892 break; 1893 case PCI_DEVICE_ID_QLOGIC_ISP2532: 1894 ha->device_type |= DT_ISP2532; 1895 ha->device_type |= DT_ZIO_SUPPORTED; 1896 ha->device_type |= DT_FWI2; 1897 ha->device_type |= DT_IIDMA; 1898 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1899 break; 1900 case PCI_DEVICE_ID_QLOGIC_ISP8001: 1901 ha->device_type |= DT_ISP8001; 1902 ha->device_type |= DT_ZIO_SUPPORTED; 1903 ha->device_type |= DT_FWI2; 1904 ha->device_type |= DT_IIDMA; 1905 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1906 break; 1907 case PCI_DEVICE_ID_QLOGIC_ISP8021: 1908 ha->device_type |= DT_ISP8021; 1909 ha->device_type |= DT_ZIO_SUPPORTED; 1910 ha->device_type |= DT_FWI2; 1911 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1912 /* Initialize 82XX ISP flags */ 1913 qla82xx_init_flags(ha); 1914 break; 1915 } 1916 1917 if (IS_QLA82XX(ha)) 1918 ha->port_no = !(ha->portnum & 1); 1919 else 1920 /* Get adapter physical port no from interrupt pin register. */ 1921 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 1922 1923 if (ha->port_no & 1) 1924 ha->flags.port0 = 1; 1925 else 1926 ha->flags.port0 = 0; 1927 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 1928 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 1929 ha->device_type, ha->flags.port0, ha->fw_srisc_address); 1930 } 1931 1932 static void 1933 qla2xxx_scan_start(struct Scsi_Host *shost) 1934 { 1935 scsi_qla_host_t *vha = shost_priv(shost); 1936 1937 if (vha->hw->flags.running_gold_fw) 1938 return; 1939 1940 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1941 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 1942 set_bit(RSCN_UPDATE, &vha->dpc_flags); 1943 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 1944 } 1945 1946 static int 1947 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 1948 { 1949 scsi_qla_host_t *vha = shost_priv(shost); 1950 1951 if (!vha->host) 1952 return 1; 1953 if (time > vha->hw->loop_reset_delay * HZ) 1954 return 1; 1955 1956 return atomic_read(&vha->loop_state) == LOOP_READY; 1957 } 1958 1959 /* 1960 * PCI driver interface 1961 */ 1962 static int __devinit 1963 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1964 { 1965 int ret = -ENODEV; 1966 struct Scsi_Host *host; 1967 scsi_qla_host_t *base_vha = NULL; 1968 struct qla_hw_data *ha; 1969 char pci_info[30]; 1970 char fw_str[30]; 1971 struct scsi_host_template *sht; 1972 int bars, max_id, mem_only = 0; 1973 uint16_t req_length = 0, rsp_length = 0; 1974 struct req_que *req = NULL; 1975 struct rsp_que *rsp = NULL; 1976 1977 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 1978 sht = &qla2xxx_driver_template; 1979 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 1980 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 1981 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 1982 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 1983 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 1984 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 1985 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 1986 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) { 1987 bars = pci_select_bars(pdev, IORESOURCE_MEM); 1988 mem_only = 1; 1989 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 1990 "Mem only adapter.\n"); 1991 } 1992 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 1993 "Bars=%d.\n", bars); 1994 1995 if (mem_only) { 1996 if (pci_enable_device_mem(pdev)) 1997 goto probe_out; 1998 } else { 1999 if (pci_enable_device(pdev)) 2000 goto probe_out; 2001 } 2002 2003 /* This may fail but that's ok */ 2004 pci_enable_pcie_error_reporting(pdev); 2005 2006 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2007 if (!ha) { 2008 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2009 "Unable to allocate memory for ha.\n"); 2010 goto probe_out; 2011 } 2012 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2013 "Memory allocated for ha=%p.\n", ha); 2014 ha->pdev = pdev; 2015 2016 /* Clear our data area */ 2017 ha->bars = bars; 2018 ha->mem_only = mem_only; 2019 spin_lock_init(&ha->hardware_lock); 2020 spin_lock_init(&ha->vport_slock); 2021 2022 /* Set ISP-type information. */ 2023 qla2x00_set_isp_flags(ha); 2024 2025 /* Set EEH reset type to fundamental if required by hba */ 2026 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) { 2027 pdev->needs_freset = 1; 2028 } 2029 2030 ha->prev_topology = 0; 2031 ha->init_cb_size = sizeof(init_cb_t); 2032 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2033 ha->optrom_size = OPTROM_SIZE_2300; 2034 2035 /* Assign ISP specific operations. */ 2036 max_id = MAX_TARGETS_2200; 2037 if (IS_QLA2100(ha)) { 2038 max_id = MAX_TARGETS_2100; 2039 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2040 req_length = REQUEST_ENTRY_CNT_2100; 2041 rsp_length = RESPONSE_ENTRY_CNT_2100; 2042 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2043 ha->gid_list_info_size = 4; 2044 ha->flash_conf_off = ~0; 2045 ha->flash_data_off = ~0; 2046 ha->nvram_conf_off = ~0; 2047 ha->nvram_data_off = ~0; 2048 ha->isp_ops = &qla2100_isp_ops; 2049 } else if (IS_QLA2200(ha)) { 2050 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2051 req_length = REQUEST_ENTRY_CNT_2200; 2052 rsp_length = RESPONSE_ENTRY_CNT_2100; 2053 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2054 ha->gid_list_info_size = 4; 2055 ha->flash_conf_off = ~0; 2056 ha->flash_data_off = ~0; 2057 ha->nvram_conf_off = ~0; 2058 ha->nvram_data_off = ~0; 2059 ha->isp_ops = &qla2100_isp_ops; 2060 } else if (IS_QLA23XX(ha)) { 2061 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2062 req_length = REQUEST_ENTRY_CNT_2200; 2063 rsp_length = RESPONSE_ENTRY_CNT_2300; 2064 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2065 ha->gid_list_info_size = 6; 2066 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2067 ha->optrom_size = OPTROM_SIZE_2322; 2068 ha->flash_conf_off = ~0; 2069 ha->flash_data_off = ~0; 2070 ha->nvram_conf_off = ~0; 2071 ha->nvram_data_off = ~0; 2072 ha->isp_ops = &qla2300_isp_ops; 2073 } else if (IS_QLA24XX_TYPE(ha)) { 2074 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2075 req_length = REQUEST_ENTRY_CNT_24XX; 2076 rsp_length = RESPONSE_ENTRY_CNT_2300; 2077 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2078 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2079 ha->gid_list_info_size = 8; 2080 ha->optrom_size = OPTROM_SIZE_24XX; 2081 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2082 ha->isp_ops = &qla24xx_isp_ops; 2083 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2084 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2085 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2086 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2087 } else if (IS_QLA25XX(ha)) { 2088 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2089 req_length = REQUEST_ENTRY_CNT_24XX; 2090 rsp_length = RESPONSE_ENTRY_CNT_2300; 2091 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2092 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2093 ha->gid_list_info_size = 8; 2094 ha->optrom_size = OPTROM_SIZE_25XX; 2095 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2096 ha->isp_ops = &qla25xx_isp_ops; 2097 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2098 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2099 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2100 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2101 } else if (IS_QLA81XX(ha)) { 2102 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2103 req_length = REQUEST_ENTRY_CNT_24XX; 2104 rsp_length = RESPONSE_ENTRY_CNT_2300; 2105 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2106 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2107 ha->gid_list_info_size = 8; 2108 ha->optrom_size = OPTROM_SIZE_81XX; 2109 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2110 ha->isp_ops = &qla81xx_isp_ops; 2111 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2112 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2113 ha->nvram_conf_off = ~0; 2114 ha->nvram_data_off = ~0; 2115 } else if (IS_QLA82XX(ha)) { 2116 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2117 req_length = REQUEST_ENTRY_CNT_82XX; 2118 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2119 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2120 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2121 ha->gid_list_info_size = 8; 2122 ha->optrom_size = OPTROM_SIZE_82XX; 2123 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2124 ha->isp_ops = &qla82xx_isp_ops; 2125 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2126 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2127 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2128 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2129 } 2130 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2131 "mbx_count=%d, req_length=%d, " 2132 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2133 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n", 2134 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2135 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2136 ha->nvram_npiv_size); 2137 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2138 "isp_ops=%p, flash_conf_off=%d, " 2139 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2140 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2141 ha->nvram_conf_off, ha->nvram_data_off); 2142 2143 /* Configure PCI I/O space */ 2144 ret = ha->isp_ops->iospace_config(ha); 2145 if (ret) 2146 goto probe_hw_failed; 2147 2148 ql_log_pci(ql_log_info, pdev, 0x001d, 2149 "Found an ISP%04X irq %d iobase 0x%p.\n", 2150 pdev->device, pdev->irq, ha->iobase); 2151 mutex_init(&ha->vport_lock); 2152 init_completion(&ha->mbx_cmd_comp); 2153 complete(&ha->mbx_cmd_comp); 2154 init_completion(&ha->mbx_intr_comp); 2155 init_completion(&ha->dcbx_comp); 2156 2157 set_bit(0, (unsigned long *) ha->vp_idx_map); 2158 2159 qla2x00_config_dma_addressing(ha); 2160 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2161 "64 Bit addressing is %s.\n", 2162 ha->flags.enable_64bit_addressing ? "enable" : 2163 "disable"); 2164 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2165 if (!ret) { 2166 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2167 "Failed to allocate memory for adapter, aborting.\n"); 2168 2169 goto probe_hw_failed; 2170 } 2171 2172 req->max_q_depth = MAX_Q_DEPTH; 2173 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2174 req->max_q_depth = ql2xmaxqdepth; 2175 2176 2177 base_vha = qla2x00_create_host(sht, ha); 2178 if (!base_vha) { 2179 ret = -ENOMEM; 2180 qla2x00_mem_free(ha); 2181 qla2x00_free_req_que(ha, req); 2182 qla2x00_free_rsp_que(ha, rsp); 2183 goto probe_hw_failed; 2184 } 2185 2186 pci_set_drvdata(pdev, base_vha); 2187 2188 host = base_vha->host; 2189 base_vha->req = req; 2190 host->can_queue = req->length + 128; 2191 if (IS_QLA2XXX_MIDTYPE(ha)) 2192 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2193 else 2194 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2195 base_vha->vp_idx; 2196 2197 /* Set the SG table size based on ISP type */ 2198 if (!IS_FWI2_CAPABLE(ha)) { 2199 if (IS_QLA2100(ha)) 2200 host->sg_tablesize = 32; 2201 } else { 2202 if (!IS_QLA82XX(ha)) 2203 host->sg_tablesize = QLA_SG_ALL; 2204 } 2205 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2206 "can_queue=%d, req=%p, " 2207 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2208 host->can_queue, base_vha->req, 2209 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2210 host->max_id = max_id; 2211 host->this_id = 255; 2212 host->cmd_per_lun = 3; 2213 host->unique_id = host->host_no; 2214 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2215 host->max_cmd_len = 32; 2216 else 2217 host->max_cmd_len = MAX_CMDSZ; 2218 host->max_channel = MAX_BUSES - 1; 2219 host->max_lun = ql2xmaxlun; 2220 host->transportt = qla2xxx_transport_template; 2221 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2222 2223 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2224 "max_id=%d this_id=%d " 2225 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2226 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, 2227 host->this_id, host->cmd_per_lun, host->unique_id, 2228 host->max_cmd_len, host->max_channel, host->max_lun, 2229 host->transportt, sht->vendor_id); 2230 2231 /* Set up the irqs */ 2232 ret = qla2x00_request_irqs(ha, rsp); 2233 if (ret) 2234 goto probe_init_failed; 2235 2236 pci_save_state(pdev); 2237 2238 /* Alloc arrays of request and response ring ptrs */ 2239 que_init: 2240 if (!qla2x00_alloc_queues(ha)) { 2241 ql_log(ql_log_fatal, base_vha, 0x003d, 2242 "Failed to allocate memory for queue pointers.. aborting.\n"); 2243 goto probe_init_failed; 2244 } 2245 2246 ha->rsp_q_map[0] = rsp; 2247 ha->req_q_map[0] = req; 2248 rsp->req = req; 2249 req->rsp = rsp; 2250 set_bit(0, ha->req_qid_map); 2251 set_bit(0, ha->rsp_qid_map); 2252 /* FWI2-capable only. */ 2253 req->req_q_in = &ha->iobase->isp24.req_q_in; 2254 req->req_q_out = &ha->iobase->isp24.req_q_out; 2255 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2256 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2257 if (ha->mqenable) { 2258 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2259 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2260 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2261 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2262 } 2263 2264 if (IS_QLA82XX(ha)) { 2265 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2266 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2267 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2268 } 2269 2270 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2271 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2272 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2273 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2274 "req->req_q_in=%p req->req_q_out=%p " 2275 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2276 req->req_q_in, req->req_q_out, 2277 rsp->rsp_q_in, rsp->rsp_q_out); 2278 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2279 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2280 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2281 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2282 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2283 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2284 2285 if (qla2x00_initialize_adapter(base_vha)) { 2286 ql_log(ql_log_fatal, base_vha, 0x00d6, 2287 "Failed to initialize adapter - Adapter flags %x.\n", 2288 base_vha->device_flags); 2289 2290 if (IS_QLA82XX(ha)) { 2291 qla82xx_idc_lock(ha); 2292 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2293 QLA82XX_DEV_FAILED); 2294 qla82xx_idc_unlock(ha); 2295 ql_log(ql_log_fatal, base_vha, 0x00d7, 2296 "HW State: FAILED.\n"); 2297 } 2298 2299 ret = -ENODEV; 2300 goto probe_failed; 2301 } 2302 2303 if (ha->mqenable) { 2304 if (qla25xx_setup_mode(base_vha)) { 2305 ql_log(ql_log_warn, base_vha, 0x00ec, 2306 "Failed to create queues, falling back to single queue mode.\n"); 2307 goto que_init; 2308 } 2309 } 2310 2311 if (ha->flags.running_gold_fw) 2312 goto skip_dpc; 2313 2314 /* 2315 * Startup the kernel thread for this host adapter 2316 */ 2317 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2318 "%s_dpc", base_vha->host_str); 2319 if (IS_ERR(ha->dpc_thread)) { 2320 ql_log(ql_log_fatal, base_vha, 0x00ed, 2321 "Failed to start DPC thread.\n"); 2322 ret = PTR_ERR(ha->dpc_thread); 2323 goto probe_failed; 2324 } 2325 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2326 "DPC thread started successfully.\n"); 2327 2328 skip_dpc: 2329 list_add_tail(&base_vha->list, &ha->vp_list); 2330 base_vha->host->irq = ha->pdev->irq; 2331 2332 /* Initialized the timer */ 2333 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2334 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2335 "Started qla2x00_timer with " 2336 "interval=%d.\n", WATCH_INTERVAL); 2337 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2338 "Detected hba at address=%p.\n", 2339 ha); 2340 2341 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2342 if (ha->fw_attributes & BIT_4) { 2343 int prot = 0; 2344 base_vha->flags.difdix_supported = 1; 2345 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2346 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2347 if (ql2xenabledif == 1) 2348 prot = SHOST_DIX_TYPE0_PROTECTION; 2349 scsi_host_set_prot(host, 2350 prot | SHOST_DIF_TYPE1_PROTECTION 2351 | SHOST_DIF_TYPE2_PROTECTION 2352 | SHOST_DIF_TYPE3_PROTECTION 2353 | SHOST_DIX_TYPE1_PROTECTION 2354 | SHOST_DIX_TYPE2_PROTECTION 2355 | SHOST_DIX_TYPE3_PROTECTION); 2356 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); 2357 } else 2358 base_vha->flags.difdix_supported = 0; 2359 } 2360 2361 ha->isp_ops->enable_intrs(ha); 2362 2363 ret = scsi_add_host(host, &pdev->dev); 2364 if (ret) 2365 goto probe_failed; 2366 2367 base_vha->flags.init_done = 1; 2368 base_vha->flags.online = 1; 2369 2370 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2371 "Init done and hba is online.\n"); 2372 2373 scsi_scan_host(host); 2374 2375 qla2x00_alloc_sysfs_attr(base_vha); 2376 2377 qla2x00_init_host_attr(base_vha); 2378 2379 qla2x00_dfs_setup(base_vha); 2380 2381 ql_log(ql_log_info, base_vha, 0x00fb, 2382 "QLogic %s - %s.\n", 2383 ha->model_number, ha->model_desc ? ha->model_desc : ""); 2384 ql_log(ql_log_info, base_vha, 0x00fc, 2385 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2386 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2387 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2388 base_vha->host_no, 2389 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2390 2391 return 0; 2392 2393 probe_init_failed: 2394 qla2x00_free_req_que(ha, req); 2395 qla2x00_free_rsp_que(ha, rsp); 2396 ha->max_req_queues = ha->max_rsp_queues = 0; 2397 2398 probe_failed: 2399 if (base_vha->timer_active) 2400 qla2x00_stop_timer(base_vha); 2401 base_vha->flags.online = 0; 2402 if (ha->dpc_thread) { 2403 struct task_struct *t = ha->dpc_thread; 2404 2405 ha->dpc_thread = NULL; 2406 kthread_stop(t); 2407 } 2408 2409 qla2x00_free_device(base_vha); 2410 2411 scsi_host_put(base_vha->host); 2412 2413 probe_hw_failed: 2414 if (IS_QLA82XX(ha)) { 2415 qla82xx_idc_lock(ha); 2416 qla82xx_clear_drv_active(ha); 2417 qla82xx_idc_unlock(ha); 2418 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2419 if (!ql2xdbwr) 2420 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2421 } else { 2422 if (ha->iobase) 2423 iounmap(ha->iobase); 2424 } 2425 pci_release_selected_regions(ha->pdev, ha->bars); 2426 kfree(ha); 2427 ha = NULL; 2428 2429 probe_out: 2430 pci_disable_device(pdev); 2431 return ret; 2432 } 2433 2434 static void 2435 qla2x00_shutdown(struct pci_dev *pdev) 2436 { 2437 scsi_qla_host_t *vha; 2438 struct qla_hw_data *ha; 2439 2440 vha = pci_get_drvdata(pdev); 2441 ha = vha->hw; 2442 2443 /* Turn-off FCE trace */ 2444 if (ha->flags.fce_enabled) { 2445 qla2x00_disable_fce_trace(vha, NULL, NULL); 2446 ha->flags.fce_enabled = 0; 2447 } 2448 2449 /* Turn-off EFT trace */ 2450 if (ha->eft) 2451 qla2x00_disable_eft_trace(vha); 2452 2453 /* Stop currently executing firmware. */ 2454 qla2x00_try_to_stop_firmware(vha); 2455 2456 /* Turn adapter off line */ 2457 vha->flags.online = 0; 2458 2459 /* turn-off interrupts on the card */ 2460 if (ha->interrupts_on) { 2461 vha->flags.init_done = 0; 2462 ha->isp_ops->disable_intrs(ha); 2463 } 2464 2465 qla2x00_free_irqs(vha); 2466 2467 qla2x00_free_fw_dump(ha); 2468 } 2469 2470 static void 2471 qla2x00_remove_one(struct pci_dev *pdev) 2472 { 2473 scsi_qla_host_t *base_vha, *vha; 2474 struct qla_hw_data *ha; 2475 unsigned long flags; 2476 2477 base_vha = pci_get_drvdata(pdev); 2478 ha = base_vha->hw; 2479 2480 mutex_lock(&ha->vport_lock); 2481 while (ha->cur_vport_count) { 2482 struct Scsi_Host *scsi_host; 2483 2484 spin_lock_irqsave(&ha->vport_slock, flags); 2485 2486 BUG_ON(base_vha->list.next == &ha->vp_list); 2487 /* This assumes first entry in ha->vp_list is always base vha */ 2488 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2489 scsi_host = scsi_host_get(vha->host); 2490 2491 spin_unlock_irqrestore(&ha->vport_slock, flags); 2492 mutex_unlock(&ha->vport_lock); 2493 2494 fc_vport_terminate(vha->fc_vport); 2495 scsi_host_put(vha->host); 2496 2497 mutex_lock(&ha->vport_lock); 2498 } 2499 mutex_unlock(&ha->vport_lock); 2500 2501 set_bit(UNLOADING, &base_vha->dpc_flags); 2502 2503 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 2504 2505 qla2x00_dfs_remove(base_vha); 2506 2507 qla84xx_put_chip(base_vha); 2508 2509 /* Disable timer */ 2510 if (base_vha->timer_active) 2511 qla2x00_stop_timer(base_vha); 2512 2513 base_vha->flags.online = 0; 2514 2515 /* Flush the work queue and remove it */ 2516 if (ha->wq) { 2517 flush_workqueue(ha->wq); 2518 destroy_workqueue(ha->wq); 2519 ha->wq = NULL; 2520 } 2521 2522 /* Kill the kernel thread for this host */ 2523 if (ha->dpc_thread) { 2524 struct task_struct *t = ha->dpc_thread; 2525 2526 /* 2527 * qla2xxx_wake_dpc checks for ->dpc_thread 2528 * so we need to zero it out. 2529 */ 2530 ha->dpc_thread = NULL; 2531 kthread_stop(t); 2532 } 2533 2534 qla2x00_free_sysfs_attr(base_vha); 2535 2536 fc_remove_host(base_vha->host); 2537 2538 scsi_remove_host(base_vha->host); 2539 2540 qla2x00_free_device(base_vha); 2541 2542 scsi_host_put(base_vha->host); 2543 2544 if (IS_QLA82XX(ha)) { 2545 qla82xx_idc_lock(ha); 2546 qla82xx_clear_drv_active(ha); 2547 qla82xx_idc_unlock(ha); 2548 2549 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2550 if (!ql2xdbwr) 2551 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2552 } else { 2553 if (ha->iobase) 2554 iounmap(ha->iobase); 2555 2556 if (ha->mqiobase) 2557 iounmap(ha->mqiobase); 2558 } 2559 2560 pci_release_selected_regions(ha->pdev, ha->bars); 2561 kfree(ha); 2562 ha = NULL; 2563 2564 pci_disable_pcie_error_reporting(pdev); 2565 2566 pci_disable_device(pdev); 2567 pci_set_drvdata(pdev, NULL); 2568 } 2569 2570 static void 2571 qla2x00_free_device(scsi_qla_host_t *vha) 2572 { 2573 struct qla_hw_data *ha = vha->hw; 2574 2575 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2576 2577 /* Disable timer */ 2578 if (vha->timer_active) 2579 qla2x00_stop_timer(vha); 2580 2581 /* Kill the kernel thread for this host */ 2582 if (ha->dpc_thread) { 2583 struct task_struct *t = ha->dpc_thread; 2584 2585 /* 2586 * qla2xxx_wake_dpc checks for ->dpc_thread 2587 * so we need to zero it out. 2588 */ 2589 ha->dpc_thread = NULL; 2590 kthread_stop(t); 2591 } 2592 2593 qla25xx_delete_queues(vha); 2594 2595 if (ha->flags.fce_enabled) 2596 qla2x00_disable_fce_trace(vha, NULL, NULL); 2597 2598 if (ha->eft) 2599 qla2x00_disable_eft_trace(vha); 2600 2601 /* Stop currently executing firmware. */ 2602 qla2x00_try_to_stop_firmware(vha); 2603 2604 vha->flags.online = 0; 2605 2606 /* turn-off interrupts on the card */ 2607 if (ha->interrupts_on) { 2608 vha->flags.init_done = 0; 2609 ha->isp_ops->disable_intrs(ha); 2610 } 2611 2612 qla2x00_free_irqs(vha); 2613 2614 qla2x00_free_fcports(vha); 2615 2616 qla2x00_mem_free(ha); 2617 2618 qla82xx_md_free(vha); 2619 2620 qla2x00_free_queues(ha); 2621 } 2622 2623 void qla2x00_free_fcports(struct scsi_qla_host *vha) 2624 { 2625 fc_port_t *fcport, *tfcport; 2626 2627 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 2628 list_del(&fcport->list); 2629 kfree(fcport); 2630 fcport = NULL; 2631 } 2632 } 2633 2634 static inline void 2635 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 2636 int defer) 2637 { 2638 struct fc_rport *rport; 2639 scsi_qla_host_t *base_vha; 2640 unsigned long flags; 2641 2642 if (!fcport->rport) 2643 return; 2644 2645 rport = fcport->rport; 2646 if (defer) { 2647 base_vha = pci_get_drvdata(vha->hw->pdev); 2648 spin_lock_irqsave(vha->host->host_lock, flags); 2649 fcport->drport = rport; 2650 spin_unlock_irqrestore(vha->host->host_lock, flags); 2651 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 2652 qla2xxx_wake_dpc(base_vha); 2653 } else 2654 fc_remote_port_delete(rport); 2655 } 2656 2657 /* 2658 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 2659 * 2660 * Input: ha = adapter block pointer. fcport = port structure pointer. 2661 * 2662 * Return: None. 2663 * 2664 * Context: 2665 */ 2666 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 2667 int do_login, int defer) 2668 { 2669 if (atomic_read(&fcport->state) == FCS_ONLINE && 2670 vha->vp_idx == fcport->vp_idx) { 2671 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2672 qla2x00_schedule_rport_del(vha, fcport, defer); 2673 } 2674 /* 2675 * We may need to retry the login, so don't change the state of the 2676 * port but do the retries. 2677 */ 2678 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 2679 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2680 2681 if (!do_login) 2682 return; 2683 2684 if (fcport->login_retry == 0) { 2685 fcport->login_retry = vha->hw->login_retry_count; 2686 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2687 2688 ql_dbg(ql_dbg_disc, vha, 0x2067, 2689 "Port login retry " 2690 "%02x%02x%02x%02x%02x%02x%02x%02x, " 2691 "id = 0x%04x retry cnt=%d.\n", 2692 fcport->port_name[0], fcport->port_name[1], 2693 fcport->port_name[2], fcport->port_name[3], 2694 fcport->port_name[4], fcport->port_name[5], 2695 fcport->port_name[6], fcport->port_name[7], 2696 fcport->loop_id, fcport->login_retry); 2697 } 2698 } 2699 2700 /* 2701 * qla2x00_mark_all_devices_lost 2702 * Updates fcport state when device goes offline. 2703 * 2704 * Input: 2705 * ha = adapter block pointer. 2706 * fcport = port structure pointer. 2707 * 2708 * Return: 2709 * None. 2710 * 2711 * Context: 2712 */ 2713 void 2714 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 2715 { 2716 fc_port_t *fcport; 2717 2718 list_for_each_entry(fcport, &vha->vp_fcports, list) { 2719 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx) 2720 continue; 2721 2722 /* 2723 * No point in marking the device as lost, if the device is 2724 * already DEAD. 2725 */ 2726 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 2727 continue; 2728 if (atomic_read(&fcport->state) == FCS_ONLINE) { 2729 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2730 if (defer) 2731 qla2x00_schedule_rport_del(vha, fcport, defer); 2732 else if (vha->vp_idx == fcport->vp_idx) 2733 qla2x00_schedule_rport_del(vha, fcport, defer); 2734 } 2735 } 2736 } 2737 2738 /* 2739 * qla2x00_mem_alloc 2740 * Allocates adapter memory. 2741 * 2742 * Returns: 2743 * 0 = success. 2744 * !0 = failure. 2745 */ 2746 static int 2747 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 2748 struct req_que **req, struct rsp_que **rsp) 2749 { 2750 char name[16]; 2751 2752 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 2753 &ha->init_cb_dma, GFP_KERNEL); 2754 if (!ha->init_cb) 2755 goto fail; 2756 2757 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE, 2758 &ha->gid_list_dma, GFP_KERNEL); 2759 if (!ha->gid_list) 2760 goto fail_free_init_cb; 2761 2762 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 2763 if (!ha->srb_mempool) 2764 goto fail_free_gid_list; 2765 2766 if (IS_QLA82XX(ha)) { 2767 /* Allocate cache for CT6 Ctx. */ 2768 if (!ctx_cachep) { 2769 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 2770 sizeof(struct ct6_dsd), 0, 2771 SLAB_HWCACHE_ALIGN, NULL); 2772 if (!ctx_cachep) 2773 goto fail_free_gid_list; 2774 } 2775 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 2776 ctx_cachep); 2777 if (!ha->ctx_mempool) 2778 goto fail_free_srb_mempool; 2779 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 2780 "ctx_cachep=%p ctx_mempool=%p.\n", 2781 ctx_cachep, ha->ctx_mempool); 2782 } 2783 2784 /* Get memory for cached NVRAM */ 2785 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 2786 if (!ha->nvram) 2787 goto fail_free_ctx_mempool; 2788 2789 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 2790 ha->pdev->device); 2791 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2792 DMA_POOL_SIZE, 8, 0); 2793 if (!ha->s_dma_pool) 2794 goto fail_free_nvram; 2795 2796 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 2797 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 2798 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 2799 2800 if (IS_QLA82XX(ha) || ql2xenabledif) { 2801 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2802 DSD_LIST_DMA_POOL_SIZE, 8, 0); 2803 if (!ha->dl_dma_pool) { 2804 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 2805 "Failed to allocate memory for dl_dma_pool.\n"); 2806 goto fail_s_dma_pool; 2807 } 2808 2809 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2810 FCP_CMND_DMA_POOL_SIZE, 8, 0); 2811 if (!ha->fcp_cmnd_dma_pool) { 2812 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 2813 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 2814 goto fail_dl_dma_pool; 2815 } 2816 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 2817 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 2818 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 2819 } 2820 2821 /* Allocate memory for SNS commands */ 2822 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 2823 /* Get consistent memory allocated for SNS commands */ 2824 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 2825 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 2826 if (!ha->sns_cmd) 2827 goto fail_dma_pool; 2828 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 2829 "sns_cmd: %p.\n", ha->sns_cmd); 2830 } else { 2831 /* Get consistent memory allocated for MS IOCB */ 2832 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2833 &ha->ms_iocb_dma); 2834 if (!ha->ms_iocb) 2835 goto fail_dma_pool; 2836 /* Get consistent memory allocated for CT SNS commands */ 2837 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 2838 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 2839 if (!ha->ct_sns) 2840 goto fail_free_ms_iocb; 2841 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 2842 "ms_iocb=%p ct_sns=%p.\n", 2843 ha->ms_iocb, ha->ct_sns); 2844 } 2845 2846 /* Allocate memory for request ring */ 2847 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 2848 if (!*req) { 2849 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 2850 "Failed to allocate memory for req.\n"); 2851 goto fail_req; 2852 } 2853 (*req)->length = req_len; 2854 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 2855 ((*req)->length + 1) * sizeof(request_t), 2856 &(*req)->dma, GFP_KERNEL); 2857 if (!(*req)->ring) { 2858 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 2859 "Failed to allocate memory for req_ring.\n"); 2860 goto fail_req_ring; 2861 } 2862 /* Allocate memory for response ring */ 2863 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 2864 if (!*rsp) { 2865 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 2866 "Failed to allocate memory for rsp.\n"); 2867 goto fail_rsp; 2868 } 2869 (*rsp)->hw = ha; 2870 (*rsp)->length = rsp_len; 2871 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 2872 ((*rsp)->length + 1) * sizeof(response_t), 2873 &(*rsp)->dma, GFP_KERNEL); 2874 if (!(*rsp)->ring) { 2875 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 2876 "Failed to allocate memory for rsp_ring.\n"); 2877 goto fail_rsp_ring; 2878 } 2879 (*req)->rsp = *rsp; 2880 (*rsp)->req = *req; 2881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 2882 "req=%p req->length=%d req->ring=%p rsp=%p " 2883 "rsp->length=%d rsp->ring=%p.\n", 2884 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 2885 (*rsp)->ring); 2886 /* Allocate memory for NVRAM data for vports */ 2887 if (ha->nvram_npiv_size) { 2888 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 2889 ha->nvram_npiv_size, GFP_KERNEL); 2890 if (!ha->npiv_info) { 2891 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 2892 "Failed to allocate memory for npiv_info.\n"); 2893 goto fail_npiv_info; 2894 } 2895 } else 2896 ha->npiv_info = NULL; 2897 2898 /* Get consistent memory allocated for EX-INIT-CB. */ 2899 if (IS_QLA8XXX_TYPE(ha)) { 2900 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2901 &ha->ex_init_cb_dma); 2902 if (!ha->ex_init_cb) 2903 goto fail_ex_init_cb; 2904 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 2905 "ex_init_cb=%p.\n", ha->ex_init_cb); 2906 } 2907 2908 INIT_LIST_HEAD(&ha->gbl_dsd_list); 2909 2910 /* Get consistent memory allocated for Async Port-Database. */ 2911 if (!IS_FWI2_CAPABLE(ha)) { 2912 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 2913 &ha->async_pd_dma); 2914 if (!ha->async_pd) 2915 goto fail_async_pd; 2916 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 2917 "async_pd=%p.\n", ha->async_pd); 2918 } 2919 2920 INIT_LIST_HEAD(&ha->vp_list); 2921 return 1; 2922 2923 fail_async_pd: 2924 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 2925 fail_ex_init_cb: 2926 kfree(ha->npiv_info); 2927 fail_npiv_info: 2928 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 2929 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 2930 (*rsp)->ring = NULL; 2931 (*rsp)->dma = 0; 2932 fail_rsp_ring: 2933 kfree(*rsp); 2934 fail_rsp: 2935 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 2936 sizeof(request_t), (*req)->ring, (*req)->dma); 2937 (*req)->ring = NULL; 2938 (*req)->dma = 0; 2939 fail_req_ring: 2940 kfree(*req); 2941 fail_req: 2942 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 2943 ha->ct_sns, ha->ct_sns_dma); 2944 ha->ct_sns = NULL; 2945 ha->ct_sns_dma = 0; 2946 fail_free_ms_iocb: 2947 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 2948 ha->ms_iocb = NULL; 2949 ha->ms_iocb_dma = 0; 2950 fail_dma_pool: 2951 if (IS_QLA82XX(ha) || ql2xenabledif) { 2952 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 2953 ha->fcp_cmnd_dma_pool = NULL; 2954 } 2955 fail_dl_dma_pool: 2956 if (IS_QLA82XX(ha) || ql2xenabledif) { 2957 dma_pool_destroy(ha->dl_dma_pool); 2958 ha->dl_dma_pool = NULL; 2959 } 2960 fail_s_dma_pool: 2961 dma_pool_destroy(ha->s_dma_pool); 2962 ha->s_dma_pool = NULL; 2963 fail_free_nvram: 2964 kfree(ha->nvram); 2965 ha->nvram = NULL; 2966 fail_free_ctx_mempool: 2967 mempool_destroy(ha->ctx_mempool); 2968 ha->ctx_mempool = NULL; 2969 fail_free_srb_mempool: 2970 mempool_destroy(ha->srb_mempool); 2971 ha->srb_mempool = NULL; 2972 fail_free_gid_list: 2973 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, 2974 ha->gid_list_dma); 2975 ha->gid_list = NULL; 2976 ha->gid_list_dma = 0; 2977 fail_free_init_cb: 2978 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 2979 ha->init_cb_dma); 2980 ha->init_cb = NULL; 2981 ha->init_cb_dma = 0; 2982 fail: 2983 ql_log(ql_log_fatal, NULL, 0x0030, 2984 "Memory allocation failure.\n"); 2985 return -ENOMEM; 2986 } 2987 2988 /* 2989 * qla2x00_free_fw_dump 2990 * Frees fw dump stuff. 2991 * 2992 * Input: 2993 * ha = adapter block pointer. 2994 */ 2995 static void 2996 qla2x00_free_fw_dump(struct qla_hw_data *ha) 2997 { 2998 if (ha->fce) 2999 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 3000 ha->fce_dma); 3001 3002 if (ha->fw_dump) { 3003 if (ha->eft) 3004 dma_free_coherent(&ha->pdev->dev, 3005 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); 3006 vfree(ha->fw_dump); 3007 } 3008 ha->fce = NULL; 3009 ha->fce_dma = 0; 3010 ha->eft = NULL; 3011 ha->eft_dma = 0; 3012 ha->fw_dump = NULL; 3013 ha->fw_dumped = 0; 3014 ha->fw_dump_reading = 0; 3015 } 3016 3017 /* 3018 * qla2x00_mem_free 3019 * Frees all adapter allocated memory. 3020 * 3021 * Input: 3022 * ha = adapter block pointer. 3023 */ 3024 static void 3025 qla2x00_mem_free(struct qla_hw_data *ha) 3026 { 3027 qla2x00_free_fw_dump(ha); 3028 3029 if (ha->srb_mempool) 3030 mempool_destroy(ha->srb_mempool); 3031 3032 if (ha->dcbx_tlv) 3033 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3034 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3035 3036 if (ha->xgmac_data) 3037 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3038 ha->xgmac_data, ha->xgmac_data_dma); 3039 3040 if (ha->sns_cmd) 3041 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3042 ha->sns_cmd, ha->sns_cmd_dma); 3043 3044 if (ha->ct_sns) 3045 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3046 ha->ct_sns, ha->ct_sns_dma); 3047 3048 if (ha->sfp_data) 3049 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3050 3051 if (ha->edc_data) 3052 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma); 3053 3054 if (ha->ms_iocb) 3055 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3056 3057 if (ha->ex_init_cb) 3058 dma_pool_free(ha->s_dma_pool, 3059 ha->ex_init_cb, ha->ex_init_cb_dma); 3060 3061 if (ha->async_pd) 3062 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3063 3064 if (ha->s_dma_pool) 3065 dma_pool_destroy(ha->s_dma_pool); 3066 3067 if (ha->gid_list) 3068 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, 3069 ha->gid_list_dma); 3070 3071 if (IS_QLA82XX(ha)) { 3072 if (!list_empty(&ha->gbl_dsd_list)) { 3073 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3074 3075 /* clean up allocated prev pool */ 3076 list_for_each_entry_safe(dsd_ptr, 3077 tdsd_ptr, &ha->gbl_dsd_list, list) { 3078 dma_pool_free(ha->dl_dma_pool, 3079 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3080 list_del(&dsd_ptr->list); 3081 kfree(dsd_ptr); 3082 } 3083 } 3084 } 3085 3086 if (ha->dl_dma_pool) 3087 dma_pool_destroy(ha->dl_dma_pool); 3088 3089 if (ha->fcp_cmnd_dma_pool) 3090 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3091 3092 if (ha->ctx_mempool) 3093 mempool_destroy(ha->ctx_mempool); 3094 3095 if (ha->init_cb) 3096 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3097 ha->init_cb, ha->init_cb_dma); 3098 vfree(ha->optrom_buffer); 3099 kfree(ha->nvram); 3100 kfree(ha->npiv_info); 3101 3102 ha->srb_mempool = NULL; 3103 ha->ctx_mempool = NULL; 3104 ha->sns_cmd = NULL; 3105 ha->sns_cmd_dma = 0; 3106 ha->ct_sns = NULL; 3107 ha->ct_sns_dma = 0; 3108 ha->ms_iocb = NULL; 3109 ha->ms_iocb_dma = 0; 3110 ha->init_cb = NULL; 3111 ha->init_cb_dma = 0; 3112 ha->ex_init_cb = NULL; 3113 ha->ex_init_cb_dma = 0; 3114 ha->async_pd = NULL; 3115 ha->async_pd_dma = 0; 3116 3117 ha->s_dma_pool = NULL; 3118 ha->dl_dma_pool = NULL; 3119 ha->fcp_cmnd_dma_pool = NULL; 3120 3121 ha->gid_list = NULL; 3122 ha->gid_list_dma = 0; 3123 } 3124 3125 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3126 struct qla_hw_data *ha) 3127 { 3128 struct Scsi_Host *host; 3129 struct scsi_qla_host *vha = NULL; 3130 3131 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3132 if (host == NULL) { 3133 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3134 "Failed to allocate host from the scsi layer, aborting.\n"); 3135 goto fail; 3136 } 3137 3138 /* Clear our data area */ 3139 vha = shost_priv(host); 3140 memset(vha, 0, sizeof(scsi_qla_host_t)); 3141 3142 vha->host = host; 3143 vha->host_no = host->host_no; 3144 vha->hw = ha; 3145 3146 INIT_LIST_HEAD(&vha->vp_fcports); 3147 INIT_LIST_HEAD(&vha->work_list); 3148 INIT_LIST_HEAD(&vha->list); 3149 3150 spin_lock_init(&vha->work_lock); 3151 3152 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3153 ql_dbg(ql_dbg_init, vha, 0x0041, 3154 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3155 vha->host, vha->hw, vha, 3156 dev_name(&(ha->pdev->dev))); 3157 3158 return vha; 3159 3160 fail: 3161 return vha; 3162 } 3163 3164 static struct qla_work_evt * 3165 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3166 { 3167 struct qla_work_evt *e; 3168 uint8_t bail; 3169 3170 QLA_VHA_MARK_BUSY(vha, bail); 3171 if (bail) 3172 return NULL; 3173 3174 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3175 if (!e) { 3176 QLA_VHA_MARK_NOT_BUSY(vha); 3177 return NULL; 3178 } 3179 3180 INIT_LIST_HEAD(&e->list); 3181 e->type = type; 3182 e->flags = QLA_EVT_FLAG_FREE; 3183 return e; 3184 } 3185 3186 static int 3187 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3188 { 3189 unsigned long flags; 3190 3191 spin_lock_irqsave(&vha->work_lock, flags); 3192 list_add_tail(&e->list, &vha->work_list); 3193 spin_unlock_irqrestore(&vha->work_lock, flags); 3194 qla2xxx_wake_dpc(vha); 3195 3196 return QLA_SUCCESS; 3197 } 3198 3199 int 3200 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3201 u32 data) 3202 { 3203 struct qla_work_evt *e; 3204 3205 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3206 if (!e) 3207 return QLA_FUNCTION_FAILED; 3208 3209 e->u.aen.code = code; 3210 e->u.aen.data = data; 3211 return qla2x00_post_work(vha, e); 3212 } 3213 3214 int 3215 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3216 { 3217 struct qla_work_evt *e; 3218 3219 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3220 if (!e) 3221 return QLA_FUNCTION_FAILED; 3222 3223 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3224 return qla2x00_post_work(vha, e); 3225 } 3226 3227 #define qla2x00_post_async_work(name, type) \ 3228 int qla2x00_post_async_##name##_work( \ 3229 struct scsi_qla_host *vha, \ 3230 fc_port_t *fcport, uint16_t *data) \ 3231 { \ 3232 struct qla_work_evt *e; \ 3233 \ 3234 e = qla2x00_alloc_work(vha, type); \ 3235 if (!e) \ 3236 return QLA_FUNCTION_FAILED; \ 3237 \ 3238 e->u.logio.fcport = fcport; \ 3239 if (data) { \ 3240 e->u.logio.data[0] = data[0]; \ 3241 e->u.logio.data[1] = data[1]; \ 3242 } \ 3243 return qla2x00_post_work(vha, e); \ 3244 } 3245 3246 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3247 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3248 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3249 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3250 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3251 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3252 3253 int 3254 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3255 { 3256 struct qla_work_evt *e; 3257 3258 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3259 if (!e) 3260 return QLA_FUNCTION_FAILED; 3261 3262 e->u.uevent.code = code; 3263 return qla2x00_post_work(vha, e); 3264 } 3265 3266 static void 3267 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3268 { 3269 char event_string[40]; 3270 char *envp[] = { event_string, NULL }; 3271 3272 switch (code) { 3273 case QLA_UEVENT_CODE_FW_DUMP: 3274 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3275 vha->host_no); 3276 break; 3277 default: 3278 /* do nothing */ 3279 break; 3280 } 3281 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3282 } 3283 3284 void 3285 qla2x00_do_work(struct scsi_qla_host *vha) 3286 { 3287 struct qla_work_evt *e, *tmp; 3288 unsigned long flags; 3289 LIST_HEAD(work); 3290 3291 spin_lock_irqsave(&vha->work_lock, flags); 3292 list_splice_init(&vha->work_list, &work); 3293 spin_unlock_irqrestore(&vha->work_lock, flags); 3294 3295 list_for_each_entry_safe(e, tmp, &work, list) { 3296 list_del_init(&e->list); 3297 3298 switch (e->type) { 3299 case QLA_EVT_AEN: 3300 fc_host_post_event(vha->host, fc_get_event_number(), 3301 e->u.aen.code, e->u.aen.data); 3302 break; 3303 case QLA_EVT_IDC_ACK: 3304 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3305 break; 3306 case QLA_EVT_ASYNC_LOGIN: 3307 qla2x00_async_login(vha, e->u.logio.fcport, 3308 e->u.logio.data); 3309 break; 3310 case QLA_EVT_ASYNC_LOGIN_DONE: 3311 qla2x00_async_login_done(vha, e->u.logio.fcport, 3312 e->u.logio.data); 3313 break; 3314 case QLA_EVT_ASYNC_LOGOUT: 3315 qla2x00_async_logout(vha, e->u.logio.fcport); 3316 break; 3317 case QLA_EVT_ASYNC_LOGOUT_DONE: 3318 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3319 e->u.logio.data); 3320 break; 3321 case QLA_EVT_ASYNC_ADISC: 3322 qla2x00_async_adisc(vha, e->u.logio.fcport, 3323 e->u.logio.data); 3324 break; 3325 case QLA_EVT_ASYNC_ADISC_DONE: 3326 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3327 e->u.logio.data); 3328 break; 3329 case QLA_EVT_UEVENT: 3330 qla2x00_uevent_emit(vha, e->u.uevent.code); 3331 break; 3332 } 3333 if (e->flags & QLA_EVT_FLAG_FREE) 3334 kfree(e); 3335 3336 /* For each work completed decrement vha ref count */ 3337 QLA_VHA_MARK_NOT_BUSY(vha); 3338 } 3339 } 3340 3341 /* Relogins all the fcports of a vport 3342 * Context: dpc thread 3343 */ 3344 void qla2x00_relogin(struct scsi_qla_host *vha) 3345 { 3346 fc_port_t *fcport; 3347 int status; 3348 uint16_t next_loopid = 0; 3349 struct qla_hw_data *ha = vha->hw; 3350 uint16_t data[2]; 3351 3352 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3353 /* 3354 * If the port is not ONLINE then try to login 3355 * to it if we haven't run out of retries. 3356 */ 3357 if (atomic_read(&fcport->state) != FCS_ONLINE && 3358 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3359 fcport->login_retry--; 3360 if (fcport->flags & FCF_FABRIC_DEVICE) { 3361 if (fcport->flags & FCF_FCP2_DEVICE) 3362 ha->isp_ops->fabric_logout(vha, 3363 fcport->loop_id, 3364 fcport->d_id.b.domain, 3365 fcport->d_id.b.area, 3366 fcport->d_id.b.al_pa); 3367 3368 if (fcport->loop_id == FC_NO_LOOP_ID) { 3369 fcport->loop_id = next_loopid = 3370 ha->min_external_loopid; 3371 status = qla2x00_find_new_loop_id( 3372 vha, fcport); 3373 if (status != QLA_SUCCESS) { 3374 /* Ran out of IDs to use */ 3375 break; 3376 } 3377 } 3378 3379 if (IS_ALOGIO_CAPABLE(ha)) { 3380 fcport->flags |= FCF_ASYNC_SENT; 3381 data[0] = 0; 3382 data[1] = QLA_LOGIO_LOGIN_RETRIED; 3383 status = qla2x00_post_async_login_work( 3384 vha, fcport, data); 3385 if (status == QLA_SUCCESS) 3386 continue; 3387 /* Attempt a retry. */ 3388 status = 1; 3389 } else 3390 status = qla2x00_fabric_login(vha, 3391 fcport, &next_loopid); 3392 } else 3393 status = qla2x00_local_device_login(vha, 3394 fcport); 3395 3396 if (status == QLA_SUCCESS) { 3397 fcport->old_loop_id = fcport->loop_id; 3398 3399 ql_dbg(ql_dbg_disc, vha, 0x2003, 3400 "Port login OK: logged in ID 0x%x.\n", 3401 fcport->loop_id); 3402 3403 qla2x00_update_fcport(vha, fcport); 3404 3405 } else if (status == 1) { 3406 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3407 /* retry the login again */ 3408 ql_dbg(ql_dbg_disc, vha, 0x2007, 3409 "Retrying %d login again loop_id 0x%x.\n", 3410 fcport->login_retry, fcport->loop_id); 3411 } else { 3412 fcport->login_retry = 0; 3413 } 3414 3415 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 3416 fcport->loop_id = FC_NO_LOOP_ID; 3417 } 3418 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3419 break; 3420 } 3421 } 3422 3423 /************************************************************************** 3424 * qla2x00_do_dpc 3425 * This kernel thread is a task that is schedule by the interrupt handler 3426 * to perform the background processing for interrupts. 3427 * 3428 * Notes: 3429 * This task always run in the context of a kernel thread. It 3430 * is kick-off by the driver's detect code and starts up 3431 * up one per adapter. It immediately goes to sleep and waits for 3432 * some fibre event. When either the interrupt handler or 3433 * the timer routine detects a event it will one of the task 3434 * bits then wake us up. 3435 **************************************************************************/ 3436 static int 3437 qla2x00_do_dpc(void *data) 3438 { 3439 int rval; 3440 scsi_qla_host_t *base_vha; 3441 struct qla_hw_data *ha; 3442 3443 ha = (struct qla_hw_data *)data; 3444 base_vha = pci_get_drvdata(ha->pdev); 3445 3446 set_user_nice(current, -20); 3447 3448 set_current_state(TASK_INTERRUPTIBLE); 3449 while (!kthread_should_stop()) { 3450 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 3451 "DPC handler sleeping.\n"); 3452 3453 schedule(); 3454 __set_current_state(TASK_RUNNING); 3455 3456 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 3457 goto end_loop; 3458 3459 if (ha->flags.eeh_busy) { 3460 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 3461 "eeh_busy=%d.\n", ha->flags.eeh_busy); 3462 goto end_loop; 3463 } 3464 3465 ha->dpc_active = 1; 3466 3467 ql_dbg(ql_dbg_dpc, base_vha, 0x4001, 3468 "DPC handler waking up.\n"); 3469 ql_dbg(ql_dbg_dpc, base_vha, 0x4002, 3470 "dpc_flags=0x%lx.\n", base_vha->dpc_flags); 3471 3472 qla2x00_do_work(base_vha); 3473 3474 if (IS_QLA82XX(ha)) { 3475 if (test_and_clear_bit(ISP_UNRECOVERABLE, 3476 &base_vha->dpc_flags)) { 3477 qla82xx_idc_lock(ha); 3478 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3479 QLA82XX_DEV_FAILED); 3480 qla82xx_idc_unlock(ha); 3481 ql_log(ql_log_info, base_vha, 0x4004, 3482 "HW State: FAILED.\n"); 3483 qla82xx_device_state_handler(base_vha); 3484 continue; 3485 } 3486 3487 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 3488 &base_vha->dpc_flags)) { 3489 3490 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 3491 "FCoE context reset scheduled.\n"); 3492 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3493 &base_vha->dpc_flags))) { 3494 if (qla82xx_fcoe_ctx_reset(base_vha)) { 3495 /* FCoE-ctx reset failed. 3496 * Escalate to chip-reset 3497 */ 3498 set_bit(ISP_ABORT_NEEDED, 3499 &base_vha->dpc_flags); 3500 } 3501 clear_bit(ABORT_ISP_ACTIVE, 3502 &base_vha->dpc_flags); 3503 } 3504 3505 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 3506 "FCoE context reset end.\n"); 3507 } 3508 } 3509 3510 if (test_and_clear_bit(ISP_ABORT_NEEDED, 3511 &base_vha->dpc_flags)) { 3512 3513 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 3514 "ISP abort scheduled.\n"); 3515 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3516 &base_vha->dpc_flags))) { 3517 3518 if (ha->isp_ops->abort_isp(base_vha)) { 3519 /* failed. retry later */ 3520 set_bit(ISP_ABORT_NEEDED, 3521 &base_vha->dpc_flags); 3522 } 3523 clear_bit(ABORT_ISP_ACTIVE, 3524 &base_vha->dpc_flags); 3525 } 3526 3527 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 3528 "ISP abort end.\n"); 3529 } 3530 3531 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { 3532 qla2x00_update_fcports(base_vha); 3533 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3534 } 3535 3536 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 3537 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 3538 "Quiescence mode scheduled.\n"); 3539 qla82xx_device_state_handler(base_vha); 3540 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); 3541 if (!ha->flags.quiesce_owner) { 3542 qla2x00_perform_loop_resync(base_vha); 3543 3544 qla82xx_idc_lock(ha); 3545 qla82xx_clear_qsnt_ready(base_vha); 3546 qla82xx_idc_unlock(ha); 3547 } 3548 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 3549 "Quiescence mode end.\n"); 3550 } 3551 3552 if (test_and_clear_bit(RESET_MARKER_NEEDED, 3553 &base_vha->dpc_flags) && 3554 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 3555 3556 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 3557 "Reset marker scheduled.\n"); 3558 qla2x00_rst_aen(base_vha); 3559 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 3560 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 3561 "Reset marker end.\n"); 3562 } 3563 3564 /* Retry each device up to login retry count */ 3565 if ((test_and_clear_bit(RELOGIN_NEEDED, 3566 &base_vha->dpc_flags)) && 3567 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 3568 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 3569 3570 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 3571 "Relogin scheduled.\n"); 3572 qla2x00_relogin(base_vha); 3573 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 3574 "Relogin end.\n"); 3575 } 3576 3577 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 3578 &base_vha->dpc_flags)) { 3579 3580 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 3581 "Loop resync scheduled.\n"); 3582 3583 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 3584 &base_vha->dpc_flags))) { 3585 3586 rval = qla2x00_loop_resync(base_vha); 3587 3588 clear_bit(LOOP_RESYNC_ACTIVE, 3589 &base_vha->dpc_flags); 3590 } 3591 3592 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 3593 "Loop resync end.\n"); 3594 } 3595 3596 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 3597 atomic_read(&base_vha->loop_state) == LOOP_READY) { 3598 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 3599 qla2xxx_flash_npiv_conf(base_vha); 3600 } 3601 3602 if (!ha->interrupts_on) 3603 ha->isp_ops->enable_intrs(ha); 3604 3605 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 3606 &base_vha->dpc_flags)) 3607 ha->isp_ops->beacon_blink(base_vha); 3608 3609 qla2x00_do_dpc_all_vps(base_vha); 3610 3611 ha->dpc_active = 0; 3612 end_loop: 3613 set_current_state(TASK_INTERRUPTIBLE); 3614 } /* End of while(1) */ 3615 __set_current_state(TASK_RUNNING); 3616 3617 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 3618 "DPC handler exiting.\n"); 3619 3620 /* 3621 * Make sure that nobody tries to wake us up again. 3622 */ 3623 ha->dpc_active = 0; 3624 3625 /* Cleanup any residual CTX SRBs. */ 3626 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3627 3628 return 0; 3629 } 3630 3631 void 3632 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 3633 { 3634 struct qla_hw_data *ha = vha->hw; 3635 struct task_struct *t = ha->dpc_thread; 3636 3637 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 3638 wake_up_process(t); 3639 } 3640 3641 /* 3642 * qla2x00_rst_aen 3643 * Processes asynchronous reset. 3644 * 3645 * Input: 3646 * ha = adapter block pointer. 3647 */ 3648 static void 3649 qla2x00_rst_aen(scsi_qla_host_t *vha) 3650 { 3651 if (vha->flags.online && !vha->flags.reset_active && 3652 !atomic_read(&vha->loop_down_timer) && 3653 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 3654 do { 3655 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 3656 3657 /* 3658 * Issue marker command only when we are going to start 3659 * the I/O. 3660 */ 3661 vha->marker_needed = 1; 3662 } while (!atomic_read(&vha->loop_down_timer) && 3663 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 3664 } 3665 } 3666 3667 static void 3668 qla2x00_sp_free_dma(srb_t *sp) 3669 { 3670 struct scsi_cmnd *cmd = sp->cmd; 3671 struct qla_hw_data *ha = sp->fcport->vha->hw; 3672 3673 if (sp->flags & SRB_DMA_VALID) { 3674 scsi_dma_unmap(cmd); 3675 sp->flags &= ~SRB_DMA_VALID; 3676 } 3677 3678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 3679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 3680 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 3681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 3682 } 3683 3684 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 3685 /* List assured to be having elements */ 3686 qla2x00_clean_dsd_pool(ha, sp); 3687 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 3688 } 3689 3690 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 3691 dma_pool_free(ha->dl_dma_pool, sp->ctx, 3692 ((struct crc_context *)sp->ctx)->crc_ctx_dma); 3693 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 3694 } 3695 3696 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 3697 struct ct6_dsd *ctx = sp->ctx; 3698 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, 3699 ctx->fcp_cmnd_dma); 3700 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list); 3701 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt; 3702 ha->gbl_dsd_avail += ctx->dsd_use_cnt; 3703 mempool_free(sp->ctx, ha->ctx_mempool); 3704 sp->ctx = NULL; 3705 } 3706 3707 CMD_SP(cmd) = NULL; 3708 } 3709 3710 static void 3711 qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp) 3712 { 3713 struct scsi_cmnd *cmd = sp->cmd; 3714 3715 qla2x00_sp_free_dma(sp); 3716 mempool_free(sp, ha->srb_mempool); 3717 cmd->scsi_done(cmd); 3718 } 3719 3720 void 3721 qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp) 3722 { 3723 if (atomic_read(&sp->ref_count) == 0) { 3724 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 3725 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 3726 sp, sp->cmd); 3727 if (ql2xextended_error_logging & ql_dbg_io) 3728 BUG(); 3729 return; 3730 } 3731 if (!atomic_dec_and_test(&sp->ref_count)) 3732 return; 3733 qla2x00_sp_final_compl(ha, sp); 3734 } 3735 3736 /************************************************************************** 3737 * qla2x00_timer 3738 * 3739 * Description: 3740 * One second timer 3741 * 3742 * Context: Interrupt 3743 ***************************************************************************/ 3744 void 3745 qla2x00_timer(scsi_qla_host_t *vha) 3746 { 3747 unsigned long cpu_flags = 0; 3748 int start_dpc = 0; 3749 int index; 3750 srb_t *sp; 3751 uint16_t w; 3752 struct qla_hw_data *ha = vha->hw; 3753 struct req_que *req; 3754 3755 if (ha->flags.eeh_busy) { 3756 ql_dbg(ql_dbg_timer, vha, 0x6000, 3757 "EEH = %d, restarting timer.\n", 3758 ha->flags.eeh_busy); 3759 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3760 return; 3761 } 3762 3763 /* Hardware read to raise pending EEH errors during mailbox waits. */ 3764 if (!pci_channel_offline(ha->pdev)) 3765 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 3766 3767 /* Make sure qla82xx_watchdog is run only for physical port */ 3768 if (!vha->vp_idx && IS_QLA82XX(ha)) { 3769 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 3770 start_dpc++; 3771 qla82xx_watchdog(vha); 3772 } 3773 3774 /* Loop down handler. */ 3775 if (atomic_read(&vha->loop_down_timer) > 0 && 3776 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 3777 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 3778 && vha->flags.online) { 3779 3780 if (atomic_read(&vha->loop_down_timer) == 3781 vha->loop_down_abort_time) { 3782 3783 ql_log(ql_log_info, vha, 0x6008, 3784 "Loop down - aborting the queues before time expires.\n"); 3785 3786 if (!IS_QLA2100(ha) && vha->link_down_timeout) 3787 atomic_set(&vha->loop_state, LOOP_DEAD); 3788 3789 /* 3790 * Schedule an ISP abort to return any FCP2-device 3791 * commands. 3792 */ 3793 /* NPIV - scan physical port only */ 3794 if (!vha->vp_idx) { 3795 spin_lock_irqsave(&ha->hardware_lock, 3796 cpu_flags); 3797 req = ha->req_q_map[0]; 3798 for (index = 1; 3799 index < MAX_OUTSTANDING_COMMANDS; 3800 index++) { 3801 fc_port_t *sfcp; 3802 3803 sp = req->outstanding_cmds[index]; 3804 if (!sp) 3805 continue; 3806 if (sp->ctx && !IS_PROT_IO(sp)) 3807 continue; 3808 sfcp = sp->fcport; 3809 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 3810 continue; 3811 3812 if (IS_QLA82XX(ha)) 3813 set_bit(FCOE_CTX_RESET_NEEDED, 3814 &vha->dpc_flags); 3815 else 3816 set_bit(ISP_ABORT_NEEDED, 3817 &vha->dpc_flags); 3818 break; 3819 } 3820 spin_unlock_irqrestore(&ha->hardware_lock, 3821 cpu_flags); 3822 } 3823 start_dpc++; 3824 } 3825 3826 /* if the loop has been down for 4 minutes, reinit adapter */ 3827 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 3828 if (!(vha->device_flags & DFLG_NO_CABLE)) { 3829 ql_log(ql_log_warn, vha, 0x6009, 3830 "Loop down - aborting ISP.\n"); 3831 3832 if (IS_QLA82XX(ha)) 3833 set_bit(FCOE_CTX_RESET_NEEDED, 3834 &vha->dpc_flags); 3835 else 3836 set_bit(ISP_ABORT_NEEDED, 3837 &vha->dpc_flags); 3838 } 3839 } 3840 ql_dbg(ql_dbg_timer, vha, 0x600a, 3841 "Loop down - seconds remaining %d.\n", 3842 atomic_read(&vha->loop_down_timer)); 3843 } 3844 3845 /* Check if beacon LED needs to be blinked for physical host only */ 3846 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 3847 /* There is no beacon_blink function for ISP82xx */ 3848 if (!IS_QLA82XX(ha)) { 3849 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 3850 start_dpc++; 3851 } 3852 } 3853 3854 /* Process any deferred work. */ 3855 if (!list_empty(&vha->work_list)) 3856 start_dpc++; 3857 3858 /* Schedule the DPC routine if needed */ 3859 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 3860 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 3861 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 3862 start_dpc || 3863 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 3864 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 3865 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 3866 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3867 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 3868 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 3869 ql_dbg(ql_dbg_timer, vha, 0x600b, 3870 "isp_abort_needed=%d loop_resync_needed=%d " 3871 "fcport_update_needed=%d start_dpc=%d " 3872 "reset_marker_needed=%d", 3873 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 3874 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 3875 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 3876 start_dpc, 3877 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 3878 ql_dbg(ql_dbg_timer, vha, 0x600c, 3879 "beacon_blink_needed=%d isp_unrecoverable=%d " 3880 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 3881 "relogin_needed=%d.\n", 3882 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 3883 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 3884 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 3885 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 3886 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 3887 qla2xxx_wake_dpc(vha); 3888 } 3889 3890 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3891 } 3892 3893 /* Firmware interface routines. */ 3894 3895 #define FW_BLOBS 8 3896 #define FW_ISP21XX 0 3897 #define FW_ISP22XX 1 3898 #define FW_ISP2300 2 3899 #define FW_ISP2322 3 3900 #define FW_ISP24XX 4 3901 #define FW_ISP25XX 5 3902 #define FW_ISP81XX 6 3903 #define FW_ISP82XX 7 3904 3905 #define FW_FILE_ISP21XX "ql2100_fw.bin" 3906 #define FW_FILE_ISP22XX "ql2200_fw.bin" 3907 #define FW_FILE_ISP2300 "ql2300_fw.bin" 3908 #define FW_FILE_ISP2322 "ql2322_fw.bin" 3909 #define FW_FILE_ISP24XX "ql2400_fw.bin" 3910 #define FW_FILE_ISP25XX "ql2500_fw.bin" 3911 #define FW_FILE_ISP81XX "ql8100_fw.bin" 3912 #define FW_FILE_ISP82XX "ql8200_fw.bin" 3913 3914 static DEFINE_MUTEX(qla_fw_lock); 3915 3916 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 3917 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 3918 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 3919 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 3920 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 3921 { .name = FW_FILE_ISP24XX, }, 3922 { .name = FW_FILE_ISP25XX, }, 3923 { .name = FW_FILE_ISP81XX, }, 3924 { .name = FW_FILE_ISP82XX, }, 3925 }; 3926 3927 struct fw_blob * 3928 qla2x00_request_firmware(scsi_qla_host_t *vha) 3929 { 3930 struct qla_hw_data *ha = vha->hw; 3931 struct fw_blob *blob; 3932 3933 blob = NULL; 3934 if (IS_QLA2100(ha)) { 3935 blob = &qla_fw_blobs[FW_ISP21XX]; 3936 } else if (IS_QLA2200(ha)) { 3937 blob = &qla_fw_blobs[FW_ISP22XX]; 3938 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 3939 blob = &qla_fw_blobs[FW_ISP2300]; 3940 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 3941 blob = &qla_fw_blobs[FW_ISP2322]; 3942 } else if (IS_QLA24XX_TYPE(ha)) { 3943 blob = &qla_fw_blobs[FW_ISP24XX]; 3944 } else if (IS_QLA25XX(ha)) { 3945 blob = &qla_fw_blobs[FW_ISP25XX]; 3946 } else if (IS_QLA81XX(ha)) { 3947 blob = &qla_fw_blobs[FW_ISP81XX]; 3948 } else if (IS_QLA82XX(ha)) { 3949 blob = &qla_fw_blobs[FW_ISP82XX]; 3950 } 3951 3952 mutex_lock(&qla_fw_lock); 3953 if (blob->fw) 3954 goto out; 3955 3956 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 3957 ql_log(ql_log_warn, vha, 0x0063, 3958 "Failed to load firmware image (%s).\n", blob->name); 3959 blob->fw = NULL; 3960 blob = NULL; 3961 goto out; 3962 } 3963 3964 out: 3965 mutex_unlock(&qla_fw_lock); 3966 return blob; 3967 } 3968 3969 static void 3970 qla2x00_release_firmware(void) 3971 { 3972 int idx; 3973 3974 mutex_lock(&qla_fw_lock); 3975 for (idx = 0; idx < FW_BLOBS; idx++) 3976 if (qla_fw_blobs[idx].fw) 3977 release_firmware(qla_fw_blobs[idx].fw); 3978 mutex_unlock(&qla_fw_lock); 3979 } 3980 3981 static pci_ers_result_t 3982 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 3983 { 3984 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 3985 struct qla_hw_data *ha = vha->hw; 3986 3987 ql_dbg(ql_dbg_aer, vha, 0x9000, 3988 "PCI error detected, state %x.\n", state); 3989 3990 switch (state) { 3991 case pci_channel_io_normal: 3992 ha->flags.eeh_busy = 0; 3993 return PCI_ERS_RESULT_CAN_RECOVER; 3994 case pci_channel_io_frozen: 3995 ha->flags.eeh_busy = 1; 3996 /* For ISP82XX complete any pending mailbox cmd */ 3997 if (IS_QLA82XX(ha)) { 3998 ha->flags.isp82xx_fw_hung = 1; 3999 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 4000 qla82xx_clear_pending_mbx(vha); 4001 } 4002 qla2x00_free_irqs(vha); 4003 pci_disable_device(pdev); 4004 /* Return back all IOs */ 4005 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4006 return PCI_ERS_RESULT_NEED_RESET; 4007 case pci_channel_io_perm_failure: 4008 ha->flags.pci_channel_io_perm_failure = 1; 4009 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4010 return PCI_ERS_RESULT_DISCONNECT; 4011 } 4012 return PCI_ERS_RESULT_NEED_RESET; 4013 } 4014 4015 static pci_ers_result_t 4016 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 4017 { 4018 int risc_paused = 0; 4019 uint32_t stat; 4020 unsigned long flags; 4021 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4022 struct qla_hw_data *ha = base_vha->hw; 4023 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4024 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 4025 4026 if (IS_QLA82XX(ha)) 4027 return PCI_ERS_RESULT_RECOVERED; 4028 4029 spin_lock_irqsave(&ha->hardware_lock, flags); 4030 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 4031 stat = RD_REG_DWORD(®->hccr); 4032 if (stat & HCCR_RISC_PAUSE) 4033 risc_paused = 1; 4034 } else if (IS_QLA23XX(ha)) { 4035 stat = RD_REG_DWORD(®->u.isp2300.host_status); 4036 if (stat & HSR_RISC_PAUSED) 4037 risc_paused = 1; 4038 } else if (IS_FWI2_CAPABLE(ha)) { 4039 stat = RD_REG_DWORD(®24->host_status); 4040 if (stat & HSRX_RISC_PAUSED) 4041 risc_paused = 1; 4042 } 4043 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4044 4045 if (risc_paused) { 4046 ql_log(ql_log_info, base_vha, 0x9003, 4047 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 4048 ha->isp_ops->fw_dump(base_vha, 0); 4049 4050 return PCI_ERS_RESULT_NEED_RESET; 4051 } else 4052 return PCI_ERS_RESULT_RECOVERED; 4053 } 4054 4055 uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) 4056 { 4057 uint32_t rval = QLA_FUNCTION_FAILED; 4058 uint32_t drv_active = 0; 4059 struct qla_hw_data *ha = base_vha->hw; 4060 int fn; 4061 struct pci_dev *other_pdev = NULL; 4062 4063 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 4064 "Entered %s.\n", __func__); 4065 4066 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4067 4068 if (base_vha->flags.online) { 4069 /* Abort all outstanding commands, 4070 * so as to be requeued later */ 4071 qla2x00_abort_isp_cleanup(base_vha); 4072 } 4073 4074 4075 fn = PCI_FUNC(ha->pdev->devfn); 4076 while (fn > 0) { 4077 fn--; 4078 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 4079 "Finding pci device at function = 0x%x.\n", fn); 4080 other_pdev = 4081 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 4082 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 4083 fn)); 4084 4085 if (!other_pdev) 4086 continue; 4087 if (atomic_read(&other_pdev->enable_cnt)) { 4088 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 4089 "Found PCI func available and enable at 0x%x.\n", 4090 fn); 4091 pci_dev_put(other_pdev); 4092 break; 4093 } 4094 pci_dev_put(other_pdev); 4095 } 4096 4097 if (!fn) { 4098 /* Reset owner */ 4099 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 4100 "This devfn is reset owner = 0x%x.\n", 4101 ha->pdev->devfn); 4102 qla82xx_idc_lock(ha); 4103 4104 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4105 QLA82XX_DEV_INITIALIZING); 4106 4107 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 4108 QLA82XX_IDC_VERSION); 4109 4110 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 4111 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 4112 "drv_active = 0x%x.\n", drv_active); 4113 4114 qla82xx_idc_unlock(ha); 4115 /* Reset if device is not already reset 4116 * drv_active would be 0 if a reset has already been done 4117 */ 4118 if (drv_active) 4119 rval = qla82xx_start_firmware(base_vha); 4120 else 4121 rval = QLA_SUCCESS; 4122 qla82xx_idc_lock(ha); 4123 4124 if (rval != QLA_SUCCESS) { 4125 ql_log(ql_log_info, base_vha, 0x900b, 4126 "HW State: FAILED.\n"); 4127 qla82xx_clear_drv_active(ha); 4128 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4129 QLA82XX_DEV_FAILED); 4130 } else { 4131 ql_log(ql_log_info, base_vha, 0x900c, 4132 "HW State: READY.\n"); 4133 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4134 QLA82XX_DEV_READY); 4135 qla82xx_idc_unlock(ha); 4136 ha->flags.isp82xx_fw_hung = 0; 4137 rval = qla82xx_restart_isp(base_vha); 4138 qla82xx_idc_lock(ha); 4139 /* Clear driver state register */ 4140 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 4141 qla82xx_set_drv_active(base_vha); 4142 } 4143 qla82xx_idc_unlock(ha); 4144 } else { 4145 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 4146 "This devfn is not reset owner = 0x%x.\n", 4147 ha->pdev->devfn); 4148 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 4149 QLA82XX_DEV_READY)) { 4150 ha->flags.isp82xx_fw_hung = 0; 4151 rval = qla82xx_restart_isp(base_vha); 4152 qla82xx_idc_lock(ha); 4153 qla82xx_set_drv_active(base_vha); 4154 qla82xx_idc_unlock(ha); 4155 } 4156 } 4157 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4158 4159 return rval; 4160 } 4161 4162 static pci_ers_result_t 4163 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 4164 { 4165 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 4166 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4167 struct qla_hw_data *ha = base_vha->hw; 4168 struct rsp_que *rsp; 4169 int rc, retries = 10; 4170 4171 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 4172 "Slot Reset.\n"); 4173 4174 /* Workaround: qla2xxx driver which access hardware earlier 4175 * needs error state to be pci_channel_io_online. 4176 * Otherwise mailbox command timesout. 4177 */ 4178 pdev->error_state = pci_channel_io_normal; 4179 4180 pci_restore_state(pdev); 4181 4182 /* pci_restore_state() clears the saved_state flag of the device 4183 * save restored state which resets saved_state flag 4184 */ 4185 pci_save_state(pdev); 4186 4187 if (ha->mem_only) 4188 rc = pci_enable_device_mem(pdev); 4189 else 4190 rc = pci_enable_device(pdev); 4191 4192 if (rc) { 4193 ql_log(ql_log_warn, base_vha, 0x9005, 4194 "Can't re-enable PCI device after reset.\n"); 4195 goto exit_slot_reset; 4196 } 4197 4198 rsp = ha->rsp_q_map[0]; 4199 if (qla2x00_request_irqs(ha, rsp)) 4200 goto exit_slot_reset; 4201 4202 if (ha->isp_ops->pci_config(base_vha)) 4203 goto exit_slot_reset; 4204 4205 if (IS_QLA82XX(ha)) { 4206 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 4207 ret = PCI_ERS_RESULT_RECOVERED; 4208 goto exit_slot_reset; 4209 } else 4210 goto exit_slot_reset; 4211 } 4212 4213 while (ha->flags.mbox_busy && retries--) 4214 msleep(1000); 4215 4216 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4217 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 4218 ret = PCI_ERS_RESULT_RECOVERED; 4219 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4220 4221 4222 exit_slot_reset: 4223 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 4224 "slot_reset return %x.\n", ret); 4225 4226 return ret; 4227 } 4228 4229 static void 4230 qla2xxx_pci_resume(struct pci_dev *pdev) 4231 { 4232 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4233 struct qla_hw_data *ha = base_vha->hw; 4234 int ret; 4235 4236 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 4237 "pci_resume.\n"); 4238 4239 ret = qla2x00_wait_for_hba_online(base_vha); 4240 if (ret != QLA_SUCCESS) { 4241 ql_log(ql_log_fatal, base_vha, 0x9002, 4242 "The device failed to resume I/O from slot/link_reset.\n"); 4243 } 4244 4245 pci_cleanup_aer_uncorrect_error_status(pdev); 4246 4247 ha->flags.eeh_busy = 0; 4248 } 4249 4250 static struct pci_error_handlers qla2xxx_err_handler = { 4251 .error_detected = qla2xxx_pci_error_detected, 4252 .mmio_enabled = qla2xxx_pci_mmio_enabled, 4253 .slot_reset = qla2xxx_pci_slot_reset, 4254 .resume = qla2xxx_pci_resume, 4255 }; 4256 4257 static struct pci_device_id qla2xxx_pci_tbl[] = { 4258 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 4259 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 4260 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 4261 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 4262 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 4263 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 4264 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 4265 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 4266 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 4267 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 4268 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 4269 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 4270 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 4271 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 4272 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 4273 { 0 }, 4274 }; 4275 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 4276 4277 static struct pci_driver qla2xxx_pci_driver = { 4278 .name = QLA2XXX_DRIVER_NAME, 4279 .driver = { 4280 .owner = THIS_MODULE, 4281 }, 4282 .id_table = qla2xxx_pci_tbl, 4283 .probe = qla2x00_probe_one, 4284 .remove = qla2x00_remove_one, 4285 .shutdown = qla2x00_shutdown, 4286 .err_handler = &qla2xxx_err_handler, 4287 }; 4288 4289 static struct file_operations apidev_fops = { 4290 .owner = THIS_MODULE, 4291 .llseek = noop_llseek, 4292 }; 4293 4294 /** 4295 * qla2x00_module_init - Module initialization. 4296 **/ 4297 static int __init 4298 qla2x00_module_init(void) 4299 { 4300 int ret = 0; 4301 4302 /* Allocate cache for SRBs. */ 4303 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 4304 SLAB_HWCACHE_ALIGN, NULL); 4305 if (srb_cachep == NULL) { 4306 ql_log(ql_log_fatal, NULL, 0x0001, 4307 "Unable to allocate SRB cache...Failing load!.\n"); 4308 return -ENOMEM; 4309 } 4310 4311 /* Derive version string. */ 4312 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 4313 if (ql2xextended_error_logging) 4314 strcat(qla2x00_version_str, "-debug"); 4315 4316 qla2xxx_transport_template = 4317 fc_attach_transport(&qla2xxx_transport_functions); 4318 if (!qla2xxx_transport_template) { 4319 kmem_cache_destroy(srb_cachep); 4320 ql_log(ql_log_fatal, NULL, 0x0002, 4321 "fc_attach_transport failed...Failing load!.\n"); 4322 return -ENODEV; 4323 } 4324 4325 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 4326 if (apidev_major < 0) { 4327 ql_log(ql_log_fatal, NULL, 0x0003, 4328 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 4329 } 4330 4331 qla2xxx_transport_vport_template = 4332 fc_attach_transport(&qla2xxx_transport_vport_functions); 4333 if (!qla2xxx_transport_vport_template) { 4334 kmem_cache_destroy(srb_cachep); 4335 fc_release_transport(qla2xxx_transport_template); 4336 ql_log(ql_log_fatal, NULL, 0x0004, 4337 "fc_attach_transport vport failed...Failing load!.\n"); 4338 return -ENODEV; 4339 } 4340 ql_log(ql_log_info, NULL, 0x0005, 4341 "QLogic Fibre Channel HBA Driver: %s.\n", 4342 qla2x00_version_str); 4343 ret = pci_register_driver(&qla2xxx_pci_driver); 4344 if (ret) { 4345 kmem_cache_destroy(srb_cachep); 4346 fc_release_transport(qla2xxx_transport_template); 4347 fc_release_transport(qla2xxx_transport_vport_template); 4348 ql_log(ql_log_fatal, NULL, 0x0006, 4349 "pci_register_driver failed...ret=%d Failing load!.\n", 4350 ret); 4351 } 4352 return ret; 4353 } 4354 4355 /** 4356 * qla2x00_module_exit - Module cleanup. 4357 **/ 4358 static void __exit 4359 qla2x00_module_exit(void) 4360 { 4361 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 4362 pci_unregister_driver(&qla2xxx_pci_driver); 4363 qla2x00_release_firmware(); 4364 kmem_cache_destroy(srb_cachep); 4365 if (ctx_cachep) 4366 kmem_cache_destroy(ctx_cachep); 4367 fc_release_transport(qla2xxx_transport_template); 4368 fc_release_transport(qla2xxx_transport_vport_template); 4369 } 4370 4371 module_init(qla2x00_module_init); 4372 module_exit(qla2x00_module_exit); 4373 4374 MODULE_AUTHOR("QLogic Corporation"); 4375 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 4376 MODULE_LICENSE("GPL"); 4377 MODULE_VERSION(QLA2XXX_VERSION); 4378 MODULE_FIRMWARE(FW_FILE_ISP21XX); 4379 MODULE_FIRMWARE(FW_FILE_ISP22XX); 4380 MODULE_FIRMWARE(FW_FILE_ISP2300); 4381 MODULE_FIRMWARE(FW_FILE_ISP2322); 4382 MODULE_FIRMWARE(FW_FILE_ISP24XX); 4383 MODULE_FIRMWARE(FW_FILE_ISP25XX); 4384