1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 int ql2xlogintimeout = 20; 51 module_param(ql2xlogintimeout, int, S_IRUGO); 52 MODULE_PARM_DESC(ql2xlogintimeout, 53 "Login timeout value in seconds."); 54 55 int qlport_down_retry; 56 module_param(qlport_down_retry, int, S_IRUGO); 57 MODULE_PARM_DESC(qlport_down_retry, 58 "Maximum number of command retries to a port that returns " 59 "a PORT-DOWN status."); 60 61 int ql2xplogiabsentdevice; 62 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 63 MODULE_PARM_DESC(ql2xplogiabsentdevice, 64 "Option to enable PLOGI to devices that are not present after " 65 "a Fabric scan. This is needed for several broken switches. " 66 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 67 68 int ql2xloginretrycount = 0; 69 module_param(ql2xloginretrycount, int, S_IRUGO); 70 MODULE_PARM_DESC(ql2xloginretrycount, 71 "Specify an alternate value for the NVRAM login retry count."); 72 73 int ql2xallocfwdump = 1; 74 module_param(ql2xallocfwdump, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xallocfwdump, 76 "Option to enable allocation of memory for a firmware dump " 77 "during HBA initialization. Memory allocation requirements " 78 "vary by ISP type. Default is 1 - allocate memory."); 79 80 int ql2xextended_error_logging; 81 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(ql2xextended_error_logging, 83 "Option to enable extended error logging,\n" 84 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 85 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 86 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 87 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 88 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 89 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 90 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 91 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 92 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 93 "\t\t0x1e400000 - Preferred value for capturing essential " 94 "debug information (equivalent to old " 95 "ql2xextended_error_logging=1).\n" 96 "\t\tDo LOGICAL OR of the value to enable more than one level"); 97 98 int ql2xshiftctondsd = 6; 99 module_param(ql2xshiftctondsd, int, S_IRUGO); 100 MODULE_PARM_DESC(ql2xshiftctondsd, 101 "Set to control shifting of command type processing " 102 "based on total number of SG elements."); 103 104 static void qla2x00_free_device(scsi_qla_host_t *); 105 106 int ql2xfdmienable=1; 107 module_param(ql2xfdmienable, int, S_IRUGO); 108 MODULE_PARM_DESC(ql2xfdmienable, 109 "Enables FDMI registrations. " 110 "0 - no FDMI. Default is 1 - perform FDMI."); 111 112 #define MAX_Q_DEPTH 32 113 static int ql2xmaxqdepth = MAX_Q_DEPTH; 114 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 115 MODULE_PARM_DESC(ql2xmaxqdepth, 116 "Maximum queue depth to report for target devices."); 117 118 /* Do not change the value of this after module load */ 119 int ql2xenabledif = 0; 120 module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xenabledif, 122 " Enable T10-CRC-DIF " 123 " Default is 0 - No DIF Support. 1 - Enable it" 124 ", 2 - Enable DIF for all types, except Type 0."); 125 126 int ql2xenablehba_err_chk = 2; 127 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 128 MODULE_PARM_DESC(ql2xenablehba_err_chk, 129 " Enable T10-CRC-DIF Error isolation by HBA:\n" 130 " Default is 1.\n" 131 " 0 -- Error isolation disabled\n" 132 " 1 -- Error isolation enabled only for DIX Type 0\n" 133 " 2 -- Error isolation enabled for all Types\n"); 134 135 int ql2xiidmaenable=1; 136 module_param(ql2xiidmaenable, int, S_IRUGO); 137 MODULE_PARM_DESC(ql2xiidmaenable, 138 "Enables iIDMA settings " 139 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 140 141 int ql2xmaxqueues = 1; 142 module_param(ql2xmaxqueues, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xmaxqueues, 144 "Enables MQ settings " 145 "Default is 1 for single queue. Set it to number " 146 "of queues in MQ mode."); 147 148 int ql2xmultique_tag; 149 module_param(ql2xmultique_tag, int, S_IRUGO); 150 MODULE_PARM_DESC(ql2xmultique_tag, 151 "Enables CPU affinity settings for the driver " 152 "Default is 0 for no affinity of request and response IO. " 153 "Set it to 1 to turn on the cpu affinity."); 154 155 int ql2xfwloadbin; 156 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 157 MODULE_PARM_DESC(ql2xfwloadbin, 158 "Option to specify location from which to load ISP firmware:.\n" 159 " 2 -- load firmware via the request_firmware() (hotplug).\n" 160 " interface.\n" 161 " 1 -- load firmware from flash.\n" 162 " 0 -- use default semantics.\n"); 163 164 int ql2xetsenable; 165 module_param(ql2xetsenable, int, S_IRUGO); 166 MODULE_PARM_DESC(ql2xetsenable, 167 "Enables firmware ETS burst." 168 "Default is 0 - skip ETS enablement."); 169 170 int ql2xdbwr = 1; 171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xdbwr, 173 "Option to specify scheme for request queue posting.\n" 174 " 0 -- Regular doorbell.\n" 175 " 1 -- CAMRAM doorbell (faster).\n"); 176 177 int ql2xtargetreset = 1; 178 module_param(ql2xtargetreset, int, S_IRUGO); 179 MODULE_PARM_DESC(ql2xtargetreset, 180 "Enable target reset." 181 "Default is 1 - use hw defaults."); 182 183 int ql2xgffidenable; 184 module_param(ql2xgffidenable, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xgffidenable, 186 "Enables GFF_ID checks of port type. " 187 "Default is 0 - Do not use GFF_ID information."); 188 189 int ql2xasynctmfenable; 190 module_param(ql2xasynctmfenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xasynctmfenable, 192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 193 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 194 195 int ql2xdontresethba; 196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 197 MODULE_PARM_DESC(ql2xdontresethba, 198 "Option to specify reset behaviour.\n" 199 " 0 (Default) -- Reset on failure.\n" 200 " 1 -- Do not reset on failure.\n"); 201 202 uint ql2xmaxlun = MAX_LUNS; 203 module_param(ql2xmaxlun, uint, S_IRUGO); 204 MODULE_PARM_DESC(ql2xmaxlun, 205 "Defines the maximum LU number to register with the SCSI " 206 "midlayer. Default is 65535."); 207 208 int ql2xmdcapmask = 0x1F; 209 module_param(ql2xmdcapmask, int, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmdcapmask, 211 "Set the Minidump driver capture mask level. " 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 213 214 int ql2xmdenable = 1; 215 module_param(ql2xmdenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdenable, 217 "Enable/disable MiniDump. " 218 "0 - MiniDump disabled. " 219 "1 (Default) - MiniDump enabled."); 220 221 /* 222 * SCSI host template entry points 223 */ 224 static int qla2xxx_slave_configure(struct scsi_device * device); 225 static int qla2xxx_slave_alloc(struct scsi_device *); 226 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 227 static void qla2xxx_scan_start(struct Scsi_Host *); 228 static void qla2xxx_slave_destroy(struct scsi_device *); 229 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 230 static int qla2xxx_eh_abort(struct scsi_cmnd *); 231 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 232 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 233 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 234 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 235 236 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 237 static int qla2x00_change_queue_type(struct scsi_device *, int); 238 239 struct scsi_host_template qla2xxx_driver_template = { 240 .module = THIS_MODULE, 241 .name = QLA2XXX_DRIVER_NAME, 242 .queuecommand = qla2xxx_queuecommand, 243 244 .eh_abort_handler = qla2xxx_eh_abort, 245 .eh_device_reset_handler = qla2xxx_eh_device_reset, 246 .eh_target_reset_handler = qla2xxx_eh_target_reset, 247 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 248 .eh_host_reset_handler = qla2xxx_eh_host_reset, 249 250 .slave_configure = qla2xxx_slave_configure, 251 252 .slave_alloc = qla2xxx_slave_alloc, 253 .slave_destroy = qla2xxx_slave_destroy, 254 .scan_finished = qla2xxx_scan_finished, 255 .scan_start = qla2xxx_scan_start, 256 .change_queue_depth = qla2x00_change_queue_depth, 257 .change_queue_type = qla2x00_change_queue_type, 258 .this_id = -1, 259 .cmd_per_lun = 3, 260 .use_clustering = ENABLE_CLUSTERING, 261 .sg_tablesize = SG_ALL, 262 263 .max_sectors = 0xFFFF, 264 .shost_attrs = qla2x00_host_attrs, 265 266 .supported_mode = MODE_INITIATOR, 267 }; 268 269 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 270 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 271 272 /* TODO Convert to inlines 273 * 274 * Timer routines 275 */ 276 277 __inline__ void 278 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 279 { 280 init_timer(&vha->timer); 281 vha->timer.expires = jiffies + interval * HZ; 282 vha->timer.data = (unsigned long)vha; 283 vha->timer.function = (void (*)(unsigned long))func; 284 add_timer(&vha->timer); 285 vha->timer_active = 1; 286 } 287 288 static inline void 289 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 290 { 291 /* Currently used for 82XX only. */ 292 if (vha->device_flags & DFLG_DEV_FAILED) { 293 ql_dbg(ql_dbg_timer, vha, 0x600d, 294 "Device in a failed state, returning.\n"); 295 return; 296 } 297 298 mod_timer(&vha->timer, jiffies + interval * HZ); 299 } 300 301 static __inline__ void 302 qla2x00_stop_timer(scsi_qla_host_t *vha) 303 { 304 del_timer_sync(&vha->timer); 305 vha->timer_active = 0; 306 } 307 308 static int qla2x00_do_dpc(void *data); 309 310 static void qla2x00_rst_aen(scsi_qla_host_t *); 311 312 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 313 struct req_que **, struct rsp_que **); 314 static void qla2x00_free_fw_dump(struct qla_hw_data *); 315 static void qla2x00_mem_free(struct qla_hw_data *); 316 317 /* -------------------------------------------------------------------------- */ 318 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 319 struct rsp_que *rsp) 320 { 321 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 322 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 323 GFP_KERNEL); 324 if (!ha->req_q_map) { 325 ql_log(ql_log_fatal, vha, 0x003b, 326 "Unable to allocate memory for request queue ptrs.\n"); 327 goto fail_req_map; 328 } 329 330 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 331 GFP_KERNEL); 332 if (!ha->rsp_q_map) { 333 ql_log(ql_log_fatal, vha, 0x003c, 334 "Unable to allocate memory for response queue ptrs.\n"); 335 goto fail_rsp_map; 336 } 337 /* 338 * Make sure we record at least the request and response queue zero in 339 * case we need to free them if part of the probe fails. 340 */ 341 ha->rsp_q_map[0] = rsp; 342 ha->req_q_map[0] = req; 343 set_bit(0, ha->rsp_qid_map); 344 set_bit(0, ha->req_qid_map); 345 return 1; 346 347 fail_rsp_map: 348 kfree(ha->req_q_map); 349 ha->req_q_map = NULL; 350 fail_req_map: 351 return -ENOMEM; 352 } 353 354 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 355 { 356 if (req && req->ring) 357 dma_free_coherent(&ha->pdev->dev, 358 (req->length + 1) * sizeof(request_t), 359 req->ring, req->dma); 360 361 kfree(req); 362 req = NULL; 363 } 364 365 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 366 { 367 if (rsp && rsp->ring) 368 dma_free_coherent(&ha->pdev->dev, 369 (rsp->length + 1) * sizeof(response_t), 370 rsp->ring, rsp->dma); 371 372 kfree(rsp); 373 rsp = NULL; 374 } 375 376 static void qla2x00_free_queues(struct qla_hw_data *ha) 377 { 378 struct req_que *req; 379 struct rsp_que *rsp; 380 int cnt; 381 382 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 383 req = ha->req_q_map[cnt]; 384 qla2x00_free_req_que(ha, req); 385 } 386 kfree(ha->req_q_map); 387 ha->req_q_map = NULL; 388 389 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 390 rsp = ha->rsp_q_map[cnt]; 391 qla2x00_free_rsp_que(ha, rsp); 392 } 393 kfree(ha->rsp_q_map); 394 ha->rsp_q_map = NULL; 395 } 396 397 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 398 { 399 uint16_t options = 0; 400 int ques, req, ret; 401 struct qla_hw_data *ha = vha->hw; 402 403 if (!(ha->fw_attributes & BIT_6)) { 404 ql_log(ql_log_warn, vha, 0x00d8, 405 "Firmware is not multi-queue capable.\n"); 406 goto fail; 407 } 408 if (ql2xmultique_tag) { 409 /* create a request queue for IO */ 410 options |= BIT_7; 411 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 412 QLA_DEFAULT_QUE_QOS); 413 if (!req) { 414 ql_log(ql_log_warn, vha, 0x00e0, 415 "Failed to create request queue.\n"); 416 goto fail; 417 } 418 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 419 vha->req = ha->req_q_map[req]; 420 options |= BIT_1; 421 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 422 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 423 if (!ret) { 424 ql_log(ql_log_warn, vha, 0x00e8, 425 "Failed to create response queue.\n"); 426 goto fail2; 427 } 428 } 429 ha->flags.cpu_affinity_enabled = 1; 430 ql_dbg(ql_dbg_multiq, vha, 0xc007, 431 "CPU affinity mode enalbed, " 432 "no. of response queues:%d no. of request queues:%d.\n", 433 ha->max_rsp_queues, ha->max_req_queues); 434 ql_dbg(ql_dbg_init, vha, 0x00e9, 435 "CPU affinity mode enalbed, " 436 "no. of response queues:%d no. of request queues:%d.\n", 437 ha->max_rsp_queues, ha->max_req_queues); 438 } 439 return 0; 440 fail2: 441 qla25xx_delete_queues(vha); 442 destroy_workqueue(ha->wq); 443 ha->wq = NULL; 444 vha->req = ha->req_q_map[0]; 445 fail: 446 ha->mqenable = 0; 447 kfree(ha->req_q_map); 448 kfree(ha->rsp_q_map); 449 ha->max_req_queues = ha->max_rsp_queues = 1; 450 return 1; 451 } 452 453 static char * 454 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 455 { 456 struct qla_hw_data *ha = vha->hw; 457 static char *pci_bus_modes[] = { 458 "33", "66", "100", "133", 459 }; 460 uint16_t pci_bus; 461 462 strcpy(str, "PCI"); 463 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 464 if (pci_bus) { 465 strcat(str, "-X ("); 466 strcat(str, pci_bus_modes[pci_bus]); 467 } else { 468 pci_bus = (ha->pci_attr & BIT_8) >> 8; 469 strcat(str, " ("); 470 strcat(str, pci_bus_modes[pci_bus]); 471 } 472 strcat(str, " MHz)"); 473 474 return (str); 475 } 476 477 static char * 478 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 479 { 480 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 481 struct qla_hw_data *ha = vha->hw; 482 uint32_t pci_bus; 483 int pcie_reg; 484 485 pcie_reg = pci_pcie_cap(ha->pdev); 486 if (pcie_reg) { 487 char lwstr[6]; 488 uint16_t pcie_lstat, lspeed, lwidth; 489 490 pcie_reg += PCI_EXP_LNKCAP; 491 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); 492 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); 493 lwidth = (pcie_lstat & 494 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; 495 496 strcpy(str, "PCIe ("); 497 if (lspeed == 1) 498 strcat(str, "2.5GT/s "); 499 else if (lspeed == 2) 500 strcat(str, "5.0GT/s "); 501 else 502 strcat(str, "<unknown> "); 503 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 504 strcat(str, lwstr); 505 506 return str; 507 } 508 509 strcpy(str, "PCI"); 510 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 511 if (pci_bus == 0 || pci_bus == 8) { 512 strcat(str, " ("); 513 strcat(str, pci_bus_modes[pci_bus >> 3]); 514 } else { 515 strcat(str, "-X "); 516 if (pci_bus & BIT_2) 517 strcat(str, "Mode 2"); 518 else 519 strcat(str, "Mode 1"); 520 strcat(str, " ("); 521 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 522 } 523 strcat(str, " MHz)"); 524 525 return str; 526 } 527 528 static char * 529 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 530 { 531 char un_str[10]; 532 struct qla_hw_data *ha = vha->hw; 533 534 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 535 ha->fw_minor_version, 536 ha->fw_subminor_version); 537 538 if (ha->fw_attributes & BIT_9) { 539 strcat(str, "FLX"); 540 return (str); 541 } 542 543 switch (ha->fw_attributes & 0xFF) { 544 case 0x7: 545 strcat(str, "EF"); 546 break; 547 case 0x17: 548 strcat(str, "TP"); 549 break; 550 case 0x37: 551 strcat(str, "IP"); 552 break; 553 case 0x77: 554 strcat(str, "VI"); 555 break; 556 default: 557 sprintf(un_str, "(%x)", ha->fw_attributes); 558 strcat(str, un_str); 559 break; 560 } 561 if (ha->fw_attributes & 0x100) 562 strcat(str, "X"); 563 564 return (str); 565 } 566 567 static char * 568 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 569 { 570 struct qla_hw_data *ha = vha->hw; 571 572 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 573 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 574 return str; 575 } 576 577 void 578 qla2x00_sp_free_dma(void *vha, void *ptr) 579 { 580 srb_t *sp = (srb_t *)ptr; 581 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 582 struct qla_hw_data *ha = sp->fcport->vha->hw; 583 void *ctx = GET_CMD_CTX_SP(sp); 584 585 if (sp->flags & SRB_DMA_VALID) { 586 scsi_dma_unmap(cmd); 587 sp->flags &= ~SRB_DMA_VALID; 588 } 589 590 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 591 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 592 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 593 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 594 } 595 596 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 597 /* List assured to be having elements */ 598 qla2x00_clean_dsd_pool(ha, sp); 599 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 600 } 601 602 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 603 dma_pool_free(ha->dl_dma_pool, ctx, 604 ((struct crc_context *)ctx)->crc_ctx_dma); 605 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 606 } 607 608 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 609 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 610 611 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 612 ctx1->fcp_cmnd_dma); 613 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 614 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 615 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 616 mempool_free(ctx1, ha->ctx_mempool); 617 ctx1 = NULL; 618 } 619 620 CMD_SP(cmd) = NULL; 621 mempool_free(sp, ha->srb_mempool); 622 } 623 624 static void 625 qla2x00_sp_compl(void *data, void *ptr, int res) 626 { 627 struct qla_hw_data *ha = (struct qla_hw_data *)data; 628 srb_t *sp = (srb_t *)ptr; 629 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 630 631 cmd->result = res; 632 633 if (atomic_read(&sp->ref_count) == 0) { 634 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 635 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 636 sp, GET_CMD_SP(sp)); 637 if (ql2xextended_error_logging & ql_dbg_io) 638 BUG(); 639 return; 640 } 641 if (!atomic_dec_and_test(&sp->ref_count)) 642 return; 643 644 qla2x00_sp_free_dma(ha, sp); 645 cmd->scsi_done(cmd); 646 } 647 648 static int 649 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 650 { 651 scsi_qla_host_t *vha = shost_priv(host); 652 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 653 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 654 struct qla_hw_data *ha = vha->hw; 655 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 656 srb_t *sp; 657 int rval; 658 659 if (ha->flags.eeh_busy) { 660 if (ha->flags.pci_channel_io_perm_failure) { 661 ql_dbg(ql_dbg_aer, vha, 0x9010, 662 "PCI Channel IO permanent failure, exiting " 663 "cmd=%p.\n", cmd); 664 cmd->result = DID_NO_CONNECT << 16; 665 } else { 666 ql_dbg(ql_dbg_aer, vha, 0x9011, 667 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 668 cmd->result = DID_REQUEUE << 16; 669 } 670 goto qc24_fail_command; 671 } 672 673 rval = fc_remote_port_chkready(rport); 674 if (rval) { 675 cmd->result = rval; 676 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 677 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 678 cmd, rval); 679 goto qc24_fail_command; 680 } 681 682 if (!vha->flags.difdix_supported && 683 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 684 ql_dbg(ql_dbg_io, vha, 0x3004, 685 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 686 cmd); 687 cmd->result = DID_NO_CONNECT << 16; 688 goto qc24_fail_command; 689 } 690 691 if (!fcport) { 692 cmd->result = DID_NO_CONNECT << 16; 693 goto qc24_fail_command; 694 } 695 696 if (atomic_read(&fcport->state) != FCS_ONLINE) { 697 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 698 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 699 ql_dbg(ql_dbg_io, vha, 0x3005, 700 "Returning DNC, fcport_state=%d loop_state=%d.\n", 701 atomic_read(&fcport->state), 702 atomic_read(&base_vha->loop_state)); 703 cmd->result = DID_NO_CONNECT << 16; 704 goto qc24_fail_command; 705 } 706 goto qc24_target_busy; 707 } 708 709 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC); 710 if (!sp) 711 goto qc24_host_busy; 712 713 sp->u.scmd.cmd = cmd; 714 sp->type = SRB_SCSI_CMD; 715 atomic_set(&sp->ref_count, 1); 716 CMD_SP(cmd) = (void *)sp; 717 sp->free = qla2x00_sp_free_dma; 718 sp->done = qla2x00_sp_compl; 719 720 rval = ha->isp_ops->start_scsi(sp); 721 if (rval != QLA_SUCCESS) { 722 ql_dbg(ql_dbg_io, vha, 0x3013, 723 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 724 goto qc24_host_busy_free_sp; 725 } 726 727 return 0; 728 729 qc24_host_busy_free_sp: 730 qla2x00_sp_free_dma(ha, sp); 731 732 qc24_host_busy: 733 return SCSI_MLQUEUE_HOST_BUSY; 734 735 qc24_target_busy: 736 return SCSI_MLQUEUE_TARGET_BUSY; 737 738 qc24_fail_command: 739 cmd->scsi_done(cmd); 740 741 return 0; 742 } 743 744 /* 745 * qla2x00_eh_wait_on_command 746 * Waits for the command to be returned by the Firmware for some 747 * max time. 748 * 749 * Input: 750 * cmd = Scsi Command to wait on. 751 * 752 * Return: 753 * Not Found : 0 754 * Found : 1 755 */ 756 static int 757 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 758 { 759 #define ABORT_POLLING_PERIOD 1000 760 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 761 unsigned long wait_iter = ABORT_WAIT_ITER; 762 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 763 struct qla_hw_data *ha = vha->hw; 764 int ret = QLA_SUCCESS; 765 766 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 767 ql_dbg(ql_dbg_taskm, vha, 0x8005, 768 "Return:eh_wait.\n"); 769 return ret; 770 } 771 772 while (CMD_SP(cmd) && wait_iter--) { 773 msleep(ABORT_POLLING_PERIOD); 774 } 775 if (CMD_SP(cmd)) 776 ret = QLA_FUNCTION_FAILED; 777 778 return ret; 779 } 780 781 /* 782 * qla2x00_wait_for_hba_online 783 * Wait till the HBA is online after going through 784 * <= MAX_RETRIES_OF_ISP_ABORT or 785 * finally HBA is disabled ie marked offline 786 * 787 * Input: 788 * ha - pointer to host adapter structure 789 * 790 * Note: 791 * Does context switching-Release SPIN_LOCK 792 * (if any) before calling this routine. 793 * 794 * Return: 795 * Success (Adapter is online) : 0 796 * Failed (Adapter is offline/disabled) : 1 797 */ 798 int 799 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 800 { 801 int return_status; 802 unsigned long wait_online; 803 struct qla_hw_data *ha = vha->hw; 804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 805 806 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 807 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 808 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 809 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 810 ha->dpc_active) && time_before(jiffies, wait_online)) { 811 812 msleep(1000); 813 } 814 if (base_vha->flags.online) 815 return_status = QLA_SUCCESS; 816 else 817 return_status = QLA_FUNCTION_FAILED; 818 819 return (return_status); 820 } 821 822 /* 823 * qla2x00_wait_for_reset_ready 824 * Wait till the HBA is online after going through 825 * <= MAX_RETRIES_OF_ISP_ABORT or 826 * finally HBA is disabled ie marked offline or flash 827 * operations are in progress. 828 * 829 * Input: 830 * ha - pointer to host adapter structure 831 * 832 * Note: 833 * Does context switching-Release SPIN_LOCK 834 * (if any) before calling this routine. 835 * 836 * Return: 837 * Success (Adapter is online/no flash ops) : 0 838 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 839 */ 840 static int 841 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 842 { 843 int return_status; 844 unsigned long wait_online; 845 struct qla_hw_data *ha = vha->hw; 846 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 847 848 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 849 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 850 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 851 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 852 ha->optrom_state != QLA_SWAITING || 853 ha->dpc_active) && time_before(jiffies, wait_online)) 854 msleep(1000); 855 856 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 857 return_status = QLA_SUCCESS; 858 else 859 return_status = QLA_FUNCTION_FAILED; 860 861 ql_dbg(ql_dbg_taskm, vha, 0x8019, 862 "%s return status=%d.\n", __func__, return_status); 863 864 return return_status; 865 } 866 867 int 868 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 869 { 870 int return_status; 871 unsigned long wait_reset; 872 struct qla_hw_data *ha = vha->hw; 873 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 874 875 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 876 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 877 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 878 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 879 ha->dpc_active) && time_before(jiffies, wait_reset)) { 880 881 msleep(1000); 882 883 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 884 ha->flags.chip_reset_done) 885 break; 886 } 887 if (ha->flags.chip_reset_done) 888 return_status = QLA_SUCCESS; 889 else 890 return_status = QLA_FUNCTION_FAILED; 891 892 return return_status; 893 } 894 895 static void 896 sp_get(struct srb *sp) 897 { 898 atomic_inc(&sp->ref_count); 899 } 900 901 /************************************************************************** 902 * qla2xxx_eh_abort 903 * 904 * Description: 905 * The abort function will abort the specified command. 906 * 907 * Input: 908 * cmd = Linux SCSI command packet to be aborted. 909 * 910 * Returns: 911 * Either SUCCESS or FAILED. 912 * 913 * Note: 914 * Only return FAILED if command not returned by firmware. 915 **************************************************************************/ 916 static int 917 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 918 { 919 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 920 srb_t *sp; 921 int ret; 922 unsigned int id, lun; 923 unsigned long flags; 924 int wait = 0; 925 struct qla_hw_data *ha = vha->hw; 926 927 if (!CMD_SP(cmd)) 928 return SUCCESS; 929 930 ret = fc_block_scsi_eh(cmd); 931 if (ret != 0) 932 return ret; 933 ret = SUCCESS; 934 935 id = cmd->device->id; 936 lun = cmd->device->lun; 937 938 spin_lock_irqsave(&ha->hardware_lock, flags); 939 sp = (srb_t *) CMD_SP(cmd); 940 if (!sp) { 941 spin_unlock_irqrestore(&ha->hardware_lock, flags); 942 return SUCCESS; 943 } 944 945 ql_dbg(ql_dbg_taskm, vha, 0x8002, 946 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", 947 vha->host_no, id, lun, sp, cmd); 948 949 /* Get a reference to the sp and drop the lock.*/ 950 sp_get(sp); 951 952 spin_unlock_irqrestore(&ha->hardware_lock, flags); 953 if (ha->isp_ops->abort_command(sp)) { 954 ret = FAILED; 955 ql_dbg(ql_dbg_taskm, vha, 0x8003, 956 "Abort command mbx failed cmd=%p.\n", cmd); 957 } else { 958 ql_dbg(ql_dbg_taskm, vha, 0x8004, 959 "Abort command mbx success cmd=%p.\n", cmd); 960 wait = 1; 961 } 962 963 spin_lock_irqsave(&ha->hardware_lock, flags); 964 sp->done(ha, sp, 0); 965 spin_unlock_irqrestore(&ha->hardware_lock, flags); 966 967 /* Did the command return during mailbox execution? */ 968 if (ret == FAILED && !CMD_SP(cmd)) 969 ret = SUCCESS; 970 971 /* Wait for the command to be returned. */ 972 if (wait) { 973 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 974 ql_log(ql_log_warn, vha, 0x8006, 975 "Abort handler timed out cmd=%p.\n", cmd); 976 ret = FAILED; 977 } 978 } 979 980 ql_log(ql_log_info, vha, 0x801c, 981 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", 982 vha->host_no, id, lun, wait, ret); 983 984 return ret; 985 } 986 987 int 988 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 989 unsigned int l, enum nexus_wait_type type) 990 { 991 int cnt, match, status; 992 unsigned long flags; 993 struct qla_hw_data *ha = vha->hw; 994 struct req_que *req; 995 srb_t *sp; 996 struct scsi_cmnd *cmd; 997 998 status = QLA_SUCCESS; 999 1000 spin_lock_irqsave(&ha->hardware_lock, flags); 1001 req = vha->req; 1002 for (cnt = 1; status == QLA_SUCCESS && 1003 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 1004 sp = req->outstanding_cmds[cnt]; 1005 if (!sp) 1006 continue; 1007 if (sp->type != SRB_SCSI_CMD) 1008 continue; 1009 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1010 continue; 1011 match = 0; 1012 cmd = GET_CMD_SP(sp); 1013 switch (type) { 1014 case WAIT_HOST: 1015 match = 1; 1016 break; 1017 case WAIT_TARGET: 1018 match = cmd->device->id == t; 1019 break; 1020 case WAIT_LUN: 1021 match = (cmd->device->id == t && 1022 cmd->device->lun == l); 1023 break; 1024 } 1025 if (!match) 1026 continue; 1027 1028 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1029 status = qla2x00_eh_wait_on_command(cmd); 1030 spin_lock_irqsave(&ha->hardware_lock, flags); 1031 } 1032 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1033 1034 return status; 1035 } 1036 1037 static char *reset_errors[] = { 1038 "HBA not online", 1039 "HBA not ready", 1040 "Task management failed", 1041 "Waiting for command completions", 1042 }; 1043 1044 static int 1045 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1046 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 1047 { 1048 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1049 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1050 int err; 1051 1052 if (!fcport) { 1053 return FAILED; 1054 } 1055 1056 err = fc_block_scsi_eh(cmd); 1057 if (err != 0) 1058 return err; 1059 1060 ql_log(ql_log_info, vha, 0x8009, 1061 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, 1062 cmd->device->id, cmd->device->lun, cmd); 1063 1064 err = 0; 1065 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1066 ql_log(ql_log_warn, vha, 0x800a, 1067 "Wait for hba online failed for cmd=%p.\n", cmd); 1068 goto eh_reset_failed; 1069 } 1070 err = 2; 1071 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1072 != QLA_SUCCESS) { 1073 ql_log(ql_log_warn, vha, 0x800c, 1074 "do_reset failed for cmd=%p.\n", cmd); 1075 goto eh_reset_failed; 1076 } 1077 err = 3; 1078 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1079 cmd->device->lun, type) != QLA_SUCCESS) { 1080 ql_log(ql_log_warn, vha, 0x800d, 1081 "wait for peding cmds failed for cmd=%p.\n", cmd); 1082 goto eh_reset_failed; 1083 } 1084 1085 ql_log(ql_log_info, vha, 0x800e, 1086 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, 1087 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1088 1089 return SUCCESS; 1090 1091 eh_reset_failed: 1092 ql_log(ql_log_info, vha, 0x800f, 1093 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, 1094 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1095 cmd); 1096 return FAILED; 1097 } 1098 1099 static int 1100 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1101 { 1102 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1103 struct qla_hw_data *ha = vha->hw; 1104 1105 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1106 ha->isp_ops->lun_reset); 1107 } 1108 1109 static int 1110 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1111 { 1112 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1113 struct qla_hw_data *ha = vha->hw; 1114 1115 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1116 ha->isp_ops->target_reset); 1117 } 1118 1119 /************************************************************************** 1120 * qla2xxx_eh_bus_reset 1121 * 1122 * Description: 1123 * The bus reset function will reset the bus and abort any executing 1124 * commands. 1125 * 1126 * Input: 1127 * cmd = Linux SCSI command packet of the command that cause the 1128 * bus reset. 1129 * 1130 * Returns: 1131 * SUCCESS/FAILURE (defined as macro in scsi.h). 1132 * 1133 **************************************************************************/ 1134 static int 1135 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1136 { 1137 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1138 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1139 int ret = FAILED; 1140 unsigned int id, lun; 1141 1142 id = cmd->device->id; 1143 lun = cmd->device->lun; 1144 1145 if (!fcport) { 1146 return ret; 1147 } 1148 1149 ret = fc_block_scsi_eh(cmd); 1150 if (ret != 0) 1151 return ret; 1152 ret = FAILED; 1153 1154 ql_log(ql_log_info, vha, 0x8012, 1155 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1156 1157 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1158 ql_log(ql_log_fatal, vha, 0x8013, 1159 "Wait for hba online failed board disabled.\n"); 1160 goto eh_bus_reset_done; 1161 } 1162 1163 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1164 ret = SUCCESS; 1165 1166 if (ret == FAILED) 1167 goto eh_bus_reset_done; 1168 1169 /* Flush outstanding commands. */ 1170 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1171 QLA_SUCCESS) { 1172 ql_log(ql_log_warn, vha, 0x8014, 1173 "Wait for pending commands failed.\n"); 1174 ret = FAILED; 1175 } 1176 1177 eh_bus_reset_done: 1178 ql_log(ql_log_warn, vha, 0x802b, 1179 "BUS RESET %s nexus=%ld:%d:%d.\n", 1180 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun); 1181 1182 return ret; 1183 } 1184 1185 /************************************************************************** 1186 * qla2xxx_eh_host_reset 1187 * 1188 * Description: 1189 * The reset function will reset the Adapter. 1190 * 1191 * Input: 1192 * cmd = Linux SCSI command packet of the command that cause the 1193 * adapter reset. 1194 * 1195 * Returns: 1196 * Either SUCCESS or FAILED. 1197 * 1198 * Note: 1199 **************************************************************************/ 1200 static int 1201 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1202 { 1203 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1204 struct qla_hw_data *ha = vha->hw; 1205 int ret = FAILED; 1206 unsigned int id, lun; 1207 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1208 1209 id = cmd->device->id; 1210 lun = cmd->device->lun; 1211 1212 ql_log(ql_log_info, vha, 0x8018, 1213 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1214 1215 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1216 goto eh_host_reset_lock; 1217 1218 if (vha != base_vha) { 1219 if (qla2x00_vp_abort_isp(vha)) 1220 goto eh_host_reset_lock; 1221 } else { 1222 if (IS_QLA82XX(vha->hw)) { 1223 if (!qla82xx_fcoe_ctx_reset(vha)) { 1224 /* Ctx reset success */ 1225 ret = SUCCESS; 1226 goto eh_host_reset_lock; 1227 } 1228 /* fall thru if ctx reset failed */ 1229 } 1230 if (ha->wq) 1231 flush_workqueue(ha->wq); 1232 1233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1234 if (ha->isp_ops->abort_isp(base_vha)) { 1235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1236 /* failed. schedule dpc to try */ 1237 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1238 1239 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1240 ql_log(ql_log_warn, vha, 0x802a, 1241 "wait for hba online failed.\n"); 1242 goto eh_host_reset_lock; 1243 } 1244 } 1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1246 } 1247 1248 /* Waiting for command to be returned to OS.*/ 1249 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1250 QLA_SUCCESS) 1251 ret = SUCCESS; 1252 1253 eh_host_reset_lock: 1254 ql_log(ql_log_info, vha, 0x8017, 1255 "ADAPTER RESET %s nexus=%ld:%d:%d.\n", 1256 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1257 1258 return ret; 1259 } 1260 1261 /* 1262 * qla2x00_loop_reset 1263 * Issue loop reset. 1264 * 1265 * Input: 1266 * ha = adapter block pointer. 1267 * 1268 * Returns: 1269 * 0 = success 1270 */ 1271 int 1272 qla2x00_loop_reset(scsi_qla_host_t *vha) 1273 { 1274 int ret; 1275 struct fc_port *fcport; 1276 struct qla_hw_data *ha = vha->hw; 1277 1278 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1279 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1280 if (fcport->port_type != FCT_TARGET) 1281 continue; 1282 1283 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1284 if (ret != QLA_SUCCESS) { 1285 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1286 "Bus Reset failed: Target Reset=%d " 1287 "d_id=%x.\n", ret, fcport->d_id.b24); 1288 } 1289 } 1290 } 1291 1292 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1293 ret = qla2x00_full_login_lip(vha); 1294 if (ret != QLA_SUCCESS) { 1295 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1296 "full_login_lip=%d.\n", ret); 1297 } 1298 atomic_set(&vha->loop_state, LOOP_DOWN); 1299 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1300 qla2x00_mark_all_devices_lost(vha, 0); 1301 } 1302 1303 if (ha->flags.enable_lip_reset) { 1304 ret = qla2x00_lip_reset(vha); 1305 if (ret != QLA_SUCCESS) 1306 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1307 "lip_reset failed (%d).\n", ret); 1308 } 1309 1310 /* Issue marker command only when we are going to start the I/O */ 1311 vha->marker_needed = 1; 1312 1313 return QLA_SUCCESS; 1314 } 1315 1316 void 1317 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1318 { 1319 int que, cnt; 1320 unsigned long flags; 1321 srb_t *sp; 1322 struct qla_hw_data *ha = vha->hw; 1323 struct req_que *req; 1324 1325 spin_lock_irqsave(&ha->hardware_lock, flags); 1326 for (que = 0; que < ha->max_req_queues; que++) { 1327 req = ha->req_q_map[que]; 1328 if (!req) 1329 continue; 1330 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 1331 sp = req->outstanding_cmds[cnt]; 1332 if (sp) { 1333 req->outstanding_cmds[cnt] = NULL; 1334 sp->done(vha, sp, res); 1335 } 1336 } 1337 } 1338 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1339 } 1340 1341 static int 1342 qla2xxx_slave_alloc(struct scsi_device *sdev) 1343 { 1344 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1345 1346 if (!rport || fc_remote_port_chkready(rport)) 1347 return -ENXIO; 1348 1349 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1350 1351 return 0; 1352 } 1353 1354 static int 1355 qla2xxx_slave_configure(struct scsi_device *sdev) 1356 { 1357 scsi_qla_host_t *vha = shost_priv(sdev->host); 1358 struct req_que *req = vha->req; 1359 1360 if (sdev->tagged_supported) 1361 scsi_activate_tcq(sdev, req->max_q_depth); 1362 else 1363 scsi_deactivate_tcq(sdev, req->max_q_depth); 1364 return 0; 1365 } 1366 1367 static void 1368 qla2xxx_slave_destroy(struct scsi_device *sdev) 1369 { 1370 sdev->hostdata = NULL; 1371 } 1372 1373 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1374 { 1375 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1376 1377 if (!scsi_track_queue_full(sdev, qdepth)) 1378 return; 1379 1380 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1381 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", 1382 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1383 } 1384 1385 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1386 { 1387 fc_port_t *fcport = sdev->hostdata; 1388 struct scsi_qla_host *vha = fcport->vha; 1389 struct req_que *req = NULL; 1390 1391 req = vha->req; 1392 if (!req) 1393 return; 1394 1395 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1396 return; 1397 1398 if (sdev->ordered_tags) 1399 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1400 else 1401 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1402 1403 ql_dbg(ql_dbg_io, vha, 0x302a, 1404 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", 1405 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1406 } 1407 1408 static int 1409 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1410 { 1411 switch (reason) { 1412 case SCSI_QDEPTH_DEFAULT: 1413 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1414 break; 1415 case SCSI_QDEPTH_QFULL: 1416 qla2x00_handle_queue_full(sdev, qdepth); 1417 break; 1418 case SCSI_QDEPTH_RAMP_UP: 1419 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1420 break; 1421 default: 1422 return -EOPNOTSUPP; 1423 } 1424 1425 return sdev->queue_depth; 1426 } 1427 1428 static int 1429 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1430 { 1431 if (sdev->tagged_supported) { 1432 scsi_set_tag_type(sdev, tag_type); 1433 if (tag_type) 1434 scsi_activate_tcq(sdev, sdev->queue_depth); 1435 else 1436 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1437 } else 1438 tag_type = 0; 1439 1440 return tag_type; 1441 } 1442 1443 /** 1444 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1445 * @ha: HA context 1446 * 1447 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1448 * supported addressing method. 1449 */ 1450 static void 1451 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1452 { 1453 /* Assume a 32bit DMA mask. */ 1454 ha->flags.enable_64bit_addressing = 0; 1455 1456 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1457 /* Any upper-dword bits set? */ 1458 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1459 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1460 /* Ok, a 64bit DMA mask is applicable. */ 1461 ha->flags.enable_64bit_addressing = 1; 1462 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1463 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1464 return; 1465 } 1466 } 1467 1468 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1469 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1470 } 1471 1472 static void 1473 qla2x00_enable_intrs(struct qla_hw_data *ha) 1474 { 1475 unsigned long flags = 0; 1476 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1477 1478 spin_lock_irqsave(&ha->hardware_lock, flags); 1479 ha->interrupts_on = 1; 1480 /* enable risc and host interrupts */ 1481 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1482 RD_REG_WORD(®->ictrl); 1483 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1484 1485 } 1486 1487 static void 1488 qla2x00_disable_intrs(struct qla_hw_data *ha) 1489 { 1490 unsigned long flags = 0; 1491 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1492 1493 spin_lock_irqsave(&ha->hardware_lock, flags); 1494 ha->interrupts_on = 0; 1495 /* disable risc and host interrupts */ 1496 WRT_REG_WORD(®->ictrl, 0); 1497 RD_REG_WORD(®->ictrl); 1498 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1499 } 1500 1501 static void 1502 qla24xx_enable_intrs(struct qla_hw_data *ha) 1503 { 1504 unsigned long flags = 0; 1505 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1506 1507 spin_lock_irqsave(&ha->hardware_lock, flags); 1508 ha->interrupts_on = 1; 1509 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1510 RD_REG_DWORD(®->ictrl); 1511 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1512 } 1513 1514 static void 1515 qla24xx_disable_intrs(struct qla_hw_data *ha) 1516 { 1517 unsigned long flags = 0; 1518 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1519 1520 if (IS_NOPOLLING_TYPE(ha)) 1521 return; 1522 spin_lock_irqsave(&ha->hardware_lock, flags); 1523 ha->interrupts_on = 0; 1524 WRT_REG_DWORD(®->ictrl, 0); 1525 RD_REG_DWORD(®->ictrl); 1526 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1527 } 1528 1529 static int 1530 qla2x00_iospace_config(struct qla_hw_data *ha) 1531 { 1532 resource_size_t pio; 1533 uint16_t msix; 1534 int cpus; 1535 1536 if (pci_request_selected_regions(ha->pdev, ha->bars, 1537 QLA2XXX_DRIVER_NAME)) { 1538 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1539 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1540 pci_name(ha->pdev)); 1541 goto iospace_error_exit; 1542 } 1543 if (!(ha->bars & 1)) 1544 goto skip_pio; 1545 1546 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1547 pio = pci_resource_start(ha->pdev, 0); 1548 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1549 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1550 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1551 "Invalid pci I/O region size (%s).\n", 1552 pci_name(ha->pdev)); 1553 pio = 0; 1554 } 1555 } else { 1556 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1557 "Region #0 no a PIO resource (%s).\n", 1558 pci_name(ha->pdev)); 1559 pio = 0; 1560 } 1561 ha->pio_address = pio; 1562 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1563 "PIO address=%llu.\n", 1564 (unsigned long long)ha->pio_address); 1565 1566 skip_pio: 1567 /* Use MMIO operations for all accesses. */ 1568 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1569 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1570 "Region #1 not an MMIO resource (%s), aborting.\n", 1571 pci_name(ha->pdev)); 1572 goto iospace_error_exit; 1573 } 1574 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1575 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1576 "Invalid PCI mem region size (%s), aborting.\n", 1577 pci_name(ha->pdev)); 1578 goto iospace_error_exit; 1579 } 1580 1581 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1582 if (!ha->iobase) { 1583 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1584 "Cannot remap MMIO (%s), aborting.\n", 1585 pci_name(ha->pdev)); 1586 goto iospace_error_exit; 1587 } 1588 1589 /* Determine queue resources */ 1590 ha->max_req_queues = ha->max_rsp_queues = 1; 1591 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1592 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1593 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1594 goto mqiobase_exit; 1595 1596 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1597 pci_resource_len(ha->pdev, 3)); 1598 if (ha->mqiobase) { 1599 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1600 "MQIO Base=%p.\n", ha->mqiobase); 1601 /* Read MSIX vector size of the board */ 1602 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1603 ha->msix_count = msix; 1604 /* Max queues are bounded by available msix vectors */ 1605 /* queue 0 uses two msix vectors */ 1606 if (ql2xmultique_tag) { 1607 cpus = num_online_cpus(); 1608 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1609 (cpus + 1) : (ha->msix_count - 1); 1610 ha->max_req_queues = 2; 1611 } else if (ql2xmaxqueues > 1) { 1612 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1613 QLA_MQ_SIZE : ql2xmaxqueues; 1614 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1615 "QoS mode set, max no of request queues:%d.\n", 1616 ha->max_req_queues); 1617 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1618 "QoS mode set, max no of request queues:%d.\n", 1619 ha->max_req_queues); 1620 } 1621 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1622 "MSI-X vector count: %d.\n", msix); 1623 } else 1624 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1625 "BAR 3 not enabled.\n"); 1626 1627 mqiobase_exit: 1628 ha->msix_count = ha->max_rsp_queues + 1; 1629 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1630 "MSIX Count:%d.\n", ha->msix_count); 1631 return (0); 1632 1633 iospace_error_exit: 1634 return (-ENOMEM); 1635 } 1636 1637 1638 static int 1639 qla83xx_iospace_config(struct qla_hw_data *ha) 1640 { 1641 uint16_t msix; 1642 int cpus; 1643 1644 if (pci_request_selected_regions(ha->pdev, ha->bars, 1645 QLA2XXX_DRIVER_NAME)) { 1646 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1647 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1648 pci_name(ha->pdev)); 1649 1650 goto iospace_error_exit; 1651 } 1652 1653 /* Use MMIO operations for all accesses. */ 1654 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1655 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1656 "Invalid pci I/O region size (%s).\n", 1657 pci_name(ha->pdev)); 1658 goto iospace_error_exit; 1659 } 1660 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1661 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1662 "Invalid PCI mem region size (%s), aborting\n", 1663 pci_name(ha->pdev)); 1664 goto iospace_error_exit; 1665 } 1666 1667 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1668 if (!ha->iobase) { 1669 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1670 "Cannot remap MMIO (%s), aborting.\n", 1671 pci_name(ha->pdev)); 1672 goto iospace_error_exit; 1673 } 1674 1675 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1676 /* 83XX 26XX always use MQ type access for queues 1677 * - mbar 2, a.k.a region 4 */ 1678 ha->max_req_queues = ha->max_rsp_queues = 1; 1679 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1680 pci_resource_len(ha->pdev, 4)); 1681 1682 if (!ha->mqiobase) { 1683 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1684 "BAR2/region4 not enabled\n"); 1685 goto mqiobase_exit; 1686 } 1687 1688 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1689 pci_resource_len(ha->pdev, 2)); 1690 if (ha->msixbase) { 1691 /* Read MSIX vector size of the board */ 1692 pci_read_config_word(ha->pdev, 1693 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1694 ha->msix_count = msix; 1695 /* Max queues are bounded by available msix vectors */ 1696 /* queue 0 uses two msix vectors */ 1697 if (ql2xmultique_tag) { 1698 cpus = num_online_cpus(); 1699 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1700 (cpus + 1) : (ha->msix_count - 1); 1701 ha->max_req_queues = 2; 1702 } else if (ql2xmaxqueues > 1) { 1703 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1704 QLA_MQ_SIZE : ql2xmaxqueues; 1705 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1706 "QoS mode set, max no of request queues:%d.\n", 1707 ha->max_req_queues); 1708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1709 "QoS mode set, max no of request queues:%d.\n", 1710 ha->max_req_queues); 1711 } 1712 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1713 "MSI-X vector count: %d.\n", msix); 1714 } else 1715 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1716 "BAR 1 not enabled.\n"); 1717 1718 mqiobase_exit: 1719 ha->msix_count = ha->max_rsp_queues + 1; 1720 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1721 "MSIX Count:%d.\n", ha->msix_count); 1722 return 0; 1723 1724 iospace_error_exit: 1725 return -ENOMEM; 1726 } 1727 1728 static struct isp_operations qla2100_isp_ops = { 1729 .pci_config = qla2100_pci_config, 1730 .reset_chip = qla2x00_reset_chip, 1731 .chip_diag = qla2x00_chip_diag, 1732 .config_rings = qla2x00_config_rings, 1733 .reset_adapter = qla2x00_reset_adapter, 1734 .nvram_config = qla2x00_nvram_config, 1735 .update_fw_options = qla2x00_update_fw_options, 1736 .load_risc = qla2x00_load_risc, 1737 .pci_info_str = qla2x00_pci_info_str, 1738 .fw_version_str = qla2x00_fw_version_str, 1739 .intr_handler = qla2100_intr_handler, 1740 .enable_intrs = qla2x00_enable_intrs, 1741 .disable_intrs = qla2x00_disable_intrs, 1742 .abort_command = qla2x00_abort_command, 1743 .target_reset = qla2x00_abort_target, 1744 .lun_reset = qla2x00_lun_reset, 1745 .fabric_login = qla2x00_login_fabric, 1746 .fabric_logout = qla2x00_fabric_logout, 1747 .calc_req_entries = qla2x00_calc_iocbs_32, 1748 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1749 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1750 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1751 .read_nvram = qla2x00_read_nvram_data, 1752 .write_nvram = qla2x00_write_nvram_data, 1753 .fw_dump = qla2100_fw_dump, 1754 .beacon_on = NULL, 1755 .beacon_off = NULL, 1756 .beacon_blink = NULL, 1757 .read_optrom = qla2x00_read_optrom_data, 1758 .write_optrom = qla2x00_write_optrom_data, 1759 .get_flash_version = qla2x00_get_flash_version, 1760 .start_scsi = qla2x00_start_scsi, 1761 .abort_isp = qla2x00_abort_isp, 1762 .iospace_config = qla2x00_iospace_config, 1763 }; 1764 1765 static struct isp_operations qla2300_isp_ops = { 1766 .pci_config = qla2300_pci_config, 1767 .reset_chip = qla2x00_reset_chip, 1768 .chip_diag = qla2x00_chip_diag, 1769 .config_rings = qla2x00_config_rings, 1770 .reset_adapter = qla2x00_reset_adapter, 1771 .nvram_config = qla2x00_nvram_config, 1772 .update_fw_options = qla2x00_update_fw_options, 1773 .load_risc = qla2x00_load_risc, 1774 .pci_info_str = qla2x00_pci_info_str, 1775 .fw_version_str = qla2x00_fw_version_str, 1776 .intr_handler = qla2300_intr_handler, 1777 .enable_intrs = qla2x00_enable_intrs, 1778 .disable_intrs = qla2x00_disable_intrs, 1779 .abort_command = qla2x00_abort_command, 1780 .target_reset = qla2x00_abort_target, 1781 .lun_reset = qla2x00_lun_reset, 1782 .fabric_login = qla2x00_login_fabric, 1783 .fabric_logout = qla2x00_fabric_logout, 1784 .calc_req_entries = qla2x00_calc_iocbs_32, 1785 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1786 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1787 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1788 .read_nvram = qla2x00_read_nvram_data, 1789 .write_nvram = qla2x00_write_nvram_data, 1790 .fw_dump = qla2300_fw_dump, 1791 .beacon_on = qla2x00_beacon_on, 1792 .beacon_off = qla2x00_beacon_off, 1793 .beacon_blink = qla2x00_beacon_blink, 1794 .read_optrom = qla2x00_read_optrom_data, 1795 .write_optrom = qla2x00_write_optrom_data, 1796 .get_flash_version = qla2x00_get_flash_version, 1797 .start_scsi = qla2x00_start_scsi, 1798 .abort_isp = qla2x00_abort_isp, 1799 .iospace_config = qla2x00_iospace_config, 1800 }; 1801 1802 static struct isp_operations qla24xx_isp_ops = { 1803 .pci_config = qla24xx_pci_config, 1804 .reset_chip = qla24xx_reset_chip, 1805 .chip_diag = qla24xx_chip_diag, 1806 .config_rings = qla24xx_config_rings, 1807 .reset_adapter = qla24xx_reset_adapter, 1808 .nvram_config = qla24xx_nvram_config, 1809 .update_fw_options = qla24xx_update_fw_options, 1810 .load_risc = qla24xx_load_risc, 1811 .pci_info_str = qla24xx_pci_info_str, 1812 .fw_version_str = qla24xx_fw_version_str, 1813 .intr_handler = qla24xx_intr_handler, 1814 .enable_intrs = qla24xx_enable_intrs, 1815 .disable_intrs = qla24xx_disable_intrs, 1816 .abort_command = qla24xx_abort_command, 1817 .target_reset = qla24xx_abort_target, 1818 .lun_reset = qla24xx_lun_reset, 1819 .fabric_login = qla24xx_login_fabric, 1820 .fabric_logout = qla24xx_fabric_logout, 1821 .calc_req_entries = NULL, 1822 .build_iocbs = NULL, 1823 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1824 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1825 .read_nvram = qla24xx_read_nvram_data, 1826 .write_nvram = qla24xx_write_nvram_data, 1827 .fw_dump = qla24xx_fw_dump, 1828 .beacon_on = qla24xx_beacon_on, 1829 .beacon_off = qla24xx_beacon_off, 1830 .beacon_blink = qla24xx_beacon_blink, 1831 .read_optrom = qla24xx_read_optrom_data, 1832 .write_optrom = qla24xx_write_optrom_data, 1833 .get_flash_version = qla24xx_get_flash_version, 1834 .start_scsi = qla24xx_start_scsi, 1835 .abort_isp = qla2x00_abort_isp, 1836 .iospace_config = qla2x00_iospace_config, 1837 }; 1838 1839 static struct isp_operations qla25xx_isp_ops = { 1840 .pci_config = qla25xx_pci_config, 1841 .reset_chip = qla24xx_reset_chip, 1842 .chip_diag = qla24xx_chip_diag, 1843 .config_rings = qla24xx_config_rings, 1844 .reset_adapter = qla24xx_reset_adapter, 1845 .nvram_config = qla24xx_nvram_config, 1846 .update_fw_options = qla24xx_update_fw_options, 1847 .load_risc = qla24xx_load_risc, 1848 .pci_info_str = qla24xx_pci_info_str, 1849 .fw_version_str = qla24xx_fw_version_str, 1850 .intr_handler = qla24xx_intr_handler, 1851 .enable_intrs = qla24xx_enable_intrs, 1852 .disable_intrs = qla24xx_disable_intrs, 1853 .abort_command = qla24xx_abort_command, 1854 .target_reset = qla24xx_abort_target, 1855 .lun_reset = qla24xx_lun_reset, 1856 .fabric_login = qla24xx_login_fabric, 1857 .fabric_logout = qla24xx_fabric_logout, 1858 .calc_req_entries = NULL, 1859 .build_iocbs = NULL, 1860 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1861 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1862 .read_nvram = qla25xx_read_nvram_data, 1863 .write_nvram = qla25xx_write_nvram_data, 1864 .fw_dump = qla25xx_fw_dump, 1865 .beacon_on = qla24xx_beacon_on, 1866 .beacon_off = qla24xx_beacon_off, 1867 .beacon_blink = qla24xx_beacon_blink, 1868 .read_optrom = qla25xx_read_optrom_data, 1869 .write_optrom = qla24xx_write_optrom_data, 1870 .get_flash_version = qla24xx_get_flash_version, 1871 .start_scsi = qla24xx_dif_start_scsi, 1872 .abort_isp = qla2x00_abort_isp, 1873 .iospace_config = qla2x00_iospace_config, 1874 }; 1875 1876 static struct isp_operations qla81xx_isp_ops = { 1877 .pci_config = qla25xx_pci_config, 1878 .reset_chip = qla24xx_reset_chip, 1879 .chip_diag = qla24xx_chip_diag, 1880 .config_rings = qla24xx_config_rings, 1881 .reset_adapter = qla24xx_reset_adapter, 1882 .nvram_config = qla81xx_nvram_config, 1883 .update_fw_options = qla81xx_update_fw_options, 1884 .load_risc = qla81xx_load_risc, 1885 .pci_info_str = qla24xx_pci_info_str, 1886 .fw_version_str = qla24xx_fw_version_str, 1887 .intr_handler = qla24xx_intr_handler, 1888 .enable_intrs = qla24xx_enable_intrs, 1889 .disable_intrs = qla24xx_disable_intrs, 1890 .abort_command = qla24xx_abort_command, 1891 .target_reset = qla24xx_abort_target, 1892 .lun_reset = qla24xx_lun_reset, 1893 .fabric_login = qla24xx_login_fabric, 1894 .fabric_logout = qla24xx_fabric_logout, 1895 .calc_req_entries = NULL, 1896 .build_iocbs = NULL, 1897 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1898 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1899 .read_nvram = NULL, 1900 .write_nvram = NULL, 1901 .fw_dump = qla81xx_fw_dump, 1902 .beacon_on = qla24xx_beacon_on, 1903 .beacon_off = qla24xx_beacon_off, 1904 .beacon_blink = qla83xx_beacon_blink, 1905 .read_optrom = qla25xx_read_optrom_data, 1906 .write_optrom = qla24xx_write_optrom_data, 1907 .get_flash_version = qla24xx_get_flash_version, 1908 .start_scsi = qla24xx_dif_start_scsi, 1909 .abort_isp = qla2x00_abort_isp, 1910 .iospace_config = qla2x00_iospace_config, 1911 }; 1912 1913 static struct isp_operations qla82xx_isp_ops = { 1914 .pci_config = qla82xx_pci_config, 1915 .reset_chip = qla82xx_reset_chip, 1916 .chip_diag = qla24xx_chip_diag, 1917 .config_rings = qla82xx_config_rings, 1918 .reset_adapter = qla24xx_reset_adapter, 1919 .nvram_config = qla81xx_nvram_config, 1920 .update_fw_options = qla24xx_update_fw_options, 1921 .load_risc = qla82xx_load_risc, 1922 .pci_info_str = qla82xx_pci_info_str, 1923 .fw_version_str = qla24xx_fw_version_str, 1924 .intr_handler = qla82xx_intr_handler, 1925 .enable_intrs = qla82xx_enable_intrs, 1926 .disable_intrs = qla82xx_disable_intrs, 1927 .abort_command = qla24xx_abort_command, 1928 .target_reset = qla24xx_abort_target, 1929 .lun_reset = qla24xx_lun_reset, 1930 .fabric_login = qla24xx_login_fabric, 1931 .fabric_logout = qla24xx_fabric_logout, 1932 .calc_req_entries = NULL, 1933 .build_iocbs = NULL, 1934 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1935 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1936 .read_nvram = qla24xx_read_nvram_data, 1937 .write_nvram = qla24xx_write_nvram_data, 1938 .fw_dump = qla24xx_fw_dump, 1939 .beacon_on = qla82xx_beacon_on, 1940 .beacon_off = qla82xx_beacon_off, 1941 .beacon_blink = NULL, 1942 .read_optrom = qla82xx_read_optrom_data, 1943 .write_optrom = qla82xx_write_optrom_data, 1944 .get_flash_version = qla24xx_get_flash_version, 1945 .start_scsi = qla82xx_start_scsi, 1946 .abort_isp = qla82xx_abort_isp, 1947 .iospace_config = qla82xx_iospace_config, 1948 }; 1949 1950 static struct isp_operations qla83xx_isp_ops = { 1951 .pci_config = qla25xx_pci_config, 1952 .reset_chip = qla24xx_reset_chip, 1953 .chip_diag = qla24xx_chip_diag, 1954 .config_rings = qla24xx_config_rings, 1955 .reset_adapter = qla24xx_reset_adapter, 1956 .nvram_config = qla81xx_nvram_config, 1957 .update_fw_options = qla81xx_update_fw_options, 1958 .load_risc = qla81xx_load_risc, 1959 .pci_info_str = qla24xx_pci_info_str, 1960 .fw_version_str = qla24xx_fw_version_str, 1961 .intr_handler = qla24xx_intr_handler, 1962 .enable_intrs = qla24xx_enable_intrs, 1963 .disable_intrs = qla24xx_disable_intrs, 1964 .abort_command = qla24xx_abort_command, 1965 .target_reset = qla24xx_abort_target, 1966 .lun_reset = qla24xx_lun_reset, 1967 .fabric_login = qla24xx_login_fabric, 1968 .fabric_logout = qla24xx_fabric_logout, 1969 .calc_req_entries = NULL, 1970 .build_iocbs = NULL, 1971 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1972 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1973 .read_nvram = NULL, 1974 .write_nvram = NULL, 1975 .fw_dump = qla83xx_fw_dump, 1976 .beacon_on = qla24xx_beacon_on, 1977 .beacon_off = qla24xx_beacon_off, 1978 .beacon_blink = qla83xx_beacon_blink, 1979 .read_optrom = qla25xx_read_optrom_data, 1980 .write_optrom = qla24xx_write_optrom_data, 1981 .get_flash_version = qla24xx_get_flash_version, 1982 .start_scsi = qla24xx_dif_start_scsi, 1983 .abort_isp = qla2x00_abort_isp, 1984 .iospace_config = qla83xx_iospace_config, 1985 }; 1986 1987 static inline void 1988 qla2x00_set_isp_flags(struct qla_hw_data *ha) 1989 { 1990 ha->device_type = DT_EXTENDED_IDS; 1991 switch (ha->pdev->device) { 1992 case PCI_DEVICE_ID_QLOGIC_ISP2100: 1993 ha->device_type |= DT_ISP2100; 1994 ha->device_type &= ~DT_EXTENDED_IDS; 1995 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1996 break; 1997 case PCI_DEVICE_ID_QLOGIC_ISP2200: 1998 ha->device_type |= DT_ISP2200; 1999 ha->device_type &= ~DT_EXTENDED_IDS; 2000 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2001 break; 2002 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2003 ha->device_type |= DT_ISP2300; 2004 ha->device_type |= DT_ZIO_SUPPORTED; 2005 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2006 break; 2007 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2008 ha->device_type |= DT_ISP2312; 2009 ha->device_type |= DT_ZIO_SUPPORTED; 2010 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2011 break; 2012 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2013 ha->device_type |= DT_ISP2322; 2014 ha->device_type |= DT_ZIO_SUPPORTED; 2015 if (ha->pdev->subsystem_vendor == 0x1028 && 2016 ha->pdev->subsystem_device == 0x0170) 2017 ha->device_type |= DT_OEM_001; 2018 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2019 break; 2020 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2021 ha->device_type |= DT_ISP6312; 2022 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2023 break; 2024 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2025 ha->device_type |= DT_ISP6322; 2026 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2027 break; 2028 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2029 ha->device_type |= DT_ISP2422; 2030 ha->device_type |= DT_ZIO_SUPPORTED; 2031 ha->device_type |= DT_FWI2; 2032 ha->device_type |= DT_IIDMA; 2033 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2034 break; 2035 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2036 ha->device_type |= DT_ISP2432; 2037 ha->device_type |= DT_ZIO_SUPPORTED; 2038 ha->device_type |= DT_FWI2; 2039 ha->device_type |= DT_IIDMA; 2040 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2041 break; 2042 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2043 ha->device_type |= DT_ISP8432; 2044 ha->device_type |= DT_ZIO_SUPPORTED; 2045 ha->device_type |= DT_FWI2; 2046 ha->device_type |= DT_IIDMA; 2047 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2048 break; 2049 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2050 ha->device_type |= DT_ISP5422; 2051 ha->device_type |= DT_FWI2; 2052 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2053 break; 2054 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2055 ha->device_type |= DT_ISP5432; 2056 ha->device_type |= DT_FWI2; 2057 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2058 break; 2059 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2060 ha->device_type |= DT_ISP2532; 2061 ha->device_type |= DT_ZIO_SUPPORTED; 2062 ha->device_type |= DT_FWI2; 2063 ha->device_type |= DT_IIDMA; 2064 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2065 break; 2066 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2067 ha->device_type |= DT_ISP8001; 2068 ha->device_type |= DT_ZIO_SUPPORTED; 2069 ha->device_type |= DT_FWI2; 2070 ha->device_type |= DT_IIDMA; 2071 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2072 break; 2073 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2074 ha->device_type |= DT_ISP8021; 2075 ha->device_type |= DT_ZIO_SUPPORTED; 2076 ha->device_type |= DT_FWI2; 2077 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2078 /* Initialize 82XX ISP flags */ 2079 qla82xx_init_flags(ha); 2080 break; 2081 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2082 ha->device_type |= DT_ISP2031; 2083 ha->device_type |= DT_ZIO_SUPPORTED; 2084 ha->device_type |= DT_FWI2; 2085 ha->device_type |= DT_IIDMA; 2086 ha->device_type |= DT_T10_PI; 2087 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2088 break; 2089 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2090 ha->device_type |= DT_ISP8031; 2091 ha->device_type |= DT_ZIO_SUPPORTED; 2092 ha->device_type |= DT_FWI2; 2093 ha->device_type |= DT_IIDMA; 2094 ha->device_type |= DT_T10_PI; 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2096 break; 2097 } 2098 2099 if (IS_QLA82XX(ha)) 2100 ha->port_no = !(ha->portnum & 1); 2101 else 2102 /* Get adapter physical port no from interrupt pin register. */ 2103 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2104 2105 if (ha->port_no & 1) 2106 ha->flags.port0 = 1; 2107 else 2108 ha->flags.port0 = 0; 2109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2110 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2111 ha->device_type, ha->flags.port0, ha->fw_srisc_address); 2112 } 2113 2114 static void 2115 qla2xxx_scan_start(struct Scsi_Host *shost) 2116 { 2117 scsi_qla_host_t *vha = shost_priv(shost); 2118 2119 if (vha->hw->flags.running_gold_fw) 2120 return; 2121 2122 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2123 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2124 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2125 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2126 } 2127 2128 static int 2129 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2130 { 2131 scsi_qla_host_t *vha = shost_priv(shost); 2132 2133 if (!vha->host) 2134 return 1; 2135 if (time > vha->hw->loop_reset_delay * HZ) 2136 return 1; 2137 2138 return atomic_read(&vha->loop_state) == LOOP_READY; 2139 } 2140 2141 /* 2142 * PCI driver interface 2143 */ 2144 static int __devinit 2145 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2146 { 2147 int ret = -ENODEV; 2148 struct Scsi_Host *host; 2149 scsi_qla_host_t *base_vha = NULL; 2150 struct qla_hw_data *ha; 2151 char pci_info[30]; 2152 char fw_str[30]; 2153 struct scsi_host_template *sht; 2154 int bars, mem_only = 0; 2155 uint16_t req_length = 0, rsp_length = 0; 2156 struct req_que *req = NULL; 2157 struct rsp_que *rsp = NULL; 2158 2159 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2160 sht = &qla2xxx_driver_template; 2161 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2162 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2163 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2164 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2165 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2166 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2167 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2168 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2169 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2170 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) { 2171 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2172 mem_only = 1; 2173 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2174 "Mem only adapter.\n"); 2175 } 2176 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2177 "Bars=%d.\n", bars); 2178 2179 if (mem_only) { 2180 if (pci_enable_device_mem(pdev)) 2181 goto probe_out; 2182 } else { 2183 if (pci_enable_device(pdev)) 2184 goto probe_out; 2185 } 2186 2187 /* This may fail but that's ok */ 2188 pci_enable_pcie_error_reporting(pdev); 2189 2190 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2191 if (!ha) { 2192 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2193 "Unable to allocate memory for ha.\n"); 2194 goto probe_out; 2195 } 2196 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2197 "Memory allocated for ha=%p.\n", ha); 2198 ha->pdev = pdev; 2199 ha->tgt.enable_class_2 = ql2xenableclass2; 2200 2201 /* Clear our data area */ 2202 ha->bars = bars; 2203 ha->mem_only = mem_only; 2204 spin_lock_init(&ha->hardware_lock); 2205 spin_lock_init(&ha->vport_slock); 2206 2207 /* Set ISP-type information. */ 2208 qla2x00_set_isp_flags(ha); 2209 2210 /* Set EEH reset type to fundamental if required by hba */ 2211 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) 2212 pdev->needs_freset = 1; 2213 2214 ha->prev_topology = 0; 2215 ha->init_cb_size = sizeof(init_cb_t); 2216 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2217 ha->optrom_size = OPTROM_SIZE_2300; 2218 2219 /* Assign ISP specific operations. */ 2220 if (IS_QLA2100(ha)) { 2221 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2222 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2223 req_length = REQUEST_ENTRY_CNT_2100; 2224 rsp_length = RESPONSE_ENTRY_CNT_2100; 2225 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2226 ha->gid_list_info_size = 4; 2227 ha->flash_conf_off = ~0; 2228 ha->flash_data_off = ~0; 2229 ha->nvram_conf_off = ~0; 2230 ha->nvram_data_off = ~0; 2231 ha->isp_ops = &qla2100_isp_ops; 2232 } else if (IS_QLA2200(ha)) { 2233 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2234 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2235 req_length = REQUEST_ENTRY_CNT_2200; 2236 rsp_length = RESPONSE_ENTRY_CNT_2100; 2237 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2238 ha->gid_list_info_size = 4; 2239 ha->flash_conf_off = ~0; 2240 ha->flash_data_off = ~0; 2241 ha->nvram_conf_off = ~0; 2242 ha->nvram_data_off = ~0; 2243 ha->isp_ops = &qla2100_isp_ops; 2244 } else if (IS_QLA23XX(ha)) { 2245 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2246 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2247 req_length = REQUEST_ENTRY_CNT_2200; 2248 rsp_length = RESPONSE_ENTRY_CNT_2300; 2249 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2250 ha->gid_list_info_size = 6; 2251 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2252 ha->optrom_size = OPTROM_SIZE_2322; 2253 ha->flash_conf_off = ~0; 2254 ha->flash_data_off = ~0; 2255 ha->nvram_conf_off = ~0; 2256 ha->nvram_data_off = ~0; 2257 ha->isp_ops = &qla2300_isp_ops; 2258 } else if (IS_QLA24XX_TYPE(ha)) { 2259 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2260 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2261 req_length = REQUEST_ENTRY_CNT_24XX; 2262 rsp_length = RESPONSE_ENTRY_CNT_2300; 2263 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2264 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2265 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2266 ha->gid_list_info_size = 8; 2267 ha->optrom_size = OPTROM_SIZE_24XX; 2268 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2269 ha->isp_ops = &qla24xx_isp_ops; 2270 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2271 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2272 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2273 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2274 } else if (IS_QLA25XX(ha)) { 2275 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2276 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2277 req_length = REQUEST_ENTRY_CNT_24XX; 2278 rsp_length = RESPONSE_ENTRY_CNT_2300; 2279 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2280 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2281 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2282 ha->gid_list_info_size = 8; 2283 ha->optrom_size = OPTROM_SIZE_25XX; 2284 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2285 ha->isp_ops = &qla25xx_isp_ops; 2286 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2287 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2288 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2289 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2290 } else if (IS_QLA81XX(ha)) { 2291 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2292 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2293 req_length = REQUEST_ENTRY_CNT_24XX; 2294 rsp_length = RESPONSE_ENTRY_CNT_2300; 2295 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2296 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2297 ha->gid_list_info_size = 8; 2298 ha->optrom_size = OPTROM_SIZE_81XX; 2299 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2300 ha->isp_ops = &qla81xx_isp_ops; 2301 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2302 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2303 ha->nvram_conf_off = ~0; 2304 ha->nvram_data_off = ~0; 2305 } else if (IS_QLA82XX(ha)) { 2306 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2307 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2308 req_length = REQUEST_ENTRY_CNT_82XX; 2309 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2310 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2311 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2312 ha->gid_list_info_size = 8; 2313 ha->optrom_size = OPTROM_SIZE_82XX; 2314 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2315 ha->isp_ops = &qla82xx_isp_ops; 2316 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2317 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2318 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2319 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2320 } else if (IS_QLA83XX(ha)) { 2321 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2322 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2323 req_length = REQUEST_ENTRY_CNT_24XX; 2324 rsp_length = RESPONSE_ENTRY_CNT_2300; 2325 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2326 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2327 ha->gid_list_info_size = 8; 2328 ha->optrom_size = OPTROM_SIZE_83XX; 2329 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2330 ha->isp_ops = &qla83xx_isp_ops; 2331 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2332 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2333 ha->nvram_conf_off = ~0; 2334 ha->nvram_data_off = ~0; 2335 } 2336 2337 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2338 "mbx_count=%d, req_length=%d, " 2339 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2340 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2341 "max_fibre_devices=%d.\n", 2342 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2343 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2344 ha->nvram_npiv_size, ha->max_fibre_devices); 2345 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2346 "isp_ops=%p, flash_conf_off=%d, " 2347 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2348 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2349 ha->nvram_conf_off, ha->nvram_data_off); 2350 2351 /* Configure PCI I/O space */ 2352 ret = ha->isp_ops->iospace_config(ha); 2353 if (ret) 2354 goto probe_hw_failed; 2355 2356 ql_log_pci(ql_log_info, pdev, 0x001d, 2357 "Found an ISP%04X irq %d iobase 0x%p.\n", 2358 pdev->device, pdev->irq, ha->iobase); 2359 mutex_init(&ha->vport_lock); 2360 init_completion(&ha->mbx_cmd_comp); 2361 complete(&ha->mbx_cmd_comp); 2362 init_completion(&ha->mbx_intr_comp); 2363 init_completion(&ha->dcbx_comp); 2364 2365 set_bit(0, (unsigned long *) ha->vp_idx_map); 2366 2367 qla2x00_config_dma_addressing(ha); 2368 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2369 "64 Bit addressing is %s.\n", 2370 ha->flags.enable_64bit_addressing ? "enable" : 2371 "disable"); 2372 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2373 if (!ret) { 2374 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2375 "Failed to allocate memory for adapter, aborting.\n"); 2376 2377 goto probe_hw_failed; 2378 } 2379 2380 req->max_q_depth = MAX_Q_DEPTH; 2381 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2382 req->max_q_depth = ql2xmaxqdepth; 2383 2384 2385 base_vha = qla2x00_create_host(sht, ha); 2386 if (!base_vha) { 2387 ret = -ENOMEM; 2388 qla2x00_mem_free(ha); 2389 qla2x00_free_req_que(ha, req); 2390 qla2x00_free_rsp_que(ha, rsp); 2391 goto probe_hw_failed; 2392 } 2393 2394 pci_set_drvdata(pdev, base_vha); 2395 2396 host = base_vha->host; 2397 base_vha->req = req; 2398 host->can_queue = req->length + 128; 2399 if (IS_QLA2XXX_MIDTYPE(ha)) 2400 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2401 else 2402 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2403 base_vha->vp_idx; 2404 2405 /* Set the SG table size based on ISP type */ 2406 if (!IS_FWI2_CAPABLE(ha)) { 2407 if (IS_QLA2100(ha)) 2408 host->sg_tablesize = 32; 2409 } else { 2410 if (!IS_QLA82XX(ha)) 2411 host->sg_tablesize = QLA_SG_ALL; 2412 } 2413 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2414 "can_queue=%d, req=%p, " 2415 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2416 host->can_queue, base_vha->req, 2417 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2418 host->max_id = ha->max_fibre_devices; 2419 host->this_id = 255; 2420 host->cmd_per_lun = 3; 2421 host->unique_id = host->host_no; 2422 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2423 host->max_cmd_len = 32; 2424 else 2425 host->max_cmd_len = MAX_CMDSZ; 2426 host->max_channel = MAX_BUSES - 1; 2427 host->max_lun = ql2xmaxlun; 2428 host->transportt = qla2xxx_transport_template; 2429 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2430 2431 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2432 "max_id=%d this_id=%d " 2433 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2434 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, 2435 host->this_id, host->cmd_per_lun, host->unique_id, 2436 host->max_cmd_len, host->max_channel, host->max_lun, 2437 host->transportt, sht->vendor_id); 2438 2439 que_init: 2440 /* Alloc arrays of request and response ring ptrs */ 2441 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2442 ql_log(ql_log_fatal, base_vha, 0x003d, 2443 "Failed to allocate memory for queue pointers..." 2444 "aborting.\n"); 2445 goto probe_init_failed; 2446 } 2447 2448 qlt_probe_one_stage1(base_vha, ha); 2449 2450 /* Set up the irqs */ 2451 ret = qla2x00_request_irqs(ha, rsp); 2452 if (ret) 2453 goto probe_init_failed; 2454 2455 pci_save_state(pdev); 2456 2457 /* Assign back pointers */ 2458 rsp->req = req; 2459 req->rsp = rsp; 2460 2461 /* FWI2-capable only. */ 2462 req->req_q_in = &ha->iobase->isp24.req_q_in; 2463 req->req_q_out = &ha->iobase->isp24.req_q_out; 2464 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2465 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2466 if (ha->mqenable || IS_QLA83XX(ha)) { 2467 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2468 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2469 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2470 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2471 } 2472 2473 if (IS_QLA82XX(ha)) { 2474 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2475 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2476 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2477 } 2478 2479 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2480 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2481 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2482 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2483 "req->req_q_in=%p req->req_q_out=%p " 2484 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2485 req->req_q_in, req->req_q_out, 2486 rsp->rsp_q_in, rsp->rsp_q_out); 2487 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2488 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2489 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2490 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2491 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2492 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2493 2494 if (qla2x00_initialize_adapter(base_vha)) { 2495 ql_log(ql_log_fatal, base_vha, 0x00d6, 2496 "Failed to initialize adapter - Adapter flags %x.\n", 2497 base_vha->device_flags); 2498 2499 if (IS_QLA82XX(ha)) { 2500 qla82xx_idc_lock(ha); 2501 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2502 QLA82XX_DEV_FAILED); 2503 qla82xx_idc_unlock(ha); 2504 ql_log(ql_log_fatal, base_vha, 0x00d7, 2505 "HW State: FAILED.\n"); 2506 } 2507 2508 ret = -ENODEV; 2509 goto probe_failed; 2510 } 2511 2512 if (ha->mqenable) { 2513 if (qla25xx_setup_mode(base_vha)) { 2514 ql_log(ql_log_warn, base_vha, 0x00ec, 2515 "Failed to create queues, falling back to single queue mode.\n"); 2516 goto que_init; 2517 } 2518 } 2519 2520 if (ha->flags.running_gold_fw) 2521 goto skip_dpc; 2522 2523 /* 2524 * Startup the kernel thread for this host adapter 2525 */ 2526 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2527 "%s_dpc", base_vha->host_str); 2528 if (IS_ERR(ha->dpc_thread)) { 2529 ql_log(ql_log_fatal, base_vha, 0x00ed, 2530 "Failed to start DPC thread.\n"); 2531 ret = PTR_ERR(ha->dpc_thread); 2532 goto probe_failed; 2533 } 2534 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2535 "DPC thread started successfully.\n"); 2536 2537 /* 2538 * If we're not coming up in initiator mode, we might sit for 2539 * a while without waking up the dpc thread, which leads to a 2540 * stuck process warning. So just kick the dpc once here and 2541 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2542 */ 2543 qla2xxx_wake_dpc(base_vha); 2544 2545 skip_dpc: 2546 list_add_tail(&base_vha->list, &ha->vp_list); 2547 base_vha->host->irq = ha->pdev->irq; 2548 2549 /* Initialized the timer */ 2550 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2551 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2552 "Started qla2x00_timer with " 2553 "interval=%d.\n", WATCH_INTERVAL); 2554 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2555 "Detected hba at address=%p.\n", 2556 ha); 2557 2558 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2559 if (ha->fw_attributes & BIT_4) { 2560 int prot = 0; 2561 base_vha->flags.difdix_supported = 1; 2562 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2563 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2564 if (ql2xenabledif == 1) 2565 prot = SHOST_DIX_TYPE0_PROTECTION; 2566 scsi_host_set_prot(host, 2567 prot | SHOST_DIF_TYPE1_PROTECTION 2568 | SHOST_DIF_TYPE2_PROTECTION 2569 | SHOST_DIF_TYPE3_PROTECTION 2570 | SHOST_DIX_TYPE1_PROTECTION 2571 | SHOST_DIX_TYPE2_PROTECTION 2572 | SHOST_DIX_TYPE3_PROTECTION); 2573 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); 2574 } else 2575 base_vha->flags.difdix_supported = 0; 2576 } 2577 2578 ha->isp_ops->enable_intrs(ha); 2579 2580 ret = scsi_add_host(host, &pdev->dev); 2581 if (ret) 2582 goto probe_failed; 2583 2584 base_vha->flags.init_done = 1; 2585 base_vha->flags.online = 1; 2586 2587 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2588 "Init done and hba is online.\n"); 2589 2590 if (qla_ini_mode_enabled(base_vha)) 2591 scsi_scan_host(host); 2592 else 2593 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2594 "skipping scsi_scan_host() for non-initiator port\n"); 2595 2596 qla2x00_alloc_sysfs_attr(base_vha); 2597 2598 qla2x00_init_host_attr(base_vha); 2599 2600 qla2x00_dfs_setup(base_vha); 2601 2602 ql_log(ql_log_info, base_vha, 0x00fb, 2603 "QLogic %s - %s.\n", 2604 ha->model_number, ha->model_desc ? ha->model_desc : ""); 2605 ql_log(ql_log_info, base_vha, 0x00fc, 2606 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2607 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2608 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2609 base_vha->host_no, 2610 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2611 2612 qlt_add_target(ha, base_vha); 2613 2614 return 0; 2615 2616 probe_init_failed: 2617 qla2x00_free_req_que(ha, req); 2618 ha->req_q_map[0] = NULL; 2619 clear_bit(0, ha->req_qid_map); 2620 qla2x00_free_rsp_que(ha, rsp); 2621 ha->rsp_q_map[0] = NULL; 2622 clear_bit(0, ha->rsp_qid_map); 2623 ha->max_req_queues = ha->max_rsp_queues = 0; 2624 2625 probe_failed: 2626 if (base_vha->timer_active) 2627 qla2x00_stop_timer(base_vha); 2628 base_vha->flags.online = 0; 2629 if (ha->dpc_thread) { 2630 struct task_struct *t = ha->dpc_thread; 2631 2632 ha->dpc_thread = NULL; 2633 kthread_stop(t); 2634 } 2635 2636 qla2x00_free_device(base_vha); 2637 2638 scsi_host_put(base_vha->host); 2639 2640 probe_hw_failed: 2641 if (IS_QLA82XX(ha)) { 2642 qla82xx_idc_lock(ha); 2643 qla82xx_clear_drv_active(ha); 2644 qla82xx_idc_unlock(ha); 2645 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2646 if (!ql2xdbwr) 2647 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2648 } else { 2649 if (ha->iobase) 2650 iounmap(ha->iobase); 2651 } 2652 pci_release_selected_regions(ha->pdev, ha->bars); 2653 kfree(ha); 2654 ha = NULL; 2655 2656 probe_out: 2657 pci_disable_device(pdev); 2658 return ret; 2659 } 2660 2661 static void 2662 qla2x00_stop_dpc_thread(scsi_qla_host_t *vha) 2663 { 2664 struct qla_hw_data *ha = vha->hw; 2665 struct task_struct *t = ha->dpc_thread; 2666 2667 if (ha->dpc_thread == NULL) 2668 return; 2669 /* 2670 * qla2xxx_wake_dpc checks for ->dpc_thread 2671 * so we need to zero it out. 2672 */ 2673 ha->dpc_thread = NULL; 2674 kthread_stop(t); 2675 } 2676 2677 static void 2678 qla2x00_shutdown(struct pci_dev *pdev) 2679 { 2680 scsi_qla_host_t *vha; 2681 struct qla_hw_data *ha; 2682 2683 vha = pci_get_drvdata(pdev); 2684 ha = vha->hw; 2685 2686 /* Turn-off FCE trace */ 2687 if (ha->flags.fce_enabled) { 2688 qla2x00_disable_fce_trace(vha, NULL, NULL); 2689 ha->flags.fce_enabled = 0; 2690 } 2691 2692 /* Turn-off EFT trace */ 2693 if (ha->eft) 2694 qla2x00_disable_eft_trace(vha); 2695 2696 /* Stop currently executing firmware. */ 2697 qla2x00_try_to_stop_firmware(vha); 2698 2699 /* Turn adapter off line */ 2700 vha->flags.online = 0; 2701 2702 /* turn-off interrupts on the card */ 2703 if (ha->interrupts_on) { 2704 vha->flags.init_done = 0; 2705 ha->isp_ops->disable_intrs(ha); 2706 } 2707 2708 qla2x00_free_irqs(vha); 2709 2710 qla2x00_free_fw_dump(ha); 2711 } 2712 2713 static void 2714 qla2x00_remove_one(struct pci_dev *pdev) 2715 { 2716 scsi_qla_host_t *base_vha, *vha; 2717 struct qla_hw_data *ha; 2718 unsigned long flags; 2719 2720 /* 2721 * If the PCI device is disabled that means that probe failed and any 2722 * resources should be have cleaned up on probe exit. 2723 */ 2724 if (!atomic_read(&pdev->enable_cnt)) 2725 return; 2726 2727 base_vha = pci_get_drvdata(pdev); 2728 ha = base_vha->hw; 2729 2730 ha->flags.host_shutting_down = 1; 2731 2732 mutex_lock(&ha->vport_lock); 2733 while (ha->cur_vport_count) { 2734 struct Scsi_Host *scsi_host; 2735 2736 spin_lock_irqsave(&ha->vport_slock, flags); 2737 2738 BUG_ON(base_vha->list.next == &ha->vp_list); 2739 /* This assumes first entry in ha->vp_list is always base vha */ 2740 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2741 scsi_host = scsi_host_get(vha->host); 2742 2743 spin_unlock_irqrestore(&ha->vport_slock, flags); 2744 mutex_unlock(&ha->vport_lock); 2745 2746 fc_vport_terminate(vha->fc_vport); 2747 scsi_host_put(vha->host); 2748 2749 mutex_lock(&ha->vport_lock); 2750 } 2751 mutex_unlock(&ha->vport_lock); 2752 2753 set_bit(UNLOADING, &base_vha->dpc_flags); 2754 2755 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 2756 2757 qla2x00_dfs_remove(base_vha); 2758 2759 qla84xx_put_chip(base_vha); 2760 2761 /* Disable timer */ 2762 if (base_vha->timer_active) 2763 qla2x00_stop_timer(base_vha); 2764 2765 base_vha->flags.online = 0; 2766 2767 /* Flush the work queue and remove it */ 2768 if (ha->wq) { 2769 flush_workqueue(ha->wq); 2770 destroy_workqueue(ha->wq); 2771 ha->wq = NULL; 2772 } 2773 2774 /* Kill the kernel thread for this host */ 2775 if (ha->dpc_thread) { 2776 struct task_struct *t = ha->dpc_thread; 2777 2778 /* 2779 * qla2xxx_wake_dpc checks for ->dpc_thread 2780 * so we need to zero it out. 2781 */ 2782 ha->dpc_thread = NULL; 2783 kthread_stop(t); 2784 } 2785 qlt_remove_target(ha, base_vha); 2786 2787 qla2x00_free_sysfs_attr(base_vha); 2788 2789 fc_remove_host(base_vha->host); 2790 2791 scsi_remove_host(base_vha->host); 2792 2793 qla2x00_free_device(base_vha); 2794 2795 scsi_host_put(base_vha->host); 2796 2797 if (IS_QLA82XX(ha)) { 2798 qla82xx_idc_lock(ha); 2799 qla82xx_clear_drv_active(ha); 2800 qla82xx_idc_unlock(ha); 2801 2802 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2803 if (!ql2xdbwr) 2804 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2805 } else { 2806 if (ha->iobase) 2807 iounmap(ha->iobase); 2808 2809 if (ha->mqiobase) 2810 iounmap(ha->mqiobase); 2811 2812 if (IS_QLA83XX(ha) && ha->msixbase) 2813 iounmap(ha->msixbase); 2814 } 2815 2816 pci_release_selected_regions(ha->pdev, ha->bars); 2817 kfree(ha); 2818 ha = NULL; 2819 2820 pci_disable_pcie_error_reporting(pdev); 2821 2822 pci_disable_device(pdev); 2823 pci_set_drvdata(pdev, NULL); 2824 } 2825 2826 static void 2827 qla2x00_free_device(scsi_qla_host_t *vha) 2828 { 2829 struct qla_hw_data *ha = vha->hw; 2830 2831 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2832 2833 /* Disable timer */ 2834 if (vha->timer_active) 2835 qla2x00_stop_timer(vha); 2836 2837 qla2x00_stop_dpc_thread(vha); 2838 2839 qla25xx_delete_queues(vha); 2840 2841 if (ha->flags.fce_enabled) 2842 qla2x00_disable_fce_trace(vha, NULL, NULL); 2843 2844 if (ha->eft) 2845 qla2x00_disable_eft_trace(vha); 2846 2847 /* Stop currently executing firmware. */ 2848 qla2x00_try_to_stop_firmware(vha); 2849 2850 vha->flags.online = 0; 2851 2852 /* turn-off interrupts on the card */ 2853 if (ha->interrupts_on) { 2854 vha->flags.init_done = 0; 2855 ha->isp_ops->disable_intrs(ha); 2856 } 2857 2858 qla2x00_free_irqs(vha); 2859 2860 qla2x00_free_fcports(vha); 2861 2862 qla2x00_mem_free(ha); 2863 2864 qla82xx_md_free(vha); 2865 2866 qla2x00_free_queues(ha); 2867 } 2868 2869 void qla2x00_free_fcports(struct scsi_qla_host *vha) 2870 { 2871 fc_port_t *fcport, *tfcport; 2872 2873 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 2874 list_del(&fcport->list); 2875 kfree(fcport); 2876 fcport = NULL; 2877 } 2878 } 2879 2880 static inline void 2881 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 2882 int defer) 2883 { 2884 struct fc_rport *rport; 2885 scsi_qla_host_t *base_vha; 2886 unsigned long flags; 2887 2888 if (!fcport->rport) 2889 return; 2890 2891 rport = fcport->rport; 2892 if (defer) { 2893 base_vha = pci_get_drvdata(vha->hw->pdev); 2894 spin_lock_irqsave(vha->host->host_lock, flags); 2895 fcport->drport = rport; 2896 spin_unlock_irqrestore(vha->host->host_lock, flags); 2897 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 2898 qla2xxx_wake_dpc(base_vha); 2899 } else { 2900 fc_remote_port_delete(rport); 2901 qlt_fc_port_deleted(vha, fcport); 2902 } 2903 } 2904 2905 /* 2906 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 2907 * 2908 * Input: ha = adapter block pointer. fcport = port structure pointer. 2909 * 2910 * Return: None. 2911 * 2912 * Context: 2913 */ 2914 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 2915 int do_login, int defer) 2916 { 2917 if (atomic_read(&fcport->state) == FCS_ONLINE && 2918 vha->vp_idx == fcport->vha->vp_idx) { 2919 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2920 qla2x00_schedule_rport_del(vha, fcport, defer); 2921 } 2922 /* 2923 * We may need to retry the login, so don't change the state of the 2924 * port but do the retries. 2925 */ 2926 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 2927 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2928 2929 if (!do_login) 2930 return; 2931 2932 if (fcport->login_retry == 0) { 2933 fcport->login_retry = vha->hw->login_retry_count; 2934 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2935 2936 ql_dbg(ql_dbg_disc, vha, 0x2067, 2937 "Port login retry " 2938 "%02x%02x%02x%02x%02x%02x%02x%02x, " 2939 "id = 0x%04x retry cnt=%d.\n", 2940 fcport->port_name[0], fcport->port_name[1], 2941 fcport->port_name[2], fcport->port_name[3], 2942 fcport->port_name[4], fcport->port_name[5], 2943 fcport->port_name[6], fcport->port_name[7], 2944 fcport->loop_id, fcport->login_retry); 2945 } 2946 } 2947 2948 /* 2949 * qla2x00_mark_all_devices_lost 2950 * Updates fcport state when device goes offline. 2951 * 2952 * Input: 2953 * ha = adapter block pointer. 2954 * fcport = port structure pointer. 2955 * 2956 * Return: 2957 * None. 2958 * 2959 * Context: 2960 */ 2961 void 2962 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 2963 { 2964 fc_port_t *fcport; 2965 2966 list_for_each_entry(fcport, &vha->vp_fcports, list) { 2967 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 2968 continue; 2969 2970 /* 2971 * No point in marking the device as lost, if the device is 2972 * already DEAD. 2973 */ 2974 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 2975 continue; 2976 if (atomic_read(&fcport->state) == FCS_ONLINE) { 2977 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2978 if (defer) 2979 qla2x00_schedule_rport_del(vha, fcport, defer); 2980 else if (vha->vp_idx == fcport->vha->vp_idx) 2981 qla2x00_schedule_rport_del(vha, fcport, defer); 2982 } 2983 } 2984 } 2985 2986 /* 2987 * qla2x00_mem_alloc 2988 * Allocates adapter memory. 2989 * 2990 * Returns: 2991 * 0 = success. 2992 * !0 = failure. 2993 */ 2994 static int 2995 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 2996 struct req_que **req, struct rsp_que **rsp) 2997 { 2998 char name[16]; 2999 3000 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3001 &ha->init_cb_dma, GFP_KERNEL); 3002 if (!ha->init_cb) 3003 goto fail; 3004 3005 if (qlt_mem_alloc(ha) < 0) 3006 goto fail_free_init_cb; 3007 3008 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3009 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3010 if (!ha->gid_list) 3011 goto fail_free_tgt_mem; 3012 3013 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3014 if (!ha->srb_mempool) 3015 goto fail_free_gid_list; 3016 3017 if (IS_QLA82XX(ha)) { 3018 /* Allocate cache for CT6 Ctx. */ 3019 if (!ctx_cachep) { 3020 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3021 sizeof(struct ct6_dsd), 0, 3022 SLAB_HWCACHE_ALIGN, NULL); 3023 if (!ctx_cachep) 3024 goto fail_free_gid_list; 3025 } 3026 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3027 ctx_cachep); 3028 if (!ha->ctx_mempool) 3029 goto fail_free_srb_mempool; 3030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3031 "ctx_cachep=%p ctx_mempool=%p.\n", 3032 ctx_cachep, ha->ctx_mempool); 3033 } 3034 3035 /* Get memory for cached NVRAM */ 3036 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3037 if (!ha->nvram) 3038 goto fail_free_ctx_mempool; 3039 3040 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3041 ha->pdev->device); 3042 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3043 DMA_POOL_SIZE, 8, 0); 3044 if (!ha->s_dma_pool) 3045 goto fail_free_nvram; 3046 3047 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3048 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3049 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3050 3051 if (IS_QLA82XX(ha) || ql2xenabledif) { 3052 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3053 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3054 if (!ha->dl_dma_pool) { 3055 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3056 "Failed to allocate memory for dl_dma_pool.\n"); 3057 goto fail_s_dma_pool; 3058 } 3059 3060 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3061 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3062 if (!ha->fcp_cmnd_dma_pool) { 3063 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3064 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3065 goto fail_dl_dma_pool; 3066 } 3067 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3068 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3069 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3070 } 3071 3072 /* Allocate memory for SNS commands */ 3073 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3074 /* Get consistent memory allocated for SNS commands */ 3075 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3076 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3077 if (!ha->sns_cmd) 3078 goto fail_dma_pool; 3079 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3080 "sns_cmd: %p.\n", ha->sns_cmd); 3081 } else { 3082 /* Get consistent memory allocated for MS IOCB */ 3083 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3084 &ha->ms_iocb_dma); 3085 if (!ha->ms_iocb) 3086 goto fail_dma_pool; 3087 /* Get consistent memory allocated for CT SNS commands */ 3088 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3089 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3090 if (!ha->ct_sns) 3091 goto fail_free_ms_iocb; 3092 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3093 "ms_iocb=%p ct_sns=%p.\n", 3094 ha->ms_iocb, ha->ct_sns); 3095 } 3096 3097 /* Allocate memory for request ring */ 3098 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3099 if (!*req) { 3100 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3101 "Failed to allocate memory for req.\n"); 3102 goto fail_req; 3103 } 3104 (*req)->length = req_len; 3105 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3106 ((*req)->length + 1) * sizeof(request_t), 3107 &(*req)->dma, GFP_KERNEL); 3108 if (!(*req)->ring) { 3109 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3110 "Failed to allocate memory for req_ring.\n"); 3111 goto fail_req_ring; 3112 } 3113 /* Allocate memory for response ring */ 3114 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3115 if (!*rsp) { 3116 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3117 "Failed to allocate memory for rsp.\n"); 3118 goto fail_rsp; 3119 } 3120 (*rsp)->hw = ha; 3121 (*rsp)->length = rsp_len; 3122 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3123 ((*rsp)->length + 1) * sizeof(response_t), 3124 &(*rsp)->dma, GFP_KERNEL); 3125 if (!(*rsp)->ring) { 3126 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3127 "Failed to allocate memory for rsp_ring.\n"); 3128 goto fail_rsp_ring; 3129 } 3130 (*req)->rsp = *rsp; 3131 (*rsp)->req = *req; 3132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3133 "req=%p req->length=%d req->ring=%p rsp=%p " 3134 "rsp->length=%d rsp->ring=%p.\n", 3135 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3136 (*rsp)->ring); 3137 /* Allocate memory for NVRAM data for vports */ 3138 if (ha->nvram_npiv_size) { 3139 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3140 ha->nvram_npiv_size, GFP_KERNEL); 3141 if (!ha->npiv_info) { 3142 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3143 "Failed to allocate memory for npiv_info.\n"); 3144 goto fail_npiv_info; 3145 } 3146 } else 3147 ha->npiv_info = NULL; 3148 3149 /* Get consistent memory allocated for EX-INIT-CB. */ 3150 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) { 3151 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3152 &ha->ex_init_cb_dma); 3153 if (!ha->ex_init_cb) 3154 goto fail_ex_init_cb; 3155 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3156 "ex_init_cb=%p.\n", ha->ex_init_cb); 3157 } 3158 3159 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3160 3161 /* Get consistent memory allocated for Async Port-Database. */ 3162 if (!IS_FWI2_CAPABLE(ha)) { 3163 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3164 &ha->async_pd_dma); 3165 if (!ha->async_pd) 3166 goto fail_async_pd; 3167 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3168 "async_pd=%p.\n", ha->async_pd); 3169 } 3170 3171 INIT_LIST_HEAD(&ha->vp_list); 3172 return 1; 3173 3174 fail_async_pd: 3175 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3176 fail_ex_init_cb: 3177 kfree(ha->npiv_info); 3178 fail_npiv_info: 3179 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3180 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3181 (*rsp)->ring = NULL; 3182 (*rsp)->dma = 0; 3183 fail_rsp_ring: 3184 kfree(*rsp); 3185 fail_rsp: 3186 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3187 sizeof(request_t), (*req)->ring, (*req)->dma); 3188 (*req)->ring = NULL; 3189 (*req)->dma = 0; 3190 fail_req_ring: 3191 kfree(*req); 3192 fail_req: 3193 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3194 ha->ct_sns, ha->ct_sns_dma); 3195 ha->ct_sns = NULL; 3196 ha->ct_sns_dma = 0; 3197 fail_free_ms_iocb: 3198 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3199 ha->ms_iocb = NULL; 3200 ha->ms_iocb_dma = 0; 3201 fail_dma_pool: 3202 if (IS_QLA82XX(ha) || ql2xenabledif) { 3203 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3204 ha->fcp_cmnd_dma_pool = NULL; 3205 } 3206 fail_dl_dma_pool: 3207 if (IS_QLA82XX(ha) || ql2xenabledif) { 3208 dma_pool_destroy(ha->dl_dma_pool); 3209 ha->dl_dma_pool = NULL; 3210 } 3211 fail_s_dma_pool: 3212 dma_pool_destroy(ha->s_dma_pool); 3213 ha->s_dma_pool = NULL; 3214 fail_free_nvram: 3215 kfree(ha->nvram); 3216 ha->nvram = NULL; 3217 fail_free_ctx_mempool: 3218 mempool_destroy(ha->ctx_mempool); 3219 ha->ctx_mempool = NULL; 3220 fail_free_srb_mempool: 3221 mempool_destroy(ha->srb_mempool); 3222 ha->srb_mempool = NULL; 3223 fail_free_gid_list: 3224 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3225 ha->gid_list, 3226 ha->gid_list_dma); 3227 ha->gid_list = NULL; 3228 ha->gid_list_dma = 0; 3229 fail_free_tgt_mem: 3230 qlt_mem_free(ha); 3231 fail_free_init_cb: 3232 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3233 ha->init_cb_dma); 3234 ha->init_cb = NULL; 3235 ha->init_cb_dma = 0; 3236 fail: 3237 ql_log(ql_log_fatal, NULL, 0x0030, 3238 "Memory allocation failure.\n"); 3239 return -ENOMEM; 3240 } 3241 3242 /* 3243 * qla2x00_free_fw_dump 3244 * Frees fw dump stuff. 3245 * 3246 * Input: 3247 * ha = adapter block pointer. 3248 */ 3249 static void 3250 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3251 { 3252 if (ha->fce) 3253 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 3254 ha->fce_dma); 3255 3256 if (ha->fw_dump) { 3257 if (ha->eft) 3258 dma_free_coherent(&ha->pdev->dev, 3259 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); 3260 vfree(ha->fw_dump); 3261 } 3262 ha->fce = NULL; 3263 ha->fce_dma = 0; 3264 ha->eft = NULL; 3265 ha->eft_dma = 0; 3266 ha->fw_dump = NULL; 3267 ha->fw_dumped = 0; 3268 ha->fw_dump_reading = 0; 3269 } 3270 3271 /* 3272 * qla2x00_mem_free 3273 * Frees all adapter allocated memory. 3274 * 3275 * Input: 3276 * ha = adapter block pointer. 3277 */ 3278 static void 3279 qla2x00_mem_free(struct qla_hw_data *ha) 3280 { 3281 qla2x00_free_fw_dump(ha); 3282 3283 if (ha->srb_mempool) 3284 mempool_destroy(ha->srb_mempool); 3285 3286 if (ha->dcbx_tlv) 3287 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3288 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3289 3290 if (ha->xgmac_data) 3291 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3292 ha->xgmac_data, ha->xgmac_data_dma); 3293 3294 if (ha->sns_cmd) 3295 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3296 ha->sns_cmd, ha->sns_cmd_dma); 3297 3298 if (ha->ct_sns) 3299 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3300 ha->ct_sns, ha->ct_sns_dma); 3301 3302 if (ha->sfp_data) 3303 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3304 3305 if (ha->ms_iocb) 3306 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3307 3308 if (ha->ex_init_cb) 3309 dma_pool_free(ha->s_dma_pool, 3310 ha->ex_init_cb, ha->ex_init_cb_dma); 3311 3312 if (ha->async_pd) 3313 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3314 3315 if (ha->s_dma_pool) 3316 dma_pool_destroy(ha->s_dma_pool); 3317 3318 if (ha->gid_list) 3319 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3320 ha->gid_list, ha->gid_list_dma); 3321 3322 if (IS_QLA82XX(ha)) { 3323 if (!list_empty(&ha->gbl_dsd_list)) { 3324 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3325 3326 /* clean up allocated prev pool */ 3327 list_for_each_entry_safe(dsd_ptr, 3328 tdsd_ptr, &ha->gbl_dsd_list, list) { 3329 dma_pool_free(ha->dl_dma_pool, 3330 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3331 list_del(&dsd_ptr->list); 3332 kfree(dsd_ptr); 3333 } 3334 } 3335 } 3336 3337 if (ha->dl_dma_pool) 3338 dma_pool_destroy(ha->dl_dma_pool); 3339 3340 if (ha->fcp_cmnd_dma_pool) 3341 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3342 3343 if (ha->ctx_mempool) 3344 mempool_destroy(ha->ctx_mempool); 3345 3346 qlt_mem_free(ha); 3347 3348 if (ha->init_cb) 3349 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3350 ha->init_cb, ha->init_cb_dma); 3351 vfree(ha->optrom_buffer); 3352 kfree(ha->nvram); 3353 kfree(ha->npiv_info); 3354 kfree(ha->swl); 3355 3356 ha->srb_mempool = NULL; 3357 ha->ctx_mempool = NULL; 3358 ha->sns_cmd = NULL; 3359 ha->sns_cmd_dma = 0; 3360 ha->ct_sns = NULL; 3361 ha->ct_sns_dma = 0; 3362 ha->ms_iocb = NULL; 3363 ha->ms_iocb_dma = 0; 3364 ha->init_cb = NULL; 3365 ha->init_cb_dma = 0; 3366 ha->ex_init_cb = NULL; 3367 ha->ex_init_cb_dma = 0; 3368 ha->async_pd = NULL; 3369 ha->async_pd_dma = 0; 3370 3371 ha->s_dma_pool = NULL; 3372 ha->dl_dma_pool = NULL; 3373 ha->fcp_cmnd_dma_pool = NULL; 3374 3375 ha->gid_list = NULL; 3376 ha->gid_list_dma = 0; 3377 3378 ha->tgt.atio_ring = NULL; 3379 ha->tgt.atio_dma = 0; 3380 ha->tgt.tgt_vp_map = NULL; 3381 } 3382 3383 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3384 struct qla_hw_data *ha) 3385 { 3386 struct Scsi_Host *host; 3387 struct scsi_qla_host *vha = NULL; 3388 3389 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3390 if (host == NULL) { 3391 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3392 "Failed to allocate host from the scsi layer, aborting.\n"); 3393 goto fail; 3394 } 3395 3396 /* Clear our data area */ 3397 vha = shost_priv(host); 3398 memset(vha, 0, sizeof(scsi_qla_host_t)); 3399 3400 vha->host = host; 3401 vha->host_no = host->host_no; 3402 vha->hw = ha; 3403 3404 INIT_LIST_HEAD(&vha->vp_fcports); 3405 INIT_LIST_HEAD(&vha->work_list); 3406 INIT_LIST_HEAD(&vha->list); 3407 3408 spin_lock_init(&vha->work_lock); 3409 3410 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3411 ql_dbg(ql_dbg_init, vha, 0x0041, 3412 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3413 vha->host, vha->hw, vha, 3414 dev_name(&(ha->pdev->dev))); 3415 3416 return vha; 3417 3418 fail: 3419 return vha; 3420 } 3421 3422 static struct qla_work_evt * 3423 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3424 { 3425 struct qla_work_evt *e; 3426 uint8_t bail; 3427 3428 QLA_VHA_MARK_BUSY(vha, bail); 3429 if (bail) 3430 return NULL; 3431 3432 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3433 if (!e) { 3434 QLA_VHA_MARK_NOT_BUSY(vha); 3435 return NULL; 3436 } 3437 3438 INIT_LIST_HEAD(&e->list); 3439 e->type = type; 3440 e->flags = QLA_EVT_FLAG_FREE; 3441 return e; 3442 } 3443 3444 static int 3445 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3446 { 3447 unsigned long flags; 3448 3449 spin_lock_irqsave(&vha->work_lock, flags); 3450 list_add_tail(&e->list, &vha->work_list); 3451 spin_unlock_irqrestore(&vha->work_lock, flags); 3452 qla2xxx_wake_dpc(vha); 3453 3454 return QLA_SUCCESS; 3455 } 3456 3457 int 3458 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3459 u32 data) 3460 { 3461 struct qla_work_evt *e; 3462 3463 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3464 if (!e) 3465 return QLA_FUNCTION_FAILED; 3466 3467 e->u.aen.code = code; 3468 e->u.aen.data = data; 3469 return qla2x00_post_work(vha, e); 3470 } 3471 3472 int 3473 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3474 { 3475 struct qla_work_evt *e; 3476 3477 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3478 if (!e) 3479 return QLA_FUNCTION_FAILED; 3480 3481 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3482 return qla2x00_post_work(vha, e); 3483 } 3484 3485 #define qla2x00_post_async_work(name, type) \ 3486 int qla2x00_post_async_##name##_work( \ 3487 struct scsi_qla_host *vha, \ 3488 fc_port_t *fcport, uint16_t *data) \ 3489 { \ 3490 struct qla_work_evt *e; \ 3491 \ 3492 e = qla2x00_alloc_work(vha, type); \ 3493 if (!e) \ 3494 return QLA_FUNCTION_FAILED; \ 3495 \ 3496 e->u.logio.fcport = fcport; \ 3497 if (data) { \ 3498 e->u.logio.data[0] = data[0]; \ 3499 e->u.logio.data[1] = data[1]; \ 3500 } \ 3501 return qla2x00_post_work(vha, e); \ 3502 } 3503 3504 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3505 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3506 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3507 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3508 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3509 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3510 3511 int 3512 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3513 { 3514 struct qla_work_evt *e; 3515 3516 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3517 if (!e) 3518 return QLA_FUNCTION_FAILED; 3519 3520 e->u.uevent.code = code; 3521 return qla2x00_post_work(vha, e); 3522 } 3523 3524 static void 3525 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3526 { 3527 char event_string[40]; 3528 char *envp[] = { event_string, NULL }; 3529 3530 switch (code) { 3531 case QLA_UEVENT_CODE_FW_DUMP: 3532 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3533 vha->host_no); 3534 break; 3535 default: 3536 /* do nothing */ 3537 break; 3538 } 3539 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3540 } 3541 3542 void 3543 qla2x00_do_work(struct scsi_qla_host *vha) 3544 { 3545 struct qla_work_evt *e, *tmp; 3546 unsigned long flags; 3547 LIST_HEAD(work); 3548 3549 spin_lock_irqsave(&vha->work_lock, flags); 3550 list_splice_init(&vha->work_list, &work); 3551 spin_unlock_irqrestore(&vha->work_lock, flags); 3552 3553 list_for_each_entry_safe(e, tmp, &work, list) { 3554 list_del_init(&e->list); 3555 3556 switch (e->type) { 3557 case QLA_EVT_AEN: 3558 fc_host_post_event(vha->host, fc_get_event_number(), 3559 e->u.aen.code, e->u.aen.data); 3560 break; 3561 case QLA_EVT_IDC_ACK: 3562 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3563 break; 3564 case QLA_EVT_ASYNC_LOGIN: 3565 qla2x00_async_login(vha, e->u.logio.fcport, 3566 e->u.logio.data); 3567 break; 3568 case QLA_EVT_ASYNC_LOGIN_DONE: 3569 qla2x00_async_login_done(vha, e->u.logio.fcport, 3570 e->u.logio.data); 3571 break; 3572 case QLA_EVT_ASYNC_LOGOUT: 3573 qla2x00_async_logout(vha, e->u.logio.fcport); 3574 break; 3575 case QLA_EVT_ASYNC_LOGOUT_DONE: 3576 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3577 e->u.logio.data); 3578 break; 3579 case QLA_EVT_ASYNC_ADISC: 3580 qla2x00_async_adisc(vha, e->u.logio.fcport, 3581 e->u.logio.data); 3582 break; 3583 case QLA_EVT_ASYNC_ADISC_DONE: 3584 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3585 e->u.logio.data); 3586 break; 3587 case QLA_EVT_UEVENT: 3588 qla2x00_uevent_emit(vha, e->u.uevent.code); 3589 break; 3590 } 3591 if (e->flags & QLA_EVT_FLAG_FREE) 3592 kfree(e); 3593 3594 /* For each work completed decrement vha ref count */ 3595 QLA_VHA_MARK_NOT_BUSY(vha); 3596 } 3597 } 3598 3599 /* Relogins all the fcports of a vport 3600 * Context: dpc thread 3601 */ 3602 void qla2x00_relogin(struct scsi_qla_host *vha) 3603 { 3604 fc_port_t *fcport; 3605 int status; 3606 uint16_t next_loopid = 0; 3607 struct qla_hw_data *ha = vha->hw; 3608 uint16_t data[2]; 3609 3610 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3611 /* 3612 * If the port is not ONLINE then try to login 3613 * to it if we haven't run out of retries. 3614 */ 3615 if (atomic_read(&fcport->state) != FCS_ONLINE && 3616 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3617 fcport->login_retry--; 3618 if (fcport->flags & FCF_FABRIC_DEVICE) { 3619 if (fcport->flags & FCF_FCP2_DEVICE) 3620 ha->isp_ops->fabric_logout(vha, 3621 fcport->loop_id, 3622 fcport->d_id.b.domain, 3623 fcport->d_id.b.area, 3624 fcport->d_id.b.al_pa); 3625 3626 if (fcport->loop_id == FC_NO_LOOP_ID) { 3627 fcport->loop_id = next_loopid = 3628 ha->min_external_loopid; 3629 status = qla2x00_find_new_loop_id( 3630 vha, fcport); 3631 if (status != QLA_SUCCESS) { 3632 /* Ran out of IDs to use */ 3633 break; 3634 } 3635 } 3636 3637 if (IS_ALOGIO_CAPABLE(ha)) { 3638 fcport->flags |= FCF_ASYNC_SENT; 3639 data[0] = 0; 3640 data[1] = QLA_LOGIO_LOGIN_RETRIED; 3641 status = qla2x00_post_async_login_work( 3642 vha, fcport, data); 3643 if (status == QLA_SUCCESS) 3644 continue; 3645 /* Attempt a retry. */ 3646 status = 1; 3647 } else { 3648 status = qla2x00_fabric_login(vha, 3649 fcport, &next_loopid); 3650 if (status == QLA_SUCCESS) { 3651 int status2; 3652 uint8_t opts; 3653 3654 opts = 0; 3655 if (fcport->flags & 3656 FCF_FCP2_DEVICE) 3657 opts |= BIT_1; 3658 status2 = 3659 qla2x00_get_port_database( 3660 vha, fcport, 3661 opts); 3662 if (status2 != QLA_SUCCESS) 3663 status = 1; 3664 } 3665 } 3666 } else 3667 status = qla2x00_local_device_login(vha, 3668 fcport); 3669 3670 if (status == QLA_SUCCESS) { 3671 fcport->old_loop_id = fcport->loop_id; 3672 3673 ql_dbg(ql_dbg_disc, vha, 0x2003, 3674 "Port login OK: logged in ID 0x%x.\n", 3675 fcport->loop_id); 3676 3677 qla2x00_update_fcport(vha, fcport); 3678 3679 } else if (status == 1) { 3680 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3681 /* retry the login again */ 3682 ql_dbg(ql_dbg_disc, vha, 0x2007, 3683 "Retrying %d login again loop_id 0x%x.\n", 3684 fcport->login_retry, fcport->loop_id); 3685 } else { 3686 fcport->login_retry = 0; 3687 } 3688 3689 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 3690 fcport->loop_id = FC_NO_LOOP_ID; 3691 } 3692 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3693 break; 3694 } 3695 } 3696 3697 /************************************************************************** 3698 * qla2x00_do_dpc 3699 * This kernel thread is a task that is schedule by the interrupt handler 3700 * to perform the background processing for interrupts. 3701 * 3702 * Notes: 3703 * This task always run in the context of a kernel thread. It 3704 * is kick-off by the driver's detect code and starts up 3705 * up one per adapter. It immediately goes to sleep and waits for 3706 * some fibre event. When either the interrupt handler or 3707 * the timer routine detects a event it will one of the task 3708 * bits then wake us up. 3709 **************************************************************************/ 3710 static int 3711 qla2x00_do_dpc(void *data) 3712 { 3713 int rval; 3714 scsi_qla_host_t *base_vha; 3715 struct qla_hw_data *ha; 3716 3717 ha = (struct qla_hw_data *)data; 3718 base_vha = pci_get_drvdata(ha->pdev); 3719 3720 set_user_nice(current, -20); 3721 3722 set_current_state(TASK_INTERRUPTIBLE); 3723 while (!kthread_should_stop()) { 3724 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 3725 "DPC handler sleeping.\n"); 3726 3727 schedule(); 3728 __set_current_state(TASK_RUNNING); 3729 3730 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 3731 goto end_loop; 3732 3733 if (ha->flags.eeh_busy) { 3734 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 3735 "eeh_busy=%d.\n", ha->flags.eeh_busy); 3736 goto end_loop; 3737 } 3738 3739 ha->dpc_active = 1; 3740 3741 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 3742 "DPC handler waking up, dpc_flags=0x%lx.\n", 3743 base_vha->dpc_flags); 3744 3745 qla2x00_do_work(base_vha); 3746 3747 if (IS_QLA82XX(ha)) { 3748 if (test_and_clear_bit(ISP_UNRECOVERABLE, 3749 &base_vha->dpc_flags)) { 3750 qla82xx_idc_lock(ha); 3751 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3752 QLA82XX_DEV_FAILED); 3753 qla82xx_idc_unlock(ha); 3754 ql_log(ql_log_info, base_vha, 0x4004, 3755 "HW State: FAILED.\n"); 3756 qla82xx_device_state_handler(base_vha); 3757 continue; 3758 } 3759 3760 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 3761 &base_vha->dpc_flags)) { 3762 3763 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 3764 "FCoE context reset scheduled.\n"); 3765 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3766 &base_vha->dpc_flags))) { 3767 if (qla82xx_fcoe_ctx_reset(base_vha)) { 3768 /* FCoE-ctx reset failed. 3769 * Escalate to chip-reset 3770 */ 3771 set_bit(ISP_ABORT_NEEDED, 3772 &base_vha->dpc_flags); 3773 } 3774 clear_bit(ABORT_ISP_ACTIVE, 3775 &base_vha->dpc_flags); 3776 } 3777 3778 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 3779 "FCoE context reset end.\n"); 3780 } 3781 } 3782 3783 if (test_and_clear_bit(ISP_ABORT_NEEDED, 3784 &base_vha->dpc_flags)) { 3785 3786 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 3787 "ISP abort scheduled.\n"); 3788 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3789 &base_vha->dpc_flags))) { 3790 3791 if (ha->isp_ops->abort_isp(base_vha)) { 3792 /* failed. retry later */ 3793 set_bit(ISP_ABORT_NEEDED, 3794 &base_vha->dpc_flags); 3795 } 3796 clear_bit(ABORT_ISP_ACTIVE, 3797 &base_vha->dpc_flags); 3798 } 3799 3800 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 3801 "ISP abort end.\n"); 3802 } 3803 3804 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { 3805 qla2x00_update_fcports(base_vha); 3806 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3807 } 3808 3809 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 3810 int ret; 3811 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 3812 if (ret != QLA_SUCCESS) 3813 ql_log(ql_log_warn, base_vha, 0x121, 3814 "Failed to enable receiving of RSCN " 3815 "requests: 0x%x.\n", ret); 3816 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 3817 } 3818 3819 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 3820 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 3821 "Quiescence mode scheduled.\n"); 3822 qla82xx_device_state_handler(base_vha); 3823 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); 3824 if (!ha->flags.quiesce_owner) { 3825 qla2x00_perform_loop_resync(base_vha); 3826 3827 qla82xx_idc_lock(ha); 3828 qla82xx_clear_qsnt_ready(base_vha); 3829 qla82xx_idc_unlock(ha); 3830 } 3831 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 3832 "Quiescence mode end.\n"); 3833 } 3834 3835 if (test_and_clear_bit(RESET_MARKER_NEEDED, 3836 &base_vha->dpc_flags) && 3837 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 3838 3839 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 3840 "Reset marker scheduled.\n"); 3841 qla2x00_rst_aen(base_vha); 3842 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 3843 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 3844 "Reset marker end.\n"); 3845 } 3846 3847 /* Retry each device up to login retry count */ 3848 if ((test_and_clear_bit(RELOGIN_NEEDED, 3849 &base_vha->dpc_flags)) && 3850 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 3851 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 3852 3853 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 3854 "Relogin scheduled.\n"); 3855 qla2x00_relogin(base_vha); 3856 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 3857 "Relogin end.\n"); 3858 } 3859 3860 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 3861 &base_vha->dpc_flags)) { 3862 3863 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 3864 "Loop resync scheduled.\n"); 3865 3866 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 3867 &base_vha->dpc_flags))) { 3868 3869 rval = qla2x00_loop_resync(base_vha); 3870 3871 clear_bit(LOOP_RESYNC_ACTIVE, 3872 &base_vha->dpc_flags); 3873 } 3874 3875 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 3876 "Loop resync end.\n"); 3877 } 3878 3879 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 3880 atomic_read(&base_vha->loop_state) == LOOP_READY) { 3881 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 3882 qla2xxx_flash_npiv_conf(base_vha); 3883 } 3884 3885 if (!ha->interrupts_on) 3886 ha->isp_ops->enable_intrs(ha); 3887 3888 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 3889 &base_vha->dpc_flags)) 3890 ha->isp_ops->beacon_blink(base_vha); 3891 3892 qla2x00_do_dpc_all_vps(base_vha); 3893 3894 ha->dpc_active = 0; 3895 end_loop: 3896 set_current_state(TASK_INTERRUPTIBLE); 3897 } /* End of while(1) */ 3898 __set_current_state(TASK_RUNNING); 3899 3900 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 3901 "DPC handler exiting.\n"); 3902 3903 /* 3904 * Make sure that nobody tries to wake us up again. 3905 */ 3906 ha->dpc_active = 0; 3907 3908 /* Cleanup any residual CTX SRBs. */ 3909 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3910 3911 return 0; 3912 } 3913 3914 void 3915 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 3916 { 3917 struct qla_hw_data *ha = vha->hw; 3918 struct task_struct *t = ha->dpc_thread; 3919 3920 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 3921 wake_up_process(t); 3922 } 3923 3924 /* 3925 * qla2x00_rst_aen 3926 * Processes asynchronous reset. 3927 * 3928 * Input: 3929 * ha = adapter block pointer. 3930 */ 3931 static void 3932 qla2x00_rst_aen(scsi_qla_host_t *vha) 3933 { 3934 if (vha->flags.online && !vha->flags.reset_active && 3935 !atomic_read(&vha->loop_down_timer) && 3936 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 3937 do { 3938 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 3939 3940 /* 3941 * Issue marker command only when we are going to start 3942 * the I/O. 3943 */ 3944 vha->marker_needed = 1; 3945 } while (!atomic_read(&vha->loop_down_timer) && 3946 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 3947 } 3948 } 3949 3950 /************************************************************************** 3951 * qla2x00_timer 3952 * 3953 * Description: 3954 * One second timer 3955 * 3956 * Context: Interrupt 3957 ***************************************************************************/ 3958 void 3959 qla2x00_timer(scsi_qla_host_t *vha) 3960 { 3961 unsigned long cpu_flags = 0; 3962 int start_dpc = 0; 3963 int index; 3964 srb_t *sp; 3965 uint16_t w; 3966 struct qla_hw_data *ha = vha->hw; 3967 struct req_que *req; 3968 3969 if (ha->flags.eeh_busy) { 3970 ql_dbg(ql_dbg_timer, vha, 0x6000, 3971 "EEH = %d, restarting timer.\n", 3972 ha->flags.eeh_busy); 3973 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3974 return; 3975 } 3976 3977 /* Hardware read to raise pending EEH errors during mailbox waits. */ 3978 if (!pci_channel_offline(ha->pdev)) 3979 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 3980 3981 /* Make sure qla82xx_watchdog is run only for physical port */ 3982 if (!vha->vp_idx && IS_QLA82XX(ha)) { 3983 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 3984 start_dpc++; 3985 qla82xx_watchdog(vha); 3986 } 3987 3988 /* Loop down handler. */ 3989 if (atomic_read(&vha->loop_down_timer) > 0 && 3990 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 3991 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 3992 && vha->flags.online) { 3993 3994 if (atomic_read(&vha->loop_down_timer) == 3995 vha->loop_down_abort_time) { 3996 3997 ql_log(ql_log_info, vha, 0x6008, 3998 "Loop down - aborting the queues before time expires.\n"); 3999 4000 if (!IS_QLA2100(ha) && vha->link_down_timeout) 4001 atomic_set(&vha->loop_state, LOOP_DEAD); 4002 4003 /* 4004 * Schedule an ISP abort to return any FCP2-device 4005 * commands. 4006 */ 4007 /* NPIV - scan physical port only */ 4008 if (!vha->vp_idx) { 4009 spin_lock_irqsave(&ha->hardware_lock, 4010 cpu_flags); 4011 req = ha->req_q_map[0]; 4012 for (index = 1; 4013 index < MAX_OUTSTANDING_COMMANDS; 4014 index++) { 4015 fc_port_t *sfcp; 4016 4017 sp = req->outstanding_cmds[index]; 4018 if (!sp) 4019 continue; 4020 if (sp->type != SRB_SCSI_CMD) 4021 continue; 4022 sfcp = sp->fcport; 4023 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 4024 continue; 4025 4026 if (IS_QLA82XX(ha)) 4027 set_bit(FCOE_CTX_RESET_NEEDED, 4028 &vha->dpc_flags); 4029 else 4030 set_bit(ISP_ABORT_NEEDED, 4031 &vha->dpc_flags); 4032 break; 4033 } 4034 spin_unlock_irqrestore(&ha->hardware_lock, 4035 cpu_flags); 4036 } 4037 start_dpc++; 4038 } 4039 4040 /* if the loop has been down for 4 minutes, reinit adapter */ 4041 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 4042 if (!(vha->device_flags & DFLG_NO_CABLE)) { 4043 ql_log(ql_log_warn, vha, 0x6009, 4044 "Loop down - aborting ISP.\n"); 4045 4046 if (IS_QLA82XX(ha)) 4047 set_bit(FCOE_CTX_RESET_NEEDED, 4048 &vha->dpc_flags); 4049 else 4050 set_bit(ISP_ABORT_NEEDED, 4051 &vha->dpc_flags); 4052 } 4053 } 4054 ql_dbg(ql_dbg_timer, vha, 0x600a, 4055 "Loop down - seconds remaining %d.\n", 4056 atomic_read(&vha->loop_down_timer)); 4057 } 4058 4059 /* Check if beacon LED needs to be blinked for physical host only */ 4060 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 4061 /* There is no beacon_blink function for ISP82xx */ 4062 if (!IS_QLA82XX(ha)) { 4063 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 4064 start_dpc++; 4065 } 4066 } 4067 4068 /* Process any deferred work. */ 4069 if (!list_empty(&vha->work_list)) 4070 start_dpc++; 4071 4072 /* Schedule the DPC routine if needed */ 4073 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 4074 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 4075 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 4076 start_dpc || 4077 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 4078 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 4079 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 4080 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 4081 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 4082 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 4083 ql_dbg(ql_dbg_timer, vha, 0x600b, 4084 "isp_abort_needed=%d loop_resync_needed=%d " 4085 "fcport_update_needed=%d start_dpc=%d " 4086 "reset_marker_needed=%d", 4087 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 4088 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 4089 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 4090 start_dpc, 4091 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 4092 ql_dbg(ql_dbg_timer, vha, 0x600c, 4093 "beacon_blink_needed=%d isp_unrecoverable=%d " 4094 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 4095 "relogin_needed=%d.\n", 4096 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 4097 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 4098 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 4099 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 4100 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 4101 qla2xxx_wake_dpc(vha); 4102 } 4103 4104 qla2x00_restart_timer(vha, WATCH_INTERVAL); 4105 } 4106 4107 /* Firmware interface routines. */ 4108 4109 #define FW_BLOBS 10 4110 #define FW_ISP21XX 0 4111 #define FW_ISP22XX 1 4112 #define FW_ISP2300 2 4113 #define FW_ISP2322 3 4114 #define FW_ISP24XX 4 4115 #define FW_ISP25XX 5 4116 #define FW_ISP81XX 6 4117 #define FW_ISP82XX 7 4118 #define FW_ISP2031 8 4119 #define FW_ISP8031 9 4120 4121 #define FW_FILE_ISP21XX "ql2100_fw.bin" 4122 #define FW_FILE_ISP22XX "ql2200_fw.bin" 4123 #define FW_FILE_ISP2300 "ql2300_fw.bin" 4124 #define FW_FILE_ISP2322 "ql2322_fw.bin" 4125 #define FW_FILE_ISP24XX "ql2400_fw.bin" 4126 #define FW_FILE_ISP25XX "ql2500_fw.bin" 4127 #define FW_FILE_ISP81XX "ql8100_fw.bin" 4128 #define FW_FILE_ISP82XX "ql8200_fw.bin" 4129 #define FW_FILE_ISP2031 "ql2600_fw.bin" 4130 #define FW_FILE_ISP8031 "ql8300_fw.bin" 4131 4132 static DEFINE_MUTEX(qla_fw_lock); 4133 4134 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 4135 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 4136 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 4137 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 4138 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 4139 { .name = FW_FILE_ISP24XX, }, 4140 { .name = FW_FILE_ISP25XX, }, 4141 { .name = FW_FILE_ISP81XX, }, 4142 { .name = FW_FILE_ISP82XX, }, 4143 { .name = FW_FILE_ISP2031, }, 4144 { .name = FW_FILE_ISP8031, }, 4145 }; 4146 4147 struct fw_blob * 4148 qla2x00_request_firmware(scsi_qla_host_t *vha) 4149 { 4150 struct qla_hw_data *ha = vha->hw; 4151 struct fw_blob *blob; 4152 4153 if (IS_QLA2100(ha)) { 4154 blob = &qla_fw_blobs[FW_ISP21XX]; 4155 } else if (IS_QLA2200(ha)) { 4156 blob = &qla_fw_blobs[FW_ISP22XX]; 4157 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4158 blob = &qla_fw_blobs[FW_ISP2300]; 4159 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 4160 blob = &qla_fw_blobs[FW_ISP2322]; 4161 } else if (IS_QLA24XX_TYPE(ha)) { 4162 blob = &qla_fw_blobs[FW_ISP24XX]; 4163 } else if (IS_QLA25XX(ha)) { 4164 blob = &qla_fw_blobs[FW_ISP25XX]; 4165 } else if (IS_QLA81XX(ha)) { 4166 blob = &qla_fw_blobs[FW_ISP81XX]; 4167 } else if (IS_QLA82XX(ha)) { 4168 blob = &qla_fw_blobs[FW_ISP82XX]; 4169 } else if (IS_QLA2031(ha)) { 4170 blob = &qla_fw_blobs[FW_ISP2031]; 4171 } else if (IS_QLA8031(ha)) { 4172 blob = &qla_fw_blobs[FW_ISP8031]; 4173 } else { 4174 return NULL; 4175 } 4176 4177 mutex_lock(&qla_fw_lock); 4178 if (blob->fw) 4179 goto out; 4180 4181 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 4182 ql_log(ql_log_warn, vha, 0x0063, 4183 "Failed to load firmware image (%s).\n", blob->name); 4184 blob->fw = NULL; 4185 blob = NULL; 4186 goto out; 4187 } 4188 4189 out: 4190 mutex_unlock(&qla_fw_lock); 4191 return blob; 4192 } 4193 4194 static void 4195 qla2x00_release_firmware(void) 4196 { 4197 int idx; 4198 4199 mutex_lock(&qla_fw_lock); 4200 for (idx = 0; idx < FW_BLOBS; idx++) 4201 release_firmware(qla_fw_blobs[idx].fw); 4202 mutex_unlock(&qla_fw_lock); 4203 } 4204 4205 static pci_ers_result_t 4206 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 4207 { 4208 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 4209 struct qla_hw_data *ha = vha->hw; 4210 4211 ql_dbg(ql_dbg_aer, vha, 0x9000, 4212 "PCI error detected, state %x.\n", state); 4213 4214 switch (state) { 4215 case pci_channel_io_normal: 4216 ha->flags.eeh_busy = 0; 4217 return PCI_ERS_RESULT_CAN_RECOVER; 4218 case pci_channel_io_frozen: 4219 ha->flags.eeh_busy = 1; 4220 /* For ISP82XX complete any pending mailbox cmd */ 4221 if (IS_QLA82XX(ha)) { 4222 ha->flags.isp82xx_fw_hung = 1; 4223 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 4224 qla82xx_clear_pending_mbx(vha); 4225 } 4226 qla2x00_free_irqs(vha); 4227 pci_disable_device(pdev); 4228 /* Return back all IOs */ 4229 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4230 return PCI_ERS_RESULT_NEED_RESET; 4231 case pci_channel_io_perm_failure: 4232 ha->flags.pci_channel_io_perm_failure = 1; 4233 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4234 return PCI_ERS_RESULT_DISCONNECT; 4235 } 4236 return PCI_ERS_RESULT_NEED_RESET; 4237 } 4238 4239 static pci_ers_result_t 4240 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 4241 { 4242 int risc_paused = 0; 4243 uint32_t stat; 4244 unsigned long flags; 4245 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4246 struct qla_hw_data *ha = base_vha->hw; 4247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4248 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 4249 4250 if (IS_QLA82XX(ha)) 4251 return PCI_ERS_RESULT_RECOVERED; 4252 4253 spin_lock_irqsave(&ha->hardware_lock, flags); 4254 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 4255 stat = RD_REG_DWORD(®->hccr); 4256 if (stat & HCCR_RISC_PAUSE) 4257 risc_paused = 1; 4258 } else if (IS_QLA23XX(ha)) { 4259 stat = RD_REG_DWORD(®->u.isp2300.host_status); 4260 if (stat & HSR_RISC_PAUSED) 4261 risc_paused = 1; 4262 } else if (IS_FWI2_CAPABLE(ha)) { 4263 stat = RD_REG_DWORD(®24->host_status); 4264 if (stat & HSRX_RISC_PAUSED) 4265 risc_paused = 1; 4266 } 4267 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4268 4269 if (risc_paused) { 4270 ql_log(ql_log_info, base_vha, 0x9003, 4271 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 4272 ha->isp_ops->fw_dump(base_vha, 0); 4273 4274 return PCI_ERS_RESULT_NEED_RESET; 4275 } else 4276 return PCI_ERS_RESULT_RECOVERED; 4277 } 4278 4279 uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) 4280 { 4281 uint32_t rval = QLA_FUNCTION_FAILED; 4282 uint32_t drv_active = 0; 4283 struct qla_hw_data *ha = base_vha->hw; 4284 int fn; 4285 struct pci_dev *other_pdev = NULL; 4286 4287 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 4288 "Entered %s.\n", __func__); 4289 4290 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4291 4292 if (base_vha->flags.online) { 4293 /* Abort all outstanding commands, 4294 * so as to be requeued later */ 4295 qla2x00_abort_isp_cleanup(base_vha); 4296 } 4297 4298 4299 fn = PCI_FUNC(ha->pdev->devfn); 4300 while (fn > 0) { 4301 fn--; 4302 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 4303 "Finding pci device at function = 0x%x.\n", fn); 4304 other_pdev = 4305 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 4306 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 4307 fn)); 4308 4309 if (!other_pdev) 4310 continue; 4311 if (atomic_read(&other_pdev->enable_cnt)) { 4312 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 4313 "Found PCI func available and enable at 0x%x.\n", 4314 fn); 4315 pci_dev_put(other_pdev); 4316 break; 4317 } 4318 pci_dev_put(other_pdev); 4319 } 4320 4321 if (!fn) { 4322 /* Reset owner */ 4323 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 4324 "This devfn is reset owner = 0x%x.\n", 4325 ha->pdev->devfn); 4326 qla82xx_idc_lock(ha); 4327 4328 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4329 QLA82XX_DEV_INITIALIZING); 4330 4331 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 4332 QLA82XX_IDC_VERSION); 4333 4334 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 4335 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 4336 "drv_active = 0x%x.\n", drv_active); 4337 4338 qla82xx_idc_unlock(ha); 4339 /* Reset if device is not already reset 4340 * drv_active would be 0 if a reset has already been done 4341 */ 4342 if (drv_active) 4343 rval = qla82xx_start_firmware(base_vha); 4344 else 4345 rval = QLA_SUCCESS; 4346 qla82xx_idc_lock(ha); 4347 4348 if (rval != QLA_SUCCESS) { 4349 ql_log(ql_log_info, base_vha, 0x900b, 4350 "HW State: FAILED.\n"); 4351 qla82xx_clear_drv_active(ha); 4352 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4353 QLA82XX_DEV_FAILED); 4354 } else { 4355 ql_log(ql_log_info, base_vha, 0x900c, 4356 "HW State: READY.\n"); 4357 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4358 QLA82XX_DEV_READY); 4359 qla82xx_idc_unlock(ha); 4360 ha->flags.isp82xx_fw_hung = 0; 4361 rval = qla82xx_restart_isp(base_vha); 4362 qla82xx_idc_lock(ha); 4363 /* Clear driver state register */ 4364 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 4365 qla82xx_set_drv_active(base_vha); 4366 } 4367 qla82xx_idc_unlock(ha); 4368 } else { 4369 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 4370 "This devfn is not reset owner = 0x%x.\n", 4371 ha->pdev->devfn); 4372 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 4373 QLA82XX_DEV_READY)) { 4374 ha->flags.isp82xx_fw_hung = 0; 4375 rval = qla82xx_restart_isp(base_vha); 4376 qla82xx_idc_lock(ha); 4377 qla82xx_set_drv_active(base_vha); 4378 qla82xx_idc_unlock(ha); 4379 } 4380 } 4381 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4382 4383 return rval; 4384 } 4385 4386 static pci_ers_result_t 4387 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 4388 { 4389 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 4390 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4391 struct qla_hw_data *ha = base_vha->hw; 4392 struct rsp_que *rsp; 4393 int rc, retries = 10; 4394 4395 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 4396 "Slot Reset.\n"); 4397 4398 /* Workaround: qla2xxx driver which access hardware earlier 4399 * needs error state to be pci_channel_io_online. 4400 * Otherwise mailbox command timesout. 4401 */ 4402 pdev->error_state = pci_channel_io_normal; 4403 4404 pci_restore_state(pdev); 4405 4406 /* pci_restore_state() clears the saved_state flag of the device 4407 * save restored state which resets saved_state flag 4408 */ 4409 pci_save_state(pdev); 4410 4411 if (ha->mem_only) 4412 rc = pci_enable_device_mem(pdev); 4413 else 4414 rc = pci_enable_device(pdev); 4415 4416 if (rc) { 4417 ql_log(ql_log_warn, base_vha, 0x9005, 4418 "Can't re-enable PCI device after reset.\n"); 4419 goto exit_slot_reset; 4420 } 4421 4422 rsp = ha->rsp_q_map[0]; 4423 if (qla2x00_request_irqs(ha, rsp)) 4424 goto exit_slot_reset; 4425 4426 if (ha->isp_ops->pci_config(base_vha)) 4427 goto exit_slot_reset; 4428 4429 if (IS_QLA82XX(ha)) { 4430 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 4431 ret = PCI_ERS_RESULT_RECOVERED; 4432 goto exit_slot_reset; 4433 } else 4434 goto exit_slot_reset; 4435 } 4436 4437 while (ha->flags.mbox_busy && retries--) 4438 msleep(1000); 4439 4440 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4441 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 4442 ret = PCI_ERS_RESULT_RECOVERED; 4443 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4444 4445 4446 exit_slot_reset: 4447 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 4448 "slot_reset return %x.\n", ret); 4449 4450 return ret; 4451 } 4452 4453 static void 4454 qla2xxx_pci_resume(struct pci_dev *pdev) 4455 { 4456 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4457 struct qla_hw_data *ha = base_vha->hw; 4458 int ret; 4459 4460 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 4461 "pci_resume.\n"); 4462 4463 ret = qla2x00_wait_for_hba_online(base_vha); 4464 if (ret != QLA_SUCCESS) { 4465 ql_log(ql_log_fatal, base_vha, 0x9002, 4466 "The device failed to resume I/O from slot/link_reset.\n"); 4467 } 4468 4469 pci_cleanup_aer_uncorrect_error_status(pdev); 4470 4471 ha->flags.eeh_busy = 0; 4472 } 4473 4474 static struct pci_error_handlers qla2xxx_err_handler = { 4475 .error_detected = qla2xxx_pci_error_detected, 4476 .mmio_enabled = qla2xxx_pci_mmio_enabled, 4477 .slot_reset = qla2xxx_pci_slot_reset, 4478 .resume = qla2xxx_pci_resume, 4479 }; 4480 4481 static struct pci_device_id qla2xxx_pci_tbl[] = { 4482 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 4483 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 4484 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 4485 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 4486 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 4487 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 4488 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 4489 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 4490 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 4491 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 4492 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 4493 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 4494 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 4495 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 4496 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 4497 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 4498 { 0 }, 4499 }; 4500 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 4501 4502 static struct pci_driver qla2xxx_pci_driver = { 4503 .name = QLA2XXX_DRIVER_NAME, 4504 .driver = { 4505 .owner = THIS_MODULE, 4506 }, 4507 .id_table = qla2xxx_pci_tbl, 4508 .probe = qla2x00_probe_one, 4509 .remove = qla2x00_remove_one, 4510 .shutdown = qla2x00_shutdown, 4511 .err_handler = &qla2xxx_err_handler, 4512 }; 4513 4514 static struct file_operations apidev_fops = { 4515 .owner = THIS_MODULE, 4516 .llseek = noop_llseek, 4517 }; 4518 4519 /** 4520 * qla2x00_module_init - Module initialization. 4521 **/ 4522 static int __init 4523 qla2x00_module_init(void) 4524 { 4525 int ret = 0; 4526 4527 /* Allocate cache for SRBs. */ 4528 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 4529 SLAB_HWCACHE_ALIGN, NULL); 4530 if (srb_cachep == NULL) { 4531 ql_log(ql_log_fatal, NULL, 0x0001, 4532 "Unable to allocate SRB cache...Failing load!.\n"); 4533 return -ENOMEM; 4534 } 4535 4536 /* Initialize target kmem_cache and mem_pools */ 4537 ret = qlt_init(); 4538 if (ret < 0) { 4539 kmem_cache_destroy(srb_cachep); 4540 return ret; 4541 } else if (ret > 0) { 4542 /* 4543 * If initiator mode is explictly disabled by qlt_init(), 4544 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 4545 * performing scsi_scan_target() during LOOP UP event. 4546 */ 4547 qla2xxx_transport_functions.disable_target_scan = 1; 4548 qla2xxx_transport_vport_functions.disable_target_scan = 1; 4549 } 4550 4551 /* Derive version string. */ 4552 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 4553 if (ql2xextended_error_logging) 4554 strcat(qla2x00_version_str, "-debug"); 4555 4556 qla2xxx_transport_template = 4557 fc_attach_transport(&qla2xxx_transport_functions); 4558 if (!qla2xxx_transport_template) { 4559 kmem_cache_destroy(srb_cachep); 4560 ql_log(ql_log_fatal, NULL, 0x0002, 4561 "fc_attach_transport failed...Failing load!.\n"); 4562 qlt_exit(); 4563 return -ENODEV; 4564 } 4565 4566 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 4567 if (apidev_major < 0) { 4568 ql_log(ql_log_fatal, NULL, 0x0003, 4569 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 4570 } 4571 4572 qla2xxx_transport_vport_template = 4573 fc_attach_transport(&qla2xxx_transport_vport_functions); 4574 if (!qla2xxx_transport_vport_template) { 4575 kmem_cache_destroy(srb_cachep); 4576 qlt_exit(); 4577 fc_release_transport(qla2xxx_transport_template); 4578 ql_log(ql_log_fatal, NULL, 0x0004, 4579 "fc_attach_transport vport failed...Failing load!.\n"); 4580 return -ENODEV; 4581 } 4582 ql_log(ql_log_info, NULL, 0x0005, 4583 "QLogic Fibre Channel HBA Driver: %s.\n", 4584 qla2x00_version_str); 4585 ret = pci_register_driver(&qla2xxx_pci_driver); 4586 if (ret) { 4587 kmem_cache_destroy(srb_cachep); 4588 qlt_exit(); 4589 fc_release_transport(qla2xxx_transport_template); 4590 fc_release_transport(qla2xxx_transport_vport_template); 4591 ql_log(ql_log_fatal, NULL, 0x0006, 4592 "pci_register_driver failed...ret=%d Failing load!.\n", 4593 ret); 4594 } 4595 return ret; 4596 } 4597 4598 /** 4599 * qla2x00_module_exit - Module cleanup. 4600 **/ 4601 static void __exit 4602 qla2x00_module_exit(void) 4603 { 4604 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 4605 pci_unregister_driver(&qla2xxx_pci_driver); 4606 qla2x00_release_firmware(); 4607 kmem_cache_destroy(srb_cachep); 4608 qlt_exit(); 4609 if (ctx_cachep) 4610 kmem_cache_destroy(ctx_cachep); 4611 fc_release_transport(qla2xxx_transport_template); 4612 fc_release_transport(qla2xxx_transport_vport_template); 4613 } 4614 4615 module_init(qla2x00_module_init); 4616 module_exit(qla2x00_module_exit); 4617 4618 MODULE_AUTHOR("QLogic Corporation"); 4619 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 4620 MODULE_LICENSE("GPL"); 4621 MODULE_VERSION(QLA2XXX_VERSION); 4622 MODULE_FIRMWARE(FW_FILE_ISP21XX); 4623 MODULE_FIRMWARE(FW_FILE_ISP22XX); 4624 MODULE_FIRMWARE(FW_FILE_ISP2300); 4625 MODULE_FIRMWARE(FW_FILE_ISP2322); 4626 MODULE_FIRMWARE(FW_FILE_ISP24XX); 4627 MODULE_FIRMWARE(FW_FILE_ISP25XX); 4628