1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 uint ql_errlev = 0x8001; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable = 1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI. Default is 1 - perform FDMI."); 117 118 #define MAX_Q_DEPTH 64 119 static int ql2xmaxqdepth = MAX_Q_DEPTH; 120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xmaxqdepth, 122 "Maximum queue depth to set for each LUN. " 123 "Default is 64."); 124 125 #if (IS_ENABLED(CONFIG_NVME_FC)) 126 int ql2xenabledif; 127 #else 128 int ql2xenabledif = 2; 129 #endif 130 module_param(ql2xenabledif, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xenabledif, 132 " Enable T10-CRC-DIF:\n" 133 " Default is 2.\n" 134 " 0 -- No DIF Support\n" 135 " 1 -- Enable DIF for all types\n" 136 " 2 -- Enable DIF for all types, except Type 0.\n"); 137 138 #if (IS_ENABLED(CONFIG_NVME_FC)) 139 int ql2xnvmeenable = 1; 140 #else 141 int ql2xnvmeenable; 142 #endif 143 module_param(ql2xnvmeenable, int, 0644); 144 MODULE_PARM_DESC(ql2xnvmeenable, 145 "Enables NVME support. " 146 "0 - no NVMe. Default is Y"); 147 148 int ql2xenablehba_err_chk = 2; 149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xenablehba_err_chk, 151 " Enable T10-CRC-DIF Error isolation by HBA:\n" 152 " Default is 2.\n" 153 " 0 -- Error isolation disabled\n" 154 " 1 -- Error isolation enabled only for DIX Type 0\n" 155 " 2 -- Error isolation enabled for all Types\n"); 156 157 int ql2xiidmaenable = 1; 158 module_param(ql2xiidmaenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xiidmaenable, 160 "Enables iIDMA settings " 161 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 162 163 int ql2xmqsupport = 1; 164 module_param(ql2xmqsupport, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xmqsupport, 166 "Enable on demand multiple queue pairs support " 167 "Default is 1 for supported. " 168 "Set it to 0 to turn off mq qpair support."); 169 170 int ql2xfwloadbin; 171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xfwloadbin, 174 "Option to specify location from which to load ISP firmware:.\n" 175 " 2 -- load firmware via the request_firmware() (hotplug).\n" 176 " interface.\n" 177 " 1 -- load firmware from flash.\n" 178 " 0 -- use default semantics.\n"); 179 180 int ql2xetsenable; 181 module_param(ql2xetsenable, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xetsenable, 183 "Enables firmware ETS burst." 184 "Default is 0 - skip ETS enablement."); 185 186 int ql2xdbwr = 1; 187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 188 MODULE_PARM_DESC(ql2xdbwr, 189 "Option to specify scheme for request queue posting.\n" 190 " 0 -- Regular doorbell.\n" 191 " 1 -- CAMRAM doorbell (faster).\n"); 192 193 int ql2xtargetreset = 1; 194 module_param(ql2xtargetreset, int, S_IRUGO); 195 MODULE_PARM_DESC(ql2xtargetreset, 196 "Enable target reset." 197 "Default is 1 - use hw defaults."); 198 199 int ql2xgffidenable; 200 module_param(ql2xgffidenable, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xgffidenable, 202 "Enables GFF_ID checks of port type. " 203 "Default is 0 - Do not use GFF_ID information."); 204 205 int ql2xasynctmfenable = 1; 206 module_param(ql2xasynctmfenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xasynctmfenable, 208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 210 211 int ql2xdontresethba; 212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 213 MODULE_PARM_DESC(ql2xdontresethba, 214 "Option to specify reset behaviour.\n" 215 " 0 (Default) -- Reset on failure.\n" 216 " 1 -- Do not reset on failure.\n"); 217 218 uint64_t ql2xmaxlun = MAX_LUNS; 219 module_param(ql2xmaxlun, ullong, S_IRUGO); 220 MODULE_PARM_DESC(ql2xmaxlun, 221 "Defines the maximum LU number to register with the SCSI " 222 "midlayer. Default is 65535."); 223 224 int ql2xmdcapmask = 0x1F; 225 module_param(ql2xmdcapmask, int, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmdcapmask, 227 "Set the Minidump driver capture mask level. " 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 229 230 int ql2xmdenable = 1; 231 module_param(ql2xmdenable, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdenable, 233 "Enable/disable MiniDump. " 234 "0 - MiniDump disabled. " 235 "1 (Default) - MiniDump enabled."); 236 237 int ql2xexlogins; 238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 239 MODULE_PARM_DESC(ql2xexlogins, 240 "Number of extended Logins. " 241 "0 (Default)- Disabled."); 242 243 int ql2xexchoffld = 1024; 244 module_param(ql2xexchoffld, uint, 0644); 245 MODULE_PARM_DESC(ql2xexchoffld, 246 "Number of target exchanges."); 247 248 int ql2xiniexchg = 1024; 249 module_param(ql2xiniexchg, uint, 0644); 250 MODULE_PARM_DESC(ql2xiniexchg, 251 "Number of initiator exchanges."); 252 253 int ql2xfwholdabts; 254 module_param(ql2xfwholdabts, int, S_IRUGO); 255 MODULE_PARM_DESC(ql2xfwholdabts, 256 "Allow FW to hold status IOCB until ABTS rsp received. " 257 "0 (Default) Do not set fw option. " 258 "1 - Set fw option to hold ABTS."); 259 260 int ql2xmvasynctoatio = 1; 261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 262 MODULE_PARM_DESC(ql2xmvasynctoatio, 263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 264 "0 (Default). Do not move IOCBs" 265 "1 - Move IOCBs."); 266 267 int ql2xautodetectsfp = 1; 268 module_param(ql2xautodetectsfp, int, 0444); 269 MODULE_PARM_DESC(ql2xautodetectsfp, 270 "Detect SFP range and set appropriate distance.\n" 271 "1 (Default): Enable\n"); 272 273 int ql2xenablemsix = 1; 274 module_param(ql2xenablemsix, int, 0444); 275 MODULE_PARM_DESC(ql2xenablemsix, 276 "Set to enable MSI or MSI-X interrupt mechanism.\n" 277 " Default is 1, enable MSI-X interrupt mechanism.\n" 278 " 0 -- enable traditional pin-based mechanism.\n" 279 " 1 -- enable MSI-X interrupt mechanism.\n" 280 " 2 -- enable MSI interrupt mechanism.\n"); 281 282 int qla2xuseresexchforels; 283 module_param(qla2xuseresexchforels, int, 0444); 284 MODULE_PARM_DESC(qla2xuseresexchforels, 285 "Reserve 1/2 of emergency exchanges for ELS.\n" 286 " 0 (default): disabled"); 287 288 static int ql2xprotmask; 289 module_param(ql2xprotmask, int, 0644); 290 MODULE_PARM_DESC(ql2xprotmask, 291 "Override DIF/DIX protection capabilities mask\n" 292 "Default is 0 which sets protection mask based on " 293 "capabilities reported by HBA firmware.\n"); 294 295 static int ql2xprotguard; 296 module_param(ql2xprotguard, int, 0644); 297 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 298 " 0 -- Let HBA firmware decide\n" 299 " 1 -- Force T10 CRC\n" 300 " 2 -- Force IP checksum\n"); 301 302 int ql2xdifbundlinginternalbuffers; 303 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 304 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 305 "Force using internal buffers for DIF information\n" 306 "0 (Default). Based on check.\n" 307 "1 Force using internal buffers\n"); 308 309 static void qla2x00_clear_drv_active(struct qla_hw_data *); 310 static void qla2x00_free_device(scsi_qla_host_t *); 311 static int qla2xxx_map_queues(struct Scsi_Host *shost); 312 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 313 314 315 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 316 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 317 318 /* TODO Convert to inlines 319 * 320 * Timer routines 321 */ 322 323 __inline__ void 324 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 325 { 326 timer_setup(&vha->timer, qla2x00_timer, 0); 327 vha->timer.expires = jiffies + interval * HZ; 328 add_timer(&vha->timer); 329 vha->timer_active = 1; 330 } 331 332 static inline void 333 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 334 { 335 /* Currently used for 82XX only. */ 336 if (vha->device_flags & DFLG_DEV_FAILED) { 337 ql_dbg(ql_dbg_timer, vha, 0x600d, 338 "Device in a failed state, returning.\n"); 339 return; 340 } 341 342 mod_timer(&vha->timer, jiffies + interval * HZ); 343 } 344 345 static __inline__ void 346 qla2x00_stop_timer(scsi_qla_host_t *vha) 347 { 348 del_timer_sync(&vha->timer); 349 vha->timer_active = 0; 350 } 351 352 static int qla2x00_do_dpc(void *data); 353 354 static void qla2x00_rst_aen(scsi_qla_host_t *); 355 356 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 357 struct req_que **, struct rsp_que **); 358 static void qla2x00_free_fw_dump(struct qla_hw_data *); 359 static void qla2x00_mem_free(struct qla_hw_data *); 360 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 361 struct qla_qpair *qpair); 362 363 /* -------------------------------------------------------------------------- */ 364 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 365 struct rsp_que *rsp) 366 { 367 struct qla_hw_data *ha = vha->hw; 368 369 rsp->qpair = ha->base_qpair; 370 rsp->req = req; 371 ha->base_qpair->hw = ha; 372 ha->base_qpair->req = req; 373 ha->base_qpair->rsp = rsp; 374 ha->base_qpair->vha = vha; 375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 378 ha->base_qpair->srb_mempool = ha->srb_mempool; 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 380 ha->base_qpair->enable_class_2 = ql2xenableclass2; 381 /* init qpair to this cpu. Will adjust at run time. */ 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 383 ha->base_qpair->pdev = ha->pdev; 384 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 387 } 388 389 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 390 struct rsp_que *rsp) 391 { 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 393 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 395 GFP_KERNEL); 396 if (!ha->req_q_map) { 397 ql_log(ql_log_fatal, vha, 0x003b, 398 "Unable to allocate memory for request queue ptrs.\n"); 399 goto fail_req_map; 400 } 401 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 403 GFP_KERNEL); 404 if (!ha->rsp_q_map) { 405 ql_log(ql_log_fatal, vha, 0x003c, 406 "Unable to allocate memory for response queue ptrs.\n"); 407 goto fail_rsp_map; 408 } 409 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 411 if (ha->base_qpair == NULL) { 412 ql_log(ql_log_warn, vha, 0x00e0, 413 "Failed to allocate base queue pair memory.\n"); 414 goto fail_base_qpair; 415 } 416 417 qla_init_base_qpair(vha, req, rsp); 418 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 421 GFP_KERNEL); 422 if (!ha->queue_pair_map) { 423 ql_log(ql_log_fatal, vha, 0x0180, 424 "Unable to allocate memory for queue pair ptrs.\n"); 425 goto fail_qpair_map; 426 } 427 } 428 429 /* 430 * Make sure we record at least the request and response queue zero in 431 * case we need to free them if part of the probe fails. 432 */ 433 ha->rsp_q_map[0] = rsp; 434 ha->req_q_map[0] = req; 435 set_bit(0, ha->rsp_qid_map); 436 set_bit(0, ha->req_qid_map); 437 return 0; 438 439 fail_qpair_map: 440 kfree(ha->base_qpair); 441 ha->base_qpair = NULL; 442 fail_base_qpair: 443 kfree(ha->rsp_q_map); 444 ha->rsp_q_map = NULL; 445 fail_rsp_map: 446 kfree(ha->req_q_map); 447 ha->req_q_map = NULL; 448 fail_req_map: 449 return -ENOMEM; 450 } 451 452 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 453 { 454 if (IS_QLAFX00(ha)) { 455 if (req && req->ring_fx00) 456 dma_free_coherent(&ha->pdev->dev, 457 (req->length_fx00 + 1) * sizeof(request_t), 458 req->ring_fx00, req->dma_fx00); 459 } else if (req && req->ring) 460 dma_free_coherent(&ha->pdev->dev, 461 (req->length + 1) * sizeof(request_t), 462 req->ring, req->dma); 463 464 if (req) 465 kfree(req->outstanding_cmds); 466 467 kfree(req); 468 } 469 470 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 471 { 472 if (IS_QLAFX00(ha)) { 473 if (rsp && rsp->ring_fx00) 474 dma_free_coherent(&ha->pdev->dev, 475 (rsp->length_fx00 + 1) * sizeof(request_t), 476 rsp->ring_fx00, rsp->dma_fx00); 477 } else if (rsp && rsp->ring) { 478 dma_free_coherent(&ha->pdev->dev, 479 (rsp->length + 1) * sizeof(response_t), 480 rsp->ring, rsp->dma); 481 } 482 kfree(rsp); 483 } 484 485 static void qla2x00_free_queues(struct qla_hw_data *ha) 486 { 487 struct req_que *req; 488 struct rsp_que *rsp; 489 int cnt; 490 unsigned long flags; 491 492 if (ha->queue_pair_map) { 493 kfree(ha->queue_pair_map); 494 ha->queue_pair_map = NULL; 495 } 496 if (ha->base_qpair) { 497 kfree(ha->base_qpair); 498 ha->base_qpair = NULL; 499 } 500 501 spin_lock_irqsave(&ha->hardware_lock, flags); 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 503 if (!test_bit(cnt, ha->req_qid_map)) 504 continue; 505 506 req = ha->req_q_map[cnt]; 507 clear_bit(cnt, ha->req_qid_map); 508 ha->req_q_map[cnt] = NULL; 509 510 spin_unlock_irqrestore(&ha->hardware_lock, flags); 511 qla2x00_free_req_que(ha, req); 512 spin_lock_irqsave(&ha->hardware_lock, flags); 513 } 514 spin_unlock_irqrestore(&ha->hardware_lock, flags); 515 516 kfree(ha->req_q_map); 517 ha->req_q_map = NULL; 518 519 520 spin_lock_irqsave(&ha->hardware_lock, flags); 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 522 if (!test_bit(cnt, ha->rsp_qid_map)) 523 continue; 524 525 rsp = ha->rsp_q_map[cnt]; 526 clear_bit(cnt, ha->rsp_qid_map); 527 ha->rsp_q_map[cnt] = NULL; 528 spin_unlock_irqrestore(&ha->hardware_lock, flags); 529 qla2x00_free_rsp_que(ha, rsp); 530 spin_lock_irqsave(&ha->hardware_lock, flags); 531 } 532 spin_unlock_irqrestore(&ha->hardware_lock, flags); 533 534 kfree(ha->rsp_q_map); 535 ha->rsp_q_map = NULL; 536 } 537 538 static char * 539 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 540 { 541 struct qla_hw_data *ha = vha->hw; 542 static const char *const pci_bus_modes[] = { 543 "33", "66", "100", "133", 544 }; 545 uint16_t pci_bus; 546 547 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 548 if (pci_bus) { 549 snprintf(str, str_len, "PCI-X (%s MHz)", 550 pci_bus_modes[pci_bus]); 551 } else { 552 pci_bus = (ha->pci_attr & BIT_8) >> 8; 553 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 554 } 555 556 return str; 557 } 558 559 static char * 560 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 561 { 562 static const char *const pci_bus_modes[] = { 563 "33", "66", "100", "133", 564 }; 565 struct qla_hw_data *ha = vha->hw; 566 uint32_t pci_bus; 567 568 if (pci_is_pcie(ha->pdev)) { 569 uint32_t lstat, lspeed, lwidth; 570 const char *speed_str; 571 572 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 573 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 574 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 575 576 switch (lspeed) { 577 case 1: 578 speed_str = "2.5GT/s"; 579 break; 580 case 2: 581 speed_str = "5.0GT/s"; 582 break; 583 case 3: 584 speed_str = "8.0GT/s"; 585 break; 586 default: 587 speed_str = "<unknown>"; 588 break; 589 } 590 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 591 592 return str; 593 } 594 595 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 596 if (pci_bus == 0 || pci_bus == 8) 597 snprintf(str, str_len, "PCI (%s MHz)", 598 pci_bus_modes[pci_bus >> 3]); 599 else 600 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 601 pci_bus & 4 ? 2 : 1, 602 pci_bus_modes[pci_bus & 3]); 603 604 return str; 605 } 606 607 static char * 608 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 609 { 610 char un_str[10]; 611 struct qla_hw_data *ha = vha->hw; 612 613 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 614 ha->fw_minor_version, ha->fw_subminor_version); 615 616 if (ha->fw_attributes & BIT_9) { 617 strcat(str, "FLX"); 618 return (str); 619 } 620 621 switch (ha->fw_attributes & 0xFF) { 622 case 0x7: 623 strcat(str, "EF"); 624 break; 625 case 0x17: 626 strcat(str, "TP"); 627 break; 628 case 0x37: 629 strcat(str, "IP"); 630 break; 631 case 0x77: 632 strcat(str, "VI"); 633 break; 634 default: 635 sprintf(un_str, "(%x)", ha->fw_attributes); 636 strcat(str, un_str); 637 break; 638 } 639 if (ha->fw_attributes & 0x100) 640 strcat(str, "X"); 641 642 return (str); 643 } 644 645 static char * 646 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 647 { 648 struct qla_hw_data *ha = vha->hw; 649 650 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 651 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 652 return str; 653 } 654 655 void qla2x00_sp_free_dma(srb_t *sp) 656 { 657 struct qla_hw_data *ha = sp->vha->hw; 658 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 659 660 if (sp->flags & SRB_DMA_VALID) { 661 scsi_dma_unmap(cmd); 662 sp->flags &= ~SRB_DMA_VALID; 663 } 664 665 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 666 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 667 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 668 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 669 } 670 671 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 672 /* List assured to be having elements */ 673 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 674 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 675 } 676 677 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 678 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 679 680 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 681 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 682 } 683 684 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 685 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 686 687 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 688 ctx1->fcp_cmnd_dma); 689 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 690 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 691 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 692 mempool_free(ctx1, ha->ctx_mempool); 693 } 694 } 695 696 void qla2x00_sp_compl(srb_t *sp, int res) 697 { 698 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 699 struct completion *comp = sp->comp; 700 701 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 702 return; 703 704 atomic_dec(&sp->ref_count); 705 706 sp->free(sp); 707 cmd->result = res; 708 CMD_SP(cmd) = NULL; 709 cmd->scsi_done(cmd); 710 if (comp) 711 complete(comp); 712 } 713 714 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 715 { 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 717 struct qla_hw_data *ha = sp->fcport->vha->hw; 718 719 if (sp->flags & SRB_DMA_VALID) { 720 scsi_dma_unmap(cmd); 721 sp->flags &= ~SRB_DMA_VALID; 722 } 723 724 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 725 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 726 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 727 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 728 } 729 730 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 731 /* List assured to be having elements */ 732 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 733 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 734 } 735 736 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 737 struct crc_context *difctx = sp->u.scmd.crc_ctx; 738 struct dsd_dma *dif_dsd, *nxt_dsd; 739 740 list_for_each_entry_safe(dif_dsd, nxt_dsd, 741 &difctx->ldif_dma_hndl_list, list) { 742 list_del(&dif_dsd->list); 743 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 744 dif_dsd->dsd_list_dma); 745 kfree(dif_dsd); 746 difctx->no_dif_bundl--; 747 } 748 749 list_for_each_entry_safe(dif_dsd, nxt_dsd, 750 &difctx->ldif_dsd_list, list) { 751 list_del(&dif_dsd->list); 752 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 753 dif_dsd->dsd_list_dma); 754 kfree(dif_dsd); 755 difctx->no_ldif_dsd--; 756 } 757 758 if (difctx->no_ldif_dsd) { 759 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 760 "%s: difctx->no_ldif_dsd=%x\n", 761 __func__, difctx->no_ldif_dsd); 762 } 763 764 if (difctx->no_dif_bundl) { 765 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 766 "%s: difctx->no_dif_bundl=%x\n", 767 __func__, difctx->no_dif_bundl); 768 } 769 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 770 } 771 772 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 773 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 774 775 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 776 ctx1->fcp_cmnd_dma); 777 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 778 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 779 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 780 mempool_free(ctx1, ha->ctx_mempool); 781 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 782 } 783 784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 785 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 786 787 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 789 } 790 } 791 792 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 793 { 794 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 795 struct completion *comp = sp->comp; 796 797 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 798 return; 799 800 atomic_dec(&sp->ref_count); 801 802 sp->free(sp); 803 cmd->result = res; 804 CMD_SP(cmd) = NULL; 805 cmd->scsi_done(cmd); 806 if (comp) 807 complete(comp); 808 } 809 810 static int 811 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 812 { 813 scsi_qla_host_t *vha = shost_priv(host); 814 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 815 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 816 struct qla_hw_data *ha = vha->hw; 817 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 818 srb_t *sp; 819 int rval; 820 821 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 822 WARN_ON_ONCE(!rport)) { 823 cmd->result = DID_NO_CONNECT << 16; 824 goto qc24_fail_command; 825 } 826 827 if (ha->mqenable) { 828 uint32_t tag; 829 uint16_t hwq; 830 struct qla_qpair *qpair = NULL; 831 832 tag = blk_mq_unique_tag(cmd->request); 833 hwq = blk_mq_unique_tag_to_hwq(tag); 834 qpair = ha->queue_pair_map[hwq]; 835 836 if (qpair) 837 return qla2xxx_mqueuecommand(host, cmd, qpair); 838 } 839 840 if (ha->flags.eeh_busy) { 841 if (ha->flags.pci_channel_io_perm_failure) { 842 ql_dbg(ql_dbg_aer, vha, 0x9010, 843 "PCI Channel IO permanent failure, exiting " 844 "cmd=%p.\n", cmd); 845 cmd->result = DID_NO_CONNECT << 16; 846 } else { 847 ql_dbg(ql_dbg_aer, vha, 0x9011, 848 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 849 cmd->result = DID_REQUEUE << 16; 850 } 851 goto qc24_fail_command; 852 } 853 854 rval = fc_remote_port_chkready(rport); 855 if (rval) { 856 cmd->result = rval; 857 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 858 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 859 cmd, rval); 860 goto qc24_fail_command; 861 } 862 863 if (!vha->flags.difdix_supported && 864 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 865 ql_dbg(ql_dbg_io, vha, 0x3004, 866 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 867 cmd); 868 cmd->result = DID_NO_CONNECT << 16; 869 goto qc24_fail_command; 870 } 871 872 if (!fcport) { 873 cmd->result = DID_NO_CONNECT << 16; 874 goto qc24_fail_command; 875 } 876 877 if (atomic_read(&fcport->state) != FCS_ONLINE) { 878 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 879 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 880 ql_dbg(ql_dbg_io, vha, 0x3005, 881 "Returning DNC, fcport_state=%d loop_state=%d.\n", 882 atomic_read(&fcport->state), 883 atomic_read(&base_vha->loop_state)); 884 cmd->result = DID_NO_CONNECT << 16; 885 goto qc24_fail_command; 886 } 887 goto qc24_target_busy; 888 } 889 890 /* 891 * Return target busy if we've received a non-zero retry_delay_timer 892 * in a FCP_RSP. 893 */ 894 if (fcport->retry_delay_timestamp == 0) { 895 /* retry delay not set */ 896 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 897 fcport->retry_delay_timestamp = 0; 898 else 899 goto qc24_target_busy; 900 901 sp = scsi_cmd_priv(cmd); 902 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 903 904 sp->u.scmd.cmd = cmd; 905 sp->type = SRB_SCSI_CMD; 906 atomic_set(&sp->ref_count, 1); 907 CMD_SP(cmd) = (void *)sp; 908 sp->free = qla2x00_sp_free_dma; 909 sp->done = qla2x00_sp_compl; 910 911 rval = ha->isp_ops->start_scsi(sp); 912 if (rval != QLA_SUCCESS) { 913 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 914 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 915 goto qc24_host_busy_free_sp; 916 } 917 918 return 0; 919 920 qc24_host_busy_free_sp: 921 sp->free(sp); 922 923 qc24_target_busy: 924 return SCSI_MLQUEUE_TARGET_BUSY; 925 926 qc24_fail_command: 927 cmd->scsi_done(cmd); 928 929 return 0; 930 } 931 932 /* For MQ supported I/O */ 933 int 934 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 935 struct qla_qpair *qpair) 936 { 937 scsi_qla_host_t *vha = shost_priv(host); 938 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 939 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 940 struct qla_hw_data *ha = vha->hw; 941 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 942 srb_t *sp; 943 int rval; 944 945 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 946 if (rval) { 947 cmd->result = rval; 948 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 949 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 950 cmd, rval); 951 goto qc24_fail_command; 952 } 953 954 if (!fcport) { 955 cmd->result = DID_NO_CONNECT << 16; 956 goto qc24_fail_command; 957 } 958 959 if (atomic_read(&fcport->state) != FCS_ONLINE) { 960 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 961 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 962 ql_dbg(ql_dbg_io, vha, 0x3077, 963 "Returning DNC, fcport_state=%d loop_state=%d.\n", 964 atomic_read(&fcport->state), 965 atomic_read(&base_vha->loop_state)); 966 cmd->result = DID_NO_CONNECT << 16; 967 goto qc24_fail_command; 968 } 969 goto qc24_target_busy; 970 } 971 972 /* 973 * Return target busy if we've received a non-zero retry_delay_timer 974 * in a FCP_RSP. 975 */ 976 if (fcport->retry_delay_timestamp == 0) { 977 /* retry delay not set */ 978 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 979 fcport->retry_delay_timestamp = 0; 980 else 981 goto qc24_target_busy; 982 983 sp = scsi_cmd_priv(cmd); 984 qla2xxx_init_sp(sp, vha, qpair, fcport); 985 986 sp->u.scmd.cmd = cmd; 987 sp->type = SRB_SCSI_CMD; 988 atomic_set(&sp->ref_count, 1); 989 CMD_SP(cmd) = (void *)sp; 990 sp->free = qla2xxx_qpair_sp_free_dma; 991 sp->done = qla2xxx_qpair_sp_compl; 992 sp->qpair = qpair; 993 994 rval = ha->isp_ops->start_scsi_mq(sp); 995 if (rval != QLA_SUCCESS) { 996 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 997 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 998 if (rval == QLA_INTERFACE_ERROR) 999 goto qc24_fail_command; 1000 goto qc24_host_busy_free_sp; 1001 } 1002 1003 return 0; 1004 1005 qc24_host_busy_free_sp: 1006 sp->free(sp); 1007 1008 qc24_target_busy: 1009 return SCSI_MLQUEUE_TARGET_BUSY; 1010 1011 qc24_fail_command: 1012 cmd->scsi_done(cmd); 1013 1014 return 0; 1015 } 1016 1017 /* 1018 * qla2x00_eh_wait_on_command 1019 * Waits for the command to be returned by the Firmware for some 1020 * max time. 1021 * 1022 * Input: 1023 * cmd = Scsi Command to wait on. 1024 * 1025 * Return: 1026 * Completed in time : QLA_SUCCESS 1027 * Did not complete in time : QLA_FUNCTION_FAILED 1028 */ 1029 static int 1030 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1031 { 1032 #define ABORT_POLLING_PERIOD 1000 1033 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1034 unsigned long wait_iter = ABORT_WAIT_ITER; 1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1036 struct qla_hw_data *ha = vha->hw; 1037 int ret = QLA_SUCCESS; 1038 1039 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1040 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1041 "Return:eh_wait.\n"); 1042 return ret; 1043 } 1044 1045 while (CMD_SP(cmd) && wait_iter--) { 1046 msleep(ABORT_POLLING_PERIOD); 1047 } 1048 if (CMD_SP(cmd)) 1049 ret = QLA_FUNCTION_FAILED; 1050 1051 return ret; 1052 } 1053 1054 /* 1055 * qla2x00_wait_for_hba_online 1056 * Wait till the HBA is online after going through 1057 * <= MAX_RETRIES_OF_ISP_ABORT or 1058 * finally HBA is disabled ie marked offline 1059 * 1060 * Input: 1061 * ha - pointer to host adapter structure 1062 * 1063 * Note: 1064 * Does context switching-Release SPIN_LOCK 1065 * (if any) before calling this routine. 1066 * 1067 * Return: 1068 * Success (Adapter is online) : 0 1069 * Failed (Adapter is offline/disabled) : 1 1070 */ 1071 int 1072 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1073 { 1074 int return_status; 1075 unsigned long wait_online; 1076 struct qla_hw_data *ha = vha->hw; 1077 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1078 1079 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1080 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1081 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1082 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1083 ha->dpc_active) && time_before(jiffies, wait_online)) { 1084 1085 msleep(1000); 1086 } 1087 if (base_vha->flags.online) 1088 return_status = QLA_SUCCESS; 1089 else 1090 return_status = QLA_FUNCTION_FAILED; 1091 1092 return (return_status); 1093 } 1094 1095 static inline int test_fcport_count(scsi_qla_host_t *vha) 1096 { 1097 struct qla_hw_data *ha = vha->hw; 1098 unsigned long flags; 1099 int res; 1100 1101 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1102 ql_dbg(ql_dbg_init, vha, 0x00ec, 1103 "tgt %p, fcport_count=%d\n", 1104 vha, vha->fcport_count); 1105 res = (vha->fcport_count == 0); 1106 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1107 1108 return res; 1109 } 1110 1111 /* 1112 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1113 * it has dependency on UNLOADING flag to stop device discovery 1114 */ 1115 void 1116 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1117 { 1118 u8 i; 1119 1120 qla2x00_mark_all_devices_lost(vha, 0); 1121 1122 for (i = 0; i < 10; i++) 1123 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 1124 HZ); 1125 1126 flush_workqueue(vha->hw->wq); 1127 } 1128 1129 /* 1130 * qla2x00_wait_for_hba_ready 1131 * Wait till the HBA is ready before doing driver unload 1132 * 1133 * Input: 1134 * ha - pointer to host adapter structure 1135 * 1136 * Note: 1137 * Does context switching-Release SPIN_LOCK 1138 * (if any) before calling this routine. 1139 * 1140 */ 1141 static void 1142 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1143 { 1144 struct qla_hw_data *ha = vha->hw; 1145 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1146 1147 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1148 ha->flags.mbox_busy) || 1149 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1150 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1151 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1152 break; 1153 msleep(1000); 1154 } 1155 } 1156 1157 int 1158 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1159 { 1160 int return_status; 1161 unsigned long wait_reset; 1162 struct qla_hw_data *ha = vha->hw; 1163 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1164 1165 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1166 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1167 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1168 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1169 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1170 1171 msleep(1000); 1172 1173 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1174 ha->flags.chip_reset_done) 1175 break; 1176 } 1177 if (ha->flags.chip_reset_done) 1178 return_status = QLA_SUCCESS; 1179 else 1180 return_status = QLA_FUNCTION_FAILED; 1181 1182 return return_status; 1183 } 1184 1185 static int 1186 sp_get(struct srb *sp) 1187 { 1188 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count)) 1189 /* kref get fail */ 1190 return ENXIO; 1191 else 1192 return 0; 1193 } 1194 1195 #define ISP_REG_DISCONNECT 0xffffffffU 1196 /************************************************************************** 1197 * qla2x00_isp_reg_stat 1198 * 1199 * Description: 1200 * Read the host status register of ISP before aborting the command. 1201 * 1202 * Input: 1203 * ha = pointer to host adapter structure. 1204 * 1205 * 1206 * Returns: 1207 * Either true or false. 1208 * 1209 * Note: Return true if there is register disconnect. 1210 **************************************************************************/ 1211 static inline 1212 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1213 { 1214 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1215 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1216 1217 if (IS_P3P_TYPE(ha)) 1218 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1219 else 1220 return ((RD_REG_DWORD(®->host_status)) == 1221 ISP_REG_DISCONNECT); 1222 } 1223 1224 /************************************************************************** 1225 * qla2xxx_eh_abort 1226 * 1227 * Description: 1228 * The abort function will abort the specified command. 1229 * 1230 * Input: 1231 * cmd = Linux SCSI command packet to be aborted. 1232 * 1233 * Returns: 1234 * Either SUCCESS or FAILED. 1235 * 1236 * Note: 1237 * Only return FAILED if command not returned by firmware. 1238 **************************************************************************/ 1239 static int 1240 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1241 { 1242 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1243 DECLARE_COMPLETION_ONSTACK(comp); 1244 srb_t *sp; 1245 int ret; 1246 unsigned int id; 1247 uint64_t lun; 1248 int rval; 1249 struct qla_hw_data *ha = vha->hw; 1250 1251 if (qla2x00_isp_reg_stat(ha)) { 1252 ql_log(ql_log_info, vha, 0x8042, 1253 "PCI/Register disconnect, exiting.\n"); 1254 return FAILED; 1255 } 1256 1257 ret = fc_block_scsi_eh(cmd); 1258 if (ret != 0) 1259 return ret; 1260 1261 sp = scsi_cmd_priv(cmd); 1262 1263 if (sp->fcport && sp->fcport->deleted) 1264 return SUCCESS; 1265 1266 /* Return if the command has already finished. */ 1267 if (sp_get(sp)) 1268 return SUCCESS; 1269 1270 id = cmd->device->id; 1271 lun = cmd->device->lun; 1272 1273 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1274 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1275 vha->host_no, id, lun, sp, cmd, sp->handle); 1276 1277 rval = ha->isp_ops->abort_command(sp); 1278 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1279 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1280 1281 switch (rval) { 1282 case QLA_SUCCESS: 1283 /* 1284 * The command has been aborted. That means that the firmware 1285 * won't report a completion. 1286 */ 1287 sp->done(sp, DID_ABORT << 16); 1288 ret = SUCCESS; 1289 break; 1290 case QLA_FUNCTION_PARAMETER_ERROR: { 1291 /* Wait for the command completion. */ 1292 uint32_t ratov = ha->r_a_tov/10; 1293 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000); 1294 1295 WARN_ON_ONCE(sp->comp); 1296 sp->comp = ∁ 1297 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1298 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1299 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1300 __func__, ha->r_a_tov); 1301 ret = FAILED; 1302 } else { 1303 ret = SUCCESS; 1304 } 1305 break; 1306 } 1307 default: 1308 /* 1309 * Either abort failed or abort and completion raced. Let 1310 * the SCSI core retry the abort in the former case. 1311 */ 1312 ret = FAILED; 1313 break; 1314 } 1315 1316 sp->comp = NULL; 1317 atomic_dec(&sp->ref_count); 1318 ql_log(ql_log_info, vha, 0x801c, 1319 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1320 vha->host_no, id, lun, ret); 1321 1322 return ret; 1323 } 1324 1325 /* 1326 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1327 */ 1328 int 1329 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1330 uint64_t l, enum nexus_wait_type type) 1331 { 1332 int cnt, match, status; 1333 unsigned long flags; 1334 struct qla_hw_data *ha = vha->hw; 1335 struct req_que *req; 1336 srb_t *sp; 1337 struct scsi_cmnd *cmd; 1338 1339 status = QLA_SUCCESS; 1340 1341 spin_lock_irqsave(&ha->hardware_lock, flags); 1342 req = vha->req; 1343 for (cnt = 1; status == QLA_SUCCESS && 1344 cnt < req->num_outstanding_cmds; cnt++) { 1345 sp = req->outstanding_cmds[cnt]; 1346 if (!sp) 1347 continue; 1348 if (sp->type != SRB_SCSI_CMD) 1349 continue; 1350 if (vha->vp_idx != sp->vha->vp_idx) 1351 continue; 1352 match = 0; 1353 cmd = GET_CMD_SP(sp); 1354 switch (type) { 1355 case WAIT_HOST: 1356 match = 1; 1357 break; 1358 case WAIT_TARGET: 1359 match = cmd->device->id == t; 1360 break; 1361 case WAIT_LUN: 1362 match = (cmd->device->id == t && 1363 cmd->device->lun == l); 1364 break; 1365 } 1366 if (!match) 1367 continue; 1368 1369 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1370 status = qla2x00_eh_wait_on_command(cmd); 1371 spin_lock_irqsave(&ha->hardware_lock, flags); 1372 } 1373 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1374 1375 return status; 1376 } 1377 1378 static char *reset_errors[] = { 1379 "HBA not online", 1380 "HBA not ready", 1381 "Task management failed", 1382 "Waiting for command completions", 1383 }; 1384 1385 static int 1386 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1387 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1388 { 1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1390 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1391 int err; 1392 1393 if (!fcport) { 1394 return FAILED; 1395 } 1396 1397 err = fc_block_scsi_eh(cmd); 1398 if (err != 0) 1399 return err; 1400 1401 if (fcport->deleted) 1402 return SUCCESS; 1403 1404 ql_log(ql_log_info, vha, 0x8009, 1405 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1406 cmd->device->id, cmd->device->lun, cmd); 1407 1408 err = 0; 1409 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1410 ql_log(ql_log_warn, vha, 0x800a, 1411 "Wait for hba online failed for cmd=%p.\n", cmd); 1412 goto eh_reset_failed; 1413 } 1414 err = 2; 1415 if (do_reset(fcport, cmd->device->lun, 1) 1416 != QLA_SUCCESS) { 1417 ql_log(ql_log_warn, vha, 0x800c, 1418 "do_reset failed for cmd=%p.\n", cmd); 1419 goto eh_reset_failed; 1420 } 1421 err = 3; 1422 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1423 cmd->device->lun, type) != QLA_SUCCESS) { 1424 ql_log(ql_log_warn, vha, 0x800d, 1425 "wait for pending cmds failed for cmd=%p.\n", cmd); 1426 goto eh_reset_failed; 1427 } 1428 1429 ql_log(ql_log_info, vha, 0x800e, 1430 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1431 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1432 1433 return SUCCESS; 1434 1435 eh_reset_failed: 1436 ql_log(ql_log_info, vha, 0x800f, 1437 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1438 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1439 cmd); 1440 return FAILED; 1441 } 1442 1443 static int 1444 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1445 { 1446 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1447 struct qla_hw_data *ha = vha->hw; 1448 1449 if (qla2x00_isp_reg_stat(ha)) { 1450 ql_log(ql_log_info, vha, 0x803e, 1451 "PCI/Register disconnect, exiting.\n"); 1452 return FAILED; 1453 } 1454 1455 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1456 ha->isp_ops->lun_reset); 1457 } 1458 1459 static int 1460 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1461 { 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1463 struct qla_hw_data *ha = vha->hw; 1464 1465 if (qla2x00_isp_reg_stat(ha)) { 1466 ql_log(ql_log_info, vha, 0x803f, 1467 "PCI/Register disconnect, exiting.\n"); 1468 return FAILED; 1469 } 1470 1471 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1472 ha->isp_ops->target_reset); 1473 } 1474 1475 /************************************************************************** 1476 * qla2xxx_eh_bus_reset 1477 * 1478 * Description: 1479 * The bus reset function will reset the bus and abort any executing 1480 * commands. 1481 * 1482 * Input: 1483 * cmd = Linux SCSI command packet of the command that cause the 1484 * bus reset. 1485 * 1486 * Returns: 1487 * SUCCESS/FAILURE (defined as macro in scsi.h). 1488 * 1489 **************************************************************************/ 1490 static int 1491 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1492 { 1493 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1494 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1495 int ret = FAILED; 1496 unsigned int id; 1497 uint64_t lun; 1498 struct qla_hw_data *ha = vha->hw; 1499 1500 if (qla2x00_isp_reg_stat(ha)) { 1501 ql_log(ql_log_info, vha, 0x8040, 1502 "PCI/Register disconnect, exiting.\n"); 1503 return FAILED; 1504 } 1505 1506 id = cmd->device->id; 1507 lun = cmd->device->lun; 1508 1509 if (!fcport) { 1510 return ret; 1511 } 1512 1513 ret = fc_block_scsi_eh(cmd); 1514 if (ret != 0) 1515 return ret; 1516 ret = FAILED; 1517 1518 if (qla2x00_chip_is_down(vha)) 1519 return ret; 1520 1521 ql_log(ql_log_info, vha, 0x8012, 1522 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1523 1524 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1525 ql_log(ql_log_fatal, vha, 0x8013, 1526 "Wait for hba online failed board disabled.\n"); 1527 goto eh_bus_reset_done; 1528 } 1529 1530 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1531 ret = SUCCESS; 1532 1533 if (ret == FAILED) 1534 goto eh_bus_reset_done; 1535 1536 /* Flush outstanding commands. */ 1537 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1538 QLA_SUCCESS) { 1539 ql_log(ql_log_warn, vha, 0x8014, 1540 "Wait for pending commands failed.\n"); 1541 ret = FAILED; 1542 } 1543 1544 eh_bus_reset_done: 1545 ql_log(ql_log_warn, vha, 0x802b, 1546 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1547 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1548 1549 return ret; 1550 } 1551 1552 /************************************************************************** 1553 * qla2xxx_eh_host_reset 1554 * 1555 * Description: 1556 * The reset function will reset the Adapter. 1557 * 1558 * Input: 1559 * cmd = Linux SCSI command packet of the command that cause the 1560 * adapter reset. 1561 * 1562 * Returns: 1563 * Either SUCCESS or FAILED. 1564 * 1565 * Note: 1566 **************************************************************************/ 1567 static int 1568 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1569 { 1570 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1571 struct qla_hw_data *ha = vha->hw; 1572 int ret = FAILED; 1573 unsigned int id; 1574 uint64_t lun; 1575 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1576 1577 if (qla2x00_isp_reg_stat(ha)) { 1578 ql_log(ql_log_info, vha, 0x8041, 1579 "PCI/Register disconnect, exiting.\n"); 1580 schedule_work(&ha->board_disable); 1581 return SUCCESS; 1582 } 1583 1584 id = cmd->device->id; 1585 lun = cmd->device->lun; 1586 1587 ql_log(ql_log_info, vha, 0x8018, 1588 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1589 1590 /* 1591 * No point in issuing another reset if one is active. Also do not 1592 * attempt a reset if we are updating flash. 1593 */ 1594 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1595 goto eh_host_reset_lock; 1596 1597 if (vha != base_vha) { 1598 if (qla2x00_vp_abort_isp(vha)) 1599 goto eh_host_reset_lock; 1600 } else { 1601 if (IS_P3P_TYPE(vha->hw)) { 1602 if (!qla82xx_fcoe_ctx_reset(vha)) { 1603 /* Ctx reset success */ 1604 ret = SUCCESS; 1605 goto eh_host_reset_lock; 1606 } 1607 /* fall thru if ctx reset failed */ 1608 } 1609 if (ha->wq) 1610 flush_workqueue(ha->wq); 1611 1612 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1613 if (ha->isp_ops->abort_isp(base_vha)) { 1614 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1615 /* failed. schedule dpc to try */ 1616 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1617 1618 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1619 ql_log(ql_log_warn, vha, 0x802a, 1620 "wait for hba online failed.\n"); 1621 goto eh_host_reset_lock; 1622 } 1623 } 1624 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1625 } 1626 1627 /* Waiting for command to be returned to OS.*/ 1628 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1629 QLA_SUCCESS) 1630 ret = SUCCESS; 1631 1632 eh_host_reset_lock: 1633 ql_log(ql_log_info, vha, 0x8017, 1634 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1635 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1636 1637 return ret; 1638 } 1639 1640 /* 1641 * qla2x00_loop_reset 1642 * Issue loop reset. 1643 * 1644 * Input: 1645 * ha = adapter block pointer. 1646 * 1647 * Returns: 1648 * 0 = success 1649 */ 1650 int 1651 qla2x00_loop_reset(scsi_qla_host_t *vha) 1652 { 1653 int ret; 1654 struct fc_port *fcport; 1655 struct qla_hw_data *ha = vha->hw; 1656 1657 if (IS_QLAFX00(ha)) { 1658 return qlafx00_loop_reset(vha); 1659 } 1660 1661 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1662 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1663 if (fcport->port_type != FCT_TARGET) 1664 continue; 1665 1666 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1667 if (ret != QLA_SUCCESS) { 1668 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1669 "Bus Reset failed: Reset=%d " 1670 "d_id=%x.\n", ret, fcport->d_id.b24); 1671 } 1672 } 1673 } 1674 1675 1676 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1677 atomic_set(&vha->loop_state, LOOP_DOWN); 1678 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1679 qla2x00_mark_all_devices_lost(vha, 0); 1680 ret = qla2x00_full_login_lip(vha); 1681 if (ret != QLA_SUCCESS) { 1682 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1683 "full_login_lip=%d.\n", ret); 1684 } 1685 } 1686 1687 if (ha->flags.enable_lip_reset) { 1688 ret = qla2x00_lip_reset(vha); 1689 if (ret != QLA_SUCCESS) 1690 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1691 "lip_reset failed (%d).\n", ret); 1692 } 1693 1694 /* Issue marker command only when we are going to start the I/O */ 1695 vha->marker_needed = 1; 1696 1697 return QLA_SUCCESS; 1698 } 1699 1700 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1701 unsigned long *flags) 1702 __releases(qp->qp_lock_ptr) 1703 __acquires(qp->qp_lock_ptr) 1704 { 1705 DECLARE_COMPLETION_ONSTACK(comp); 1706 scsi_qla_host_t *vha = qp->vha; 1707 struct qla_hw_data *ha = vha->hw; 1708 int rval; 1709 1710 if (sp_get(sp)) 1711 return; 1712 1713 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1714 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1715 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1716 !qla2x00_isp_reg_stat(ha))) { 1717 sp->comp = ∁ 1718 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1719 rval = ha->isp_ops->abort_command(sp); 1720 1721 switch (rval) { 1722 case QLA_SUCCESS: 1723 sp->done(sp, res); 1724 break; 1725 case QLA_FUNCTION_PARAMETER_ERROR: 1726 wait_for_completion(&comp); 1727 break; 1728 } 1729 1730 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1731 sp->comp = NULL; 1732 } 1733 1734 atomic_dec(&sp->ref_count); 1735 } 1736 1737 static void 1738 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1739 { 1740 int cnt; 1741 unsigned long flags; 1742 srb_t *sp; 1743 scsi_qla_host_t *vha = qp->vha; 1744 struct qla_hw_data *ha = vha->hw; 1745 struct req_que *req; 1746 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1747 struct qla_tgt_cmd *cmd; 1748 1749 if (!ha->req_q_map) 1750 return; 1751 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1752 req = qp->req; 1753 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1754 sp = req->outstanding_cmds[cnt]; 1755 if (sp) { 1756 req->outstanding_cmds[cnt] = NULL; 1757 switch (sp->cmd_type) { 1758 case TYPE_SRB: 1759 qla2x00_abort_srb(qp, sp, res, &flags); 1760 break; 1761 case TYPE_TGT_CMD: 1762 if (!vha->hw->tgt.tgt_ops || !tgt || 1763 qla_ini_mode_enabled(vha)) { 1764 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1765 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1766 vha->dpc_flags); 1767 continue; 1768 } 1769 cmd = (struct qla_tgt_cmd *)sp; 1770 cmd->aborted = 1; 1771 break; 1772 case TYPE_TGT_TMCMD: 1773 /* Skip task management functions. */ 1774 break; 1775 default: 1776 break; 1777 } 1778 } 1779 } 1780 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1781 } 1782 1783 void 1784 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1785 { 1786 int que; 1787 struct qla_hw_data *ha = vha->hw; 1788 1789 /* Continue only if initialization complete. */ 1790 if (!ha->base_qpair) 1791 return; 1792 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1793 1794 if (!ha->queue_pair_map) 1795 return; 1796 for (que = 0; que < ha->max_qpairs; que++) { 1797 if (!ha->queue_pair_map[que]) 1798 continue; 1799 1800 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1801 } 1802 } 1803 1804 static int 1805 qla2xxx_slave_alloc(struct scsi_device *sdev) 1806 { 1807 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1808 1809 if (!rport || fc_remote_port_chkready(rport)) 1810 return -ENXIO; 1811 1812 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1813 1814 return 0; 1815 } 1816 1817 static int 1818 qla2xxx_slave_configure(struct scsi_device *sdev) 1819 { 1820 scsi_qla_host_t *vha = shost_priv(sdev->host); 1821 struct req_que *req = vha->req; 1822 1823 if (IS_T10_PI_CAPABLE(vha->hw)) 1824 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1825 1826 scsi_change_queue_depth(sdev, req->max_q_depth); 1827 return 0; 1828 } 1829 1830 static void 1831 qla2xxx_slave_destroy(struct scsi_device *sdev) 1832 { 1833 sdev->hostdata = NULL; 1834 } 1835 1836 /** 1837 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1838 * @ha: HA context 1839 * 1840 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1841 * supported addressing method. 1842 */ 1843 static void 1844 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1845 { 1846 /* Assume a 32bit DMA mask. */ 1847 ha->flags.enable_64bit_addressing = 0; 1848 1849 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1850 /* Any upper-dword bits set? */ 1851 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1852 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1853 /* Ok, a 64bit DMA mask is applicable. */ 1854 ha->flags.enable_64bit_addressing = 1; 1855 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1856 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1857 return; 1858 } 1859 } 1860 1861 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1862 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1863 } 1864 1865 static void 1866 qla2x00_enable_intrs(struct qla_hw_data *ha) 1867 { 1868 unsigned long flags = 0; 1869 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1870 1871 spin_lock_irqsave(&ha->hardware_lock, flags); 1872 ha->interrupts_on = 1; 1873 /* enable risc and host interrupts */ 1874 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1875 RD_REG_WORD(®->ictrl); 1876 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1877 1878 } 1879 1880 static void 1881 qla2x00_disable_intrs(struct qla_hw_data *ha) 1882 { 1883 unsigned long flags = 0; 1884 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1885 1886 spin_lock_irqsave(&ha->hardware_lock, flags); 1887 ha->interrupts_on = 0; 1888 /* disable risc and host interrupts */ 1889 WRT_REG_WORD(®->ictrl, 0); 1890 RD_REG_WORD(®->ictrl); 1891 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1892 } 1893 1894 static void 1895 qla24xx_enable_intrs(struct qla_hw_data *ha) 1896 { 1897 unsigned long flags = 0; 1898 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1899 1900 spin_lock_irqsave(&ha->hardware_lock, flags); 1901 ha->interrupts_on = 1; 1902 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1903 RD_REG_DWORD(®->ictrl); 1904 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1905 } 1906 1907 static void 1908 qla24xx_disable_intrs(struct qla_hw_data *ha) 1909 { 1910 unsigned long flags = 0; 1911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1912 1913 if (IS_NOPOLLING_TYPE(ha)) 1914 return; 1915 spin_lock_irqsave(&ha->hardware_lock, flags); 1916 ha->interrupts_on = 0; 1917 WRT_REG_DWORD(®->ictrl, 0); 1918 RD_REG_DWORD(®->ictrl); 1919 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1920 } 1921 1922 static int 1923 qla2x00_iospace_config(struct qla_hw_data *ha) 1924 { 1925 resource_size_t pio; 1926 uint16_t msix; 1927 1928 if (pci_request_selected_regions(ha->pdev, ha->bars, 1929 QLA2XXX_DRIVER_NAME)) { 1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1931 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1932 pci_name(ha->pdev)); 1933 goto iospace_error_exit; 1934 } 1935 if (!(ha->bars & 1)) 1936 goto skip_pio; 1937 1938 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1939 pio = pci_resource_start(ha->pdev, 0); 1940 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1941 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1942 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1943 "Invalid pci I/O region size (%s).\n", 1944 pci_name(ha->pdev)); 1945 pio = 0; 1946 } 1947 } else { 1948 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1949 "Region #0 no a PIO resource (%s).\n", 1950 pci_name(ha->pdev)); 1951 pio = 0; 1952 } 1953 ha->pio_address = pio; 1954 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1955 "PIO address=%llu.\n", 1956 (unsigned long long)ha->pio_address); 1957 1958 skip_pio: 1959 /* Use MMIO operations for all accesses. */ 1960 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1962 "Region #1 not an MMIO resource (%s), aborting.\n", 1963 pci_name(ha->pdev)); 1964 goto iospace_error_exit; 1965 } 1966 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1967 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1968 "Invalid PCI mem region size (%s), aborting.\n", 1969 pci_name(ha->pdev)); 1970 goto iospace_error_exit; 1971 } 1972 1973 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1974 if (!ha->iobase) { 1975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1976 "Cannot remap MMIO (%s), aborting.\n", 1977 pci_name(ha->pdev)); 1978 goto iospace_error_exit; 1979 } 1980 1981 /* Determine queue resources */ 1982 ha->max_req_queues = ha->max_rsp_queues = 1; 1983 ha->msix_count = QLA_BASE_VECTORS; 1984 if (!ql2xmqsupport || !ql2xnvmeenable || 1985 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1986 goto mqiobase_exit; 1987 1988 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1989 pci_resource_len(ha->pdev, 3)); 1990 if (ha->mqiobase) { 1991 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1992 "MQIO Base=%p.\n", ha->mqiobase); 1993 /* Read MSIX vector size of the board */ 1994 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1995 ha->msix_count = msix + 1; 1996 /* Max queues are bounded by available msix vectors */ 1997 /* MB interrupt uses 1 vector */ 1998 ha->max_req_queues = ha->msix_count - 1; 1999 ha->max_rsp_queues = ha->max_req_queues; 2000 /* Queue pairs is the max value minus the base queue pair */ 2001 ha->max_qpairs = ha->max_rsp_queues - 1; 2002 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2003 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2004 2005 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2006 "MSI-X vector count: %d.\n", ha->msix_count); 2007 } else 2008 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2009 "BAR 3 not enabled.\n"); 2010 2011 mqiobase_exit: 2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2013 "MSIX Count: %d.\n", ha->msix_count); 2014 return (0); 2015 2016 iospace_error_exit: 2017 return (-ENOMEM); 2018 } 2019 2020 2021 static int 2022 qla83xx_iospace_config(struct qla_hw_data *ha) 2023 { 2024 uint16_t msix; 2025 2026 if (pci_request_selected_regions(ha->pdev, ha->bars, 2027 QLA2XXX_DRIVER_NAME)) { 2028 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2029 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2030 pci_name(ha->pdev)); 2031 2032 goto iospace_error_exit; 2033 } 2034 2035 /* Use MMIO operations for all accesses. */ 2036 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2037 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2038 "Invalid pci I/O region size (%s).\n", 2039 pci_name(ha->pdev)); 2040 goto iospace_error_exit; 2041 } 2042 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2043 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2044 "Invalid PCI mem region size (%s), aborting\n", 2045 pci_name(ha->pdev)); 2046 goto iospace_error_exit; 2047 } 2048 2049 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2050 if (!ha->iobase) { 2051 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2052 "Cannot remap MMIO (%s), aborting.\n", 2053 pci_name(ha->pdev)); 2054 goto iospace_error_exit; 2055 } 2056 2057 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2058 /* 83XX 26XX always use MQ type access for queues 2059 * - mbar 2, a.k.a region 4 */ 2060 ha->max_req_queues = ha->max_rsp_queues = 1; 2061 ha->msix_count = QLA_BASE_VECTORS; 2062 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2063 pci_resource_len(ha->pdev, 4)); 2064 2065 if (!ha->mqiobase) { 2066 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2067 "BAR2/region4 not enabled\n"); 2068 goto mqiobase_exit; 2069 } 2070 2071 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2072 pci_resource_len(ha->pdev, 2)); 2073 if (ha->msixbase) { 2074 /* Read MSIX vector size of the board */ 2075 pci_read_config_word(ha->pdev, 2076 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2077 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2078 /* 2079 * By default, driver uses at least two msix vectors 2080 * (default & rspq) 2081 */ 2082 if (ql2xmqsupport || ql2xnvmeenable) { 2083 /* MB interrupt uses 1 vector */ 2084 ha->max_req_queues = ha->msix_count - 1; 2085 2086 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2087 if (QLA_TGT_MODE_ENABLED()) 2088 ha->max_req_queues--; 2089 2090 ha->max_rsp_queues = ha->max_req_queues; 2091 2092 /* Queue pairs is the max value minus 2093 * the base queue pair */ 2094 ha->max_qpairs = ha->max_req_queues - 1; 2095 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2096 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2097 } 2098 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2099 "MSI-X vector count: %d.\n", ha->msix_count); 2100 } else 2101 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2102 "BAR 1 not enabled.\n"); 2103 2104 mqiobase_exit: 2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2106 "MSIX Count: %d.\n", ha->msix_count); 2107 return 0; 2108 2109 iospace_error_exit: 2110 return -ENOMEM; 2111 } 2112 2113 static struct isp_operations qla2100_isp_ops = { 2114 .pci_config = qla2100_pci_config, 2115 .reset_chip = qla2x00_reset_chip, 2116 .chip_diag = qla2x00_chip_diag, 2117 .config_rings = qla2x00_config_rings, 2118 .reset_adapter = qla2x00_reset_adapter, 2119 .nvram_config = qla2x00_nvram_config, 2120 .update_fw_options = qla2x00_update_fw_options, 2121 .load_risc = qla2x00_load_risc, 2122 .pci_info_str = qla2x00_pci_info_str, 2123 .fw_version_str = qla2x00_fw_version_str, 2124 .intr_handler = qla2100_intr_handler, 2125 .enable_intrs = qla2x00_enable_intrs, 2126 .disable_intrs = qla2x00_disable_intrs, 2127 .abort_command = qla2x00_abort_command, 2128 .target_reset = qla2x00_abort_target, 2129 .lun_reset = qla2x00_lun_reset, 2130 .fabric_login = qla2x00_login_fabric, 2131 .fabric_logout = qla2x00_fabric_logout, 2132 .calc_req_entries = qla2x00_calc_iocbs_32, 2133 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2134 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2135 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2136 .read_nvram = qla2x00_read_nvram_data, 2137 .write_nvram = qla2x00_write_nvram_data, 2138 .fw_dump = qla2100_fw_dump, 2139 .beacon_on = NULL, 2140 .beacon_off = NULL, 2141 .beacon_blink = NULL, 2142 .read_optrom = qla2x00_read_optrom_data, 2143 .write_optrom = qla2x00_write_optrom_data, 2144 .get_flash_version = qla2x00_get_flash_version, 2145 .start_scsi = qla2x00_start_scsi, 2146 .start_scsi_mq = NULL, 2147 .abort_isp = qla2x00_abort_isp, 2148 .iospace_config = qla2x00_iospace_config, 2149 .initialize_adapter = qla2x00_initialize_adapter, 2150 }; 2151 2152 static struct isp_operations qla2300_isp_ops = { 2153 .pci_config = qla2300_pci_config, 2154 .reset_chip = qla2x00_reset_chip, 2155 .chip_diag = qla2x00_chip_diag, 2156 .config_rings = qla2x00_config_rings, 2157 .reset_adapter = qla2x00_reset_adapter, 2158 .nvram_config = qla2x00_nvram_config, 2159 .update_fw_options = qla2x00_update_fw_options, 2160 .load_risc = qla2x00_load_risc, 2161 .pci_info_str = qla2x00_pci_info_str, 2162 .fw_version_str = qla2x00_fw_version_str, 2163 .intr_handler = qla2300_intr_handler, 2164 .enable_intrs = qla2x00_enable_intrs, 2165 .disable_intrs = qla2x00_disable_intrs, 2166 .abort_command = qla2x00_abort_command, 2167 .target_reset = qla2x00_abort_target, 2168 .lun_reset = qla2x00_lun_reset, 2169 .fabric_login = qla2x00_login_fabric, 2170 .fabric_logout = qla2x00_fabric_logout, 2171 .calc_req_entries = qla2x00_calc_iocbs_32, 2172 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2173 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2174 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2175 .read_nvram = qla2x00_read_nvram_data, 2176 .write_nvram = qla2x00_write_nvram_data, 2177 .fw_dump = qla2300_fw_dump, 2178 .beacon_on = qla2x00_beacon_on, 2179 .beacon_off = qla2x00_beacon_off, 2180 .beacon_blink = qla2x00_beacon_blink, 2181 .read_optrom = qla2x00_read_optrom_data, 2182 .write_optrom = qla2x00_write_optrom_data, 2183 .get_flash_version = qla2x00_get_flash_version, 2184 .start_scsi = qla2x00_start_scsi, 2185 .start_scsi_mq = NULL, 2186 .abort_isp = qla2x00_abort_isp, 2187 .iospace_config = qla2x00_iospace_config, 2188 .initialize_adapter = qla2x00_initialize_adapter, 2189 }; 2190 2191 static struct isp_operations qla24xx_isp_ops = { 2192 .pci_config = qla24xx_pci_config, 2193 .reset_chip = qla24xx_reset_chip, 2194 .chip_diag = qla24xx_chip_diag, 2195 .config_rings = qla24xx_config_rings, 2196 .reset_adapter = qla24xx_reset_adapter, 2197 .nvram_config = qla24xx_nvram_config, 2198 .update_fw_options = qla24xx_update_fw_options, 2199 .load_risc = qla24xx_load_risc, 2200 .pci_info_str = qla24xx_pci_info_str, 2201 .fw_version_str = qla24xx_fw_version_str, 2202 .intr_handler = qla24xx_intr_handler, 2203 .enable_intrs = qla24xx_enable_intrs, 2204 .disable_intrs = qla24xx_disable_intrs, 2205 .abort_command = qla24xx_abort_command, 2206 .target_reset = qla24xx_abort_target, 2207 .lun_reset = qla24xx_lun_reset, 2208 .fabric_login = qla24xx_login_fabric, 2209 .fabric_logout = qla24xx_fabric_logout, 2210 .calc_req_entries = NULL, 2211 .build_iocbs = NULL, 2212 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2213 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2214 .read_nvram = qla24xx_read_nvram_data, 2215 .write_nvram = qla24xx_write_nvram_data, 2216 .fw_dump = qla24xx_fw_dump, 2217 .beacon_on = qla24xx_beacon_on, 2218 .beacon_off = qla24xx_beacon_off, 2219 .beacon_blink = qla24xx_beacon_blink, 2220 .read_optrom = qla24xx_read_optrom_data, 2221 .write_optrom = qla24xx_write_optrom_data, 2222 .get_flash_version = qla24xx_get_flash_version, 2223 .start_scsi = qla24xx_start_scsi, 2224 .start_scsi_mq = NULL, 2225 .abort_isp = qla2x00_abort_isp, 2226 .iospace_config = qla2x00_iospace_config, 2227 .initialize_adapter = qla2x00_initialize_adapter, 2228 }; 2229 2230 static struct isp_operations qla25xx_isp_ops = { 2231 .pci_config = qla25xx_pci_config, 2232 .reset_chip = qla24xx_reset_chip, 2233 .chip_diag = qla24xx_chip_diag, 2234 .config_rings = qla24xx_config_rings, 2235 .reset_adapter = qla24xx_reset_adapter, 2236 .nvram_config = qla24xx_nvram_config, 2237 .update_fw_options = qla24xx_update_fw_options, 2238 .load_risc = qla24xx_load_risc, 2239 .pci_info_str = qla24xx_pci_info_str, 2240 .fw_version_str = qla24xx_fw_version_str, 2241 .intr_handler = qla24xx_intr_handler, 2242 .enable_intrs = qla24xx_enable_intrs, 2243 .disable_intrs = qla24xx_disable_intrs, 2244 .abort_command = qla24xx_abort_command, 2245 .target_reset = qla24xx_abort_target, 2246 .lun_reset = qla24xx_lun_reset, 2247 .fabric_login = qla24xx_login_fabric, 2248 .fabric_logout = qla24xx_fabric_logout, 2249 .calc_req_entries = NULL, 2250 .build_iocbs = NULL, 2251 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2252 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2253 .read_nvram = qla25xx_read_nvram_data, 2254 .write_nvram = qla25xx_write_nvram_data, 2255 .fw_dump = qla25xx_fw_dump, 2256 .beacon_on = qla24xx_beacon_on, 2257 .beacon_off = qla24xx_beacon_off, 2258 .beacon_blink = qla24xx_beacon_blink, 2259 .read_optrom = qla25xx_read_optrom_data, 2260 .write_optrom = qla24xx_write_optrom_data, 2261 .get_flash_version = qla24xx_get_flash_version, 2262 .start_scsi = qla24xx_dif_start_scsi, 2263 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2264 .abort_isp = qla2x00_abort_isp, 2265 .iospace_config = qla2x00_iospace_config, 2266 .initialize_adapter = qla2x00_initialize_adapter, 2267 }; 2268 2269 static struct isp_operations qla81xx_isp_ops = { 2270 .pci_config = qla25xx_pci_config, 2271 .reset_chip = qla24xx_reset_chip, 2272 .chip_diag = qla24xx_chip_diag, 2273 .config_rings = qla24xx_config_rings, 2274 .reset_adapter = qla24xx_reset_adapter, 2275 .nvram_config = qla81xx_nvram_config, 2276 .update_fw_options = qla81xx_update_fw_options, 2277 .load_risc = qla81xx_load_risc, 2278 .pci_info_str = qla24xx_pci_info_str, 2279 .fw_version_str = qla24xx_fw_version_str, 2280 .intr_handler = qla24xx_intr_handler, 2281 .enable_intrs = qla24xx_enable_intrs, 2282 .disable_intrs = qla24xx_disable_intrs, 2283 .abort_command = qla24xx_abort_command, 2284 .target_reset = qla24xx_abort_target, 2285 .lun_reset = qla24xx_lun_reset, 2286 .fabric_login = qla24xx_login_fabric, 2287 .fabric_logout = qla24xx_fabric_logout, 2288 .calc_req_entries = NULL, 2289 .build_iocbs = NULL, 2290 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2291 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2292 .read_nvram = NULL, 2293 .write_nvram = NULL, 2294 .fw_dump = qla81xx_fw_dump, 2295 .beacon_on = qla24xx_beacon_on, 2296 .beacon_off = qla24xx_beacon_off, 2297 .beacon_blink = qla83xx_beacon_blink, 2298 .read_optrom = qla25xx_read_optrom_data, 2299 .write_optrom = qla24xx_write_optrom_data, 2300 .get_flash_version = qla24xx_get_flash_version, 2301 .start_scsi = qla24xx_dif_start_scsi, 2302 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2303 .abort_isp = qla2x00_abort_isp, 2304 .iospace_config = qla2x00_iospace_config, 2305 .initialize_adapter = qla2x00_initialize_adapter, 2306 }; 2307 2308 static struct isp_operations qla82xx_isp_ops = { 2309 .pci_config = qla82xx_pci_config, 2310 .reset_chip = qla82xx_reset_chip, 2311 .chip_diag = qla24xx_chip_diag, 2312 .config_rings = qla82xx_config_rings, 2313 .reset_adapter = qla24xx_reset_adapter, 2314 .nvram_config = qla81xx_nvram_config, 2315 .update_fw_options = qla24xx_update_fw_options, 2316 .load_risc = qla82xx_load_risc, 2317 .pci_info_str = qla24xx_pci_info_str, 2318 .fw_version_str = qla24xx_fw_version_str, 2319 .intr_handler = qla82xx_intr_handler, 2320 .enable_intrs = qla82xx_enable_intrs, 2321 .disable_intrs = qla82xx_disable_intrs, 2322 .abort_command = qla24xx_abort_command, 2323 .target_reset = qla24xx_abort_target, 2324 .lun_reset = qla24xx_lun_reset, 2325 .fabric_login = qla24xx_login_fabric, 2326 .fabric_logout = qla24xx_fabric_logout, 2327 .calc_req_entries = NULL, 2328 .build_iocbs = NULL, 2329 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2330 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2331 .read_nvram = qla24xx_read_nvram_data, 2332 .write_nvram = qla24xx_write_nvram_data, 2333 .fw_dump = qla82xx_fw_dump, 2334 .beacon_on = qla82xx_beacon_on, 2335 .beacon_off = qla82xx_beacon_off, 2336 .beacon_blink = NULL, 2337 .read_optrom = qla82xx_read_optrom_data, 2338 .write_optrom = qla82xx_write_optrom_data, 2339 .get_flash_version = qla82xx_get_flash_version, 2340 .start_scsi = qla82xx_start_scsi, 2341 .start_scsi_mq = NULL, 2342 .abort_isp = qla82xx_abort_isp, 2343 .iospace_config = qla82xx_iospace_config, 2344 .initialize_adapter = qla2x00_initialize_adapter, 2345 }; 2346 2347 static struct isp_operations qla8044_isp_ops = { 2348 .pci_config = qla82xx_pci_config, 2349 .reset_chip = qla82xx_reset_chip, 2350 .chip_diag = qla24xx_chip_diag, 2351 .config_rings = qla82xx_config_rings, 2352 .reset_adapter = qla24xx_reset_adapter, 2353 .nvram_config = qla81xx_nvram_config, 2354 .update_fw_options = qla24xx_update_fw_options, 2355 .load_risc = qla82xx_load_risc, 2356 .pci_info_str = qla24xx_pci_info_str, 2357 .fw_version_str = qla24xx_fw_version_str, 2358 .intr_handler = qla8044_intr_handler, 2359 .enable_intrs = qla82xx_enable_intrs, 2360 .disable_intrs = qla82xx_disable_intrs, 2361 .abort_command = qla24xx_abort_command, 2362 .target_reset = qla24xx_abort_target, 2363 .lun_reset = qla24xx_lun_reset, 2364 .fabric_login = qla24xx_login_fabric, 2365 .fabric_logout = qla24xx_fabric_logout, 2366 .calc_req_entries = NULL, 2367 .build_iocbs = NULL, 2368 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2369 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2370 .read_nvram = NULL, 2371 .write_nvram = NULL, 2372 .fw_dump = qla8044_fw_dump, 2373 .beacon_on = qla82xx_beacon_on, 2374 .beacon_off = qla82xx_beacon_off, 2375 .beacon_blink = NULL, 2376 .read_optrom = qla8044_read_optrom_data, 2377 .write_optrom = qla8044_write_optrom_data, 2378 .get_flash_version = qla82xx_get_flash_version, 2379 .start_scsi = qla82xx_start_scsi, 2380 .start_scsi_mq = NULL, 2381 .abort_isp = qla8044_abort_isp, 2382 .iospace_config = qla82xx_iospace_config, 2383 .initialize_adapter = qla2x00_initialize_adapter, 2384 }; 2385 2386 static struct isp_operations qla83xx_isp_ops = { 2387 .pci_config = qla25xx_pci_config, 2388 .reset_chip = qla24xx_reset_chip, 2389 .chip_diag = qla24xx_chip_diag, 2390 .config_rings = qla24xx_config_rings, 2391 .reset_adapter = qla24xx_reset_adapter, 2392 .nvram_config = qla81xx_nvram_config, 2393 .update_fw_options = qla81xx_update_fw_options, 2394 .load_risc = qla81xx_load_risc, 2395 .pci_info_str = qla24xx_pci_info_str, 2396 .fw_version_str = qla24xx_fw_version_str, 2397 .intr_handler = qla24xx_intr_handler, 2398 .enable_intrs = qla24xx_enable_intrs, 2399 .disable_intrs = qla24xx_disable_intrs, 2400 .abort_command = qla24xx_abort_command, 2401 .target_reset = qla24xx_abort_target, 2402 .lun_reset = qla24xx_lun_reset, 2403 .fabric_login = qla24xx_login_fabric, 2404 .fabric_logout = qla24xx_fabric_logout, 2405 .calc_req_entries = NULL, 2406 .build_iocbs = NULL, 2407 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2408 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2409 .read_nvram = NULL, 2410 .write_nvram = NULL, 2411 .fw_dump = qla83xx_fw_dump, 2412 .beacon_on = qla24xx_beacon_on, 2413 .beacon_off = qla24xx_beacon_off, 2414 .beacon_blink = qla83xx_beacon_blink, 2415 .read_optrom = qla25xx_read_optrom_data, 2416 .write_optrom = qla24xx_write_optrom_data, 2417 .get_flash_version = qla24xx_get_flash_version, 2418 .start_scsi = qla24xx_dif_start_scsi, 2419 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2420 .abort_isp = qla2x00_abort_isp, 2421 .iospace_config = qla83xx_iospace_config, 2422 .initialize_adapter = qla2x00_initialize_adapter, 2423 }; 2424 2425 static struct isp_operations qlafx00_isp_ops = { 2426 .pci_config = qlafx00_pci_config, 2427 .reset_chip = qlafx00_soft_reset, 2428 .chip_diag = qlafx00_chip_diag, 2429 .config_rings = qlafx00_config_rings, 2430 .reset_adapter = qlafx00_soft_reset, 2431 .nvram_config = NULL, 2432 .update_fw_options = NULL, 2433 .load_risc = NULL, 2434 .pci_info_str = qlafx00_pci_info_str, 2435 .fw_version_str = qlafx00_fw_version_str, 2436 .intr_handler = qlafx00_intr_handler, 2437 .enable_intrs = qlafx00_enable_intrs, 2438 .disable_intrs = qlafx00_disable_intrs, 2439 .abort_command = qla24xx_async_abort_command, 2440 .target_reset = qlafx00_abort_target, 2441 .lun_reset = qlafx00_lun_reset, 2442 .fabric_login = NULL, 2443 .fabric_logout = NULL, 2444 .calc_req_entries = NULL, 2445 .build_iocbs = NULL, 2446 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2447 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2448 .read_nvram = qla24xx_read_nvram_data, 2449 .write_nvram = qla24xx_write_nvram_data, 2450 .fw_dump = NULL, 2451 .beacon_on = qla24xx_beacon_on, 2452 .beacon_off = qla24xx_beacon_off, 2453 .beacon_blink = NULL, 2454 .read_optrom = qla24xx_read_optrom_data, 2455 .write_optrom = qla24xx_write_optrom_data, 2456 .get_flash_version = qla24xx_get_flash_version, 2457 .start_scsi = qlafx00_start_scsi, 2458 .start_scsi_mq = NULL, 2459 .abort_isp = qlafx00_abort_isp, 2460 .iospace_config = qlafx00_iospace_config, 2461 .initialize_adapter = qlafx00_initialize_adapter, 2462 }; 2463 2464 static struct isp_operations qla27xx_isp_ops = { 2465 .pci_config = qla25xx_pci_config, 2466 .reset_chip = qla24xx_reset_chip, 2467 .chip_diag = qla24xx_chip_diag, 2468 .config_rings = qla24xx_config_rings, 2469 .reset_adapter = qla24xx_reset_adapter, 2470 .nvram_config = qla81xx_nvram_config, 2471 .update_fw_options = qla24xx_update_fw_options, 2472 .load_risc = qla81xx_load_risc, 2473 .pci_info_str = qla24xx_pci_info_str, 2474 .fw_version_str = qla24xx_fw_version_str, 2475 .intr_handler = qla24xx_intr_handler, 2476 .enable_intrs = qla24xx_enable_intrs, 2477 .disable_intrs = qla24xx_disable_intrs, 2478 .abort_command = qla24xx_abort_command, 2479 .target_reset = qla24xx_abort_target, 2480 .lun_reset = qla24xx_lun_reset, 2481 .fabric_login = qla24xx_login_fabric, 2482 .fabric_logout = qla24xx_fabric_logout, 2483 .calc_req_entries = NULL, 2484 .build_iocbs = NULL, 2485 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2486 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2487 .read_nvram = NULL, 2488 .write_nvram = NULL, 2489 .fw_dump = qla27xx_fwdump, 2490 .beacon_on = qla24xx_beacon_on, 2491 .beacon_off = qla24xx_beacon_off, 2492 .beacon_blink = qla83xx_beacon_blink, 2493 .read_optrom = qla25xx_read_optrom_data, 2494 .write_optrom = qla24xx_write_optrom_data, 2495 .get_flash_version = qla24xx_get_flash_version, 2496 .start_scsi = qla24xx_dif_start_scsi, 2497 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2498 .abort_isp = qla2x00_abort_isp, 2499 .iospace_config = qla83xx_iospace_config, 2500 .initialize_adapter = qla2x00_initialize_adapter, 2501 }; 2502 2503 static inline void 2504 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2505 { 2506 ha->device_type = DT_EXTENDED_IDS; 2507 switch (ha->pdev->device) { 2508 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2509 ha->isp_type |= DT_ISP2100; 2510 ha->device_type &= ~DT_EXTENDED_IDS; 2511 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2512 break; 2513 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2514 ha->isp_type |= DT_ISP2200; 2515 ha->device_type &= ~DT_EXTENDED_IDS; 2516 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2517 break; 2518 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2519 ha->isp_type |= DT_ISP2300; 2520 ha->device_type |= DT_ZIO_SUPPORTED; 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2522 break; 2523 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2524 ha->isp_type |= DT_ISP2312; 2525 ha->device_type |= DT_ZIO_SUPPORTED; 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2527 break; 2528 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2529 ha->isp_type |= DT_ISP2322; 2530 ha->device_type |= DT_ZIO_SUPPORTED; 2531 if (ha->pdev->subsystem_vendor == 0x1028 && 2532 ha->pdev->subsystem_device == 0x0170) 2533 ha->device_type |= DT_OEM_001; 2534 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2535 break; 2536 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2537 ha->isp_type |= DT_ISP6312; 2538 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2539 break; 2540 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2541 ha->isp_type |= DT_ISP6322; 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2543 break; 2544 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2545 ha->isp_type |= DT_ISP2422; 2546 ha->device_type |= DT_ZIO_SUPPORTED; 2547 ha->device_type |= DT_FWI2; 2548 ha->device_type |= DT_IIDMA; 2549 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2550 break; 2551 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2552 ha->isp_type |= DT_ISP2432; 2553 ha->device_type |= DT_ZIO_SUPPORTED; 2554 ha->device_type |= DT_FWI2; 2555 ha->device_type |= DT_IIDMA; 2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2557 break; 2558 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2559 ha->isp_type |= DT_ISP8432; 2560 ha->device_type |= DT_ZIO_SUPPORTED; 2561 ha->device_type |= DT_FWI2; 2562 ha->device_type |= DT_IIDMA; 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2564 break; 2565 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2566 ha->isp_type |= DT_ISP5422; 2567 ha->device_type |= DT_FWI2; 2568 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2569 break; 2570 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2571 ha->isp_type |= DT_ISP5432; 2572 ha->device_type |= DT_FWI2; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2576 ha->isp_type |= DT_ISP2532; 2577 ha->device_type |= DT_ZIO_SUPPORTED; 2578 ha->device_type |= DT_FWI2; 2579 ha->device_type |= DT_IIDMA; 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2581 break; 2582 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2583 ha->isp_type |= DT_ISP8001; 2584 ha->device_type |= DT_ZIO_SUPPORTED; 2585 ha->device_type |= DT_FWI2; 2586 ha->device_type |= DT_IIDMA; 2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2588 break; 2589 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2590 ha->isp_type |= DT_ISP8021; 2591 ha->device_type |= DT_ZIO_SUPPORTED; 2592 ha->device_type |= DT_FWI2; 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2594 /* Initialize 82XX ISP flags */ 2595 qla82xx_init_flags(ha); 2596 break; 2597 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2598 ha->isp_type |= DT_ISP8044; 2599 ha->device_type |= DT_ZIO_SUPPORTED; 2600 ha->device_type |= DT_FWI2; 2601 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2602 /* Initialize 82XX ISP flags */ 2603 qla82xx_init_flags(ha); 2604 break; 2605 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2606 ha->isp_type |= DT_ISP2031; 2607 ha->device_type |= DT_ZIO_SUPPORTED; 2608 ha->device_type |= DT_FWI2; 2609 ha->device_type |= DT_IIDMA; 2610 ha->device_type |= DT_T10_PI; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2614 ha->isp_type |= DT_ISP8031; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->device_type |= DT_IIDMA; 2618 ha->device_type |= DT_T10_PI; 2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2620 break; 2621 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2622 ha->isp_type |= DT_ISPFX00; 2623 break; 2624 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2625 ha->isp_type |= DT_ISP2071; 2626 ha->device_type |= DT_ZIO_SUPPORTED; 2627 ha->device_type |= DT_FWI2; 2628 ha->device_type |= DT_IIDMA; 2629 ha->device_type |= DT_T10_PI; 2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2631 break; 2632 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2633 ha->isp_type |= DT_ISP2271; 2634 ha->device_type |= DT_ZIO_SUPPORTED; 2635 ha->device_type |= DT_FWI2; 2636 ha->device_type |= DT_IIDMA; 2637 ha->device_type |= DT_T10_PI; 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2639 break; 2640 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2641 ha->isp_type |= DT_ISP2261; 2642 ha->device_type |= DT_ZIO_SUPPORTED; 2643 ha->device_type |= DT_FWI2; 2644 ha->device_type |= DT_IIDMA; 2645 ha->device_type |= DT_T10_PI; 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2647 break; 2648 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2649 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2650 ha->isp_type |= DT_ISP2081; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->device_type |= DT_FWI2; 2653 ha->device_type |= DT_IIDMA; 2654 ha->device_type |= DT_T10_PI; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 break; 2657 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2658 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2659 ha->isp_type |= DT_ISP2281; 2660 ha->device_type |= DT_ZIO_SUPPORTED; 2661 ha->device_type |= DT_FWI2; 2662 ha->device_type |= DT_IIDMA; 2663 ha->device_type |= DT_T10_PI; 2664 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2665 break; 2666 } 2667 2668 if (IS_QLA82XX(ha)) 2669 ha->port_no = ha->portnum & 1; 2670 else { 2671 /* Get adapter physical port no from interrupt pin register. */ 2672 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2673 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2674 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2675 ha->port_no--; 2676 else 2677 ha->port_no = !(ha->port_no & 1); 2678 } 2679 2680 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2681 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2682 ha->device_type, ha->port_no, ha->fw_srisc_address); 2683 } 2684 2685 static void 2686 qla2xxx_scan_start(struct Scsi_Host *shost) 2687 { 2688 scsi_qla_host_t *vha = shost_priv(shost); 2689 2690 if (vha->hw->flags.running_gold_fw) 2691 return; 2692 2693 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2694 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2695 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2696 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2697 } 2698 2699 static int 2700 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2701 { 2702 scsi_qla_host_t *vha = shost_priv(shost); 2703 2704 if (test_bit(UNLOADING, &vha->dpc_flags)) 2705 return 1; 2706 if (!vha->host) 2707 return 1; 2708 if (time > vha->hw->loop_reset_delay * HZ) 2709 return 1; 2710 2711 return atomic_read(&vha->loop_state) == LOOP_READY; 2712 } 2713 2714 static void qla2x00_iocb_work_fn(struct work_struct *work) 2715 { 2716 struct scsi_qla_host *vha = container_of(work, 2717 struct scsi_qla_host, iocb_work); 2718 struct qla_hw_data *ha = vha->hw; 2719 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2720 int i = 2; 2721 unsigned long flags; 2722 2723 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2724 return; 2725 2726 while (!list_empty(&vha->work_list) && i > 0) { 2727 qla2x00_do_work(vha); 2728 i--; 2729 } 2730 2731 spin_lock_irqsave(&vha->work_lock, flags); 2732 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2733 spin_unlock_irqrestore(&vha->work_lock, flags); 2734 } 2735 2736 /* 2737 * PCI driver interface 2738 */ 2739 static int 2740 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2741 { 2742 int ret = -ENODEV; 2743 struct Scsi_Host *host; 2744 scsi_qla_host_t *base_vha = NULL; 2745 struct qla_hw_data *ha; 2746 char pci_info[30]; 2747 char fw_str[30], wq_name[30]; 2748 struct scsi_host_template *sht; 2749 int bars, mem_only = 0; 2750 uint16_t req_length = 0, rsp_length = 0; 2751 struct req_que *req = NULL; 2752 struct rsp_que *rsp = NULL; 2753 int i; 2754 2755 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2756 sht = &qla2xxx_driver_template; 2757 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2763 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2764 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2765 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2766 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2776 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2777 mem_only = 1; 2778 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2779 "Mem only adapter.\n"); 2780 } 2781 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2782 "Bars=%d.\n", bars); 2783 2784 if (mem_only) { 2785 if (pci_enable_device_mem(pdev)) 2786 return ret; 2787 } else { 2788 if (pci_enable_device(pdev)) 2789 return ret; 2790 } 2791 2792 /* This may fail but that's ok */ 2793 pci_enable_pcie_error_reporting(pdev); 2794 2795 /* Turn off T10-DIF when FC-NVMe is enabled */ 2796 if (ql2xnvmeenable) 2797 ql2xenabledif = 0; 2798 2799 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2800 if (!ha) { 2801 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2802 "Unable to allocate memory for ha.\n"); 2803 goto disable_device; 2804 } 2805 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2806 "Memory allocated for ha=%p.\n", ha); 2807 ha->pdev = pdev; 2808 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2809 spin_lock_init(&ha->tgt.q_full_lock); 2810 spin_lock_init(&ha->tgt.sess_lock); 2811 spin_lock_init(&ha->tgt.atio_lock); 2812 2813 atomic_set(&ha->nvme_active_aen_cnt, 0); 2814 2815 /* Clear our data area */ 2816 ha->bars = bars; 2817 ha->mem_only = mem_only; 2818 spin_lock_init(&ha->hardware_lock); 2819 spin_lock_init(&ha->vport_slock); 2820 mutex_init(&ha->selflogin_lock); 2821 mutex_init(&ha->optrom_mutex); 2822 2823 /* Set ISP-type information. */ 2824 qla2x00_set_isp_flags(ha); 2825 2826 /* Set EEH reset type to fundamental if required by hba */ 2827 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2828 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2829 pdev->needs_freset = 1; 2830 2831 ha->prev_topology = 0; 2832 ha->init_cb_size = sizeof(init_cb_t); 2833 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2834 ha->optrom_size = OPTROM_SIZE_2300; 2835 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2836 atomic_set(&ha->num_pend_mbx_stage1, 0); 2837 atomic_set(&ha->num_pend_mbx_stage2, 0); 2838 atomic_set(&ha->num_pend_mbx_stage3, 0); 2839 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2840 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2841 2842 /* Assign ISP specific operations. */ 2843 if (IS_QLA2100(ha)) { 2844 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2845 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2846 req_length = REQUEST_ENTRY_CNT_2100; 2847 rsp_length = RESPONSE_ENTRY_CNT_2100; 2848 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2849 ha->gid_list_info_size = 4; 2850 ha->flash_conf_off = ~0; 2851 ha->flash_data_off = ~0; 2852 ha->nvram_conf_off = ~0; 2853 ha->nvram_data_off = ~0; 2854 ha->isp_ops = &qla2100_isp_ops; 2855 } else if (IS_QLA2200(ha)) { 2856 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2857 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2858 req_length = REQUEST_ENTRY_CNT_2200; 2859 rsp_length = RESPONSE_ENTRY_CNT_2100; 2860 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2861 ha->gid_list_info_size = 4; 2862 ha->flash_conf_off = ~0; 2863 ha->flash_data_off = ~0; 2864 ha->nvram_conf_off = ~0; 2865 ha->nvram_data_off = ~0; 2866 ha->isp_ops = &qla2100_isp_ops; 2867 } else if (IS_QLA23XX(ha)) { 2868 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2869 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2870 req_length = REQUEST_ENTRY_CNT_2200; 2871 rsp_length = RESPONSE_ENTRY_CNT_2300; 2872 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2873 ha->gid_list_info_size = 6; 2874 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2875 ha->optrom_size = OPTROM_SIZE_2322; 2876 ha->flash_conf_off = ~0; 2877 ha->flash_data_off = ~0; 2878 ha->nvram_conf_off = ~0; 2879 ha->nvram_data_off = ~0; 2880 ha->isp_ops = &qla2300_isp_ops; 2881 } else if (IS_QLA24XX_TYPE(ha)) { 2882 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2883 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2884 req_length = REQUEST_ENTRY_CNT_24XX; 2885 rsp_length = RESPONSE_ENTRY_CNT_2300; 2886 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2887 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2888 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2889 ha->gid_list_info_size = 8; 2890 ha->optrom_size = OPTROM_SIZE_24XX; 2891 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2892 ha->isp_ops = &qla24xx_isp_ops; 2893 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2894 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2895 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2896 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2897 } else if (IS_QLA25XX(ha)) { 2898 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2899 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2900 req_length = REQUEST_ENTRY_CNT_24XX; 2901 rsp_length = RESPONSE_ENTRY_CNT_2300; 2902 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2903 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2904 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2905 ha->gid_list_info_size = 8; 2906 ha->optrom_size = OPTROM_SIZE_25XX; 2907 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2908 ha->isp_ops = &qla25xx_isp_ops; 2909 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2910 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2911 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2912 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2913 } else if (IS_QLA81XX(ha)) { 2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2915 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2916 req_length = REQUEST_ENTRY_CNT_24XX; 2917 rsp_length = RESPONSE_ENTRY_CNT_2300; 2918 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2920 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2921 ha->gid_list_info_size = 8; 2922 ha->optrom_size = OPTROM_SIZE_81XX; 2923 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2924 ha->isp_ops = &qla81xx_isp_ops; 2925 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2926 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2927 ha->nvram_conf_off = ~0; 2928 ha->nvram_data_off = ~0; 2929 } else if (IS_QLA82XX(ha)) { 2930 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2931 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2932 req_length = REQUEST_ENTRY_CNT_82XX; 2933 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2934 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2935 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2936 ha->gid_list_info_size = 8; 2937 ha->optrom_size = OPTROM_SIZE_82XX; 2938 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2939 ha->isp_ops = &qla82xx_isp_ops; 2940 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2941 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2942 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2943 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2944 } else if (IS_QLA8044(ha)) { 2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2946 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2947 req_length = REQUEST_ENTRY_CNT_82XX; 2948 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2949 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2950 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2951 ha->gid_list_info_size = 8; 2952 ha->optrom_size = OPTROM_SIZE_83XX; 2953 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2954 ha->isp_ops = &qla8044_isp_ops; 2955 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2956 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2957 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2958 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2959 } else if (IS_QLA83XX(ha)) { 2960 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2961 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2962 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2963 req_length = REQUEST_ENTRY_CNT_83XX; 2964 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2965 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2967 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2968 ha->gid_list_info_size = 8; 2969 ha->optrom_size = OPTROM_SIZE_83XX; 2970 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2971 ha->isp_ops = &qla83xx_isp_ops; 2972 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2973 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2974 ha->nvram_conf_off = ~0; 2975 ha->nvram_data_off = ~0; 2976 } else if (IS_QLAFX00(ha)) { 2977 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2978 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2979 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2980 req_length = REQUEST_ENTRY_CNT_FX00; 2981 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2982 ha->isp_ops = &qlafx00_isp_ops; 2983 ha->port_down_retry_count = 30; /* default value */ 2984 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2985 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2986 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2987 ha->mr.fw_hbt_en = 1; 2988 ha->mr.host_info_resend = false; 2989 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2990 } else if (IS_QLA27XX(ha)) { 2991 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2993 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2994 req_length = REQUEST_ENTRY_CNT_83XX; 2995 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2996 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2997 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2998 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2999 ha->gid_list_info_size = 8; 3000 ha->optrom_size = OPTROM_SIZE_83XX; 3001 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3002 ha->isp_ops = &qla27xx_isp_ops; 3003 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3004 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3005 ha->nvram_conf_off = ~0; 3006 ha->nvram_data_off = ~0; 3007 } else if (IS_QLA28XX(ha)) { 3008 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3009 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3010 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3011 req_length = REQUEST_ENTRY_CNT_24XX; 3012 rsp_length = RESPONSE_ENTRY_CNT_2300; 3013 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3014 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3015 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3016 ha->gid_list_info_size = 8; 3017 ha->optrom_size = OPTROM_SIZE_28XX; 3018 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3019 ha->isp_ops = &qla27xx_isp_ops; 3020 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3021 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3022 ha->nvram_conf_off = ~0; 3023 ha->nvram_data_off = ~0; 3024 } 3025 3026 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3027 "mbx_count=%d, req_length=%d, " 3028 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3029 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3030 "max_fibre_devices=%d.\n", 3031 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3032 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3033 ha->nvram_npiv_size, ha->max_fibre_devices); 3034 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3035 "isp_ops=%p, flash_conf_off=%d, " 3036 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3037 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3038 ha->nvram_conf_off, ha->nvram_data_off); 3039 3040 /* Configure PCI I/O space */ 3041 ret = ha->isp_ops->iospace_config(ha); 3042 if (ret) 3043 goto iospace_config_failed; 3044 3045 ql_log_pci(ql_log_info, pdev, 0x001d, 3046 "Found an ISP%04X irq %d iobase 0x%p.\n", 3047 pdev->device, pdev->irq, ha->iobase); 3048 mutex_init(&ha->vport_lock); 3049 mutex_init(&ha->mq_lock); 3050 init_completion(&ha->mbx_cmd_comp); 3051 complete(&ha->mbx_cmd_comp); 3052 init_completion(&ha->mbx_intr_comp); 3053 init_completion(&ha->dcbx_comp); 3054 init_completion(&ha->lb_portup_comp); 3055 3056 set_bit(0, (unsigned long *) ha->vp_idx_map); 3057 3058 qla2x00_config_dma_addressing(ha); 3059 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3060 "64 Bit addressing is %s.\n", 3061 ha->flags.enable_64bit_addressing ? "enable" : 3062 "disable"); 3063 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3064 if (ret) { 3065 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3066 "Failed to allocate memory for adapter, aborting.\n"); 3067 3068 goto probe_hw_failed; 3069 } 3070 3071 req->max_q_depth = MAX_Q_DEPTH; 3072 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3073 req->max_q_depth = ql2xmaxqdepth; 3074 3075 3076 base_vha = qla2x00_create_host(sht, ha); 3077 if (!base_vha) { 3078 ret = -ENOMEM; 3079 goto probe_hw_failed; 3080 } 3081 3082 pci_set_drvdata(pdev, base_vha); 3083 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3084 3085 host = base_vha->host; 3086 base_vha->req = req; 3087 if (IS_QLA2XXX_MIDTYPE(ha)) 3088 base_vha->mgmt_svr_loop_id = 3089 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3090 else 3091 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3092 base_vha->vp_idx; 3093 3094 /* Setup fcport template structure. */ 3095 ha->mr.fcport.vha = base_vha; 3096 ha->mr.fcport.port_type = FCT_UNKNOWN; 3097 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3098 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3099 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3100 ha->mr.fcport.scan_state = 1; 3101 3102 /* Set the SG table size based on ISP type */ 3103 if (!IS_FWI2_CAPABLE(ha)) { 3104 if (IS_QLA2100(ha)) 3105 host->sg_tablesize = 32; 3106 } else { 3107 if (!IS_QLA82XX(ha)) 3108 host->sg_tablesize = QLA_SG_ALL; 3109 } 3110 host->max_id = ha->max_fibre_devices; 3111 host->cmd_per_lun = 3; 3112 host->unique_id = host->host_no; 3113 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3114 host->max_cmd_len = 32; 3115 else 3116 host->max_cmd_len = MAX_CMDSZ; 3117 host->max_channel = MAX_BUSES - 1; 3118 /* Older HBAs support only 16-bit LUNs */ 3119 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3120 ql2xmaxlun > 0xffff) 3121 host->max_lun = 0xffff; 3122 else 3123 host->max_lun = ql2xmaxlun; 3124 host->transportt = qla2xxx_transport_template; 3125 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3126 3127 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3128 "max_id=%d this_id=%d " 3129 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3130 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3131 host->this_id, host->cmd_per_lun, host->unique_id, 3132 host->max_cmd_len, host->max_channel, host->max_lun, 3133 host->transportt, sht->vendor_id); 3134 3135 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3136 3137 /* Set up the irqs */ 3138 ret = qla2x00_request_irqs(ha, rsp); 3139 if (ret) 3140 goto probe_failed; 3141 3142 /* Alloc arrays of request and response ring ptrs */ 3143 ret = qla2x00_alloc_queues(ha, req, rsp); 3144 if (ret) { 3145 ql_log(ql_log_fatal, base_vha, 0x003d, 3146 "Failed to allocate memory for queue pointers..." 3147 "aborting.\n"); 3148 ret = -ENODEV; 3149 goto probe_failed; 3150 } 3151 3152 if (ha->mqenable) { 3153 /* number of hardware queues supported by blk/scsi-mq*/ 3154 host->nr_hw_queues = ha->max_qpairs; 3155 3156 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3157 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3158 } else { 3159 if (ql2xnvmeenable) { 3160 host->nr_hw_queues = ha->max_qpairs; 3161 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3162 "FC-NVMe support is enabled, HW queues=%d\n", 3163 host->nr_hw_queues); 3164 } else { 3165 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3166 "blk/scsi-mq disabled.\n"); 3167 } 3168 } 3169 3170 qlt_probe_one_stage1(base_vha, ha); 3171 3172 pci_save_state(pdev); 3173 3174 /* Assign back pointers */ 3175 rsp->req = req; 3176 req->rsp = rsp; 3177 3178 if (IS_QLAFX00(ha)) { 3179 ha->rsp_q_map[0] = rsp; 3180 ha->req_q_map[0] = req; 3181 set_bit(0, ha->req_qid_map); 3182 set_bit(0, ha->rsp_qid_map); 3183 } 3184 3185 /* FWI2-capable only. */ 3186 req->req_q_in = &ha->iobase->isp24.req_q_in; 3187 req->req_q_out = &ha->iobase->isp24.req_q_out; 3188 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3189 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3190 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3191 IS_QLA28XX(ha)) { 3192 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3193 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3194 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3195 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3196 } 3197 3198 if (IS_QLAFX00(ha)) { 3199 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3200 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3201 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3202 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3203 } 3204 3205 if (IS_P3P_TYPE(ha)) { 3206 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3207 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3208 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3209 } 3210 3211 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3212 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3213 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3214 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3215 "req->req_q_in=%p req->req_q_out=%p " 3216 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3217 req->req_q_in, req->req_q_out, 3218 rsp->rsp_q_in, rsp->rsp_q_out); 3219 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3220 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3221 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3222 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3223 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3224 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3225 3226 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3227 3228 if (ha->isp_ops->initialize_adapter(base_vha)) { 3229 ql_log(ql_log_fatal, base_vha, 0x00d6, 3230 "Failed to initialize adapter - Adapter flags %x.\n", 3231 base_vha->device_flags); 3232 3233 if (IS_QLA82XX(ha)) { 3234 qla82xx_idc_lock(ha); 3235 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3236 QLA8XXX_DEV_FAILED); 3237 qla82xx_idc_unlock(ha); 3238 ql_log(ql_log_fatal, base_vha, 0x00d7, 3239 "HW State: FAILED.\n"); 3240 } else if (IS_QLA8044(ha)) { 3241 qla8044_idc_lock(ha); 3242 qla8044_wr_direct(base_vha, 3243 QLA8044_CRB_DEV_STATE_INDEX, 3244 QLA8XXX_DEV_FAILED); 3245 qla8044_idc_unlock(ha); 3246 ql_log(ql_log_fatal, base_vha, 0x0150, 3247 "HW State: FAILED.\n"); 3248 } 3249 3250 ret = -ENODEV; 3251 goto probe_failed; 3252 } 3253 3254 if (IS_QLAFX00(ha)) 3255 host->can_queue = QLAFX00_MAX_CANQUEUE; 3256 else 3257 host->can_queue = req->num_outstanding_cmds - 10; 3258 3259 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3260 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3261 host->can_queue, base_vha->req, 3262 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3263 3264 if (ha->mqenable) { 3265 bool startit = false; 3266 3267 if (QLA_TGT_MODE_ENABLED()) 3268 startit = false; 3269 3270 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3271 startit = true; 3272 3273 /* Create start of day qpairs for Block MQ */ 3274 for (i = 0; i < ha->max_qpairs; i++) 3275 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3276 } 3277 3278 if (ha->flags.running_gold_fw) 3279 goto skip_dpc; 3280 3281 /* 3282 * Startup the kernel thread for this host adapter 3283 */ 3284 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3285 "%s_dpc", base_vha->host_str); 3286 if (IS_ERR(ha->dpc_thread)) { 3287 ql_log(ql_log_fatal, base_vha, 0x00ed, 3288 "Failed to start DPC thread.\n"); 3289 ret = PTR_ERR(ha->dpc_thread); 3290 ha->dpc_thread = NULL; 3291 goto probe_failed; 3292 } 3293 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3294 "DPC thread started successfully.\n"); 3295 3296 /* 3297 * If we're not coming up in initiator mode, we might sit for 3298 * a while without waking up the dpc thread, which leads to a 3299 * stuck process warning. So just kick the dpc once here and 3300 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3301 */ 3302 qla2xxx_wake_dpc(base_vha); 3303 3304 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3305 3306 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3307 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3308 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3309 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3310 3311 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3312 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3313 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3314 INIT_WORK(&ha->idc_state_handler, 3315 qla83xx_idc_state_handler_work); 3316 INIT_WORK(&ha->nic_core_unrecoverable, 3317 qla83xx_nic_core_unrecoverable_work); 3318 } 3319 3320 skip_dpc: 3321 list_add_tail(&base_vha->list, &ha->vp_list); 3322 base_vha->host->irq = ha->pdev->irq; 3323 3324 /* Initialized the timer */ 3325 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3326 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3327 "Started qla2x00_timer with " 3328 "interval=%d.\n", WATCH_INTERVAL); 3329 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3330 "Detected hba at address=%p.\n", 3331 ha); 3332 3333 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3334 if (ha->fw_attributes & BIT_4) { 3335 int prot = 0, guard; 3336 3337 base_vha->flags.difdix_supported = 1; 3338 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3339 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3340 if (ql2xenabledif == 1) 3341 prot = SHOST_DIX_TYPE0_PROTECTION; 3342 if (ql2xprotmask) 3343 scsi_host_set_prot(host, ql2xprotmask); 3344 else 3345 scsi_host_set_prot(host, 3346 prot | SHOST_DIF_TYPE1_PROTECTION 3347 | SHOST_DIF_TYPE2_PROTECTION 3348 | SHOST_DIF_TYPE3_PROTECTION 3349 | SHOST_DIX_TYPE1_PROTECTION 3350 | SHOST_DIX_TYPE2_PROTECTION 3351 | SHOST_DIX_TYPE3_PROTECTION); 3352 3353 guard = SHOST_DIX_GUARD_CRC; 3354 3355 if (IS_PI_IPGUARD_CAPABLE(ha) && 3356 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3357 guard |= SHOST_DIX_GUARD_IP; 3358 3359 if (ql2xprotguard) 3360 scsi_host_set_guard(host, ql2xprotguard); 3361 else 3362 scsi_host_set_guard(host, guard); 3363 } else 3364 base_vha->flags.difdix_supported = 0; 3365 } 3366 3367 ha->isp_ops->enable_intrs(ha); 3368 3369 if (IS_QLAFX00(ha)) { 3370 ret = qlafx00_fx_disc(base_vha, 3371 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3372 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3373 QLA_SG_ALL : 128; 3374 } 3375 3376 ret = scsi_add_host(host, &pdev->dev); 3377 if (ret) 3378 goto probe_failed; 3379 3380 base_vha->flags.init_done = 1; 3381 base_vha->flags.online = 1; 3382 ha->prev_minidump_failed = 0; 3383 3384 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3385 "Init done and hba is online.\n"); 3386 3387 if (qla_ini_mode_enabled(base_vha) || 3388 qla_dual_mode_enabled(base_vha)) 3389 scsi_scan_host(host); 3390 else 3391 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3392 "skipping scsi_scan_host() for non-initiator port\n"); 3393 3394 qla2x00_alloc_sysfs_attr(base_vha); 3395 3396 if (IS_QLAFX00(ha)) { 3397 ret = qlafx00_fx_disc(base_vha, 3398 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3399 3400 /* Register system information */ 3401 ret = qlafx00_fx_disc(base_vha, 3402 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3403 } 3404 3405 qla2x00_init_host_attr(base_vha); 3406 3407 qla2x00_dfs_setup(base_vha); 3408 3409 ql_log(ql_log_info, base_vha, 0x00fb, 3410 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3411 ql_log(ql_log_info, base_vha, 0x00fc, 3412 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3413 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3414 sizeof(pci_info)), 3415 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3416 base_vha->host_no, 3417 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3418 3419 qlt_add_target(ha, base_vha); 3420 3421 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3422 3423 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3424 return -ENODEV; 3425 3426 if (ha->flags.detected_lr_sfp) { 3427 ql_log(ql_log_info, base_vha, 0xffff, 3428 "Reset chip to pick up LR SFP setting\n"); 3429 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3430 qla2xxx_wake_dpc(base_vha); 3431 } 3432 3433 return 0; 3434 3435 probe_failed: 3436 if (base_vha->gnl.l) { 3437 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3438 base_vha->gnl.l, base_vha->gnl.ldma); 3439 base_vha->gnl.l = NULL; 3440 } 3441 3442 if (base_vha->timer_active) 3443 qla2x00_stop_timer(base_vha); 3444 base_vha->flags.online = 0; 3445 if (ha->dpc_thread) { 3446 struct task_struct *t = ha->dpc_thread; 3447 3448 ha->dpc_thread = NULL; 3449 kthread_stop(t); 3450 } 3451 3452 qla2x00_free_device(base_vha); 3453 scsi_host_put(base_vha->host); 3454 /* 3455 * Need to NULL out local req/rsp after 3456 * qla2x00_free_device => qla2x00_free_queues frees 3457 * what these are pointing to. Or else we'll 3458 * fall over below in qla2x00_free_req/rsp_que. 3459 */ 3460 req = NULL; 3461 rsp = NULL; 3462 3463 probe_hw_failed: 3464 qla2x00_mem_free(ha); 3465 qla2x00_free_req_que(ha, req); 3466 qla2x00_free_rsp_que(ha, rsp); 3467 qla2x00_clear_drv_active(ha); 3468 3469 iospace_config_failed: 3470 if (IS_P3P_TYPE(ha)) { 3471 if (!ha->nx_pcibase) 3472 iounmap((device_reg_t *)ha->nx_pcibase); 3473 if (!ql2xdbwr) 3474 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3475 } else { 3476 if (ha->iobase) 3477 iounmap(ha->iobase); 3478 if (ha->cregbase) 3479 iounmap(ha->cregbase); 3480 } 3481 pci_release_selected_regions(ha->pdev, ha->bars); 3482 kfree(ha); 3483 3484 disable_device: 3485 pci_disable_device(pdev); 3486 return ret; 3487 } 3488 3489 static void 3490 qla2x00_shutdown(struct pci_dev *pdev) 3491 { 3492 scsi_qla_host_t *vha; 3493 struct qla_hw_data *ha; 3494 3495 vha = pci_get_drvdata(pdev); 3496 ha = vha->hw; 3497 3498 ql_log(ql_log_info, vha, 0xfffa, 3499 "Adapter shutdown\n"); 3500 3501 /* 3502 * Prevent future board_disable and wait 3503 * until any pending board_disable has completed. 3504 */ 3505 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3506 cancel_work_sync(&ha->board_disable); 3507 3508 if (!atomic_read(&pdev->enable_cnt)) 3509 return; 3510 3511 /* Notify ISPFX00 firmware */ 3512 if (IS_QLAFX00(ha)) 3513 qlafx00_driver_shutdown(vha, 20); 3514 3515 /* Turn-off FCE trace */ 3516 if (ha->flags.fce_enabled) { 3517 qla2x00_disable_fce_trace(vha, NULL, NULL); 3518 ha->flags.fce_enabled = 0; 3519 } 3520 3521 /* Turn-off EFT trace */ 3522 if (ha->eft) 3523 qla2x00_disable_eft_trace(vha); 3524 3525 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3526 IS_QLA28XX(ha)) { 3527 if (ha->flags.fw_started) 3528 qla2x00_abort_isp_cleanup(vha); 3529 } else { 3530 /* Stop currently executing firmware. */ 3531 qla2x00_try_to_stop_firmware(vha); 3532 } 3533 3534 /* Turn adapter off line */ 3535 vha->flags.online = 0; 3536 3537 /* turn-off interrupts on the card */ 3538 if (ha->interrupts_on) { 3539 vha->flags.init_done = 0; 3540 ha->isp_ops->disable_intrs(ha); 3541 } 3542 3543 qla2x00_free_irqs(vha); 3544 3545 qla2x00_free_fw_dump(ha); 3546 3547 pci_disable_device(pdev); 3548 ql_log(ql_log_info, vha, 0xfffe, 3549 "Adapter shutdown successfully.\n"); 3550 } 3551 3552 /* Deletes all the virtual ports for a given ha */ 3553 static void 3554 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3555 { 3556 scsi_qla_host_t *vha; 3557 unsigned long flags; 3558 3559 mutex_lock(&ha->vport_lock); 3560 while (ha->cur_vport_count) { 3561 spin_lock_irqsave(&ha->vport_slock, flags); 3562 3563 BUG_ON(base_vha->list.next == &ha->vp_list); 3564 /* This assumes first entry in ha->vp_list is always base vha */ 3565 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3566 scsi_host_get(vha->host); 3567 3568 spin_unlock_irqrestore(&ha->vport_slock, flags); 3569 mutex_unlock(&ha->vport_lock); 3570 3571 qla_nvme_delete(vha); 3572 3573 fc_vport_terminate(vha->fc_vport); 3574 scsi_host_put(vha->host); 3575 3576 mutex_lock(&ha->vport_lock); 3577 } 3578 mutex_unlock(&ha->vport_lock); 3579 } 3580 3581 /* Stops all deferred work threads */ 3582 static void 3583 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3584 { 3585 /* Cancel all work and destroy DPC workqueues */ 3586 if (ha->dpc_lp_wq) { 3587 cancel_work_sync(&ha->idc_aen); 3588 destroy_workqueue(ha->dpc_lp_wq); 3589 ha->dpc_lp_wq = NULL; 3590 } 3591 3592 if (ha->dpc_hp_wq) { 3593 cancel_work_sync(&ha->nic_core_reset); 3594 cancel_work_sync(&ha->idc_state_handler); 3595 cancel_work_sync(&ha->nic_core_unrecoverable); 3596 destroy_workqueue(ha->dpc_hp_wq); 3597 ha->dpc_hp_wq = NULL; 3598 } 3599 3600 /* Kill the kernel thread for this host */ 3601 if (ha->dpc_thread) { 3602 struct task_struct *t = ha->dpc_thread; 3603 3604 /* 3605 * qla2xxx_wake_dpc checks for ->dpc_thread 3606 * so we need to zero it out. 3607 */ 3608 ha->dpc_thread = NULL; 3609 kthread_stop(t); 3610 } 3611 } 3612 3613 static void 3614 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3615 { 3616 if (IS_QLA82XX(ha)) { 3617 3618 iounmap((device_reg_t *)ha->nx_pcibase); 3619 if (!ql2xdbwr) 3620 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3621 } else { 3622 if (ha->iobase) 3623 iounmap(ha->iobase); 3624 3625 if (ha->cregbase) 3626 iounmap(ha->cregbase); 3627 3628 if (ha->mqiobase) 3629 iounmap(ha->mqiobase); 3630 3631 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3632 ha->msixbase) 3633 iounmap(ha->msixbase); 3634 } 3635 } 3636 3637 static void 3638 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3639 { 3640 if (IS_QLA8044(ha)) { 3641 qla8044_idc_lock(ha); 3642 qla8044_clear_drv_active(ha); 3643 qla8044_idc_unlock(ha); 3644 } else if (IS_QLA82XX(ha)) { 3645 qla82xx_idc_lock(ha); 3646 qla82xx_clear_drv_active(ha); 3647 qla82xx_idc_unlock(ha); 3648 } 3649 } 3650 3651 static void 3652 qla2x00_remove_one(struct pci_dev *pdev) 3653 { 3654 scsi_qla_host_t *base_vha; 3655 struct qla_hw_data *ha; 3656 3657 base_vha = pci_get_drvdata(pdev); 3658 ha = base_vha->hw; 3659 ql_log(ql_log_info, base_vha, 0xb079, 3660 "Removing driver\n"); 3661 3662 /* Indicate device removal to prevent future board_disable and wait 3663 * until any pending board_disable has completed. */ 3664 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3665 cancel_work_sync(&ha->board_disable); 3666 3667 /* 3668 * If the PCI device is disabled then there was a PCI-disconnect and 3669 * qla2x00_disable_board_on_pci_error has taken care of most of the 3670 * resources. 3671 */ 3672 if (!atomic_read(&pdev->enable_cnt)) { 3673 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3674 base_vha->gnl.l, base_vha->gnl.ldma); 3675 base_vha->gnl.l = NULL; 3676 scsi_host_put(base_vha->host); 3677 kfree(ha); 3678 pci_set_drvdata(pdev, NULL); 3679 return; 3680 } 3681 qla2x00_wait_for_hba_ready(base_vha); 3682 3683 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3684 IS_QLA28XX(ha)) { 3685 if (ha->flags.fw_started) 3686 qla2x00_abort_isp_cleanup(base_vha); 3687 } else if (!IS_QLAFX00(ha)) { 3688 if (IS_QLA8031(ha)) { 3689 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3690 "Clearing fcoe driver presence.\n"); 3691 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3692 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3693 "Error while clearing DRV-Presence.\n"); 3694 } 3695 3696 qla2x00_try_to_stop_firmware(base_vha); 3697 } 3698 3699 qla2x00_wait_for_sess_deletion(base_vha); 3700 3701 /* 3702 * if UNLOAD flag is already set, then continue unload, 3703 * where it was set first. 3704 */ 3705 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3706 return; 3707 3708 set_bit(UNLOADING, &base_vha->dpc_flags); 3709 3710 qla_nvme_delete(base_vha); 3711 3712 dma_free_coherent(&ha->pdev->dev, 3713 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3714 3715 base_vha->gnl.l = NULL; 3716 3717 vfree(base_vha->scan.l); 3718 3719 if (IS_QLAFX00(ha)) 3720 qlafx00_driver_shutdown(base_vha, 20); 3721 3722 qla2x00_delete_all_vps(ha, base_vha); 3723 3724 qla2x00_dfs_remove(base_vha); 3725 3726 qla84xx_put_chip(base_vha); 3727 3728 /* Disable timer */ 3729 if (base_vha->timer_active) 3730 qla2x00_stop_timer(base_vha); 3731 3732 base_vha->flags.online = 0; 3733 3734 /* free DMA memory */ 3735 if (ha->exlogin_buf) 3736 qla2x00_free_exlogin_buffer(ha); 3737 3738 /* free DMA memory */ 3739 if (ha->exchoffld_buf) 3740 qla2x00_free_exchoffld_buffer(ha); 3741 3742 qla2x00_destroy_deferred_work(ha); 3743 3744 qlt_remove_target(ha, base_vha); 3745 3746 qla2x00_free_sysfs_attr(base_vha, true); 3747 3748 fc_remove_host(base_vha->host); 3749 qlt_remove_target_resources(ha); 3750 3751 scsi_remove_host(base_vha->host); 3752 3753 qla2x00_free_device(base_vha); 3754 3755 qla2x00_clear_drv_active(ha); 3756 3757 scsi_host_put(base_vha->host); 3758 3759 qla2x00_unmap_iobases(ha); 3760 3761 pci_release_selected_regions(ha->pdev, ha->bars); 3762 kfree(ha); 3763 3764 pci_disable_pcie_error_reporting(pdev); 3765 3766 pci_disable_device(pdev); 3767 } 3768 3769 static void 3770 qla2x00_free_device(scsi_qla_host_t *vha) 3771 { 3772 struct qla_hw_data *ha = vha->hw; 3773 3774 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3775 3776 /* Disable timer */ 3777 if (vha->timer_active) 3778 qla2x00_stop_timer(vha); 3779 3780 qla25xx_delete_queues(vha); 3781 vha->flags.online = 0; 3782 3783 /* turn-off interrupts on the card */ 3784 if (ha->interrupts_on) { 3785 vha->flags.init_done = 0; 3786 ha->isp_ops->disable_intrs(ha); 3787 } 3788 3789 qla2x00_free_fcports(vha); 3790 3791 qla2x00_free_irqs(vha); 3792 3793 /* Flush the work queue and remove it */ 3794 if (ha->wq) { 3795 flush_workqueue(ha->wq); 3796 destroy_workqueue(ha->wq); 3797 ha->wq = NULL; 3798 } 3799 3800 3801 qla2x00_mem_free(ha); 3802 3803 qla82xx_md_free(vha); 3804 3805 qla2x00_free_queues(ha); 3806 } 3807 3808 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3809 { 3810 fc_port_t *fcport, *tfcport; 3811 3812 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3813 qla2x00_free_fcport(fcport); 3814 } 3815 3816 static inline void 3817 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3818 int defer) 3819 { 3820 struct fc_rport *rport; 3821 scsi_qla_host_t *base_vha; 3822 unsigned long flags; 3823 3824 if (!fcport->rport) 3825 return; 3826 3827 rport = fcport->rport; 3828 if (defer) { 3829 base_vha = pci_get_drvdata(vha->hw->pdev); 3830 spin_lock_irqsave(vha->host->host_lock, flags); 3831 fcport->drport = rport; 3832 spin_unlock_irqrestore(vha->host->host_lock, flags); 3833 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3834 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3835 qla2xxx_wake_dpc(base_vha); 3836 } else { 3837 int now; 3838 3839 if (rport) { 3840 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3841 "%s %8phN. rport %p roles %x\n", 3842 __func__, fcport->port_name, rport, 3843 rport->roles); 3844 fc_remote_port_delete(rport); 3845 } 3846 qlt_do_generation_tick(vha, &now); 3847 } 3848 } 3849 3850 /* 3851 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3852 * 3853 * Input: ha = adapter block pointer. fcport = port structure pointer. 3854 * 3855 * Return: None. 3856 * 3857 * Context: 3858 */ 3859 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3860 int do_login, int defer) 3861 { 3862 if (IS_QLAFX00(vha->hw)) { 3863 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3864 qla2x00_schedule_rport_del(vha, fcport, defer); 3865 return; 3866 } 3867 3868 if (atomic_read(&fcport->state) == FCS_ONLINE && 3869 vha->vp_idx == fcport->vha->vp_idx) { 3870 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3871 qla2x00_schedule_rport_del(vha, fcport, defer); 3872 } 3873 /* 3874 * We may need to retry the login, so don't change the state of the 3875 * port but do the retries. 3876 */ 3877 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3878 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3879 3880 if (!do_login) 3881 return; 3882 3883 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3884 } 3885 3886 /* 3887 * qla2x00_mark_all_devices_lost 3888 * Updates fcport state when device goes offline. 3889 * 3890 * Input: 3891 * ha = adapter block pointer. 3892 * fcport = port structure pointer. 3893 * 3894 * Return: 3895 * None. 3896 * 3897 * Context: 3898 */ 3899 void 3900 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3901 { 3902 fc_port_t *fcport; 3903 3904 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3905 "Mark all dev lost\n"); 3906 3907 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3908 fcport->scan_state = 0; 3909 qlt_schedule_sess_for_deletion(fcport); 3910 3911 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3912 continue; 3913 3914 /* 3915 * No point in marking the device as lost, if the device is 3916 * already DEAD. 3917 */ 3918 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3919 continue; 3920 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3921 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3922 if (defer) 3923 qla2x00_schedule_rport_del(vha, fcport, defer); 3924 else if (vha->vp_idx == fcport->vha->vp_idx) 3925 qla2x00_schedule_rport_del(vha, fcport, defer); 3926 } 3927 } 3928 } 3929 3930 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3931 { 3932 int i; 3933 3934 if (IS_FWI2_CAPABLE(ha)) 3935 return; 3936 3937 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3938 set_bit(i, ha->loop_id_map); 3939 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3940 set_bit(BROADCAST, ha->loop_id_map); 3941 } 3942 3943 /* 3944 * qla2x00_mem_alloc 3945 * Allocates adapter memory. 3946 * 3947 * Returns: 3948 * 0 = success. 3949 * !0 = failure. 3950 */ 3951 static int 3952 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3953 struct req_que **req, struct rsp_que **rsp) 3954 { 3955 char name[16]; 3956 3957 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3958 &ha->init_cb_dma, GFP_KERNEL); 3959 if (!ha->init_cb) 3960 goto fail; 3961 3962 if (qlt_mem_alloc(ha) < 0) 3963 goto fail_free_init_cb; 3964 3965 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3966 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3967 if (!ha->gid_list) 3968 goto fail_free_tgt_mem; 3969 3970 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3971 if (!ha->srb_mempool) 3972 goto fail_free_gid_list; 3973 3974 if (IS_P3P_TYPE(ha)) { 3975 /* Allocate cache for CT6 Ctx. */ 3976 if (!ctx_cachep) { 3977 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3978 sizeof(struct ct6_dsd), 0, 3979 SLAB_HWCACHE_ALIGN, NULL); 3980 if (!ctx_cachep) 3981 goto fail_free_srb_mempool; 3982 } 3983 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3984 ctx_cachep); 3985 if (!ha->ctx_mempool) 3986 goto fail_free_srb_mempool; 3987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3988 "ctx_cachep=%p ctx_mempool=%p.\n", 3989 ctx_cachep, ha->ctx_mempool); 3990 } 3991 3992 /* Get memory for cached NVRAM */ 3993 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3994 if (!ha->nvram) 3995 goto fail_free_ctx_mempool; 3996 3997 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3998 ha->pdev->device); 3999 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4000 DMA_POOL_SIZE, 8, 0); 4001 if (!ha->s_dma_pool) 4002 goto fail_free_nvram; 4003 4004 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4005 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4006 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4007 4008 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4009 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4010 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4011 if (!ha->dl_dma_pool) { 4012 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4013 "Failed to allocate memory for dl_dma_pool.\n"); 4014 goto fail_s_dma_pool; 4015 } 4016 4017 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4018 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4019 if (!ha->fcp_cmnd_dma_pool) { 4020 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4021 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4022 goto fail_dl_dma_pool; 4023 } 4024 4025 if (ql2xenabledif) { 4026 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4027 struct dsd_dma *dsd, *nxt; 4028 uint i; 4029 /* Creata a DMA pool of buffers for DIF bundling */ 4030 ha->dif_bundl_pool = dma_pool_create(name, 4031 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4032 if (!ha->dif_bundl_pool) { 4033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4034 "%s: failed create dif_bundl_pool\n", 4035 __func__); 4036 goto fail_dif_bundl_dma_pool; 4037 } 4038 4039 INIT_LIST_HEAD(&ha->pool.good.head); 4040 INIT_LIST_HEAD(&ha->pool.unusable.head); 4041 ha->pool.good.count = 0; 4042 ha->pool.unusable.count = 0; 4043 for (i = 0; i < 128; i++) { 4044 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4045 if (!dsd) { 4046 ql_dbg_pci(ql_dbg_init, ha->pdev, 4047 0xe0ee, "%s: failed alloc dsd\n", 4048 __func__); 4049 return 1; 4050 } 4051 ha->dif_bundle_kallocs++; 4052 4053 dsd->dsd_addr = dma_pool_alloc( 4054 ha->dif_bundl_pool, GFP_ATOMIC, 4055 &dsd->dsd_list_dma); 4056 if (!dsd->dsd_addr) { 4057 ql_dbg_pci(ql_dbg_init, ha->pdev, 4058 0xe0ee, 4059 "%s: failed alloc ->dsd_addr\n", 4060 __func__); 4061 kfree(dsd); 4062 ha->dif_bundle_kallocs--; 4063 continue; 4064 } 4065 ha->dif_bundle_dma_allocs++; 4066 4067 /* 4068 * if DMA buffer crosses 4G boundary, 4069 * put it on bad list 4070 */ 4071 if (MSD(dsd->dsd_list_dma) ^ 4072 MSD(dsd->dsd_list_dma + bufsize)) { 4073 list_add_tail(&dsd->list, 4074 &ha->pool.unusable.head); 4075 ha->pool.unusable.count++; 4076 } else { 4077 list_add_tail(&dsd->list, 4078 &ha->pool.good.head); 4079 ha->pool.good.count++; 4080 } 4081 } 4082 4083 /* return the good ones back to the pool */ 4084 list_for_each_entry_safe(dsd, nxt, 4085 &ha->pool.good.head, list) { 4086 list_del(&dsd->list); 4087 dma_pool_free(ha->dif_bundl_pool, 4088 dsd->dsd_addr, dsd->dsd_list_dma); 4089 ha->dif_bundle_dma_allocs--; 4090 kfree(dsd); 4091 ha->dif_bundle_kallocs--; 4092 } 4093 4094 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4095 "%s: dif dma pool (good=%u unusable=%u)\n", 4096 __func__, ha->pool.good.count, 4097 ha->pool.unusable.count); 4098 } 4099 4100 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4101 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4102 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4103 ha->dif_bundl_pool); 4104 } 4105 4106 /* Allocate memory for SNS commands */ 4107 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4108 /* Get consistent memory allocated for SNS commands */ 4109 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4110 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4111 if (!ha->sns_cmd) 4112 goto fail_dma_pool; 4113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4114 "sns_cmd: %p.\n", ha->sns_cmd); 4115 } else { 4116 /* Get consistent memory allocated for MS IOCB */ 4117 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4118 &ha->ms_iocb_dma); 4119 if (!ha->ms_iocb) 4120 goto fail_dma_pool; 4121 /* Get consistent memory allocated for CT SNS commands */ 4122 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4123 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4124 if (!ha->ct_sns) 4125 goto fail_free_ms_iocb; 4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4127 "ms_iocb=%p ct_sns=%p.\n", 4128 ha->ms_iocb, ha->ct_sns); 4129 } 4130 4131 /* Allocate memory for request ring */ 4132 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4133 if (!*req) { 4134 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4135 "Failed to allocate memory for req.\n"); 4136 goto fail_req; 4137 } 4138 (*req)->length = req_len; 4139 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4140 ((*req)->length + 1) * sizeof(request_t), 4141 &(*req)->dma, GFP_KERNEL); 4142 if (!(*req)->ring) { 4143 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4144 "Failed to allocate memory for req_ring.\n"); 4145 goto fail_req_ring; 4146 } 4147 /* Allocate memory for response ring */ 4148 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4149 if (!*rsp) { 4150 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4151 "Failed to allocate memory for rsp.\n"); 4152 goto fail_rsp; 4153 } 4154 (*rsp)->hw = ha; 4155 (*rsp)->length = rsp_len; 4156 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4157 ((*rsp)->length + 1) * sizeof(response_t), 4158 &(*rsp)->dma, GFP_KERNEL); 4159 if (!(*rsp)->ring) { 4160 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4161 "Failed to allocate memory for rsp_ring.\n"); 4162 goto fail_rsp_ring; 4163 } 4164 (*req)->rsp = *rsp; 4165 (*rsp)->req = *req; 4166 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4167 "req=%p req->length=%d req->ring=%p rsp=%p " 4168 "rsp->length=%d rsp->ring=%p.\n", 4169 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4170 (*rsp)->ring); 4171 /* Allocate memory for NVRAM data for vports */ 4172 if (ha->nvram_npiv_size) { 4173 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4174 sizeof(struct qla_npiv_entry), 4175 GFP_KERNEL); 4176 if (!ha->npiv_info) { 4177 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4178 "Failed to allocate memory for npiv_info.\n"); 4179 goto fail_npiv_info; 4180 } 4181 } else 4182 ha->npiv_info = NULL; 4183 4184 /* Get consistent memory allocated for EX-INIT-CB. */ 4185 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4186 IS_QLA28XX(ha)) { 4187 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4188 &ha->ex_init_cb_dma); 4189 if (!ha->ex_init_cb) 4190 goto fail_ex_init_cb; 4191 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4192 "ex_init_cb=%p.\n", ha->ex_init_cb); 4193 } 4194 4195 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4196 4197 /* Get consistent memory allocated for Async Port-Database. */ 4198 if (!IS_FWI2_CAPABLE(ha)) { 4199 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4200 &ha->async_pd_dma); 4201 if (!ha->async_pd) 4202 goto fail_async_pd; 4203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4204 "async_pd=%p.\n", ha->async_pd); 4205 } 4206 4207 INIT_LIST_HEAD(&ha->vp_list); 4208 4209 /* Allocate memory for our loop_id bitmap */ 4210 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4211 sizeof(long), 4212 GFP_KERNEL); 4213 if (!ha->loop_id_map) 4214 goto fail_loop_id_map; 4215 else { 4216 qla2x00_set_reserved_loop_ids(ha); 4217 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4218 "loop_id_map=%p.\n", ha->loop_id_map); 4219 } 4220 4221 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4222 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4223 if (!ha->sfp_data) { 4224 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4225 "Unable to allocate memory for SFP read-data.\n"); 4226 goto fail_sfp_data; 4227 } 4228 4229 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4230 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4231 GFP_KERNEL); 4232 if (!ha->flt) { 4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4234 "Unable to allocate memory for FLT.\n"); 4235 goto fail_flt_buffer; 4236 } 4237 4238 return 0; 4239 4240 fail_flt_buffer: 4241 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4242 ha->sfp_data, ha->sfp_data_dma); 4243 fail_sfp_data: 4244 kfree(ha->loop_id_map); 4245 fail_loop_id_map: 4246 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4247 fail_async_pd: 4248 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4249 fail_ex_init_cb: 4250 kfree(ha->npiv_info); 4251 fail_npiv_info: 4252 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4253 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4254 (*rsp)->ring = NULL; 4255 (*rsp)->dma = 0; 4256 fail_rsp_ring: 4257 kfree(*rsp); 4258 *rsp = NULL; 4259 fail_rsp: 4260 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4261 sizeof(request_t), (*req)->ring, (*req)->dma); 4262 (*req)->ring = NULL; 4263 (*req)->dma = 0; 4264 fail_req_ring: 4265 kfree(*req); 4266 *req = NULL; 4267 fail_req: 4268 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4269 ha->ct_sns, ha->ct_sns_dma); 4270 ha->ct_sns = NULL; 4271 ha->ct_sns_dma = 0; 4272 fail_free_ms_iocb: 4273 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4274 ha->ms_iocb = NULL; 4275 ha->ms_iocb_dma = 0; 4276 4277 if (ha->sns_cmd) 4278 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4279 ha->sns_cmd, ha->sns_cmd_dma); 4280 fail_dma_pool: 4281 if (ql2xenabledif) { 4282 struct dsd_dma *dsd, *nxt; 4283 4284 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4285 list) { 4286 list_del(&dsd->list); 4287 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4288 dsd->dsd_list_dma); 4289 ha->dif_bundle_dma_allocs--; 4290 kfree(dsd); 4291 ha->dif_bundle_kallocs--; 4292 ha->pool.unusable.count--; 4293 } 4294 dma_pool_destroy(ha->dif_bundl_pool); 4295 ha->dif_bundl_pool = NULL; 4296 } 4297 4298 fail_dif_bundl_dma_pool: 4299 if (IS_QLA82XX(ha) || ql2xenabledif) { 4300 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4301 ha->fcp_cmnd_dma_pool = NULL; 4302 } 4303 fail_dl_dma_pool: 4304 if (IS_QLA82XX(ha) || ql2xenabledif) { 4305 dma_pool_destroy(ha->dl_dma_pool); 4306 ha->dl_dma_pool = NULL; 4307 } 4308 fail_s_dma_pool: 4309 dma_pool_destroy(ha->s_dma_pool); 4310 ha->s_dma_pool = NULL; 4311 fail_free_nvram: 4312 kfree(ha->nvram); 4313 ha->nvram = NULL; 4314 fail_free_ctx_mempool: 4315 mempool_destroy(ha->ctx_mempool); 4316 ha->ctx_mempool = NULL; 4317 fail_free_srb_mempool: 4318 mempool_destroy(ha->srb_mempool); 4319 ha->srb_mempool = NULL; 4320 fail_free_gid_list: 4321 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4322 ha->gid_list, 4323 ha->gid_list_dma); 4324 ha->gid_list = NULL; 4325 ha->gid_list_dma = 0; 4326 fail_free_tgt_mem: 4327 qlt_mem_free(ha); 4328 fail_free_init_cb: 4329 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4330 ha->init_cb_dma); 4331 ha->init_cb = NULL; 4332 ha->init_cb_dma = 0; 4333 fail: 4334 ql_log(ql_log_fatal, NULL, 0x0030, 4335 "Memory allocation failure.\n"); 4336 return -ENOMEM; 4337 } 4338 4339 int 4340 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4341 { 4342 int rval; 4343 uint16_t size, max_cnt, temp; 4344 struct qla_hw_data *ha = vha->hw; 4345 4346 /* Return if we don't need to alloacate any extended logins */ 4347 if (!ql2xexlogins) 4348 return QLA_SUCCESS; 4349 4350 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4351 return QLA_SUCCESS; 4352 4353 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4354 max_cnt = 0; 4355 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4356 if (rval != QLA_SUCCESS) { 4357 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4358 "Failed to get exlogin status.\n"); 4359 return rval; 4360 } 4361 4362 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4363 temp *= size; 4364 4365 if (temp != ha->exlogin_size) { 4366 qla2x00_free_exlogin_buffer(ha); 4367 ha->exlogin_size = temp; 4368 4369 ql_log(ql_log_info, vha, 0xd024, 4370 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4371 max_cnt, size, temp); 4372 4373 ql_log(ql_log_info, vha, 0xd025, 4374 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4375 4376 /* Get consistent memory for extended logins */ 4377 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4378 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4379 if (!ha->exlogin_buf) { 4380 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4381 "Failed to allocate memory for exlogin_buf_dma.\n"); 4382 return -ENOMEM; 4383 } 4384 } 4385 4386 /* Now configure the dma buffer */ 4387 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4388 if (rval) { 4389 ql_log(ql_log_fatal, vha, 0xd033, 4390 "Setup extended login buffer ****FAILED****.\n"); 4391 qla2x00_free_exlogin_buffer(ha); 4392 } 4393 4394 return rval; 4395 } 4396 4397 /* 4398 * qla2x00_free_exlogin_buffer 4399 * 4400 * Input: 4401 * ha = adapter block pointer 4402 */ 4403 void 4404 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4405 { 4406 if (ha->exlogin_buf) { 4407 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4408 ha->exlogin_buf, ha->exlogin_buf_dma); 4409 ha->exlogin_buf = NULL; 4410 ha->exlogin_size = 0; 4411 } 4412 } 4413 4414 static void 4415 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4416 { 4417 u32 temp; 4418 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4419 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4420 4421 if (max_cnt > vha->hw->max_exchg) 4422 max_cnt = vha->hw->max_exchg; 4423 4424 if (qla_ini_mode_enabled(vha)) { 4425 if (vha->ql2xiniexchg > max_cnt) 4426 vha->ql2xiniexchg = max_cnt; 4427 4428 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4429 *ret_cnt = vha->ql2xiniexchg; 4430 4431 } else if (qla_tgt_mode_enabled(vha)) { 4432 if (vha->ql2xexchoffld > max_cnt) { 4433 vha->ql2xexchoffld = max_cnt; 4434 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4435 } 4436 4437 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4438 *ret_cnt = vha->ql2xexchoffld; 4439 } else if (qla_dual_mode_enabled(vha)) { 4440 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4441 if (temp > max_cnt) { 4442 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4443 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4444 temp = max_cnt; 4445 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4446 } 4447 4448 if (temp > FW_DEF_EXCHANGES_CNT) 4449 *ret_cnt = temp; 4450 } 4451 } 4452 4453 int 4454 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4455 { 4456 int rval; 4457 u16 size, max_cnt; 4458 u32 actual_cnt, totsz; 4459 struct qla_hw_data *ha = vha->hw; 4460 4461 if (!ha->flags.exchoffld_enabled) 4462 return QLA_SUCCESS; 4463 4464 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4465 return QLA_SUCCESS; 4466 4467 max_cnt = 0; 4468 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4469 if (rval != QLA_SUCCESS) { 4470 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4471 "Failed to get exlogin status.\n"); 4472 return rval; 4473 } 4474 4475 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4476 ql_log(ql_log_info, vha, 0xd014, 4477 "Actual exchange offload count: %d.\n", actual_cnt); 4478 4479 totsz = actual_cnt * size; 4480 4481 if (totsz != ha->exchoffld_size) { 4482 qla2x00_free_exchoffld_buffer(ha); 4483 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4484 ha->exchoffld_size = 0; 4485 ha->flags.exchoffld_enabled = 0; 4486 return QLA_SUCCESS; 4487 } 4488 4489 ha->exchoffld_size = totsz; 4490 4491 ql_log(ql_log_info, vha, 0xd016, 4492 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4493 max_cnt, actual_cnt, size, totsz); 4494 4495 ql_log(ql_log_info, vha, 0xd017, 4496 "Exchange Buffers requested size = 0x%x\n", 4497 ha->exchoffld_size); 4498 4499 /* Get consistent memory for extended logins */ 4500 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4501 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4502 if (!ha->exchoffld_buf) { 4503 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4504 "Failed to allocate memory for Exchange Offload.\n"); 4505 4506 if (ha->max_exchg > 4507 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4508 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4509 } else if (ha->max_exchg > 4510 (FW_DEF_EXCHANGES_CNT + 512)) { 4511 ha->max_exchg -= 512; 4512 } else { 4513 ha->flags.exchoffld_enabled = 0; 4514 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4515 "Disabling Exchange offload due to lack of memory\n"); 4516 } 4517 ha->exchoffld_size = 0; 4518 4519 return -ENOMEM; 4520 } 4521 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4522 /* pathological case */ 4523 qla2x00_free_exchoffld_buffer(ha); 4524 ha->exchoffld_size = 0; 4525 ha->flags.exchoffld_enabled = 0; 4526 ql_log(ql_log_info, vha, 0xd016, 4527 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4528 ha->exchoffld_size, actual_cnt, size, totsz); 4529 return 0; 4530 } 4531 4532 /* Now configure the dma buffer */ 4533 rval = qla_set_exchoffld_mem_cfg(vha); 4534 if (rval) { 4535 ql_log(ql_log_fatal, vha, 0xd02e, 4536 "Setup exchange offload buffer ****FAILED****.\n"); 4537 qla2x00_free_exchoffld_buffer(ha); 4538 } else { 4539 /* re-adjust number of target exchange */ 4540 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4541 4542 if (qla_ini_mode_enabled(vha)) 4543 icb->exchange_count = 0; 4544 else 4545 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4546 } 4547 4548 return rval; 4549 } 4550 4551 /* 4552 * qla2x00_free_exchoffld_buffer 4553 * 4554 * Input: 4555 * ha = adapter block pointer 4556 */ 4557 void 4558 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4559 { 4560 if (ha->exchoffld_buf) { 4561 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4562 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4563 ha->exchoffld_buf = NULL; 4564 ha->exchoffld_size = 0; 4565 } 4566 } 4567 4568 /* 4569 * qla2x00_free_fw_dump 4570 * Frees fw dump stuff. 4571 * 4572 * Input: 4573 * ha = adapter block pointer 4574 */ 4575 static void 4576 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4577 { 4578 struct fwdt *fwdt = ha->fwdt; 4579 uint j; 4580 4581 if (ha->fce) 4582 dma_free_coherent(&ha->pdev->dev, 4583 FCE_SIZE, ha->fce, ha->fce_dma); 4584 4585 if (ha->eft) 4586 dma_free_coherent(&ha->pdev->dev, 4587 EFT_SIZE, ha->eft, ha->eft_dma); 4588 4589 if (ha->fw_dump) 4590 vfree(ha->fw_dump); 4591 4592 ha->fce = NULL; 4593 ha->fce_dma = 0; 4594 ha->flags.fce_enabled = 0; 4595 ha->eft = NULL; 4596 ha->eft_dma = 0; 4597 ha->fw_dumped = 0; 4598 ha->fw_dump_cap_flags = 0; 4599 ha->fw_dump_reading = 0; 4600 ha->fw_dump = NULL; 4601 ha->fw_dump_len = 0; 4602 4603 for (j = 0; j < 2; j++, fwdt++) { 4604 if (fwdt->template) 4605 vfree(fwdt->template); 4606 fwdt->template = NULL; 4607 fwdt->length = 0; 4608 } 4609 } 4610 4611 /* 4612 * qla2x00_mem_free 4613 * Frees all adapter allocated memory. 4614 * 4615 * Input: 4616 * ha = adapter block pointer. 4617 */ 4618 static void 4619 qla2x00_mem_free(struct qla_hw_data *ha) 4620 { 4621 qla2x00_free_fw_dump(ha); 4622 4623 if (ha->mctp_dump) 4624 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4625 ha->mctp_dump_dma); 4626 ha->mctp_dump = NULL; 4627 4628 mempool_destroy(ha->srb_mempool); 4629 ha->srb_mempool = NULL; 4630 4631 if (ha->dcbx_tlv) 4632 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4633 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4634 ha->dcbx_tlv = NULL; 4635 4636 if (ha->xgmac_data) 4637 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4638 ha->xgmac_data, ha->xgmac_data_dma); 4639 ha->xgmac_data = NULL; 4640 4641 if (ha->sns_cmd) 4642 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4643 ha->sns_cmd, ha->sns_cmd_dma); 4644 ha->sns_cmd = NULL; 4645 ha->sns_cmd_dma = 0; 4646 4647 if (ha->ct_sns) 4648 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4649 ha->ct_sns, ha->ct_sns_dma); 4650 ha->ct_sns = NULL; 4651 ha->ct_sns_dma = 0; 4652 4653 if (ha->sfp_data) 4654 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4655 ha->sfp_data_dma); 4656 ha->sfp_data = NULL; 4657 4658 if (ha->flt) 4659 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4660 ha->flt, ha->flt_dma); 4661 ha->flt = NULL; 4662 ha->flt_dma = 0; 4663 4664 if (ha->ms_iocb) 4665 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4666 ha->ms_iocb = NULL; 4667 ha->ms_iocb_dma = 0; 4668 4669 if (ha->ex_init_cb) 4670 dma_pool_free(ha->s_dma_pool, 4671 ha->ex_init_cb, ha->ex_init_cb_dma); 4672 ha->ex_init_cb = NULL; 4673 ha->ex_init_cb_dma = 0; 4674 4675 if (ha->async_pd) 4676 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4677 ha->async_pd = NULL; 4678 ha->async_pd_dma = 0; 4679 4680 dma_pool_destroy(ha->s_dma_pool); 4681 ha->s_dma_pool = NULL; 4682 4683 if (ha->gid_list) 4684 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4685 ha->gid_list, ha->gid_list_dma); 4686 ha->gid_list = NULL; 4687 ha->gid_list_dma = 0; 4688 4689 if (IS_QLA82XX(ha)) { 4690 if (!list_empty(&ha->gbl_dsd_list)) { 4691 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4692 4693 /* clean up allocated prev pool */ 4694 list_for_each_entry_safe(dsd_ptr, 4695 tdsd_ptr, &ha->gbl_dsd_list, list) { 4696 dma_pool_free(ha->dl_dma_pool, 4697 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4698 list_del(&dsd_ptr->list); 4699 kfree(dsd_ptr); 4700 } 4701 } 4702 } 4703 4704 dma_pool_destroy(ha->dl_dma_pool); 4705 ha->dl_dma_pool = NULL; 4706 4707 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4708 ha->fcp_cmnd_dma_pool = NULL; 4709 4710 mempool_destroy(ha->ctx_mempool); 4711 ha->ctx_mempool = NULL; 4712 4713 if (ql2xenabledif && ha->dif_bundl_pool) { 4714 struct dsd_dma *dsd, *nxt; 4715 4716 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4717 list) { 4718 list_del(&dsd->list); 4719 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4720 dsd->dsd_list_dma); 4721 ha->dif_bundle_dma_allocs--; 4722 kfree(dsd); 4723 ha->dif_bundle_kallocs--; 4724 ha->pool.unusable.count--; 4725 } 4726 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4727 list_del(&dsd->list); 4728 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4729 dsd->dsd_list_dma); 4730 ha->dif_bundle_dma_allocs--; 4731 kfree(dsd); 4732 ha->dif_bundle_kallocs--; 4733 } 4734 } 4735 4736 dma_pool_destroy(ha->dif_bundl_pool); 4737 ha->dif_bundl_pool = NULL; 4738 4739 qlt_mem_free(ha); 4740 4741 if (ha->init_cb) 4742 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4743 ha->init_cb, ha->init_cb_dma); 4744 ha->init_cb = NULL; 4745 ha->init_cb_dma = 0; 4746 4747 vfree(ha->optrom_buffer); 4748 ha->optrom_buffer = NULL; 4749 kfree(ha->nvram); 4750 ha->nvram = NULL; 4751 kfree(ha->npiv_info); 4752 ha->npiv_info = NULL; 4753 kfree(ha->swl); 4754 ha->swl = NULL; 4755 kfree(ha->loop_id_map); 4756 ha->loop_id_map = NULL; 4757 } 4758 4759 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4760 struct qla_hw_data *ha) 4761 { 4762 struct Scsi_Host *host; 4763 struct scsi_qla_host *vha = NULL; 4764 4765 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4766 if (!host) { 4767 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4768 "Failed to allocate host from the scsi layer, aborting.\n"); 4769 return NULL; 4770 } 4771 4772 /* Clear our data area */ 4773 vha = shost_priv(host); 4774 memset(vha, 0, sizeof(scsi_qla_host_t)); 4775 4776 vha->host = host; 4777 vha->host_no = host->host_no; 4778 vha->hw = ha; 4779 4780 vha->qlini_mode = ql2x_ini_mode; 4781 vha->ql2xexchoffld = ql2xexchoffld; 4782 vha->ql2xiniexchg = ql2xiniexchg; 4783 4784 INIT_LIST_HEAD(&vha->vp_fcports); 4785 INIT_LIST_HEAD(&vha->work_list); 4786 INIT_LIST_HEAD(&vha->list); 4787 INIT_LIST_HEAD(&vha->qla_cmd_list); 4788 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4789 INIT_LIST_HEAD(&vha->logo_list); 4790 INIT_LIST_HEAD(&vha->plogi_ack_list); 4791 INIT_LIST_HEAD(&vha->qp_list); 4792 INIT_LIST_HEAD(&vha->gnl.fcports); 4793 INIT_LIST_HEAD(&vha->gpnid_list); 4794 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4795 4796 spin_lock_init(&vha->work_lock); 4797 spin_lock_init(&vha->cmd_list_lock); 4798 init_waitqueue_head(&vha->fcport_waitQ); 4799 init_waitqueue_head(&vha->vref_waitq); 4800 4801 vha->gnl.size = sizeof(struct get_name_list_extended) * 4802 (ha->max_loop_id + 1); 4803 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4804 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4805 if (!vha->gnl.l) { 4806 ql_log(ql_log_fatal, vha, 0xd04a, 4807 "Alloc failed for name list.\n"); 4808 scsi_host_put(vha->host); 4809 return NULL; 4810 } 4811 4812 /* todo: what about ext login? */ 4813 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4814 vha->scan.l = vmalloc(vha->scan.size); 4815 if (!vha->scan.l) { 4816 ql_log(ql_log_fatal, vha, 0xd04a, 4817 "Alloc failed for scan database.\n"); 4818 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4819 vha->gnl.l, vha->gnl.ldma); 4820 vha->gnl.l = NULL; 4821 scsi_host_put(vha->host); 4822 return NULL; 4823 } 4824 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4825 4826 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4827 ql_dbg(ql_dbg_init, vha, 0x0041, 4828 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4829 vha->host, vha->hw, vha, 4830 dev_name(&(ha->pdev->dev))); 4831 4832 return vha; 4833 } 4834 4835 struct qla_work_evt * 4836 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4837 { 4838 struct qla_work_evt *e; 4839 uint8_t bail; 4840 4841 QLA_VHA_MARK_BUSY(vha, bail); 4842 if (bail) 4843 return NULL; 4844 4845 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4846 if (!e) { 4847 QLA_VHA_MARK_NOT_BUSY(vha); 4848 return NULL; 4849 } 4850 4851 INIT_LIST_HEAD(&e->list); 4852 e->type = type; 4853 e->flags = QLA_EVT_FLAG_FREE; 4854 return e; 4855 } 4856 4857 int 4858 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4859 { 4860 unsigned long flags; 4861 bool q = false; 4862 4863 spin_lock_irqsave(&vha->work_lock, flags); 4864 list_add_tail(&e->list, &vha->work_list); 4865 4866 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4867 q = true; 4868 4869 spin_unlock_irqrestore(&vha->work_lock, flags); 4870 4871 if (q) 4872 queue_work(vha->hw->wq, &vha->iocb_work); 4873 4874 return QLA_SUCCESS; 4875 } 4876 4877 int 4878 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4879 u32 data) 4880 { 4881 struct qla_work_evt *e; 4882 4883 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4884 if (!e) 4885 return QLA_FUNCTION_FAILED; 4886 4887 e->u.aen.code = code; 4888 e->u.aen.data = data; 4889 return qla2x00_post_work(vha, e); 4890 } 4891 4892 int 4893 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4894 { 4895 struct qla_work_evt *e; 4896 4897 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4898 if (!e) 4899 return QLA_FUNCTION_FAILED; 4900 4901 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4902 return qla2x00_post_work(vha, e); 4903 } 4904 4905 #define qla2x00_post_async_work(name, type) \ 4906 int qla2x00_post_async_##name##_work( \ 4907 struct scsi_qla_host *vha, \ 4908 fc_port_t *fcport, uint16_t *data) \ 4909 { \ 4910 struct qla_work_evt *e; \ 4911 \ 4912 e = qla2x00_alloc_work(vha, type); \ 4913 if (!e) \ 4914 return QLA_FUNCTION_FAILED; \ 4915 \ 4916 e->u.logio.fcport = fcport; \ 4917 if (data) { \ 4918 e->u.logio.data[0] = data[0]; \ 4919 e->u.logio.data[1] = data[1]; \ 4920 } \ 4921 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4922 return qla2x00_post_work(vha, e); \ 4923 } 4924 4925 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4926 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4927 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4928 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4929 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4930 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4931 4932 int 4933 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4934 { 4935 struct qla_work_evt *e; 4936 4937 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4938 if (!e) 4939 return QLA_FUNCTION_FAILED; 4940 4941 e->u.uevent.code = code; 4942 return qla2x00_post_work(vha, e); 4943 } 4944 4945 static void 4946 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4947 { 4948 char event_string[40]; 4949 char *envp[] = { event_string, NULL }; 4950 4951 switch (code) { 4952 case QLA_UEVENT_CODE_FW_DUMP: 4953 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4954 vha->host_no); 4955 break; 4956 default: 4957 /* do nothing */ 4958 break; 4959 } 4960 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4961 } 4962 4963 int 4964 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4965 uint32_t *data, int cnt) 4966 { 4967 struct qla_work_evt *e; 4968 4969 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4970 if (!e) 4971 return QLA_FUNCTION_FAILED; 4972 4973 e->u.aenfx.evtcode = evtcode; 4974 e->u.aenfx.count = cnt; 4975 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4976 return qla2x00_post_work(vha, e); 4977 } 4978 4979 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 4980 { 4981 unsigned long flags; 4982 4983 if (IS_SW_RESV_ADDR(fcport->d_id)) 4984 return; 4985 4986 spin_lock_irqsave(&fcport->vha->work_lock, flags); 4987 if (fcport->disc_state == DSC_UPD_FCPORT) { 4988 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4989 return; 4990 } 4991 fcport->jiffies_at_registration = jiffies; 4992 fcport->sec_since_registration = 0; 4993 fcport->next_disc_state = DSC_DELETED; 4994 fcport->disc_state = DSC_UPD_FCPORT; 4995 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4996 4997 queue_work(system_unbound_wq, &fcport->reg_work); 4998 } 4999 5000 static 5001 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5002 { 5003 unsigned long flags; 5004 fc_port_t *fcport = NULL, *tfcp; 5005 struct qlt_plogi_ack_t *pla = 5006 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5007 uint8_t free_fcport = 0; 5008 5009 ql_dbg(ql_dbg_disc, vha, 0xffff, 5010 "%s %d %8phC enter\n", 5011 __func__, __LINE__, e->u.new_sess.port_name); 5012 5013 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5014 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5015 if (fcport) { 5016 fcport->d_id = e->u.new_sess.id; 5017 if (pla) { 5018 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5019 memcpy(fcport->node_name, 5020 pla->iocb.u.isp24.u.plogi.node_name, 5021 WWN_SIZE); 5022 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5023 /* we took an extra ref_count to prevent PLOGI ACK when 5024 * fcport/sess has not been created. 5025 */ 5026 pla->ref_count--; 5027 } 5028 } else { 5029 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5030 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5031 if (fcport) { 5032 fcport->d_id = e->u.new_sess.id; 5033 fcport->flags |= FCF_FABRIC_DEVICE; 5034 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5035 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP) 5036 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 5037 5038 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) { 5039 fcport->fc4_type = FC4_TYPE_OTHER; 5040 fcport->fc4f_nvme = FC4_TYPE_NVME; 5041 } 5042 5043 memcpy(fcport->port_name, e->u.new_sess.port_name, 5044 WWN_SIZE); 5045 5046 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) 5047 fcport->n2n_flag = 1; 5048 5049 } else { 5050 ql_dbg(ql_dbg_disc, vha, 0xffff, 5051 "%s %8phC mem alloc fail.\n", 5052 __func__, e->u.new_sess.port_name); 5053 5054 if (pla) { 5055 list_del(&pla->list); 5056 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5057 } 5058 return; 5059 } 5060 5061 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5062 /* search again to make sure no one else got ahead */ 5063 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5064 e->u.new_sess.port_name, 1); 5065 if (tfcp) { 5066 /* should rarily happen */ 5067 ql_dbg(ql_dbg_disc, vha, 0xffff, 5068 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5069 __func__, tfcp->port_name, tfcp->disc_state, 5070 tfcp->fw_login_state); 5071 5072 free_fcport = 1; 5073 } else { 5074 list_add_tail(&fcport->list, &vha->vp_fcports); 5075 5076 } 5077 if (pla) { 5078 qlt_plogi_ack_link(vha, pla, fcport, 5079 QLT_PLOGI_LINK_SAME_WWN); 5080 pla->ref_count--; 5081 } 5082 } 5083 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5084 5085 if (fcport) { 5086 fcport->id_changed = 1; 5087 fcport->scan_state = QLA_FCPORT_FOUND; 5088 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5089 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5090 5091 if (pla) { 5092 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5093 u16 wd3_lo; 5094 5095 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5096 fcport->local = 0; 5097 fcport->loop_id = 5098 le16_to_cpu( 5099 pla->iocb.u.isp24.nport_handle); 5100 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5101 wd3_lo = 5102 le16_to_cpu( 5103 pla->iocb.u.isp24.u.prli.wd3_lo); 5104 5105 if (wd3_lo & BIT_7) 5106 fcport->conf_compl_supported = 1; 5107 5108 if ((wd3_lo & BIT_4) == 0) 5109 fcport->port_type = FCT_INITIATOR; 5110 else 5111 fcport->port_type = FCT_TARGET; 5112 } 5113 qlt_plogi_ack_unref(vha, pla); 5114 } else { 5115 fc_port_t *dfcp = NULL; 5116 5117 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5118 tfcp = qla2x00_find_fcport_by_nportid(vha, 5119 &e->u.new_sess.id, 1); 5120 if (tfcp && (tfcp != fcport)) { 5121 /* 5122 * We have a conflict fcport with same NportID. 5123 */ 5124 ql_dbg(ql_dbg_disc, vha, 0xffff, 5125 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5126 __func__, tfcp->port_name, tfcp->disc_state, 5127 tfcp->fw_login_state); 5128 5129 switch (tfcp->disc_state) { 5130 case DSC_DELETED: 5131 break; 5132 case DSC_DELETE_PEND: 5133 fcport->login_pause = 1; 5134 tfcp->conflict = fcport; 5135 break; 5136 default: 5137 fcport->login_pause = 1; 5138 tfcp->conflict = fcport; 5139 dfcp = tfcp; 5140 break; 5141 } 5142 } 5143 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5144 if (dfcp) 5145 qlt_schedule_sess_for_deletion(tfcp); 5146 5147 if (N2N_TOPO(vha->hw)) { 5148 fcport->flags &= ~FCF_FABRIC_DEVICE; 5149 fcport->keep_nport_handle = 1; 5150 if (vha->flags.nvme_enabled) { 5151 fcport->fc4f_nvme = 1; 5152 fcport->n2n_flag = 1; 5153 } 5154 fcport->fw_login_state = 0; 5155 /* 5156 * wait link init done before sending login 5157 */ 5158 } else { 5159 qla24xx_fcport_handle_login(vha, fcport); 5160 } 5161 } 5162 } 5163 5164 if (free_fcport) { 5165 qla2x00_free_fcport(fcport); 5166 if (pla) { 5167 list_del(&pla->list); 5168 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5169 } 5170 } 5171 } 5172 5173 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5174 { 5175 struct srb *sp = e->u.iosb.sp; 5176 int rval; 5177 5178 rval = qla2x00_start_sp(sp); 5179 if (rval != QLA_SUCCESS) { 5180 ql_dbg(ql_dbg_disc, vha, 0x2043, 5181 "%s: %s: Re-issue IOCB failed (%d).\n", 5182 __func__, sp->name, rval); 5183 qla24xx_sp_unmap(vha, sp); 5184 } 5185 } 5186 5187 void 5188 qla2x00_do_work(struct scsi_qla_host *vha) 5189 { 5190 struct qla_work_evt *e, *tmp; 5191 unsigned long flags; 5192 LIST_HEAD(work); 5193 int rc; 5194 5195 spin_lock_irqsave(&vha->work_lock, flags); 5196 list_splice_init(&vha->work_list, &work); 5197 spin_unlock_irqrestore(&vha->work_lock, flags); 5198 5199 list_for_each_entry_safe(e, tmp, &work, list) { 5200 rc = QLA_SUCCESS; 5201 switch (e->type) { 5202 case QLA_EVT_AEN: 5203 fc_host_post_event(vha->host, fc_get_event_number(), 5204 e->u.aen.code, e->u.aen.data); 5205 break; 5206 case QLA_EVT_IDC_ACK: 5207 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5208 break; 5209 case QLA_EVT_ASYNC_LOGIN: 5210 qla2x00_async_login(vha, e->u.logio.fcport, 5211 e->u.logio.data); 5212 break; 5213 case QLA_EVT_ASYNC_LOGOUT: 5214 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5215 break; 5216 case QLA_EVT_ASYNC_LOGOUT_DONE: 5217 qla2x00_async_logout_done(vha, e->u.logio.fcport, 5218 e->u.logio.data); 5219 break; 5220 case QLA_EVT_ASYNC_ADISC: 5221 qla2x00_async_adisc(vha, e->u.logio.fcport, 5222 e->u.logio.data); 5223 break; 5224 case QLA_EVT_UEVENT: 5225 qla2x00_uevent_emit(vha, e->u.uevent.code); 5226 break; 5227 case QLA_EVT_AENFX: 5228 qlafx00_process_aen(vha, e); 5229 break; 5230 case QLA_EVT_GPNID: 5231 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5232 break; 5233 case QLA_EVT_UNMAP: 5234 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5235 break; 5236 case QLA_EVT_RELOGIN: 5237 qla2x00_relogin(vha); 5238 break; 5239 case QLA_EVT_NEW_SESS: 5240 qla24xx_create_new_sess(vha, e); 5241 break; 5242 case QLA_EVT_GPDB: 5243 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5244 e->u.fcport.opt); 5245 break; 5246 case QLA_EVT_PRLI: 5247 qla24xx_async_prli(vha, e->u.fcport.fcport); 5248 break; 5249 case QLA_EVT_GPSC: 5250 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5251 break; 5252 case QLA_EVT_GNL: 5253 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5254 break; 5255 case QLA_EVT_NACK: 5256 qla24xx_do_nack_work(vha, e); 5257 break; 5258 case QLA_EVT_ASYNC_PRLO: 5259 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5260 break; 5261 case QLA_EVT_ASYNC_PRLO_DONE: 5262 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5263 e->u.logio.data); 5264 break; 5265 case QLA_EVT_GPNFT: 5266 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5267 e->u.gpnft.sp); 5268 break; 5269 case QLA_EVT_GPNFT_DONE: 5270 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5271 break; 5272 case QLA_EVT_GNNFT_DONE: 5273 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5274 break; 5275 case QLA_EVT_GNNID: 5276 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5277 break; 5278 case QLA_EVT_GFPNID: 5279 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5280 break; 5281 case QLA_EVT_SP_RETRY: 5282 qla_sp_retry(vha, e); 5283 break; 5284 case QLA_EVT_IIDMA: 5285 qla_do_iidma_work(vha, e->u.fcport.fcport); 5286 break; 5287 case QLA_EVT_ELS_PLOGI: 5288 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5289 e->u.fcport.fcport, false); 5290 break; 5291 } 5292 5293 if (rc == EAGAIN) { 5294 /* put 'work' at head of 'vha->work_list' */ 5295 spin_lock_irqsave(&vha->work_lock, flags); 5296 list_splice(&work, &vha->work_list); 5297 spin_unlock_irqrestore(&vha->work_lock, flags); 5298 break; 5299 } 5300 list_del_init(&e->list); 5301 if (e->flags & QLA_EVT_FLAG_FREE) 5302 kfree(e); 5303 5304 /* For each work completed decrement vha ref count */ 5305 QLA_VHA_MARK_NOT_BUSY(vha); 5306 } 5307 } 5308 5309 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5310 { 5311 struct qla_work_evt *e; 5312 5313 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5314 5315 if (!e) { 5316 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5317 return QLA_FUNCTION_FAILED; 5318 } 5319 5320 return qla2x00_post_work(vha, e); 5321 } 5322 5323 /* Relogins all the fcports of a vport 5324 * Context: dpc thread 5325 */ 5326 void qla2x00_relogin(struct scsi_qla_host *vha) 5327 { 5328 fc_port_t *fcport; 5329 int status, relogin_needed = 0; 5330 struct event_arg ea; 5331 5332 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5333 /* 5334 * If the port is not ONLINE then try to login 5335 * to it if we haven't run out of retries. 5336 */ 5337 if (atomic_read(&fcport->state) != FCS_ONLINE && 5338 fcport->login_retry) { 5339 if (fcport->scan_state != QLA_FCPORT_FOUND || 5340 fcport->disc_state == DSC_LOGIN_COMPLETE) 5341 continue; 5342 5343 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5344 fcport->disc_state == DSC_DELETE_PEND) { 5345 relogin_needed = 1; 5346 } else { 5347 if (vha->hw->current_topology != ISP_CFG_NL) { 5348 memset(&ea, 0, sizeof(ea)); 5349 ea.fcport = fcport; 5350 qla24xx_handle_relogin_event(vha, &ea); 5351 } else if (vha->hw->current_topology == 5352 ISP_CFG_NL) { 5353 fcport->login_retry--; 5354 status = 5355 qla2x00_local_device_login(vha, 5356 fcport); 5357 if (status == QLA_SUCCESS) { 5358 fcport->old_loop_id = 5359 fcport->loop_id; 5360 ql_dbg(ql_dbg_disc, vha, 0x2003, 5361 "Port login OK: logged in ID 0x%x.\n", 5362 fcport->loop_id); 5363 qla2x00_update_fcport 5364 (vha, fcport); 5365 } else if (status == 1) { 5366 set_bit(RELOGIN_NEEDED, 5367 &vha->dpc_flags); 5368 /* retry the login again */ 5369 ql_dbg(ql_dbg_disc, vha, 0x2007, 5370 "Retrying %d login again loop_id 0x%x.\n", 5371 fcport->login_retry, 5372 fcport->loop_id); 5373 } else { 5374 fcport->login_retry = 0; 5375 } 5376 5377 if (fcport->login_retry == 0 && 5378 status != QLA_SUCCESS) 5379 qla2x00_clear_loop_id(fcport); 5380 } 5381 } 5382 } 5383 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5384 break; 5385 } 5386 5387 if (relogin_needed) 5388 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5389 5390 ql_dbg(ql_dbg_disc, vha, 0x400e, 5391 "Relogin end.\n"); 5392 } 5393 5394 /* Schedule work on any of the dpc-workqueues */ 5395 void 5396 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5397 { 5398 struct qla_hw_data *ha = base_vha->hw; 5399 5400 switch (work_code) { 5401 case MBA_IDC_AEN: /* 0x8200 */ 5402 if (ha->dpc_lp_wq) 5403 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5404 break; 5405 5406 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5407 if (!ha->flags.nic_core_reset_hdlr_active) { 5408 if (ha->dpc_hp_wq) 5409 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5410 } else 5411 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5412 "NIC Core reset is already active. Skip " 5413 "scheduling it again.\n"); 5414 break; 5415 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5416 if (ha->dpc_hp_wq) 5417 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5418 break; 5419 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5420 if (ha->dpc_hp_wq) 5421 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5422 break; 5423 default: 5424 ql_log(ql_log_warn, base_vha, 0xb05f, 5425 "Unknown work-code=0x%x.\n", work_code); 5426 } 5427 5428 return; 5429 } 5430 5431 /* Work: Perform NIC Core Unrecoverable state handling */ 5432 void 5433 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5434 { 5435 struct qla_hw_data *ha = 5436 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5437 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5438 uint32_t dev_state = 0; 5439 5440 qla83xx_idc_lock(base_vha, 0); 5441 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5442 qla83xx_reset_ownership(base_vha); 5443 if (ha->flags.nic_core_reset_owner) { 5444 ha->flags.nic_core_reset_owner = 0; 5445 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5446 QLA8XXX_DEV_FAILED); 5447 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5448 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5449 } 5450 qla83xx_idc_unlock(base_vha, 0); 5451 } 5452 5453 /* Work: Execute IDC state handler */ 5454 void 5455 qla83xx_idc_state_handler_work(struct work_struct *work) 5456 { 5457 struct qla_hw_data *ha = 5458 container_of(work, struct qla_hw_data, idc_state_handler); 5459 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5460 uint32_t dev_state = 0; 5461 5462 qla83xx_idc_lock(base_vha, 0); 5463 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5464 if (dev_state == QLA8XXX_DEV_FAILED || 5465 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5466 qla83xx_idc_state_handler(base_vha); 5467 qla83xx_idc_unlock(base_vha, 0); 5468 } 5469 5470 static int 5471 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5472 { 5473 int rval = QLA_SUCCESS; 5474 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5475 uint32_t heart_beat_counter1, heart_beat_counter2; 5476 5477 do { 5478 if (time_after(jiffies, heart_beat_wait)) { 5479 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5480 "Nic Core f/w is not alive.\n"); 5481 rval = QLA_FUNCTION_FAILED; 5482 break; 5483 } 5484 5485 qla83xx_idc_lock(base_vha, 0); 5486 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5487 &heart_beat_counter1); 5488 qla83xx_idc_unlock(base_vha, 0); 5489 msleep(100); 5490 qla83xx_idc_lock(base_vha, 0); 5491 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5492 &heart_beat_counter2); 5493 qla83xx_idc_unlock(base_vha, 0); 5494 } while (heart_beat_counter1 == heart_beat_counter2); 5495 5496 return rval; 5497 } 5498 5499 /* Work: Perform NIC Core Reset handling */ 5500 void 5501 qla83xx_nic_core_reset_work(struct work_struct *work) 5502 { 5503 struct qla_hw_data *ha = 5504 container_of(work, struct qla_hw_data, nic_core_reset); 5505 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5506 uint32_t dev_state = 0; 5507 5508 if (IS_QLA2031(ha)) { 5509 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5510 ql_log(ql_log_warn, base_vha, 0xb081, 5511 "Failed to dump mctp\n"); 5512 return; 5513 } 5514 5515 if (!ha->flags.nic_core_reset_hdlr_active) { 5516 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5517 qla83xx_idc_lock(base_vha, 0); 5518 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5519 &dev_state); 5520 qla83xx_idc_unlock(base_vha, 0); 5521 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5522 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5523 "Nic Core f/w is alive.\n"); 5524 return; 5525 } 5526 } 5527 5528 ha->flags.nic_core_reset_hdlr_active = 1; 5529 if (qla83xx_nic_core_reset(base_vha)) { 5530 /* NIC Core reset failed. */ 5531 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5532 "NIC Core reset failed.\n"); 5533 } 5534 ha->flags.nic_core_reset_hdlr_active = 0; 5535 } 5536 } 5537 5538 /* Work: Handle 8200 IDC aens */ 5539 void 5540 qla83xx_service_idc_aen(struct work_struct *work) 5541 { 5542 struct qla_hw_data *ha = 5543 container_of(work, struct qla_hw_data, idc_aen); 5544 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5545 uint32_t dev_state, idc_control; 5546 5547 qla83xx_idc_lock(base_vha, 0); 5548 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5549 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5550 qla83xx_idc_unlock(base_vha, 0); 5551 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5552 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5553 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5554 "Application requested NIC Core Reset.\n"); 5555 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5556 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5557 QLA_SUCCESS) { 5558 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5559 "Other protocol driver requested NIC Core Reset.\n"); 5560 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5561 } 5562 } else if (dev_state == QLA8XXX_DEV_FAILED || 5563 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5564 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5565 } 5566 } 5567 5568 static void 5569 qla83xx_wait_logic(void) 5570 { 5571 int i; 5572 5573 /* Yield CPU */ 5574 if (!in_interrupt()) { 5575 /* 5576 * Wait about 200ms before retrying again. 5577 * This controls the number of retries for single 5578 * lock operation. 5579 */ 5580 msleep(100); 5581 schedule(); 5582 } else { 5583 for (i = 0; i < 20; i++) 5584 cpu_relax(); /* This a nop instr on i386 */ 5585 } 5586 } 5587 5588 static int 5589 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5590 { 5591 int rval; 5592 uint32_t data; 5593 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5594 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5595 struct qla_hw_data *ha = base_vha->hw; 5596 5597 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5598 "Trying force recovery of the IDC lock.\n"); 5599 5600 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5601 if (rval) 5602 return rval; 5603 5604 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5605 return QLA_SUCCESS; 5606 } else { 5607 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5608 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5609 data); 5610 if (rval) 5611 return rval; 5612 5613 msleep(200); 5614 5615 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5616 &data); 5617 if (rval) 5618 return rval; 5619 5620 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5621 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5622 ~(idc_lck_rcvry_stage_mask)); 5623 rval = qla83xx_wr_reg(base_vha, 5624 QLA83XX_IDC_LOCK_RECOVERY, data); 5625 if (rval) 5626 return rval; 5627 5628 /* Forcefully perform IDC UnLock */ 5629 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5630 &data); 5631 if (rval) 5632 return rval; 5633 /* Clear lock-id by setting 0xff */ 5634 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5635 0xff); 5636 if (rval) 5637 return rval; 5638 /* Clear lock-recovery by setting 0x0 */ 5639 rval = qla83xx_wr_reg(base_vha, 5640 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5641 if (rval) 5642 return rval; 5643 } else 5644 return QLA_SUCCESS; 5645 } 5646 5647 return rval; 5648 } 5649 5650 static int 5651 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5652 { 5653 int rval = QLA_SUCCESS; 5654 uint32_t o_drv_lockid, n_drv_lockid; 5655 unsigned long lock_recovery_timeout; 5656 5657 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5658 retry_lockid: 5659 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5660 if (rval) 5661 goto exit; 5662 5663 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5664 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5665 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5666 return QLA_SUCCESS; 5667 else 5668 return QLA_FUNCTION_FAILED; 5669 } 5670 5671 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5672 if (rval) 5673 goto exit; 5674 5675 if (o_drv_lockid == n_drv_lockid) { 5676 qla83xx_wait_logic(); 5677 goto retry_lockid; 5678 } else 5679 return QLA_SUCCESS; 5680 5681 exit: 5682 return rval; 5683 } 5684 5685 void 5686 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5687 { 5688 uint32_t data; 5689 uint32_t lock_owner; 5690 struct qla_hw_data *ha = base_vha->hw; 5691 5692 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5693 retry_lock: 5694 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5695 == QLA_SUCCESS) { 5696 if (data) { 5697 /* Setting lock-id to our function-number */ 5698 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5699 ha->portnum); 5700 } else { 5701 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5702 &lock_owner); 5703 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5704 "Failed to acquire IDC lock, acquired by %d, " 5705 "retrying...\n", lock_owner); 5706 5707 /* Retry/Perform IDC-Lock recovery */ 5708 if (qla83xx_idc_lock_recovery(base_vha) 5709 == QLA_SUCCESS) { 5710 qla83xx_wait_logic(); 5711 goto retry_lock; 5712 } else 5713 ql_log(ql_log_warn, base_vha, 0xb075, 5714 "IDC Lock recovery FAILED.\n"); 5715 } 5716 5717 } 5718 5719 return; 5720 } 5721 5722 void 5723 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5724 { 5725 #if 0 5726 uint16_t options = (requester_id << 15) | BIT_7; 5727 #endif 5728 uint16_t retry; 5729 uint32_t data; 5730 struct qla_hw_data *ha = base_vha->hw; 5731 5732 /* IDC-unlock implementation using driver-unlock/lock-id 5733 * remote registers 5734 */ 5735 retry = 0; 5736 retry_unlock: 5737 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5738 == QLA_SUCCESS) { 5739 if (data == ha->portnum) { 5740 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5741 /* Clearing lock-id by setting 0xff */ 5742 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5743 } else if (retry < 10) { 5744 /* SV: XXX: IDC unlock retrying needed here? */ 5745 5746 /* Retry for IDC-unlock */ 5747 qla83xx_wait_logic(); 5748 retry++; 5749 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5750 "Failed to release IDC lock, retrying=%d\n", retry); 5751 goto retry_unlock; 5752 } 5753 } else if (retry < 10) { 5754 /* Retry for IDC-unlock */ 5755 qla83xx_wait_logic(); 5756 retry++; 5757 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5758 "Failed to read drv-lockid, retrying=%d\n", retry); 5759 goto retry_unlock; 5760 } 5761 5762 return; 5763 5764 #if 0 5765 /* XXX: IDC-unlock implementation using access-control mbx */ 5766 retry = 0; 5767 retry_unlock2: 5768 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5769 if (retry < 10) { 5770 /* Retry for IDC-unlock */ 5771 qla83xx_wait_logic(); 5772 retry++; 5773 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5774 "Failed to release IDC lock, retrying=%d\n", retry); 5775 goto retry_unlock2; 5776 } 5777 } 5778 5779 return; 5780 #endif 5781 } 5782 5783 int 5784 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5785 { 5786 int rval = QLA_SUCCESS; 5787 struct qla_hw_data *ha = vha->hw; 5788 uint32_t drv_presence; 5789 5790 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5791 if (rval == QLA_SUCCESS) { 5792 drv_presence |= (1 << ha->portnum); 5793 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5794 drv_presence); 5795 } 5796 5797 return rval; 5798 } 5799 5800 int 5801 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5802 { 5803 int rval = QLA_SUCCESS; 5804 5805 qla83xx_idc_lock(vha, 0); 5806 rval = __qla83xx_set_drv_presence(vha); 5807 qla83xx_idc_unlock(vha, 0); 5808 5809 return rval; 5810 } 5811 5812 int 5813 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5814 { 5815 int rval = QLA_SUCCESS; 5816 struct qla_hw_data *ha = vha->hw; 5817 uint32_t drv_presence; 5818 5819 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5820 if (rval == QLA_SUCCESS) { 5821 drv_presence &= ~(1 << ha->portnum); 5822 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5823 drv_presence); 5824 } 5825 5826 return rval; 5827 } 5828 5829 int 5830 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5831 { 5832 int rval = QLA_SUCCESS; 5833 5834 qla83xx_idc_lock(vha, 0); 5835 rval = __qla83xx_clear_drv_presence(vha); 5836 qla83xx_idc_unlock(vha, 0); 5837 5838 return rval; 5839 } 5840 5841 static void 5842 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5843 { 5844 struct qla_hw_data *ha = vha->hw; 5845 uint32_t drv_ack, drv_presence; 5846 unsigned long ack_timeout; 5847 5848 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5849 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5850 while (1) { 5851 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5852 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5853 if ((drv_ack & drv_presence) == drv_presence) 5854 break; 5855 5856 if (time_after_eq(jiffies, ack_timeout)) { 5857 ql_log(ql_log_warn, vha, 0xb067, 5858 "RESET ACK TIMEOUT! drv_presence=0x%x " 5859 "drv_ack=0x%x\n", drv_presence, drv_ack); 5860 /* 5861 * The function(s) which did not ack in time are forced 5862 * to withdraw any further participation in the IDC 5863 * reset. 5864 */ 5865 if (drv_ack != drv_presence) 5866 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5867 drv_ack); 5868 break; 5869 } 5870 5871 qla83xx_idc_unlock(vha, 0); 5872 msleep(1000); 5873 qla83xx_idc_lock(vha, 0); 5874 } 5875 5876 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5877 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5878 } 5879 5880 static int 5881 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5882 { 5883 int rval = QLA_SUCCESS; 5884 uint32_t idc_control; 5885 5886 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5887 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5888 5889 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5890 __qla83xx_get_idc_control(vha, &idc_control); 5891 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5892 __qla83xx_set_idc_control(vha, 0); 5893 5894 qla83xx_idc_unlock(vha, 0); 5895 rval = qla83xx_restart_nic_firmware(vha); 5896 qla83xx_idc_lock(vha, 0); 5897 5898 if (rval != QLA_SUCCESS) { 5899 ql_log(ql_log_fatal, vha, 0xb06a, 5900 "Failed to restart NIC f/w.\n"); 5901 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5902 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5903 } else { 5904 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5905 "Success in restarting nic f/w.\n"); 5906 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5907 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5908 } 5909 5910 return rval; 5911 } 5912 5913 /* Assumes idc_lock always held on entry */ 5914 int 5915 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5916 { 5917 struct qla_hw_data *ha = base_vha->hw; 5918 int rval = QLA_SUCCESS; 5919 unsigned long dev_init_timeout; 5920 uint32_t dev_state; 5921 5922 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5923 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5924 5925 while (1) { 5926 5927 if (time_after_eq(jiffies, dev_init_timeout)) { 5928 ql_log(ql_log_warn, base_vha, 0xb06e, 5929 "Initialization TIMEOUT!\n"); 5930 /* Init timeout. Disable further NIC Core 5931 * communication. 5932 */ 5933 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5934 QLA8XXX_DEV_FAILED); 5935 ql_log(ql_log_info, base_vha, 0xb06f, 5936 "HW State: FAILED.\n"); 5937 } 5938 5939 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5940 switch (dev_state) { 5941 case QLA8XXX_DEV_READY: 5942 if (ha->flags.nic_core_reset_owner) 5943 qla83xx_idc_audit(base_vha, 5944 IDC_AUDIT_COMPLETION); 5945 ha->flags.nic_core_reset_owner = 0; 5946 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5947 "Reset_owner reset by 0x%x.\n", 5948 ha->portnum); 5949 goto exit; 5950 case QLA8XXX_DEV_COLD: 5951 if (ha->flags.nic_core_reset_owner) 5952 rval = qla83xx_device_bootstrap(base_vha); 5953 else { 5954 /* Wait for AEN to change device-state */ 5955 qla83xx_idc_unlock(base_vha, 0); 5956 msleep(1000); 5957 qla83xx_idc_lock(base_vha, 0); 5958 } 5959 break; 5960 case QLA8XXX_DEV_INITIALIZING: 5961 /* Wait for AEN to change device-state */ 5962 qla83xx_idc_unlock(base_vha, 0); 5963 msleep(1000); 5964 qla83xx_idc_lock(base_vha, 0); 5965 break; 5966 case QLA8XXX_DEV_NEED_RESET: 5967 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5968 qla83xx_need_reset_handler(base_vha); 5969 else { 5970 /* Wait for AEN to change device-state */ 5971 qla83xx_idc_unlock(base_vha, 0); 5972 msleep(1000); 5973 qla83xx_idc_lock(base_vha, 0); 5974 } 5975 /* reset timeout value after need reset handler */ 5976 dev_init_timeout = jiffies + 5977 (ha->fcoe_dev_init_timeout * HZ); 5978 break; 5979 case QLA8XXX_DEV_NEED_QUIESCENT: 5980 /* XXX: DEBUG for now */ 5981 qla83xx_idc_unlock(base_vha, 0); 5982 msleep(1000); 5983 qla83xx_idc_lock(base_vha, 0); 5984 break; 5985 case QLA8XXX_DEV_QUIESCENT: 5986 /* XXX: DEBUG for now */ 5987 if (ha->flags.quiesce_owner) 5988 goto exit; 5989 5990 qla83xx_idc_unlock(base_vha, 0); 5991 msleep(1000); 5992 qla83xx_idc_lock(base_vha, 0); 5993 dev_init_timeout = jiffies + 5994 (ha->fcoe_dev_init_timeout * HZ); 5995 break; 5996 case QLA8XXX_DEV_FAILED: 5997 if (ha->flags.nic_core_reset_owner) 5998 qla83xx_idc_audit(base_vha, 5999 IDC_AUDIT_COMPLETION); 6000 ha->flags.nic_core_reset_owner = 0; 6001 __qla83xx_clear_drv_presence(base_vha); 6002 qla83xx_idc_unlock(base_vha, 0); 6003 qla8xxx_dev_failed_handler(base_vha); 6004 rval = QLA_FUNCTION_FAILED; 6005 qla83xx_idc_lock(base_vha, 0); 6006 goto exit; 6007 case QLA8XXX_BAD_VALUE: 6008 qla83xx_idc_unlock(base_vha, 0); 6009 msleep(1000); 6010 qla83xx_idc_lock(base_vha, 0); 6011 break; 6012 default: 6013 ql_log(ql_log_warn, base_vha, 0xb071, 6014 "Unknown Device State: %x.\n", dev_state); 6015 qla83xx_idc_unlock(base_vha, 0); 6016 qla8xxx_dev_failed_handler(base_vha); 6017 rval = QLA_FUNCTION_FAILED; 6018 qla83xx_idc_lock(base_vha, 0); 6019 goto exit; 6020 } 6021 } 6022 6023 exit: 6024 return rval; 6025 } 6026 6027 void 6028 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6029 { 6030 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6031 board_disable); 6032 struct pci_dev *pdev = ha->pdev; 6033 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6034 6035 /* 6036 * if UNLOAD flag is already set, then continue unload, 6037 * where it was set first. 6038 */ 6039 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6040 return; 6041 6042 ql_log(ql_log_warn, base_vha, 0x015b, 6043 "Disabling adapter.\n"); 6044 6045 if (!atomic_read(&pdev->enable_cnt)) { 6046 ql_log(ql_log_info, base_vha, 0xfffc, 6047 "PCI device disabled, no action req for PCI error=%lx\n", 6048 base_vha->pci_flags); 6049 return; 6050 } 6051 6052 qla2x00_wait_for_sess_deletion(base_vha); 6053 6054 set_bit(UNLOADING, &base_vha->dpc_flags); 6055 6056 qla2x00_delete_all_vps(ha, base_vha); 6057 6058 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6059 6060 qla2x00_dfs_remove(base_vha); 6061 6062 qla84xx_put_chip(base_vha); 6063 6064 if (base_vha->timer_active) 6065 qla2x00_stop_timer(base_vha); 6066 6067 base_vha->flags.online = 0; 6068 6069 qla2x00_destroy_deferred_work(ha); 6070 6071 /* 6072 * Do not try to stop beacon blink as it will issue a mailbox 6073 * command. 6074 */ 6075 qla2x00_free_sysfs_attr(base_vha, false); 6076 6077 fc_remove_host(base_vha->host); 6078 6079 scsi_remove_host(base_vha->host); 6080 6081 base_vha->flags.init_done = 0; 6082 qla25xx_delete_queues(base_vha); 6083 qla2x00_free_fcports(base_vha); 6084 qla2x00_free_irqs(base_vha); 6085 qla2x00_mem_free(ha); 6086 qla82xx_md_free(base_vha); 6087 qla2x00_free_queues(ha); 6088 6089 qla2x00_unmap_iobases(ha); 6090 6091 pci_release_selected_regions(ha->pdev, ha->bars); 6092 pci_disable_pcie_error_reporting(pdev); 6093 pci_disable_device(pdev); 6094 6095 /* 6096 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6097 */ 6098 } 6099 6100 /************************************************************************** 6101 * qla2x00_do_dpc 6102 * This kernel thread is a task that is schedule by the interrupt handler 6103 * to perform the background processing for interrupts. 6104 * 6105 * Notes: 6106 * This task always run in the context of a kernel thread. It 6107 * is kick-off by the driver's detect code and starts up 6108 * up one per adapter. It immediately goes to sleep and waits for 6109 * some fibre event. When either the interrupt handler or 6110 * the timer routine detects a event it will one of the task 6111 * bits then wake us up. 6112 **************************************************************************/ 6113 static int 6114 qla2x00_do_dpc(void *data) 6115 { 6116 scsi_qla_host_t *base_vha; 6117 struct qla_hw_data *ha; 6118 uint32_t online; 6119 struct qla_qpair *qpair; 6120 6121 ha = (struct qla_hw_data *)data; 6122 base_vha = pci_get_drvdata(ha->pdev); 6123 6124 set_user_nice(current, MIN_NICE); 6125 6126 set_current_state(TASK_INTERRUPTIBLE); 6127 while (!kthread_should_stop()) { 6128 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6129 "DPC handler sleeping.\n"); 6130 6131 schedule(); 6132 6133 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6134 goto end_loop; 6135 6136 if (ha->flags.eeh_busy) { 6137 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6138 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6139 goto end_loop; 6140 } 6141 6142 ha->dpc_active = 1; 6143 6144 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6145 "DPC handler waking up, dpc_flags=0x%lx.\n", 6146 base_vha->dpc_flags); 6147 6148 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6149 break; 6150 6151 if (IS_P3P_TYPE(ha)) { 6152 if (IS_QLA8044(ha)) { 6153 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6154 &base_vha->dpc_flags)) { 6155 qla8044_idc_lock(ha); 6156 qla8044_wr_direct(base_vha, 6157 QLA8044_CRB_DEV_STATE_INDEX, 6158 QLA8XXX_DEV_FAILED); 6159 qla8044_idc_unlock(ha); 6160 ql_log(ql_log_info, base_vha, 0x4004, 6161 "HW State: FAILED.\n"); 6162 qla8044_device_state_handler(base_vha); 6163 continue; 6164 } 6165 6166 } else { 6167 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6168 &base_vha->dpc_flags)) { 6169 qla82xx_idc_lock(ha); 6170 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6171 QLA8XXX_DEV_FAILED); 6172 qla82xx_idc_unlock(ha); 6173 ql_log(ql_log_info, base_vha, 0x0151, 6174 "HW State: FAILED.\n"); 6175 qla82xx_device_state_handler(base_vha); 6176 continue; 6177 } 6178 } 6179 6180 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6181 &base_vha->dpc_flags)) { 6182 6183 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6184 "FCoE context reset scheduled.\n"); 6185 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6186 &base_vha->dpc_flags))) { 6187 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6188 /* FCoE-ctx reset failed. 6189 * Escalate to chip-reset 6190 */ 6191 set_bit(ISP_ABORT_NEEDED, 6192 &base_vha->dpc_flags); 6193 } 6194 clear_bit(ABORT_ISP_ACTIVE, 6195 &base_vha->dpc_flags); 6196 } 6197 6198 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6199 "FCoE context reset end.\n"); 6200 } 6201 } else if (IS_QLAFX00(ha)) { 6202 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6203 &base_vha->dpc_flags)) { 6204 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6205 "Firmware Reset Recovery\n"); 6206 if (qlafx00_reset_initialize(base_vha)) { 6207 /* Failed. Abort isp later. */ 6208 if (!test_bit(UNLOADING, 6209 &base_vha->dpc_flags)) { 6210 set_bit(ISP_UNRECOVERABLE, 6211 &base_vha->dpc_flags); 6212 ql_dbg(ql_dbg_dpc, base_vha, 6213 0x4021, 6214 "Reset Recovery Failed\n"); 6215 } 6216 } 6217 } 6218 6219 if (test_and_clear_bit(FX00_TARGET_SCAN, 6220 &base_vha->dpc_flags)) { 6221 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6222 "ISPFx00 Target Scan scheduled\n"); 6223 if (qlafx00_rescan_isp(base_vha)) { 6224 if (!test_bit(UNLOADING, 6225 &base_vha->dpc_flags)) 6226 set_bit(ISP_UNRECOVERABLE, 6227 &base_vha->dpc_flags); 6228 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6229 "ISPFx00 Target Scan Failed\n"); 6230 } 6231 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6232 "ISPFx00 Target Scan End\n"); 6233 } 6234 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6235 &base_vha->dpc_flags)) { 6236 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6237 "ISPFx00 Host Info resend scheduled\n"); 6238 qlafx00_fx_disc(base_vha, 6239 &base_vha->hw->mr.fcport, 6240 FXDISC_REG_HOST_INFO); 6241 } 6242 } 6243 6244 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6245 &base_vha->dpc_flags) && 6246 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6247 qla24xx_detect_sfp(base_vha); 6248 6249 if (ha->flags.detected_lr_sfp != 6250 ha->flags.using_lr_setting) 6251 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6252 } 6253 6254 if (test_and_clear_bit 6255 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6256 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6257 bool do_reset = true; 6258 6259 switch (base_vha->qlini_mode) { 6260 case QLA2XXX_INI_MODE_ENABLED: 6261 break; 6262 case QLA2XXX_INI_MODE_DISABLED: 6263 if (!qla_tgt_mode_enabled(base_vha) && 6264 !ha->flags.fw_started) 6265 do_reset = false; 6266 break; 6267 case QLA2XXX_INI_MODE_DUAL: 6268 if (!qla_dual_mode_enabled(base_vha) && 6269 !ha->flags.fw_started) 6270 do_reset = false; 6271 break; 6272 default: 6273 break; 6274 } 6275 6276 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6277 &base_vha->dpc_flags))) { 6278 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6279 "ISP abort scheduled.\n"); 6280 if (ha->isp_ops->abort_isp(base_vha)) { 6281 /* failed. retry later */ 6282 set_bit(ISP_ABORT_NEEDED, 6283 &base_vha->dpc_flags); 6284 } 6285 clear_bit(ABORT_ISP_ACTIVE, 6286 &base_vha->dpc_flags); 6287 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6288 "ISP abort end.\n"); 6289 } 6290 } 6291 6292 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6293 &base_vha->dpc_flags)) { 6294 qla2x00_update_fcports(base_vha); 6295 } 6296 6297 if (IS_QLAFX00(ha)) 6298 goto loop_resync_check; 6299 6300 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6301 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6302 "Quiescence mode scheduled.\n"); 6303 if (IS_P3P_TYPE(ha)) { 6304 if (IS_QLA82XX(ha)) 6305 qla82xx_device_state_handler(base_vha); 6306 if (IS_QLA8044(ha)) 6307 qla8044_device_state_handler(base_vha); 6308 clear_bit(ISP_QUIESCE_NEEDED, 6309 &base_vha->dpc_flags); 6310 if (!ha->flags.quiesce_owner) { 6311 qla2x00_perform_loop_resync(base_vha); 6312 if (IS_QLA82XX(ha)) { 6313 qla82xx_idc_lock(ha); 6314 qla82xx_clear_qsnt_ready( 6315 base_vha); 6316 qla82xx_idc_unlock(ha); 6317 } else if (IS_QLA8044(ha)) { 6318 qla8044_idc_lock(ha); 6319 qla8044_clear_qsnt_ready( 6320 base_vha); 6321 qla8044_idc_unlock(ha); 6322 } 6323 } 6324 } else { 6325 clear_bit(ISP_QUIESCE_NEEDED, 6326 &base_vha->dpc_flags); 6327 qla2x00_quiesce_io(base_vha); 6328 } 6329 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6330 "Quiescence mode end.\n"); 6331 } 6332 6333 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6334 &base_vha->dpc_flags) && 6335 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6336 6337 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6338 "Reset marker scheduled.\n"); 6339 qla2x00_rst_aen(base_vha); 6340 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6341 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6342 "Reset marker end.\n"); 6343 } 6344 6345 /* Retry each device up to login retry count */ 6346 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6347 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6348 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6349 6350 if (!base_vha->relogin_jif || 6351 time_after_eq(jiffies, base_vha->relogin_jif)) { 6352 base_vha->relogin_jif = jiffies + HZ; 6353 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6354 6355 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6356 "Relogin scheduled.\n"); 6357 qla24xx_post_relogin_work(base_vha); 6358 } 6359 } 6360 loop_resync_check: 6361 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6362 &base_vha->dpc_flags)) { 6363 6364 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6365 "Loop resync scheduled.\n"); 6366 6367 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6368 &base_vha->dpc_flags))) { 6369 6370 qla2x00_loop_resync(base_vha); 6371 6372 clear_bit(LOOP_RESYNC_ACTIVE, 6373 &base_vha->dpc_flags); 6374 } 6375 6376 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6377 "Loop resync end.\n"); 6378 } 6379 6380 if (IS_QLAFX00(ha)) 6381 goto intr_on_check; 6382 6383 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6384 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6385 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6386 qla2xxx_flash_npiv_conf(base_vha); 6387 } 6388 6389 intr_on_check: 6390 if (!ha->interrupts_on) 6391 ha->isp_ops->enable_intrs(ha); 6392 6393 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6394 &base_vha->dpc_flags)) { 6395 if (ha->beacon_blink_led == 1) 6396 ha->isp_ops->beacon_blink(base_vha); 6397 } 6398 6399 /* qpair online check */ 6400 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6401 &base_vha->dpc_flags)) { 6402 if (ha->flags.eeh_busy || 6403 ha->flags.pci_channel_io_perm_failure) 6404 online = 0; 6405 else 6406 online = 1; 6407 6408 mutex_lock(&ha->mq_lock); 6409 list_for_each_entry(qpair, &base_vha->qp_list, 6410 qp_list_elem) 6411 qpair->online = online; 6412 mutex_unlock(&ha->mq_lock); 6413 } 6414 6415 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6416 &base_vha->dpc_flags)) { 6417 ql_log(ql_log_info, base_vha, 0xffffff, 6418 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6419 ha->nvme_last_rptd_aen); 6420 if (qla27xx_set_zio_threshold(base_vha, 6421 ha->nvme_last_rptd_aen)) { 6422 ql_log(ql_log_info, base_vha, 0xffffff, 6423 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6424 ha->nvme_last_rptd_aen); 6425 } 6426 } 6427 6428 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6429 &base_vha->dpc_flags)) { 6430 ql_log(ql_log_info, base_vha, 0xffffff, 6431 "SET ZIO Activity exchange threshold to %d.\n", 6432 ha->last_zio_threshold); 6433 qla27xx_set_zio_threshold(base_vha, 6434 ha->last_zio_threshold); 6435 } 6436 6437 if (!IS_QLAFX00(ha)) 6438 qla2x00_do_dpc_all_vps(base_vha); 6439 6440 if (test_and_clear_bit(N2N_LINK_RESET, 6441 &base_vha->dpc_flags)) { 6442 qla2x00_lip_reset(base_vha); 6443 } 6444 6445 ha->dpc_active = 0; 6446 end_loop: 6447 set_current_state(TASK_INTERRUPTIBLE); 6448 } /* End of while(1) */ 6449 __set_current_state(TASK_RUNNING); 6450 6451 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6452 "DPC handler exiting.\n"); 6453 6454 /* 6455 * Make sure that nobody tries to wake us up again. 6456 */ 6457 ha->dpc_active = 0; 6458 6459 /* Cleanup any residual CTX SRBs. */ 6460 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6461 6462 return 0; 6463 } 6464 6465 void 6466 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6467 { 6468 struct qla_hw_data *ha = vha->hw; 6469 struct task_struct *t = ha->dpc_thread; 6470 6471 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6472 wake_up_process(t); 6473 } 6474 6475 /* 6476 * qla2x00_rst_aen 6477 * Processes asynchronous reset. 6478 * 6479 * Input: 6480 * ha = adapter block pointer. 6481 */ 6482 static void 6483 qla2x00_rst_aen(scsi_qla_host_t *vha) 6484 { 6485 if (vha->flags.online && !vha->flags.reset_active && 6486 !atomic_read(&vha->loop_down_timer) && 6487 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6488 do { 6489 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6490 6491 /* 6492 * Issue marker command only when we are going to start 6493 * the I/O. 6494 */ 6495 vha->marker_needed = 1; 6496 } while (!atomic_read(&vha->loop_down_timer) && 6497 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6498 } 6499 } 6500 6501 /************************************************************************** 6502 * qla2x00_timer 6503 * 6504 * Description: 6505 * One second timer 6506 * 6507 * Context: Interrupt 6508 ***************************************************************************/ 6509 void 6510 qla2x00_timer(struct timer_list *t) 6511 { 6512 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6513 unsigned long cpu_flags = 0; 6514 int start_dpc = 0; 6515 int index; 6516 srb_t *sp; 6517 uint16_t w; 6518 struct qla_hw_data *ha = vha->hw; 6519 struct req_que *req; 6520 6521 if (ha->flags.eeh_busy) { 6522 ql_dbg(ql_dbg_timer, vha, 0x6000, 6523 "EEH = %d, restarting timer.\n", 6524 ha->flags.eeh_busy); 6525 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6526 return; 6527 } 6528 6529 /* 6530 * Hardware read to raise pending EEH errors during mailbox waits. If 6531 * the read returns -1 then disable the board. 6532 */ 6533 if (!pci_channel_offline(ha->pdev)) { 6534 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6535 qla2x00_check_reg16_for_disconnect(vha, w); 6536 } 6537 6538 /* Make sure qla82xx_watchdog is run only for physical port */ 6539 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6540 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6541 start_dpc++; 6542 if (IS_QLA82XX(ha)) 6543 qla82xx_watchdog(vha); 6544 else if (IS_QLA8044(ha)) 6545 qla8044_watchdog(vha); 6546 } 6547 6548 if (!vha->vp_idx && IS_QLAFX00(ha)) 6549 qlafx00_timer_routine(vha); 6550 6551 /* Loop down handler. */ 6552 if (atomic_read(&vha->loop_down_timer) > 0 && 6553 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6554 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6555 && vha->flags.online) { 6556 6557 if (atomic_read(&vha->loop_down_timer) == 6558 vha->loop_down_abort_time) { 6559 6560 ql_log(ql_log_info, vha, 0x6008, 6561 "Loop down - aborting the queues before time expires.\n"); 6562 6563 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6564 atomic_set(&vha->loop_state, LOOP_DEAD); 6565 6566 /* 6567 * Schedule an ISP abort to return any FCP2-device 6568 * commands. 6569 */ 6570 /* NPIV - scan physical port only */ 6571 if (!vha->vp_idx) { 6572 spin_lock_irqsave(&ha->hardware_lock, 6573 cpu_flags); 6574 req = ha->req_q_map[0]; 6575 for (index = 1; 6576 index < req->num_outstanding_cmds; 6577 index++) { 6578 fc_port_t *sfcp; 6579 6580 sp = req->outstanding_cmds[index]; 6581 if (!sp) 6582 continue; 6583 if (sp->cmd_type != TYPE_SRB) 6584 continue; 6585 if (sp->type != SRB_SCSI_CMD) 6586 continue; 6587 sfcp = sp->fcport; 6588 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6589 continue; 6590 6591 if (IS_QLA82XX(ha)) 6592 set_bit(FCOE_CTX_RESET_NEEDED, 6593 &vha->dpc_flags); 6594 else 6595 set_bit(ISP_ABORT_NEEDED, 6596 &vha->dpc_flags); 6597 break; 6598 } 6599 spin_unlock_irqrestore(&ha->hardware_lock, 6600 cpu_flags); 6601 } 6602 start_dpc++; 6603 } 6604 6605 /* if the loop has been down for 4 minutes, reinit adapter */ 6606 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6607 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6608 ql_log(ql_log_warn, vha, 0x6009, 6609 "Loop down - aborting ISP.\n"); 6610 6611 if (IS_QLA82XX(ha)) 6612 set_bit(FCOE_CTX_RESET_NEEDED, 6613 &vha->dpc_flags); 6614 else 6615 set_bit(ISP_ABORT_NEEDED, 6616 &vha->dpc_flags); 6617 } 6618 } 6619 ql_dbg(ql_dbg_timer, vha, 0x600a, 6620 "Loop down - seconds remaining %d.\n", 6621 atomic_read(&vha->loop_down_timer)); 6622 } 6623 /* Check if beacon LED needs to be blinked for physical host only */ 6624 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6625 /* There is no beacon_blink function for ISP82xx */ 6626 if (!IS_P3P_TYPE(ha)) { 6627 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6628 start_dpc++; 6629 } 6630 } 6631 6632 /* Process any deferred work. */ 6633 if (!list_empty(&vha->work_list)) { 6634 unsigned long flags; 6635 bool q = false; 6636 6637 spin_lock_irqsave(&vha->work_lock, flags); 6638 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6639 q = true; 6640 spin_unlock_irqrestore(&vha->work_lock, flags); 6641 if (q) 6642 queue_work(vha->hw->wq, &vha->iocb_work); 6643 } 6644 6645 /* 6646 * FC-NVME 6647 * see if the active AEN count has changed from what was last reported. 6648 */ 6649 if (!vha->vp_idx && 6650 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) && 6651 ha->zio_mode == QLA_ZIO_MODE_6 && 6652 !ha->flags.host_shutting_down) { 6653 ql_log(ql_log_info, vha, 0x3002, 6654 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6655 ha->nvme_last_rptd_aen); 6656 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6657 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6658 start_dpc++; 6659 } 6660 6661 if (!vha->vp_idx && 6662 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 6663 (ha->zio_mode == QLA_ZIO_MODE_6) && 6664 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 6665 ql_log(ql_log_info, vha, 0x3002, 6666 "Sched: Set ZIO exchange threshold to %d.\n", 6667 ha->last_zio_threshold); 6668 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 6669 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6670 start_dpc++; 6671 } 6672 6673 /* Schedule the DPC routine if needed */ 6674 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6675 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6676 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6677 start_dpc || 6678 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6679 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6680 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6681 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6682 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6683 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6684 ql_dbg(ql_dbg_timer, vha, 0x600b, 6685 "isp_abort_needed=%d loop_resync_needed=%d " 6686 "fcport_update_needed=%d start_dpc=%d " 6687 "reset_marker_needed=%d", 6688 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6689 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6690 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6691 start_dpc, 6692 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6693 ql_dbg(ql_dbg_timer, vha, 0x600c, 6694 "beacon_blink_needed=%d isp_unrecoverable=%d " 6695 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6696 "relogin_needed=%d.\n", 6697 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6698 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6699 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6700 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6701 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6702 qla2xxx_wake_dpc(vha); 6703 } 6704 6705 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6706 } 6707 6708 /* Firmware interface routines. */ 6709 6710 #define FW_ISP21XX 0 6711 #define FW_ISP22XX 1 6712 #define FW_ISP2300 2 6713 #define FW_ISP2322 3 6714 #define FW_ISP24XX 4 6715 #define FW_ISP25XX 5 6716 #define FW_ISP81XX 6 6717 #define FW_ISP82XX 7 6718 #define FW_ISP2031 8 6719 #define FW_ISP8031 9 6720 #define FW_ISP27XX 10 6721 #define FW_ISP28XX 11 6722 6723 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6724 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6725 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6726 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6727 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6728 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6729 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6730 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6731 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6732 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6733 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6734 #define FW_FILE_ISP28XX "ql2800_fw.bin" 6735 6736 6737 static DEFINE_MUTEX(qla_fw_lock); 6738 6739 static struct fw_blob qla_fw_blobs[] = { 6740 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6741 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6742 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6743 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6744 { .name = FW_FILE_ISP24XX, }, 6745 { .name = FW_FILE_ISP25XX, }, 6746 { .name = FW_FILE_ISP81XX, }, 6747 { .name = FW_FILE_ISP82XX, }, 6748 { .name = FW_FILE_ISP2031, }, 6749 { .name = FW_FILE_ISP8031, }, 6750 { .name = FW_FILE_ISP27XX, }, 6751 { .name = FW_FILE_ISP28XX, }, 6752 { .name = NULL, }, 6753 }; 6754 6755 struct fw_blob * 6756 qla2x00_request_firmware(scsi_qla_host_t *vha) 6757 { 6758 struct qla_hw_data *ha = vha->hw; 6759 struct fw_blob *blob; 6760 6761 if (IS_QLA2100(ha)) { 6762 blob = &qla_fw_blobs[FW_ISP21XX]; 6763 } else if (IS_QLA2200(ha)) { 6764 blob = &qla_fw_blobs[FW_ISP22XX]; 6765 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6766 blob = &qla_fw_blobs[FW_ISP2300]; 6767 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6768 blob = &qla_fw_blobs[FW_ISP2322]; 6769 } else if (IS_QLA24XX_TYPE(ha)) { 6770 blob = &qla_fw_blobs[FW_ISP24XX]; 6771 } else if (IS_QLA25XX(ha)) { 6772 blob = &qla_fw_blobs[FW_ISP25XX]; 6773 } else if (IS_QLA81XX(ha)) { 6774 blob = &qla_fw_blobs[FW_ISP81XX]; 6775 } else if (IS_QLA82XX(ha)) { 6776 blob = &qla_fw_blobs[FW_ISP82XX]; 6777 } else if (IS_QLA2031(ha)) { 6778 blob = &qla_fw_blobs[FW_ISP2031]; 6779 } else if (IS_QLA8031(ha)) { 6780 blob = &qla_fw_blobs[FW_ISP8031]; 6781 } else if (IS_QLA27XX(ha)) { 6782 blob = &qla_fw_blobs[FW_ISP27XX]; 6783 } else if (IS_QLA28XX(ha)) { 6784 blob = &qla_fw_blobs[FW_ISP28XX]; 6785 } else { 6786 return NULL; 6787 } 6788 6789 if (!blob->name) 6790 return NULL; 6791 6792 mutex_lock(&qla_fw_lock); 6793 if (blob->fw) 6794 goto out; 6795 6796 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6797 ql_log(ql_log_warn, vha, 0x0063, 6798 "Failed to load firmware image (%s).\n", blob->name); 6799 blob->fw = NULL; 6800 blob = NULL; 6801 } 6802 6803 out: 6804 mutex_unlock(&qla_fw_lock); 6805 return blob; 6806 } 6807 6808 static void 6809 qla2x00_release_firmware(void) 6810 { 6811 struct fw_blob *blob; 6812 6813 mutex_lock(&qla_fw_lock); 6814 for (blob = qla_fw_blobs; blob->name; blob++) 6815 release_firmware(blob->fw); 6816 mutex_unlock(&qla_fw_lock); 6817 } 6818 6819 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 6820 { 6821 struct qla_hw_data *ha = vha->hw; 6822 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6823 struct qla_qpair *qpair = NULL; 6824 struct scsi_qla_host *vp; 6825 fc_port_t *fcport; 6826 int i; 6827 unsigned long flags; 6828 6829 ha->chip_reset++; 6830 6831 ha->base_qpair->chip_reset = ha->chip_reset; 6832 for (i = 0; i < ha->max_qpairs; i++) { 6833 if (ha->queue_pair_map[i]) 6834 ha->queue_pair_map[i]->chip_reset = 6835 ha->base_qpair->chip_reset; 6836 } 6837 6838 /* purge MBox commands */ 6839 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6840 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6841 complete(&ha->mbx_intr_comp); 6842 } 6843 6844 i = 0; 6845 6846 while (atomic_read(&ha->num_pend_mbx_stage3) || 6847 atomic_read(&ha->num_pend_mbx_stage2) || 6848 atomic_read(&ha->num_pend_mbx_stage1)) { 6849 msleep(20); 6850 i++; 6851 if (i > 50) 6852 break; 6853 } 6854 6855 ha->flags.purge_mbox = 0; 6856 6857 mutex_lock(&ha->mq_lock); 6858 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 6859 qpair->online = 0; 6860 mutex_unlock(&ha->mq_lock); 6861 6862 qla2x00_mark_all_devices_lost(vha, 0); 6863 6864 spin_lock_irqsave(&ha->vport_slock, flags); 6865 list_for_each_entry(vp, &ha->vp_list, list) { 6866 atomic_inc(&vp->vref_count); 6867 spin_unlock_irqrestore(&ha->vport_slock, flags); 6868 qla2x00_mark_all_devices_lost(vp, 0); 6869 spin_lock_irqsave(&ha->vport_slock, flags); 6870 atomic_dec(&vp->vref_count); 6871 } 6872 spin_unlock_irqrestore(&ha->vport_slock, flags); 6873 6874 /* Clear all async request states across all VPs. */ 6875 list_for_each_entry(fcport, &vha->vp_fcports, list) 6876 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6877 6878 spin_lock_irqsave(&ha->vport_slock, flags); 6879 list_for_each_entry(vp, &ha->vp_list, list) { 6880 atomic_inc(&vp->vref_count); 6881 spin_unlock_irqrestore(&ha->vport_slock, flags); 6882 list_for_each_entry(fcport, &vp->vp_fcports, list) 6883 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6884 spin_lock_irqsave(&ha->vport_slock, flags); 6885 atomic_dec(&vp->vref_count); 6886 } 6887 spin_unlock_irqrestore(&ha->vport_slock, flags); 6888 } 6889 6890 6891 static pci_ers_result_t 6892 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6893 { 6894 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6895 struct qla_hw_data *ha = vha->hw; 6896 6897 ql_dbg(ql_dbg_aer, vha, 0x9000, 6898 "PCI error detected, state %x.\n", state); 6899 6900 if (!atomic_read(&pdev->enable_cnt)) { 6901 ql_log(ql_log_info, vha, 0xffff, 6902 "PCI device is disabled,state %x\n", state); 6903 return PCI_ERS_RESULT_NEED_RESET; 6904 } 6905 6906 switch (state) { 6907 case pci_channel_io_normal: 6908 ha->flags.eeh_busy = 0; 6909 if (ql2xmqsupport || ql2xnvmeenable) { 6910 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6911 qla2xxx_wake_dpc(vha); 6912 } 6913 return PCI_ERS_RESULT_CAN_RECOVER; 6914 case pci_channel_io_frozen: 6915 ha->flags.eeh_busy = 1; 6916 qla_pci_error_cleanup(vha); 6917 return PCI_ERS_RESULT_NEED_RESET; 6918 case pci_channel_io_perm_failure: 6919 ha->flags.pci_channel_io_perm_failure = 1; 6920 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6921 if (ql2xmqsupport || ql2xnvmeenable) { 6922 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6923 qla2xxx_wake_dpc(vha); 6924 } 6925 return PCI_ERS_RESULT_DISCONNECT; 6926 } 6927 return PCI_ERS_RESULT_NEED_RESET; 6928 } 6929 6930 static pci_ers_result_t 6931 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6932 { 6933 int risc_paused = 0; 6934 uint32_t stat; 6935 unsigned long flags; 6936 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6937 struct qla_hw_data *ha = base_vha->hw; 6938 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6939 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6940 6941 if (IS_QLA82XX(ha)) 6942 return PCI_ERS_RESULT_RECOVERED; 6943 6944 spin_lock_irqsave(&ha->hardware_lock, flags); 6945 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6946 stat = RD_REG_DWORD(®->hccr); 6947 if (stat & HCCR_RISC_PAUSE) 6948 risc_paused = 1; 6949 } else if (IS_QLA23XX(ha)) { 6950 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6951 if (stat & HSR_RISC_PAUSED) 6952 risc_paused = 1; 6953 } else if (IS_FWI2_CAPABLE(ha)) { 6954 stat = RD_REG_DWORD(®24->host_status); 6955 if (stat & HSRX_RISC_PAUSED) 6956 risc_paused = 1; 6957 } 6958 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6959 6960 if (risc_paused) { 6961 ql_log(ql_log_info, base_vha, 0x9003, 6962 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6963 ha->isp_ops->fw_dump(base_vha, 0); 6964 6965 return PCI_ERS_RESULT_NEED_RESET; 6966 } else 6967 return PCI_ERS_RESULT_RECOVERED; 6968 } 6969 6970 static pci_ers_result_t 6971 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6972 { 6973 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6974 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6975 struct qla_hw_data *ha = base_vha->hw; 6976 int rc; 6977 struct qla_qpair *qpair = NULL; 6978 6979 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6980 "Slot Reset.\n"); 6981 6982 /* Workaround: qla2xxx driver which access hardware earlier 6983 * needs error state to be pci_channel_io_online. 6984 * Otherwise mailbox command timesout. 6985 */ 6986 pdev->error_state = pci_channel_io_normal; 6987 6988 pci_restore_state(pdev); 6989 6990 /* pci_restore_state() clears the saved_state flag of the device 6991 * save restored state which resets saved_state flag 6992 */ 6993 pci_save_state(pdev); 6994 6995 if (ha->mem_only) 6996 rc = pci_enable_device_mem(pdev); 6997 else 6998 rc = pci_enable_device(pdev); 6999 7000 if (rc) { 7001 ql_log(ql_log_warn, base_vha, 0x9005, 7002 "Can't re-enable PCI device after reset.\n"); 7003 goto exit_slot_reset; 7004 } 7005 7006 7007 if (ha->isp_ops->pci_config(base_vha)) 7008 goto exit_slot_reset; 7009 7010 mutex_lock(&ha->mq_lock); 7011 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7012 qpair->online = 1; 7013 mutex_unlock(&ha->mq_lock); 7014 7015 base_vha->flags.online = 1; 7016 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7017 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7018 ret = PCI_ERS_RESULT_RECOVERED; 7019 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7020 7021 7022 exit_slot_reset: 7023 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7024 "slot_reset return %x.\n", ret); 7025 7026 return ret; 7027 } 7028 7029 static void 7030 qla2xxx_pci_resume(struct pci_dev *pdev) 7031 { 7032 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7033 struct qla_hw_data *ha = base_vha->hw; 7034 int ret; 7035 7036 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7037 "pci_resume.\n"); 7038 7039 ha->flags.eeh_busy = 0; 7040 7041 ret = qla2x00_wait_for_hba_online(base_vha); 7042 if (ret != QLA_SUCCESS) { 7043 ql_log(ql_log_fatal, base_vha, 0x9002, 7044 "The device failed to resume I/O from slot/link_reset.\n"); 7045 } 7046 } 7047 7048 static void 7049 qla_pci_reset_prepare(struct pci_dev *pdev) 7050 { 7051 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7052 struct qla_hw_data *ha = base_vha->hw; 7053 struct qla_qpair *qpair; 7054 7055 ql_log(ql_log_warn, base_vha, 0xffff, 7056 "%s.\n", __func__); 7057 7058 /* 7059 * PCI FLR/function reset is about to reset the 7060 * slot. Stop the chip to stop all DMA access. 7061 * It is assumed that pci_reset_done will be called 7062 * after FLR to resume Chip operation. 7063 */ 7064 ha->flags.eeh_busy = 1; 7065 mutex_lock(&ha->mq_lock); 7066 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7067 qpair->online = 0; 7068 mutex_unlock(&ha->mq_lock); 7069 7070 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7071 qla2x00_abort_isp_cleanup(base_vha); 7072 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7073 } 7074 7075 static void 7076 qla_pci_reset_done(struct pci_dev *pdev) 7077 { 7078 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7079 struct qla_hw_data *ha = base_vha->hw; 7080 struct qla_qpair *qpair; 7081 7082 ql_log(ql_log_warn, base_vha, 0xffff, 7083 "%s.\n", __func__); 7084 7085 /* 7086 * FLR just completed by PCI layer. Resume adapter 7087 */ 7088 ha->flags.eeh_busy = 0; 7089 mutex_lock(&ha->mq_lock); 7090 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7091 qpair->online = 1; 7092 mutex_unlock(&ha->mq_lock); 7093 7094 base_vha->flags.online = 1; 7095 ha->isp_ops->abort_isp(base_vha); 7096 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7097 } 7098 7099 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7100 { 7101 int rc; 7102 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7103 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7104 7105 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7106 rc = blk_mq_map_queues(qmap); 7107 else 7108 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7109 return rc; 7110 } 7111 7112 struct scsi_host_template qla2xxx_driver_template = { 7113 .module = THIS_MODULE, 7114 .name = QLA2XXX_DRIVER_NAME, 7115 .queuecommand = qla2xxx_queuecommand, 7116 7117 .eh_timed_out = fc_eh_timed_out, 7118 .eh_abort_handler = qla2xxx_eh_abort, 7119 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7120 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7121 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7122 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7123 7124 .slave_configure = qla2xxx_slave_configure, 7125 7126 .slave_alloc = qla2xxx_slave_alloc, 7127 .slave_destroy = qla2xxx_slave_destroy, 7128 .scan_finished = qla2xxx_scan_finished, 7129 .scan_start = qla2xxx_scan_start, 7130 .change_queue_depth = scsi_change_queue_depth, 7131 .map_queues = qla2xxx_map_queues, 7132 .this_id = -1, 7133 .cmd_per_lun = 3, 7134 .sg_tablesize = SG_ALL, 7135 7136 .max_sectors = 0xFFFF, 7137 .shost_attrs = qla2x00_host_attrs, 7138 7139 .supported_mode = MODE_INITIATOR, 7140 .track_queue_depth = 1, 7141 .cmd_size = sizeof(srb_t), 7142 }; 7143 7144 static const struct pci_error_handlers qla2xxx_err_handler = { 7145 .error_detected = qla2xxx_pci_error_detected, 7146 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7147 .slot_reset = qla2xxx_pci_slot_reset, 7148 .resume = qla2xxx_pci_resume, 7149 .reset_prepare = qla_pci_reset_prepare, 7150 .reset_done = qla_pci_reset_done, 7151 }; 7152 7153 static struct pci_device_id qla2xxx_pci_tbl[] = { 7154 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7155 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7156 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7157 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7158 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7160 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7161 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7162 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7163 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7164 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7165 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7166 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7169 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7170 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7171 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7172 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7173 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7179 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7180 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7181 { 0 }, 7182 }; 7183 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7184 7185 static struct pci_driver qla2xxx_pci_driver = { 7186 .name = QLA2XXX_DRIVER_NAME, 7187 .driver = { 7188 .owner = THIS_MODULE, 7189 }, 7190 .id_table = qla2xxx_pci_tbl, 7191 .probe = qla2x00_probe_one, 7192 .remove = qla2x00_remove_one, 7193 .shutdown = qla2x00_shutdown, 7194 .err_handler = &qla2xxx_err_handler, 7195 }; 7196 7197 static const struct file_operations apidev_fops = { 7198 .owner = THIS_MODULE, 7199 .llseek = noop_llseek, 7200 }; 7201 7202 /** 7203 * qla2x00_module_init - Module initialization. 7204 **/ 7205 static int __init 7206 qla2x00_module_init(void) 7207 { 7208 int ret = 0; 7209 7210 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7211 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7212 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7213 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7214 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7215 BUILD_BUG_ON(sizeof(request_t) != 64); 7216 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7217 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7218 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7219 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7220 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7221 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7222 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7223 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7224 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7225 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7226 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7227 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7228 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7229 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7230 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7231 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7232 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7233 7234 /* Allocate cache for SRBs. */ 7235 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7236 SLAB_HWCACHE_ALIGN, NULL); 7237 if (srb_cachep == NULL) { 7238 ql_log(ql_log_fatal, NULL, 0x0001, 7239 "Unable to allocate SRB cache...Failing load!.\n"); 7240 return -ENOMEM; 7241 } 7242 7243 /* Initialize target kmem_cache and mem_pools */ 7244 ret = qlt_init(); 7245 if (ret < 0) { 7246 goto destroy_cache; 7247 } else if (ret > 0) { 7248 /* 7249 * If initiator mode is explictly disabled by qlt_init(), 7250 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7251 * performing scsi_scan_target() during LOOP UP event. 7252 */ 7253 qla2xxx_transport_functions.disable_target_scan = 1; 7254 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7255 } 7256 7257 /* Derive version string. */ 7258 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7259 if (ql2xextended_error_logging) 7260 strcat(qla2x00_version_str, "-debug"); 7261 if (ql2xextended_error_logging == 1) 7262 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7263 7264 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7265 qla_insert_tgt_attrs(); 7266 7267 qla2xxx_transport_template = 7268 fc_attach_transport(&qla2xxx_transport_functions); 7269 if (!qla2xxx_transport_template) { 7270 ql_log(ql_log_fatal, NULL, 0x0002, 7271 "fc_attach_transport failed...Failing load!.\n"); 7272 ret = -ENODEV; 7273 goto qlt_exit; 7274 } 7275 7276 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7277 if (apidev_major < 0) { 7278 ql_log(ql_log_fatal, NULL, 0x0003, 7279 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7280 } 7281 7282 qla2xxx_transport_vport_template = 7283 fc_attach_transport(&qla2xxx_transport_vport_functions); 7284 if (!qla2xxx_transport_vport_template) { 7285 ql_log(ql_log_fatal, NULL, 0x0004, 7286 "fc_attach_transport vport failed...Failing load!.\n"); 7287 ret = -ENODEV; 7288 goto unreg_chrdev; 7289 } 7290 ql_log(ql_log_info, NULL, 0x0005, 7291 "QLogic Fibre Channel HBA Driver: %s.\n", 7292 qla2x00_version_str); 7293 ret = pci_register_driver(&qla2xxx_pci_driver); 7294 if (ret) { 7295 ql_log(ql_log_fatal, NULL, 0x0006, 7296 "pci_register_driver failed...ret=%d Failing load!.\n", 7297 ret); 7298 goto release_vport_transport; 7299 } 7300 return ret; 7301 7302 release_vport_transport: 7303 fc_release_transport(qla2xxx_transport_vport_template); 7304 7305 unreg_chrdev: 7306 if (apidev_major >= 0) 7307 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7308 fc_release_transport(qla2xxx_transport_template); 7309 7310 qlt_exit: 7311 qlt_exit(); 7312 7313 destroy_cache: 7314 kmem_cache_destroy(srb_cachep); 7315 return ret; 7316 } 7317 7318 /** 7319 * qla2x00_module_exit - Module cleanup. 7320 **/ 7321 static void __exit 7322 qla2x00_module_exit(void) 7323 { 7324 pci_unregister_driver(&qla2xxx_pci_driver); 7325 qla2x00_release_firmware(); 7326 kmem_cache_destroy(ctx_cachep); 7327 fc_release_transport(qla2xxx_transport_vport_template); 7328 if (apidev_major >= 0) 7329 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7330 fc_release_transport(qla2xxx_transport_template); 7331 qlt_exit(); 7332 kmem_cache_destroy(srb_cachep); 7333 } 7334 7335 module_init(qla2x00_module_init); 7336 module_exit(qla2x00_module_exit); 7337 7338 MODULE_AUTHOR("QLogic Corporation"); 7339 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7340 MODULE_LICENSE("GPL"); 7341 MODULE_VERSION(QLA2XXX_VERSION); 7342 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7343 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7344 MODULE_FIRMWARE(FW_FILE_ISP2300); 7345 MODULE_FIRMWARE(FW_FILE_ISP2322); 7346 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7347 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7348