1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 struct scsi_host_template qla2xxx_driver_template = { 307 .module = THIS_MODULE, 308 .name = QLA2XXX_DRIVER_NAME, 309 .queuecommand = qla2xxx_queuecommand, 310 311 .eh_timed_out = fc_eh_timed_out, 312 .eh_abort_handler = qla2xxx_eh_abort, 313 .eh_device_reset_handler = qla2xxx_eh_device_reset, 314 .eh_target_reset_handler = qla2xxx_eh_target_reset, 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 316 .eh_host_reset_handler = qla2xxx_eh_host_reset, 317 318 .slave_configure = qla2xxx_slave_configure, 319 320 .slave_alloc = qla2xxx_slave_alloc, 321 .slave_destroy = qla2xxx_slave_destroy, 322 .scan_finished = qla2xxx_scan_finished, 323 .scan_start = qla2xxx_scan_start, 324 .change_queue_depth = scsi_change_queue_depth, 325 .map_queues = qla2xxx_map_queues, 326 .this_id = -1, 327 .cmd_per_lun = 3, 328 .use_clustering = ENABLE_CLUSTERING, 329 .sg_tablesize = SG_ALL, 330 331 .max_sectors = 0xFFFF, 332 .shost_attrs = qla2x00_host_attrs, 333 334 .supported_mode = MODE_INITIATOR, 335 .track_queue_depth = 1, 336 }; 337 338 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 339 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 340 341 /* TODO Convert to inlines 342 * 343 * Timer routines 344 */ 345 346 __inline__ void 347 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 348 { 349 timer_setup(&vha->timer, qla2x00_timer, 0); 350 vha->timer.expires = jiffies + interval * HZ; 351 add_timer(&vha->timer); 352 vha->timer_active = 1; 353 } 354 355 static inline void 356 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 357 { 358 /* Currently used for 82XX only. */ 359 if (vha->device_flags & DFLG_DEV_FAILED) { 360 ql_dbg(ql_dbg_timer, vha, 0x600d, 361 "Device in a failed state, returning.\n"); 362 return; 363 } 364 365 mod_timer(&vha->timer, jiffies + interval * HZ); 366 } 367 368 static __inline__ void 369 qla2x00_stop_timer(scsi_qla_host_t *vha) 370 { 371 del_timer_sync(&vha->timer); 372 vha->timer_active = 0; 373 } 374 375 static int qla2x00_do_dpc(void *data); 376 377 static void qla2x00_rst_aen(scsi_qla_host_t *); 378 379 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 380 struct req_que **, struct rsp_que **); 381 static void qla2x00_free_fw_dump(struct qla_hw_data *); 382 static void qla2x00_mem_free(struct qla_hw_data *); 383 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 384 struct qla_qpair *qpair); 385 386 /* -------------------------------------------------------------------------- */ 387 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 388 struct rsp_que *rsp) 389 { 390 struct qla_hw_data *ha = vha->hw; 391 rsp->qpair = ha->base_qpair; 392 rsp->req = req; 393 ha->base_qpair->req = req; 394 ha->base_qpair->rsp = rsp; 395 ha->base_qpair->vha = vha; 396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 399 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 400 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list); 401 ha->base_qpair->enable_class_2 = ql2xenableclass2; 402 /* init qpair to this cpu. Will adjust at run time. */ 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 404 ha->base_qpair->pdev = ha->pdev; 405 406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 408 } 409 410 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 414 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 415 GFP_KERNEL); 416 if (!ha->req_q_map) { 417 ql_log(ql_log_fatal, vha, 0x003b, 418 "Unable to allocate memory for request queue ptrs.\n"); 419 goto fail_req_map; 420 } 421 422 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 423 GFP_KERNEL); 424 if (!ha->rsp_q_map) { 425 ql_log(ql_log_fatal, vha, 0x003c, 426 "Unable to allocate memory for response queue ptrs.\n"); 427 goto fail_rsp_map; 428 } 429 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 431 if (ha->base_qpair == NULL) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to allocate base queue pair memory.\n"); 434 goto fail_base_qpair; 435 } 436 437 qla_init_base_qpair(vha, req, rsp); 438 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 441 GFP_KERNEL); 442 if (!ha->queue_pair_map) { 443 ql_log(ql_log_fatal, vha, 0x0180, 444 "Unable to allocate memory for queue pair ptrs.\n"); 445 goto fail_qpair_map; 446 } 447 } 448 449 /* 450 * Make sure we record at least the request and response queue zero in 451 * case we need to free them if part of the probe fails. 452 */ 453 ha->rsp_q_map[0] = rsp; 454 ha->req_q_map[0] = req; 455 set_bit(0, ha->rsp_qid_map); 456 set_bit(0, ha->req_qid_map); 457 return 0; 458 459 fail_qpair_map: 460 kfree(ha->base_qpair); 461 ha->base_qpair = NULL; 462 fail_base_qpair: 463 kfree(ha->rsp_q_map); 464 ha->rsp_q_map = NULL; 465 fail_rsp_map: 466 kfree(ha->req_q_map); 467 ha->req_q_map = NULL; 468 fail_req_map: 469 return -ENOMEM; 470 } 471 472 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 473 { 474 if (!ha->req_q_map) 475 return; 476 477 if (IS_QLAFX00(ha)) { 478 if (req && req->ring_fx00) 479 dma_free_coherent(&ha->pdev->dev, 480 (req->length_fx00 + 1) * sizeof(request_t), 481 req->ring_fx00, req->dma_fx00); 482 } else if (req && req->ring) 483 dma_free_coherent(&ha->pdev->dev, 484 (req->length + 1) * sizeof(request_t), 485 req->ring, req->dma); 486 487 if (req) { 488 kfree(req->outstanding_cmds); 489 kfree(req); 490 } 491 } 492 493 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 494 { 495 if (!ha->rsp_q_map) 496 return; 497 498 if (IS_QLAFX00(ha)) { 499 if (rsp && rsp->ring) 500 dma_free_coherent(&ha->pdev->dev, 501 (rsp->length_fx00 + 1) * sizeof(request_t), 502 rsp->ring_fx00, rsp->dma_fx00); 503 } else if (rsp && rsp->ring) { 504 dma_free_coherent(&ha->pdev->dev, 505 (rsp->length + 1) * sizeof(response_t), 506 rsp->ring, rsp->dma); 507 } 508 if (rsp) 509 kfree(rsp); 510 } 511 512 static void qla2x00_free_queues(struct qla_hw_data *ha) 513 { 514 struct req_que *req; 515 struct rsp_que *rsp; 516 int cnt; 517 unsigned long flags; 518 519 if (ha->queue_pair_map) { 520 kfree(ha->queue_pair_map); 521 ha->queue_pair_map = NULL; 522 } 523 if (ha->base_qpair) { 524 kfree(ha->base_qpair); 525 ha->base_qpair = NULL; 526 } 527 528 spin_lock_irqsave(&ha->hardware_lock, flags); 529 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 530 if (!test_bit(cnt, ha->req_qid_map)) 531 continue; 532 533 req = ha->req_q_map[cnt]; 534 clear_bit(cnt, ha->req_qid_map); 535 ha->req_q_map[cnt] = NULL; 536 537 spin_unlock_irqrestore(&ha->hardware_lock, flags); 538 qla2x00_free_req_que(ha, req); 539 spin_lock_irqsave(&ha->hardware_lock, flags); 540 } 541 spin_unlock_irqrestore(&ha->hardware_lock, flags); 542 543 kfree(ha->req_q_map); 544 ha->req_q_map = NULL; 545 546 547 spin_lock_irqsave(&ha->hardware_lock, flags); 548 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 549 if (!test_bit(cnt, ha->rsp_qid_map)) 550 continue; 551 552 rsp = ha->rsp_q_map[cnt]; 553 clear_bit(cnt, ha->rsp_qid_map); 554 ha->rsp_q_map[cnt] = NULL; 555 spin_unlock_irqrestore(&ha->hardware_lock, flags); 556 qla2x00_free_rsp_que(ha, rsp); 557 spin_lock_irqsave(&ha->hardware_lock, flags); 558 } 559 spin_unlock_irqrestore(&ha->hardware_lock, flags); 560 561 kfree(ha->rsp_q_map); 562 ha->rsp_q_map = NULL; 563 } 564 565 static char * 566 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 567 { 568 struct qla_hw_data *ha = vha->hw; 569 static char *pci_bus_modes[] = { 570 "33", "66", "100", "133", 571 }; 572 uint16_t pci_bus; 573 574 strcpy(str, "PCI"); 575 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 576 if (pci_bus) { 577 strcat(str, "-X ("); 578 strcat(str, pci_bus_modes[pci_bus]); 579 } else { 580 pci_bus = (ha->pci_attr & BIT_8) >> 8; 581 strcat(str, " ("); 582 strcat(str, pci_bus_modes[pci_bus]); 583 } 584 strcat(str, " MHz)"); 585 586 return (str); 587 } 588 589 static char * 590 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 591 { 592 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 593 struct qla_hw_data *ha = vha->hw; 594 uint32_t pci_bus; 595 596 if (pci_is_pcie(ha->pdev)) { 597 char lwstr[6]; 598 uint32_t lstat, lspeed, lwidth; 599 600 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 601 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 602 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 603 604 strcpy(str, "PCIe ("); 605 switch (lspeed) { 606 case 1: 607 strcat(str, "2.5GT/s "); 608 break; 609 case 2: 610 strcat(str, "5.0GT/s "); 611 break; 612 case 3: 613 strcat(str, "8.0GT/s "); 614 break; 615 default: 616 strcat(str, "<unknown> "); 617 break; 618 } 619 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 620 strcat(str, lwstr); 621 622 return str; 623 } 624 625 strcpy(str, "PCI"); 626 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 627 if (pci_bus == 0 || pci_bus == 8) { 628 strcat(str, " ("); 629 strcat(str, pci_bus_modes[pci_bus >> 3]); 630 } else { 631 strcat(str, "-X "); 632 if (pci_bus & BIT_2) 633 strcat(str, "Mode 2"); 634 else 635 strcat(str, "Mode 1"); 636 strcat(str, " ("); 637 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 638 } 639 strcat(str, " MHz)"); 640 641 return str; 642 } 643 644 static char * 645 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 646 { 647 char un_str[10]; 648 struct qla_hw_data *ha = vha->hw; 649 650 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 651 ha->fw_minor_version, ha->fw_subminor_version); 652 653 if (ha->fw_attributes & BIT_9) { 654 strcat(str, "FLX"); 655 return (str); 656 } 657 658 switch (ha->fw_attributes & 0xFF) { 659 case 0x7: 660 strcat(str, "EF"); 661 break; 662 case 0x17: 663 strcat(str, "TP"); 664 break; 665 case 0x37: 666 strcat(str, "IP"); 667 break; 668 case 0x77: 669 strcat(str, "VI"); 670 break; 671 default: 672 sprintf(un_str, "(%x)", ha->fw_attributes); 673 strcat(str, un_str); 674 break; 675 } 676 if (ha->fw_attributes & 0x100) 677 strcat(str, "X"); 678 679 return (str); 680 } 681 682 static char * 683 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 684 { 685 struct qla_hw_data *ha = vha->hw; 686 687 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 688 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 689 return str; 690 } 691 692 void 693 qla2x00_sp_free_dma(void *ptr) 694 { 695 srb_t *sp = ptr; 696 struct qla_hw_data *ha = sp->vha->hw; 697 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 698 void *ctx = GET_CMD_CTX_SP(sp); 699 700 if (sp->flags & SRB_DMA_VALID) { 701 scsi_dma_unmap(cmd); 702 sp->flags &= ~SRB_DMA_VALID; 703 } 704 705 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 706 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 707 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 708 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 709 } 710 711 if (!ctx) 712 goto end; 713 714 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 715 /* List assured to be having elements */ 716 qla2x00_clean_dsd_pool(ha, ctx); 717 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 718 } 719 720 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 721 struct crc_context *ctx0 = ctx; 722 723 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 724 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 725 } 726 727 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 728 struct ct6_dsd *ctx1 = ctx; 729 730 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 731 ctx1->fcp_cmnd_dma); 732 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 733 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 734 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 735 mempool_free(ctx1, ha->ctx_mempool); 736 } 737 738 end: 739 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 740 CMD_SP(cmd) = NULL; 741 qla2x00_rel_sp(sp); 742 } 743 } 744 745 void 746 qla2x00_sp_compl(void *ptr, int res) 747 { 748 srb_t *sp = ptr; 749 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 750 751 cmd->result = res; 752 753 if (atomic_read(&sp->ref_count) == 0) { 754 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 755 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 756 sp, GET_CMD_SP(sp)); 757 if (ql2xextended_error_logging & ql_dbg_io) 758 WARN_ON(atomic_read(&sp->ref_count) == 0); 759 return; 760 } 761 if (!atomic_dec_and_test(&sp->ref_count)) 762 return; 763 764 sp->free(sp); 765 cmd->scsi_done(cmd); 766 } 767 768 void 769 qla2xxx_qpair_sp_free_dma(void *ptr) 770 { 771 srb_t *sp = (srb_t *)ptr; 772 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 773 struct qla_hw_data *ha = sp->fcport->vha->hw; 774 void *ctx = GET_CMD_CTX_SP(sp); 775 776 if (sp->flags & SRB_DMA_VALID) { 777 scsi_dma_unmap(cmd); 778 sp->flags &= ~SRB_DMA_VALID; 779 } 780 781 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 782 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 783 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 784 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 785 } 786 787 if (!ctx) 788 goto end; 789 790 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 791 /* List assured to be having elements */ 792 qla2x00_clean_dsd_pool(ha, ctx); 793 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 794 } 795 796 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 797 struct crc_context *ctx0 = ctx; 798 799 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 800 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 801 } 802 803 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 804 struct ct6_dsd *ctx1 = ctx; 805 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 806 ctx1->fcp_cmnd_dma); 807 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 808 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 809 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 810 mempool_free(ctx1, ha->ctx_mempool); 811 } 812 end: 813 CMD_SP(cmd) = NULL; 814 qla2xxx_rel_qpair_sp(sp->qpair, sp); 815 } 816 817 void 818 qla2xxx_qpair_sp_compl(void *ptr, int res) 819 { 820 srb_t *sp = ptr; 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 822 823 cmd->result = res; 824 825 if (atomic_read(&sp->ref_count) == 0) { 826 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 827 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 828 sp, GET_CMD_SP(sp)); 829 if (ql2xextended_error_logging & ql_dbg_io) 830 WARN_ON(atomic_read(&sp->ref_count) == 0); 831 return; 832 } 833 if (!atomic_dec_and_test(&sp->ref_count)) 834 return; 835 836 sp->free(sp); 837 cmd->scsi_done(cmd); 838 } 839 840 /* If we are SP1 here, we need to still take and release the host_lock as SP1 841 * does not have the changes necessary to avoid taking host->host_lock. 842 */ 843 static int 844 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 845 { 846 scsi_qla_host_t *vha = shost_priv(host); 847 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 848 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 849 struct qla_hw_data *ha = vha->hw; 850 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 851 srb_t *sp; 852 int rval; 853 struct qla_qpair *qpair = NULL; 854 uint32_t tag; 855 uint16_t hwq; 856 857 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 858 cmd->result = DID_NO_CONNECT << 16; 859 goto qc24_fail_command; 860 } 861 862 if (ha->mqenable) { 863 if (shost_use_blk_mq(vha->host)) { 864 tag = blk_mq_unique_tag(cmd->request); 865 hwq = blk_mq_unique_tag_to_hwq(tag); 866 qpair = ha->queue_pair_map[hwq]; 867 } else if (vha->vp_idx && vha->qpair) { 868 qpair = vha->qpair; 869 } 870 871 if (qpair) 872 return qla2xxx_mqueuecommand(host, cmd, qpair); 873 } 874 875 if (ha->flags.eeh_busy) { 876 if (ha->flags.pci_channel_io_perm_failure) { 877 ql_dbg(ql_dbg_aer, vha, 0x9010, 878 "PCI Channel IO permanent failure, exiting " 879 "cmd=%p.\n", cmd); 880 cmd->result = DID_NO_CONNECT << 16; 881 } else { 882 ql_dbg(ql_dbg_aer, vha, 0x9011, 883 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 884 cmd->result = DID_REQUEUE << 16; 885 } 886 goto qc24_fail_command; 887 } 888 889 rval = fc_remote_port_chkready(rport); 890 if (rval) { 891 cmd->result = rval; 892 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 893 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 894 cmd, rval); 895 goto qc24_fail_command; 896 } 897 898 if (!vha->flags.difdix_supported && 899 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 900 ql_dbg(ql_dbg_io, vha, 0x3004, 901 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 902 cmd); 903 cmd->result = DID_NO_CONNECT << 16; 904 goto qc24_fail_command; 905 } 906 907 if (!fcport) { 908 cmd->result = DID_NO_CONNECT << 16; 909 goto qc24_fail_command; 910 } 911 912 if (atomic_read(&fcport->state) != FCS_ONLINE) { 913 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 914 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 915 ql_dbg(ql_dbg_io, vha, 0x3005, 916 "Returning DNC, fcport_state=%d loop_state=%d.\n", 917 atomic_read(&fcport->state), 918 atomic_read(&base_vha->loop_state)); 919 cmd->result = DID_NO_CONNECT << 16; 920 goto qc24_fail_command; 921 } 922 goto qc24_target_busy; 923 } 924 925 /* 926 * Return target busy if we've received a non-zero retry_delay_timer 927 * in a FCP_RSP. 928 */ 929 if (fcport->retry_delay_timestamp == 0) { 930 /* retry delay not set */ 931 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 932 fcport->retry_delay_timestamp = 0; 933 else 934 goto qc24_target_busy; 935 936 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 937 if (!sp) 938 goto qc24_host_busy; 939 940 sp->u.scmd.cmd = cmd; 941 sp->type = SRB_SCSI_CMD; 942 atomic_set(&sp->ref_count, 1); 943 CMD_SP(cmd) = (void *)sp; 944 sp->free = qla2x00_sp_free_dma; 945 sp->done = qla2x00_sp_compl; 946 947 rval = ha->isp_ops->start_scsi(sp); 948 if (rval != QLA_SUCCESS) { 949 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 950 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 951 goto qc24_host_busy_free_sp; 952 } 953 954 return 0; 955 956 qc24_host_busy_free_sp: 957 sp->free(sp); 958 959 qc24_host_busy: 960 return SCSI_MLQUEUE_HOST_BUSY; 961 962 qc24_target_busy: 963 return SCSI_MLQUEUE_TARGET_BUSY; 964 965 qc24_fail_command: 966 cmd->scsi_done(cmd); 967 968 return 0; 969 } 970 971 /* For MQ supported I/O */ 972 int 973 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 974 struct qla_qpair *qpair) 975 { 976 scsi_qla_host_t *vha = shost_priv(host); 977 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 978 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 979 struct qla_hw_data *ha = vha->hw; 980 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 981 srb_t *sp; 982 int rval; 983 984 rval = fc_remote_port_chkready(rport); 985 if (rval) { 986 cmd->result = rval; 987 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 988 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 989 cmd, rval); 990 goto qc24_fail_command; 991 } 992 993 if (!fcport) { 994 cmd->result = DID_NO_CONNECT << 16; 995 goto qc24_fail_command; 996 } 997 998 if (atomic_read(&fcport->state) != FCS_ONLINE) { 999 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1000 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1001 ql_dbg(ql_dbg_io, vha, 0x3077, 1002 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1003 atomic_read(&fcport->state), 1004 atomic_read(&base_vha->loop_state)); 1005 cmd->result = DID_NO_CONNECT << 16; 1006 goto qc24_fail_command; 1007 } 1008 goto qc24_target_busy; 1009 } 1010 1011 /* 1012 * Return target busy if we've received a non-zero retry_delay_timer 1013 * in a FCP_RSP. 1014 */ 1015 if (fcport->retry_delay_timestamp == 0) { 1016 /* retry delay not set */ 1017 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1018 fcport->retry_delay_timestamp = 0; 1019 else 1020 goto qc24_target_busy; 1021 1022 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1023 if (!sp) 1024 goto qc24_host_busy; 1025 1026 sp->u.scmd.cmd = cmd; 1027 sp->type = SRB_SCSI_CMD; 1028 atomic_set(&sp->ref_count, 1); 1029 CMD_SP(cmd) = (void *)sp; 1030 sp->free = qla2xxx_qpair_sp_free_dma; 1031 sp->done = qla2xxx_qpair_sp_compl; 1032 sp->qpair = qpair; 1033 1034 rval = ha->isp_ops->start_scsi_mq(sp); 1035 if (rval != QLA_SUCCESS) { 1036 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1037 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1038 if (rval == QLA_INTERFACE_ERROR) 1039 goto qc24_fail_command; 1040 goto qc24_host_busy_free_sp; 1041 } 1042 1043 return 0; 1044 1045 qc24_host_busy_free_sp: 1046 sp->free(sp); 1047 1048 qc24_host_busy: 1049 return SCSI_MLQUEUE_HOST_BUSY; 1050 1051 qc24_target_busy: 1052 return SCSI_MLQUEUE_TARGET_BUSY; 1053 1054 qc24_fail_command: 1055 cmd->scsi_done(cmd); 1056 1057 return 0; 1058 } 1059 1060 /* 1061 * qla2x00_eh_wait_on_command 1062 * Waits for the command to be returned by the Firmware for some 1063 * max time. 1064 * 1065 * Input: 1066 * cmd = Scsi Command to wait on. 1067 * 1068 * Return: 1069 * Not Found : 0 1070 * Found : 1 1071 */ 1072 static int 1073 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1074 { 1075 #define ABORT_POLLING_PERIOD 1000 1076 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1077 unsigned long wait_iter = ABORT_WAIT_ITER; 1078 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1079 struct qla_hw_data *ha = vha->hw; 1080 int ret = QLA_SUCCESS; 1081 1082 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1083 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1084 "Return:eh_wait.\n"); 1085 return ret; 1086 } 1087 1088 while (CMD_SP(cmd) && wait_iter--) { 1089 msleep(ABORT_POLLING_PERIOD); 1090 } 1091 if (CMD_SP(cmd)) 1092 ret = QLA_FUNCTION_FAILED; 1093 1094 return ret; 1095 } 1096 1097 /* 1098 * qla2x00_wait_for_hba_online 1099 * Wait till the HBA is online after going through 1100 * <= MAX_RETRIES_OF_ISP_ABORT or 1101 * finally HBA is disabled ie marked offline 1102 * 1103 * Input: 1104 * ha - pointer to host adapter structure 1105 * 1106 * Note: 1107 * Does context switching-Release SPIN_LOCK 1108 * (if any) before calling this routine. 1109 * 1110 * Return: 1111 * Success (Adapter is online) : 0 1112 * Failed (Adapter is offline/disabled) : 1 1113 */ 1114 int 1115 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1116 { 1117 int return_status; 1118 unsigned long wait_online; 1119 struct qla_hw_data *ha = vha->hw; 1120 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1121 1122 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1123 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1124 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1125 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1126 ha->dpc_active) && time_before(jiffies, wait_online)) { 1127 1128 msleep(1000); 1129 } 1130 if (base_vha->flags.online) 1131 return_status = QLA_SUCCESS; 1132 else 1133 return_status = QLA_FUNCTION_FAILED; 1134 1135 return (return_status); 1136 } 1137 1138 static inline int test_fcport_count(scsi_qla_host_t *vha) 1139 { 1140 struct qla_hw_data *ha = vha->hw; 1141 unsigned long flags; 1142 int res; 1143 1144 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1145 ql_dbg(ql_dbg_init, vha, 0x00ec, 1146 "tgt %p, fcport_count=%d\n", 1147 vha, vha->fcport_count); 1148 res = (vha->fcport_count == 0); 1149 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1150 1151 return res; 1152 } 1153 1154 /* 1155 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1156 * it has dependency on UNLOADING flag to stop device discovery 1157 */ 1158 static void 1159 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1160 { 1161 qla2x00_mark_all_devices_lost(vha, 0); 1162 1163 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1164 } 1165 1166 /* 1167 * qla2x00_wait_for_hba_ready 1168 * Wait till the HBA is ready before doing driver unload 1169 * 1170 * Input: 1171 * ha - pointer to host adapter structure 1172 * 1173 * Note: 1174 * Does context switching-Release SPIN_LOCK 1175 * (if any) before calling this routine. 1176 * 1177 */ 1178 static void 1179 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1180 { 1181 struct qla_hw_data *ha = vha->hw; 1182 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1183 1184 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1185 ha->flags.mbox_busy) || 1186 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1187 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1188 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1189 break; 1190 msleep(1000); 1191 } 1192 } 1193 1194 int 1195 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1196 { 1197 int return_status; 1198 unsigned long wait_reset; 1199 struct qla_hw_data *ha = vha->hw; 1200 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1201 1202 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1203 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1204 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1205 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1206 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1207 1208 msleep(1000); 1209 1210 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1211 ha->flags.chip_reset_done) 1212 break; 1213 } 1214 if (ha->flags.chip_reset_done) 1215 return_status = QLA_SUCCESS; 1216 else 1217 return_status = QLA_FUNCTION_FAILED; 1218 1219 return return_status; 1220 } 1221 1222 static void 1223 sp_get(struct srb *sp) 1224 { 1225 atomic_inc(&sp->ref_count); 1226 } 1227 1228 #define ISP_REG_DISCONNECT 0xffffffffU 1229 /************************************************************************** 1230 * qla2x00_isp_reg_stat 1231 * 1232 * Description: 1233 * Read the host status register of ISP before aborting the command. 1234 * 1235 * Input: 1236 * ha = pointer to host adapter structure. 1237 * 1238 * 1239 * Returns: 1240 * Either true or false. 1241 * 1242 * Note: Return true if there is register disconnect. 1243 **************************************************************************/ 1244 static inline 1245 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1246 { 1247 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1248 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1249 1250 if (IS_P3P_TYPE(ha)) 1251 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1252 else 1253 return ((RD_REG_DWORD(®->host_status)) == 1254 ISP_REG_DISCONNECT); 1255 } 1256 1257 /************************************************************************** 1258 * qla2xxx_eh_abort 1259 * 1260 * Description: 1261 * The abort function will abort the specified command. 1262 * 1263 * Input: 1264 * cmd = Linux SCSI command packet to be aborted. 1265 * 1266 * Returns: 1267 * Either SUCCESS or FAILED. 1268 * 1269 * Note: 1270 * Only return FAILED if command not returned by firmware. 1271 **************************************************************************/ 1272 static int 1273 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1274 { 1275 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1276 srb_t *sp; 1277 int ret; 1278 unsigned int id; 1279 uint64_t lun; 1280 unsigned long flags; 1281 int rval, wait = 0; 1282 struct qla_hw_data *ha = vha->hw; 1283 1284 if (qla2x00_isp_reg_stat(ha)) { 1285 ql_log(ql_log_info, vha, 0x8042, 1286 "PCI/Register disconnect, exiting.\n"); 1287 return FAILED; 1288 } 1289 if (!CMD_SP(cmd)) 1290 return SUCCESS; 1291 1292 ret = fc_block_scsi_eh(cmd); 1293 if (ret != 0) 1294 return ret; 1295 ret = SUCCESS; 1296 1297 id = cmd->device->id; 1298 lun = cmd->device->lun; 1299 1300 spin_lock_irqsave(&ha->hardware_lock, flags); 1301 sp = (srb_t *) CMD_SP(cmd); 1302 if (!sp) { 1303 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1304 return SUCCESS; 1305 } 1306 1307 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1308 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1309 vha->host_no, id, lun, sp, cmd, sp->handle); 1310 1311 /* Get a reference to the sp and drop the lock.*/ 1312 sp_get(sp); 1313 1314 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1315 rval = ha->isp_ops->abort_command(sp); 1316 if (rval) { 1317 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1318 ret = SUCCESS; 1319 else 1320 ret = FAILED; 1321 1322 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1323 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1324 } else { 1325 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1326 "Abort command mbx success cmd=%p.\n", cmd); 1327 wait = 1; 1328 } 1329 1330 spin_lock_irqsave(&ha->hardware_lock, flags); 1331 sp->done(sp, 0); 1332 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1333 1334 /* Did the command return during mailbox execution? */ 1335 if (ret == FAILED && !CMD_SP(cmd)) 1336 ret = SUCCESS; 1337 1338 /* Wait for the command to be returned. */ 1339 if (wait) { 1340 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1341 ql_log(ql_log_warn, vha, 0x8006, 1342 "Abort handler timed out cmd=%p.\n", cmd); 1343 ret = FAILED; 1344 } 1345 } 1346 1347 ql_log(ql_log_info, vha, 0x801c, 1348 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1349 vha->host_no, id, lun, wait, ret); 1350 1351 return ret; 1352 } 1353 1354 int 1355 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1356 uint64_t l, enum nexus_wait_type type) 1357 { 1358 int cnt, match, status; 1359 unsigned long flags; 1360 struct qla_hw_data *ha = vha->hw; 1361 struct req_que *req; 1362 srb_t *sp; 1363 struct scsi_cmnd *cmd; 1364 1365 status = QLA_SUCCESS; 1366 1367 spin_lock_irqsave(&ha->hardware_lock, flags); 1368 req = vha->req; 1369 for (cnt = 1; status == QLA_SUCCESS && 1370 cnt < req->num_outstanding_cmds; cnt++) { 1371 sp = req->outstanding_cmds[cnt]; 1372 if (!sp) 1373 continue; 1374 if (sp->type != SRB_SCSI_CMD) 1375 continue; 1376 if (vha->vp_idx != sp->vha->vp_idx) 1377 continue; 1378 match = 0; 1379 cmd = GET_CMD_SP(sp); 1380 switch (type) { 1381 case WAIT_HOST: 1382 match = 1; 1383 break; 1384 case WAIT_TARGET: 1385 match = cmd->device->id == t; 1386 break; 1387 case WAIT_LUN: 1388 match = (cmd->device->id == t && 1389 cmd->device->lun == l); 1390 break; 1391 } 1392 if (!match) 1393 continue; 1394 1395 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1396 status = qla2x00_eh_wait_on_command(cmd); 1397 spin_lock_irqsave(&ha->hardware_lock, flags); 1398 } 1399 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1400 1401 return status; 1402 } 1403 1404 static char *reset_errors[] = { 1405 "HBA not online", 1406 "HBA not ready", 1407 "Task management failed", 1408 "Waiting for command completions", 1409 }; 1410 1411 static int 1412 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1413 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1414 { 1415 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1416 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1417 int err; 1418 1419 if (!fcport) { 1420 return FAILED; 1421 } 1422 1423 err = fc_block_scsi_eh(cmd); 1424 if (err != 0) 1425 return err; 1426 1427 ql_log(ql_log_info, vha, 0x8009, 1428 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1429 cmd->device->id, cmd->device->lun, cmd); 1430 1431 err = 0; 1432 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1433 ql_log(ql_log_warn, vha, 0x800a, 1434 "Wait for hba online failed for cmd=%p.\n", cmd); 1435 goto eh_reset_failed; 1436 } 1437 err = 2; 1438 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1439 != QLA_SUCCESS) { 1440 ql_log(ql_log_warn, vha, 0x800c, 1441 "do_reset failed for cmd=%p.\n", cmd); 1442 goto eh_reset_failed; 1443 } 1444 err = 3; 1445 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1446 cmd->device->lun, type) != QLA_SUCCESS) { 1447 ql_log(ql_log_warn, vha, 0x800d, 1448 "wait for pending cmds failed for cmd=%p.\n", cmd); 1449 goto eh_reset_failed; 1450 } 1451 1452 ql_log(ql_log_info, vha, 0x800e, 1453 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1454 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1455 1456 return SUCCESS; 1457 1458 eh_reset_failed: 1459 ql_log(ql_log_info, vha, 0x800f, 1460 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1461 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1462 cmd); 1463 return FAILED; 1464 } 1465 1466 static int 1467 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1468 { 1469 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1470 struct qla_hw_data *ha = vha->hw; 1471 1472 if (qla2x00_isp_reg_stat(ha)) { 1473 ql_log(ql_log_info, vha, 0x803e, 1474 "PCI/Register disconnect, exiting.\n"); 1475 return FAILED; 1476 } 1477 1478 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1479 ha->isp_ops->lun_reset); 1480 } 1481 1482 static int 1483 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1484 { 1485 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1486 struct qla_hw_data *ha = vha->hw; 1487 1488 if (qla2x00_isp_reg_stat(ha)) { 1489 ql_log(ql_log_info, vha, 0x803f, 1490 "PCI/Register disconnect, exiting.\n"); 1491 return FAILED; 1492 } 1493 1494 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1495 ha->isp_ops->target_reset); 1496 } 1497 1498 /************************************************************************** 1499 * qla2xxx_eh_bus_reset 1500 * 1501 * Description: 1502 * The bus reset function will reset the bus and abort any executing 1503 * commands. 1504 * 1505 * Input: 1506 * cmd = Linux SCSI command packet of the command that cause the 1507 * bus reset. 1508 * 1509 * Returns: 1510 * SUCCESS/FAILURE (defined as macro in scsi.h). 1511 * 1512 **************************************************************************/ 1513 static int 1514 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1515 { 1516 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1517 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1518 int ret = FAILED; 1519 unsigned int id; 1520 uint64_t lun; 1521 struct qla_hw_data *ha = vha->hw; 1522 1523 if (qla2x00_isp_reg_stat(ha)) { 1524 ql_log(ql_log_info, vha, 0x8040, 1525 "PCI/Register disconnect, exiting.\n"); 1526 return FAILED; 1527 } 1528 1529 id = cmd->device->id; 1530 lun = cmd->device->lun; 1531 1532 if (!fcport) { 1533 return ret; 1534 } 1535 1536 ret = fc_block_scsi_eh(cmd); 1537 if (ret != 0) 1538 return ret; 1539 ret = FAILED; 1540 1541 ql_log(ql_log_info, vha, 0x8012, 1542 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1543 1544 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1545 ql_log(ql_log_fatal, vha, 0x8013, 1546 "Wait for hba online failed board disabled.\n"); 1547 goto eh_bus_reset_done; 1548 } 1549 1550 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1551 ret = SUCCESS; 1552 1553 if (ret == FAILED) 1554 goto eh_bus_reset_done; 1555 1556 /* Flush outstanding commands. */ 1557 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1558 QLA_SUCCESS) { 1559 ql_log(ql_log_warn, vha, 0x8014, 1560 "Wait for pending commands failed.\n"); 1561 ret = FAILED; 1562 } 1563 1564 eh_bus_reset_done: 1565 ql_log(ql_log_warn, vha, 0x802b, 1566 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1567 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1568 1569 return ret; 1570 } 1571 1572 /************************************************************************** 1573 * qla2xxx_eh_host_reset 1574 * 1575 * Description: 1576 * The reset function will reset the Adapter. 1577 * 1578 * Input: 1579 * cmd = Linux SCSI command packet of the command that cause the 1580 * adapter reset. 1581 * 1582 * Returns: 1583 * Either SUCCESS or FAILED. 1584 * 1585 * Note: 1586 **************************************************************************/ 1587 static int 1588 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1589 { 1590 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1591 struct qla_hw_data *ha = vha->hw; 1592 int ret = FAILED; 1593 unsigned int id; 1594 uint64_t lun; 1595 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1596 1597 if (qla2x00_isp_reg_stat(ha)) { 1598 ql_log(ql_log_info, vha, 0x8041, 1599 "PCI/Register disconnect, exiting.\n"); 1600 schedule_work(&ha->board_disable); 1601 return SUCCESS; 1602 } 1603 1604 id = cmd->device->id; 1605 lun = cmd->device->lun; 1606 1607 ql_log(ql_log_info, vha, 0x8018, 1608 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1609 1610 /* 1611 * No point in issuing another reset if one is active. Also do not 1612 * attempt a reset if we are updating flash. 1613 */ 1614 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1615 goto eh_host_reset_lock; 1616 1617 if (vha != base_vha) { 1618 if (qla2x00_vp_abort_isp(vha)) 1619 goto eh_host_reset_lock; 1620 } else { 1621 if (IS_P3P_TYPE(vha->hw)) { 1622 if (!qla82xx_fcoe_ctx_reset(vha)) { 1623 /* Ctx reset success */ 1624 ret = SUCCESS; 1625 goto eh_host_reset_lock; 1626 } 1627 /* fall thru if ctx reset failed */ 1628 } 1629 if (ha->wq) 1630 flush_workqueue(ha->wq); 1631 1632 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1633 if (ha->isp_ops->abort_isp(base_vha)) { 1634 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1635 /* failed. schedule dpc to try */ 1636 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1637 1638 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1639 ql_log(ql_log_warn, vha, 0x802a, 1640 "wait for hba online failed.\n"); 1641 goto eh_host_reset_lock; 1642 } 1643 } 1644 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1645 } 1646 1647 /* Waiting for command to be returned to OS.*/ 1648 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1649 QLA_SUCCESS) 1650 ret = SUCCESS; 1651 1652 eh_host_reset_lock: 1653 ql_log(ql_log_info, vha, 0x8017, 1654 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1655 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1656 1657 return ret; 1658 } 1659 1660 /* 1661 * qla2x00_loop_reset 1662 * Issue loop reset. 1663 * 1664 * Input: 1665 * ha = adapter block pointer. 1666 * 1667 * Returns: 1668 * 0 = success 1669 */ 1670 int 1671 qla2x00_loop_reset(scsi_qla_host_t *vha) 1672 { 1673 int ret; 1674 struct fc_port *fcport; 1675 struct qla_hw_data *ha = vha->hw; 1676 1677 if (IS_QLAFX00(ha)) { 1678 return qlafx00_loop_reset(vha); 1679 } 1680 1681 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1682 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1683 if (fcport->port_type != FCT_TARGET) 1684 continue; 1685 1686 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1687 if (ret != QLA_SUCCESS) { 1688 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1689 "Bus Reset failed: Reset=%d " 1690 "d_id=%x.\n", ret, fcport->d_id.b24); 1691 } 1692 } 1693 } 1694 1695 1696 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1697 atomic_set(&vha->loop_state, LOOP_DOWN); 1698 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1699 qla2x00_mark_all_devices_lost(vha, 0); 1700 ret = qla2x00_full_login_lip(vha); 1701 if (ret != QLA_SUCCESS) { 1702 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1703 "full_login_lip=%d.\n", ret); 1704 } 1705 } 1706 1707 if (ha->flags.enable_lip_reset) { 1708 ret = qla2x00_lip_reset(vha); 1709 if (ret != QLA_SUCCESS) 1710 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1711 "lip_reset failed (%d).\n", ret); 1712 } 1713 1714 /* Issue marker command only when we are going to start the I/O */ 1715 vha->marker_needed = 1; 1716 1717 return QLA_SUCCESS; 1718 } 1719 1720 static void 1721 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1722 { 1723 int cnt, status; 1724 unsigned long flags; 1725 srb_t *sp; 1726 scsi_qla_host_t *vha = qp->vha; 1727 struct qla_hw_data *ha = vha->hw; 1728 struct req_que *req; 1729 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1730 struct qla_tgt_cmd *cmd; 1731 uint8_t trace = 0; 1732 1733 if (!ha->req_q_map) 1734 return; 1735 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1736 req = qp->req; 1737 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1738 sp = req->outstanding_cmds[cnt]; 1739 if (sp) { 1740 req->outstanding_cmds[cnt] = NULL; 1741 if (sp->cmd_type == TYPE_SRB) { 1742 if (sp->type == SRB_NVME_CMD || 1743 sp->type == SRB_NVME_LS) { 1744 sp_get(sp); 1745 spin_unlock_irqrestore(qp->qp_lock_ptr, 1746 flags); 1747 qla_nvme_abort(ha, sp); 1748 spin_lock_irqsave(qp->qp_lock_ptr, 1749 flags); 1750 } else if (GET_CMD_SP(sp) && 1751 !ha->flags.eeh_busy && 1752 (!test_bit(ABORT_ISP_ACTIVE, 1753 &vha->dpc_flags)) && 1754 (sp->type == SRB_SCSI_CMD)) { 1755 /* 1756 * Don't abort commands in 1757 * adapter during EEH 1758 * recovery as it's not 1759 * accessible/responding. 1760 * 1761 * Get a reference to the sp 1762 * and drop the lock. The 1763 * reference ensures this 1764 * sp->done() call and not the 1765 * call in qla2xxx_eh_abort() 1766 * ends the SCSI command (with 1767 * result 'res'). 1768 */ 1769 sp_get(sp); 1770 spin_unlock_irqrestore(qp->qp_lock_ptr, 1771 flags); 1772 status = qla2xxx_eh_abort( 1773 GET_CMD_SP(sp)); 1774 spin_lock_irqsave(qp->qp_lock_ptr, 1775 flags); 1776 /* 1777 * Get rid of extra reference 1778 * if immediate exit from 1779 * ql2xxx_eh_abort 1780 */ 1781 if (status == FAILED && 1782 (qla2x00_isp_reg_stat(ha))) 1783 atomic_dec( 1784 &sp->ref_count); 1785 } 1786 sp->done(sp, res); 1787 } else { 1788 if (!vha->hw->tgt.tgt_ops || !tgt || 1789 qla_ini_mode_enabled(vha)) { 1790 if (!trace) 1791 ql_dbg(ql_dbg_tgt_mgt, 1792 vha, 0xf003, 1793 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1794 vha->dpc_flags); 1795 continue; 1796 } 1797 cmd = (struct qla_tgt_cmd *)sp; 1798 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1799 } 1800 } 1801 } 1802 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1803 } 1804 1805 void 1806 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1807 { 1808 int que; 1809 struct qla_hw_data *ha = vha->hw; 1810 1811 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1812 1813 for (que = 0; que < ha->max_qpairs; que++) { 1814 if (!ha->queue_pair_map[que]) 1815 continue; 1816 1817 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1818 } 1819 } 1820 1821 static int 1822 qla2xxx_slave_alloc(struct scsi_device *sdev) 1823 { 1824 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1825 1826 if (!rport || fc_remote_port_chkready(rport)) 1827 return -ENXIO; 1828 1829 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1830 1831 return 0; 1832 } 1833 1834 static int 1835 qla2xxx_slave_configure(struct scsi_device *sdev) 1836 { 1837 scsi_qla_host_t *vha = shost_priv(sdev->host); 1838 struct req_que *req = vha->req; 1839 1840 if (IS_T10_PI_CAPABLE(vha->hw)) 1841 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1842 1843 scsi_change_queue_depth(sdev, req->max_q_depth); 1844 return 0; 1845 } 1846 1847 static void 1848 qla2xxx_slave_destroy(struct scsi_device *sdev) 1849 { 1850 sdev->hostdata = NULL; 1851 } 1852 1853 /** 1854 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1855 * @ha: HA context 1856 * 1857 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1858 * supported addressing method. 1859 */ 1860 static void 1861 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1862 { 1863 /* Assume a 32bit DMA mask. */ 1864 ha->flags.enable_64bit_addressing = 0; 1865 1866 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1867 /* Any upper-dword bits set? */ 1868 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1869 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1870 /* Ok, a 64bit DMA mask is applicable. */ 1871 ha->flags.enable_64bit_addressing = 1; 1872 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1873 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1874 return; 1875 } 1876 } 1877 1878 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1879 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1880 } 1881 1882 static void 1883 qla2x00_enable_intrs(struct qla_hw_data *ha) 1884 { 1885 unsigned long flags = 0; 1886 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1887 1888 spin_lock_irqsave(&ha->hardware_lock, flags); 1889 ha->interrupts_on = 1; 1890 /* enable risc and host interrupts */ 1891 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1892 RD_REG_WORD(®->ictrl); 1893 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1894 1895 } 1896 1897 static void 1898 qla2x00_disable_intrs(struct qla_hw_data *ha) 1899 { 1900 unsigned long flags = 0; 1901 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1902 1903 spin_lock_irqsave(&ha->hardware_lock, flags); 1904 ha->interrupts_on = 0; 1905 /* disable risc and host interrupts */ 1906 WRT_REG_WORD(®->ictrl, 0); 1907 RD_REG_WORD(®->ictrl); 1908 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1909 } 1910 1911 static void 1912 qla24xx_enable_intrs(struct qla_hw_data *ha) 1913 { 1914 unsigned long flags = 0; 1915 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1916 1917 spin_lock_irqsave(&ha->hardware_lock, flags); 1918 ha->interrupts_on = 1; 1919 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1920 RD_REG_DWORD(®->ictrl); 1921 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1922 } 1923 1924 static void 1925 qla24xx_disable_intrs(struct qla_hw_data *ha) 1926 { 1927 unsigned long flags = 0; 1928 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1929 1930 if (IS_NOPOLLING_TYPE(ha)) 1931 return; 1932 spin_lock_irqsave(&ha->hardware_lock, flags); 1933 ha->interrupts_on = 0; 1934 WRT_REG_DWORD(®->ictrl, 0); 1935 RD_REG_DWORD(®->ictrl); 1936 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1937 } 1938 1939 static int 1940 qla2x00_iospace_config(struct qla_hw_data *ha) 1941 { 1942 resource_size_t pio; 1943 uint16_t msix; 1944 1945 if (pci_request_selected_regions(ha->pdev, ha->bars, 1946 QLA2XXX_DRIVER_NAME)) { 1947 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1948 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1949 pci_name(ha->pdev)); 1950 goto iospace_error_exit; 1951 } 1952 if (!(ha->bars & 1)) 1953 goto skip_pio; 1954 1955 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1956 pio = pci_resource_start(ha->pdev, 0); 1957 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1958 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1959 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1960 "Invalid pci I/O region size (%s).\n", 1961 pci_name(ha->pdev)); 1962 pio = 0; 1963 } 1964 } else { 1965 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1966 "Region #0 no a PIO resource (%s).\n", 1967 pci_name(ha->pdev)); 1968 pio = 0; 1969 } 1970 ha->pio_address = pio; 1971 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1972 "PIO address=%llu.\n", 1973 (unsigned long long)ha->pio_address); 1974 1975 skip_pio: 1976 /* Use MMIO operations for all accesses. */ 1977 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1978 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1979 "Region #1 not an MMIO resource (%s), aborting.\n", 1980 pci_name(ha->pdev)); 1981 goto iospace_error_exit; 1982 } 1983 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1985 "Invalid PCI mem region size (%s), aborting.\n", 1986 pci_name(ha->pdev)); 1987 goto iospace_error_exit; 1988 } 1989 1990 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1991 if (!ha->iobase) { 1992 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1993 "Cannot remap MMIO (%s), aborting.\n", 1994 pci_name(ha->pdev)); 1995 goto iospace_error_exit; 1996 } 1997 1998 /* Determine queue resources */ 1999 ha->max_req_queues = ha->max_rsp_queues = 1; 2000 ha->msix_count = QLA_BASE_VECTORS; 2001 if (!ql2xmqsupport || !ql2xnvmeenable || 2002 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2003 goto mqiobase_exit; 2004 2005 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2006 pci_resource_len(ha->pdev, 3)); 2007 if (ha->mqiobase) { 2008 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2009 "MQIO Base=%p.\n", ha->mqiobase); 2010 /* Read MSIX vector size of the board */ 2011 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2012 ha->msix_count = msix + 1; 2013 /* Max queues are bounded by available msix vectors */ 2014 /* MB interrupt uses 1 vector */ 2015 ha->max_req_queues = ha->msix_count - 1; 2016 ha->max_rsp_queues = ha->max_req_queues; 2017 /* Queue pairs is the max value minus the base queue pair */ 2018 ha->max_qpairs = ha->max_rsp_queues - 1; 2019 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2020 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2021 2022 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2023 "MSI-X vector count: %d.\n", ha->msix_count); 2024 } else 2025 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2026 "BAR 3 not enabled.\n"); 2027 2028 mqiobase_exit: 2029 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2030 "MSIX Count: %d.\n", ha->msix_count); 2031 return (0); 2032 2033 iospace_error_exit: 2034 return (-ENOMEM); 2035 } 2036 2037 2038 static int 2039 qla83xx_iospace_config(struct qla_hw_data *ha) 2040 { 2041 uint16_t msix; 2042 2043 if (pci_request_selected_regions(ha->pdev, ha->bars, 2044 QLA2XXX_DRIVER_NAME)) { 2045 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2046 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2047 pci_name(ha->pdev)); 2048 2049 goto iospace_error_exit; 2050 } 2051 2052 /* Use MMIO operations for all accesses. */ 2053 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2054 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2055 "Invalid pci I/O region size (%s).\n", 2056 pci_name(ha->pdev)); 2057 goto iospace_error_exit; 2058 } 2059 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2060 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2061 "Invalid PCI mem region size (%s), aborting\n", 2062 pci_name(ha->pdev)); 2063 goto iospace_error_exit; 2064 } 2065 2066 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2067 if (!ha->iobase) { 2068 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2069 "Cannot remap MMIO (%s), aborting.\n", 2070 pci_name(ha->pdev)); 2071 goto iospace_error_exit; 2072 } 2073 2074 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2075 /* 83XX 26XX always use MQ type access for queues 2076 * - mbar 2, a.k.a region 4 */ 2077 ha->max_req_queues = ha->max_rsp_queues = 1; 2078 ha->msix_count = QLA_BASE_VECTORS; 2079 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2080 pci_resource_len(ha->pdev, 4)); 2081 2082 if (!ha->mqiobase) { 2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2084 "BAR2/region4 not enabled\n"); 2085 goto mqiobase_exit; 2086 } 2087 2088 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2089 pci_resource_len(ha->pdev, 2)); 2090 if (ha->msixbase) { 2091 /* Read MSIX vector size of the board */ 2092 pci_read_config_word(ha->pdev, 2093 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2094 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2095 /* 2096 * By default, driver uses at least two msix vectors 2097 * (default & rspq) 2098 */ 2099 if (ql2xmqsupport || ql2xnvmeenable) { 2100 /* MB interrupt uses 1 vector */ 2101 ha->max_req_queues = ha->msix_count - 1; 2102 2103 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2104 if (QLA_TGT_MODE_ENABLED()) 2105 ha->max_req_queues--; 2106 2107 ha->max_rsp_queues = ha->max_req_queues; 2108 2109 /* Queue pairs is the max value minus 2110 * the base queue pair */ 2111 ha->max_qpairs = ha->max_req_queues - 1; 2112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2113 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2114 } 2115 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2116 "MSI-X vector count: %d.\n", ha->msix_count); 2117 } else 2118 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2119 "BAR 1 not enabled.\n"); 2120 2121 mqiobase_exit: 2122 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2123 "MSIX Count: %d.\n", ha->msix_count); 2124 return 0; 2125 2126 iospace_error_exit: 2127 return -ENOMEM; 2128 } 2129 2130 static struct isp_operations qla2100_isp_ops = { 2131 .pci_config = qla2100_pci_config, 2132 .reset_chip = qla2x00_reset_chip, 2133 .chip_diag = qla2x00_chip_diag, 2134 .config_rings = qla2x00_config_rings, 2135 .reset_adapter = qla2x00_reset_adapter, 2136 .nvram_config = qla2x00_nvram_config, 2137 .update_fw_options = qla2x00_update_fw_options, 2138 .load_risc = qla2x00_load_risc, 2139 .pci_info_str = qla2x00_pci_info_str, 2140 .fw_version_str = qla2x00_fw_version_str, 2141 .intr_handler = qla2100_intr_handler, 2142 .enable_intrs = qla2x00_enable_intrs, 2143 .disable_intrs = qla2x00_disable_intrs, 2144 .abort_command = qla2x00_abort_command, 2145 .target_reset = qla2x00_abort_target, 2146 .lun_reset = qla2x00_lun_reset, 2147 .fabric_login = qla2x00_login_fabric, 2148 .fabric_logout = qla2x00_fabric_logout, 2149 .calc_req_entries = qla2x00_calc_iocbs_32, 2150 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2151 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2152 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2153 .read_nvram = qla2x00_read_nvram_data, 2154 .write_nvram = qla2x00_write_nvram_data, 2155 .fw_dump = qla2100_fw_dump, 2156 .beacon_on = NULL, 2157 .beacon_off = NULL, 2158 .beacon_blink = NULL, 2159 .read_optrom = qla2x00_read_optrom_data, 2160 .write_optrom = qla2x00_write_optrom_data, 2161 .get_flash_version = qla2x00_get_flash_version, 2162 .start_scsi = qla2x00_start_scsi, 2163 .start_scsi_mq = NULL, 2164 .abort_isp = qla2x00_abort_isp, 2165 .iospace_config = qla2x00_iospace_config, 2166 .initialize_adapter = qla2x00_initialize_adapter, 2167 }; 2168 2169 static struct isp_operations qla2300_isp_ops = { 2170 .pci_config = qla2300_pci_config, 2171 .reset_chip = qla2x00_reset_chip, 2172 .chip_diag = qla2x00_chip_diag, 2173 .config_rings = qla2x00_config_rings, 2174 .reset_adapter = qla2x00_reset_adapter, 2175 .nvram_config = qla2x00_nvram_config, 2176 .update_fw_options = qla2x00_update_fw_options, 2177 .load_risc = qla2x00_load_risc, 2178 .pci_info_str = qla2x00_pci_info_str, 2179 .fw_version_str = qla2x00_fw_version_str, 2180 .intr_handler = qla2300_intr_handler, 2181 .enable_intrs = qla2x00_enable_intrs, 2182 .disable_intrs = qla2x00_disable_intrs, 2183 .abort_command = qla2x00_abort_command, 2184 .target_reset = qla2x00_abort_target, 2185 .lun_reset = qla2x00_lun_reset, 2186 .fabric_login = qla2x00_login_fabric, 2187 .fabric_logout = qla2x00_fabric_logout, 2188 .calc_req_entries = qla2x00_calc_iocbs_32, 2189 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2190 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2191 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2192 .read_nvram = qla2x00_read_nvram_data, 2193 .write_nvram = qla2x00_write_nvram_data, 2194 .fw_dump = qla2300_fw_dump, 2195 .beacon_on = qla2x00_beacon_on, 2196 .beacon_off = qla2x00_beacon_off, 2197 .beacon_blink = qla2x00_beacon_blink, 2198 .read_optrom = qla2x00_read_optrom_data, 2199 .write_optrom = qla2x00_write_optrom_data, 2200 .get_flash_version = qla2x00_get_flash_version, 2201 .start_scsi = qla2x00_start_scsi, 2202 .start_scsi_mq = NULL, 2203 .abort_isp = qla2x00_abort_isp, 2204 .iospace_config = qla2x00_iospace_config, 2205 .initialize_adapter = qla2x00_initialize_adapter, 2206 }; 2207 2208 static struct isp_operations qla24xx_isp_ops = { 2209 .pci_config = qla24xx_pci_config, 2210 .reset_chip = qla24xx_reset_chip, 2211 .chip_diag = qla24xx_chip_diag, 2212 .config_rings = qla24xx_config_rings, 2213 .reset_adapter = qla24xx_reset_adapter, 2214 .nvram_config = qla24xx_nvram_config, 2215 .update_fw_options = qla24xx_update_fw_options, 2216 .load_risc = qla24xx_load_risc, 2217 .pci_info_str = qla24xx_pci_info_str, 2218 .fw_version_str = qla24xx_fw_version_str, 2219 .intr_handler = qla24xx_intr_handler, 2220 .enable_intrs = qla24xx_enable_intrs, 2221 .disable_intrs = qla24xx_disable_intrs, 2222 .abort_command = qla24xx_abort_command, 2223 .target_reset = qla24xx_abort_target, 2224 .lun_reset = qla24xx_lun_reset, 2225 .fabric_login = qla24xx_login_fabric, 2226 .fabric_logout = qla24xx_fabric_logout, 2227 .calc_req_entries = NULL, 2228 .build_iocbs = NULL, 2229 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2230 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2231 .read_nvram = qla24xx_read_nvram_data, 2232 .write_nvram = qla24xx_write_nvram_data, 2233 .fw_dump = qla24xx_fw_dump, 2234 .beacon_on = qla24xx_beacon_on, 2235 .beacon_off = qla24xx_beacon_off, 2236 .beacon_blink = qla24xx_beacon_blink, 2237 .read_optrom = qla24xx_read_optrom_data, 2238 .write_optrom = qla24xx_write_optrom_data, 2239 .get_flash_version = qla24xx_get_flash_version, 2240 .start_scsi = qla24xx_start_scsi, 2241 .start_scsi_mq = NULL, 2242 .abort_isp = qla2x00_abort_isp, 2243 .iospace_config = qla2x00_iospace_config, 2244 .initialize_adapter = qla2x00_initialize_adapter, 2245 }; 2246 2247 static struct isp_operations qla25xx_isp_ops = { 2248 .pci_config = qla25xx_pci_config, 2249 .reset_chip = qla24xx_reset_chip, 2250 .chip_diag = qla24xx_chip_diag, 2251 .config_rings = qla24xx_config_rings, 2252 .reset_adapter = qla24xx_reset_adapter, 2253 .nvram_config = qla24xx_nvram_config, 2254 .update_fw_options = qla24xx_update_fw_options, 2255 .load_risc = qla24xx_load_risc, 2256 .pci_info_str = qla24xx_pci_info_str, 2257 .fw_version_str = qla24xx_fw_version_str, 2258 .intr_handler = qla24xx_intr_handler, 2259 .enable_intrs = qla24xx_enable_intrs, 2260 .disable_intrs = qla24xx_disable_intrs, 2261 .abort_command = qla24xx_abort_command, 2262 .target_reset = qla24xx_abort_target, 2263 .lun_reset = qla24xx_lun_reset, 2264 .fabric_login = qla24xx_login_fabric, 2265 .fabric_logout = qla24xx_fabric_logout, 2266 .calc_req_entries = NULL, 2267 .build_iocbs = NULL, 2268 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2269 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2270 .read_nvram = qla25xx_read_nvram_data, 2271 .write_nvram = qla25xx_write_nvram_data, 2272 .fw_dump = qla25xx_fw_dump, 2273 .beacon_on = qla24xx_beacon_on, 2274 .beacon_off = qla24xx_beacon_off, 2275 .beacon_blink = qla24xx_beacon_blink, 2276 .read_optrom = qla25xx_read_optrom_data, 2277 .write_optrom = qla24xx_write_optrom_data, 2278 .get_flash_version = qla24xx_get_flash_version, 2279 .start_scsi = qla24xx_dif_start_scsi, 2280 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2281 .abort_isp = qla2x00_abort_isp, 2282 .iospace_config = qla2x00_iospace_config, 2283 .initialize_adapter = qla2x00_initialize_adapter, 2284 }; 2285 2286 static struct isp_operations qla81xx_isp_ops = { 2287 .pci_config = qla25xx_pci_config, 2288 .reset_chip = qla24xx_reset_chip, 2289 .chip_diag = qla24xx_chip_diag, 2290 .config_rings = qla24xx_config_rings, 2291 .reset_adapter = qla24xx_reset_adapter, 2292 .nvram_config = qla81xx_nvram_config, 2293 .update_fw_options = qla81xx_update_fw_options, 2294 .load_risc = qla81xx_load_risc, 2295 .pci_info_str = qla24xx_pci_info_str, 2296 .fw_version_str = qla24xx_fw_version_str, 2297 .intr_handler = qla24xx_intr_handler, 2298 .enable_intrs = qla24xx_enable_intrs, 2299 .disable_intrs = qla24xx_disable_intrs, 2300 .abort_command = qla24xx_abort_command, 2301 .target_reset = qla24xx_abort_target, 2302 .lun_reset = qla24xx_lun_reset, 2303 .fabric_login = qla24xx_login_fabric, 2304 .fabric_logout = qla24xx_fabric_logout, 2305 .calc_req_entries = NULL, 2306 .build_iocbs = NULL, 2307 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2308 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2309 .read_nvram = NULL, 2310 .write_nvram = NULL, 2311 .fw_dump = qla81xx_fw_dump, 2312 .beacon_on = qla24xx_beacon_on, 2313 .beacon_off = qla24xx_beacon_off, 2314 .beacon_blink = qla83xx_beacon_blink, 2315 .read_optrom = qla25xx_read_optrom_data, 2316 .write_optrom = qla24xx_write_optrom_data, 2317 .get_flash_version = qla24xx_get_flash_version, 2318 .start_scsi = qla24xx_dif_start_scsi, 2319 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2320 .abort_isp = qla2x00_abort_isp, 2321 .iospace_config = qla2x00_iospace_config, 2322 .initialize_adapter = qla2x00_initialize_adapter, 2323 }; 2324 2325 static struct isp_operations qla82xx_isp_ops = { 2326 .pci_config = qla82xx_pci_config, 2327 .reset_chip = qla82xx_reset_chip, 2328 .chip_diag = qla24xx_chip_diag, 2329 .config_rings = qla82xx_config_rings, 2330 .reset_adapter = qla24xx_reset_adapter, 2331 .nvram_config = qla81xx_nvram_config, 2332 .update_fw_options = qla24xx_update_fw_options, 2333 .load_risc = qla82xx_load_risc, 2334 .pci_info_str = qla24xx_pci_info_str, 2335 .fw_version_str = qla24xx_fw_version_str, 2336 .intr_handler = qla82xx_intr_handler, 2337 .enable_intrs = qla82xx_enable_intrs, 2338 .disable_intrs = qla82xx_disable_intrs, 2339 .abort_command = qla24xx_abort_command, 2340 .target_reset = qla24xx_abort_target, 2341 .lun_reset = qla24xx_lun_reset, 2342 .fabric_login = qla24xx_login_fabric, 2343 .fabric_logout = qla24xx_fabric_logout, 2344 .calc_req_entries = NULL, 2345 .build_iocbs = NULL, 2346 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2347 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2348 .read_nvram = qla24xx_read_nvram_data, 2349 .write_nvram = qla24xx_write_nvram_data, 2350 .fw_dump = qla82xx_fw_dump, 2351 .beacon_on = qla82xx_beacon_on, 2352 .beacon_off = qla82xx_beacon_off, 2353 .beacon_blink = NULL, 2354 .read_optrom = qla82xx_read_optrom_data, 2355 .write_optrom = qla82xx_write_optrom_data, 2356 .get_flash_version = qla82xx_get_flash_version, 2357 .start_scsi = qla82xx_start_scsi, 2358 .start_scsi_mq = NULL, 2359 .abort_isp = qla82xx_abort_isp, 2360 .iospace_config = qla82xx_iospace_config, 2361 .initialize_adapter = qla2x00_initialize_adapter, 2362 }; 2363 2364 static struct isp_operations qla8044_isp_ops = { 2365 .pci_config = qla82xx_pci_config, 2366 .reset_chip = qla82xx_reset_chip, 2367 .chip_diag = qla24xx_chip_diag, 2368 .config_rings = qla82xx_config_rings, 2369 .reset_adapter = qla24xx_reset_adapter, 2370 .nvram_config = qla81xx_nvram_config, 2371 .update_fw_options = qla24xx_update_fw_options, 2372 .load_risc = qla82xx_load_risc, 2373 .pci_info_str = qla24xx_pci_info_str, 2374 .fw_version_str = qla24xx_fw_version_str, 2375 .intr_handler = qla8044_intr_handler, 2376 .enable_intrs = qla82xx_enable_intrs, 2377 .disable_intrs = qla82xx_disable_intrs, 2378 .abort_command = qla24xx_abort_command, 2379 .target_reset = qla24xx_abort_target, 2380 .lun_reset = qla24xx_lun_reset, 2381 .fabric_login = qla24xx_login_fabric, 2382 .fabric_logout = qla24xx_fabric_logout, 2383 .calc_req_entries = NULL, 2384 .build_iocbs = NULL, 2385 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2386 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2387 .read_nvram = NULL, 2388 .write_nvram = NULL, 2389 .fw_dump = qla8044_fw_dump, 2390 .beacon_on = qla82xx_beacon_on, 2391 .beacon_off = qla82xx_beacon_off, 2392 .beacon_blink = NULL, 2393 .read_optrom = qla8044_read_optrom_data, 2394 .write_optrom = qla8044_write_optrom_data, 2395 .get_flash_version = qla82xx_get_flash_version, 2396 .start_scsi = qla82xx_start_scsi, 2397 .start_scsi_mq = NULL, 2398 .abort_isp = qla8044_abort_isp, 2399 .iospace_config = qla82xx_iospace_config, 2400 .initialize_adapter = qla2x00_initialize_adapter, 2401 }; 2402 2403 static struct isp_operations qla83xx_isp_ops = { 2404 .pci_config = qla25xx_pci_config, 2405 .reset_chip = qla24xx_reset_chip, 2406 .chip_diag = qla24xx_chip_diag, 2407 .config_rings = qla24xx_config_rings, 2408 .reset_adapter = qla24xx_reset_adapter, 2409 .nvram_config = qla81xx_nvram_config, 2410 .update_fw_options = qla81xx_update_fw_options, 2411 .load_risc = qla81xx_load_risc, 2412 .pci_info_str = qla24xx_pci_info_str, 2413 .fw_version_str = qla24xx_fw_version_str, 2414 .intr_handler = qla24xx_intr_handler, 2415 .enable_intrs = qla24xx_enable_intrs, 2416 .disable_intrs = qla24xx_disable_intrs, 2417 .abort_command = qla24xx_abort_command, 2418 .target_reset = qla24xx_abort_target, 2419 .lun_reset = qla24xx_lun_reset, 2420 .fabric_login = qla24xx_login_fabric, 2421 .fabric_logout = qla24xx_fabric_logout, 2422 .calc_req_entries = NULL, 2423 .build_iocbs = NULL, 2424 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2425 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2426 .read_nvram = NULL, 2427 .write_nvram = NULL, 2428 .fw_dump = qla83xx_fw_dump, 2429 .beacon_on = qla24xx_beacon_on, 2430 .beacon_off = qla24xx_beacon_off, 2431 .beacon_blink = qla83xx_beacon_blink, 2432 .read_optrom = qla25xx_read_optrom_data, 2433 .write_optrom = qla24xx_write_optrom_data, 2434 .get_flash_version = qla24xx_get_flash_version, 2435 .start_scsi = qla24xx_dif_start_scsi, 2436 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2437 .abort_isp = qla2x00_abort_isp, 2438 .iospace_config = qla83xx_iospace_config, 2439 .initialize_adapter = qla2x00_initialize_adapter, 2440 }; 2441 2442 static struct isp_operations qlafx00_isp_ops = { 2443 .pci_config = qlafx00_pci_config, 2444 .reset_chip = qlafx00_soft_reset, 2445 .chip_diag = qlafx00_chip_diag, 2446 .config_rings = qlafx00_config_rings, 2447 .reset_adapter = qlafx00_soft_reset, 2448 .nvram_config = NULL, 2449 .update_fw_options = NULL, 2450 .load_risc = NULL, 2451 .pci_info_str = qlafx00_pci_info_str, 2452 .fw_version_str = qlafx00_fw_version_str, 2453 .intr_handler = qlafx00_intr_handler, 2454 .enable_intrs = qlafx00_enable_intrs, 2455 .disable_intrs = qlafx00_disable_intrs, 2456 .abort_command = qla24xx_async_abort_command, 2457 .target_reset = qlafx00_abort_target, 2458 .lun_reset = qlafx00_lun_reset, 2459 .fabric_login = NULL, 2460 .fabric_logout = NULL, 2461 .calc_req_entries = NULL, 2462 .build_iocbs = NULL, 2463 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2464 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2465 .read_nvram = qla24xx_read_nvram_data, 2466 .write_nvram = qla24xx_write_nvram_data, 2467 .fw_dump = NULL, 2468 .beacon_on = qla24xx_beacon_on, 2469 .beacon_off = qla24xx_beacon_off, 2470 .beacon_blink = NULL, 2471 .read_optrom = qla24xx_read_optrom_data, 2472 .write_optrom = qla24xx_write_optrom_data, 2473 .get_flash_version = qla24xx_get_flash_version, 2474 .start_scsi = qlafx00_start_scsi, 2475 .start_scsi_mq = NULL, 2476 .abort_isp = qlafx00_abort_isp, 2477 .iospace_config = qlafx00_iospace_config, 2478 .initialize_adapter = qlafx00_initialize_adapter, 2479 }; 2480 2481 static struct isp_operations qla27xx_isp_ops = { 2482 .pci_config = qla25xx_pci_config, 2483 .reset_chip = qla24xx_reset_chip, 2484 .chip_diag = qla24xx_chip_diag, 2485 .config_rings = qla24xx_config_rings, 2486 .reset_adapter = qla24xx_reset_adapter, 2487 .nvram_config = qla81xx_nvram_config, 2488 .update_fw_options = qla81xx_update_fw_options, 2489 .load_risc = qla81xx_load_risc, 2490 .pci_info_str = qla24xx_pci_info_str, 2491 .fw_version_str = qla24xx_fw_version_str, 2492 .intr_handler = qla24xx_intr_handler, 2493 .enable_intrs = qla24xx_enable_intrs, 2494 .disable_intrs = qla24xx_disable_intrs, 2495 .abort_command = qla24xx_abort_command, 2496 .target_reset = qla24xx_abort_target, 2497 .lun_reset = qla24xx_lun_reset, 2498 .fabric_login = qla24xx_login_fabric, 2499 .fabric_logout = qla24xx_fabric_logout, 2500 .calc_req_entries = NULL, 2501 .build_iocbs = NULL, 2502 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2503 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2504 .read_nvram = NULL, 2505 .write_nvram = NULL, 2506 .fw_dump = qla27xx_fwdump, 2507 .beacon_on = qla24xx_beacon_on, 2508 .beacon_off = qla24xx_beacon_off, 2509 .beacon_blink = qla83xx_beacon_blink, 2510 .read_optrom = qla25xx_read_optrom_data, 2511 .write_optrom = qla24xx_write_optrom_data, 2512 .get_flash_version = qla24xx_get_flash_version, 2513 .start_scsi = qla24xx_dif_start_scsi, 2514 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2515 .abort_isp = qla2x00_abort_isp, 2516 .iospace_config = qla83xx_iospace_config, 2517 .initialize_adapter = qla2x00_initialize_adapter, 2518 }; 2519 2520 static inline void 2521 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2522 { 2523 ha->device_type = DT_EXTENDED_IDS; 2524 switch (ha->pdev->device) { 2525 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2526 ha->isp_type |= DT_ISP2100; 2527 ha->device_type &= ~DT_EXTENDED_IDS; 2528 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2529 break; 2530 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2531 ha->isp_type |= DT_ISP2200; 2532 ha->device_type &= ~DT_EXTENDED_IDS; 2533 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2534 break; 2535 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2536 ha->isp_type |= DT_ISP2300; 2537 ha->device_type |= DT_ZIO_SUPPORTED; 2538 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2539 break; 2540 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2541 ha->isp_type |= DT_ISP2312; 2542 ha->device_type |= DT_ZIO_SUPPORTED; 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2544 break; 2545 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2546 ha->isp_type |= DT_ISP2322; 2547 ha->device_type |= DT_ZIO_SUPPORTED; 2548 if (ha->pdev->subsystem_vendor == 0x1028 && 2549 ha->pdev->subsystem_device == 0x0170) 2550 ha->device_type |= DT_OEM_001; 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2552 break; 2553 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2554 ha->isp_type |= DT_ISP6312; 2555 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2556 break; 2557 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2558 ha->isp_type |= DT_ISP6322; 2559 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2560 break; 2561 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2562 ha->isp_type |= DT_ISP2422; 2563 ha->device_type |= DT_ZIO_SUPPORTED; 2564 ha->device_type |= DT_FWI2; 2565 ha->device_type |= DT_IIDMA; 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2567 break; 2568 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2569 ha->isp_type |= DT_ISP2432; 2570 ha->device_type |= DT_ZIO_SUPPORTED; 2571 ha->device_type |= DT_FWI2; 2572 ha->device_type |= DT_IIDMA; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2576 ha->isp_type |= DT_ISP8432; 2577 ha->device_type |= DT_ZIO_SUPPORTED; 2578 ha->device_type |= DT_FWI2; 2579 ha->device_type |= DT_IIDMA; 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2581 break; 2582 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2583 ha->isp_type |= DT_ISP5422; 2584 ha->device_type |= DT_FWI2; 2585 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2586 break; 2587 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2588 ha->isp_type |= DT_ISP5432; 2589 ha->device_type |= DT_FWI2; 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2591 break; 2592 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2593 ha->isp_type |= DT_ISP2532; 2594 ha->device_type |= DT_ZIO_SUPPORTED; 2595 ha->device_type |= DT_FWI2; 2596 ha->device_type |= DT_IIDMA; 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2600 ha->isp_type |= DT_ISP8001; 2601 ha->device_type |= DT_ZIO_SUPPORTED; 2602 ha->device_type |= DT_FWI2; 2603 ha->device_type |= DT_IIDMA; 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2607 ha->isp_type |= DT_ISP8021; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2611 /* Initialize 82XX ISP flags */ 2612 qla82xx_init_flags(ha); 2613 break; 2614 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2615 ha->isp_type |= DT_ISP8044; 2616 ha->device_type |= DT_ZIO_SUPPORTED; 2617 ha->device_type |= DT_FWI2; 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2619 /* Initialize 82XX ISP flags */ 2620 qla82xx_init_flags(ha); 2621 break; 2622 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2623 ha->isp_type |= DT_ISP2031; 2624 ha->device_type |= DT_ZIO_SUPPORTED; 2625 ha->device_type |= DT_FWI2; 2626 ha->device_type |= DT_IIDMA; 2627 ha->device_type |= DT_T10_PI; 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2629 break; 2630 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2631 ha->isp_type |= DT_ISP8031; 2632 ha->device_type |= DT_ZIO_SUPPORTED; 2633 ha->device_type |= DT_FWI2; 2634 ha->device_type |= DT_IIDMA; 2635 ha->device_type |= DT_T10_PI; 2636 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2637 break; 2638 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2639 ha->isp_type |= DT_ISPFX00; 2640 break; 2641 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2642 ha->isp_type |= DT_ISP2071; 2643 ha->device_type |= DT_ZIO_SUPPORTED; 2644 ha->device_type |= DT_FWI2; 2645 ha->device_type |= DT_IIDMA; 2646 ha->device_type |= DT_T10_PI; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2648 break; 2649 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2650 ha->isp_type |= DT_ISP2271; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->device_type |= DT_FWI2; 2653 ha->device_type |= DT_IIDMA; 2654 ha->device_type |= DT_T10_PI; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 break; 2657 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2658 ha->isp_type |= DT_ISP2261; 2659 ha->device_type |= DT_ZIO_SUPPORTED; 2660 ha->device_type |= DT_FWI2; 2661 ha->device_type |= DT_IIDMA; 2662 ha->device_type |= DT_T10_PI; 2663 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2664 break; 2665 } 2666 2667 if (IS_QLA82XX(ha)) 2668 ha->port_no = ha->portnum & 1; 2669 else { 2670 /* Get adapter physical port no from interrupt pin register. */ 2671 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2672 if (IS_QLA27XX(ha)) 2673 ha->port_no--; 2674 else 2675 ha->port_no = !(ha->port_no & 1); 2676 } 2677 2678 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2679 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2680 ha->device_type, ha->port_no, ha->fw_srisc_address); 2681 } 2682 2683 static void 2684 qla2xxx_scan_start(struct Scsi_Host *shost) 2685 { 2686 scsi_qla_host_t *vha = shost_priv(shost); 2687 2688 if (vha->hw->flags.running_gold_fw) 2689 return; 2690 2691 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2692 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2693 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2694 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2695 } 2696 2697 static int 2698 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2699 { 2700 scsi_qla_host_t *vha = shost_priv(shost); 2701 2702 if (test_bit(UNLOADING, &vha->dpc_flags)) 2703 return 1; 2704 if (!vha->host) 2705 return 1; 2706 if (time > vha->hw->loop_reset_delay * HZ) 2707 return 1; 2708 2709 return atomic_read(&vha->loop_state) == LOOP_READY; 2710 } 2711 2712 static void qla2x00_iocb_work_fn(struct work_struct *work) 2713 { 2714 struct scsi_qla_host *vha = container_of(work, 2715 struct scsi_qla_host, iocb_work); 2716 struct qla_hw_data *ha = vha->hw; 2717 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2718 int i = 20; 2719 unsigned long flags; 2720 2721 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2722 return; 2723 2724 while (!list_empty(&vha->work_list) && i > 0) { 2725 qla2x00_do_work(vha); 2726 i--; 2727 } 2728 2729 spin_lock_irqsave(&vha->work_lock, flags); 2730 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2731 spin_unlock_irqrestore(&vha->work_lock, flags); 2732 } 2733 2734 /* 2735 * PCI driver interface 2736 */ 2737 static int 2738 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2739 { 2740 int ret = -ENODEV; 2741 struct Scsi_Host *host; 2742 scsi_qla_host_t *base_vha = NULL; 2743 struct qla_hw_data *ha; 2744 char pci_info[30]; 2745 char fw_str[30], wq_name[30]; 2746 struct scsi_host_template *sht; 2747 int bars, mem_only = 0; 2748 uint16_t req_length = 0, rsp_length = 0; 2749 struct req_que *req = NULL; 2750 struct rsp_que *rsp = NULL; 2751 int i; 2752 2753 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2754 sht = &qla2xxx_driver_template; 2755 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2763 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2764 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2765 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2766 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2770 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2771 mem_only = 1; 2772 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2773 "Mem only adapter.\n"); 2774 } 2775 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2776 "Bars=%d.\n", bars); 2777 2778 if (mem_only) { 2779 if (pci_enable_device_mem(pdev)) 2780 return ret; 2781 } else { 2782 if (pci_enable_device(pdev)) 2783 return ret; 2784 } 2785 2786 /* This may fail but that's ok */ 2787 pci_enable_pcie_error_reporting(pdev); 2788 2789 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2790 if (!ha) { 2791 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2792 "Unable to allocate memory for ha.\n"); 2793 goto disable_device; 2794 } 2795 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2796 "Memory allocated for ha=%p.\n", ha); 2797 ha->pdev = pdev; 2798 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2799 spin_lock_init(&ha->tgt.q_full_lock); 2800 spin_lock_init(&ha->tgt.sess_lock); 2801 spin_lock_init(&ha->tgt.atio_lock); 2802 2803 atomic_set(&ha->nvme_active_aen_cnt, 0); 2804 2805 /* Clear our data area */ 2806 ha->bars = bars; 2807 ha->mem_only = mem_only; 2808 spin_lock_init(&ha->hardware_lock); 2809 spin_lock_init(&ha->vport_slock); 2810 mutex_init(&ha->selflogin_lock); 2811 mutex_init(&ha->optrom_mutex); 2812 2813 /* Set ISP-type information. */ 2814 qla2x00_set_isp_flags(ha); 2815 2816 /* Set EEH reset type to fundamental if required by hba */ 2817 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2818 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2819 pdev->needs_freset = 1; 2820 2821 ha->prev_topology = 0; 2822 ha->init_cb_size = sizeof(init_cb_t); 2823 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2824 ha->optrom_size = OPTROM_SIZE_2300; 2825 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2826 2827 /* Assign ISP specific operations. */ 2828 if (IS_QLA2100(ha)) { 2829 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2830 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2831 req_length = REQUEST_ENTRY_CNT_2100; 2832 rsp_length = RESPONSE_ENTRY_CNT_2100; 2833 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2834 ha->gid_list_info_size = 4; 2835 ha->flash_conf_off = ~0; 2836 ha->flash_data_off = ~0; 2837 ha->nvram_conf_off = ~0; 2838 ha->nvram_data_off = ~0; 2839 ha->isp_ops = &qla2100_isp_ops; 2840 } else if (IS_QLA2200(ha)) { 2841 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2842 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2843 req_length = REQUEST_ENTRY_CNT_2200; 2844 rsp_length = RESPONSE_ENTRY_CNT_2100; 2845 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2846 ha->gid_list_info_size = 4; 2847 ha->flash_conf_off = ~0; 2848 ha->flash_data_off = ~0; 2849 ha->nvram_conf_off = ~0; 2850 ha->nvram_data_off = ~0; 2851 ha->isp_ops = &qla2100_isp_ops; 2852 } else if (IS_QLA23XX(ha)) { 2853 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2854 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2855 req_length = REQUEST_ENTRY_CNT_2200; 2856 rsp_length = RESPONSE_ENTRY_CNT_2300; 2857 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2858 ha->gid_list_info_size = 6; 2859 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2860 ha->optrom_size = OPTROM_SIZE_2322; 2861 ha->flash_conf_off = ~0; 2862 ha->flash_data_off = ~0; 2863 ha->nvram_conf_off = ~0; 2864 ha->nvram_data_off = ~0; 2865 ha->isp_ops = &qla2300_isp_ops; 2866 } else if (IS_QLA24XX_TYPE(ha)) { 2867 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2868 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2869 req_length = REQUEST_ENTRY_CNT_24XX; 2870 rsp_length = RESPONSE_ENTRY_CNT_2300; 2871 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2872 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2873 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2874 ha->gid_list_info_size = 8; 2875 ha->optrom_size = OPTROM_SIZE_24XX; 2876 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2877 ha->isp_ops = &qla24xx_isp_ops; 2878 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2879 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2880 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2881 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2882 } else if (IS_QLA25XX(ha)) { 2883 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2884 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2885 req_length = REQUEST_ENTRY_CNT_24XX; 2886 rsp_length = RESPONSE_ENTRY_CNT_2300; 2887 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2888 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2889 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2890 ha->gid_list_info_size = 8; 2891 ha->optrom_size = OPTROM_SIZE_25XX; 2892 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2893 ha->isp_ops = &qla25xx_isp_ops; 2894 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2895 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2896 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2897 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2898 } else if (IS_QLA81XX(ha)) { 2899 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2900 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2901 req_length = REQUEST_ENTRY_CNT_24XX; 2902 rsp_length = RESPONSE_ENTRY_CNT_2300; 2903 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2904 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2905 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2906 ha->gid_list_info_size = 8; 2907 ha->optrom_size = OPTROM_SIZE_81XX; 2908 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2909 ha->isp_ops = &qla81xx_isp_ops; 2910 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2911 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2912 ha->nvram_conf_off = ~0; 2913 ha->nvram_data_off = ~0; 2914 } else if (IS_QLA82XX(ha)) { 2915 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2916 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2917 req_length = REQUEST_ENTRY_CNT_82XX; 2918 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2920 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2921 ha->gid_list_info_size = 8; 2922 ha->optrom_size = OPTROM_SIZE_82XX; 2923 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2924 ha->isp_ops = &qla82xx_isp_ops; 2925 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2926 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2927 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2928 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2929 } else if (IS_QLA8044(ha)) { 2930 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2931 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2932 req_length = REQUEST_ENTRY_CNT_82XX; 2933 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2934 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2935 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2936 ha->gid_list_info_size = 8; 2937 ha->optrom_size = OPTROM_SIZE_83XX; 2938 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2939 ha->isp_ops = &qla8044_isp_ops; 2940 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2941 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2942 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2943 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2944 } else if (IS_QLA83XX(ha)) { 2945 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2946 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2947 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2948 req_length = REQUEST_ENTRY_CNT_83XX; 2949 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2950 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2951 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2952 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2953 ha->gid_list_info_size = 8; 2954 ha->optrom_size = OPTROM_SIZE_83XX; 2955 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2956 ha->isp_ops = &qla83xx_isp_ops; 2957 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2958 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2959 ha->nvram_conf_off = ~0; 2960 ha->nvram_data_off = ~0; 2961 } else if (IS_QLAFX00(ha)) { 2962 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2963 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2964 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2965 req_length = REQUEST_ENTRY_CNT_FX00; 2966 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2967 ha->isp_ops = &qlafx00_isp_ops; 2968 ha->port_down_retry_count = 30; /* default value */ 2969 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2970 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2971 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2972 ha->mr.fw_hbt_en = 1; 2973 ha->mr.host_info_resend = false; 2974 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2975 } else if (IS_QLA27XX(ha)) { 2976 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2977 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2978 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2979 req_length = REQUEST_ENTRY_CNT_83XX; 2980 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2981 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2982 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2983 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2984 ha->gid_list_info_size = 8; 2985 ha->optrom_size = OPTROM_SIZE_83XX; 2986 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2987 ha->isp_ops = &qla27xx_isp_ops; 2988 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2989 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2990 ha->nvram_conf_off = ~0; 2991 ha->nvram_data_off = ~0; 2992 } 2993 2994 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2995 "mbx_count=%d, req_length=%d, " 2996 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2997 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2998 "max_fibre_devices=%d.\n", 2999 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3000 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3001 ha->nvram_npiv_size, ha->max_fibre_devices); 3002 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3003 "isp_ops=%p, flash_conf_off=%d, " 3004 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3005 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3006 ha->nvram_conf_off, ha->nvram_data_off); 3007 3008 /* Configure PCI I/O space */ 3009 ret = ha->isp_ops->iospace_config(ha); 3010 if (ret) 3011 goto iospace_config_failed; 3012 3013 ql_log_pci(ql_log_info, pdev, 0x001d, 3014 "Found an ISP%04X irq %d iobase 0x%p.\n", 3015 pdev->device, pdev->irq, ha->iobase); 3016 mutex_init(&ha->vport_lock); 3017 mutex_init(&ha->mq_lock); 3018 init_completion(&ha->mbx_cmd_comp); 3019 complete(&ha->mbx_cmd_comp); 3020 init_completion(&ha->mbx_intr_comp); 3021 init_completion(&ha->dcbx_comp); 3022 init_completion(&ha->lb_portup_comp); 3023 3024 set_bit(0, (unsigned long *) ha->vp_idx_map); 3025 3026 qla2x00_config_dma_addressing(ha); 3027 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3028 "64 Bit addressing is %s.\n", 3029 ha->flags.enable_64bit_addressing ? "enable" : 3030 "disable"); 3031 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3032 if (ret) { 3033 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3034 "Failed to allocate memory for adapter, aborting.\n"); 3035 3036 goto probe_hw_failed; 3037 } 3038 3039 req->max_q_depth = MAX_Q_DEPTH; 3040 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3041 req->max_q_depth = ql2xmaxqdepth; 3042 3043 3044 base_vha = qla2x00_create_host(sht, ha); 3045 if (!base_vha) { 3046 ret = -ENOMEM; 3047 goto probe_hw_failed; 3048 } 3049 3050 pci_set_drvdata(pdev, base_vha); 3051 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3052 3053 host = base_vha->host; 3054 base_vha->req = req; 3055 if (IS_QLA2XXX_MIDTYPE(ha)) 3056 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER; 3057 else 3058 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3059 base_vha->vp_idx; 3060 3061 /* Setup fcport template structure. */ 3062 ha->mr.fcport.vha = base_vha; 3063 ha->mr.fcport.port_type = FCT_UNKNOWN; 3064 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3065 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3066 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3067 ha->mr.fcport.scan_state = 1; 3068 3069 /* Set the SG table size based on ISP type */ 3070 if (!IS_FWI2_CAPABLE(ha)) { 3071 if (IS_QLA2100(ha)) 3072 host->sg_tablesize = 32; 3073 } else { 3074 if (!IS_QLA82XX(ha)) 3075 host->sg_tablesize = QLA_SG_ALL; 3076 } 3077 host->max_id = ha->max_fibre_devices; 3078 host->cmd_per_lun = 3; 3079 host->unique_id = host->host_no; 3080 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3081 host->max_cmd_len = 32; 3082 else 3083 host->max_cmd_len = MAX_CMDSZ; 3084 host->max_channel = MAX_BUSES - 1; 3085 /* Older HBAs support only 16-bit LUNs */ 3086 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3087 ql2xmaxlun > 0xffff) 3088 host->max_lun = 0xffff; 3089 else 3090 host->max_lun = ql2xmaxlun; 3091 host->transportt = qla2xxx_transport_template; 3092 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3093 3094 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3095 "max_id=%d this_id=%d " 3096 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3097 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3098 host->this_id, host->cmd_per_lun, host->unique_id, 3099 host->max_cmd_len, host->max_channel, host->max_lun, 3100 host->transportt, sht->vendor_id); 3101 3102 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3103 3104 /* Set up the irqs */ 3105 ret = qla2x00_request_irqs(ha, rsp); 3106 if (ret) 3107 goto probe_failed; 3108 3109 /* Alloc arrays of request and response ring ptrs */ 3110 if (qla2x00_alloc_queues(ha, req, rsp)) { 3111 ql_log(ql_log_fatal, base_vha, 0x003d, 3112 "Failed to allocate memory for queue pointers..." 3113 "aborting.\n"); 3114 goto probe_failed; 3115 } 3116 3117 if (ha->mqenable && shost_use_blk_mq(host)) { 3118 /* number of hardware queues supported by blk/scsi-mq*/ 3119 host->nr_hw_queues = ha->max_qpairs; 3120 3121 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3122 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3123 } else { 3124 if (ql2xnvmeenable) { 3125 host->nr_hw_queues = ha->max_qpairs; 3126 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3127 "FC-NVMe support is enabled, HW queues=%d\n", 3128 host->nr_hw_queues); 3129 } else { 3130 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3131 "blk/scsi-mq disabled.\n"); 3132 } 3133 } 3134 3135 qlt_probe_one_stage1(base_vha, ha); 3136 3137 pci_save_state(pdev); 3138 3139 /* Assign back pointers */ 3140 rsp->req = req; 3141 req->rsp = rsp; 3142 3143 if (IS_QLAFX00(ha)) { 3144 ha->rsp_q_map[0] = rsp; 3145 ha->req_q_map[0] = req; 3146 set_bit(0, ha->req_qid_map); 3147 set_bit(0, ha->rsp_qid_map); 3148 } 3149 3150 /* FWI2-capable only. */ 3151 req->req_q_in = &ha->iobase->isp24.req_q_in; 3152 req->req_q_out = &ha->iobase->isp24.req_q_out; 3153 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3154 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3155 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3156 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3157 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3158 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3159 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3160 } 3161 3162 if (IS_QLAFX00(ha)) { 3163 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3164 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3165 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3166 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3167 } 3168 3169 if (IS_P3P_TYPE(ha)) { 3170 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3171 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3172 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3173 } 3174 3175 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3176 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3177 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3178 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3179 "req->req_q_in=%p req->req_q_out=%p " 3180 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3181 req->req_q_in, req->req_q_out, 3182 rsp->rsp_q_in, rsp->rsp_q_out); 3183 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3184 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3185 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3186 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3187 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3188 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3189 3190 if (ha->isp_ops->initialize_adapter(base_vha)) { 3191 ql_log(ql_log_fatal, base_vha, 0x00d6, 3192 "Failed to initialize adapter - Adapter flags %x.\n", 3193 base_vha->device_flags); 3194 3195 if (IS_QLA82XX(ha)) { 3196 qla82xx_idc_lock(ha); 3197 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3198 QLA8XXX_DEV_FAILED); 3199 qla82xx_idc_unlock(ha); 3200 ql_log(ql_log_fatal, base_vha, 0x00d7, 3201 "HW State: FAILED.\n"); 3202 } else if (IS_QLA8044(ha)) { 3203 qla8044_idc_lock(ha); 3204 qla8044_wr_direct(base_vha, 3205 QLA8044_CRB_DEV_STATE_INDEX, 3206 QLA8XXX_DEV_FAILED); 3207 qla8044_idc_unlock(ha); 3208 ql_log(ql_log_fatal, base_vha, 0x0150, 3209 "HW State: FAILED.\n"); 3210 } 3211 3212 ret = -ENODEV; 3213 goto probe_failed; 3214 } 3215 3216 if (IS_QLAFX00(ha)) 3217 host->can_queue = QLAFX00_MAX_CANQUEUE; 3218 else 3219 host->can_queue = req->num_outstanding_cmds - 10; 3220 3221 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3222 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3223 host->can_queue, base_vha->req, 3224 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3225 3226 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3227 3228 if (ha->mqenable) { 3229 bool mq = false; 3230 bool startit = false; 3231 3232 if (QLA_TGT_MODE_ENABLED()) { 3233 mq = true; 3234 startit = false; 3235 } 3236 3237 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3238 shost_use_blk_mq(host)) { 3239 mq = true; 3240 startit = true; 3241 } 3242 3243 if (mq) { 3244 /* Create start of day qpairs for Block MQ */ 3245 for (i = 0; i < ha->max_qpairs; i++) 3246 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3247 } 3248 } 3249 3250 if (ha->flags.running_gold_fw) 3251 goto skip_dpc; 3252 3253 /* 3254 * Startup the kernel thread for this host adapter 3255 */ 3256 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3257 "%s_dpc", base_vha->host_str); 3258 if (IS_ERR(ha->dpc_thread)) { 3259 ql_log(ql_log_fatal, base_vha, 0x00ed, 3260 "Failed to start DPC thread.\n"); 3261 ret = PTR_ERR(ha->dpc_thread); 3262 ha->dpc_thread = NULL; 3263 goto probe_failed; 3264 } 3265 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3266 "DPC thread started successfully.\n"); 3267 3268 /* 3269 * If we're not coming up in initiator mode, we might sit for 3270 * a while without waking up the dpc thread, which leads to a 3271 * stuck process warning. So just kick the dpc once here and 3272 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3273 */ 3274 qla2xxx_wake_dpc(base_vha); 3275 3276 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3277 3278 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3279 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3280 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3281 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3282 3283 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3284 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3285 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3286 INIT_WORK(&ha->idc_state_handler, 3287 qla83xx_idc_state_handler_work); 3288 INIT_WORK(&ha->nic_core_unrecoverable, 3289 qla83xx_nic_core_unrecoverable_work); 3290 } 3291 3292 skip_dpc: 3293 list_add_tail(&base_vha->list, &ha->vp_list); 3294 base_vha->host->irq = ha->pdev->irq; 3295 3296 /* Initialized the timer */ 3297 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3298 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3299 "Started qla2x00_timer with " 3300 "interval=%d.\n", WATCH_INTERVAL); 3301 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3302 "Detected hba at address=%p.\n", 3303 ha); 3304 3305 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3306 if (ha->fw_attributes & BIT_4) { 3307 int prot = 0, guard; 3308 base_vha->flags.difdix_supported = 1; 3309 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3310 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3311 if (ql2xenabledif == 1) 3312 prot = SHOST_DIX_TYPE0_PROTECTION; 3313 scsi_host_set_prot(host, 3314 prot | SHOST_DIF_TYPE1_PROTECTION 3315 | SHOST_DIF_TYPE2_PROTECTION 3316 | SHOST_DIF_TYPE3_PROTECTION 3317 | SHOST_DIX_TYPE1_PROTECTION 3318 | SHOST_DIX_TYPE2_PROTECTION 3319 | SHOST_DIX_TYPE3_PROTECTION); 3320 3321 guard = SHOST_DIX_GUARD_CRC; 3322 3323 if (IS_PI_IPGUARD_CAPABLE(ha) && 3324 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3325 guard |= SHOST_DIX_GUARD_IP; 3326 3327 scsi_host_set_guard(host, guard); 3328 } else 3329 base_vha->flags.difdix_supported = 0; 3330 } 3331 3332 ha->isp_ops->enable_intrs(ha); 3333 3334 if (IS_QLAFX00(ha)) { 3335 ret = qlafx00_fx_disc(base_vha, 3336 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3337 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3338 QLA_SG_ALL : 128; 3339 } 3340 3341 ret = scsi_add_host(host, &pdev->dev); 3342 if (ret) 3343 goto probe_failed; 3344 3345 base_vha->flags.init_done = 1; 3346 base_vha->flags.online = 1; 3347 ha->prev_minidump_failed = 0; 3348 3349 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3350 "Init done and hba is online.\n"); 3351 3352 if (qla_ini_mode_enabled(base_vha) || 3353 qla_dual_mode_enabled(base_vha)) 3354 scsi_scan_host(host); 3355 else 3356 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3357 "skipping scsi_scan_host() for non-initiator port\n"); 3358 3359 qla2x00_alloc_sysfs_attr(base_vha); 3360 3361 if (IS_QLAFX00(ha)) { 3362 ret = qlafx00_fx_disc(base_vha, 3363 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3364 3365 /* Register system information */ 3366 ret = qlafx00_fx_disc(base_vha, 3367 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3368 } 3369 3370 qla2x00_init_host_attr(base_vha); 3371 3372 qla2x00_dfs_setup(base_vha); 3373 3374 ql_log(ql_log_info, base_vha, 0x00fb, 3375 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3376 ql_log(ql_log_info, base_vha, 0x00fc, 3377 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3378 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3379 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3380 base_vha->host_no, 3381 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3382 3383 qlt_add_target(ha, base_vha); 3384 3385 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3386 3387 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3388 return -ENODEV; 3389 3390 if (ha->flags.detected_lr_sfp) { 3391 ql_log(ql_log_info, base_vha, 0xffff, 3392 "Reset chip to pick up LR SFP setting\n"); 3393 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3394 qla2xxx_wake_dpc(base_vha); 3395 } 3396 3397 return 0; 3398 3399 probe_failed: 3400 if (base_vha->timer_active) 3401 qla2x00_stop_timer(base_vha); 3402 base_vha->flags.online = 0; 3403 if (ha->dpc_thread) { 3404 struct task_struct *t = ha->dpc_thread; 3405 3406 ha->dpc_thread = NULL; 3407 kthread_stop(t); 3408 } 3409 3410 qla2x00_free_device(base_vha); 3411 3412 scsi_host_put(base_vha->host); 3413 3414 probe_hw_failed: 3415 qla2x00_mem_free(ha); 3416 qla2x00_free_req_que(ha, req); 3417 qla2x00_free_rsp_que(ha, rsp); 3418 qla2x00_clear_drv_active(ha); 3419 3420 iospace_config_failed: 3421 if (IS_P3P_TYPE(ha)) { 3422 if (!ha->nx_pcibase) 3423 iounmap((device_reg_t *)ha->nx_pcibase); 3424 if (!ql2xdbwr) 3425 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3426 } else { 3427 if (ha->iobase) 3428 iounmap(ha->iobase); 3429 if (ha->cregbase) 3430 iounmap(ha->cregbase); 3431 } 3432 pci_release_selected_regions(ha->pdev, ha->bars); 3433 kfree(ha); 3434 3435 disable_device: 3436 pci_disable_device(pdev); 3437 return ret; 3438 } 3439 3440 static void 3441 qla2x00_shutdown(struct pci_dev *pdev) 3442 { 3443 scsi_qla_host_t *vha; 3444 struct qla_hw_data *ha; 3445 3446 vha = pci_get_drvdata(pdev); 3447 ha = vha->hw; 3448 3449 ql_log(ql_log_info, vha, 0xfffa, 3450 "Adapter shutdown\n"); 3451 3452 /* 3453 * Prevent future board_disable and wait 3454 * until any pending board_disable has completed. 3455 */ 3456 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3457 cancel_work_sync(&ha->board_disable); 3458 3459 if (!atomic_read(&pdev->enable_cnt)) 3460 return; 3461 3462 /* Notify ISPFX00 firmware */ 3463 if (IS_QLAFX00(ha)) 3464 qlafx00_driver_shutdown(vha, 20); 3465 3466 /* Turn-off FCE trace */ 3467 if (ha->flags.fce_enabled) { 3468 qla2x00_disable_fce_trace(vha, NULL, NULL); 3469 ha->flags.fce_enabled = 0; 3470 } 3471 3472 /* Turn-off EFT trace */ 3473 if (ha->eft) 3474 qla2x00_disable_eft_trace(vha); 3475 3476 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3477 if (ha->flags.fw_started) 3478 qla2x00_abort_isp_cleanup(vha); 3479 } else { 3480 /* Stop currently executing firmware. */ 3481 qla2x00_try_to_stop_firmware(vha); 3482 } 3483 3484 /* Turn adapter off line */ 3485 vha->flags.online = 0; 3486 3487 /* turn-off interrupts on the card */ 3488 if (ha->interrupts_on) { 3489 vha->flags.init_done = 0; 3490 ha->isp_ops->disable_intrs(ha); 3491 } 3492 3493 qla2x00_free_irqs(vha); 3494 3495 qla2x00_free_fw_dump(ha); 3496 3497 pci_disable_device(pdev); 3498 ql_log(ql_log_info, vha, 0xfffe, 3499 "Adapter shutdown successfully.\n"); 3500 } 3501 3502 /* Deletes all the virtual ports for a given ha */ 3503 static void 3504 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3505 { 3506 scsi_qla_host_t *vha; 3507 unsigned long flags; 3508 3509 mutex_lock(&ha->vport_lock); 3510 while (ha->cur_vport_count) { 3511 spin_lock_irqsave(&ha->vport_slock, flags); 3512 3513 BUG_ON(base_vha->list.next == &ha->vp_list); 3514 /* This assumes first entry in ha->vp_list is always base vha */ 3515 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3516 scsi_host_get(vha->host); 3517 3518 spin_unlock_irqrestore(&ha->vport_slock, flags); 3519 mutex_unlock(&ha->vport_lock); 3520 3521 fc_vport_terminate(vha->fc_vport); 3522 scsi_host_put(vha->host); 3523 3524 mutex_lock(&ha->vport_lock); 3525 } 3526 mutex_unlock(&ha->vport_lock); 3527 } 3528 3529 /* Stops all deferred work threads */ 3530 static void 3531 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3532 { 3533 /* Cancel all work and destroy DPC workqueues */ 3534 if (ha->dpc_lp_wq) { 3535 cancel_work_sync(&ha->idc_aen); 3536 destroy_workqueue(ha->dpc_lp_wq); 3537 ha->dpc_lp_wq = NULL; 3538 } 3539 3540 if (ha->dpc_hp_wq) { 3541 cancel_work_sync(&ha->nic_core_reset); 3542 cancel_work_sync(&ha->idc_state_handler); 3543 cancel_work_sync(&ha->nic_core_unrecoverable); 3544 destroy_workqueue(ha->dpc_hp_wq); 3545 ha->dpc_hp_wq = NULL; 3546 } 3547 3548 /* Kill the kernel thread for this host */ 3549 if (ha->dpc_thread) { 3550 struct task_struct *t = ha->dpc_thread; 3551 3552 /* 3553 * qla2xxx_wake_dpc checks for ->dpc_thread 3554 * so we need to zero it out. 3555 */ 3556 ha->dpc_thread = NULL; 3557 kthread_stop(t); 3558 } 3559 } 3560 3561 static void 3562 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3563 { 3564 if (IS_QLA82XX(ha)) { 3565 3566 iounmap((device_reg_t *)ha->nx_pcibase); 3567 if (!ql2xdbwr) 3568 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3569 } else { 3570 if (ha->iobase) 3571 iounmap(ha->iobase); 3572 3573 if (ha->cregbase) 3574 iounmap(ha->cregbase); 3575 3576 if (ha->mqiobase) 3577 iounmap(ha->mqiobase); 3578 3579 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3580 iounmap(ha->msixbase); 3581 } 3582 } 3583 3584 static void 3585 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3586 { 3587 if (IS_QLA8044(ha)) { 3588 qla8044_idc_lock(ha); 3589 qla8044_clear_drv_active(ha); 3590 qla8044_idc_unlock(ha); 3591 } else if (IS_QLA82XX(ha)) { 3592 qla82xx_idc_lock(ha); 3593 qla82xx_clear_drv_active(ha); 3594 qla82xx_idc_unlock(ha); 3595 } 3596 } 3597 3598 static void 3599 qla2x00_remove_one(struct pci_dev *pdev) 3600 { 3601 scsi_qla_host_t *base_vha; 3602 struct qla_hw_data *ha; 3603 3604 base_vha = pci_get_drvdata(pdev); 3605 ha = base_vha->hw; 3606 3607 /* Indicate device removal to prevent future board_disable and wait 3608 * until any pending board_disable has completed. */ 3609 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3610 cancel_work_sync(&ha->board_disable); 3611 3612 /* 3613 * If the PCI device is disabled then there was a PCI-disconnect and 3614 * qla2x00_disable_board_on_pci_error has taken care of most of the 3615 * resources. 3616 */ 3617 if (!atomic_read(&pdev->enable_cnt)) { 3618 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3619 base_vha->gnl.l, base_vha->gnl.ldma); 3620 3621 scsi_host_put(base_vha->host); 3622 kfree(ha); 3623 pci_set_drvdata(pdev, NULL); 3624 return; 3625 } 3626 qla2x00_wait_for_hba_ready(base_vha); 3627 3628 qla2x00_wait_for_sess_deletion(base_vha); 3629 3630 /* 3631 * if UNLOAD flag is already set, then continue unload, 3632 * where it was set first. 3633 */ 3634 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3635 return; 3636 3637 set_bit(UNLOADING, &base_vha->dpc_flags); 3638 3639 qla_nvme_delete(base_vha); 3640 3641 dma_free_coherent(&ha->pdev->dev, 3642 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3643 3644 vfree(base_vha->scan.l); 3645 3646 if (IS_QLAFX00(ha)) 3647 qlafx00_driver_shutdown(base_vha, 20); 3648 3649 qla2x00_delete_all_vps(ha, base_vha); 3650 3651 if (IS_QLA8031(ha)) { 3652 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3653 "Clearing fcoe driver presence.\n"); 3654 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3655 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3656 "Error while clearing DRV-Presence.\n"); 3657 } 3658 3659 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3660 3661 qla2x00_dfs_remove(base_vha); 3662 3663 qla84xx_put_chip(base_vha); 3664 3665 /* Disable timer */ 3666 if (base_vha->timer_active) 3667 qla2x00_stop_timer(base_vha); 3668 3669 base_vha->flags.online = 0; 3670 3671 /* free DMA memory */ 3672 if (ha->exlogin_buf) 3673 qla2x00_free_exlogin_buffer(ha); 3674 3675 /* free DMA memory */ 3676 if (ha->exchoffld_buf) 3677 qla2x00_free_exchoffld_buffer(ha); 3678 3679 qla2x00_destroy_deferred_work(ha); 3680 3681 qlt_remove_target(ha, base_vha); 3682 3683 qla2x00_free_sysfs_attr(base_vha, true); 3684 3685 fc_remove_host(base_vha->host); 3686 qlt_remove_target_resources(ha); 3687 3688 scsi_remove_host(base_vha->host); 3689 3690 qla2x00_free_device(base_vha); 3691 3692 qla2x00_clear_drv_active(ha); 3693 3694 scsi_host_put(base_vha->host); 3695 3696 qla2x00_unmap_iobases(ha); 3697 3698 pci_release_selected_regions(ha->pdev, ha->bars); 3699 kfree(ha); 3700 3701 pci_disable_pcie_error_reporting(pdev); 3702 3703 pci_disable_device(pdev); 3704 } 3705 3706 static void 3707 qla2x00_free_device(scsi_qla_host_t *vha) 3708 { 3709 struct qla_hw_data *ha = vha->hw; 3710 3711 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3712 3713 /* Disable timer */ 3714 if (vha->timer_active) 3715 qla2x00_stop_timer(vha); 3716 3717 qla25xx_delete_queues(vha); 3718 3719 if (ha->flags.fce_enabled) 3720 qla2x00_disable_fce_trace(vha, NULL, NULL); 3721 3722 if (ha->eft) 3723 qla2x00_disable_eft_trace(vha); 3724 3725 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3726 if (ha->flags.fw_started) 3727 qla2x00_abort_isp_cleanup(vha); 3728 } else { 3729 if (ha->flags.fw_started) { 3730 /* Stop currently executing firmware. */ 3731 qla2x00_try_to_stop_firmware(vha); 3732 ha->flags.fw_started = 0; 3733 } 3734 } 3735 3736 vha->flags.online = 0; 3737 3738 /* turn-off interrupts on the card */ 3739 if (ha->interrupts_on) { 3740 vha->flags.init_done = 0; 3741 ha->isp_ops->disable_intrs(ha); 3742 } 3743 3744 qla2x00_free_fcports(vha); 3745 3746 qla2x00_free_irqs(vha); 3747 3748 /* Flush the work queue and remove it */ 3749 if (ha->wq) { 3750 flush_workqueue(ha->wq); 3751 destroy_workqueue(ha->wq); 3752 ha->wq = NULL; 3753 } 3754 3755 3756 qla2x00_mem_free(ha); 3757 3758 qla82xx_md_free(vha); 3759 3760 qla2x00_free_queues(ha); 3761 } 3762 3763 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3764 { 3765 fc_port_t *fcport, *tfcport; 3766 3767 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3768 list_del(&fcport->list); 3769 qla2x00_clear_loop_id(fcport); 3770 kfree(fcport); 3771 } 3772 } 3773 3774 static inline void 3775 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3776 int defer) 3777 { 3778 struct fc_rport *rport; 3779 scsi_qla_host_t *base_vha; 3780 unsigned long flags; 3781 3782 if (!fcport->rport) 3783 return; 3784 3785 rport = fcport->rport; 3786 if (defer) { 3787 base_vha = pci_get_drvdata(vha->hw->pdev); 3788 spin_lock_irqsave(vha->host->host_lock, flags); 3789 fcport->drport = rport; 3790 spin_unlock_irqrestore(vha->host->host_lock, flags); 3791 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3792 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3793 qla2xxx_wake_dpc(base_vha); 3794 } else { 3795 int now; 3796 if (rport) { 3797 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3798 "%s %8phN. rport %p roles %x\n", 3799 __func__, fcport->port_name, rport, 3800 rport->roles); 3801 fc_remote_port_delete(rport); 3802 } 3803 qlt_do_generation_tick(vha, &now); 3804 } 3805 } 3806 3807 /* 3808 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3809 * 3810 * Input: ha = adapter block pointer. fcport = port structure pointer. 3811 * 3812 * Return: None. 3813 * 3814 * Context: 3815 */ 3816 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3817 int do_login, int defer) 3818 { 3819 if (IS_QLAFX00(vha->hw)) { 3820 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3821 qla2x00_schedule_rport_del(vha, fcport, defer); 3822 return; 3823 } 3824 3825 if (atomic_read(&fcport->state) == FCS_ONLINE && 3826 vha->vp_idx == fcport->vha->vp_idx) { 3827 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3828 qla2x00_schedule_rport_del(vha, fcport, defer); 3829 } 3830 /* 3831 * We may need to retry the login, so don't change the state of the 3832 * port but do the retries. 3833 */ 3834 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3835 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3836 3837 if (!do_login) 3838 return; 3839 3840 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3841 3842 if (fcport->login_retry == 0) { 3843 fcport->login_retry = vha->hw->login_retry_count; 3844 3845 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3846 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3847 fcport->port_name, fcport->loop_id, fcport->login_retry); 3848 } 3849 } 3850 3851 /* 3852 * qla2x00_mark_all_devices_lost 3853 * Updates fcport state when device goes offline. 3854 * 3855 * Input: 3856 * ha = adapter block pointer. 3857 * fcport = port structure pointer. 3858 * 3859 * Return: 3860 * None. 3861 * 3862 * Context: 3863 */ 3864 void 3865 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3866 { 3867 fc_port_t *fcport; 3868 3869 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3870 "Mark all dev lost\n"); 3871 3872 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3873 fcport->scan_state = 0; 3874 qlt_schedule_sess_for_deletion(fcport); 3875 3876 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3877 continue; 3878 3879 /* 3880 * No point in marking the device as lost, if the device is 3881 * already DEAD. 3882 */ 3883 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3884 continue; 3885 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3886 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3887 if (defer) 3888 qla2x00_schedule_rport_del(vha, fcport, defer); 3889 else if (vha->vp_idx == fcport->vha->vp_idx) 3890 qla2x00_schedule_rport_del(vha, fcport, defer); 3891 } 3892 } 3893 } 3894 3895 /* 3896 * qla2x00_mem_alloc 3897 * Allocates adapter memory. 3898 * 3899 * Returns: 3900 * 0 = success. 3901 * !0 = failure. 3902 */ 3903 static int 3904 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3905 struct req_que **req, struct rsp_que **rsp) 3906 { 3907 char name[16]; 3908 3909 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3910 &ha->init_cb_dma, GFP_KERNEL); 3911 if (!ha->init_cb) 3912 goto fail; 3913 3914 if (qlt_mem_alloc(ha) < 0) 3915 goto fail_free_init_cb; 3916 3917 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3918 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3919 if (!ha->gid_list) 3920 goto fail_free_tgt_mem; 3921 3922 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3923 if (!ha->srb_mempool) 3924 goto fail_free_gid_list; 3925 3926 if (IS_P3P_TYPE(ha)) { 3927 /* Allocate cache for CT6 Ctx. */ 3928 if (!ctx_cachep) { 3929 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3930 sizeof(struct ct6_dsd), 0, 3931 SLAB_HWCACHE_ALIGN, NULL); 3932 if (!ctx_cachep) 3933 goto fail_free_srb_mempool; 3934 } 3935 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3936 ctx_cachep); 3937 if (!ha->ctx_mempool) 3938 goto fail_free_srb_mempool; 3939 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3940 "ctx_cachep=%p ctx_mempool=%p.\n", 3941 ctx_cachep, ha->ctx_mempool); 3942 } 3943 3944 /* Get memory for cached NVRAM */ 3945 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3946 if (!ha->nvram) 3947 goto fail_free_ctx_mempool; 3948 3949 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3950 ha->pdev->device); 3951 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3952 DMA_POOL_SIZE, 8, 0); 3953 if (!ha->s_dma_pool) 3954 goto fail_free_nvram; 3955 3956 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3957 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3958 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3959 3960 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3961 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3962 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3963 if (!ha->dl_dma_pool) { 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3965 "Failed to allocate memory for dl_dma_pool.\n"); 3966 goto fail_s_dma_pool; 3967 } 3968 3969 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3970 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3971 if (!ha->fcp_cmnd_dma_pool) { 3972 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3973 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3974 goto fail_dl_dma_pool; 3975 } 3976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3977 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3978 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3979 } 3980 3981 /* Allocate memory for SNS commands */ 3982 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3983 /* Get consistent memory allocated for SNS commands */ 3984 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3985 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3986 if (!ha->sns_cmd) 3987 goto fail_dma_pool; 3988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3989 "sns_cmd: %p.\n", ha->sns_cmd); 3990 } else { 3991 /* Get consistent memory allocated for MS IOCB */ 3992 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3993 &ha->ms_iocb_dma); 3994 if (!ha->ms_iocb) 3995 goto fail_dma_pool; 3996 /* Get consistent memory allocated for CT SNS commands */ 3997 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3998 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3999 if (!ha->ct_sns) 4000 goto fail_free_ms_iocb; 4001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4002 "ms_iocb=%p ct_sns=%p.\n", 4003 ha->ms_iocb, ha->ct_sns); 4004 } 4005 4006 /* Allocate memory for request ring */ 4007 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4008 if (!*req) { 4009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4010 "Failed to allocate memory for req.\n"); 4011 goto fail_req; 4012 } 4013 (*req)->length = req_len; 4014 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4015 ((*req)->length + 1) * sizeof(request_t), 4016 &(*req)->dma, GFP_KERNEL); 4017 if (!(*req)->ring) { 4018 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4019 "Failed to allocate memory for req_ring.\n"); 4020 goto fail_req_ring; 4021 } 4022 /* Allocate memory for response ring */ 4023 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4024 if (!*rsp) { 4025 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4026 "Failed to allocate memory for rsp.\n"); 4027 goto fail_rsp; 4028 } 4029 (*rsp)->hw = ha; 4030 (*rsp)->length = rsp_len; 4031 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4032 ((*rsp)->length + 1) * sizeof(response_t), 4033 &(*rsp)->dma, GFP_KERNEL); 4034 if (!(*rsp)->ring) { 4035 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4036 "Failed to allocate memory for rsp_ring.\n"); 4037 goto fail_rsp_ring; 4038 } 4039 (*req)->rsp = *rsp; 4040 (*rsp)->req = *req; 4041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4042 "req=%p req->length=%d req->ring=%p rsp=%p " 4043 "rsp->length=%d rsp->ring=%p.\n", 4044 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4045 (*rsp)->ring); 4046 /* Allocate memory for NVRAM data for vports */ 4047 if (ha->nvram_npiv_size) { 4048 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 4049 ha->nvram_npiv_size, GFP_KERNEL); 4050 if (!ha->npiv_info) { 4051 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4052 "Failed to allocate memory for npiv_info.\n"); 4053 goto fail_npiv_info; 4054 } 4055 } else 4056 ha->npiv_info = NULL; 4057 4058 /* Get consistent memory allocated for EX-INIT-CB. */ 4059 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4060 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4061 &ha->ex_init_cb_dma); 4062 if (!ha->ex_init_cb) 4063 goto fail_ex_init_cb; 4064 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4065 "ex_init_cb=%p.\n", ha->ex_init_cb); 4066 } 4067 4068 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4069 4070 /* Get consistent memory allocated for Async Port-Database. */ 4071 if (!IS_FWI2_CAPABLE(ha)) { 4072 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4073 &ha->async_pd_dma); 4074 if (!ha->async_pd) 4075 goto fail_async_pd; 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4077 "async_pd=%p.\n", ha->async_pd); 4078 } 4079 4080 INIT_LIST_HEAD(&ha->vp_list); 4081 4082 /* Allocate memory for our loop_id bitmap */ 4083 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 4084 GFP_KERNEL); 4085 if (!ha->loop_id_map) 4086 goto fail_loop_id_map; 4087 else { 4088 qla2x00_set_reserved_loop_ids(ha); 4089 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4090 "loop_id_map=%p.\n", ha->loop_id_map); 4091 } 4092 4093 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4094 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4095 if (!ha->sfp_data) { 4096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4097 "Unable to allocate memory for SFP read-data.\n"); 4098 goto fail_sfp_data; 4099 } 4100 4101 return 0; 4102 4103 fail_sfp_data: 4104 kfree(ha->loop_id_map); 4105 fail_loop_id_map: 4106 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4107 fail_async_pd: 4108 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4109 fail_ex_init_cb: 4110 kfree(ha->npiv_info); 4111 fail_npiv_info: 4112 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4113 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4114 (*rsp)->ring = NULL; 4115 (*rsp)->dma = 0; 4116 fail_rsp_ring: 4117 kfree(*rsp); 4118 fail_rsp: 4119 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4120 sizeof(request_t), (*req)->ring, (*req)->dma); 4121 (*req)->ring = NULL; 4122 (*req)->dma = 0; 4123 fail_req_ring: 4124 kfree(*req); 4125 fail_req: 4126 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4127 ha->ct_sns, ha->ct_sns_dma); 4128 ha->ct_sns = NULL; 4129 ha->ct_sns_dma = 0; 4130 fail_free_ms_iocb: 4131 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4132 ha->ms_iocb = NULL; 4133 ha->ms_iocb_dma = 0; 4134 4135 if (ha->sns_cmd) 4136 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4137 ha->sns_cmd, ha->sns_cmd_dma); 4138 fail_dma_pool: 4139 if (IS_QLA82XX(ha) || ql2xenabledif) { 4140 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4141 ha->fcp_cmnd_dma_pool = NULL; 4142 } 4143 fail_dl_dma_pool: 4144 if (IS_QLA82XX(ha) || ql2xenabledif) { 4145 dma_pool_destroy(ha->dl_dma_pool); 4146 ha->dl_dma_pool = NULL; 4147 } 4148 fail_s_dma_pool: 4149 dma_pool_destroy(ha->s_dma_pool); 4150 ha->s_dma_pool = NULL; 4151 fail_free_nvram: 4152 kfree(ha->nvram); 4153 ha->nvram = NULL; 4154 fail_free_ctx_mempool: 4155 if (ha->ctx_mempool) 4156 mempool_destroy(ha->ctx_mempool); 4157 ha->ctx_mempool = NULL; 4158 fail_free_srb_mempool: 4159 if (ha->srb_mempool) 4160 mempool_destroy(ha->srb_mempool); 4161 ha->srb_mempool = NULL; 4162 fail_free_gid_list: 4163 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4164 ha->gid_list, 4165 ha->gid_list_dma); 4166 ha->gid_list = NULL; 4167 ha->gid_list_dma = 0; 4168 fail_free_tgt_mem: 4169 qlt_mem_free(ha); 4170 fail_free_init_cb: 4171 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4172 ha->init_cb_dma); 4173 ha->init_cb = NULL; 4174 ha->init_cb_dma = 0; 4175 fail: 4176 ql_log(ql_log_fatal, NULL, 0x0030, 4177 "Memory allocation failure.\n"); 4178 return -ENOMEM; 4179 } 4180 4181 int 4182 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4183 { 4184 int rval; 4185 uint16_t size, max_cnt, temp; 4186 struct qla_hw_data *ha = vha->hw; 4187 4188 /* Return if we don't need to alloacate any extended logins */ 4189 if (!ql2xexlogins) 4190 return QLA_SUCCESS; 4191 4192 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4193 return QLA_SUCCESS; 4194 4195 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4196 max_cnt = 0; 4197 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4198 if (rval != QLA_SUCCESS) { 4199 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4200 "Failed to get exlogin status.\n"); 4201 return rval; 4202 } 4203 4204 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4205 temp *= size; 4206 4207 if (temp != ha->exlogin_size) { 4208 qla2x00_free_exlogin_buffer(ha); 4209 ha->exlogin_size = temp; 4210 4211 ql_log(ql_log_info, vha, 0xd024, 4212 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4213 max_cnt, size, temp); 4214 4215 ql_log(ql_log_info, vha, 0xd025, 4216 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4217 4218 /* Get consistent memory for extended logins */ 4219 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4220 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4221 if (!ha->exlogin_buf) { 4222 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4223 "Failed to allocate memory for exlogin_buf_dma.\n"); 4224 return -ENOMEM; 4225 } 4226 } 4227 4228 /* Now configure the dma buffer */ 4229 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4230 if (rval) { 4231 ql_log(ql_log_fatal, vha, 0xd033, 4232 "Setup extended login buffer ****FAILED****.\n"); 4233 qla2x00_free_exlogin_buffer(ha); 4234 } 4235 4236 return rval; 4237 } 4238 4239 /* 4240 * qla2x00_free_exlogin_buffer 4241 * 4242 * Input: 4243 * ha = adapter block pointer 4244 */ 4245 void 4246 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4247 { 4248 if (ha->exlogin_buf) { 4249 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4250 ha->exlogin_buf, ha->exlogin_buf_dma); 4251 ha->exlogin_buf = NULL; 4252 ha->exlogin_size = 0; 4253 } 4254 } 4255 4256 static void 4257 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4258 { 4259 u32 temp; 4260 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4261 4262 if (max_cnt > vha->hw->max_exchg) 4263 max_cnt = vha->hw->max_exchg; 4264 4265 if (qla_ini_mode_enabled(vha)) { 4266 if (ql2xiniexchg > max_cnt) 4267 ql2xiniexchg = max_cnt; 4268 4269 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4270 *ret_cnt = ql2xiniexchg; 4271 } else if (qla_tgt_mode_enabled(vha)) { 4272 if (ql2xexchoffld > max_cnt) 4273 ql2xexchoffld = max_cnt; 4274 4275 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4276 *ret_cnt = ql2xexchoffld; 4277 } else if (qla_dual_mode_enabled(vha)) { 4278 temp = ql2xiniexchg + ql2xexchoffld; 4279 if (temp > max_cnt) { 4280 ql2xiniexchg -= (temp - max_cnt)/2; 4281 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4282 temp = max_cnt; 4283 } 4284 4285 if (temp > FW_DEF_EXCHANGES_CNT) 4286 *ret_cnt = temp; 4287 } 4288 } 4289 4290 int 4291 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4292 { 4293 int rval; 4294 u16 size, max_cnt; 4295 u32 actual_cnt, totsz; 4296 struct qla_hw_data *ha = vha->hw; 4297 4298 if (!ha->flags.exchoffld_enabled) 4299 return QLA_SUCCESS; 4300 4301 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4302 return QLA_SUCCESS; 4303 4304 max_cnt = 0; 4305 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4306 if (rval != QLA_SUCCESS) { 4307 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4308 "Failed to get exlogin status.\n"); 4309 return rval; 4310 } 4311 4312 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4313 ql_log(ql_log_info, vha, 0xd014, 4314 "Actual exchange offload count: %d.\n", actual_cnt); 4315 4316 totsz = actual_cnt * size; 4317 4318 if (totsz != ha->exchoffld_size) { 4319 qla2x00_free_exchoffld_buffer(ha); 4320 ha->exchoffld_size = totsz; 4321 4322 ql_log(ql_log_info, vha, 0xd016, 4323 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4324 max_cnt, actual_cnt, size, totsz); 4325 4326 ql_log(ql_log_info, vha, 0xd017, 4327 "Exchange Buffers requested size = 0x%x\n", 4328 ha->exchoffld_size); 4329 4330 /* Get consistent memory for extended logins */ 4331 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4332 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4333 if (!ha->exchoffld_buf) { 4334 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4335 "Failed to allocate memory for Exchange Offload.\n"); 4336 4337 if (ha->max_exchg > 4338 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4339 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4340 } else if (ha->max_exchg > 4341 (FW_DEF_EXCHANGES_CNT + 512)) { 4342 ha->max_exchg -= 512; 4343 } else { 4344 ha->flags.exchoffld_enabled = 0; 4345 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4346 "Disabling Exchange offload due to lack of memory\n"); 4347 } 4348 ha->exchoffld_size = 0; 4349 4350 return -ENOMEM; 4351 } 4352 } 4353 4354 /* Now configure the dma buffer */ 4355 rval = qla_set_exchoffld_mem_cfg(vha); 4356 if (rval) { 4357 ql_log(ql_log_fatal, vha, 0xd02e, 4358 "Setup exchange offload buffer ****FAILED****.\n"); 4359 qla2x00_free_exchoffld_buffer(ha); 4360 } else { 4361 /* re-adjust number of target exchange */ 4362 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4363 4364 if (qla_ini_mode_enabled(vha)) 4365 icb->exchange_count = 0; 4366 else 4367 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4368 } 4369 4370 return rval; 4371 } 4372 4373 /* 4374 * qla2x00_free_exchoffld_buffer 4375 * 4376 * Input: 4377 * ha = adapter block pointer 4378 */ 4379 void 4380 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4381 { 4382 if (ha->exchoffld_buf) { 4383 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4384 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4385 ha->exchoffld_buf = NULL; 4386 ha->exchoffld_size = 0; 4387 } 4388 } 4389 4390 /* 4391 * qla2x00_free_fw_dump 4392 * Frees fw dump stuff. 4393 * 4394 * Input: 4395 * ha = adapter block pointer 4396 */ 4397 static void 4398 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4399 { 4400 if (ha->fce) 4401 dma_free_coherent(&ha->pdev->dev, 4402 FCE_SIZE, ha->fce, ha->fce_dma); 4403 4404 if (ha->eft) 4405 dma_free_coherent(&ha->pdev->dev, 4406 EFT_SIZE, ha->eft, ha->eft_dma); 4407 4408 if (ha->fw_dump) 4409 vfree(ha->fw_dump); 4410 if (ha->fw_dump_template) 4411 vfree(ha->fw_dump_template); 4412 4413 ha->fce = NULL; 4414 ha->fce_dma = 0; 4415 ha->eft = NULL; 4416 ha->eft_dma = 0; 4417 ha->fw_dumped = 0; 4418 ha->fw_dump_cap_flags = 0; 4419 ha->fw_dump_reading = 0; 4420 ha->fw_dump = NULL; 4421 ha->fw_dump_len = 0; 4422 ha->fw_dump_template = NULL; 4423 ha->fw_dump_template_len = 0; 4424 } 4425 4426 /* 4427 * qla2x00_mem_free 4428 * Frees all adapter allocated memory. 4429 * 4430 * Input: 4431 * ha = adapter block pointer. 4432 */ 4433 static void 4434 qla2x00_mem_free(struct qla_hw_data *ha) 4435 { 4436 qla2x00_free_fw_dump(ha); 4437 4438 if (ha->mctp_dump) 4439 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4440 ha->mctp_dump_dma); 4441 4442 if (ha->srb_mempool) 4443 mempool_destroy(ha->srb_mempool); 4444 4445 if (ha->dcbx_tlv) 4446 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4447 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4448 4449 if (ha->xgmac_data) 4450 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4451 ha->xgmac_data, ha->xgmac_data_dma); 4452 4453 if (ha->sns_cmd) 4454 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4455 ha->sns_cmd, ha->sns_cmd_dma); 4456 4457 if (ha->ct_sns) 4458 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4459 ha->ct_sns, ha->ct_sns_dma); 4460 4461 if (ha->sfp_data) 4462 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4463 ha->sfp_data_dma); 4464 4465 if (ha->ms_iocb) 4466 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4467 4468 if (ha->ex_init_cb) 4469 dma_pool_free(ha->s_dma_pool, 4470 ha->ex_init_cb, ha->ex_init_cb_dma); 4471 4472 if (ha->async_pd) 4473 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4474 4475 if (ha->s_dma_pool) 4476 dma_pool_destroy(ha->s_dma_pool); 4477 4478 if (ha->gid_list) 4479 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4480 ha->gid_list, ha->gid_list_dma); 4481 4482 if (IS_QLA82XX(ha)) { 4483 if (!list_empty(&ha->gbl_dsd_list)) { 4484 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4485 4486 /* clean up allocated prev pool */ 4487 list_for_each_entry_safe(dsd_ptr, 4488 tdsd_ptr, &ha->gbl_dsd_list, list) { 4489 dma_pool_free(ha->dl_dma_pool, 4490 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4491 list_del(&dsd_ptr->list); 4492 kfree(dsd_ptr); 4493 } 4494 } 4495 } 4496 4497 if (ha->dl_dma_pool) 4498 dma_pool_destroy(ha->dl_dma_pool); 4499 4500 if (ha->fcp_cmnd_dma_pool) 4501 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4502 4503 if (ha->ctx_mempool) 4504 mempool_destroy(ha->ctx_mempool); 4505 4506 qlt_mem_free(ha); 4507 4508 if (ha->init_cb) 4509 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4510 ha->init_cb, ha->init_cb_dma); 4511 4512 if (ha->optrom_buffer) 4513 vfree(ha->optrom_buffer); 4514 if (ha->nvram) 4515 kfree(ha->nvram); 4516 if (ha->npiv_info) 4517 kfree(ha->npiv_info); 4518 if (ha->swl) 4519 kfree(ha->swl); 4520 if (ha->loop_id_map) 4521 kfree(ha->loop_id_map); 4522 4523 ha->srb_mempool = NULL; 4524 ha->ctx_mempool = NULL; 4525 ha->sns_cmd = NULL; 4526 ha->sns_cmd_dma = 0; 4527 ha->ct_sns = NULL; 4528 ha->ct_sns_dma = 0; 4529 ha->ms_iocb = NULL; 4530 ha->ms_iocb_dma = 0; 4531 ha->init_cb = NULL; 4532 ha->init_cb_dma = 0; 4533 ha->ex_init_cb = NULL; 4534 ha->ex_init_cb_dma = 0; 4535 ha->async_pd = NULL; 4536 ha->async_pd_dma = 0; 4537 ha->loop_id_map = NULL; 4538 ha->npiv_info = NULL; 4539 ha->optrom_buffer = NULL; 4540 ha->swl = NULL; 4541 ha->nvram = NULL; 4542 ha->mctp_dump = NULL; 4543 ha->dcbx_tlv = NULL; 4544 ha->xgmac_data = NULL; 4545 ha->sfp_data = NULL; 4546 4547 ha->s_dma_pool = NULL; 4548 ha->dl_dma_pool = NULL; 4549 ha->fcp_cmnd_dma_pool = NULL; 4550 4551 ha->gid_list = NULL; 4552 ha->gid_list_dma = 0; 4553 4554 ha->tgt.atio_ring = NULL; 4555 ha->tgt.atio_dma = 0; 4556 ha->tgt.tgt_vp_map = NULL; 4557 } 4558 4559 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4560 struct qla_hw_data *ha) 4561 { 4562 struct Scsi_Host *host; 4563 struct scsi_qla_host *vha = NULL; 4564 4565 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4566 if (!host) { 4567 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4568 "Failed to allocate host from the scsi layer, aborting.\n"); 4569 return NULL; 4570 } 4571 4572 /* Clear our data area */ 4573 vha = shost_priv(host); 4574 memset(vha, 0, sizeof(scsi_qla_host_t)); 4575 4576 vha->host = host; 4577 vha->host_no = host->host_no; 4578 vha->hw = ha; 4579 4580 INIT_LIST_HEAD(&vha->vp_fcports); 4581 INIT_LIST_HEAD(&vha->work_list); 4582 INIT_LIST_HEAD(&vha->list); 4583 INIT_LIST_HEAD(&vha->qla_cmd_list); 4584 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4585 INIT_LIST_HEAD(&vha->logo_list); 4586 INIT_LIST_HEAD(&vha->plogi_ack_list); 4587 INIT_LIST_HEAD(&vha->qp_list); 4588 INIT_LIST_HEAD(&vha->gnl.fcports); 4589 INIT_LIST_HEAD(&vha->nvme_rport_list); 4590 INIT_LIST_HEAD(&vha->gpnid_list); 4591 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4592 4593 spin_lock_init(&vha->work_lock); 4594 spin_lock_init(&vha->cmd_list_lock); 4595 spin_lock_init(&vha->gnl.fcports_lock); 4596 init_waitqueue_head(&vha->fcport_waitQ); 4597 init_waitqueue_head(&vha->vref_waitq); 4598 4599 vha->gnl.size = sizeof(struct get_name_list_extended) * 4600 (ha->max_loop_id + 1); 4601 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4602 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4603 if (!vha->gnl.l) { 4604 ql_log(ql_log_fatal, vha, 0xd04a, 4605 "Alloc failed for name list.\n"); 4606 scsi_remove_host(vha->host); 4607 return NULL; 4608 } 4609 4610 /* todo: what about ext login? */ 4611 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4612 vha->scan.l = vmalloc(vha->scan.size); 4613 if (!vha->scan.l) { 4614 ql_log(ql_log_fatal, vha, 0xd04a, 4615 "Alloc failed for scan database.\n"); 4616 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4617 vha->gnl.l, vha->gnl.ldma); 4618 scsi_remove_host(vha->host); 4619 return NULL; 4620 } 4621 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4622 4623 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4624 ql_dbg(ql_dbg_init, vha, 0x0041, 4625 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4626 vha->host, vha->hw, vha, 4627 dev_name(&(ha->pdev->dev))); 4628 4629 return vha; 4630 } 4631 4632 struct qla_work_evt * 4633 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4634 { 4635 struct qla_work_evt *e; 4636 uint8_t bail; 4637 4638 QLA_VHA_MARK_BUSY(vha, bail); 4639 if (bail) 4640 return NULL; 4641 4642 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4643 if (!e) { 4644 QLA_VHA_MARK_NOT_BUSY(vha); 4645 return NULL; 4646 } 4647 4648 INIT_LIST_HEAD(&e->list); 4649 e->type = type; 4650 e->flags = QLA_EVT_FLAG_FREE; 4651 return e; 4652 } 4653 4654 int 4655 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4656 { 4657 unsigned long flags; 4658 bool q = false; 4659 4660 spin_lock_irqsave(&vha->work_lock, flags); 4661 list_add_tail(&e->list, &vha->work_list); 4662 4663 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4664 q = true; 4665 4666 spin_unlock_irqrestore(&vha->work_lock, flags); 4667 4668 if (q) 4669 queue_work(vha->hw->wq, &vha->iocb_work); 4670 4671 return QLA_SUCCESS; 4672 } 4673 4674 int 4675 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4676 u32 data) 4677 { 4678 struct qla_work_evt *e; 4679 4680 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4681 if (!e) 4682 return QLA_FUNCTION_FAILED; 4683 4684 e->u.aen.code = code; 4685 e->u.aen.data = data; 4686 return qla2x00_post_work(vha, e); 4687 } 4688 4689 int 4690 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4691 { 4692 struct qla_work_evt *e; 4693 4694 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4695 if (!e) 4696 return QLA_FUNCTION_FAILED; 4697 4698 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4699 return qla2x00_post_work(vha, e); 4700 } 4701 4702 #define qla2x00_post_async_work(name, type) \ 4703 int qla2x00_post_async_##name##_work( \ 4704 struct scsi_qla_host *vha, \ 4705 fc_port_t *fcport, uint16_t *data) \ 4706 { \ 4707 struct qla_work_evt *e; \ 4708 \ 4709 e = qla2x00_alloc_work(vha, type); \ 4710 if (!e) \ 4711 return QLA_FUNCTION_FAILED; \ 4712 \ 4713 e->u.logio.fcport = fcport; \ 4714 if (data) { \ 4715 e->u.logio.data[0] = data[0]; \ 4716 e->u.logio.data[1] = data[1]; \ 4717 } \ 4718 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4719 return qla2x00_post_work(vha, e); \ 4720 } 4721 4722 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4723 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4724 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4725 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4726 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4727 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4728 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4729 4730 int 4731 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4732 { 4733 struct qla_work_evt *e; 4734 4735 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4736 if (!e) 4737 return QLA_FUNCTION_FAILED; 4738 4739 e->u.uevent.code = code; 4740 return qla2x00_post_work(vha, e); 4741 } 4742 4743 static void 4744 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4745 { 4746 char event_string[40]; 4747 char *envp[] = { event_string, NULL }; 4748 4749 switch (code) { 4750 case QLA_UEVENT_CODE_FW_DUMP: 4751 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4752 vha->host_no); 4753 break; 4754 default: 4755 /* do nothing */ 4756 break; 4757 } 4758 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4759 } 4760 4761 int 4762 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4763 uint32_t *data, int cnt) 4764 { 4765 struct qla_work_evt *e; 4766 4767 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4768 if (!e) 4769 return QLA_FUNCTION_FAILED; 4770 4771 e->u.aenfx.evtcode = evtcode; 4772 e->u.aenfx.count = cnt; 4773 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4774 return qla2x00_post_work(vha, e); 4775 } 4776 4777 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4778 { 4779 struct qla_work_evt *e; 4780 4781 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4782 if (!e) 4783 return QLA_FUNCTION_FAILED; 4784 4785 e->u.fcport.fcport = fcport; 4786 return qla2x00_post_work(vha, e); 4787 } 4788 4789 static 4790 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4791 { 4792 unsigned long flags; 4793 fc_port_t *fcport = NULL, *tfcp; 4794 struct qlt_plogi_ack_t *pla = 4795 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4796 uint8_t free_fcport = 0; 4797 u64 wwn; 4798 4799 ql_dbg(ql_dbg_disc, vha, 0xffff, 4800 "%s %d %8phC enter\n", 4801 __func__, __LINE__, e->u.new_sess.port_name); 4802 4803 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4804 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4805 if (fcport) { 4806 fcport->d_id = e->u.new_sess.id; 4807 if (pla) { 4808 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4809 memcpy(fcport->node_name, 4810 pla->iocb.u.isp24.u.plogi.node_name, 4811 WWN_SIZE); 4812 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4813 /* we took an extra ref_count to prevent PLOGI ACK when 4814 * fcport/sess has not been created. 4815 */ 4816 pla->ref_count--; 4817 } 4818 } else { 4819 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4820 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4821 if (fcport) { 4822 fcport->d_id = e->u.new_sess.id; 4823 fcport->flags |= FCF_FABRIC_DEVICE; 4824 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4825 if (e->u.new_sess.fc4_type == FC4_TYPE_FCP_SCSI) { 4826 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4827 } else if (e->u.new_sess.fc4_type == FC4_TYPE_NVME) { 4828 fcport->fc4_type = FC4_TYPE_OTHER; 4829 fcport->fc4f_nvme = FC4_TYPE_NVME; 4830 } 4831 memcpy(fcport->port_name, e->u.new_sess.port_name, 4832 WWN_SIZE); 4833 } else { 4834 ql_dbg(ql_dbg_disc, vha, 0xffff, 4835 "%s %8phC mem alloc fail.\n", 4836 __func__, e->u.new_sess.port_name); 4837 4838 if (pla) 4839 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4840 return; 4841 } 4842 4843 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4844 /* search again to make sure no one else got ahead */ 4845 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4846 e->u.new_sess.port_name, 1); 4847 if (tfcp) { 4848 /* should rarily happen */ 4849 ql_dbg(ql_dbg_disc, vha, 0xffff, 4850 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4851 __func__, tfcp->port_name, tfcp->disc_state, 4852 tfcp->fw_login_state); 4853 4854 free_fcport = 1; 4855 } else { 4856 list_add_tail(&fcport->list, &vha->vp_fcports); 4857 4858 } 4859 if (pla) { 4860 qlt_plogi_ack_link(vha, pla, fcport, 4861 QLT_PLOGI_LINK_SAME_WWN); 4862 pla->ref_count--; 4863 } 4864 } 4865 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4866 4867 if (fcport) { 4868 if (N2N_TOPO(vha->hw)) 4869 fcport->flags &= ~FCF_FABRIC_DEVICE; 4870 4871 fcport->id_changed = 1; 4872 fcport->scan_state = QLA_FCPORT_FOUND; 4873 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4874 4875 if (pla) { 4876 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4877 u16 wd3_lo; 4878 4879 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4880 fcport->local = 0; 4881 fcport->loop_id = 4882 le16_to_cpu( 4883 pla->iocb.u.isp24.nport_handle); 4884 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4885 wd3_lo = 4886 le16_to_cpu( 4887 pla->iocb.u.isp24.u.prli.wd3_lo); 4888 4889 if (wd3_lo & BIT_7) 4890 fcport->conf_compl_supported = 1; 4891 4892 if ((wd3_lo & BIT_4) == 0) 4893 fcport->port_type = FCT_INITIATOR; 4894 else 4895 fcport->port_type = FCT_TARGET; 4896 } 4897 qlt_plogi_ack_unref(vha, pla); 4898 } else { 4899 fc_port_t *dfcp = NULL; 4900 4901 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4902 tfcp = qla2x00_find_fcport_by_nportid(vha, 4903 &e->u.new_sess.id, 1); 4904 if (tfcp && (tfcp != fcport)) { 4905 /* 4906 * We have a conflict fcport with same NportID. 4907 */ 4908 ql_dbg(ql_dbg_disc, vha, 0xffff, 4909 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4910 __func__, tfcp->port_name, tfcp->disc_state, 4911 tfcp->fw_login_state); 4912 4913 switch (tfcp->disc_state) { 4914 case DSC_DELETED: 4915 break; 4916 case DSC_DELETE_PEND: 4917 fcport->login_pause = 1; 4918 tfcp->conflict = fcport; 4919 break; 4920 default: 4921 fcport->login_pause = 1; 4922 tfcp->conflict = fcport; 4923 dfcp = tfcp; 4924 break; 4925 } 4926 } 4927 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4928 if (dfcp) 4929 qlt_schedule_sess_for_deletion(tfcp); 4930 4931 wwn = wwn_to_u64(fcport->node_name); 4932 4933 if (!wwn) 4934 qla24xx_async_gnnid(vha, fcport); 4935 else 4936 qla24xx_async_gnl(vha, fcport); 4937 } 4938 } 4939 4940 if (free_fcport) { 4941 qla2x00_free_fcport(fcport); 4942 if (pla) 4943 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4944 } 4945 } 4946 4947 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4948 { 4949 struct srb *sp = e->u.iosb.sp; 4950 int rval; 4951 4952 rval = qla2x00_start_sp(sp); 4953 if (rval != QLA_SUCCESS) { 4954 ql_dbg(ql_dbg_disc, vha, 0x2043, 4955 "%s: %s: Re-issue IOCB failed (%d).\n", 4956 __func__, sp->name, rval); 4957 qla24xx_sp_unmap(vha, sp); 4958 } 4959 } 4960 4961 void 4962 qla2x00_do_work(struct scsi_qla_host *vha) 4963 { 4964 struct qla_work_evt *e, *tmp; 4965 unsigned long flags; 4966 LIST_HEAD(work); 4967 4968 spin_lock_irqsave(&vha->work_lock, flags); 4969 list_splice_init(&vha->work_list, &work); 4970 spin_unlock_irqrestore(&vha->work_lock, flags); 4971 4972 list_for_each_entry_safe(e, tmp, &work, list) { 4973 list_del_init(&e->list); 4974 4975 switch (e->type) { 4976 case QLA_EVT_AEN: 4977 fc_host_post_event(vha->host, fc_get_event_number(), 4978 e->u.aen.code, e->u.aen.data); 4979 break; 4980 case QLA_EVT_IDC_ACK: 4981 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4982 break; 4983 case QLA_EVT_ASYNC_LOGIN: 4984 qla2x00_async_login(vha, e->u.logio.fcport, 4985 e->u.logio.data); 4986 break; 4987 case QLA_EVT_ASYNC_LOGOUT: 4988 qla2x00_async_logout(vha, e->u.logio.fcport); 4989 break; 4990 case QLA_EVT_ASYNC_LOGOUT_DONE: 4991 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4992 e->u.logio.data); 4993 break; 4994 case QLA_EVT_ASYNC_ADISC: 4995 qla2x00_async_adisc(vha, e->u.logio.fcport, 4996 e->u.logio.data); 4997 break; 4998 case QLA_EVT_ASYNC_ADISC_DONE: 4999 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 5000 e->u.logio.data); 5001 break; 5002 case QLA_EVT_UEVENT: 5003 qla2x00_uevent_emit(vha, e->u.uevent.code); 5004 break; 5005 case QLA_EVT_AENFX: 5006 qlafx00_process_aen(vha, e); 5007 break; 5008 case QLA_EVT_GIDPN: 5009 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 5010 break; 5011 case QLA_EVT_GPNID: 5012 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5013 break; 5014 case QLA_EVT_UNMAP: 5015 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5016 break; 5017 case QLA_EVT_RELOGIN: 5018 qla2x00_relogin(vha); 5019 break; 5020 case QLA_EVT_NEW_SESS: 5021 qla24xx_create_new_sess(vha, e); 5022 break; 5023 case QLA_EVT_GPDB: 5024 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5025 e->u.fcport.opt); 5026 break; 5027 case QLA_EVT_PRLI: 5028 qla24xx_async_prli(vha, e->u.fcport.fcport); 5029 break; 5030 case QLA_EVT_GPSC: 5031 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5032 break; 5033 case QLA_EVT_UPD_FCPORT: 5034 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5035 break; 5036 case QLA_EVT_GNL: 5037 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5038 break; 5039 case QLA_EVT_NACK: 5040 qla24xx_do_nack_work(vha, e); 5041 break; 5042 case QLA_EVT_ASYNC_PRLO: 5043 qla2x00_async_prlo(vha, e->u.logio.fcport); 5044 break; 5045 case QLA_EVT_ASYNC_PRLO_DONE: 5046 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5047 e->u.logio.data); 5048 break; 5049 case QLA_EVT_GPNFT: 5050 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type); 5051 break; 5052 case QLA_EVT_GPNFT_DONE: 5053 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5054 break; 5055 case QLA_EVT_GNNFT_DONE: 5056 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5057 break; 5058 case QLA_EVT_GNNID: 5059 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5060 break; 5061 case QLA_EVT_GFPNID: 5062 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5063 break; 5064 case QLA_EVT_SP_RETRY: 5065 qla_sp_retry(vha, e); 5066 } 5067 if (e->flags & QLA_EVT_FLAG_FREE) 5068 kfree(e); 5069 5070 /* For each work completed decrement vha ref count */ 5071 QLA_VHA_MARK_NOT_BUSY(vha); 5072 } 5073 } 5074 5075 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5076 { 5077 struct qla_work_evt *e; 5078 5079 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5080 5081 if (!e) { 5082 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5083 return QLA_FUNCTION_FAILED; 5084 } 5085 5086 return qla2x00_post_work(vha, e); 5087 } 5088 5089 /* Relogins all the fcports of a vport 5090 * Context: dpc thread 5091 */ 5092 void qla2x00_relogin(struct scsi_qla_host *vha) 5093 { 5094 fc_port_t *fcport; 5095 int status; 5096 struct event_arg ea; 5097 5098 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5099 /* 5100 * If the port is not ONLINE then try to login 5101 * to it if we haven't run out of retries. 5102 */ 5103 if (atomic_read(&fcport->state) != FCS_ONLINE && 5104 fcport->login_retry && 5105 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) { 5106 if (vha->hw->current_topology != ISP_CFG_NL) { 5107 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 5108 "%s %8phC DS %d LS %d\n", __func__, 5109 fcport->port_name, fcport->disc_state, 5110 fcport->fw_login_state); 5111 memset(&ea, 0, sizeof(ea)); 5112 ea.event = FCME_RELOGIN; 5113 ea.fcport = fcport; 5114 qla2x00_fcport_event_handler(vha, &ea); 5115 } else if (vha->hw->current_topology == ISP_CFG_NL) { 5116 fcport->login_retry--; 5117 status = qla2x00_local_device_login(vha, 5118 fcport); 5119 if (status == QLA_SUCCESS) { 5120 fcport->old_loop_id = fcport->loop_id; 5121 ql_dbg(ql_dbg_disc, vha, 0x2003, 5122 "Port login OK: logged in ID 0x%x.\n", 5123 fcport->loop_id); 5124 qla2x00_update_fcport(vha, fcport); 5125 } else if (status == 1) { 5126 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5127 /* retry the login again */ 5128 ql_dbg(ql_dbg_disc, vha, 0x2007, 5129 "Retrying %d login again loop_id 0x%x.\n", 5130 fcport->login_retry, 5131 fcport->loop_id); 5132 } else { 5133 fcport->login_retry = 0; 5134 } 5135 5136 if (fcport->login_retry == 0 && 5137 status != QLA_SUCCESS) 5138 qla2x00_clear_loop_id(fcport); 5139 } 5140 } 5141 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5142 break; 5143 } 5144 5145 ql_dbg(ql_dbg_disc, vha, 0x400e, 5146 "Relogin end.\n"); 5147 } 5148 5149 /* Schedule work on any of the dpc-workqueues */ 5150 void 5151 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5152 { 5153 struct qla_hw_data *ha = base_vha->hw; 5154 5155 switch (work_code) { 5156 case MBA_IDC_AEN: /* 0x8200 */ 5157 if (ha->dpc_lp_wq) 5158 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5159 break; 5160 5161 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5162 if (!ha->flags.nic_core_reset_hdlr_active) { 5163 if (ha->dpc_hp_wq) 5164 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5165 } else 5166 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5167 "NIC Core reset is already active. Skip " 5168 "scheduling it again.\n"); 5169 break; 5170 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5171 if (ha->dpc_hp_wq) 5172 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5173 break; 5174 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5175 if (ha->dpc_hp_wq) 5176 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5177 break; 5178 default: 5179 ql_log(ql_log_warn, base_vha, 0xb05f, 5180 "Unknown work-code=0x%x.\n", work_code); 5181 } 5182 5183 return; 5184 } 5185 5186 /* Work: Perform NIC Core Unrecoverable state handling */ 5187 void 5188 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5189 { 5190 struct qla_hw_data *ha = 5191 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5193 uint32_t dev_state = 0; 5194 5195 qla83xx_idc_lock(base_vha, 0); 5196 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5197 qla83xx_reset_ownership(base_vha); 5198 if (ha->flags.nic_core_reset_owner) { 5199 ha->flags.nic_core_reset_owner = 0; 5200 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5201 QLA8XXX_DEV_FAILED); 5202 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5203 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5204 } 5205 qla83xx_idc_unlock(base_vha, 0); 5206 } 5207 5208 /* Work: Execute IDC state handler */ 5209 void 5210 qla83xx_idc_state_handler_work(struct work_struct *work) 5211 { 5212 struct qla_hw_data *ha = 5213 container_of(work, struct qla_hw_data, idc_state_handler); 5214 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5215 uint32_t dev_state = 0; 5216 5217 qla83xx_idc_lock(base_vha, 0); 5218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5219 if (dev_state == QLA8XXX_DEV_FAILED || 5220 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5221 qla83xx_idc_state_handler(base_vha); 5222 qla83xx_idc_unlock(base_vha, 0); 5223 } 5224 5225 static int 5226 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5227 { 5228 int rval = QLA_SUCCESS; 5229 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5230 uint32_t heart_beat_counter1, heart_beat_counter2; 5231 5232 do { 5233 if (time_after(jiffies, heart_beat_wait)) { 5234 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5235 "Nic Core f/w is not alive.\n"); 5236 rval = QLA_FUNCTION_FAILED; 5237 break; 5238 } 5239 5240 qla83xx_idc_lock(base_vha, 0); 5241 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5242 &heart_beat_counter1); 5243 qla83xx_idc_unlock(base_vha, 0); 5244 msleep(100); 5245 qla83xx_idc_lock(base_vha, 0); 5246 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5247 &heart_beat_counter2); 5248 qla83xx_idc_unlock(base_vha, 0); 5249 } while (heart_beat_counter1 == heart_beat_counter2); 5250 5251 return rval; 5252 } 5253 5254 /* Work: Perform NIC Core Reset handling */ 5255 void 5256 qla83xx_nic_core_reset_work(struct work_struct *work) 5257 { 5258 struct qla_hw_data *ha = 5259 container_of(work, struct qla_hw_data, nic_core_reset); 5260 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5261 uint32_t dev_state = 0; 5262 5263 if (IS_QLA2031(ha)) { 5264 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5265 ql_log(ql_log_warn, base_vha, 0xb081, 5266 "Failed to dump mctp\n"); 5267 return; 5268 } 5269 5270 if (!ha->flags.nic_core_reset_hdlr_active) { 5271 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5272 qla83xx_idc_lock(base_vha, 0); 5273 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5274 &dev_state); 5275 qla83xx_idc_unlock(base_vha, 0); 5276 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5277 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5278 "Nic Core f/w is alive.\n"); 5279 return; 5280 } 5281 } 5282 5283 ha->flags.nic_core_reset_hdlr_active = 1; 5284 if (qla83xx_nic_core_reset(base_vha)) { 5285 /* NIC Core reset failed. */ 5286 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5287 "NIC Core reset failed.\n"); 5288 } 5289 ha->flags.nic_core_reset_hdlr_active = 0; 5290 } 5291 } 5292 5293 /* Work: Handle 8200 IDC aens */ 5294 void 5295 qla83xx_service_idc_aen(struct work_struct *work) 5296 { 5297 struct qla_hw_data *ha = 5298 container_of(work, struct qla_hw_data, idc_aen); 5299 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5300 uint32_t dev_state, idc_control; 5301 5302 qla83xx_idc_lock(base_vha, 0); 5303 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5304 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5305 qla83xx_idc_unlock(base_vha, 0); 5306 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5307 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5308 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5309 "Application requested NIC Core Reset.\n"); 5310 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5311 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5312 QLA_SUCCESS) { 5313 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5314 "Other protocol driver requested NIC Core Reset.\n"); 5315 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5316 } 5317 } else if (dev_state == QLA8XXX_DEV_FAILED || 5318 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5319 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5320 } 5321 } 5322 5323 static void 5324 qla83xx_wait_logic(void) 5325 { 5326 int i; 5327 5328 /* Yield CPU */ 5329 if (!in_interrupt()) { 5330 /* 5331 * Wait about 200ms before retrying again. 5332 * This controls the number of retries for single 5333 * lock operation. 5334 */ 5335 msleep(100); 5336 schedule(); 5337 } else { 5338 for (i = 0; i < 20; i++) 5339 cpu_relax(); /* This a nop instr on i386 */ 5340 } 5341 } 5342 5343 static int 5344 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5345 { 5346 int rval; 5347 uint32_t data; 5348 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5349 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5350 struct qla_hw_data *ha = base_vha->hw; 5351 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5352 "Trying force recovery of the IDC lock.\n"); 5353 5354 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5355 if (rval) 5356 return rval; 5357 5358 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5359 return QLA_SUCCESS; 5360 } else { 5361 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5362 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5363 data); 5364 if (rval) 5365 return rval; 5366 5367 msleep(200); 5368 5369 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5370 &data); 5371 if (rval) 5372 return rval; 5373 5374 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5375 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5376 ~(idc_lck_rcvry_stage_mask)); 5377 rval = qla83xx_wr_reg(base_vha, 5378 QLA83XX_IDC_LOCK_RECOVERY, data); 5379 if (rval) 5380 return rval; 5381 5382 /* Forcefully perform IDC UnLock */ 5383 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5384 &data); 5385 if (rval) 5386 return rval; 5387 /* Clear lock-id by setting 0xff */ 5388 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5389 0xff); 5390 if (rval) 5391 return rval; 5392 /* Clear lock-recovery by setting 0x0 */ 5393 rval = qla83xx_wr_reg(base_vha, 5394 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5395 if (rval) 5396 return rval; 5397 } else 5398 return QLA_SUCCESS; 5399 } 5400 5401 return rval; 5402 } 5403 5404 static int 5405 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5406 { 5407 int rval = QLA_SUCCESS; 5408 uint32_t o_drv_lockid, n_drv_lockid; 5409 unsigned long lock_recovery_timeout; 5410 5411 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5412 retry_lockid: 5413 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5414 if (rval) 5415 goto exit; 5416 5417 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5418 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5419 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5420 return QLA_SUCCESS; 5421 else 5422 return QLA_FUNCTION_FAILED; 5423 } 5424 5425 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5426 if (rval) 5427 goto exit; 5428 5429 if (o_drv_lockid == n_drv_lockid) { 5430 qla83xx_wait_logic(); 5431 goto retry_lockid; 5432 } else 5433 return QLA_SUCCESS; 5434 5435 exit: 5436 return rval; 5437 } 5438 5439 void 5440 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5441 { 5442 uint16_t options = (requester_id << 15) | BIT_6; 5443 uint32_t data; 5444 uint32_t lock_owner; 5445 struct qla_hw_data *ha = base_vha->hw; 5446 5447 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5448 retry_lock: 5449 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5450 == QLA_SUCCESS) { 5451 if (data) { 5452 /* Setting lock-id to our function-number */ 5453 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5454 ha->portnum); 5455 } else { 5456 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5457 &lock_owner); 5458 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5459 "Failed to acquire IDC lock, acquired by %d, " 5460 "retrying...\n", lock_owner); 5461 5462 /* Retry/Perform IDC-Lock recovery */ 5463 if (qla83xx_idc_lock_recovery(base_vha) 5464 == QLA_SUCCESS) { 5465 qla83xx_wait_logic(); 5466 goto retry_lock; 5467 } else 5468 ql_log(ql_log_warn, base_vha, 0xb075, 5469 "IDC Lock recovery FAILED.\n"); 5470 } 5471 5472 } 5473 5474 return; 5475 5476 /* XXX: IDC-lock implementation using access-control mbx */ 5477 retry_lock2: 5478 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5479 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5480 "Failed to acquire IDC lock. retrying...\n"); 5481 /* Retry/Perform IDC-Lock recovery */ 5482 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5483 qla83xx_wait_logic(); 5484 goto retry_lock2; 5485 } else 5486 ql_log(ql_log_warn, base_vha, 0xb076, 5487 "IDC Lock recovery FAILED.\n"); 5488 } 5489 5490 return; 5491 } 5492 5493 void 5494 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5495 { 5496 #if 0 5497 uint16_t options = (requester_id << 15) | BIT_7; 5498 #endif 5499 uint16_t retry; 5500 uint32_t data; 5501 struct qla_hw_data *ha = base_vha->hw; 5502 5503 /* IDC-unlock implementation using driver-unlock/lock-id 5504 * remote registers 5505 */ 5506 retry = 0; 5507 retry_unlock: 5508 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5509 == QLA_SUCCESS) { 5510 if (data == ha->portnum) { 5511 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5512 /* Clearing lock-id by setting 0xff */ 5513 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5514 } else if (retry < 10) { 5515 /* SV: XXX: IDC unlock retrying needed here? */ 5516 5517 /* Retry for IDC-unlock */ 5518 qla83xx_wait_logic(); 5519 retry++; 5520 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5521 "Failed to release IDC lock, retrying=%d\n", retry); 5522 goto retry_unlock; 5523 } 5524 } else if (retry < 10) { 5525 /* Retry for IDC-unlock */ 5526 qla83xx_wait_logic(); 5527 retry++; 5528 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5529 "Failed to read drv-lockid, retrying=%d\n", retry); 5530 goto retry_unlock; 5531 } 5532 5533 return; 5534 5535 #if 0 5536 /* XXX: IDC-unlock implementation using access-control mbx */ 5537 retry = 0; 5538 retry_unlock2: 5539 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5540 if (retry < 10) { 5541 /* Retry for IDC-unlock */ 5542 qla83xx_wait_logic(); 5543 retry++; 5544 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5545 "Failed to release IDC lock, retrying=%d\n", retry); 5546 goto retry_unlock2; 5547 } 5548 } 5549 5550 return; 5551 #endif 5552 } 5553 5554 int 5555 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5556 { 5557 int rval = QLA_SUCCESS; 5558 struct qla_hw_data *ha = vha->hw; 5559 uint32_t drv_presence; 5560 5561 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5562 if (rval == QLA_SUCCESS) { 5563 drv_presence |= (1 << ha->portnum); 5564 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5565 drv_presence); 5566 } 5567 5568 return rval; 5569 } 5570 5571 int 5572 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5573 { 5574 int rval = QLA_SUCCESS; 5575 5576 qla83xx_idc_lock(vha, 0); 5577 rval = __qla83xx_set_drv_presence(vha); 5578 qla83xx_idc_unlock(vha, 0); 5579 5580 return rval; 5581 } 5582 5583 int 5584 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5585 { 5586 int rval = QLA_SUCCESS; 5587 struct qla_hw_data *ha = vha->hw; 5588 uint32_t drv_presence; 5589 5590 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5591 if (rval == QLA_SUCCESS) { 5592 drv_presence &= ~(1 << ha->portnum); 5593 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5594 drv_presence); 5595 } 5596 5597 return rval; 5598 } 5599 5600 int 5601 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5602 { 5603 int rval = QLA_SUCCESS; 5604 5605 qla83xx_idc_lock(vha, 0); 5606 rval = __qla83xx_clear_drv_presence(vha); 5607 qla83xx_idc_unlock(vha, 0); 5608 5609 return rval; 5610 } 5611 5612 static void 5613 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5614 { 5615 struct qla_hw_data *ha = vha->hw; 5616 uint32_t drv_ack, drv_presence; 5617 unsigned long ack_timeout; 5618 5619 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5620 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5621 while (1) { 5622 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5623 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5624 if ((drv_ack & drv_presence) == drv_presence) 5625 break; 5626 5627 if (time_after_eq(jiffies, ack_timeout)) { 5628 ql_log(ql_log_warn, vha, 0xb067, 5629 "RESET ACK TIMEOUT! drv_presence=0x%x " 5630 "drv_ack=0x%x\n", drv_presence, drv_ack); 5631 /* 5632 * The function(s) which did not ack in time are forced 5633 * to withdraw any further participation in the IDC 5634 * reset. 5635 */ 5636 if (drv_ack != drv_presence) 5637 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5638 drv_ack); 5639 break; 5640 } 5641 5642 qla83xx_idc_unlock(vha, 0); 5643 msleep(1000); 5644 qla83xx_idc_lock(vha, 0); 5645 } 5646 5647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5648 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5649 } 5650 5651 static int 5652 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5653 { 5654 int rval = QLA_SUCCESS; 5655 uint32_t idc_control; 5656 5657 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5658 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5659 5660 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5661 __qla83xx_get_idc_control(vha, &idc_control); 5662 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5663 __qla83xx_set_idc_control(vha, 0); 5664 5665 qla83xx_idc_unlock(vha, 0); 5666 rval = qla83xx_restart_nic_firmware(vha); 5667 qla83xx_idc_lock(vha, 0); 5668 5669 if (rval != QLA_SUCCESS) { 5670 ql_log(ql_log_fatal, vha, 0xb06a, 5671 "Failed to restart NIC f/w.\n"); 5672 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5673 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5674 } else { 5675 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5676 "Success in restarting nic f/w.\n"); 5677 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5678 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5679 } 5680 5681 return rval; 5682 } 5683 5684 /* Assumes idc_lock always held on entry */ 5685 int 5686 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5687 { 5688 struct qla_hw_data *ha = base_vha->hw; 5689 int rval = QLA_SUCCESS; 5690 unsigned long dev_init_timeout; 5691 uint32_t dev_state; 5692 5693 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5694 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5695 5696 while (1) { 5697 5698 if (time_after_eq(jiffies, dev_init_timeout)) { 5699 ql_log(ql_log_warn, base_vha, 0xb06e, 5700 "Initialization TIMEOUT!\n"); 5701 /* Init timeout. Disable further NIC Core 5702 * communication. 5703 */ 5704 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5705 QLA8XXX_DEV_FAILED); 5706 ql_log(ql_log_info, base_vha, 0xb06f, 5707 "HW State: FAILED.\n"); 5708 } 5709 5710 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5711 switch (dev_state) { 5712 case QLA8XXX_DEV_READY: 5713 if (ha->flags.nic_core_reset_owner) 5714 qla83xx_idc_audit(base_vha, 5715 IDC_AUDIT_COMPLETION); 5716 ha->flags.nic_core_reset_owner = 0; 5717 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5718 "Reset_owner reset by 0x%x.\n", 5719 ha->portnum); 5720 goto exit; 5721 case QLA8XXX_DEV_COLD: 5722 if (ha->flags.nic_core_reset_owner) 5723 rval = qla83xx_device_bootstrap(base_vha); 5724 else { 5725 /* Wait for AEN to change device-state */ 5726 qla83xx_idc_unlock(base_vha, 0); 5727 msleep(1000); 5728 qla83xx_idc_lock(base_vha, 0); 5729 } 5730 break; 5731 case QLA8XXX_DEV_INITIALIZING: 5732 /* Wait for AEN to change device-state */ 5733 qla83xx_idc_unlock(base_vha, 0); 5734 msleep(1000); 5735 qla83xx_idc_lock(base_vha, 0); 5736 break; 5737 case QLA8XXX_DEV_NEED_RESET: 5738 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5739 qla83xx_need_reset_handler(base_vha); 5740 else { 5741 /* Wait for AEN to change device-state */ 5742 qla83xx_idc_unlock(base_vha, 0); 5743 msleep(1000); 5744 qla83xx_idc_lock(base_vha, 0); 5745 } 5746 /* reset timeout value after need reset handler */ 5747 dev_init_timeout = jiffies + 5748 (ha->fcoe_dev_init_timeout * HZ); 5749 break; 5750 case QLA8XXX_DEV_NEED_QUIESCENT: 5751 /* XXX: DEBUG for now */ 5752 qla83xx_idc_unlock(base_vha, 0); 5753 msleep(1000); 5754 qla83xx_idc_lock(base_vha, 0); 5755 break; 5756 case QLA8XXX_DEV_QUIESCENT: 5757 /* XXX: DEBUG for now */ 5758 if (ha->flags.quiesce_owner) 5759 goto exit; 5760 5761 qla83xx_idc_unlock(base_vha, 0); 5762 msleep(1000); 5763 qla83xx_idc_lock(base_vha, 0); 5764 dev_init_timeout = jiffies + 5765 (ha->fcoe_dev_init_timeout * HZ); 5766 break; 5767 case QLA8XXX_DEV_FAILED: 5768 if (ha->flags.nic_core_reset_owner) 5769 qla83xx_idc_audit(base_vha, 5770 IDC_AUDIT_COMPLETION); 5771 ha->flags.nic_core_reset_owner = 0; 5772 __qla83xx_clear_drv_presence(base_vha); 5773 qla83xx_idc_unlock(base_vha, 0); 5774 qla8xxx_dev_failed_handler(base_vha); 5775 rval = QLA_FUNCTION_FAILED; 5776 qla83xx_idc_lock(base_vha, 0); 5777 goto exit; 5778 case QLA8XXX_BAD_VALUE: 5779 qla83xx_idc_unlock(base_vha, 0); 5780 msleep(1000); 5781 qla83xx_idc_lock(base_vha, 0); 5782 break; 5783 default: 5784 ql_log(ql_log_warn, base_vha, 0xb071, 5785 "Unknown Device State: %x.\n", dev_state); 5786 qla83xx_idc_unlock(base_vha, 0); 5787 qla8xxx_dev_failed_handler(base_vha); 5788 rval = QLA_FUNCTION_FAILED; 5789 qla83xx_idc_lock(base_vha, 0); 5790 goto exit; 5791 } 5792 } 5793 5794 exit: 5795 return rval; 5796 } 5797 5798 void 5799 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5800 { 5801 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5802 board_disable); 5803 struct pci_dev *pdev = ha->pdev; 5804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5805 5806 /* 5807 * if UNLOAD flag is already set, then continue unload, 5808 * where it was set first. 5809 */ 5810 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5811 return; 5812 5813 ql_log(ql_log_warn, base_vha, 0x015b, 5814 "Disabling adapter.\n"); 5815 5816 if (!atomic_read(&pdev->enable_cnt)) { 5817 ql_log(ql_log_info, base_vha, 0xfffc, 5818 "PCI device disabled, no action req for PCI error=%lx\n", 5819 base_vha->pci_flags); 5820 return; 5821 } 5822 5823 qla2x00_wait_for_sess_deletion(base_vha); 5824 5825 set_bit(UNLOADING, &base_vha->dpc_flags); 5826 5827 qla2x00_delete_all_vps(ha, base_vha); 5828 5829 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5830 5831 qla2x00_dfs_remove(base_vha); 5832 5833 qla84xx_put_chip(base_vha); 5834 5835 if (base_vha->timer_active) 5836 qla2x00_stop_timer(base_vha); 5837 5838 base_vha->flags.online = 0; 5839 5840 qla2x00_destroy_deferred_work(ha); 5841 5842 /* 5843 * Do not try to stop beacon blink as it will issue a mailbox 5844 * command. 5845 */ 5846 qla2x00_free_sysfs_attr(base_vha, false); 5847 5848 fc_remove_host(base_vha->host); 5849 5850 scsi_remove_host(base_vha->host); 5851 5852 base_vha->flags.init_done = 0; 5853 qla25xx_delete_queues(base_vha); 5854 qla2x00_free_fcports(base_vha); 5855 qla2x00_free_irqs(base_vha); 5856 qla2x00_mem_free(ha); 5857 qla82xx_md_free(base_vha); 5858 qla2x00_free_queues(ha); 5859 5860 qla2x00_unmap_iobases(ha); 5861 5862 pci_release_selected_regions(ha->pdev, ha->bars); 5863 pci_disable_pcie_error_reporting(pdev); 5864 pci_disable_device(pdev); 5865 5866 /* 5867 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5868 */ 5869 } 5870 5871 /************************************************************************** 5872 * qla2x00_do_dpc 5873 * This kernel thread is a task that is schedule by the interrupt handler 5874 * to perform the background processing for interrupts. 5875 * 5876 * Notes: 5877 * This task always run in the context of a kernel thread. It 5878 * is kick-off by the driver's detect code and starts up 5879 * up one per adapter. It immediately goes to sleep and waits for 5880 * some fibre event. When either the interrupt handler or 5881 * the timer routine detects a event it will one of the task 5882 * bits then wake us up. 5883 **************************************************************************/ 5884 static int 5885 qla2x00_do_dpc(void *data) 5886 { 5887 scsi_qla_host_t *base_vha; 5888 struct qla_hw_data *ha; 5889 uint32_t online; 5890 struct qla_qpair *qpair; 5891 5892 ha = (struct qla_hw_data *)data; 5893 base_vha = pci_get_drvdata(ha->pdev); 5894 5895 set_user_nice(current, MIN_NICE); 5896 5897 set_current_state(TASK_INTERRUPTIBLE); 5898 while (!kthread_should_stop()) { 5899 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5900 "DPC handler sleeping.\n"); 5901 5902 schedule(); 5903 5904 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5905 goto end_loop; 5906 5907 if (ha->flags.eeh_busy) { 5908 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5909 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5910 goto end_loop; 5911 } 5912 5913 ha->dpc_active = 1; 5914 5915 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5916 "DPC handler waking up, dpc_flags=0x%lx.\n", 5917 base_vha->dpc_flags); 5918 5919 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5920 break; 5921 5922 if (IS_P3P_TYPE(ha)) { 5923 if (IS_QLA8044(ha)) { 5924 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5925 &base_vha->dpc_flags)) { 5926 qla8044_idc_lock(ha); 5927 qla8044_wr_direct(base_vha, 5928 QLA8044_CRB_DEV_STATE_INDEX, 5929 QLA8XXX_DEV_FAILED); 5930 qla8044_idc_unlock(ha); 5931 ql_log(ql_log_info, base_vha, 0x4004, 5932 "HW State: FAILED.\n"); 5933 qla8044_device_state_handler(base_vha); 5934 continue; 5935 } 5936 5937 } else { 5938 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5939 &base_vha->dpc_flags)) { 5940 qla82xx_idc_lock(ha); 5941 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5942 QLA8XXX_DEV_FAILED); 5943 qla82xx_idc_unlock(ha); 5944 ql_log(ql_log_info, base_vha, 0x0151, 5945 "HW State: FAILED.\n"); 5946 qla82xx_device_state_handler(base_vha); 5947 continue; 5948 } 5949 } 5950 5951 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5952 &base_vha->dpc_flags)) { 5953 5954 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5955 "FCoE context reset scheduled.\n"); 5956 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5957 &base_vha->dpc_flags))) { 5958 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5959 /* FCoE-ctx reset failed. 5960 * Escalate to chip-reset 5961 */ 5962 set_bit(ISP_ABORT_NEEDED, 5963 &base_vha->dpc_flags); 5964 } 5965 clear_bit(ABORT_ISP_ACTIVE, 5966 &base_vha->dpc_flags); 5967 } 5968 5969 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5970 "FCoE context reset end.\n"); 5971 } 5972 } else if (IS_QLAFX00(ha)) { 5973 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5974 &base_vha->dpc_flags)) { 5975 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5976 "Firmware Reset Recovery\n"); 5977 if (qlafx00_reset_initialize(base_vha)) { 5978 /* Failed. Abort isp later. */ 5979 if (!test_bit(UNLOADING, 5980 &base_vha->dpc_flags)) { 5981 set_bit(ISP_UNRECOVERABLE, 5982 &base_vha->dpc_flags); 5983 ql_dbg(ql_dbg_dpc, base_vha, 5984 0x4021, 5985 "Reset Recovery Failed\n"); 5986 } 5987 } 5988 } 5989 5990 if (test_and_clear_bit(FX00_TARGET_SCAN, 5991 &base_vha->dpc_flags)) { 5992 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5993 "ISPFx00 Target Scan scheduled\n"); 5994 if (qlafx00_rescan_isp(base_vha)) { 5995 if (!test_bit(UNLOADING, 5996 &base_vha->dpc_flags)) 5997 set_bit(ISP_UNRECOVERABLE, 5998 &base_vha->dpc_flags); 5999 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6000 "ISPFx00 Target Scan Failed\n"); 6001 } 6002 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6003 "ISPFx00 Target Scan End\n"); 6004 } 6005 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6006 &base_vha->dpc_flags)) { 6007 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6008 "ISPFx00 Host Info resend scheduled\n"); 6009 qlafx00_fx_disc(base_vha, 6010 &base_vha->hw->mr.fcport, 6011 FXDISC_REG_HOST_INFO); 6012 } 6013 } 6014 6015 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6016 &base_vha->dpc_flags) && 6017 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6018 qla24xx_detect_sfp(base_vha); 6019 6020 if (ha->flags.detected_lr_sfp != 6021 ha->flags.using_lr_setting) 6022 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6023 } 6024 6025 if (test_and_clear_bit(ISP_ABORT_NEEDED, 6026 &base_vha->dpc_flags)) { 6027 6028 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6029 "ISP abort scheduled.\n"); 6030 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6031 &base_vha->dpc_flags))) { 6032 6033 if (ha->isp_ops->abort_isp(base_vha)) { 6034 /* failed. retry later */ 6035 set_bit(ISP_ABORT_NEEDED, 6036 &base_vha->dpc_flags); 6037 } 6038 clear_bit(ABORT_ISP_ACTIVE, 6039 &base_vha->dpc_flags); 6040 } 6041 6042 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6043 "ISP abort end.\n"); 6044 } 6045 6046 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6047 &base_vha->dpc_flags)) { 6048 qla2x00_update_fcports(base_vha); 6049 } 6050 6051 if (IS_QLAFX00(ha)) 6052 goto loop_resync_check; 6053 6054 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6055 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6056 "Quiescence mode scheduled.\n"); 6057 if (IS_P3P_TYPE(ha)) { 6058 if (IS_QLA82XX(ha)) 6059 qla82xx_device_state_handler(base_vha); 6060 if (IS_QLA8044(ha)) 6061 qla8044_device_state_handler(base_vha); 6062 clear_bit(ISP_QUIESCE_NEEDED, 6063 &base_vha->dpc_flags); 6064 if (!ha->flags.quiesce_owner) { 6065 qla2x00_perform_loop_resync(base_vha); 6066 if (IS_QLA82XX(ha)) { 6067 qla82xx_idc_lock(ha); 6068 qla82xx_clear_qsnt_ready( 6069 base_vha); 6070 qla82xx_idc_unlock(ha); 6071 } else if (IS_QLA8044(ha)) { 6072 qla8044_idc_lock(ha); 6073 qla8044_clear_qsnt_ready( 6074 base_vha); 6075 qla8044_idc_unlock(ha); 6076 } 6077 } 6078 } else { 6079 clear_bit(ISP_QUIESCE_NEEDED, 6080 &base_vha->dpc_flags); 6081 qla2x00_quiesce_io(base_vha); 6082 } 6083 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6084 "Quiescence mode end.\n"); 6085 } 6086 6087 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6088 &base_vha->dpc_flags) && 6089 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6090 6091 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6092 "Reset marker scheduled.\n"); 6093 qla2x00_rst_aen(base_vha); 6094 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6095 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6096 "Reset marker end.\n"); 6097 } 6098 6099 /* Retry each device up to login retry count */ 6100 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6101 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6102 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6103 6104 if (!base_vha->relogin_jif || 6105 time_after_eq(jiffies, base_vha->relogin_jif)) { 6106 base_vha->relogin_jif = jiffies + HZ; 6107 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6108 6109 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6110 "Relogin scheduled.\n"); 6111 qla24xx_post_relogin_work(base_vha); 6112 } 6113 } 6114 loop_resync_check: 6115 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6116 &base_vha->dpc_flags)) { 6117 6118 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6119 "Loop resync scheduled.\n"); 6120 6121 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6122 &base_vha->dpc_flags))) { 6123 6124 qla2x00_loop_resync(base_vha); 6125 6126 clear_bit(LOOP_RESYNC_ACTIVE, 6127 &base_vha->dpc_flags); 6128 } 6129 6130 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6131 "Loop resync end.\n"); 6132 } 6133 6134 if (IS_QLAFX00(ha)) 6135 goto intr_on_check; 6136 6137 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6138 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6139 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6140 qla2xxx_flash_npiv_conf(base_vha); 6141 } 6142 6143 intr_on_check: 6144 if (!ha->interrupts_on) 6145 ha->isp_ops->enable_intrs(ha); 6146 6147 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6148 &base_vha->dpc_flags)) { 6149 if (ha->beacon_blink_led == 1) 6150 ha->isp_ops->beacon_blink(base_vha); 6151 } 6152 6153 /* qpair online check */ 6154 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6155 &base_vha->dpc_flags)) { 6156 if (ha->flags.eeh_busy || 6157 ha->flags.pci_channel_io_perm_failure) 6158 online = 0; 6159 else 6160 online = 1; 6161 6162 mutex_lock(&ha->mq_lock); 6163 list_for_each_entry(qpair, &base_vha->qp_list, 6164 qp_list_elem) 6165 qpair->online = online; 6166 mutex_unlock(&ha->mq_lock); 6167 } 6168 6169 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6170 ql_log(ql_log_info, base_vha, 0xffffff, 6171 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6172 ha->nvme_last_rptd_aen); 6173 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6174 ql_log(ql_log_info, base_vha, 0xffffff, 6175 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6176 ha->nvme_last_rptd_aen); 6177 } 6178 } 6179 6180 if (!IS_QLAFX00(ha)) 6181 qla2x00_do_dpc_all_vps(base_vha); 6182 6183 ha->dpc_active = 0; 6184 end_loop: 6185 set_current_state(TASK_INTERRUPTIBLE); 6186 } /* End of while(1) */ 6187 __set_current_state(TASK_RUNNING); 6188 6189 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6190 "DPC handler exiting.\n"); 6191 6192 /* 6193 * Make sure that nobody tries to wake us up again. 6194 */ 6195 ha->dpc_active = 0; 6196 6197 /* Cleanup any residual CTX SRBs. */ 6198 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6199 6200 return 0; 6201 } 6202 6203 void 6204 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6205 { 6206 struct qla_hw_data *ha = vha->hw; 6207 struct task_struct *t = ha->dpc_thread; 6208 6209 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6210 wake_up_process(t); 6211 } 6212 6213 /* 6214 * qla2x00_rst_aen 6215 * Processes asynchronous reset. 6216 * 6217 * Input: 6218 * ha = adapter block pointer. 6219 */ 6220 static void 6221 qla2x00_rst_aen(scsi_qla_host_t *vha) 6222 { 6223 if (vha->flags.online && !vha->flags.reset_active && 6224 !atomic_read(&vha->loop_down_timer) && 6225 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6226 do { 6227 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6228 6229 /* 6230 * Issue marker command only when we are going to start 6231 * the I/O. 6232 */ 6233 vha->marker_needed = 1; 6234 } while (!atomic_read(&vha->loop_down_timer) && 6235 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6236 } 6237 } 6238 6239 /************************************************************************** 6240 * qla2x00_timer 6241 * 6242 * Description: 6243 * One second timer 6244 * 6245 * Context: Interrupt 6246 ***************************************************************************/ 6247 void 6248 qla2x00_timer(struct timer_list *t) 6249 { 6250 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6251 unsigned long cpu_flags = 0; 6252 int start_dpc = 0; 6253 int index; 6254 srb_t *sp; 6255 uint16_t w; 6256 struct qla_hw_data *ha = vha->hw; 6257 struct req_que *req; 6258 6259 if (ha->flags.eeh_busy) { 6260 ql_dbg(ql_dbg_timer, vha, 0x6000, 6261 "EEH = %d, restarting timer.\n", 6262 ha->flags.eeh_busy); 6263 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6264 return; 6265 } 6266 6267 /* 6268 * Hardware read to raise pending EEH errors during mailbox waits. If 6269 * the read returns -1 then disable the board. 6270 */ 6271 if (!pci_channel_offline(ha->pdev)) { 6272 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6273 qla2x00_check_reg16_for_disconnect(vha, w); 6274 } 6275 6276 /* Make sure qla82xx_watchdog is run only for physical port */ 6277 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6278 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6279 start_dpc++; 6280 if (IS_QLA82XX(ha)) 6281 qla82xx_watchdog(vha); 6282 else if (IS_QLA8044(ha)) 6283 qla8044_watchdog(vha); 6284 } 6285 6286 if (!vha->vp_idx && IS_QLAFX00(ha)) 6287 qlafx00_timer_routine(vha); 6288 6289 /* Loop down handler. */ 6290 if (atomic_read(&vha->loop_down_timer) > 0 && 6291 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6292 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6293 && vha->flags.online) { 6294 6295 if (atomic_read(&vha->loop_down_timer) == 6296 vha->loop_down_abort_time) { 6297 6298 ql_log(ql_log_info, vha, 0x6008, 6299 "Loop down - aborting the queues before time expires.\n"); 6300 6301 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6302 atomic_set(&vha->loop_state, LOOP_DEAD); 6303 6304 /* 6305 * Schedule an ISP abort to return any FCP2-device 6306 * commands. 6307 */ 6308 /* NPIV - scan physical port only */ 6309 if (!vha->vp_idx) { 6310 spin_lock_irqsave(&ha->hardware_lock, 6311 cpu_flags); 6312 req = ha->req_q_map[0]; 6313 for (index = 1; 6314 index < req->num_outstanding_cmds; 6315 index++) { 6316 fc_port_t *sfcp; 6317 6318 sp = req->outstanding_cmds[index]; 6319 if (!sp) 6320 continue; 6321 if (sp->cmd_type != TYPE_SRB) 6322 continue; 6323 if (sp->type != SRB_SCSI_CMD) 6324 continue; 6325 sfcp = sp->fcport; 6326 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6327 continue; 6328 6329 if (IS_QLA82XX(ha)) 6330 set_bit(FCOE_CTX_RESET_NEEDED, 6331 &vha->dpc_flags); 6332 else 6333 set_bit(ISP_ABORT_NEEDED, 6334 &vha->dpc_flags); 6335 break; 6336 } 6337 spin_unlock_irqrestore(&ha->hardware_lock, 6338 cpu_flags); 6339 } 6340 start_dpc++; 6341 } 6342 6343 /* if the loop has been down for 4 minutes, reinit adapter */ 6344 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6345 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6346 ql_log(ql_log_warn, vha, 0x6009, 6347 "Loop down - aborting ISP.\n"); 6348 6349 if (IS_QLA82XX(ha)) 6350 set_bit(FCOE_CTX_RESET_NEEDED, 6351 &vha->dpc_flags); 6352 else 6353 set_bit(ISP_ABORT_NEEDED, 6354 &vha->dpc_flags); 6355 } 6356 } 6357 ql_dbg(ql_dbg_timer, vha, 0x600a, 6358 "Loop down - seconds remaining %d.\n", 6359 atomic_read(&vha->loop_down_timer)); 6360 } 6361 /* Check if beacon LED needs to be blinked for physical host only */ 6362 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6363 /* There is no beacon_blink function for ISP82xx */ 6364 if (!IS_P3P_TYPE(ha)) { 6365 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6366 start_dpc++; 6367 } 6368 } 6369 6370 /* Process any deferred work. */ 6371 if (!list_empty(&vha->work_list)) { 6372 unsigned long flags; 6373 bool q = false; 6374 6375 spin_lock_irqsave(&vha->work_lock, flags); 6376 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6377 q = true; 6378 spin_unlock_irqrestore(&vha->work_lock, flags); 6379 if (q) 6380 queue_work(vha->hw->wq, &vha->iocb_work); 6381 } 6382 6383 /* 6384 * FC-NVME 6385 * see if the active AEN count has changed from what was last reported. 6386 */ 6387 if (!vha->vp_idx && 6388 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6389 ha->zio_mode == QLA_ZIO_MODE_6) { 6390 ql_log(ql_log_info, vha, 0x3002, 6391 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6392 ha->nvme_last_rptd_aen); 6393 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6394 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6395 start_dpc++; 6396 } 6397 6398 /* Schedule the DPC routine if needed */ 6399 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6400 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6401 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6402 start_dpc || 6403 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6404 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6405 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6406 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6407 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6408 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6409 ql_dbg(ql_dbg_timer, vha, 0x600b, 6410 "isp_abort_needed=%d loop_resync_needed=%d " 6411 "fcport_update_needed=%d start_dpc=%d " 6412 "reset_marker_needed=%d", 6413 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6414 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6415 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6416 start_dpc, 6417 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6418 ql_dbg(ql_dbg_timer, vha, 0x600c, 6419 "beacon_blink_needed=%d isp_unrecoverable=%d " 6420 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6421 "relogin_needed=%d.\n", 6422 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6423 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6424 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6425 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6426 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6427 qla2xxx_wake_dpc(vha); 6428 } 6429 6430 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6431 } 6432 6433 /* Firmware interface routines. */ 6434 6435 #define FW_BLOBS 11 6436 #define FW_ISP21XX 0 6437 #define FW_ISP22XX 1 6438 #define FW_ISP2300 2 6439 #define FW_ISP2322 3 6440 #define FW_ISP24XX 4 6441 #define FW_ISP25XX 5 6442 #define FW_ISP81XX 6 6443 #define FW_ISP82XX 7 6444 #define FW_ISP2031 8 6445 #define FW_ISP8031 9 6446 #define FW_ISP27XX 10 6447 6448 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6449 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6450 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6451 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6452 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6453 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6454 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6455 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6456 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6457 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6458 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6459 6460 6461 static DEFINE_MUTEX(qla_fw_lock); 6462 6463 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6464 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6465 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6466 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6467 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6468 { .name = FW_FILE_ISP24XX, }, 6469 { .name = FW_FILE_ISP25XX, }, 6470 { .name = FW_FILE_ISP81XX, }, 6471 { .name = FW_FILE_ISP82XX, }, 6472 { .name = FW_FILE_ISP2031, }, 6473 { .name = FW_FILE_ISP8031, }, 6474 { .name = FW_FILE_ISP27XX, }, 6475 }; 6476 6477 struct fw_blob * 6478 qla2x00_request_firmware(scsi_qla_host_t *vha) 6479 { 6480 struct qla_hw_data *ha = vha->hw; 6481 struct fw_blob *blob; 6482 6483 if (IS_QLA2100(ha)) { 6484 blob = &qla_fw_blobs[FW_ISP21XX]; 6485 } else if (IS_QLA2200(ha)) { 6486 blob = &qla_fw_blobs[FW_ISP22XX]; 6487 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6488 blob = &qla_fw_blobs[FW_ISP2300]; 6489 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6490 blob = &qla_fw_blobs[FW_ISP2322]; 6491 } else if (IS_QLA24XX_TYPE(ha)) { 6492 blob = &qla_fw_blobs[FW_ISP24XX]; 6493 } else if (IS_QLA25XX(ha)) { 6494 blob = &qla_fw_blobs[FW_ISP25XX]; 6495 } else if (IS_QLA81XX(ha)) { 6496 blob = &qla_fw_blobs[FW_ISP81XX]; 6497 } else if (IS_QLA82XX(ha)) { 6498 blob = &qla_fw_blobs[FW_ISP82XX]; 6499 } else if (IS_QLA2031(ha)) { 6500 blob = &qla_fw_blobs[FW_ISP2031]; 6501 } else if (IS_QLA8031(ha)) { 6502 blob = &qla_fw_blobs[FW_ISP8031]; 6503 } else if (IS_QLA27XX(ha)) { 6504 blob = &qla_fw_blobs[FW_ISP27XX]; 6505 } else { 6506 return NULL; 6507 } 6508 6509 mutex_lock(&qla_fw_lock); 6510 if (blob->fw) 6511 goto out; 6512 6513 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6514 ql_log(ql_log_warn, vha, 0x0063, 6515 "Failed to load firmware image (%s).\n", blob->name); 6516 blob->fw = NULL; 6517 blob = NULL; 6518 goto out; 6519 } 6520 6521 out: 6522 mutex_unlock(&qla_fw_lock); 6523 return blob; 6524 } 6525 6526 static void 6527 qla2x00_release_firmware(void) 6528 { 6529 int idx; 6530 6531 mutex_lock(&qla_fw_lock); 6532 for (idx = 0; idx < FW_BLOBS; idx++) 6533 release_firmware(qla_fw_blobs[idx].fw); 6534 mutex_unlock(&qla_fw_lock); 6535 } 6536 6537 static pci_ers_result_t 6538 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6539 { 6540 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6541 struct qla_hw_data *ha = vha->hw; 6542 6543 ql_dbg(ql_dbg_aer, vha, 0x9000, 6544 "PCI error detected, state %x.\n", state); 6545 6546 if (!atomic_read(&pdev->enable_cnt)) { 6547 ql_log(ql_log_info, vha, 0xffff, 6548 "PCI device is disabled,state %x\n", state); 6549 return PCI_ERS_RESULT_NEED_RESET; 6550 } 6551 6552 switch (state) { 6553 case pci_channel_io_normal: 6554 ha->flags.eeh_busy = 0; 6555 if (ql2xmqsupport || ql2xnvmeenable) { 6556 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6557 qla2xxx_wake_dpc(vha); 6558 } 6559 return PCI_ERS_RESULT_CAN_RECOVER; 6560 case pci_channel_io_frozen: 6561 ha->flags.eeh_busy = 1; 6562 /* For ISP82XX complete any pending mailbox cmd */ 6563 if (IS_QLA82XX(ha)) { 6564 ha->flags.isp82xx_fw_hung = 1; 6565 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6566 qla82xx_clear_pending_mbx(vha); 6567 } 6568 qla2x00_free_irqs(vha); 6569 pci_disable_device(pdev); 6570 /* Return back all IOs */ 6571 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6572 if (ql2xmqsupport || ql2xnvmeenable) { 6573 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6574 qla2xxx_wake_dpc(vha); 6575 } 6576 return PCI_ERS_RESULT_NEED_RESET; 6577 case pci_channel_io_perm_failure: 6578 ha->flags.pci_channel_io_perm_failure = 1; 6579 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6580 if (ql2xmqsupport || ql2xnvmeenable) { 6581 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6582 qla2xxx_wake_dpc(vha); 6583 } 6584 return PCI_ERS_RESULT_DISCONNECT; 6585 } 6586 return PCI_ERS_RESULT_NEED_RESET; 6587 } 6588 6589 static pci_ers_result_t 6590 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6591 { 6592 int risc_paused = 0; 6593 uint32_t stat; 6594 unsigned long flags; 6595 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6596 struct qla_hw_data *ha = base_vha->hw; 6597 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6598 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6599 6600 if (IS_QLA82XX(ha)) 6601 return PCI_ERS_RESULT_RECOVERED; 6602 6603 spin_lock_irqsave(&ha->hardware_lock, flags); 6604 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6605 stat = RD_REG_DWORD(®->hccr); 6606 if (stat & HCCR_RISC_PAUSE) 6607 risc_paused = 1; 6608 } else if (IS_QLA23XX(ha)) { 6609 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6610 if (stat & HSR_RISC_PAUSED) 6611 risc_paused = 1; 6612 } else if (IS_FWI2_CAPABLE(ha)) { 6613 stat = RD_REG_DWORD(®24->host_status); 6614 if (stat & HSRX_RISC_PAUSED) 6615 risc_paused = 1; 6616 } 6617 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6618 6619 if (risc_paused) { 6620 ql_log(ql_log_info, base_vha, 0x9003, 6621 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6622 ha->isp_ops->fw_dump(base_vha, 0); 6623 6624 return PCI_ERS_RESULT_NEED_RESET; 6625 } else 6626 return PCI_ERS_RESULT_RECOVERED; 6627 } 6628 6629 static uint32_t 6630 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6631 { 6632 uint32_t rval = QLA_FUNCTION_FAILED; 6633 uint32_t drv_active = 0; 6634 struct qla_hw_data *ha = base_vha->hw; 6635 int fn; 6636 struct pci_dev *other_pdev = NULL; 6637 6638 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6639 "Entered %s.\n", __func__); 6640 6641 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6642 6643 if (base_vha->flags.online) { 6644 /* Abort all outstanding commands, 6645 * so as to be requeued later */ 6646 qla2x00_abort_isp_cleanup(base_vha); 6647 } 6648 6649 6650 fn = PCI_FUNC(ha->pdev->devfn); 6651 while (fn > 0) { 6652 fn--; 6653 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6654 "Finding pci device at function = 0x%x.\n", fn); 6655 other_pdev = 6656 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6657 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6658 fn)); 6659 6660 if (!other_pdev) 6661 continue; 6662 if (atomic_read(&other_pdev->enable_cnt)) { 6663 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6664 "Found PCI func available and enable at 0x%x.\n", 6665 fn); 6666 pci_dev_put(other_pdev); 6667 break; 6668 } 6669 pci_dev_put(other_pdev); 6670 } 6671 6672 if (!fn) { 6673 /* Reset owner */ 6674 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6675 "This devfn is reset owner = 0x%x.\n", 6676 ha->pdev->devfn); 6677 qla82xx_idc_lock(ha); 6678 6679 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6680 QLA8XXX_DEV_INITIALIZING); 6681 6682 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6683 QLA82XX_IDC_VERSION); 6684 6685 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6686 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6687 "drv_active = 0x%x.\n", drv_active); 6688 6689 qla82xx_idc_unlock(ha); 6690 /* Reset if device is not already reset 6691 * drv_active would be 0 if a reset has already been done 6692 */ 6693 if (drv_active) 6694 rval = qla82xx_start_firmware(base_vha); 6695 else 6696 rval = QLA_SUCCESS; 6697 qla82xx_idc_lock(ha); 6698 6699 if (rval != QLA_SUCCESS) { 6700 ql_log(ql_log_info, base_vha, 0x900b, 6701 "HW State: FAILED.\n"); 6702 qla82xx_clear_drv_active(ha); 6703 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6704 QLA8XXX_DEV_FAILED); 6705 } else { 6706 ql_log(ql_log_info, base_vha, 0x900c, 6707 "HW State: READY.\n"); 6708 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6709 QLA8XXX_DEV_READY); 6710 qla82xx_idc_unlock(ha); 6711 ha->flags.isp82xx_fw_hung = 0; 6712 rval = qla82xx_restart_isp(base_vha); 6713 qla82xx_idc_lock(ha); 6714 /* Clear driver state register */ 6715 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6716 qla82xx_set_drv_active(base_vha); 6717 } 6718 qla82xx_idc_unlock(ha); 6719 } else { 6720 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6721 "This devfn is not reset owner = 0x%x.\n", 6722 ha->pdev->devfn); 6723 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6724 QLA8XXX_DEV_READY)) { 6725 ha->flags.isp82xx_fw_hung = 0; 6726 rval = qla82xx_restart_isp(base_vha); 6727 qla82xx_idc_lock(ha); 6728 qla82xx_set_drv_active(base_vha); 6729 qla82xx_idc_unlock(ha); 6730 } 6731 } 6732 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6733 6734 return rval; 6735 } 6736 6737 static pci_ers_result_t 6738 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6739 { 6740 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6741 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6742 struct qla_hw_data *ha = base_vha->hw; 6743 struct rsp_que *rsp; 6744 int rc, retries = 10; 6745 6746 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6747 "Slot Reset.\n"); 6748 6749 /* Workaround: qla2xxx driver which access hardware earlier 6750 * needs error state to be pci_channel_io_online. 6751 * Otherwise mailbox command timesout. 6752 */ 6753 pdev->error_state = pci_channel_io_normal; 6754 6755 pci_restore_state(pdev); 6756 6757 /* pci_restore_state() clears the saved_state flag of the device 6758 * save restored state which resets saved_state flag 6759 */ 6760 pci_save_state(pdev); 6761 6762 if (ha->mem_only) 6763 rc = pci_enable_device_mem(pdev); 6764 else 6765 rc = pci_enable_device(pdev); 6766 6767 if (rc) { 6768 ql_log(ql_log_warn, base_vha, 0x9005, 6769 "Can't re-enable PCI device after reset.\n"); 6770 goto exit_slot_reset; 6771 } 6772 6773 rsp = ha->rsp_q_map[0]; 6774 if (qla2x00_request_irqs(ha, rsp)) 6775 goto exit_slot_reset; 6776 6777 if (ha->isp_ops->pci_config(base_vha)) 6778 goto exit_slot_reset; 6779 6780 if (IS_QLA82XX(ha)) { 6781 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6782 ret = PCI_ERS_RESULT_RECOVERED; 6783 goto exit_slot_reset; 6784 } else 6785 goto exit_slot_reset; 6786 } 6787 6788 while (ha->flags.mbox_busy && retries--) 6789 msleep(1000); 6790 6791 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6792 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6793 ret = PCI_ERS_RESULT_RECOVERED; 6794 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6795 6796 6797 exit_slot_reset: 6798 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6799 "slot_reset return %x.\n", ret); 6800 6801 return ret; 6802 } 6803 6804 static void 6805 qla2xxx_pci_resume(struct pci_dev *pdev) 6806 { 6807 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6808 struct qla_hw_data *ha = base_vha->hw; 6809 int ret; 6810 6811 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6812 "pci_resume.\n"); 6813 6814 ret = qla2x00_wait_for_hba_online(base_vha); 6815 if (ret != QLA_SUCCESS) { 6816 ql_log(ql_log_fatal, base_vha, 0x9002, 6817 "The device failed to resume I/O from slot/link_reset.\n"); 6818 } 6819 6820 pci_cleanup_aer_uncorrect_error_status(pdev); 6821 6822 ha->flags.eeh_busy = 0; 6823 } 6824 6825 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6826 { 6827 int rc; 6828 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6829 6830 if (USER_CTRL_IRQ(vha->hw)) 6831 rc = blk_mq_map_queues(&shost->tag_set); 6832 else 6833 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6834 return rc; 6835 } 6836 6837 static const struct pci_error_handlers qla2xxx_err_handler = { 6838 .error_detected = qla2xxx_pci_error_detected, 6839 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6840 .slot_reset = qla2xxx_pci_slot_reset, 6841 .resume = qla2xxx_pci_resume, 6842 }; 6843 6844 static struct pci_device_id qla2xxx_pci_tbl[] = { 6845 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6846 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6847 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6848 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6849 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6850 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6867 { 0 }, 6868 }; 6869 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6870 6871 static struct pci_driver qla2xxx_pci_driver = { 6872 .name = QLA2XXX_DRIVER_NAME, 6873 .driver = { 6874 .owner = THIS_MODULE, 6875 }, 6876 .id_table = qla2xxx_pci_tbl, 6877 .probe = qla2x00_probe_one, 6878 .remove = qla2x00_remove_one, 6879 .shutdown = qla2x00_shutdown, 6880 .err_handler = &qla2xxx_err_handler, 6881 }; 6882 6883 static const struct file_operations apidev_fops = { 6884 .owner = THIS_MODULE, 6885 .llseek = noop_llseek, 6886 }; 6887 6888 /** 6889 * qla2x00_module_init - Module initialization. 6890 **/ 6891 static int __init 6892 qla2x00_module_init(void) 6893 { 6894 int ret = 0; 6895 6896 /* Allocate cache for SRBs. */ 6897 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6898 SLAB_HWCACHE_ALIGN, NULL); 6899 if (srb_cachep == NULL) { 6900 ql_log(ql_log_fatal, NULL, 0x0001, 6901 "Unable to allocate SRB cache...Failing load!.\n"); 6902 return -ENOMEM; 6903 } 6904 6905 /* Initialize target kmem_cache and mem_pools */ 6906 ret = qlt_init(); 6907 if (ret < 0) { 6908 kmem_cache_destroy(srb_cachep); 6909 return ret; 6910 } else if (ret > 0) { 6911 /* 6912 * If initiator mode is explictly disabled by qlt_init(), 6913 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6914 * performing scsi_scan_target() during LOOP UP event. 6915 */ 6916 qla2xxx_transport_functions.disable_target_scan = 1; 6917 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6918 } 6919 6920 /* Derive version string. */ 6921 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6922 if (ql2xextended_error_logging) 6923 strcat(qla2x00_version_str, "-debug"); 6924 if (ql2xextended_error_logging == 1) 6925 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6926 6927 qla2xxx_transport_template = 6928 fc_attach_transport(&qla2xxx_transport_functions); 6929 if (!qla2xxx_transport_template) { 6930 kmem_cache_destroy(srb_cachep); 6931 ql_log(ql_log_fatal, NULL, 0x0002, 6932 "fc_attach_transport failed...Failing load!.\n"); 6933 qlt_exit(); 6934 return -ENODEV; 6935 } 6936 6937 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6938 if (apidev_major < 0) { 6939 ql_log(ql_log_fatal, NULL, 0x0003, 6940 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6941 } 6942 6943 qla2xxx_transport_vport_template = 6944 fc_attach_transport(&qla2xxx_transport_vport_functions); 6945 if (!qla2xxx_transport_vport_template) { 6946 kmem_cache_destroy(srb_cachep); 6947 qlt_exit(); 6948 fc_release_transport(qla2xxx_transport_template); 6949 ql_log(ql_log_fatal, NULL, 0x0004, 6950 "fc_attach_transport vport failed...Failing load!.\n"); 6951 return -ENODEV; 6952 } 6953 ql_log(ql_log_info, NULL, 0x0005, 6954 "QLogic Fibre Channel HBA Driver: %s.\n", 6955 qla2x00_version_str); 6956 ret = pci_register_driver(&qla2xxx_pci_driver); 6957 if (ret) { 6958 kmem_cache_destroy(srb_cachep); 6959 qlt_exit(); 6960 fc_release_transport(qla2xxx_transport_template); 6961 fc_release_transport(qla2xxx_transport_vport_template); 6962 ql_log(ql_log_fatal, NULL, 0x0006, 6963 "pci_register_driver failed...ret=%d Failing load!.\n", 6964 ret); 6965 } 6966 return ret; 6967 } 6968 6969 /** 6970 * qla2x00_module_exit - Module cleanup. 6971 **/ 6972 static void __exit 6973 qla2x00_module_exit(void) 6974 { 6975 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6976 pci_unregister_driver(&qla2xxx_pci_driver); 6977 qla2x00_release_firmware(); 6978 kmem_cache_destroy(srb_cachep); 6979 qlt_exit(); 6980 if (ctx_cachep) 6981 kmem_cache_destroy(ctx_cachep); 6982 fc_release_transport(qla2xxx_transport_template); 6983 fc_release_transport(qla2xxx_transport_vport_template); 6984 } 6985 6986 module_init(qla2x00_module_init); 6987 module_exit(qla2x00_module_exit); 6988 6989 MODULE_AUTHOR("QLogic Corporation"); 6990 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6991 MODULE_LICENSE("GPL"); 6992 MODULE_VERSION(QLA2XXX_VERSION); 6993 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6994 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6995 MODULE_FIRMWARE(FW_FILE_ISP2300); 6996 MODULE_FIRMWARE(FW_FILE_ISP2322); 6997 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6998 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6999