1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 2; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) " 51 "1: track usage per queue, 2: track usage per adapter"); 52 53 /* 54 * CT6 CTX allocation cache 55 */ 56 static struct kmem_cache *ctx_cachep; 57 /* 58 * error level for logging 59 */ 60 uint ql_errlev = 0x8001; 61 62 int ql2xsecenable; 63 module_param(ql2xsecenable, int, S_IRUGO); 64 MODULE_PARM_DESC(ql2xsecenable, 65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 66 67 static int ql2xenableclass2; 68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 69 MODULE_PARM_DESC(ql2xenableclass2, 70 "Specify if Class 2 operations are supported from the very " 71 "beginning. Default is 0 - class 2 not supported."); 72 73 74 int ql2xlogintimeout = 20; 75 module_param(ql2xlogintimeout, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xlogintimeout, 77 "Login timeout value in seconds."); 78 79 int qlport_down_retry; 80 module_param(qlport_down_retry, int, S_IRUGO); 81 MODULE_PARM_DESC(qlport_down_retry, 82 "Maximum number of command retries to a port that returns " 83 "a PORT-DOWN status."); 84 85 int ql2xplogiabsentdevice; 86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xplogiabsentdevice, 88 "Option to enable PLOGI to devices that are not present after " 89 "a Fabric scan. This is needed for several broken switches. " 90 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 91 92 int ql2xloginretrycount; 93 module_param(ql2xloginretrycount, int, S_IRUGO); 94 MODULE_PARM_DESC(ql2xloginretrycount, 95 "Specify an alternate value for the NVRAM login retry count."); 96 97 int ql2xallocfwdump = 1; 98 module_param(ql2xallocfwdump, int, S_IRUGO); 99 MODULE_PARM_DESC(ql2xallocfwdump, 100 "Option to enable allocation of memory for a firmware dump " 101 "during HBA initialization. Memory allocation requirements " 102 "vary by ISP type. Default is 1 - allocate memory."); 103 104 int ql2xextended_error_logging; 105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 107 MODULE_PARM_DESC(ql2xextended_error_logging, 108 "Option to enable extended error logging,\n" 109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 120 "\t\t0x1e400000 - Preferred value for capturing essential " 121 "debug information (equivalent to old " 122 "ql2xextended_error_logging=1).\n" 123 "\t\tDo LOGICAL OR of the value to enable more than one level"); 124 125 int ql2xextended_error_logging_ktrace = 1; 126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 128 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 129 130 int ql2xshiftctondsd = 6; 131 module_param(ql2xshiftctondsd, int, S_IRUGO); 132 MODULE_PARM_DESC(ql2xshiftctondsd, 133 "Set to control shifting of command type processing " 134 "based on total number of SG elements."); 135 136 int ql2xfdmienable = 1; 137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 139 MODULE_PARM_DESC(ql2xfdmienable, 140 "Enables FDMI registrations. " 141 "0 - no FDMI registrations. " 142 "1 - provide FDMI registrations (default)."); 143 144 #define MAX_Q_DEPTH 64 145 static int ql2xmaxqdepth = MAX_Q_DEPTH; 146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 147 MODULE_PARM_DESC(ql2xmaxqdepth, 148 "Maximum queue depth to set for each LUN. " 149 "Default is 64."); 150 151 int ql2xenabledif = 2; 152 module_param(ql2xenabledif, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xenabledif, 154 " Enable T10-CRC-DIF:\n" 155 " Default is 2.\n" 156 " 0 -- No DIF Support\n" 157 " 1 -- Enable DIF for all types\n" 158 " 2 -- Enable DIF for all types, except Type 0.\n"); 159 160 #if (IS_ENABLED(CONFIG_NVME_FC)) 161 int ql2xnvmeenable = 1; 162 #else 163 int ql2xnvmeenable; 164 #endif 165 module_param(ql2xnvmeenable, int, 0644); 166 MODULE_PARM_DESC(ql2xnvmeenable, 167 "Enables NVME support. " 168 "0 - no NVMe. Default is Y"); 169 170 int ql2xenablehba_err_chk = 2; 171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xenablehba_err_chk, 173 " Enable T10-CRC-DIF Error isolation by HBA:\n" 174 " Default is 2.\n" 175 " 0 -- Error isolation disabled\n" 176 " 1 -- Error isolation enabled only for DIX Type 0\n" 177 " 2 -- Error isolation enabled for all Types\n"); 178 179 int ql2xiidmaenable = 1; 180 module_param(ql2xiidmaenable, int, S_IRUGO); 181 MODULE_PARM_DESC(ql2xiidmaenable, 182 "Enables iIDMA settings " 183 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 184 185 int ql2xmqsupport = 1; 186 module_param(ql2xmqsupport, int, S_IRUGO); 187 MODULE_PARM_DESC(ql2xmqsupport, 188 "Enable on demand multiple queue pairs support " 189 "Default is 1 for supported. " 190 "Set it to 0 to turn off mq qpair support."); 191 192 int ql2xfwloadbin; 193 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 195 MODULE_PARM_DESC(ql2xfwloadbin, 196 "Option to specify location from which to load ISP firmware:.\n" 197 " 2 -- load firmware via the request_firmware() (hotplug).\n" 198 " interface.\n" 199 " 1 -- load firmware from flash.\n" 200 " 0 -- use default semantics.\n"); 201 202 int ql2xetsenable; 203 module_param(ql2xetsenable, int, S_IRUGO); 204 MODULE_PARM_DESC(ql2xetsenable, 205 "Enables firmware ETS burst." 206 "Default is 0 - skip ETS enablement."); 207 208 int ql2xdbwr = 1; 209 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 210 MODULE_PARM_DESC(ql2xdbwr, 211 "Option to specify scheme for request queue posting.\n" 212 " 0 -- Regular doorbell.\n" 213 " 1 -- CAMRAM doorbell (faster).\n"); 214 215 int ql2xgffidenable; 216 module_param(ql2xgffidenable, int, S_IRUGO); 217 MODULE_PARM_DESC(ql2xgffidenable, 218 "Enables GFF_ID checks of port type. " 219 "Default is 0 - Do not use GFF_ID information."); 220 221 int ql2xasynctmfenable = 1; 222 module_param(ql2xasynctmfenable, int, S_IRUGO); 223 MODULE_PARM_DESC(ql2xasynctmfenable, 224 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 225 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 226 227 int ql2xdontresethba; 228 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xdontresethba, 230 "Option to specify reset behaviour.\n" 231 " 0 (Default) -- Reset on failure.\n" 232 " 1 -- Do not reset on failure.\n"); 233 234 uint64_t ql2xmaxlun = MAX_LUNS; 235 module_param(ql2xmaxlun, ullong, S_IRUGO); 236 MODULE_PARM_DESC(ql2xmaxlun, 237 "Defines the maximum LU number to register with the SCSI " 238 "midlayer. Default is 65535."); 239 240 int ql2xmdcapmask = 0x1F; 241 module_param(ql2xmdcapmask, int, S_IRUGO); 242 MODULE_PARM_DESC(ql2xmdcapmask, 243 "Set the Minidump driver capture mask level. " 244 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 245 246 int ql2xmdenable = 1; 247 module_param(ql2xmdenable, int, S_IRUGO); 248 MODULE_PARM_DESC(ql2xmdenable, 249 "Enable/disable MiniDump. " 250 "0 - MiniDump disabled. " 251 "1 (Default) - MiniDump enabled."); 252 253 int ql2xexlogins; 254 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 255 MODULE_PARM_DESC(ql2xexlogins, 256 "Number of extended Logins. " 257 "0 (Default)- Disabled."); 258 259 int ql2xexchoffld = 1024; 260 module_param(ql2xexchoffld, uint, 0644); 261 MODULE_PARM_DESC(ql2xexchoffld, 262 "Number of target exchanges."); 263 264 int ql2xiniexchg = 1024; 265 module_param(ql2xiniexchg, uint, 0644); 266 MODULE_PARM_DESC(ql2xiniexchg, 267 "Number of initiator exchanges."); 268 269 int ql2xfwholdabts; 270 module_param(ql2xfwholdabts, int, S_IRUGO); 271 MODULE_PARM_DESC(ql2xfwholdabts, 272 "Allow FW to hold status IOCB until ABTS rsp received. " 273 "0 (Default) Do not set fw option. " 274 "1 - Set fw option to hold ABTS."); 275 276 int ql2xmvasynctoatio = 1; 277 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 278 MODULE_PARM_DESC(ql2xmvasynctoatio, 279 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 280 "0 (Default). Do not move IOCBs" 281 "1 - Move IOCBs."); 282 283 int ql2xautodetectsfp = 1; 284 module_param(ql2xautodetectsfp, int, 0444); 285 MODULE_PARM_DESC(ql2xautodetectsfp, 286 "Detect SFP range and set appropriate distance.\n" 287 "1 (Default): Enable\n"); 288 289 int ql2xenablemsix = 1; 290 module_param(ql2xenablemsix, int, 0444); 291 MODULE_PARM_DESC(ql2xenablemsix, 292 "Set to enable MSI or MSI-X interrupt mechanism.\n" 293 " Default is 1, enable MSI-X interrupt mechanism.\n" 294 " 0 -- enable traditional pin-based mechanism.\n" 295 " 1 -- enable MSI-X interrupt mechanism.\n" 296 " 2 -- enable MSI interrupt mechanism.\n"); 297 298 int qla2xuseresexchforels; 299 module_param(qla2xuseresexchforels, int, 0444); 300 MODULE_PARM_DESC(qla2xuseresexchforels, 301 "Reserve 1/2 of emergency exchanges for ELS.\n" 302 " 0 (default): disabled"); 303 304 static int ql2xprotmask; 305 module_param(ql2xprotmask, int, 0644); 306 MODULE_PARM_DESC(ql2xprotmask, 307 "Override DIF/DIX protection capabilities mask\n" 308 "Default is 0 which sets protection mask based on " 309 "capabilities reported by HBA firmware.\n"); 310 311 static int ql2xprotguard; 312 module_param(ql2xprotguard, int, 0644); 313 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 314 " 0 -- Let HBA firmware decide\n" 315 " 1 -- Force T10 CRC\n" 316 " 2 -- Force IP checksum\n"); 317 318 int ql2xdifbundlinginternalbuffers; 319 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 320 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 321 "Force using internal buffers for DIF information\n" 322 "0 (Default). Based on check.\n" 323 "1 Force using internal buffers\n"); 324 325 int ql2xsmartsan; 326 module_param(ql2xsmartsan, int, 0444); 327 module_param_named(smartsan, ql2xsmartsan, int, 0444); 328 MODULE_PARM_DESC(ql2xsmartsan, 329 "Send SmartSAN Management Attributes for FDMI Registration." 330 " Default is 0 - No SmartSAN registration," 331 " 1 - Register SmartSAN Management Attributes."); 332 333 int ql2xrdpenable; 334 module_param(ql2xrdpenable, int, 0444); 335 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 336 MODULE_PARM_DESC(ql2xrdpenable, 337 "Enables RDP responses. " 338 "0 - no RDP responses (default). " 339 "1 - provide RDP responses."); 340 int ql2xabts_wait_nvme = 1; 341 module_param(ql2xabts_wait_nvme, int, 0444); 342 MODULE_PARM_DESC(ql2xabts_wait_nvme, 343 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 344 345 346 static u32 ql2xdelay_before_pci_error_handling = 5; 347 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 348 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 349 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 350 351 static void qla2x00_clear_drv_active(struct qla_hw_data *); 352 static void qla2x00_free_device(scsi_qla_host_t *); 353 static void qla2xxx_map_queues(struct Scsi_Host *shost); 354 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 355 356 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 357 module_param(ql2xnvme_queues, uint, S_IRUGO); 358 MODULE_PARM_DESC(ql2xnvme_queues, 359 "Number of NVMe Queues that can be configured.\n" 360 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 361 "1 - Minimum number of queues supported\n" 362 "8 - Default value"); 363 364 int ql2xfc2target = 1; 365 module_param(ql2xfc2target, int, 0444); 366 MODULE_PARM_DESC(qla2xfc2target, 367 "Enables FC2 Target support. " 368 "0 - FC2 Target support is disabled. " 369 "1 - FC2 Target support is enabled (default)."); 370 371 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 372 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 373 374 /* TODO Convert to inlines 375 * 376 * Timer routines 377 */ 378 379 __inline__ void 380 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 381 { 382 timer_setup(&vha->timer, qla2x00_timer, 0); 383 vha->timer.expires = jiffies + interval * HZ; 384 add_timer(&vha->timer); 385 vha->timer_active = 1; 386 } 387 388 static inline void 389 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 390 { 391 /* Currently used for 82XX only. */ 392 if (vha->device_flags & DFLG_DEV_FAILED) { 393 ql_dbg(ql_dbg_timer, vha, 0x600d, 394 "Device in a failed state, returning.\n"); 395 return; 396 } 397 398 mod_timer(&vha->timer, jiffies + interval * HZ); 399 } 400 401 static __inline__ void 402 qla2x00_stop_timer(scsi_qla_host_t *vha) 403 { 404 del_timer_sync(&vha->timer); 405 vha->timer_active = 0; 406 } 407 408 static int qla2x00_do_dpc(void *data); 409 410 static void qla2x00_rst_aen(scsi_qla_host_t *); 411 412 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 413 struct req_que **, struct rsp_que **); 414 static void qla2x00_free_fw_dump(struct qla_hw_data *); 415 static void qla2x00_mem_free(struct qla_hw_data *); 416 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 417 struct qla_qpair *qpair); 418 419 /* -------------------------------------------------------------------------- */ 420 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 421 struct rsp_que *rsp) 422 { 423 struct qla_hw_data *ha = vha->hw; 424 425 rsp->qpair = ha->base_qpair; 426 rsp->req = req; 427 ha->base_qpair->hw = ha; 428 ha->base_qpair->req = req; 429 ha->base_qpair->rsp = rsp; 430 ha->base_qpair->vha = vha; 431 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 432 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 433 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 434 ha->base_qpair->srb_mempool = ha->srb_mempool; 435 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 436 INIT_LIST_HEAD(&ha->base_qpair->dsd_list); 437 ha->base_qpair->enable_class_2 = ql2xenableclass2; 438 /* init qpair to this cpu. Will adjust at run time. */ 439 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 440 ha->base_qpair->pdev = ha->pdev; 441 442 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 443 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 444 } 445 446 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 447 struct rsp_que *rsp) 448 { 449 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 450 451 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 452 GFP_KERNEL); 453 if (!ha->req_q_map) { 454 ql_log(ql_log_fatal, vha, 0x003b, 455 "Unable to allocate memory for request queue ptrs.\n"); 456 goto fail_req_map; 457 } 458 459 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 460 GFP_KERNEL); 461 if (!ha->rsp_q_map) { 462 ql_log(ql_log_fatal, vha, 0x003c, 463 "Unable to allocate memory for response queue ptrs.\n"); 464 goto fail_rsp_map; 465 } 466 467 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 468 if (ha->base_qpair == NULL) { 469 ql_log(ql_log_warn, vha, 0x00e0, 470 "Failed to allocate base queue pair memory.\n"); 471 goto fail_base_qpair; 472 } 473 474 qla_init_base_qpair(vha, req, rsp); 475 476 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 477 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 478 GFP_KERNEL); 479 if (!ha->queue_pair_map) { 480 ql_log(ql_log_fatal, vha, 0x0180, 481 "Unable to allocate memory for queue pair ptrs.\n"); 482 goto fail_qpair_map; 483 } 484 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 485 kfree(ha->queue_pair_map); 486 ha->queue_pair_map = NULL; 487 goto fail_qpair_map; 488 } 489 } 490 491 /* 492 * Make sure we record at least the request and response queue zero in 493 * case we need to free them if part of the probe fails. 494 */ 495 ha->rsp_q_map[0] = rsp; 496 ha->req_q_map[0] = req; 497 set_bit(0, ha->rsp_qid_map); 498 set_bit(0, ha->req_qid_map); 499 return 0; 500 501 fail_qpair_map: 502 kfree(ha->base_qpair); 503 ha->base_qpair = NULL; 504 fail_base_qpair: 505 kfree(ha->rsp_q_map); 506 ha->rsp_q_map = NULL; 507 fail_rsp_map: 508 kfree(ha->req_q_map); 509 ha->req_q_map = NULL; 510 fail_req_map: 511 return -ENOMEM; 512 } 513 514 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 515 { 516 if (IS_QLAFX00(ha)) { 517 if (req && req->ring_fx00) 518 dma_free_coherent(&ha->pdev->dev, 519 (req->length_fx00 + 1) * sizeof(request_t), 520 req->ring_fx00, req->dma_fx00); 521 } else if (req && req->ring) 522 dma_free_coherent(&ha->pdev->dev, 523 (req->length + 1) * sizeof(request_t), 524 req->ring, req->dma); 525 526 if (req) 527 kfree(req->outstanding_cmds); 528 529 kfree(req); 530 } 531 532 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 533 { 534 if (IS_QLAFX00(ha)) { 535 if (rsp && rsp->ring_fx00) 536 dma_free_coherent(&ha->pdev->dev, 537 (rsp->length_fx00 + 1) * sizeof(request_t), 538 rsp->ring_fx00, rsp->dma_fx00); 539 } else if (rsp && rsp->ring) { 540 dma_free_coherent(&ha->pdev->dev, 541 (rsp->length + 1) * sizeof(response_t), 542 rsp->ring, rsp->dma); 543 } 544 kfree(rsp); 545 } 546 547 static void qla2x00_free_queues(struct qla_hw_data *ha) 548 { 549 struct req_que *req; 550 struct rsp_que *rsp; 551 int cnt; 552 unsigned long flags; 553 554 if (ha->queue_pair_map) { 555 kfree(ha->queue_pair_map); 556 ha->queue_pair_map = NULL; 557 } 558 if (ha->base_qpair) { 559 kfree(ha->base_qpair); 560 ha->base_qpair = NULL; 561 } 562 563 qla_mapq_free_qp_cpu_map(ha); 564 spin_lock_irqsave(&ha->hardware_lock, flags); 565 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 566 if (!test_bit(cnt, ha->req_qid_map)) 567 continue; 568 569 req = ha->req_q_map[cnt]; 570 clear_bit(cnt, ha->req_qid_map); 571 ha->req_q_map[cnt] = NULL; 572 573 spin_unlock_irqrestore(&ha->hardware_lock, flags); 574 qla2x00_free_req_que(ha, req); 575 spin_lock_irqsave(&ha->hardware_lock, flags); 576 } 577 spin_unlock_irqrestore(&ha->hardware_lock, flags); 578 579 kfree(ha->req_q_map); 580 ha->req_q_map = NULL; 581 582 583 spin_lock_irqsave(&ha->hardware_lock, flags); 584 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 585 if (!test_bit(cnt, ha->rsp_qid_map)) 586 continue; 587 588 rsp = ha->rsp_q_map[cnt]; 589 clear_bit(cnt, ha->rsp_qid_map); 590 ha->rsp_q_map[cnt] = NULL; 591 spin_unlock_irqrestore(&ha->hardware_lock, flags); 592 qla2x00_free_rsp_que(ha, rsp); 593 spin_lock_irqsave(&ha->hardware_lock, flags); 594 } 595 spin_unlock_irqrestore(&ha->hardware_lock, flags); 596 597 kfree(ha->rsp_q_map); 598 ha->rsp_q_map = NULL; 599 } 600 601 static char * 602 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 603 { 604 struct qla_hw_data *ha = vha->hw; 605 static const char *const pci_bus_modes[] = { 606 "33", "66", "100", "133", 607 }; 608 uint16_t pci_bus; 609 610 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 611 if (pci_bus) { 612 snprintf(str, str_len, "PCI-X (%s MHz)", 613 pci_bus_modes[pci_bus]); 614 } else { 615 pci_bus = (ha->pci_attr & BIT_8) >> 8; 616 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 617 } 618 619 return str; 620 } 621 622 static char * 623 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 624 { 625 static const char *const pci_bus_modes[] = { 626 "33", "66", "100", "133", 627 }; 628 struct qla_hw_data *ha = vha->hw; 629 uint32_t pci_bus; 630 631 if (pci_is_pcie(ha->pdev)) { 632 uint32_t lstat, lspeed, lwidth; 633 const char *speed_str; 634 635 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 636 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat); 637 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat); 638 639 switch (lspeed) { 640 case 1: 641 speed_str = "2.5GT/s"; 642 break; 643 case 2: 644 speed_str = "5.0GT/s"; 645 break; 646 case 3: 647 speed_str = "8.0GT/s"; 648 break; 649 case 4: 650 speed_str = "16.0GT/s"; 651 break; 652 default: 653 speed_str = "<unknown>"; 654 break; 655 } 656 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 657 658 return str; 659 } 660 661 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 662 if (pci_bus == 0 || pci_bus == 8) 663 snprintf(str, str_len, "PCI (%s MHz)", 664 pci_bus_modes[pci_bus >> 3]); 665 else 666 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 667 pci_bus & 4 ? 2 : 1, 668 pci_bus_modes[pci_bus & 3]); 669 670 return str; 671 } 672 673 static char * 674 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 675 { 676 char un_str[10]; 677 struct qla_hw_data *ha = vha->hw; 678 679 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 680 ha->fw_minor_version, ha->fw_subminor_version); 681 682 if (ha->fw_attributes & BIT_9) { 683 strcat(str, "FLX"); 684 return (str); 685 } 686 687 switch (ha->fw_attributes & 0xFF) { 688 case 0x7: 689 strcat(str, "EF"); 690 break; 691 case 0x17: 692 strcat(str, "TP"); 693 break; 694 case 0x37: 695 strcat(str, "IP"); 696 break; 697 case 0x77: 698 strcat(str, "VI"); 699 break; 700 default: 701 sprintf(un_str, "(%x)", ha->fw_attributes); 702 strcat(str, un_str); 703 break; 704 } 705 if (ha->fw_attributes & 0x100) 706 strcat(str, "X"); 707 708 return (str); 709 } 710 711 static char * 712 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 713 { 714 struct qla_hw_data *ha = vha->hw; 715 716 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 717 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 718 return str; 719 } 720 721 void qla2x00_sp_free_dma(srb_t *sp) 722 { 723 struct qla_hw_data *ha = sp->vha->hw; 724 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 725 726 if (sp->flags & SRB_DMA_VALID) { 727 scsi_dma_unmap(cmd); 728 sp->flags &= ~SRB_DMA_VALID; 729 } 730 731 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 732 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 733 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 734 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 735 } 736 737 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 738 /* List assured to be having elements */ 739 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 740 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 741 } 742 743 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 744 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 745 746 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 747 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 748 } 749 750 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 751 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 752 753 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 754 ctx1->fcp_cmnd_dma); 755 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 756 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 757 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 758 } 759 760 if (sp->flags & SRB_GOT_BUF) 761 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 762 } 763 764 void qla2x00_sp_compl(srb_t *sp, int res) 765 { 766 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 767 struct completion *comp = sp->comp; 768 769 /* kref: INIT */ 770 kref_put(&sp->cmd_kref, qla2x00_sp_release); 771 cmd->result = res; 772 sp->type = 0; 773 scsi_done(cmd); 774 if (comp) 775 complete(comp); 776 } 777 778 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 779 { 780 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 781 struct qla_hw_data *ha = sp->fcport->vha->hw; 782 783 if (sp->flags & SRB_DMA_VALID) { 784 scsi_dma_unmap(cmd); 785 sp->flags &= ~SRB_DMA_VALID; 786 } 787 788 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 789 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 790 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 791 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 792 } 793 794 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 795 /* List assured to be having elements */ 796 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 797 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 798 } 799 800 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 801 struct crc_context *difctx = sp->u.scmd.crc_ctx; 802 struct dsd_dma *dif_dsd, *nxt_dsd; 803 804 list_for_each_entry_safe(dif_dsd, nxt_dsd, 805 &difctx->ldif_dma_hndl_list, list) { 806 list_del(&dif_dsd->list); 807 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 808 dif_dsd->dsd_list_dma); 809 kfree(dif_dsd); 810 difctx->no_dif_bundl--; 811 } 812 813 list_for_each_entry_safe(dif_dsd, nxt_dsd, 814 &difctx->ldif_dsd_list, list) { 815 list_del(&dif_dsd->list); 816 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 817 dif_dsd->dsd_list_dma); 818 kfree(dif_dsd); 819 difctx->no_ldif_dsd--; 820 } 821 822 if (difctx->no_ldif_dsd) { 823 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 824 "%s: difctx->no_ldif_dsd=%x\n", 825 __func__, difctx->no_ldif_dsd); 826 } 827 828 if (difctx->no_dif_bundl) { 829 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 830 "%s: difctx->no_dif_bundl=%x\n", 831 __func__, difctx->no_dif_bundl); 832 } 833 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 834 } 835 836 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 837 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 838 839 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 840 ctx1->fcp_cmnd_dma); 841 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 842 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 843 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 844 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 845 } 846 847 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 848 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 849 850 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 851 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 852 } 853 854 if (sp->flags & SRB_GOT_BUF) 855 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 856 } 857 858 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 859 { 860 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 861 struct completion *comp = sp->comp; 862 863 /* ref: INIT */ 864 kref_put(&sp->cmd_kref, qla2x00_sp_release); 865 cmd->result = res; 866 sp->type = 0; 867 scsi_done(cmd); 868 if (comp) 869 complete(comp); 870 } 871 872 static int 873 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 874 { 875 scsi_qla_host_t *vha = shost_priv(host); 876 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 877 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 878 struct qla_hw_data *ha = vha->hw; 879 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 880 srb_t *sp; 881 int rval; 882 883 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 884 WARN_ON_ONCE(!rport)) { 885 cmd->result = DID_NO_CONNECT << 16; 886 goto qc24_fail_command; 887 } 888 889 if (ha->mqenable) { 890 uint32_t tag; 891 uint16_t hwq; 892 struct qla_qpair *qpair = NULL; 893 894 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 895 hwq = blk_mq_unique_tag_to_hwq(tag); 896 qpair = ha->queue_pair_map[hwq]; 897 898 if (qpair) 899 return qla2xxx_mqueuecommand(host, cmd, qpair); 900 } 901 902 if (ha->flags.eeh_busy) { 903 if (ha->flags.pci_channel_io_perm_failure) { 904 ql_dbg(ql_dbg_aer, vha, 0x9010, 905 "PCI Channel IO permanent failure, exiting " 906 "cmd=%p.\n", cmd); 907 cmd->result = DID_NO_CONNECT << 16; 908 } else { 909 ql_dbg(ql_dbg_aer, vha, 0x9011, 910 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 911 cmd->result = DID_REQUEUE << 16; 912 } 913 goto qc24_fail_command; 914 } 915 916 rval = fc_remote_port_chkready(rport); 917 if (rval) { 918 cmd->result = rval; 919 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 920 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 921 cmd, rval); 922 goto qc24_fail_command; 923 } 924 925 if (!vha->flags.difdix_supported && 926 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 927 ql_dbg(ql_dbg_io, vha, 0x3004, 928 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 929 cmd); 930 cmd->result = DID_NO_CONNECT << 16; 931 goto qc24_fail_command; 932 } 933 934 if (!fcport || fcport->deleted) { 935 cmd->result = DID_IMM_RETRY << 16; 936 goto qc24_fail_command; 937 } 938 939 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 940 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 941 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 942 ql_dbg(ql_dbg_io, vha, 0x3005, 943 "Returning DNC, fcport_state=%d loop_state=%d.\n", 944 atomic_read(&fcport->state), 945 atomic_read(&base_vha->loop_state)); 946 cmd->result = DID_NO_CONNECT << 16; 947 goto qc24_fail_command; 948 } 949 goto qc24_target_busy; 950 } 951 952 /* 953 * Return target busy if we've received a non-zero retry_delay_timer 954 * in a FCP_RSP. 955 */ 956 if (fcport->retry_delay_timestamp == 0) { 957 /* retry delay not set */ 958 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 959 fcport->retry_delay_timestamp = 0; 960 else 961 goto qc24_target_busy; 962 963 sp = scsi_cmd_priv(cmd); 964 /* ref: INIT */ 965 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 966 967 sp->u.scmd.cmd = cmd; 968 sp->type = SRB_SCSI_CMD; 969 sp->free = qla2x00_sp_free_dma; 970 sp->done = qla2x00_sp_compl; 971 972 rval = ha->isp_ops->start_scsi(sp); 973 if (rval != QLA_SUCCESS) { 974 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 975 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 976 goto qc24_host_busy_free_sp; 977 } 978 979 return 0; 980 981 qc24_host_busy_free_sp: 982 /* ref: INIT */ 983 kref_put(&sp->cmd_kref, qla2x00_sp_release); 984 985 qc24_target_busy: 986 return SCSI_MLQUEUE_TARGET_BUSY; 987 988 qc24_fail_command: 989 scsi_done(cmd); 990 991 return 0; 992 } 993 994 /* For MQ supported I/O */ 995 int 996 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 997 struct qla_qpair *qpair) 998 { 999 scsi_qla_host_t *vha = shost_priv(host); 1000 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1001 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1002 struct qla_hw_data *ha = vha->hw; 1003 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1004 srb_t *sp; 1005 int rval; 1006 1007 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1008 if (rval) { 1009 cmd->result = rval; 1010 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1011 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1012 cmd, rval); 1013 goto qc24_fail_command; 1014 } 1015 1016 if (!qpair->online) { 1017 ql_dbg(ql_dbg_io, vha, 0x3077, 1018 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1019 cmd->result = DID_NO_CONNECT << 16; 1020 goto qc24_fail_command; 1021 } 1022 1023 if (!fcport || fcport->deleted) { 1024 cmd->result = DID_IMM_RETRY << 16; 1025 goto qc24_fail_command; 1026 } 1027 1028 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1029 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1030 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1031 ql_dbg(ql_dbg_io, vha, 0x3077, 1032 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1033 atomic_read(&fcport->state), 1034 atomic_read(&base_vha->loop_state)); 1035 cmd->result = DID_NO_CONNECT << 16; 1036 goto qc24_fail_command; 1037 } 1038 goto qc24_target_busy; 1039 } 1040 1041 /* 1042 * Return target busy if we've received a non-zero retry_delay_timer 1043 * in a FCP_RSP. 1044 */ 1045 if (fcport->retry_delay_timestamp == 0) { 1046 /* retry delay not set */ 1047 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1048 fcport->retry_delay_timestamp = 0; 1049 else 1050 goto qc24_target_busy; 1051 1052 sp = scsi_cmd_priv(cmd); 1053 /* ref: INIT */ 1054 qla2xxx_init_sp(sp, vha, qpair, fcport); 1055 1056 sp->u.scmd.cmd = cmd; 1057 sp->type = SRB_SCSI_CMD; 1058 sp->free = qla2xxx_qpair_sp_free_dma; 1059 sp->done = qla2xxx_qpair_sp_compl; 1060 1061 rval = ha->isp_ops->start_scsi_mq(sp); 1062 if (rval != QLA_SUCCESS) { 1063 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1064 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1065 goto qc24_host_busy_free_sp; 1066 } 1067 1068 return 0; 1069 1070 qc24_host_busy_free_sp: 1071 /* ref: INIT */ 1072 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1073 1074 qc24_target_busy: 1075 return SCSI_MLQUEUE_TARGET_BUSY; 1076 1077 qc24_fail_command: 1078 scsi_done(cmd); 1079 1080 return 0; 1081 } 1082 1083 /* 1084 * qla2x00_wait_for_hba_online 1085 * Wait till the HBA is online after going through 1086 * <= MAX_RETRIES_OF_ISP_ABORT or 1087 * finally HBA is disabled ie marked offline 1088 * 1089 * Input: 1090 * ha - pointer to host adapter structure 1091 * 1092 * Note: 1093 * Does context switching-Release SPIN_LOCK 1094 * (if any) before calling this routine. 1095 * 1096 * Return: 1097 * Success (Adapter is online) : 0 1098 * Failed (Adapter is offline/disabled) : 1 1099 */ 1100 int 1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1102 { 1103 int return_status; 1104 unsigned long wait_online; 1105 struct qla_hw_data *ha = vha->hw; 1106 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1107 1108 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1109 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1110 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1111 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1112 ha->dpc_active) && time_before(jiffies, wait_online)) { 1113 1114 msleep(1000); 1115 } 1116 if (base_vha->flags.online) 1117 return_status = QLA_SUCCESS; 1118 else 1119 return_status = QLA_FUNCTION_FAILED; 1120 1121 return (return_status); 1122 } 1123 1124 static inline int test_fcport_count(scsi_qla_host_t *vha) 1125 { 1126 struct qla_hw_data *ha = vha->hw; 1127 unsigned long flags; 1128 int res; 1129 /* Return 0 = sleep, x=wake */ 1130 1131 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1132 ql_dbg(ql_dbg_init, vha, 0x00ec, 1133 "tgt %p, fcport_count=%d\n", 1134 vha, vha->fcport_count); 1135 res = (vha->fcport_count == 0); 1136 if (res) { 1137 struct fc_port *fcport; 1138 1139 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1140 if (fcport->deleted != QLA_SESS_DELETED) { 1141 /* session(s) may not be fully logged in 1142 * (ie fcport_count=0), but session 1143 * deletion thread(s) may be inflight. 1144 */ 1145 1146 res = 0; 1147 break; 1148 } 1149 } 1150 } 1151 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1152 1153 return res; 1154 } 1155 1156 /* 1157 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1158 * it has dependency on UNLOADING flag to stop device discovery 1159 */ 1160 void 1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1162 { 1163 u8 i; 1164 1165 qla2x00_mark_all_devices_lost(vha); 1166 1167 for (i = 0; i < 10; i++) { 1168 if (wait_event_timeout(vha->fcport_waitQ, 1169 test_fcport_count(vha), HZ) > 0) 1170 break; 1171 } 1172 1173 flush_workqueue(vha->hw->wq); 1174 } 1175 1176 /* 1177 * qla2x00_wait_for_hba_ready 1178 * Wait till the HBA is ready before doing driver unload 1179 * 1180 * Input: 1181 * ha - pointer to host adapter structure 1182 * 1183 * Note: 1184 * Does context switching-Release SPIN_LOCK 1185 * (if any) before calling this routine. 1186 * 1187 */ 1188 static void 1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1190 { 1191 struct qla_hw_data *ha = vha->hw; 1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1195 ha->flags.mbox_busy) || 1196 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1197 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1198 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1199 break; 1200 msleep(1000); 1201 } 1202 } 1203 1204 int 1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1206 { 1207 int return_status; 1208 unsigned long wait_reset; 1209 struct qla_hw_data *ha = vha->hw; 1210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1211 1212 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1213 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1214 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1215 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1216 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1217 1218 msleep(1000); 1219 1220 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1221 ha->flags.chip_reset_done) 1222 break; 1223 } 1224 if (ha->flags.chip_reset_done) 1225 return_status = QLA_SUCCESS; 1226 else 1227 return_status = QLA_FUNCTION_FAILED; 1228 1229 return return_status; 1230 } 1231 1232 /************************************************************************** 1233 * qla2xxx_eh_abort 1234 * 1235 * Description: 1236 * The abort function will abort the specified command. 1237 * 1238 * Input: 1239 * cmd = Linux SCSI command packet to be aborted. 1240 * 1241 * Returns: 1242 * Either SUCCESS or FAILED. 1243 * 1244 * Note: 1245 * Only return FAILED if command not returned by firmware. 1246 **************************************************************************/ 1247 static int 1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1249 { 1250 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1251 DECLARE_COMPLETION_ONSTACK(comp); 1252 srb_t *sp; 1253 int ret; 1254 unsigned int id; 1255 uint64_t lun; 1256 int rval; 1257 struct qla_hw_data *ha = vha->hw; 1258 uint32_t ratov_j; 1259 struct qla_qpair *qpair; 1260 unsigned long flags; 1261 int fast_fail_status = SUCCESS; 1262 1263 if (qla2x00_isp_reg_stat(ha)) { 1264 ql_log(ql_log_info, vha, 0x8042, 1265 "PCI/Register disconnect, exiting.\n"); 1266 qla_pci_set_eeh_busy(vha); 1267 return FAILED; 1268 } 1269 1270 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1271 ret = fc_block_scsi_eh(cmd); 1272 if (ret != 0) 1273 fast_fail_status = ret; 1274 1275 sp = scsi_cmd_priv(cmd); 1276 qpair = sp->qpair; 1277 1278 vha->cmd_timeout_cnt++; 1279 1280 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1281 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1282 1283 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1284 sp->comp = ∁ 1285 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1286 1287 1288 id = cmd->device->id; 1289 lun = cmd->device->lun; 1290 1291 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1292 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1293 vha->host_no, id, lun, sp, cmd, sp->handle); 1294 1295 /* 1296 * Abort will release the original Command/sp from FW. Let the 1297 * original command call scsi_done. In return, he will wakeup 1298 * this sleeping thread. 1299 */ 1300 rval = ha->isp_ops->abort_command(sp); 1301 1302 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1303 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1304 1305 /* Wait for the command completion. */ 1306 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1307 ratov_j = msecs_to_jiffies(ratov_j); 1308 switch (rval) { 1309 case QLA_SUCCESS: 1310 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1311 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1312 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1313 __func__, ha->r_a_tov/10); 1314 ret = FAILED; 1315 } else { 1316 ret = fast_fail_status; 1317 } 1318 break; 1319 default: 1320 ret = FAILED; 1321 break; 1322 } 1323 1324 sp->comp = NULL; 1325 1326 ql_log(ql_log_info, vha, 0x801c, 1327 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1328 vha->host_no, id, lun, ret); 1329 1330 return ret; 1331 } 1332 1333 #define ABORT_POLLING_PERIOD 1000 1334 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1335 1336 /* 1337 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1338 */ 1339 static int 1340 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1341 uint64_t l, enum nexus_wait_type type) 1342 { 1343 int cnt, match, status; 1344 unsigned long flags; 1345 scsi_qla_host_t *vha = qpair->vha; 1346 struct req_que *req = qpair->req; 1347 srb_t *sp; 1348 struct scsi_cmnd *cmd; 1349 unsigned long wait_iter = ABORT_WAIT_ITER; 1350 bool found; 1351 struct qla_hw_data *ha = vha->hw; 1352 1353 status = QLA_SUCCESS; 1354 1355 while (wait_iter--) { 1356 found = false; 1357 1358 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1360 sp = req->outstanding_cmds[cnt]; 1361 if (!sp) 1362 continue; 1363 if (sp->type != SRB_SCSI_CMD) 1364 continue; 1365 if (vha->vp_idx != sp->vha->vp_idx) 1366 continue; 1367 match = 0; 1368 cmd = GET_CMD_SP(sp); 1369 switch (type) { 1370 case WAIT_HOST: 1371 match = 1; 1372 break; 1373 case WAIT_TARGET: 1374 if (sp->fcport) 1375 match = sp->fcport->d_id.b24 == t; 1376 else 1377 match = 0; 1378 break; 1379 case WAIT_LUN: 1380 if (sp->fcport) 1381 match = (sp->fcport->d_id.b24 == t && 1382 cmd->device->lun == l); 1383 else 1384 match = 0; 1385 break; 1386 } 1387 if (!match) 1388 continue; 1389 1390 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1391 1392 if (unlikely(pci_channel_offline(ha->pdev)) || 1393 ha->flags.eeh_busy) { 1394 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1395 "Return:eh_wait.\n"); 1396 return status; 1397 } 1398 1399 /* 1400 * SRB_SCSI_CMD is still in the outstanding_cmds array. 1401 * it means scsi_done has not called. Wait for it to 1402 * clear from outstanding_cmds. 1403 */ 1404 msleep(ABORT_POLLING_PERIOD); 1405 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1406 found = true; 1407 } 1408 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1409 1410 if (!found) 1411 break; 1412 } 1413 1414 if (wait_iter == -1) 1415 status = QLA_FUNCTION_FAILED; 1416 1417 return status; 1418 } 1419 1420 int 1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1422 uint64_t l, enum nexus_wait_type type) 1423 { 1424 struct qla_qpair *qpair; 1425 struct qla_hw_data *ha = vha->hw; 1426 int i, status = QLA_SUCCESS; 1427 1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1429 type); 1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1431 qpair = ha->queue_pair_map[i]; 1432 if (!qpair) 1433 continue; 1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1435 type); 1436 } 1437 return status; 1438 } 1439 1440 static char *reset_errors[] = { 1441 "HBA not online", 1442 "HBA not ready", 1443 "Task management failed", 1444 "Waiting for command completions", 1445 }; 1446 1447 static int 1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 struct scsi_device *sdev = cmd->device; 1451 scsi_qla_host_t *vha = shost_priv(sdev->host); 1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1454 struct qla_hw_data *ha = vha->hw; 1455 int err; 1456 1457 if (qla2x00_isp_reg_stat(ha)) { 1458 ql_log(ql_log_info, vha, 0x803e, 1459 "PCI/Register disconnect, exiting.\n"); 1460 qla_pci_set_eeh_busy(vha); 1461 return FAILED; 1462 } 1463 1464 if (!fcport) { 1465 return FAILED; 1466 } 1467 1468 err = fc_block_rport(rport); 1469 if (err != 0) 1470 return err; 1471 1472 if (fcport->deleted) 1473 return FAILED; 1474 1475 ql_log(ql_log_info, vha, 0x8009, 1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1477 sdev->id, sdev->lun, cmd); 1478 1479 err = 0; 1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1481 ql_log(ql_log_warn, vha, 0x800a, 1482 "Wait for hba online failed for cmd=%p.\n", cmd); 1483 goto eh_reset_failed; 1484 } 1485 err = 2; 1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1487 != QLA_SUCCESS) { 1488 ql_log(ql_log_warn, vha, 0x800c, 1489 "do_reset failed for cmd=%p.\n", cmd); 1490 goto eh_reset_failed; 1491 } 1492 err = 3; 1493 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 1494 cmd->device->lun, 1495 WAIT_LUN) != QLA_SUCCESS) { 1496 ql_log(ql_log_warn, vha, 0x800d, 1497 "wait for pending cmds failed for cmd=%p.\n", cmd); 1498 goto eh_reset_failed; 1499 } 1500 1501 ql_log(ql_log_info, vha, 0x800e, 1502 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1503 vha->host_no, sdev->id, sdev->lun, cmd); 1504 1505 return SUCCESS; 1506 1507 eh_reset_failed: 1508 ql_log(ql_log_info, vha, 0x800f, 1509 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1510 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1511 cmd); 1512 vha->reset_cmd_err_cnt++; 1513 return FAILED; 1514 } 1515 1516 static int 1517 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1518 { 1519 struct scsi_device *sdev = cmd->device; 1520 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1521 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1522 struct qla_hw_data *ha = vha->hw; 1523 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1524 int err; 1525 1526 if (qla2x00_isp_reg_stat(ha)) { 1527 ql_log(ql_log_info, vha, 0x803f, 1528 "PCI/Register disconnect, exiting.\n"); 1529 qla_pci_set_eeh_busy(vha); 1530 return FAILED; 1531 } 1532 1533 if (!fcport) { 1534 return FAILED; 1535 } 1536 1537 err = fc_block_rport(rport); 1538 if (err != 0) 1539 return err; 1540 1541 if (fcport->deleted) 1542 return FAILED; 1543 1544 ql_log(ql_log_info, vha, 0x8009, 1545 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1546 sdev->id, cmd); 1547 1548 err = 0; 1549 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1550 ql_log(ql_log_warn, vha, 0x800a, 1551 "Wait for hba online failed for cmd=%p.\n", cmd); 1552 goto eh_reset_failed; 1553 } 1554 err = 2; 1555 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1556 ql_log(ql_log_warn, vha, 0x800c, 1557 "target_reset failed for cmd=%p.\n", cmd); 1558 goto eh_reset_failed; 1559 } 1560 err = 3; 1561 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0, 1562 WAIT_TARGET) != QLA_SUCCESS) { 1563 ql_log(ql_log_warn, vha, 0x800d, 1564 "wait for pending cmds failed for cmd=%p.\n", cmd); 1565 goto eh_reset_failed; 1566 } 1567 1568 ql_log(ql_log_info, vha, 0x800e, 1569 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1570 vha->host_no, sdev->id, cmd); 1571 1572 return SUCCESS; 1573 1574 eh_reset_failed: 1575 ql_log(ql_log_info, vha, 0x800f, 1576 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1577 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1578 cmd); 1579 vha->reset_cmd_err_cnt++; 1580 return FAILED; 1581 } 1582 1583 /************************************************************************** 1584 * qla2xxx_eh_bus_reset 1585 * 1586 * Description: 1587 * The bus reset function will reset the bus and abort any executing 1588 * commands. 1589 * 1590 * Input: 1591 * cmd = Linux SCSI command packet of the command that cause the 1592 * bus reset. 1593 * 1594 * Returns: 1595 * SUCCESS/FAILURE (defined as macro in scsi.h). 1596 * 1597 **************************************************************************/ 1598 static int 1599 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1600 { 1601 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1602 int ret = FAILED; 1603 unsigned int id; 1604 uint64_t lun; 1605 struct qla_hw_data *ha = vha->hw; 1606 1607 if (qla2x00_isp_reg_stat(ha)) { 1608 ql_log(ql_log_info, vha, 0x8040, 1609 "PCI/Register disconnect, exiting.\n"); 1610 qla_pci_set_eeh_busy(vha); 1611 return FAILED; 1612 } 1613 1614 id = cmd->device->id; 1615 lun = cmd->device->lun; 1616 1617 if (qla2x00_chip_is_down(vha)) 1618 return ret; 1619 1620 ql_log(ql_log_info, vha, 0x8012, 1621 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1622 1623 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1624 ql_log(ql_log_fatal, vha, 0x8013, 1625 "Wait for hba online failed board disabled.\n"); 1626 goto eh_bus_reset_done; 1627 } 1628 1629 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1630 ret = SUCCESS; 1631 1632 if (ret == FAILED) 1633 goto eh_bus_reset_done; 1634 1635 /* Flush outstanding commands. */ 1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1637 QLA_SUCCESS) { 1638 ql_log(ql_log_warn, vha, 0x8014, 1639 "Wait for pending commands failed.\n"); 1640 ret = FAILED; 1641 } 1642 1643 eh_bus_reset_done: 1644 ql_log(ql_log_warn, vha, 0x802b, 1645 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1646 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1647 1648 return ret; 1649 } 1650 1651 /************************************************************************** 1652 * qla2xxx_eh_host_reset 1653 * 1654 * Description: 1655 * The reset function will reset the Adapter. 1656 * 1657 * Input: 1658 * cmd = Linux SCSI command packet of the command that cause the 1659 * adapter reset. 1660 * 1661 * Returns: 1662 * Either SUCCESS or FAILED. 1663 * 1664 * Note: 1665 **************************************************************************/ 1666 static int 1667 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1668 { 1669 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1670 struct qla_hw_data *ha = vha->hw; 1671 int ret = FAILED; 1672 unsigned int id; 1673 uint64_t lun; 1674 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1675 1676 if (qla2x00_isp_reg_stat(ha)) { 1677 ql_log(ql_log_info, vha, 0x8041, 1678 "PCI/Register disconnect, exiting.\n"); 1679 qla_pci_set_eeh_busy(vha); 1680 return SUCCESS; 1681 } 1682 1683 id = cmd->device->id; 1684 lun = cmd->device->lun; 1685 1686 ql_log(ql_log_info, vha, 0x8018, 1687 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1688 1689 /* 1690 * No point in issuing another reset if one is active. Also do not 1691 * attempt a reset if we are updating flash. 1692 */ 1693 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1694 goto eh_host_reset_lock; 1695 1696 if (vha != base_vha) { 1697 if (qla2x00_vp_abort_isp(vha)) 1698 goto eh_host_reset_lock; 1699 } else { 1700 if (IS_P3P_TYPE(vha->hw)) { 1701 if (!qla82xx_fcoe_ctx_reset(vha)) { 1702 /* Ctx reset success */ 1703 ret = SUCCESS; 1704 goto eh_host_reset_lock; 1705 } 1706 /* fall thru if ctx reset failed */ 1707 } 1708 if (ha->wq) 1709 flush_workqueue(ha->wq); 1710 1711 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1712 if (ha->isp_ops->abort_isp(base_vha)) { 1713 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1714 /* failed. schedule dpc to try */ 1715 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1716 1717 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1718 ql_log(ql_log_warn, vha, 0x802a, 1719 "wait for hba online failed.\n"); 1720 goto eh_host_reset_lock; 1721 } 1722 } 1723 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1724 } 1725 1726 /* Waiting for command to be returned to OS.*/ 1727 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1728 QLA_SUCCESS) 1729 ret = SUCCESS; 1730 1731 eh_host_reset_lock: 1732 ql_log(ql_log_info, vha, 0x8017, 1733 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1734 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1735 1736 return ret; 1737 } 1738 1739 /* 1740 * qla2x00_loop_reset 1741 * Issue loop reset. 1742 * 1743 * Input: 1744 * ha = adapter block pointer. 1745 * 1746 * Returns: 1747 * 0 = success 1748 */ 1749 int 1750 qla2x00_loop_reset(scsi_qla_host_t *vha) 1751 { 1752 int ret; 1753 struct qla_hw_data *ha = vha->hw; 1754 1755 if (IS_QLAFX00(ha)) 1756 return QLA_SUCCESS; 1757 1758 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1759 atomic_set(&vha->loop_state, LOOP_DOWN); 1760 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1761 qla2x00_mark_all_devices_lost(vha); 1762 ret = qla2x00_full_login_lip(vha); 1763 if (ret != QLA_SUCCESS) { 1764 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1765 "full_login_lip=%d.\n", ret); 1766 } 1767 } 1768 1769 if (ha->flags.enable_lip_reset) { 1770 ret = qla2x00_lip_reset(vha); 1771 if (ret != QLA_SUCCESS) 1772 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1773 "lip_reset failed (%d).\n", ret); 1774 } 1775 1776 /* Issue marker command only when we are going to start the I/O */ 1777 vha->marker_needed = 1; 1778 1779 return QLA_SUCCESS; 1780 } 1781 1782 /* 1783 * The caller must ensure that no completion interrupts will happen 1784 * while this function is in progress. 1785 */ 1786 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1787 unsigned long *flags) 1788 __releases(qp->qp_lock_ptr) 1789 __acquires(qp->qp_lock_ptr) 1790 { 1791 DECLARE_COMPLETION_ONSTACK(comp); 1792 scsi_qla_host_t *vha = qp->vha; 1793 struct qla_hw_data *ha = vha->hw; 1794 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1795 int rval; 1796 bool ret_cmd; 1797 uint32_t ratov_j; 1798 1799 lockdep_assert_held(qp->qp_lock_ptr); 1800 1801 if (qla2x00_chip_is_down(vha)) { 1802 sp->done(sp, res); 1803 return; 1804 } 1805 1806 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1807 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1808 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1809 !qla2x00_isp_reg_stat(ha))) { 1810 if (sp->comp) { 1811 sp->done(sp, res); 1812 return; 1813 } 1814 1815 sp->comp = ∁ 1816 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1817 1818 rval = ha->isp_ops->abort_command(sp); 1819 /* Wait for command completion. */ 1820 ret_cmd = false; 1821 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1822 ratov_j = msecs_to_jiffies(ratov_j); 1823 switch (rval) { 1824 case QLA_SUCCESS: 1825 if (wait_for_completion_timeout(&comp, ratov_j)) { 1826 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1827 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1828 __func__, ha->r_a_tov/10); 1829 ret_cmd = true; 1830 } 1831 /* else FW return SP to driver */ 1832 break; 1833 default: 1834 ret_cmd = true; 1835 break; 1836 } 1837 1838 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1839 switch (sp->type) { 1840 case SRB_SCSI_CMD: 1841 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1842 sp->done(sp, res); 1843 break; 1844 default: 1845 if (ret_cmd) 1846 sp->done(sp, res); 1847 break; 1848 } 1849 } else { 1850 sp->done(sp, res); 1851 } 1852 } 1853 1854 /* 1855 * The caller must ensure that no completion interrupts will happen 1856 * while this function is in progress. 1857 */ 1858 static void 1859 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1860 { 1861 int cnt; 1862 unsigned long flags; 1863 srb_t *sp; 1864 scsi_qla_host_t *vha = qp->vha; 1865 struct qla_hw_data *ha = vha->hw; 1866 struct req_que *req; 1867 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1868 struct qla_tgt_cmd *cmd; 1869 1870 if (!ha->req_q_map) 1871 return; 1872 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1873 req = qp->req; 1874 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1875 sp = req->outstanding_cmds[cnt]; 1876 if (sp) { 1877 if (qla2x00_chip_is_down(vha)) { 1878 req->outstanding_cmds[cnt] = NULL; 1879 sp->done(sp, res); 1880 continue; 1881 } 1882 1883 switch (sp->cmd_type) { 1884 case TYPE_SRB: 1885 qla2x00_abort_srb(qp, sp, res, &flags); 1886 break; 1887 case TYPE_TGT_CMD: 1888 if (!vha->hw->tgt.tgt_ops || !tgt || 1889 qla_ini_mode_enabled(vha)) { 1890 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1891 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1892 vha->dpc_flags); 1893 continue; 1894 } 1895 cmd = (struct qla_tgt_cmd *)sp; 1896 cmd->aborted = 1; 1897 break; 1898 case TYPE_TGT_TMCMD: 1899 /* Skip task management functions. */ 1900 break; 1901 default: 1902 break; 1903 } 1904 req->outstanding_cmds[cnt] = NULL; 1905 } 1906 } 1907 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1908 } 1909 1910 /* 1911 * The caller must ensure that no completion interrupts will happen 1912 * while this function is in progress. 1913 */ 1914 void 1915 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1916 { 1917 int que; 1918 struct qla_hw_data *ha = vha->hw; 1919 1920 /* Continue only if initialization complete. */ 1921 if (!ha->base_qpair) 1922 return; 1923 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1924 1925 if (!ha->queue_pair_map) 1926 return; 1927 for (que = 0; que < ha->max_qpairs; que++) { 1928 if (!ha->queue_pair_map[que]) 1929 continue; 1930 1931 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1932 } 1933 } 1934 1935 static int 1936 qla2xxx_slave_alloc(struct scsi_device *sdev) 1937 { 1938 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1939 1940 if (!rport || fc_remote_port_chkready(rport)) 1941 return -ENXIO; 1942 1943 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1944 1945 return 0; 1946 } 1947 1948 static int 1949 qla2xxx_slave_configure(struct scsi_device *sdev) 1950 { 1951 scsi_qla_host_t *vha = shost_priv(sdev->host); 1952 struct req_que *req = vha->req; 1953 1954 scsi_change_queue_depth(sdev, req->max_q_depth); 1955 return 0; 1956 } 1957 1958 static void 1959 qla2xxx_slave_destroy(struct scsi_device *sdev) 1960 { 1961 sdev->hostdata = NULL; 1962 } 1963 1964 /** 1965 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1966 * @ha: HA context 1967 * 1968 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1969 * supported addressing method. 1970 */ 1971 static void 1972 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1973 { 1974 /* Assume a 32bit DMA mask. */ 1975 ha->flags.enable_64bit_addressing = 0; 1976 1977 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1978 /* Any upper-dword bits set? */ 1979 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1980 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1981 /* Ok, a 64bit DMA mask is applicable. */ 1982 ha->flags.enable_64bit_addressing = 1; 1983 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1984 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1985 return; 1986 } 1987 } 1988 1989 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1990 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1991 } 1992 1993 static void 1994 qla2x00_enable_intrs(struct qla_hw_data *ha) 1995 { 1996 unsigned long flags = 0; 1997 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1998 1999 spin_lock_irqsave(&ha->hardware_lock, flags); 2000 ha->interrupts_on = 1; 2001 /* enable risc and host interrupts */ 2002 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2003 rd_reg_word(®->ictrl); 2004 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2005 2006 } 2007 2008 static void 2009 qla2x00_disable_intrs(struct qla_hw_data *ha) 2010 { 2011 unsigned long flags = 0; 2012 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2013 2014 spin_lock_irqsave(&ha->hardware_lock, flags); 2015 ha->interrupts_on = 0; 2016 /* disable risc and host interrupts */ 2017 wrt_reg_word(®->ictrl, 0); 2018 rd_reg_word(®->ictrl); 2019 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2020 } 2021 2022 static void 2023 qla24xx_enable_intrs(struct qla_hw_data *ha) 2024 { 2025 unsigned long flags = 0; 2026 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2027 2028 spin_lock_irqsave(&ha->hardware_lock, flags); 2029 ha->interrupts_on = 1; 2030 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2031 rd_reg_dword(®->ictrl); 2032 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2033 } 2034 2035 static void 2036 qla24xx_disable_intrs(struct qla_hw_data *ha) 2037 { 2038 unsigned long flags = 0; 2039 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2040 2041 if (IS_NOPOLLING_TYPE(ha)) 2042 return; 2043 spin_lock_irqsave(&ha->hardware_lock, flags); 2044 ha->interrupts_on = 0; 2045 wrt_reg_dword(®->ictrl, 0); 2046 rd_reg_dword(®->ictrl); 2047 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2048 } 2049 2050 static int 2051 qla2x00_iospace_config(struct qla_hw_data *ha) 2052 { 2053 resource_size_t pio; 2054 uint16_t msix; 2055 2056 if (pci_request_selected_regions(ha->pdev, ha->bars, 2057 QLA2XXX_DRIVER_NAME)) { 2058 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2059 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2060 pci_name(ha->pdev)); 2061 goto iospace_error_exit; 2062 } 2063 if (!(ha->bars & 1)) 2064 goto skip_pio; 2065 2066 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2067 pio = pci_resource_start(ha->pdev, 0); 2068 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2069 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2070 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2071 "Invalid pci I/O region size (%s).\n", 2072 pci_name(ha->pdev)); 2073 pio = 0; 2074 } 2075 } else { 2076 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2077 "Region #0 no a PIO resource (%s).\n", 2078 pci_name(ha->pdev)); 2079 pio = 0; 2080 } 2081 ha->pio_address = pio; 2082 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2083 "PIO address=%llu.\n", 2084 (unsigned long long)ha->pio_address); 2085 2086 skip_pio: 2087 /* Use MMIO operations for all accesses. */ 2088 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2089 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2090 "Region #1 not an MMIO resource (%s), aborting.\n", 2091 pci_name(ha->pdev)); 2092 goto iospace_error_exit; 2093 } 2094 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2095 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2096 "Invalid PCI mem region size (%s), aborting.\n", 2097 pci_name(ha->pdev)); 2098 goto iospace_error_exit; 2099 } 2100 2101 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2102 if (!ha->iobase) { 2103 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2104 "Cannot remap MMIO (%s), aborting.\n", 2105 pci_name(ha->pdev)); 2106 goto iospace_error_exit; 2107 } 2108 2109 /* Determine queue resources */ 2110 ha->max_req_queues = ha->max_rsp_queues = 1; 2111 ha->msix_count = QLA_BASE_VECTORS; 2112 2113 /* Check if FW supports MQ or not */ 2114 if (!(ha->fw_attributes & BIT_6)) 2115 goto mqiobase_exit; 2116 2117 if (!ql2xmqsupport || !ql2xnvmeenable || 2118 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2119 goto mqiobase_exit; 2120 2121 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2122 pci_resource_len(ha->pdev, 3)); 2123 if (ha->mqiobase) { 2124 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2125 "MQIO Base=%p.\n", ha->mqiobase); 2126 /* Read MSIX vector size of the board */ 2127 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2128 ha->msix_count = msix + 1; 2129 /* Max queues are bounded by available msix vectors */ 2130 /* MB interrupt uses 1 vector */ 2131 ha->max_req_queues = ha->msix_count - 1; 2132 ha->max_rsp_queues = ha->max_req_queues; 2133 /* Queue pairs is the max value minus the base queue pair */ 2134 ha->max_qpairs = ha->max_rsp_queues - 1; 2135 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2136 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2137 2138 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2139 "MSI-X vector count: %d.\n", ha->msix_count); 2140 } else 2141 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2142 "BAR 3 not enabled.\n"); 2143 2144 mqiobase_exit: 2145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2146 "MSIX Count: %d.\n", ha->msix_count); 2147 return (0); 2148 2149 iospace_error_exit: 2150 return (-ENOMEM); 2151 } 2152 2153 2154 static int 2155 qla83xx_iospace_config(struct qla_hw_data *ha) 2156 { 2157 uint16_t msix; 2158 2159 if (pci_request_selected_regions(ha->pdev, ha->bars, 2160 QLA2XXX_DRIVER_NAME)) { 2161 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2162 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2163 pci_name(ha->pdev)); 2164 2165 goto iospace_error_exit; 2166 } 2167 2168 /* Use MMIO operations for all accesses. */ 2169 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2170 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2171 "Invalid pci I/O region size (%s).\n", 2172 pci_name(ha->pdev)); 2173 goto iospace_error_exit; 2174 } 2175 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2176 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2177 "Invalid PCI mem region size (%s), aborting\n", 2178 pci_name(ha->pdev)); 2179 goto iospace_error_exit; 2180 } 2181 2182 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2183 if (!ha->iobase) { 2184 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2185 "Cannot remap MMIO (%s), aborting.\n", 2186 pci_name(ha->pdev)); 2187 goto iospace_error_exit; 2188 } 2189 2190 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2191 /* 83XX 26XX always use MQ type access for queues 2192 * - mbar 2, a.k.a region 4 */ 2193 ha->max_req_queues = ha->max_rsp_queues = 1; 2194 ha->msix_count = QLA_BASE_VECTORS; 2195 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2196 pci_resource_len(ha->pdev, 4)); 2197 2198 if (!ha->mqiobase) { 2199 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2200 "BAR2/region4 not enabled\n"); 2201 goto mqiobase_exit; 2202 } 2203 2204 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2205 pci_resource_len(ha->pdev, 2)); 2206 if (ha->msixbase) { 2207 /* Read MSIX vector size of the board */ 2208 pci_read_config_word(ha->pdev, 2209 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2210 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2211 /* 2212 * By default, driver uses at least two msix vectors 2213 * (default & rspq) 2214 */ 2215 if (ql2xmqsupport || ql2xnvmeenable) { 2216 /* MB interrupt uses 1 vector */ 2217 ha->max_req_queues = ha->msix_count - 1; 2218 2219 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2220 if (QLA_TGT_MODE_ENABLED()) 2221 ha->max_req_queues--; 2222 2223 ha->max_rsp_queues = ha->max_req_queues; 2224 2225 /* Queue pairs is the max value minus 2226 * the base queue pair */ 2227 ha->max_qpairs = ha->max_req_queues - 1; 2228 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2229 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2230 } 2231 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2232 "MSI-X vector count: %d.\n", ha->msix_count); 2233 } else 2234 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2235 "BAR 1 not enabled.\n"); 2236 2237 mqiobase_exit: 2238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2239 "MSIX Count: %d.\n", ha->msix_count); 2240 return 0; 2241 2242 iospace_error_exit: 2243 return -ENOMEM; 2244 } 2245 2246 static struct isp_operations qla2100_isp_ops = { 2247 .pci_config = qla2100_pci_config, 2248 .reset_chip = qla2x00_reset_chip, 2249 .chip_diag = qla2x00_chip_diag, 2250 .config_rings = qla2x00_config_rings, 2251 .reset_adapter = qla2x00_reset_adapter, 2252 .nvram_config = qla2x00_nvram_config, 2253 .update_fw_options = qla2x00_update_fw_options, 2254 .load_risc = qla2x00_load_risc, 2255 .pci_info_str = qla2x00_pci_info_str, 2256 .fw_version_str = qla2x00_fw_version_str, 2257 .intr_handler = qla2100_intr_handler, 2258 .enable_intrs = qla2x00_enable_intrs, 2259 .disable_intrs = qla2x00_disable_intrs, 2260 .abort_command = qla2x00_abort_command, 2261 .target_reset = qla2x00_abort_target, 2262 .lun_reset = qla2x00_lun_reset, 2263 .fabric_login = qla2x00_login_fabric, 2264 .fabric_logout = qla2x00_fabric_logout, 2265 .calc_req_entries = qla2x00_calc_iocbs_32, 2266 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2267 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2268 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2269 .read_nvram = qla2x00_read_nvram_data, 2270 .write_nvram = qla2x00_write_nvram_data, 2271 .fw_dump = qla2100_fw_dump, 2272 .beacon_on = NULL, 2273 .beacon_off = NULL, 2274 .beacon_blink = NULL, 2275 .read_optrom = qla2x00_read_optrom_data, 2276 .write_optrom = qla2x00_write_optrom_data, 2277 .get_flash_version = qla2x00_get_flash_version, 2278 .start_scsi = qla2x00_start_scsi, 2279 .start_scsi_mq = NULL, 2280 .abort_isp = qla2x00_abort_isp, 2281 .iospace_config = qla2x00_iospace_config, 2282 .initialize_adapter = qla2x00_initialize_adapter, 2283 }; 2284 2285 static struct isp_operations qla2300_isp_ops = { 2286 .pci_config = qla2300_pci_config, 2287 .reset_chip = qla2x00_reset_chip, 2288 .chip_diag = qla2x00_chip_diag, 2289 .config_rings = qla2x00_config_rings, 2290 .reset_adapter = qla2x00_reset_adapter, 2291 .nvram_config = qla2x00_nvram_config, 2292 .update_fw_options = qla2x00_update_fw_options, 2293 .load_risc = qla2x00_load_risc, 2294 .pci_info_str = qla2x00_pci_info_str, 2295 .fw_version_str = qla2x00_fw_version_str, 2296 .intr_handler = qla2300_intr_handler, 2297 .enable_intrs = qla2x00_enable_intrs, 2298 .disable_intrs = qla2x00_disable_intrs, 2299 .abort_command = qla2x00_abort_command, 2300 .target_reset = qla2x00_abort_target, 2301 .lun_reset = qla2x00_lun_reset, 2302 .fabric_login = qla2x00_login_fabric, 2303 .fabric_logout = qla2x00_fabric_logout, 2304 .calc_req_entries = qla2x00_calc_iocbs_32, 2305 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2306 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2307 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2308 .read_nvram = qla2x00_read_nvram_data, 2309 .write_nvram = qla2x00_write_nvram_data, 2310 .fw_dump = qla2300_fw_dump, 2311 .beacon_on = qla2x00_beacon_on, 2312 .beacon_off = qla2x00_beacon_off, 2313 .beacon_blink = qla2x00_beacon_blink, 2314 .read_optrom = qla2x00_read_optrom_data, 2315 .write_optrom = qla2x00_write_optrom_data, 2316 .get_flash_version = qla2x00_get_flash_version, 2317 .start_scsi = qla2x00_start_scsi, 2318 .start_scsi_mq = NULL, 2319 .abort_isp = qla2x00_abort_isp, 2320 .iospace_config = qla2x00_iospace_config, 2321 .initialize_adapter = qla2x00_initialize_adapter, 2322 }; 2323 2324 static struct isp_operations qla24xx_isp_ops = { 2325 .pci_config = qla24xx_pci_config, 2326 .reset_chip = qla24xx_reset_chip, 2327 .chip_diag = qla24xx_chip_diag, 2328 .config_rings = qla24xx_config_rings, 2329 .reset_adapter = qla24xx_reset_adapter, 2330 .nvram_config = qla24xx_nvram_config, 2331 .update_fw_options = qla24xx_update_fw_options, 2332 .load_risc = qla24xx_load_risc, 2333 .pci_info_str = qla24xx_pci_info_str, 2334 .fw_version_str = qla24xx_fw_version_str, 2335 .intr_handler = qla24xx_intr_handler, 2336 .enable_intrs = qla24xx_enable_intrs, 2337 .disable_intrs = qla24xx_disable_intrs, 2338 .abort_command = qla24xx_abort_command, 2339 .target_reset = qla24xx_abort_target, 2340 .lun_reset = qla24xx_lun_reset, 2341 .fabric_login = qla24xx_login_fabric, 2342 .fabric_logout = qla24xx_fabric_logout, 2343 .calc_req_entries = NULL, 2344 .build_iocbs = NULL, 2345 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2346 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2347 .read_nvram = qla24xx_read_nvram_data, 2348 .write_nvram = qla24xx_write_nvram_data, 2349 .fw_dump = qla24xx_fw_dump, 2350 .beacon_on = qla24xx_beacon_on, 2351 .beacon_off = qla24xx_beacon_off, 2352 .beacon_blink = qla24xx_beacon_blink, 2353 .read_optrom = qla24xx_read_optrom_data, 2354 .write_optrom = qla24xx_write_optrom_data, 2355 .get_flash_version = qla24xx_get_flash_version, 2356 .start_scsi = qla24xx_start_scsi, 2357 .start_scsi_mq = NULL, 2358 .abort_isp = qla2x00_abort_isp, 2359 .iospace_config = qla2x00_iospace_config, 2360 .initialize_adapter = qla2x00_initialize_adapter, 2361 }; 2362 2363 static struct isp_operations qla25xx_isp_ops = { 2364 .pci_config = qla25xx_pci_config, 2365 .reset_chip = qla24xx_reset_chip, 2366 .chip_diag = qla24xx_chip_diag, 2367 .config_rings = qla24xx_config_rings, 2368 .reset_adapter = qla24xx_reset_adapter, 2369 .nvram_config = qla24xx_nvram_config, 2370 .update_fw_options = qla24xx_update_fw_options, 2371 .load_risc = qla24xx_load_risc, 2372 .pci_info_str = qla24xx_pci_info_str, 2373 .fw_version_str = qla24xx_fw_version_str, 2374 .intr_handler = qla24xx_intr_handler, 2375 .enable_intrs = qla24xx_enable_intrs, 2376 .disable_intrs = qla24xx_disable_intrs, 2377 .abort_command = qla24xx_abort_command, 2378 .target_reset = qla24xx_abort_target, 2379 .lun_reset = qla24xx_lun_reset, 2380 .fabric_login = qla24xx_login_fabric, 2381 .fabric_logout = qla24xx_fabric_logout, 2382 .calc_req_entries = NULL, 2383 .build_iocbs = NULL, 2384 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2385 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2386 .read_nvram = qla25xx_read_nvram_data, 2387 .write_nvram = qla25xx_write_nvram_data, 2388 .fw_dump = qla25xx_fw_dump, 2389 .beacon_on = qla24xx_beacon_on, 2390 .beacon_off = qla24xx_beacon_off, 2391 .beacon_blink = qla24xx_beacon_blink, 2392 .read_optrom = qla25xx_read_optrom_data, 2393 .write_optrom = qla24xx_write_optrom_data, 2394 .get_flash_version = qla24xx_get_flash_version, 2395 .start_scsi = qla24xx_dif_start_scsi, 2396 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2397 .abort_isp = qla2x00_abort_isp, 2398 .iospace_config = qla2x00_iospace_config, 2399 .initialize_adapter = qla2x00_initialize_adapter, 2400 }; 2401 2402 static struct isp_operations qla81xx_isp_ops = { 2403 .pci_config = qla25xx_pci_config, 2404 .reset_chip = qla24xx_reset_chip, 2405 .chip_diag = qla24xx_chip_diag, 2406 .config_rings = qla24xx_config_rings, 2407 .reset_adapter = qla24xx_reset_adapter, 2408 .nvram_config = qla81xx_nvram_config, 2409 .update_fw_options = qla24xx_update_fw_options, 2410 .load_risc = qla81xx_load_risc, 2411 .pci_info_str = qla24xx_pci_info_str, 2412 .fw_version_str = qla24xx_fw_version_str, 2413 .intr_handler = qla24xx_intr_handler, 2414 .enable_intrs = qla24xx_enable_intrs, 2415 .disable_intrs = qla24xx_disable_intrs, 2416 .abort_command = qla24xx_abort_command, 2417 .target_reset = qla24xx_abort_target, 2418 .lun_reset = qla24xx_lun_reset, 2419 .fabric_login = qla24xx_login_fabric, 2420 .fabric_logout = qla24xx_fabric_logout, 2421 .calc_req_entries = NULL, 2422 .build_iocbs = NULL, 2423 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2424 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2425 .read_nvram = NULL, 2426 .write_nvram = NULL, 2427 .fw_dump = qla81xx_fw_dump, 2428 .beacon_on = qla24xx_beacon_on, 2429 .beacon_off = qla24xx_beacon_off, 2430 .beacon_blink = qla83xx_beacon_blink, 2431 .read_optrom = qla25xx_read_optrom_data, 2432 .write_optrom = qla24xx_write_optrom_data, 2433 .get_flash_version = qla24xx_get_flash_version, 2434 .start_scsi = qla24xx_dif_start_scsi, 2435 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2436 .abort_isp = qla2x00_abort_isp, 2437 .iospace_config = qla2x00_iospace_config, 2438 .initialize_adapter = qla2x00_initialize_adapter, 2439 }; 2440 2441 static struct isp_operations qla82xx_isp_ops = { 2442 .pci_config = qla82xx_pci_config, 2443 .reset_chip = qla82xx_reset_chip, 2444 .chip_diag = qla24xx_chip_diag, 2445 .config_rings = qla82xx_config_rings, 2446 .reset_adapter = qla24xx_reset_adapter, 2447 .nvram_config = qla81xx_nvram_config, 2448 .update_fw_options = qla24xx_update_fw_options, 2449 .load_risc = qla82xx_load_risc, 2450 .pci_info_str = qla24xx_pci_info_str, 2451 .fw_version_str = qla24xx_fw_version_str, 2452 .intr_handler = qla82xx_intr_handler, 2453 .enable_intrs = qla82xx_enable_intrs, 2454 .disable_intrs = qla82xx_disable_intrs, 2455 .abort_command = qla24xx_abort_command, 2456 .target_reset = qla24xx_abort_target, 2457 .lun_reset = qla24xx_lun_reset, 2458 .fabric_login = qla24xx_login_fabric, 2459 .fabric_logout = qla24xx_fabric_logout, 2460 .calc_req_entries = NULL, 2461 .build_iocbs = NULL, 2462 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2463 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2464 .read_nvram = qla24xx_read_nvram_data, 2465 .write_nvram = qla24xx_write_nvram_data, 2466 .fw_dump = qla82xx_fw_dump, 2467 .beacon_on = qla82xx_beacon_on, 2468 .beacon_off = qla82xx_beacon_off, 2469 .beacon_blink = NULL, 2470 .read_optrom = qla82xx_read_optrom_data, 2471 .write_optrom = qla82xx_write_optrom_data, 2472 .get_flash_version = qla82xx_get_flash_version, 2473 .start_scsi = qla82xx_start_scsi, 2474 .start_scsi_mq = NULL, 2475 .abort_isp = qla82xx_abort_isp, 2476 .iospace_config = qla82xx_iospace_config, 2477 .initialize_adapter = qla2x00_initialize_adapter, 2478 }; 2479 2480 static struct isp_operations qla8044_isp_ops = { 2481 .pci_config = qla82xx_pci_config, 2482 .reset_chip = qla82xx_reset_chip, 2483 .chip_diag = qla24xx_chip_diag, 2484 .config_rings = qla82xx_config_rings, 2485 .reset_adapter = qla24xx_reset_adapter, 2486 .nvram_config = qla81xx_nvram_config, 2487 .update_fw_options = qla24xx_update_fw_options, 2488 .load_risc = qla82xx_load_risc, 2489 .pci_info_str = qla24xx_pci_info_str, 2490 .fw_version_str = qla24xx_fw_version_str, 2491 .intr_handler = qla8044_intr_handler, 2492 .enable_intrs = qla82xx_enable_intrs, 2493 .disable_intrs = qla82xx_disable_intrs, 2494 .abort_command = qla24xx_abort_command, 2495 .target_reset = qla24xx_abort_target, 2496 .lun_reset = qla24xx_lun_reset, 2497 .fabric_login = qla24xx_login_fabric, 2498 .fabric_logout = qla24xx_fabric_logout, 2499 .calc_req_entries = NULL, 2500 .build_iocbs = NULL, 2501 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2502 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2503 .read_nvram = NULL, 2504 .write_nvram = NULL, 2505 .fw_dump = qla8044_fw_dump, 2506 .beacon_on = qla82xx_beacon_on, 2507 .beacon_off = qla82xx_beacon_off, 2508 .beacon_blink = NULL, 2509 .read_optrom = qla8044_read_optrom_data, 2510 .write_optrom = qla8044_write_optrom_data, 2511 .get_flash_version = qla82xx_get_flash_version, 2512 .start_scsi = qla82xx_start_scsi, 2513 .start_scsi_mq = NULL, 2514 .abort_isp = qla8044_abort_isp, 2515 .iospace_config = qla82xx_iospace_config, 2516 .initialize_adapter = qla2x00_initialize_adapter, 2517 }; 2518 2519 static struct isp_operations qla83xx_isp_ops = { 2520 .pci_config = qla25xx_pci_config, 2521 .reset_chip = qla24xx_reset_chip, 2522 .chip_diag = qla24xx_chip_diag, 2523 .config_rings = qla24xx_config_rings, 2524 .reset_adapter = qla24xx_reset_adapter, 2525 .nvram_config = qla81xx_nvram_config, 2526 .update_fw_options = qla24xx_update_fw_options, 2527 .load_risc = qla81xx_load_risc, 2528 .pci_info_str = qla24xx_pci_info_str, 2529 .fw_version_str = qla24xx_fw_version_str, 2530 .intr_handler = qla24xx_intr_handler, 2531 .enable_intrs = qla24xx_enable_intrs, 2532 .disable_intrs = qla24xx_disable_intrs, 2533 .abort_command = qla24xx_abort_command, 2534 .target_reset = qla24xx_abort_target, 2535 .lun_reset = qla24xx_lun_reset, 2536 .fabric_login = qla24xx_login_fabric, 2537 .fabric_logout = qla24xx_fabric_logout, 2538 .calc_req_entries = NULL, 2539 .build_iocbs = NULL, 2540 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2541 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2542 .read_nvram = NULL, 2543 .write_nvram = NULL, 2544 .fw_dump = qla83xx_fw_dump, 2545 .beacon_on = qla24xx_beacon_on, 2546 .beacon_off = qla24xx_beacon_off, 2547 .beacon_blink = qla83xx_beacon_blink, 2548 .read_optrom = qla25xx_read_optrom_data, 2549 .write_optrom = qla24xx_write_optrom_data, 2550 .get_flash_version = qla24xx_get_flash_version, 2551 .start_scsi = qla24xx_dif_start_scsi, 2552 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2553 .abort_isp = qla2x00_abort_isp, 2554 .iospace_config = qla83xx_iospace_config, 2555 .initialize_adapter = qla2x00_initialize_adapter, 2556 }; 2557 2558 static struct isp_operations qlafx00_isp_ops = { 2559 .pci_config = qlafx00_pci_config, 2560 .reset_chip = qlafx00_soft_reset, 2561 .chip_diag = qlafx00_chip_diag, 2562 .config_rings = qlafx00_config_rings, 2563 .reset_adapter = qlafx00_soft_reset, 2564 .nvram_config = NULL, 2565 .update_fw_options = NULL, 2566 .load_risc = NULL, 2567 .pci_info_str = qlafx00_pci_info_str, 2568 .fw_version_str = qlafx00_fw_version_str, 2569 .intr_handler = qlafx00_intr_handler, 2570 .enable_intrs = qlafx00_enable_intrs, 2571 .disable_intrs = qlafx00_disable_intrs, 2572 .abort_command = qla24xx_async_abort_command, 2573 .target_reset = qlafx00_abort_target, 2574 .lun_reset = qlafx00_lun_reset, 2575 .fabric_login = NULL, 2576 .fabric_logout = NULL, 2577 .calc_req_entries = NULL, 2578 .build_iocbs = NULL, 2579 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2580 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2581 .read_nvram = qla24xx_read_nvram_data, 2582 .write_nvram = qla24xx_write_nvram_data, 2583 .fw_dump = NULL, 2584 .beacon_on = qla24xx_beacon_on, 2585 .beacon_off = qla24xx_beacon_off, 2586 .beacon_blink = NULL, 2587 .read_optrom = qla24xx_read_optrom_data, 2588 .write_optrom = qla24xx_write_optrom_data, 2589 .get_flash_version = qla24xx_get_flash_version, 2590 .start_scsi = qlafx00_start_scsi, 2591 .start_scsi_mq = NULL, 2592 .abort_isp = qlafx00_abort_isp, 2593 .iospace_config = qlafx00_iospace_config, 2594 .initialize_adapter = qlafx00_initialize_adapter, 2595 }; 2596 2597 static struct isp_operations qla27xx_isp_ops = { 2598 .pci_config = qla25xx_pci_config, 2599 .reset_chip = qla24xx_reset_chip, 2600 .chip_diag = qla24xx_chip_diag, 2601 .config_rings = qla24xx_config_rings, 2602 .reset_adapter = qla24xx_reset_adapter, 2603 .nvram_config = qla81xx_nvram_config, 2604 .update_fw_options = qla24xx_update_fw_options, 2605 .load_risc = qla81xx_load_risc, 2606 .pci_info_str = qla24xx_pci_info_str, 2607 .fw_version_str = qla24xx_fw_version_str, 2608 .intr_handler = qla24xx_intr_handler, 2609 .enable_intrs = qla24xx_enable_intrs, 2610 .disable_intrs = qla24xx_disable_intrs, 2611 .abort_command = qla24xx_abort_command, 2612 .target_reset = qla24xx_abort_target, 2613 .lun_reset = qla24xx_lun_reset, 2614 .fabric_login = qla24xx_login_fabric, 2615 .fabric_logout = qla24xx_fabric_logout, 2616 .calc_req_entries = NULL, 2617 .build_iocbs = NULL, 2618 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2619 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2620 .read_nvram = NULL, 2621 .write_nvram = NULL, 2622 .fw_dump = qla27xx_fwdump, 2623 .mpi_fw_dump = qla27xx_mpi_fwdump, 2624 .beacon_on = qla24xx_beacon_on, 2625 .beacon_off = qla24xx_beacon_off, 2626 .beacon_blink = qla83xx_beacon_blink, 2627 .read_optrom = qla25xx_read_optrom_data, 2628 .write_optrom = qla24xx_write_optrom_data, 2629 .get_flash_version = qla24xx_get_flash_version, 2630 .start_scsi = qla24xx_dif_start_scsi, 2631 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2632 .abort_isp = qla2x00_abort_isp, 2633 .iospace_config = qla83xx_iospace_config, 2634 .initialize_adapter = qla2x00_initialize_adapter, 2635 }; 2636 2637 static inline void 2638 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2639 { 2640 ha->device_type = DT_EXTENDED_IDS; 2641 switch (ha->pdev->device) { 2642 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2643 ha->isp_type |= DT_ISP2100; 2644 ha->device_type &= ~DT_EXTENDED_IDS; 2645 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2646 break; 2647 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2648 ha->isp_type |= DT_ISP2200; 2649 ha->device_type &= ~DT_EXTENDED_IDS; 2650 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2651 break; 2652 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2653 ha->isp_type |= DT_ISP2300; 2654 ha->device_type |= DT_ZIO_SUPPORTED; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2656 break; 2657 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2658 ha->isp_type |= DT_ISP2312; 2659 ha->device_type |= DT_ZIO_SUPPORTED; 2660 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2661 break; 2662 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2663 ha->isp_type |= DT_ISP2322; 2664 ha->device_type |= DT_ZIO_SUPPORTED; 2665 if (ha->pdev->subsystem_vendor == 0x1028 && 2666 ha->pdev->subsystem_device == 0x0170) 2667 ha->device_type |= DT_OEM_001; 2668 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2669 break; 2670 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2671 ha->isp_type |= DT_ISP6312; 2672 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2673 break; 2674 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2675 ha->isp_type |= DT_ISP6322; 2676 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2677 break; 2678 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2679 ha->isp_type |= DT_ISP2422; 2680 ha->device_type |= DT_ZIO_SUPPORTED; 2681 ha->device_type |= DT_FWI2; 2682 ha->device_type |= DT_IIDMA; 2683 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2684 break; 2685 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2686 ha->isp_type |= DT_ISP2432; 2687 ha->device_type |= DT_ZIO_SUPPORTED; 2688 ha->device_type |= DT_FWI2; 2689 ha->device_type |= DT_IIDMA; 2690 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2691 break; 2692 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2693 ha->isp_type |= DT_ISP8432; 2694 ha->device_type |= DT_ZIO_SUPPORTED; 2695 ha->device_type |= DT_FWI2; 2696 ha->device_type |= DT_IIDMA; 2697 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2698 break; 2699 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2700 ha->isp_type |= DT_ISP5422; 2701 ha->device_type |= DT_FWI2; 2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2703 break; 2704 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2705 ha->isp_type |= DT_ISP5432; 2706 ha->device_type |= DT_FWI2; 2707 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2708 break; 2709 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2710 ha->isp_type |= DT_ISP2532; 2711 ha->device_type |= DT_ZIO_SUPPORTED; 2712 ha->device_type |= DT_FWI2; 2713 ha->device_type |= DT_IIDMA; 2714 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2715 break; 2716 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2717 ha->isp_type |= DT_ISP8001; 2718 ha->device_type |= DT_ZIO_SUPPORTED; 2719 ha->device_type |= DT_FWI2; 2720 ha->device_type |= DT_IIDMA; 2721 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2722 break; 2723 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2724 ha->isp_type |= DT_ISP8021; 2725 ha->device_type |= DT_ZIO_SUPPORTED; 2726 ha->device_type |= DT_FWI2; 2727 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2728 /* Initialize 82XX ISP flags */ 2729 qla82xx_init_flags(ha); 2730 break; 2731 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2732 ha->isp_type |= DT_ISP8044; 2733 ha->device_type |= DT_ZIO_SUPPORTED; 2734 ha->device_type |= DT_FWI2; 2735 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2736 /* Initialize 82XX ISP flags */ 2737 qla82xx_init_flags(ha); 2738 break; 2739 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2740 ha->isp_type |= DT_ISP2031; 2741 ha->device_type |= DT_ZIO_SUPPORTED; 2742 ha->device_type |= DT_FWI2; 2743 ha->device_type |= DT_IIDMA; 2744 ha->device_type |= DT_T10_PI; 2745 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2746 break; 2747 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2748 ha->isp_type |= DT_ISP8031; 2749 ha->device_type |= DT_ZIO_SUPPORTED; 2750 ha->device_type |= DT_FWI2; 2751 ha->device_type |= DT_IIDMA; 2752 ha->device_type |= DT_T10_PI; 2753 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2754 break; 2755 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2756 ha->isp_type |= DT_ISPFX00; 2757 break; 2758 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2759 ha->isp_type |= DT_ISP2071; 2760 ha->device_type |= DT_ZIO_SUPPORTED; 2761 ha->device_type |= DT_FWI2; 2762 ha->device_type |= DT_IIDMA; 2763 ha->device_type |= DT_T10_PI; 2764 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2765 break; 2766 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2767 ha->isp_type |= DT_ISP2271; 2768 ha->device_type |= DT_ZIO_SUPPORTED; 2769 ha->device_type |= DT_FWI2; 2770 ha->device_type |= DT_IIDMA; 2771 ha->device_type |= DT_T10_PI; 2772 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2773 break; 2774 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2775 ha->isp_type |= DT_ISP2261; 2776 ha->device_type |= DT_ZIO_SUPPORTED; 2777 ha->device_type |= DT_FWI2; 2778 ha->device_type |= DT_IIDMA; 2779 ha->device_type |= DT_T10_PI; 2780 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2781 break; 2782 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2783 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2784 ha->isp_type |= DT_ISP2081; 2785 ha->device_type |= DT_ZIO_SUPPORTED; 2786 ha->device_type |= DT_FWI2; 2787 ha->device_type |= DT_IIDMA; 2788 ha->device_type |= DT_T10_PI; 2789 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2790 break; 2791 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2792 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2793 ha->isp_type |= DT_ISP2281; 2794 ha->device_type |= DT_ZIO_SUPPORTED; 2795 ha->device_type |= DT_FWI2; 2796 ha->device_type |= DT_IIDMA; 2797 ha->device_type |= DT_T10_PI; 2798 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2799 break; 2800 } 2801 2802 if (IS_QLA82XX(ha)) 2803 ha->port_no = ha->portnum & 1; 2804 else { 2805 /* Get adapter physical port no from interrupt pin register. */ 2806 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2807 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2808 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2809 ha->port_no--; 2810 else 2811 ha->port_no = !(ha->port_no & 1); 2812 } 2813 2814 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2815 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2816 ha->device_type, ha->port_no, ha->fw_srisc_address); 2817 } 2818 2819 static void 2820 qla2xxx_scan_start(struct Scsi_Host *shost) 2821 { 2822 scsi_qla_host_t *vha = shost_priv(shost); 2823 2824 if (vha->hw->flags.running_gold_fw) 2825 return; 2826 2827 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2828 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2829 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2830 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2831 } 2832 2833 static int 2834 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2835 { 2836 scsi_qla_host_t *vha = shost_priv(shost); 2837 2838 if (test_bit(UNLOADING, &vha->dpc_flags)) 2839 return 1; 2840 if (!vha->host) 2841 return 1; 2842 if (time > vha->hw->loop_reset_delay * HZ) 2843 return 1; 2844 2845 return atomic_read(&vha->loop_state) == LOOP_READY; 2846 } 2847 2848 static void qla_heartbeat_work_fn(struct work_struct *work) 2849 { 2850 struct qla_hw_data *ha = container_of(work, 2851 struct qla_hw_data, heartbeat_work); 2852 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2853 2854 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2855 qla_no_op_mb(base_vha); 2856 } 2857 2858 static void qla2x00_iocb_work_fn(struct work_struct *work) 2859 { 2860 struct scsi_qla_host *vha = container_of(work, 2861 struct scsi_qla_host, iocb_work); 2862 struct qla_hw_data *ha = vha->hw; 2863 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2864 int i = 2; 2865 unsigned long flags; 2866 2867 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2868 return; 2869 2870 while (!list_empty(&vha->work_list) && i > 0) { 2871 qla2x00_do_work(vha); 2872 i--; 2873 } 2874 2875 spin_lock_irqsave(&vha->work_lock, flags); 2876 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2877 spin_unlock_irqrestore(&vha->work_lock, flags); 2878 } 2879 2880 static void 2881 qla_trace_init(void) 2882 { 2883 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL); 2884 if (!qla_trc_array) { 2885 ql_log(ql_log_fatal, NULL, 0x0001, 2886 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2887 return; 2888 } 2889 2890 QLA_TRACE_ENABLE(qla_trc_array); 2891 } 2892 2893 static void 2894 qla_trace_uninit(void) 2895 { 2896 if (!qla_trc_array) 2897 return; 2898 trace_array_put(qla_trc_array); 2899 } 2900 2901 /* 2902 * PCI driver interface 2903 */ 2904 static int 2905 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2906 { 2907 int ret = -ENODEV; 2908 struct Scsi_Host *host; 2909 scsi_qla_host_t *base_vha = NULL; 2910 struct qla_hw_data *ha; 2911 char pci_info[30]; 2912 char fw_str[30], wq_name[30]; 2913 struct scsi_host_template *sht; 2914 int bars, mem_only = 0; 2915 uint16_t req_length = 0, rsp_length = 0; 2916 struct req_que *req = NULL; 2917 struct rsp_que *rsp = NULL; 2918 int i; 2919 2920 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2921 sht = &qla2xxx_driver_template; 2922 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2940 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2941 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2942 mem_only = 1; 2943 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2944 "Mem only adapter.\n"); 2945 } 2946 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2947 "Bars=%d.\n", bars); 2948 2949 if (mem_only) { 2950 if (pci_enable_device_mem(pdev)) 2951 return ret; 2952 } else { 2953 if (pci_enable_device(pdev)) 2954 return ret; 2955 } 2956 2957 if (is_kdump_kernel()) { 2958 ql2xmqsupport = 0; 2959 ql2xallocfwdump = 0; 2960 } 2961 2962 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2963 if (!ha) { 2964 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2965 "Unable to allocate memory for ha.\n"); 2966 goto disable_device; 2967 } 2968 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2969 "Memory allocated for ha=%p.\n", ha); 2970 ha->pdev = pdev; 2971 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2972 spin_lock_init(&ha->tgt.q_full_lock); 2973 spin_lock_init(&ha->tgt.sess_lock); 2974 spin_lock_init(&ha->tgt.atio_lock); 2975 2976 spin_lock_init(&ha->sadb_lock); 2977 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2978 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2979 2980 spin_lock_init(&ha->sadb_fp_lock); 2981 2982 if (qla_edif_sadb_build_free_pool(ha)) { 2983 kfree(ha); 2984 goto disable_device; 2985 } 2986 2987 atomic_set(&ha->nvme_active_aen_cnt, 0); 2988 2989 /* Clear our data area */ 2990 ha->bars = bars; 2991 ha->mem_only = mem_only; 2992 spin_lock_init(&ha->hardware_lock); 2993 spin_lock_init(&ha->vport_slock); 2994 mutex_init(&ha->selflogin_lock); 2995 mutex_init(&ha->optrom_mutex); 2996 2997 /* Set ISP-type information. */ 2998 qla2x00_set_isp_flags(ha); 2999 3000 /* Set EEH reset type to fundamental if required by hba */ 3001 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3002 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3003 pdev->needs_freset = 1; 3004 3005 ha->prev_topology = 0; 3006 ha->init_cb_size = sizeof(init_cb_t); 3007 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3008 ha->optrom_size = OPTROM_SIZE_2300; 3009 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3010 atomic_set(&ha->num_pend_mbx_stage1, 0); 3011 atomic_set(&ha->num_pend_mbx_stage2, 0); 3012 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3013 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3014 INIT_LIST_HEAD(&ha->tmf_pending); 3015 INIT_LIST_HEAD(&ha->tmf_active); 3016 3017 /* Assign ISP specific operations. */ 3018 if (IS_QLA2100(ha)) { 3019 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3020 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3021 req_length = REQUEST_ENTRY_CNT_2100; 3022 rsp_length = RESPONSE_ENTRY_CNT_2100; 3023 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3024 ha->gid_list_info_size = 4; 3025 ha->flash_conf_off = ~0; 3026 ha->flash_data_off = ~0; 3027 ha->nvram_conf_off = ~0; 3028 ha->nvram_data_off = ~0; 3029 ha->isp_ops = &qla2100_isp_ops; 3030 } else if (IS_QLA2200(ha)) { 3031 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3032 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3033 req_length = REQUEST_ENTRY_CNT_2200; 3034 rsp_length = RESPONSE_ENTRY_CNT_2100; 3035 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3036 ha->gid_list_info_size = 4; 3037 ha->flash_conf_off = ~0; 3038 ha->flash_data_off = ~0; 3039 ha->nvram_conf_off = ~0; 3040 ha->nvram_data_off = ~0; 3041 ha->isp_ops = &qla2100_isp_ops; 3042 } else if (IS_QLA23XX(ha)) { 3043 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3044 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3045 req_length = REQUEST_ENTRY_CNT_2200; 3046 rsp_length = RESPONSE_ENTRY_CNT_2300; 3047 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3048 ha->gid_list_info_size = 6; 3049 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3050 ha->optrom_size = OPTROM_SIZE_2322; 3051 ha->flash_conf_off = ~0; 3052 ha->flash_data_off = ~0; 3053 ha->nvram_conf_off = ~0; 3054 ha->nvram_data_off = ~0; 3055 ha->isp_ops = &qla2300_isp_ops; 3056 } else if (IS_QLA24XX_TYPE(ha)) { 3057 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3058 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3059 req_length = REQUEST_ENTRY_CNT_24XX; 3060 rsp_length = RESPONSE_ENTRY_CNT_2300; 3061 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3062 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3063 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3064 ha->gid_list_info_size = 8; 3065 ha->optrom_size = OPTROM_SIZE_24XX; 3066 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3067 ha->isp_ops = &qla24xx_isp_ops; 3068 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3069 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3070 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3071 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3072 } else if (IS_QLA25XX(ha)) { 3073 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3074 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3075 req_length = REQUEST_ENTRY_CNT_24XX; 3076 rsp_length = RESPONSE_ENTRY_CNT_2300; 3077 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3078 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3079 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3080 ha->gid_list_info_size = 8; 3081 ha->optrom_size = OPTROM_SIZE_25XX; 3082 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3083 ha->isp_ops = &qla25xx_isp_ops; 3084 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3085 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3086 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3087 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3088 } else if (IS_QLA81XX(ha)) { 3089 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3090 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3091 req_length = REQUEST_ENTRY_CNT_24XX; 3092 rsp_length = RESPONSE_ENTRY_CNT_2300; 3093 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3094 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3095 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3096 ha->gid_list_info_size = 8; 3097 ha->optrom_size = OPTROM_SIZE_81XX; 3098 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3099 ha->isp_ops = &qla81xx_isp_ops; 3100 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3101 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3102 ha->nvram_conf_off = ~0; 3103 ha->nvram_data_off = ~0; 3104 } else if (IS_QLA82XX(ha)) { 3105 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3106 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3107 req_length = REQUEST_ENTRY_CNT_82XX; 3108 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3109 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3110 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3111 ha->gid_list_info_size = 8; 3112 ha->optrom_size = OPTROM_SIZE_82XX; 3113 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3114 ha->isp_ops = &qla82xx_isp_ops; 3115 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3116 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3117 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3118 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3119 } else if (IS_QLA8044(ha)) { 3120 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3121 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3122 req_length = REQUEST_ENTRY_CNT_82XX; 3123 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3124 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3125 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3126 ha->gid_list_info_size = 8; 3127 ha->optrom_size = OPTROM_SIZE_83XX; 3128 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3129 ha->isp_ops = &qla8044_isp_ops; 3130 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3131 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3132 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3133 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3134 } else if (IS_QLA83XX(ha)) { 3135 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3136 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3137 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3138 req_length = REQUEST_ENTRY_CNT_83XX; 3139 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3140 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3141 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3142 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3143 ha->gid_list_info_size = 8; 3144 ha->optrom_size = OPTROM_SIZE_83XX; 3145 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3146 ha->isp_ops = &qla83xx_isp_ops; 3147 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3148 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3149 ha->nvram_conf_off = ~0; 3150 ha->nvram_data_off = ~0; 3151 } else if (IS_QLAFX00(ha)) { 3152 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3153 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3154 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3155 req_length = REQUEST_ENTRY_CNT_FX00; 3156 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3157 ha->isp_ops = &qlafx00_isp_ops; 3158 ha->port_down_retry_count = 30; /* default value */ 3159 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3160 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3161 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3162 ha->mr.fw_hbt_en = 1; 3163 ha->mr.host_info_resend = false; 3164 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3165 } else if (IS_QLA27XX(ha)) { 3166 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3167 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3168 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3169 req_length = REQUEST_ENTRY_CNT_83XX; 3170 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3171 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3172 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3173 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3174 ha->gid_list_info_size = 8; 3175 ha->optrom_size = OPTROM_SIZE_83XX; 3176 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3177 ha->isp_ops = &qla27xx_isp_ops; 3178 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3179 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3180 ha->nvram_conf_off = ~0; 3181 ha->nvram_data_off = ~0; 3182 } else if (IS_QLA28XX(ha)) { 3183 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3184 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3185 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3186 req_length = REQUEST_ENTRY_CNT_83XX; 3187 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3188 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3189 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3190 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3191 ha->gid_list_info_size = 8; 3192 ha->optrom_size = OPTROM_SIZE_28XX; 3193 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3194 ha->isp_ops = &qla27xx_isp_ops; 3195 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3196 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3197 ha->nvram_conf_off = ~0; 3198 ha->nvram_data_off = ~0; 3199 } 3200 3201 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3202 "mbx_count=%d, req_length=%d, " 3203 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3204 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3205 "max_fibre_devices=%d.\n", 3206 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3207 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3208 ha->nvram_npiv_size, ha->max_fibre_devices); 3209 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3210 "isp_ops=%p, flash_conf_off=%d, " 3211 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3212 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3213 ha->nvram_conf_off, ha->nvram_data_off); 3214 3215 /* Configure PCI I/O space */ 3216 ret = ha->isp_ops->iospace_config(ha); 3217 if (ret) 3218 goto iospace_config_failed; 3219 3220 ql_log_pci(ql_log_info, pdev, 0x001d, 3221 "Found an ISP%04X irq %d iobase 0x%p.\n", 3222 pdev->device, pdev->irq, ha->iobase); 3223 mutex_init(&ha->vport_lock); 3224 mutex_init(&ha->mq_lock); 3225 init_completion(&ha->mbx_cmd_comp); 3226 complete(&ha->mbx_cmd_comp); 3227 init_completion(&ha->mbx_intr_comp); 3228 init_completion(&ha->dcbx_comp); 3229 init_completion(&ha->lb_portup_comp); 3230 3231 set_bit(0, (unsigned long *) ha->vp_idx_map); 3232 3233 qla2x00_config_dma_addressing(ha); 3234 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3235 "64 Bit addressing is %s.\n", 3236 ha->flags.enable_64bit_addressing ? "enable" : 3237 "disable"); 3238 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3239 if (ret) { 3240 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3241 "Failed to allocate memory for adapter, aborting.\n"); 3242 3243 goto probe_hw_failed; 3244 } 3245 3246 req->max_q_depth = MAX_Q_DEPTH; 3247 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3248 req->max_q_depth = ql2xmaxqdepth; 3249 3250 3251 base_vha = qla2x00_create_host(sht, ha); 3252 if (!base_vha) { 3253 ret = -ENOMEM; 3254 goto probe_hw_failed; 3255 } 3256 3257 pci_set_drvdata(pdev, base_vha); 3258 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3259 3260 host = base_vha->host; 3261 base_vha->req = req; 3262 if (IS_QLA2XXX_MIDTYPE(ha)) 3263 base_vha->mgmt_svr_loop_id = 3264 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3265 else 3266 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3267 base_vha->vp_idx; 3268 3269 /* Setup fcport template structure. */ 3270 ha->mr.fcport.vha = base_vha; 3271 ha->mr.fcport.port_type = FCT_UNKNOWN; 3272 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3273 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3274 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3275 ha->mr.fcport.scan_state = 1; 3276 3277 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3278 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3279 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3280 3281 /* Set the SG table size based on ISP type */ 3282 if (!IS_FWI2_CAPABLE(ha)) { 3283 if (IS_QLA2100(ha)) 3284 host->sg_tablesize = 32; 3285 } else { 3286 if (!IS_QLA82XX(ha)) 3287 host->sg_tablesize = QLA_SG_ALL; 3288 } 3289 host->max_id = ha->max_fibre_devices; 3290 host->cmd_per_lun = 3; 3291 host->unique_id = host->host_no; 3292 3293 if (ql2xenabledif && ql2xenabledif != 2) { 3294 ql_log(ql_log_warn, base_vha, 0x302d, 3295 "Invalid value for ql2xenabledif, resetting it to default (2)\n"); 3296 ql2xenabledif = 2; 3297 } 3298 3299 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3300 host->max_cmd_len = 32; 3301 else 3302 host->max_cmd_len = MAX_CMDSZ; 3303 host->max_channel = MAX_BUSES - 1; 3304 /* Older HBAs support only 16-bit LUNs */ 3305 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3306 ql2xmaxlun > 0xffff) 3307 host->max_lun = 0xffff; 3308 else 3309 host->max_lun = ql2xmaxlun; 3310 host->transportt = qla2xxx_transport_template; 3311 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3312 3313 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3314 "max_id=%d this_id=%d " 3315 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3316 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3317 host->this_id, host->cmd_per_lun, host->unique_id, 3318 host->max_cmd_len, host->max_channel, host->max_lun, 3319 host->transportt, sht->vendor_id); 3320 3321 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3322 3323 /* Set up the irqs */ 3324 ret = qla2x00_request_irqs(ha, rsp); 3325 if (ret) 3326 goto probe_failed; 3327 3328 /* Alloc arrays of request and response ring ptrs */ 3329 ret = qla2x00_alloc_queues(ha, req, rsp); 3330 if (ret) { 3331 ql_log(ql_log_fatal, base_vha, 0x003d, 3332 "Failed to allocate memory for queue pointers..." 3333 "aborting.\n"); 3334 ret = -ENODEV; 3335 goto probe_failed; 3336 } 3337 3338 if (ha->mqenable) { 3339 /* number of hardware queues supported by blk/scsi-mq*/ 3340 host->nr_hw_queues = ha->max_qpairs; 3341 3342 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3343 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3344 } else { 3345 if (ql2xnvmeenable) { 3346 host->nr_hw_queues = ha->max_qpairs; 3347 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3348 "FC-NVMe support is enabled, HW queues=%d\n", 3349 host->nr_hw_queues); 3350 } else { 3351 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3352 "blk/scsi-mq disabled.\n"); 3353 } 3354 } 3355 3356 qlt_probe_one_stage1(base_vha, ha); 3357 3358 pci_save_state(pdev); 3359 3360 /* Assign back pointers */ 3361 rsp->req = req; 3362 req->rsp = rsp; 3363 3364 if (IS_QLAFX00(ha)) { 3365 ha->rsp_q_map[0] = rsp; 3366 ha->req_q_map[0] = req; 3367 set_bit(0, ha->req_qid_map); 3368 set_bit(0, ha->rsp_qid_map); 3369 } 3370 3371 /* FWI2-capable only. */ 3372 req->req_q_in = &ha->iobase->isp24.req_q_in; 3373 req->req_q_out = &ha->iobase->isp24.req_q_out; 3374 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3375 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3376 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3377 IS_QLA28XX(ha)) { 3378 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3379 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3380 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3381 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3382 } 3383 3384 if (IS_QLAFX00(ha)) { 3385 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3386 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3387 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3388 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3389 } 3390 3391 if (IS_P3P_TYPE(ha)) { 3392 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3393 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3394 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3395 } 3396 3397 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3398 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3399 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3400 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3401 "req->req_q_in=%p req->req_q_out=%p " 3402 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3403 req->req_q_in, req->req_q_out, 3404 rsp->rsp_q_in, rsp->rsp_q_out); 3405 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3406 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3407 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3408 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3409 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3410 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3411 3412 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3413 if (unlikely(!ha->wq)) { 3414 ret = -ENOMEM; 3415 goto probe_failed; 3416 } 3417 3418 if (ha->isp_ops->initialize_adapter(base_vha)) { 3419 ql_log(ql_log_fatal, base_vha, 0x00d6, 3420 "Failed to initialize adapter - Adapter flags %x.\n", 3421 base_vha->device_flags); 3422 3423 if (IS_QLA82XX(ha)) { 3424 qla82xx_idc_lock(ha); 3425 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3426 QLA8XXX_DEV_FAILED); 3427 qla82xx_idc_unlock(ha); 3428 ql_log(ql_log_fatal, base_vha, 0x00d7, 3429 "HW State: FAILED.\n"); 3430 } else if (IS_QLA8044(ha)) { 3431 qla8044_idc_lock(ha); 3432 qla8044_wr_direct(base_vha, 3433 QLA8044_CRB_DEV_STATE_INDEX, 3434 QLA8XXX_DEV_FAILED); 3435 qla8044_idc_unlock(ha); 3436 ql_log(ql_log_fatal, base_vha, 0x0150, 3437 "HW State: FAILED.\n"); 3438 } 3439 3440 ret = -ENODEV; 3441 goto probe_failed; 3442 } 3443 3444 if (IS_QLAFX00(ha)) 3445 host->can_queue = QLAFX00_MAX_CANQUEUE; 3446 else 3447 host->can_queue = req->num_outstanding_cmds - 10; 3448 3449 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3450 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3451 host->can_queue, base_vha->req, 3452 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3453 3454 /* Check if FW supports MQ or not for ISP25xx */ 3455 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3456 ha->mqenable = 0; 3457 3458 if (ha->mqenable) { 3459 bool startit = false; 3460 3461 if (QLA_TGT_MODE_ENABLED()) 3462 startit = false; 3463 3464 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3465 startit = true; 3466 3467 /* Create start of day qpairs for Block MQ */ 3468 for (i = 0; i < ha->max_qpairs; i++) 3469 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3470 } 3471 qla_init_iocb_limit(base_vha); 3472 3473 if (ha->flags.running_gold_fw) 3474 goto skip_dpc; 3475 3476 /* 3477 * Startup the kernel thread for this host adapter 3478 */ 3479 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3480 "%s_dpc", base_vha->host_str); 3481 if (IS_ERR(ha->dpc_thread)) { 3482 ql_log(ql_log_fatal, base_vha, 0x00ed, 3483 "Failed to start DPC thread.\n"); 3484 ret = PTR_ERR(ha->dpc_thread); 3485 ha->dpc_thread = NULL; 3486 goto probe_failed; 3487 } 3488 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3489 "DPC thread started successfully.\n"); 3490 3491 /* 3492 * If we're not coming up in initiator mode, we might sit for 3493 * a while without waking up the dpc thread, which leads to a 3494 * stuck process warning. So just kick the dpc once here and 3495 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3496 */ 3497 qla2xxx_wake_dpc(base_vha); 3498 3499 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3500 3501 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3502 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3503 ha->dpc_lp_wq = 3504 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name); 3505 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3506 3507 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3508 ha->dpc_hp_wq = 3509 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name); 3510 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3511 INIT_WORK(&ha->idc_state_handler, 3512 qla83xx_idc_state_handler_work); 3513 INIT_WORK(&ha->nic_core_unrecoverable, 3514 qla83xx_nic_core_unrecoverable_work); 3515 } 3516 3517 skip_dpc: 3518 list_add_tail(&base_vha->list, &ha->vp_list); 3519 base_vha->host->irq = ha->pdev->irq; 3520 3521 /* Initialized the timer */ 3522 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3523 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3524 "Started qla2x00_timer with " 3525 "interval=%d.\n", WATCH_INTERVAL); 3526 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3527 "Detected hba at address=%p.\n", 3528 ha); 3529 3530 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3531 if (ha->fw_attributes & BIT_4) { 3532 int prot = 0, guard; 3533 3534 base_vha->flags.difdix_supported = 1; 3535 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3536 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3537 if (ql2xprotmask) 3538 scsi_host_set_prot(host, ql2xprotmask); 3539 else 3540 scsi_host_set_prot(host, 3541 prot | SHOST_DIF_TYPE1_PROTECTION 3542 | SHOST_DIF_TYPE2_PROTECTION 3543 | SHOST_DIF_TYPE3_PROTECTION 3544 | SHOST_DIX_TYPE1_PROTECTION 3545 | SHOST_DIX_TYPE2_PROTECTION 3546 | SHOST_DIX_TYPE3_PROTECTION); 3547 3548 guard = SHOST_DIX_GUARD_CRC; 3549 3550 if (IS_PI_IPGUARD_CAPABLE(ha) && 3551 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3552 guard |= SHOST_DIX_GUARD_IP; 3553 3554 if (ql2xprotguard) 3555 scsi_host_set_guard(host, ql2xprotguard); 3556 else 3557 scsi_host_set_guard(host, guard); 3558 } else 3559 base_vha->flags.difdix_supported = 0; 3560 } 3561 3562 ha->isp_ops->enable_intrs(ha); 3563 3564 if (IS_QLAFX00(ha)) { 3565 ret = qlafx00_fx_disc(base_vha, 3566 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3567 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3568 QLA_SG_ALL : 128; 3569 } 3570 3571 if (IS_T10_PI_CAPABLE(base_vha->hw)) 3572 host->dma_alignment = 0x7; 3573 3574 ret = scsi_add_host(host, &pdev->dev); 3575 if (ret) 3576 goto probe_failed; 3577 3578 base_vha->flags.init_done = 1; 3579 base_vha->flags.online = 1; 3580 ha->prev_minidump_failed = 0; 3581 3582 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3583 "Init done and hba is online.\n"); 3584 3585 if (qla_ini_mode_enabled(base_vha) || 3586 qla_dual_mode_enabled(base_vha)) 3587 scsi_scan_host(host); 3588 else 3589 ql_log(ql_log_info, base_vha, 0x0122, 3590 "skipping scsi_scan_host() for non-initiator port\n"); 3591 3592 qla2x00_alloc_sysfs_attr(base_vha); 3593 3594 if (IS_QLAFX00(ha)) { 3595 ret = qlafx00_fx_disc(base_vha, 3596 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3597 3598 /* Register system information */ 3599 ret = qlafx00_fx_disc(base_vha, 3600 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3601 } 3602 3603 qla2x00_init_host_attr(base_vha); 3604 3605 qla2x00_dfs_setup(base_vha); 3606 3607 ql_log(ql_log_info, base_vha, 0x00fb, 3608 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3609 ql_log(ql_log_info, base_vha, 0x00fc, 3610 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3611 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3612 sizeof(pci_info)), 3613 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3614 base_vha->host_no, 3615 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3616 3617 qlt_add_target(ha, base_vha); 3618 3619 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3620 3621 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3622 return -ENODEV; 3623 3624 return 0; 3625 3626 probe_failed: 3627 qla_enode_stop(base_vha); 3628 qla_edb_stop(base_vha); 3629 vfree(base_vha->scan.l); 3630 if (base_vha->gnl.l) { 3631 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3632 base_vha->gnl.l, base_vha->gnl.ldma); 3633 base_vha->gnl.l = NULL; 3634 } 3635 3636 if (base_vha->timer_active) 3637 qla2x00_stop_timer(base_vha); 3638 base_vha->flags.online = 0; 3639 if (ha->dpc_thread) { 3640 struct task_struct *t = ha->dpc_thread; 3641 3642 ha->dpc_thread = NULL; 3643 kthread_stop(t); 3644 } 3645 3646 qla2x00_free_device(base_vha); 3647 scsi_host_put(base_vha->host); 3648 /* 3649 * Need to NULL out local req/rsp after 3650 * qla2x00_free_device => qla2x00_free_queues frees 3651 * what these are pointing to. Or else we'll 3652 * fall over below in qla2x00_free_req/rsp_que. 3653 */ 3654 req = NULL; 3655 rsp = NULL; 3656 3657 probe_hw_failed: 3658 qla2x00_mem_free(ha); 3659 qla2x00_free_req_que(ha, req); 3660 qla2x00_free_rsp_que(ha, rsp); 3661 qla2x00_clear_drv_active(ha); 3662 3663 iospace_config_failed: 3664 if (IS_P3P_TYPE(ha)) { 3665 if (!ha->nx_pcibase) 3666 iounmap((device_reg_t *)ha->nx_pcibase); 3667 if (!ql2xdbwr) 3668 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3669 } else { 3670 if (ha->iobase) 3671 iounmap(ha->iobase); 3672 if (ha->cregbase) 3673 iounmap(ha->cregbase); 3674 } 3675 pci_release_selected_regions(ha->pdev, ha->bars); 3676 kfree(ha); 3677 3678 disable_device: 3679 pci_disable_device(pdev); 3680 return ret; 3681 } 3682 3683 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3684 { 3685 scsi_qla_host_t *vp; 3686 unsigned long flags; 3687 struct qla_hw_data *ha; 3688 3689 if (!base_vha) 3690 return; 3691 3692 ha = base_vha->hw; 3693 3694 spin_lock_irqsave(&ha->vport_slock, flags); 3695 list_for_each_entry(vp, &ha->vp_list, list) 3696 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3697 3698 /* 3699 * Indicate device removal to prevent future board_disable 3700 * and wait until any pending board_disable has completed. 3701 */ 3702 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3703 spin_unlock_irqrestore(&ha->vport_slock, flags); 3704 } 3705 3706 static void 3707 qla2x00_shutdown(struct pci_dev *pdev) 3708 { 3709 scsi_qla_host_t *vha; 3710 struct qla_hw_data *ha; 3711 3712 vha = pci_get_drvdata(pdev); 3713 ha = vha->hw; 3714 3715 ql_log(ql_log_info, vha, 0xfffa, 3716 "Adapter shutdown\n"); 3717 3718 /* 3719 * Prevent future board_disable and wait 3720 * until any pending board_disable has completed. 3721 */ 3722 __qla_set_remove_flag(vha); 3723 cancel_work_sync(&ha->board_disable); 3724 3725 if (!atomic_read(&pdev->enable_cnt)) 3726 return; 3727 3728 /* Notify ISPFX00 firmware */ 3729 if (IS_QLAFX00(ha)) 3730 qlafx00_driver_shutdown(vha, 20); 3731 3732 /* Turn-off FCE trace */ 3733 if (ha->flags.fce_enabled) { 3734 qla2x00_disable_fce_trace(vha, NULL, NULL); 3735 ha->flags.fce_enabled = 0; 3736 } 3737 3738 /* Turn-off EFT trace */ 3739 if (ha->eft) 3740 qla2x00_disable_eft_trace(vha); 3741 3742 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3743 IS_QLA28XX(ha)) { 3744 if (ha->flags.fw_started) 3745 qla2x00_abort_isp_cleanup(vha); 3746 } else { 3747 /* Stop currently executing firmware. */ 3748 qla2x00_try_to_stop_firmware(vha); 3749 } 3750 3751 /* Disable timer */ 3752 if (vha->timer_active) 3753 qla2x00_stop_timer(vha); 3754 3755 /* Turn adapter off line */ 3756 vha->flags.online = 0; 3757 3758 /* turn-off interrupts on the card */ 3759 if (ha->interrupts_on) { 3760 vha->flags.init_done = 0; 3761 ha->isp_ops->disable_intrs(ha); 3762 } 3763 3764 qla2x00_free_irqs(vha); 3765 3766 qla2x00_free_fw_dump(ha); 3767 3768 pci_disable_device(pdev); 3769 ql_log(ql_log_info, vha, 0xfffe, 3770 "Adapter shutdown successfully.\n"); 3771 } 3772 3773 /* Deletes all the virtual ports for a given ha */ 3774 static void 3775 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3776 { 3777 scsi_qla_host_t *vha; 3778 unsigned long flags; 3779 3780 mutex_lock(&ha->vport_lock); 3781 while (ha->cur_vport_count) { 3782 spin_lock_irqsave(&ha->vport_slock, flags); 3783 3784 BUG_ON(base_vha->list.next == &ha->vp_list); 3785 /* This assumes first entry in ha->vp_list is always base vha */ 3786 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3787 scsi_host_get(vha->host); 3788 3789 spin_unlock_irqrestore(&ha->vport_slock, flags); 3790 mutex_unlock(&ha->vport_lock); 3791 3792 qla_nvme_delete(vha); 3793 3794 fc_vport_terminate(vha->fc_vport); 3795 scsi_host_put(vha->host); 3796 3797 mutex_lock(&ha->vport_lock); 3798 } 3799 mutex_unlock(&ha->vport_lock); 3800 } 3801 3802 /* Stops all deferred work threads */ 3803 static void 3804 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3805 { 3806 /* Cancel all work and destroy DPC workqueues */ 3807 if (ha->dpc_lp_wq) { 3808 cancel_work_sync(&ha->idc_aen); 3809 destroy_workqueue(ha->dpc_lp_wq); 3810 ha->dpc_lp_wq = NULL; 3811 } 3812 3813 if (ha->dpc_hp_wq) { 3814 cancel_work_sync(&ha->nic_core_reset); 3815 cancel_work_sync(&ha->idc_state_handler); 3816 cancel_work_sync(&ha->nic_core_unrecoverable); 3817 destroy_workqueue(ha->dpc_hp_wq); 3818 ha->dpc_hp_wq = NULL; 3819 } 3820 3821 /* Kill the kernel thread for this host */ 3822 if (ha->dpc_thread) { 3823 struct task_struct *t = ha->dpc_thread; 3824 3825 /* 3826 * qla2xxx_wake_dpc checks for ->dpc_thread 3827 * so we need to zero it out. 3828 */ 3829 ha->dpc_thread = NULL; 3830 kthread_stop(t); 3831 } 3832 } 3833 3834 static void 3835 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3836 { 3837 if (IS_QLA82XX(ha)) { 3838 3839 iounmap((device_reg_t *)ha->nx_pcibase); 3840 if (!ql2xdbwr) 3841 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3842 } else { 3843 if (ha->iobase) 3844 iounmap(ha->iobase); 3845 3846 if (ha->cregbase) 3847 iounmap(ha->cregbase); 3848 3849 if (ha->mqiobase) 3850 iounmap(ha->mqiobase); 3851 3852 if (ha->msixbase) 3853 iounmap(ha->msixbase); 3854 } 3855 } 3856 3857 static void 3858 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3859 { 3860 if (IS_QLA8044(ha)) { 3861 qla8044_idc_lock(ha); 3862 qla8044_clear_drv_active(ha); 3863 qla8044_idc_unlock(ha); 3864 } else if (IS_QLA82XX(ha)) { 3865 qla82xx_idc_lock(ha); 3866 qla82xx_clear_drv_active(ha); 3867 qla82xx_idc_unlock(ha); 3868 } 3869 } 3870 3871 static void 3872 qla2x00_remove_one(struct pci_dev *pdev) 3873 { 3874 scsi_qla_host_t *base_vha; 3875 struct qla_hw_data *ha; 3876 3877 base_vha = pci_get_drvdata(pdev); 3878 ha = base_vha->hw; 3879 ql_log(ql_log_info, base_vha, 0xb079, 3880 "Removing driver\n"); 3881 __qla_set_remove_flag(base_vha); 3882 cancel_work_sync(&ha->board_disable); 3883 3884 /* 3885 * If the PCI device is disabled then there was a PCI-disconnect and 3886 * qla2x00_disable_board_on_pci_error has taken care of most of the 3887 * resources. 3888 */ 3889 if (!atomic_read(&pdev->enable_cnt)) { 3890 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3891 base_vha->gnl.l, base_vha->gnl.ldma); 3892 base_vha->gnl.l = NULL; 3893 scsi_host_put(base_vha->host); 3894 kfree(ha); 3895 pci_set_drvdata(pdev, NULL); 3896 return; 3897 } 3898 qla2x00_wait_for_hba_ready(base_vha); 3899 3900 /* 3901 * if UNLOADING flag is already set, then continue unload, 3902 * where it was set first. 3903 */ 3904 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3905 return; 3906 3907 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3908 IS_QLA28XX(ha)) { 3909 if (ha->flags.fw_started) 3910 qla2x00_abort_isp_cleanup(base_vha); 3911 } else if (!IS_QLAFX00(ha)) { 3912 if (IS_QLA8031(ha)) { 3913 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3914 "Clearing fcoe driver presence.\n"); 3915 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3916 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3917 "Error while clearing DRV-Presence.\n"); 3918 } 3919 3920 qla2x00_try_to_stop_firmware(base_vha); 3921 } 3922 3923 qla2x00_wait_for_sess_deletion(base_vha); 3924 3925 qla_nvme_delete(base_vha); 3926 3927 dma_free_coherent(&ha->pdev->dev, 3928 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3929 3930 base_vha->gnl.l = NULL; 3931 qla_enode_stop(base_vha); 3932 qla_edb_stop(base_vha); 3933 3934 vfree(base_vha->scan.l); 3935 3936 if (IS_QLAFX00(ha)) 3937 qlafx00_driver_shutdown(base_vha, 20); 3938 3939 qla2x00_delete_all_vps(ha, base_vha); 3940 3941 qla2x00_dfs_remove(base_vha); 3942 3943 qla84xx_put_chip(base_vha); 3944 3945 /* Disable timer */ 3946 if (base_vha->timer_active) 3947 qla2x00_stop_timer(base_vha); 3948 3949 base_vha->flags.online = 0; 3950 3951 /* free DMA memory */ 3952 if (ha->exlogin_buf) 3953 qla2x00_free_exlogin_buffer(ha); 3954 3955 /* free DMA memory */ 3956 if (ha->exchoffld_buf) 3957 qla2x00_free_exchoffld_buffer(ha); 3958 3959 qla2x00_destroy_deferred_work(ha); 3960 3961 qlt_remove_target(ha, base_vha); 3962 3963 qla2x00_free_sysfs_attr(base_vha, true); 3964 3965 fc_remove_host(base_vha->host); 3966 3967 scsi_remove_host(base_vha->host); 3968 3969 qla2x00_free_device(base_vha); 3970 3971 qla2x00_clear_drv_active(ha); 3972 3973 scsi_host_put(base_vha->host); 3974 3975 qla2x00_unmap_iobases(ha); 3976 3977 pci_release_selected_regions(ha->pdev, ha->bars); 3978 kfree(ha); 3979 3980 pci_disable_device(pdev); 3981 } 3982 3983 static inline void 3984 qla24xx_free_purex_list(struct purex_list *list) 3985 { 3986 struct purex_item *item, *next; 3987 ulong flags; 3988 3989 spin_lock_irqsave(&list->lock, flags); 3990 list_for_each_entry_safe(item, next, &list->head, list) { 3991 list_del(&item->list); 3992 if (item == &item->vha->default_item) 3993 continue; 3994 kfree(item); 3995 } 3996 spin_unlock_irqrestore(&list->lock, flags); 3997 } 3998 3999 static void 4000 qla2x00_free_device(scsi_qla_host_t *vha) 4001 { 4002 struct qla_hw_data *ha = vha->hw; 4003 4004 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4005 4006 /* Disable timer */ 4007 if (vha->timer_active) 4008 qla2x00_stop_timer(vha); 4009 4010 qla25xx_delete_queues(vha); 4011 vha->flags.online = 0; 4012 4013 /* turn-off interrupts on the card */ 4014 if (ha->interrupts_on) { 4015 vha->flags.init_done = 0; 4016 ha->isp_ops->disable_intrs(ha); 4017 } 4018 4019 qla2x00_free_fcports(vha); 4020 4021 qla2x00_free_irqs(vha); 4022 4023 /* Flush the work queue and remove it */ 4024 if (ha->wq) { 4025 destroy_workqueue(ha->wq); 4026 ha->wq = NULL; 4027 } 4028 4029 4030 qla24xx_free_purex_list(&vha->purex_list); 4031 4032 qla2x00_mem_free(ha); 4033 4034 qla82xx_md_free(vha); 4035 4036 qla_edif_sadb_release_free_pool(ha); 4037 qla_edif_sadb_release(ha); 4038 4039 qla2x00_free_queues(ha); 4040 } 4041 4042 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4043 { 4044 fc_port_t *fcport, *tfcport; 4045 4046 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4047 qla2x00_free_fcport(fcport); 4048 } 4049 4050 static inline void 4051 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4052 { 4053 int now; 4054 4055 if (!fcport->rport) 4056 return; 4057 4058 if (fcport->rport) { 4059 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4060 "%s %8phN. rport %p roles %x\n", 4061 __func__, fcport->port_name, fcport->rport, 4062 fcport->rport->roles); 4063 fc_remote_port_delete(fcport->rport); 4064 } 4065 qlt_do_generation_tick(vha, &now); 4066 } 4067 4068 /* 4069 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4070 * 4071 * Input: ha = adapter block pointer. fcport = port structure pointer. 4072 * 4073 * Return: None. 4074 * 4075 * Context: 4076 */ 4077 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4078 int do_login) 4079 { 4080 if (IS_QLAFX00(vha->hw)) { 4081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4082 qla2x00_schedule_rport_del(vha, fcport); 4083 return; 4084 } 4085 4086 if (atomic_read(&fcport->state) == FCS_ONLINE && 4087 vha->vp_idx == fcport->vha->vp_idx) { 4088 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4089 qla2x00_schedule_rport_del(vha, fcport); 4090 } 4091 4092 /* 4093 * We may need to retry the login, so don't change the state of the 4094 * port but do the retries. 4095 */ 4096 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4097 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4098 4099 if (!do_login) 4100 return; 4101 4102 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4103 } 4104 4105 void 4106 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4107 { 4108 fc_port_t *fcport; 4109 4110 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4111 "Mark all dev lost\n"); 4112 4113 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4114 if (ql2xfc2target && 4115 fcport->loop_id != FC_NO_LOOP_ID && 4116 (fcport->flags & FCF_FCP2_DEVICE) && 4117 fcport->port_type == FCT_TARGET && 4118 !qla2x00_reset_active(vha)) { 4119 ql_dbg(ql_dbg_disc, vha, 0x211a, 4120 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4121 fcport->flags, fcport->port_type, 4122 fcport->d_id.b24, fcport->port_name); 4123 continue; 4124 } 4125 fcport->scan_state = 0; 4126 qlt_schedule_sess_for_deletion(fcport); 4127 } 4128 } 4129 4130 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4131 { 4132 int i; 4133 4134 if (IS_FWI2_CAPABLE(ha)) 4135 return; 4136 4137 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4138 set_bit(i, ha->loop_id_map); 4139 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4140 set_bit(BROADCAST, ha->loop_id_map); 4141 } 4142 4143 /* 4144 * qla2x00_mem_alloc 4145 * Allocates adapter memory. 4146 * 4147 * Returns: 4148 * 0 = success. 4149 * !0 = failure. 4150 */ 4151 static int 4152 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4153 struct req_que **req, struct rsp_que **rsp) 4154 { 4155 char name[16]; 4156 int rc; 4157 4158 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4159 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4160 if (!ha->vp_map) 4161 goto fail; 4162 } 4163 4164 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4165 &ha->init_cb_dma, GFP_KERNEL); 4166 if (!ha->init_cb) 4167 goto fail_free_vp_map; 4168 4169 rc = btree_init32(&ha->host_map); 4170 if (rc) 4171 goto fail_free_init_cb; 4172 4173 if (qlt_mem_alloc(ha) < 0) 4174 goto fail_free_btree; 4175 4176 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4177 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4178 if (!ha->gid_list) 4179 goto fail_free_tgt_mem; 4180 4181 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4182 if (!ha->srb_mempool) 4183 goto fail_free_gid_list; 4184 4185 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4186 /* Allocate cache for CT6 Ctx. */ 4187 if (!ctx_cachep) { 4188 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4189 sizeof(struct ct6_dsd), 0, 4190 SLAB_HWCACHE_ALIGN, NULL); 4191 if (!ctx_cachep) 4192 goto fail_free_srb_mempool; 4193 } 4194 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4195 ctx_cachep); 4196 if (!ha->ctx_mempool) 4197 goto fail_free_srb_mempool; 4198 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4199 "ctx_cachep=%p ctx_mempool=%p.\n", 4200 ctx_cachep, ha->ctx_mempool); 4201 } 4202 4203 /* Get memory for cached NVRAM */ 4204 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4205 if (!ha->nvram) 4206 goto fail_free_ctx_mempool; 4207 4208 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4209 ha->pdev->device); 4210 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4211 DMA_POOL_SIZE, 8, 0); 4212 if (!ha->s_dma_pool) 4213 goto fail_free_nvram; 4214 4215 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4216 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4217 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4218 4219 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4220 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4221 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4222 if (!ha->dl_dma_pool) { 4223 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4224 "Failed to allocate memory for dl_dma_pool.\n"); 4225 goto fail_s_dma_pool; 4226 } 4227 4228 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4229 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4230 if (!ha->fcp_cmnd_dma_pool) { 4231 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4232 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4233 goto fail_dl_dma_pool; 4234 } 4235 4236 if (ql2xenabledif) { 4237 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4238 struct dsd_dma *dsd, *nxt; 4239 uint i; 4240 /* Creata a DMA pool of buffers for DIF bundling */ 4241 ha->dif_bundl_pool = dma_pool_create(name, 4242 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4243 if (!ha->dif_bundl_pool) { 4244 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4245 "%s: failed create dif_bundl_pool\n", 4246 __func__); 4247 goto fail_dif_bundl_dma_pool; 4248 } 4249 4250 INIT_LIST_HEAD(&ha->pool.good.head); 4251 INIT_LIST_HEAD(&ha->pool.unusable.head); 4252 ha->pool.good.count = 0; 4253 ha->pool.unusable.count = 0; 4254 for (i = 0; i < 128; i++) { 4255 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4256 if (!dsd) { 4257 ql_dbg_pci(ql_dbg_init, ha->pdev, 4258 0xe0ee, "%s: failed alloc dsd\n", 4259 __func__); 4260 return -ENOMEM; 4261 } 4262 ha->dif_bundle_kallocs++; 4263 4264 dsd->dsd_addr = dma_pool_alloc( 4265 ha->dif_bundl_pool, GFP_ATOMIC, 4266 &dsd->dsd_list_dma); 4267 if (!dsd->dsd_addr) { 4268 ql_dbg_pci(ql_dbg_init, ha->pdev, 4269 0xe0ee, 4270 "%s: failed alloc ->dsd_addr\n", 4271 __func__); 4272 kfree(dsd); 4273 ha->dif_bundle_kallocs--; 4274 continue; 4275 } 4276 ha->dif_bundle_dma_allocs++; 4277 4278 /* 4279 * if DMA buffer crosses 4G boundary, 4280 * put it on bad list 4281 */ 4282 if (MSD(dsd->dsd_list_dma) ^ 4283 MSD(dsd->dsd_list_dma + bufsize)) { 4284 list_add_tail(&dsd->list, 4285 &ha->pool.unusable.head); 4286 ha->pool.unusable.count++; 4287 } else { 4288 list_add_tail(&dsd->list, 4289 &ha->pool.good.head); 4290 ha->pool.good.count++; 4291 } 4292 } 4293 4294 /* return the good ones back to the pool */ 4295 list_for_each_entry_safe(dsd, nxt, 4296 &ha->pool.good.head, list) { 4297 list_del(&dsd->list); 4298 dma_pool_free(ha->dif_bundl_pool, 4299 dsd->dsd_addr, dsd->dsd_list_dma); 4300 ha->dif_bundle_dma_allocs--; 4301 kfree(dsd); 4302 ha->dif_bundle_kallocs--; 4303 } 4304 4305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4306 "%s: dif dma pool (good=%u unusable=%u)\n", 4307 __func__, ha->pool.good.count, 4308 ha->pool.unusable.count); 4309 } 4310 4311 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4312 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4313 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4314 ha->dif_bundl_pool); 4315 } 4316 4317 /* Allocate memory for SNS commands */ 4318 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4319 /* Get consistent memory allocated for SNS commands */ 4320 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4321 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4322 if (!ha->sns_cmd) 4323 goto fail_dma_pool; 4324 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4325 "sns_cmd: %p.\n", ha->sns_cmd); 4326 } else { 4327 /* Get consistent memory allocated for MS IOCB */ 4328 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4329 &ha->ms_iocb_dma); 4330 if (!ha->ms_iocb) 4331 goto fail_dma_pool; 4332 /* Get consistent memory allocated for CT SNS commands */ 4333 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4334 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4335 if (!ha->ct_sns) 4336 goto fail_free_ms_iocb; 4337 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4338 "ms_iocb=%p ct_sns=%p.\n", 4339 ha->ms_iocb, ha->ct_sns); 4340 } 4341 4342 /* Allocate memory for request ring */ 4343 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4344 if (!*req) { 4345 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4346 "Failed to allocate memory for req.\n"); 4347 goto fail_req; 4348 } 4349 (*req)->length = req_len; 4350 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4351 ((*req)->length + 1) * sizeof(request_t), 4352 &(*req)->dma, GFP_KERNEL); 4353 if (!(*req)->ring) { 4354 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4355 "Failed to allocate memory for req_ring.\n"); 4356 goto fail_req_ring; 4357 } 4358 /* Allocate memory for response ring */ 4359 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4360 if (!*rsp) { 4361 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4362 "Failed to allocate memory for rsp.\n"); 4363 goto fail_rsp; 4364 } 4365 (*rsp)->hw = ha; 4366 (*rsp)->length = rsp_len; 4367 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4368 ((*rsp)->length + 1) * sizeof(response_t), 4369 &(*rsp)->dma, GFP_KERNEL); 4370 if (!(*rsp)->ring) { 4371 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4372 "Failed to allocate memory for rsp_ring.\n"); 4373 goto fail_rsp_ring; 4374 } 4375 (*req)->rsp = *rsp; 4376 (*rsp)->req = *req; 4377 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4378 "req=%p req->length=%d req->ring=%p rsp=%p " 4379 "rsp->length=%d rsp->ring=%p.\n", 4380 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4381 (*rsp)->ring); 4382 /* Allocate memory for NVRAM data for vports */ 4383 if (ha->nvram_npiv_size) { 4384 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4385 sizeof(struct qla_npiv_entry), 4386 GFP_KERNEL); 4387 if (!ha->npiv_info) { 4388 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4389 "Failed to allocate memory for npiv_info.\n"); 4390 goto fail_npiv_info; 4391 } 4392 } else 4393 ha->npiv_info = NULL; 4394 4395 /* Get consistent memory allocated for EX-INIT-CB. */ 4396 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4397 IS_QLA28XX(ha)) { 4398 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4399 &ha->ex_init_cb_dma); 4400 if (!ha->ex_init_cb) 4401 goto fail_ex_init_cb; 4402 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4403 "ex_init_cb=%p.\n", ha->ex_init_cb); 4404 } 4405 4406 /* Get consistent memory allocated for Special Features-CB. */ 4407 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4408 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4409 &ha->sf_init_cb_dma); 4410 if (!ha->sf_init_cb) 4411 goto fail_sf_init_cb; 4412 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4413 "sf_init_cb=%p.\n", ha->sf_init_cb); 4414 } 4415 4416 4417 /* Get consistent memory allocated for Async Port-Database. */ 4418 if (!IS_FWI2_CAPABLE(ha)) { 4419 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4420 &ha->async_pd_dma); 4421 if (!ha->async_pd) 4422 goto fail_async_pd; 4423 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4424 "async_pd=%p.\n", ha->async_pd); 4425 } 4426 4427 INIT_LIST_HEAD(&ha->vp_list); 4428 4429 /* Allocate memory for our loop_id bitmap */ 4430 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4431 sizeof(long), 4432 GFP_KERNEL); 4433 if (!ha->loop_id_map) 4434 goto fail_loop_id_map; 4435 else { 4436 qla2x00_set_reserved_loop_ids(ha); 4437 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4438 "loop_id_map=%p.\n", ha->loop_id_map); 4439 } 4440 4441 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4442 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4443 if (!ha->sfp_data) { 4444 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4445 "Unable to allocate memory for SFP read-data.\n"); 4446 goto fail_sfp_data; 4447 } 4448 4449 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4450 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4451 GFP_KERNEL); 4452 if (!ha->flt) { 4453 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4454 "Unable to allocate memory for FLT.\n"); 4455 goto fail_flt_buffer; 4456 } 4457 4458 /* allocate the purex dma pool */ 4459 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4460 ELS_MAX_PAYLOAD, 8, 0); 4461 4462 if (!ha->purex_dma_pool) { 4463 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4464 "Unable to allocate purex_dma_pool.\n"); 4465 goto fail_flt; 4466 } 4467 4468 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4469 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4470 ha->elsrej.size, 4471 &ha->elsrej.cdma, 4472 GFP_KERNEL); 4473 if (!ha->elsrej.c) { 4474 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4475 "Alloc failed for els reject cmd.\n"); 4476 goto fail_elsrej; 4477 } 4478 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4479 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4480 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4481 4482 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt); 4483 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size, 4484 &ha->lsrjt.cdma, GFP_KERNEL); 4485 if (!ha->lsrjt.c) { 4486 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4487 "Alloc failed for nvme fc reject cmd.\n"); 4488 goto fail_lsrjt; 4489 } 4490 4491 return 0; 4492 4493 fail_lsrjt: 4494 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4495 ha->elsrej.c, ha->elsrej.cdma); 4496 fail_elsrej: 4497 dma_pool_destroy(ha->purex_dma_pool); 4498 fail_flt: 4499 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4500 ha->flt, ha->flt_dma); 4501 4502 fail_flt_buffer: 4503 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4504 ha->sfp_data, ha->sfp_data_dma); 4505 fail_sfp_data: 4506 kfree(ha->loop_id_map); 4507 fail_loop_id_map: 4508 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4509 fail_async_pd: 4510 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4511 fail_sf_init_cb: 4512 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4513 fail_ex_init_cb: 4514 kfree(ha->npiv_info); 4515 fail_npiv_info: 4516 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4517 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4518 (*rsp)->ring = NULL; 4519 (*rsp)->dma = 0; 4520 fail_rsp_ring: 4521 kfree(*rsp); 4522 *rsp = NULL; 4523 fail_rsp: 4524 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4525 sizeof(request_t), (*req)->ring, (*req)->dma); 4526 (*req)->ring = NULL; 4527 (*req)->dma = 0; 4528 fail_req_ring: 4529 kfree(*req); 4530 *req = NULL; 4531 fail_req: 4532 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4533 ha->ct_sns, ha->ct_sns_dma); 4534 ha->ct_sns = NULL; 4535 ha->ct_sns_dma = 0; 4536 fail_free_ms_iocb: 4537 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4538 ha->ms_iocb = NULL; 4539 ha->ms_iocb_dma = 0; 4540 4541 if (ha->sns_cmd) 4542 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4543 ha->sns_cmd, ha->sns_cmd_dma); 4544 fail_dma_pool: 4545 if (ql2xenabledif) { 4546 struct dsd_dma *dsd, *nxt; 4547 4548 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4549 list) { 4550 list_del(&dsd->list); 4551 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4552 dsd->dsd_list_dma); 4553 ha->dif_bundle_dma_allocs--; 4554 kfree(dsd); 4555 ha->dif_bundle_kallocs--; 4556 ha->pool.unusable.count--; 4557 } 4558 dma_pool_destroy(ha->dif_bundl_pool); 4559 ha->dif_bundl_pool = NULL; 4560 } 4561 4562 fail_dif_bundl_dma_pool: 4563 if (IS_QLA82XX(ha) || ql2xenabledif) { 4564 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4565 ha->fcp_cmnd_dma_pool = NULL; 4566 } 4567 fail_dl_dma_pool: 4568 if (IS_QLA82XX(ha) || ql2xenabledif) { 4569 dma_pool_destroy(ha->dl_dma_pool); 4570 ha->dl_dma_pool = NULL; 4571 } 4572 fail_s_dma_pool: 4573 dma_pool_destroy(ha->s_dma_pool); 4574 ha->s_dma_pool = NULL; 4575 fail_free_nvram: 4576 kfree(ha->nvram); 4577 ha->nvram = NULL; 4578 fail_free_ctx_mempool: 4579 mempool_destroy(ha->ctx_mempool); 4580 ha->ctx_mempool = NULL; 4581 fail_free_srb_mempool: 4582 mempool_destroy(ha->srb_mempool); 4583 ha->srb_mempool = NULL; 4584 fail_free_gid_list: 4585 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4586 ha->gid_list, 4587 ha->gid_list_dma); 4588 ha->gid_list = NULL; 4589 ha->gid_list_dma = 0; 4590 fail_free_tgt_mem: 4591 qlt_mem_free(ha); 4592 fail_free_btree: 4593 btree_destroy32(&ha->host_map); 4594 fail_free_init_cb: 4595 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4596 ha->init_cb_dma); 4597 ha->init_cb = NULL; 4598 ha->init_cb_dma = 0; 4599 fail_free_vp_map: 4600 kfree(ha->vp_map); 4601 ha->vp_map = NULL; 4602 fail: 4603 ql_log(ql_log_fatal, NULL, 0x0030, 4604 "Memory allocation failure.\n"); 4605 return -ENOMEM; 4606 } 4607 4608 int 4609 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4610 { 4611 int rval; 4612 uint16_t size, max_cnt; 4613 uint32_t temp; 4614 struct qla_hw_data *ha = vha->hw; 4615 4616 /* Return if we don't need to alloacate any extended logins */ 4617 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4618 return QLA_SUCCESS; 4619 4620 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4621 return QLA_SUCCESS; 4622 4623 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4624 max_cnt = 0; 4625 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4626 if (rval != QLA_SUCCESS) { 4627 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4628 "Failed to get exlogin status.\n"); 4629 return rval; 4630 } 4631 4632 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4633 temp *= size; 4634 4635 if (temp != ha->exlogin_size) { 4636 qla2x00_free_exlogin_buffer(ha); 4637 ha->exlogin_size = temp; 4638 4639 ql_log(ql_log_info, vha, 0xd024, 4640 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4641 max_cnt, size, temp); 4642 4643 ql_log(ql_log_info, vha, 0xd025, 4644 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4645 4646 /* Get consistent memory for extended logins */ 4647 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4648 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4649 if (!ha->exlogin_buf) { 4650 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4651 "Failed to allocate memory for exlogin_buf_dma.\n"); 4652 return -ENOMEM; 4653 } 4654 } 4655 4656 /* Now configure the dma buffer */ 4657 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4658 if (rval) { 4659 ql_log(ql_log_fatal, vha, 0xd033, 4660 "Setup extended login buffer ****FAILED****.\n"); 4661 qla2x00_free_exlogin_buffer(ha); 4662 } 4663 4664 return rval; 4665 } 4666 4667 /* 4668 * qla2x00_free_exlogin_buffer 4669 * 4670 * Input: 4671 * ha = adapter block pointer 4672 */ 4673 void 4674 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4675 { 4676 if (ha->exlogin_buf) { 4677 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4678 ha->exlogin_buf, ha->exlogin_buf_dma); 4679 ha->exlogin_buf = NULL; 4680 ha->exlogin_size = 0; 4681 } 4682 } 4683 4684 static void 4685 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4686 { 4687 u32 temp; 4688 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb; 4689 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4690 4691 if (max_cnt > vha->hw->max_exchg) 4692 max_cnt = vha->hw->max_exchg; 4693 4694 if (qla_ini_mode_enabled(vha)) { 4695 if (vha->ql2xiniexchg > max_cnt) 4696 vha->ql2xiniexchg = max_cnt; 4697 4698 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4699 *ret_cnt = vha->ql2xiniexchg; 4700 4701 } else if (qla_tgt_mode_enabled(vha)) { 4702 if (vha->ql2xexchoffld > max_cnt) { 4703 vha->ql2xexchoffld = max_cnt; 4704 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4705 } 4706 4707 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4708 *ret_cnt = vha->ql2xexchoffld; 4709 } else if (qla_dual_mode_enabled(vha)) { 4710 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4711 if (temp > max_cnt) { 4712 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4713 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4714 temp = max_cnt; 4715 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4716 } 4717 4718 if (temp > FW_DEF_EXCHANGES_CNT) 4719 *ret_cnt = temp; 4720 } 4721 } 4722 4723 int 4724 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4725 { 4726 int rval; 4727 u16 size, max_cnt; 4728 u32 actual_cnt, totsz; 4729 struct qla_hw_data *ha = vha->hw; 4730 4731 if (!ha->flags.exchoffld_enabled) 4732 return QLA_SUCCESS; 4733 4734 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4735 return QLA_SUCCESS; 4736 4737 max_cnt = 0; 4738 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4739 if (rval != QLA_SUCCESS) { 4740 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4741 "Failed to get exlogin status.\n"); 4742 return rval; 4743 } 4744 4745 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4746 ql_log(ql_log_info, vha, 0xd014, 4747 "Actual exchange offload count: %d.\n", actual_cnt); 4748 4749 totsz = actual_cnt * size; 4750 4751 if (totsz != ha->exchoffld_size) { 4752 qla2x00_free_exchoffld_buffer(ha); 4753 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4754 ha->exchoffld_size = 0; 4755 ha->flags.exchoffld_enabled = 0; 4756 return QLA_SUCCESS; 4757 } 4758 4759 ha->exchoffld_size = totsz; 4760 4761 ql_log(ql_log_info, vha, 0xd016, 4762 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4763 max_cnt, actual_cnt, size, totsz); 4764 4765 ql_log(ql_log_info, vha, 0xd017, 4766 "Exchange Buffers requested size = 0x%x\n", 4767 ha->exchoffld_size); 4768 4769 /* Get consistent memory for extended logins */ 4770 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4771 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4772 if (!ha->exchoffld_buf) { 4773 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4774 "Failed to allocate memory for Exchange Offload.\n"); 4775 4776 if (ha->max_exchg > 4777 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4778 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4779 } else if (ha->max_exchg > 4780 (FW_DEF_EXCHANGES_CNT + 512)) { 4781 ha->max_exchg -= 512; 4782 } else { 4783 ha->flags.exchoffld_enabled = 0; 4784 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4785 "Disabling Exchange offload due to lack of memory\n"); 4786 } 4787 ha->exchoffld_size = 0; 4788 4789 return -ENOMEM; 4790 } 4791 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4792 /* pathological case */ 4793 qla2x00_free_exchoffld_buffer(ha); 4794 ha->exchoffld_size = 0; 4795 ha->flags.exchoffld_enabled = 0; 4796 ql_log(ql_log_info, vha, 0xd016, 4797 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4798 ha->exchoffld_size, actual_cnt, size, totsz); 4799 return 0; 4800 } 4801 4802 /* Now configure the dma buffer */ 4803 rval = qla_set_exchoffld_mem_cfg(vha); 4804 if (rval) { 4805 ql_log(ql_log_fatal, vha, 0xd02e, 4806 "Setup exchange offload buffer ****FAILED****.\n"); 4807 qla2x00_free_exchoffld_buffer(ha); 4808 } else { 4809 /* re-adjust number of target exchange */ 4810 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4811 4812 if (qla_ini_mode_enabled(vha)) 4813 icb->exchange_count = 0; 4814 else 4815 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4816 } 4817 4818 return rval; 4819 } 4820 4821 /* 4822 * qla2x00_free_exchoffld_buffer 4823 * 4824 * Input: 4825 * ha = adapter block pointer 4826 */ 4827 void 4828 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4829 { 4830 if (ha->exchoffld_buf) { 4831 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4832 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4833 ha->exchoffld_buf = NULL; 4834 ha->exchoffld_size = 0; 4835 } 4836 } 4837 4838 /* 4839 * qla2x00_free_fw_dump 4840 * Frees fw dump stuff. 4841 * 4842 * Input: 4843 * ha = adapter block pointer 4844 */ 4845 static void 4846 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4847 { 4848 struct fwdt *fwdt = ha->fwdt; 4849 uint j; 4850 4851 if (ha->fce) 4852 dma_free_coherent(&ha->pdev->dev, 4853 FCE_SIZE, ha->fce, ha->fce_dma); 4854 4855 if (ha->eft) 4856 dma_free_coherent(&ha->pdev->dev, 4857 EFT_SIZE, ha->eft, ha->eft_dma); 4858 4859 vfree(ha->fw_dump); 4860 4861 ha->fce = NULL; 4862 ha->fce_dma = 0; 4863 ha->flags.fce_enabled = 0; 4864 ha->eft = NULL; 4865 ha->eft_dma = 0; 4866 ha->fw_dumped = false; 4867 ha->fw_dump_cap_flags = 0; 4868 ha->fw_dump_reading = 0; 4869 ha->fw_dump = NULL; 4870 ha->fw_dump_len = 0; 4871 4872 for (j = 0; j < 2; j++, fwdt++) { 4873 vfree(fwdt->template); 4874 fwdt->template = NULL; 4875 fwdt->length = 0; 4876 } 4877 } 4878 4879 /* 4880 * qla2x00_mem_free 4881 * Frees all adapter allocated memory. 4882 * 4883 * Input: 4884 * ha = adapter block pointer. 4885 */ 4886 static void 4887 qla2x00_mem_free(struct qla_hw_data *ha) 4888 { 4889 qla2x00_free_fw_dump(ha); 4890 4891 if (ha->mctp_dump) 4892 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4893 ha->mctp_dump_dma); 4894 ha->mctp_dump = NULL; 4895 4896 mempool_destroy(ha->srb_mempool); 4897 ha->srb_mempool = NULL; 4898 4899 if (ha->dcbx_tlv) 4900 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4901 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4902 ha->dcbx_tlv = NULL; 4903 4904 if (ha->xgmac_data) 4905 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4906 ha->xgmac_data, ha->xgmac_data_dma); 4907 ha->xgmac_data = NULL; 4908 4909 if (ha->sns_cmd) 4910 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4911 ha->sns_cmd, ha->sns_cmd_dma); 4912 ha->sns_cmd = NULL; 4913 ha->sns_cmd_dma = 0; 4914 4915 if (ha->ct_sns) 4916 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4917 ha->ct_sns, ha->ct_sns_dma); 4918 ha->ct_sns = NULL; 4919 ha->ct_sns_dma = 0; 4920 4921 if (ha->sfp_data) 4922 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4923 ha->sfp_data_dma); 4924 ha->sfp_data = NULL; 4925 4926 if (ha->flt) 4927 dma_free_coherent(&ha->pdev->dev, 4928 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4929 ha->flt, ha->flt_dma); 4930 ha->flt = NULL; 4931 ha->flt_dma = 0; 4932 4933 if (ha->ms_iocb) 4934 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4935 ha->ms_iocb = NULL; 4936 ha->ms_iocb_dma = 0; 4937 4938 if (ha->sf_init_cb) 4939 dma_pool_free(ha->s_dma_pool, 4940 ha->sf_init_cb, ha->sf_init_cb_dma); 4941 4942 if (ha->ex_init_cb) 4943 dma_pool_free(ha->s_dma_pool, 4944 ha->ex_init_cb, ha->ex_init_cb_dma); 4945 ha->ex_init_cb = NULL; 4946 ha->ex_init_cb_dma = 0; 4947 4948 if (ha->async_pd) 4949 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4950 ha->async_pd = NULL; 4951 ha->async_pd_dma = 0; 4952 4953 dma_pool_destroy(ha->s_dma_pool); 4954 ha->s_dma_pool = NULL; 4955 4956 if (ha->gid_list) 4957 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4958 ha->gid_list, ha->gid_list_dma); 4959 ha->gid_list = NULL; 4960 ha->gid_list_dma = 0; 4961 4962 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) { 4963 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4964 4965 /* clean up allocated prev pool */ 4966 list_for_each_entry_safe(dsd_ptr, tdsd_ptr, 4967 &ha->base_qpair->dsd_list, list) { 4968 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr, 4969 dsd_ptr->dsd_list_dma); 4970 list_del(&dsd_ptr->list); 4971 kfree(dsd_ptr); 4972 } 4973 } 4974 4975 dma_pool_destroy(ha->dl_dma_pool); 4976 ha->dl_dma_pool = NULL; 4977 4978 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4979 ha->fcp_cmnd_dma_pool = NULL; 4980 4981 mempool_destroy(ha->ctx_mempool); 4982 ha->ctx_mempool = NULL; 4983 4984 if (ql2xenabledif && ha->dif_bundl_pool) { 4985 struct dsd_dma *dsd, *nxt; 4986 4987 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4988 list) { 4989 list_del(&dsd->list); 4990 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4991 dsd->dsd_list_dma); 4992 ha->dif_bundle_dma_allocs--; 4993 kfree(dsd); 4994 ha->dif_bundle_kallocs--; 4995 ha->pool.unusable.count--; 4996 } 4997 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4998 list_del(&dsd->list); 4999 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 5000 dsd->dsd_list_dma); 5001 ha->dif_bundle_dma_allocs--; 5002 kfree(dsd); 5003 ha->dif_bundle_kallocs--; 5004 } 5005 } 5006 5007 dma_pool_destroy(ha->dif_bundl_pool); 5008 ha->dif_bundl_pool = NULL; 5009 5010 qlt_mem_free(ha); 5011 qla_remove_hostmap(ha); 5012 5013 if (ha->init_cb) 5014 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 5015 ha->init_cb, ha->init_cb_dma); 5016 5017 dma_pool_destroy(ha->purex_dma_pool); 5018 ha->purex_dma_pool = NULL; 5019 5020 if (ha->elsrej.c) { 5021 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 5022 ha->elsrej.c, ha->elsrej.cdma); 5023 ha->elsrej.c = NULL; 5024 } 5025 5026 if (ha->lsrjt.c) { 5027 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c, 5028 ha->lsrjt.cdma); 5029 ha->lsrjt.c = NULL; 5030 } 5031 5032 ha->init_cb = NULL; 5033 ha->init_cb_dma = 0; 5034 5035 vfree(ha->optrom_buffer); 5036 ha->optrom_buffer = NULL; 5037 kfree(ha->nvram); 5038 ha->nvram = NULL; 5039 kfree(ha->npiv_info); 5040 ha->npiv_info = NULL; 5041 kfree(ha->swl); 5042 ha->swl = NULL; 5043 kfree(ha->loop_id_map); 5044 ha->sf_init_cb = NULL; 5045 ha->sf_init_cb_dma = 0; 5046 ha->loop_id_map = NULL; 5047 5048 kfree(ha->vp_map); 5049 ha->vp_map = NULL; 5050 } 5051 5052 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5053 struct qla_hw_data *ha) 5054 { 5055 struct Scsi_Host *host; 5056 struct scsi_qla_host *vha = NULL; 5057 5058 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5059 if (!host) { 5060 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5061 "Failed to allocate host from the scsi layer, aborting.\n"); 5062 return NULL; 5063 } 5064 5065 /* Clear our data area */ 5066 vha = shost_priv(host); 5067 memset(vha, 0, sizeof(scsi_qla_host_t)); 5068 5069 vha->host = host; 5070 vha->host_no = host->host_no; 5071 vha->hw = ha; 5072 5073 vha->qlini_mode = ql2x_ini_mode; 5074 vha->ql2xexchoffld = ql2xexchoffld; 5075 vha->ql2xiniexchg = ql2xiniexchg; 5076 5077 INIT_LIST_HEAD(&vha->vp_fcports); 5078 INIT_LIST_HEAD(&vha->work_list); 5079 INIT_LIST_HEAD(&vha->list); 5080 INIT_LIST_HEAD(&vha->qla_cmd_list); 5081 INIT_LIST_HEAD(&vha->logo_list); 5082 INIT_LIST_HEAD(&vha->plogi_ack_list); 5083 INIT_LIST_HEAD(&vha->qp_list); 5084 INIT_LIST_HEAD(&vha->gnl.fcports); 5085 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5086 5087 INIT_LIST_HEAD(&vha->purex_list.head); 5088 spin_lock_init(&vha->purex_list.lock); 5089 5090 spin_lock_init(&vha->work_lock); 5091 spin_lock_init(&vha->cmd_list_lock); 5092 init_waitqueue_head(&vha->fcport_waitQ); 5093 init_waitqueue_head(&vha->vref_waitq); 5094 qla_enode_init(vha); 5095 qla_edb_init(vha); 5096 5097 5098 vha->gnl.size = sizeof(struct get_name_list_extended) * 5099 (ha->max_loop_id + 1); 5100 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5101 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5102 if (!vha->gnl.l) { 5103 ql_log(ql_log_fatal, vha, 0xd04a, 5104 "Alloc failed for name list.\n"); 5105 scsi_host_put(vha->host); 5106 return NULL; 5107 } 5108 5109 /* todo: what about ext login? */ 5110 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5111 vha->scan.l = vmalloc(vha->scan.size); 5112 if (!vha->scan.l) { 5113 ql_log(ql_log_fatal, vha, 0xd04a, 5114 "Alloc failed for scan database.\n"); 5115 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5116 vha->gnl.l, vha->gnl.ldma); 5117 vha->gnl.l = NULL; 5118 scsi_host_put(vha->host); 5119 return NULL; 5120 } 5121 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5122 5123 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", 5124 QLA2XXX_DRIVER_NAME, vha->host_no); 5125 ql_dbg(ql_dbg_init, vha, 0x0041, 5126 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5127 vha->host, vha->hw, vha, 5128 dev_name(&(ha->pdev->dev))); 5129 5130 return vha; 5131 } 5132 5133 struct qla_work_evt * 5134 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5135 { 5136 struct qla_work_evt *e; 5137 5138 if (test_bit(UNLOADING, &vha->dpc_flags)) 5139 return NULL; 5140 5141 if (qla_vha_mark_busy(vha)) 5142 return NULL; 5143 5144 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5145 if (!e) { 5146 QLA_VHA_MARK_NOT_BUSY(vha); 5147 return NULL; 5148 } 5149 5150 INIT_LIST_HEAD(&e->list); 5151 e->type = type; 5152 e->flags = QLA_EVT_FLAG_FREE; 5153 return e; 5154 } 5155 5156 int 5157 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5158 { 5159 unsigned long flags; 5160 bool q = false; 5161 5162 spin_lock_irqsave(&vha->work_lock, flags); 5163 list_add_tail(&e->list, &vha->work_list); 5164 5165 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5166 q = true; 5167 5168 spin_unlock_irqrestore(&vha->work_lock, flags); 5169 5170 if (q) 5171 queue_work(vha->hw->wq, &vha->iocb_work); 5172 5173 return QLA_SUCCESS; 5174 } 5175 5176 int 5177 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5178 u32 data) 5179 { 5180 struct qla_work_evt *e; 5181 5182 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5183 if (!e) 5184 return QLA_FUNCTION_FAILED; 5185 5186 e->u.aen.code = code; 5187 e->u.aen.data = data; 5188 return qla2x00_post_work(vha, e); 5189 } 5190 5191 int 5192 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5193 { 5194 struct qla_work_evt *e; 5195 5196 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5197 if (!e) 5198 return QLA_FUNCTION_FAILED; 5199 5200 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5201 return qla2x00_post_work(vha, e); 5202 } 5203 5204 #define qla2x00_post_async_work(name, type) \ 5205 int qla2x00_post_async_##name##_work( \ 5206 struct scsi_qla_host *vha, \ 5207 fc_port_t *fcport, uint16_t *data) \ 5208 { \ 5209 struct qla_work_evt *e; \ 5210 \ 5211 e = qla2x00_alloc_work(vha, type); \ 5212 if (!e) \ 5213 return QLA_FUNCTION_FAILED; \ 5214 \ 5215 e->u.logio.fcport = fcport; \ 5216 if (data) { \ 5217 e->u.logio.data[0] = data[0]; \ 5218 e->u.logio.data[1] = data[1]; \ 5219 } \ 5220 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5221 return qla2x00_post_work(vha, e); \ 5222 } 5223 5224 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5225 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5226 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5227 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5228 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5229 5230 int 5231 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5232 { 5233 struct qla_work_evt *e; 5234 5235 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5236 if (!e) 5237 return QLA_FUNCTION_FAILED; 5238 5239 e->u.uevent.code = code; 5240 return qla2x00_post_work(vha, e); 5241 } 5242 5243 static void 5244 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5245 { 5246 char event_string[40]; 5247 char *envp[] = { event_string, NULL }; 5248 5249 switch (code) { 5250 case QLA_UEVENT_CODE_FW_DUMP: 5251 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5252 vha->host_no); 5253 break; 5254 default: 5255 /* do nothing */ 5256 break; 5257 } 5258 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5259 } 5260 5261 int 5262 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5263 uint32_t *data, int cnt) 5264 { 5265 struct qla_work_evt *e; 5266 5267 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5268 if (!e) 5269 return QLA_FUNCTION_FAILED; 5270 5271 e->u.aenfx.evtcode = evtcode; 5272 e->u.aenfx.count = cnt; 5273 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5274 return qla2x00_post_work(vha, e); 5275 } 5276 5277 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5278 { 5279 unsigned long flags; 5280 5281 if (IS_SW_RESV_ADDR(fcport->d_id)) 5282 return; 5283 5284 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5285 if (fcport->disc_state == DSC_UPD_FCPORT) { 5286 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5287 return; 5288 } 5289 fcport->jiffies_at_registration = jiffies; 5290 fcport->sec_since_registration = 0; 5291 fcport->next_disc_state = DSC_DELETED; 5292 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5293 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5294 5295 queue_work(system_unbound_wq, &fcport->reg_work); 5296 } 5297 5298 static 5299 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5300 { 5301 unsigned long flags; 5302 fc_port_t *fcport = NULL, *tfcp; 5303 struct qlt_plogi_ack_t *pla = 5304 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5305 uint8_t free_fcport = 0; 5306 5307 ql_dbg(ql_dbg_disc, vha, 0xffff, 5308 "%s %d %8phC enter\n", 5309 __func__, __LINE__, e->u.new_sess.port_name); 5310 5311 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5312 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5313 if (fcport) { 5314 fcport->d_id = e->u.new_sess.id; 5315 if (pla) { 5316 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5317 memcpy(fcport->node_name, 5318 pla->iocb.u.isp24.u.plogi.node_name, 5319 WWN_SIZE); 5320 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5321 /* we took an extra ref_count to prevent PLOGI ACK when 5322 * fcport/sess has not been created. 5323 */ 5324 pla->ref_count--; 5325 } 5326 } else { 5327 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5328 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5329 if (fcport) { 5330 fcport->d_id = e->u.new_sess.id; 5331 fcport->flags |= FCF_FABRIC_DEVICE; 5332 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5333 fcport->tgt_short_link_down_cnt = 0; 5334 5335 memcpy(fcport->port_name, e->u.new_sess.port_name, 5336 WWN_SIZE); 5337 5338 fcport->fc4_type = e->u.new_sess.fc4_type; 5339 if (NVME_PRIORITY(vha->hw, fcport)) 5340 fcport->do_prli_nvme = 1; 5341 else 5342 fcport->do_prli_nvme = 0; 5343 5344 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5345 fcport->dm_login_expire = jiffies + 5346 QLA_N2N_WAIT_TIME * HZ; 5347 fcport->fc4_type = FS_FC4TYPE_FCP; 5348 fcport->n2n_flag = 1; 5349 if (vha->flags.nvme_enabled) 5350 fcport->fc4_type |= FS_FC4TYPE_NVME; 5351 } 5352 5353 } else { 5354 ql_dbg(ql_dbg_disc, vha, 0xffff, 5355 "%s %8phC mem alloc fail.\n", 5356 __func__, e->u.new_sess.port_name); 5357 5358 if (pla) { 5359 list_del(&pla->list); 5360 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5361 } 5362 return; 5363 } 5364 5365 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5366 /* search again to make sure no one else got ahead */ 5367 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5368 e->u.new_sess.port_name, 1); 5369 if (tfcp) { 5370 /* should rarily happen */ 5371 ql_dbg(ql_dbg_disc, vha, 0xffff, 5372 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5373 __func__, tfcp->port_name, tfcp->disc_state, 5374 tfcp->fw_login_state); 5375 5376 free_fcport = 1; 5377 } else { 5378 list_add_tail(&fcport->list, &vha->vp_fcports); 5379 5380 } 5381 if (pla) { 5382 qlt_plogi_ack_link(vha, pla, fcport, 5383 QLT_PLOGI_LINK_SAME_WWN); 5384 pla->ref_count--; 5385 } 5386 } 5387 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5388 5389 if (fcport) { 5390 fcport->id_changed = 1; 5391 fcport->scan_state = QLA_FCPORT_FOUND; 5392 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5393 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5394 5395 if (pla) { 5396 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5397 u16 wd3_lo; 5398 5399 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5400 fcport->local = 0; 5401 fcport->loop_id = 5402 le16_to_cpu( 5403 pla->iocb.u.isp24.nport_handle); 5404 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5405 wd3_lo = 5406 le16_to_cpu( 5407 pla->iocb.u.isp24.u.prli.wd3_lo); 5408 5409 if (wd3_lo & BIT_7) 5410 fcport->conf_compl_supported = 1; 5411 5412 if ((wd3_lo & BIT_4) == 0) 5413 fcport->port_type = FCT_INITIATOR; 5414 else 5415 fcport->port_type = FCT_TARGET; 5416 } 5417 qlt_plogi_ack_unref(vha, pla); 5418 } else { 5419 fc_port_t *dfcp = NULL; 5420 5421 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5422 tfcp = qla2x00_find_fcport_by_nportid(vha, 5423 &e->u.new_sess.id, 1); 5424 if (tfcp && (tfcp != fcport)) { 5425 /* 5426 * We have a conflict fcport with same NportID. 5427 */ 5428 ql_dbg(ql_dbg_disc, vha, 0xffff, 5429 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5430 __func__, tfcp->port_name, tfcp->disc_state, 5431 tfcp->fw_login_state); 5432 5433 switch (tfcp->disc_state) { 5434 case DSC_DELETED: 5435 break; 5436 case DSC_DELETE_PEND: 5437 fcport->login_pause = 1; 5438 tfcp->conflict = fcport; 5439 break; 5440 default: 5441 fcport->login_pause = 1; 5442 tfcp->conflict = fcport; 5443 dfcp = tfcp; 5444 break; 5445 } 5446 } 5447 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5448 if (dfcp) 5449 qlt_schedule_sess_for_deletion(tfcp); 5450 5451 if (N2N_TOPO(vha->hw)) { 5452 fcport->flags &= ~FCF_FABRIC_DEVICE; 5453 fcport->keep_nport_handle = 1; 5454 if (vha->flags.nvme_enabled) { 5455 fcport->fc4_type = 5456 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5457 fcport->n2n_flag = 1; 5458 } 5459 fcport->fw_login_state = 0; 5460 5461 schedule_delayed_work(&vha->scan.scan_work, 5); 5462 } else { 5463 qla24xx_fcport_handle_login(vha, fcport); 5464 } 5465 } 5466 } 5467 5468 if (free_fcport) { 5469 qla2x00_free_fcport(fcport); 5470 if (pla) { 5471 list_del(&pla->list); 5472 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5473 } 5474 } 5475 } 5476 5477 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5478 { 5479 struct srb *sp = e->u.iosb.sp; 5480 int rval; 5481 5482 rval = qla2x00_start_sp(sp); 5483 if (rval != QLA_SUCCESS) { 5484 ql_dbg(ql_dbg_disc, vha, 0x2043, 5485 "%s: %s: Re-issue IOCB failed (%d).\n", 5486 __func__, sp->name, rval); 5487 qla24xx_sp_unmap(vha, sp); 5488 } 5489 } 5490 5491 void 5492 qla2x00_do_work(struct scsi_qla_host *vha) 5493 { 5494 struct qla_work_evt *e, *tmp; 5495 unsigned long flags; 5496 LIST_HEAD(work); 5497 int rc; 5498 5499 spin_lock_irqsave(&vha->work_lock, flags); 5500 list_splice_init(&vha->work_list, &work); 5501 spin_unlock_irqrestore(&vha->work_lock, flags); 5502 5503 list_for_each_entry_safe(e, tmp, &work, list) { 5504 rc = QLA_SUCCESS; 5505 switch (e->type) { 5506 case QLA_EVT_AEN: 5507 fc_host_post_event(vha->host, fc_get_event_number(), 5508 e->u.aen.code, e->u.aen.data); 5509 break; 5510 case QLA_EVT_IDC_ACK: 5511 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5512 break; 5513 case QLA_EVT_ASYNC_LOGIN: 5514 qla2x00_async_login(vha, e->u.logio.fcport, 5515 e->u.logio.data); 5516 break; 5517 case QLA_EVT_ASYNC_LOGOUT: 5518 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5519 break; 5520 case QLA_EVT_ASYNC_ADISC: 5521 qla2x00_async_adisc(vha, e->u.logio.fcport, 5522 e->u.logio.data); 5523 break; 5524 case QLA_EVT_UEVENT: 5525 qla2x00_uevent_emit(vha, e->u.uevent.code); 5526 break; 5527 case QLA_EVT_AENFX: 5528 qlafx00_process_aen(vha, e); 5529 break; 5530 case QLA_EVT_UNMAP: 5531 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5532 break; 5533 case QLA_EVT_RELOGIN: 5534 qla2x00_relogin(vha); 5535 break; 5536 case QLA_EVT_NEW_SESS: 5537 qla24xx_create_new_sess(vha, e); 5538 break; 5539 case QLA_EVT_GPDB: 5540 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5541 e->u.fcport.opt); 5542 break; 5543 case QLA_EVT_PRLI: 5544 qla24xx_async_prli(vha, e->u.fcport.fcport); 5545 break; 5546 case QLA_EVT_GPSC: 5547 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5548 break; 5549 case QLA_EVT_GNL: 5550 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5551 break; 5552 case QLA_EVT_NACK: 5553 qla24xx_do_nack_work(vha, e); 5554 break; 5555 case QLA_EVT_ASYNC_PRLO: 5556 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5557 break; 5558 case QLA_EVT_ASYNC_PRLO_DONE: 5559 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5560 e->u.logio.data); 5561 break; 5562 case QLA_EVT_SCAN_CMD: 5563 qla_fab_async_scan(vha, e->u.iosb.sp); 5564 break; 5565 case QLA_EVT_SCAN_FINISH: 5566 qla_fab_scan_finish(vha, e->u.iosb.sp); 5567 break; 5568 case QLA_EVT_GFPNID: 5569 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5570 break; 5571 case QLA_EVT_SP_RETRY: 5572 qla_sp_retry(vha, e); 5573 break; 5574 case QLA_EVT_IIDMA: 5575 qla_do_iidma_work(vha, e->u.fcport.fcport); 5576 break; 5577 case QLA_EVT_ELS_PLOGI: 5578 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5579 e->u.fcport.fcport); 5580 break; 5581 case QLA_EVT_SA_REPLACE: 5582 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5583 break; 5584 } 5585 5586 if (rc == EAGAIN) { 5587 /* put 'work' at head of 'vha->work_list' */ 5588 spin_lock_irqsave(&vha->work_lock, flags); 5589 list_splice(&work, &vha->work_list); 5590 spin_unlock_irqrestore(&vha->work_lock, flags); 5591 break; 5592 } 5593 list_del_init(&e->list); 5594 if (e->flags & QLA_EVT_FLAG_FREE) 5595 kfree(e); 5596 5597 /* For each work completed decrement vha ref count */ 5598 QLA_VHA_MARK_NOT_BUSY(vha); 5599 } 5600 } 5601 5602 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5603 { 5604 struct qla_work_evt *e; 5605 5606 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5607 5608 if (!e) { 5609 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5610 return QLA_FUNCTION_FAILED; 5611 } 5612 5613 return qla2x00_post_work(vha, e); 5614 } 5615 5616 /* Relogins all the fcports of a vport 5617 * Context: dpc thread 5618 */ 5619 void qla2x00_relogin(struct scsi_qla_host *vha) 5620 { 5621 fc_port_t *fcport; 5622 int status, relogin_needed = 0; 5623 struct event_arg ea; 5624 5625 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5626 /* 5627 * If the port is not ONLINE then try to login 5628 * to it if we haven't run out of retries. 5629 */ 5630 if (atomic_read(&fcport->state) != FCS_ONLINE && 5631 fcport->login_retry) { 5632 if (fcport->scan_state != QLA_FCPORT_FOUND || 5633 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5634 fcport->disc_state == DSC_LOGIN_COMPLETE) 5635 continue; 5636 5637 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5638 fcport->disc_state == DSC_DELETE_PEND) { 5639 relogin_needed = 1; 5640 } else { 5641 if (vha->hw->current_topology != ISP_CFG_NL) { 5642 memset(&ea, 0, sizeof(ea)); 5643 ea.fcport = fcport; 5644 qla24xx_handle_relogin_event(vha, &ea); 5645 } else if (vha->hw->current_topology == 5646 ISP_CFG_NL && 5647 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5648 (void)qla24xx_fcport_handle_login(vha, 5649 fcport); 5650 } else if (vha->hw->current_topology == 5651 ISP_CFG_NL) { 5652 fcport->login_retry--; 5653 status = 5654 qla2x00_local_device_login(vha, 5655 fcport); 5656 if (status == QLA_SUCCESS) { 5657 fcport->old_loop_id = 5658 fcport->loop_id; 5659 ql_dbg(ql_dbg_disc, vha, 0x2003, 5660 "Port login OK: logged in ID 0x%x.\n", 5661 fcport->loop_id); 5662 qla2x00_update_fcport 5663 (vha, fcport); 5664 } else if (status == 1) { 5665 set_bit(RELOGIN_NEEDED, 5666 &vha->dpc_flags); 5667 /* retry the login again */ 5668 ql_dbg(ql_dbg_disc, vha, 0x2007, 5669 "Retrying %d login again loop_id 0x%x.\n", 5670 fcport->login_retry, 5671 fcport->loop_id); 5672 } else { 5673 fcport->login_retry = 0; 5674 } 5675 5676 if (fcport->login_retry == 0 && 5677 status != QLA_SUCCESS) 5678 qla2x00_clear_loop_id(fcport); 5679 } 5680 } 5681 } 5682 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5683 break; 5684 } 5685 5686 if (relogin_needed) 5687 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5688 5689 ql_dbg(ql_dbg_disc, vha, 0x400e, 5690 "Relogin end.\n"); 5691 } 5692 5693 /* Schedule work on any of the dpc-workqueues */ 5694 void 5695 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5696 { 5697 struct qla_hw_data *ha = base_vha->hw; 5698 5699 switch (work_code) { 5700 case MBA_IDC_AEN: /* 0x8200 */ 5701 if (ha->dpc_lp_wq) 5702 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5703 break; 5704 5705 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5706 if (!ha->flags.nic_core_reset_hdlr_active) { 5707 if (ha->dpc_hp_wq) 5708 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5709 } else 5710 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5711 "NIC Core reset is already active. Skip " 5712 "scheduling it again.\n"); 5713 break; 5714 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5715 if (ha->dpc_hp_wq) 5716 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5717 break; 5718 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5719 if (ha->dpc_hp_wq) 5720 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5721 break; 5722 default: 5723 ql_log(ql_log_warn, base_vha, 0xb05f, 5724 "Unknown work-code=0x%x.\n", work_code); 5725 } 5726 5727 return; 5728 } 5729 5730 /* Work: Perform NIC Core Unrecoverable state handling */ 5731 void 5732 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5733 { 5734 struct qla_hw_data *ha = 5735 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5736 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5737 uint32_t dev_state = 0; 5738 5739 qla83xx_idc_lock(base_vha, 0); 5740 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5741 qla83xx_reset_ownership(base_vha); 5742 if (ha->flags.nic_core_reset_owner) { 5743 ha->flags.nic_core_reset_owner = 0; 5744 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5745 QLA8XXX_DEV_FAILED); 5746 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5747 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5748 } 5749 qla83xx_idc_unlock(base_vha, 0); 5750 } 5751 5752 /* Work: Execute IDC state handler */ 5753 void 5754 qla83xx_idc_state_handler_work(struct work_struct *work) 5755 { 5756 struct qla_hw_data *ha = 5757 container_of(work, struct qla_hw_data, idc_state_handler); 5758 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5759 uint32_t dev_state = 0; 5760 5761 qla83xx_idc_lock(base_vha, 0); 5762 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5763 if (dev_state == QLA8XXX_DEV_FAILED || 5764 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5765 qla83xx_idc_state_handler(base_vha); 5766 qla83xx_idc_unlock(base_vha, 0); 5767 } 5768 5769 static int 5770 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5771 { 5772 int rval = QLA_SUCCESS; 5773 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5774 uint32_t heart_beat_counter1, heart_beat_counter2; 5775 5776 do { 5777 if (time_after(jiffies, heart_beat_wait)) { 5778 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5779 "Nic Core f/w is not alive.\n"); 5780 rval = QLA_FUNCTION_FAILED; 5781 break; 5782 } 5783 5784 qla83xx_idc_lock(base_vha, 0); 5785 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5786 &heart_beat_counter1); 5787 qla83xx_idc_unlock(base_vha, 0); 5788 msleep(100); 5789 qla83xx_idc_lock(base_vha, 0); 5790 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5791 &heart_beat_counter2); 5792 qla83xx_idc_unlock(base_vha, 0); 5793 } while (heart_beat_counter1 == heart_beat_counter2); 5794 5795 return rval; 5796 } 5797 5798 /* Work: Perform NIC Core Reset handling */ 5799 void 5800 qla83xx_nic_core_reset_work(struct work_struct *work) 5801 { 5802 struct qla_hw_data *ha = 5803 container_of(work, struct qla_hw_data, nic_core_reset); 5804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5805 uint32_t dev_state = 0; 5806 5807 if (IS_QLA2031(ha)) { 5808 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5809 ql_log(ql_log_warn, base_vha, 0xb081, 5810 "Failed to dump mctp\n"); 5811 return; 5812 } 5813 5814 if (!ha->flags.nic_core_reset_hdlr_active) { 5815 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5816 qla83xx_idc_lock(base_vha, 0); 5817 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5818 &dev_state); 5819 qla83xx_idc_unlock(base_vha, 0); 5820 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5821 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5822 "Nic Core f/w is alive.\n"); 5823 return; 5824 } 5825 } 5826 5827 ha->flags.nic_core_reset_hdlr_active = 1; 5828 if (qla83xx_nic_core_reset(base_vha)) { 5829 /* NIC Core reset failed. */ 5830 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5831 "NIC Core reset failed.\n"); 5832 } 5833 ha->flags.nic_core_reset_hdlr_active = 0; 5834 } 5835 } 5836 5837 /* Work: Handle 8200 IDC aens */ 5838 void 5839 qla83xx_service_idc_aen(struct work_struct *work) 5840 { 5841 struct qla_hw_data *ha = 5842 container_of(work, struct qla_hw_data, idc_aen); 5843 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5844 uint32_t dev_state, idc_control; 5845 5846 qla83xx_idc_lock(base_vha, 0); 5847 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5848 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5849 qla83xx_idc_unlock(base_vha, 0); 5850 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5851 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5852 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5853 "Application requested NIC Core Reset.\n"); 5854 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5855 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5856 QLA_SUCCESS) { 5857 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5858 "Other protocol driver requested NIC Core Reset.\n"); 5859 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5860 } 5861 } else if (dev_state == QLA8XXX_DEV_FAILED || 5862 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5863 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5864 } 5865 } 5866 5867 /* 5868 * Control the frequency of IDC lock retries 5869 */ 5870 #define QLA83XX_WAIT_LOGIC_MS 100 5871 5872 static int 5873 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5874 { 5875 int rval; 5876 uint32_t data; 5877 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5878 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5879 struct qla_hw_data *ha = base_vha->hw; 5880 5881 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5882 "Trying force recovery of the IDC lock.\n"); 5883 5884 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5885 if (rval) 5886 return rval; 5887 5888 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5889 return QLA_SUCCESS; 5890 } else { 5891 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5892 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5893 data); 5894 if (rval) 5895 return rval; 5896 5897 msleep(200); 5898 5899 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5900 &data); 5901 if (rval) 5902 return rval; 5903 5904 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5905 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5906 ~(idc_lck_rcvry_stage_mask)); 5907 rval = qla83xx_wr_reg(base_vha, 5908 QLA83XX_IDC_LOCK_RECOVERY, data); 5909 if (rval) 5910 return rval; 5911 5912 /* Forcefully perform IDC UnLock */ 5913 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5914 &data); 5915 if (rval) 5916 return rval; 5917 /* Clear lock-id by setting 0xff */ 5918 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5919 0xff); 5920 if (rval) 5921 return rval; 5922 /* Clear lock-recovery by setting 0x0 */ 5923 rval = qla83xx_wr_reg(base_vha, 5924 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5925 if (rval) 5926 return rval; 5927 } else 5928 return QLA_SUCCESS; 5929 } 5930 5931 return rval; 5932 } 5933 5934 static int 5935 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5936 { 5937 int rval = QLA_SUCCESS; 5938 uint32_t o_drv_lockid, n_drv_lockid; 5939 unsigned long lock_recovery_timeout; 5940 5941 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5942 retry_lockid: 5943 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5944 if (rval) 5945 goto exit; 5946 5947 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5948 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5949 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5950 return QLA_SUCCESS; 5951 else 5952 return QLA_FUNCTION_FAILED; 5953 } 5954 5955 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5956 if (rval) 5957 goto exit; 5958 5959 if (o_drv_lockid == n_drv_lockid) { 5960 msleep(QLA83XX_WAIT_LOGIC_MS); 5961 goto retry_lockid; 5962 } else 5963 return QLA_SUCCESS; 5964 5965 exit: 5966 return rval; 5967 } 5968 5969 /* 5970 * Context: task, can sleep 5971 */ 5972 void 5973 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5974 { 5975 uint32_t data; 5976 uint32_t lock_owner; 5977 struct qla_hw_data *ha = base_vha->hw; 5978 5979 might_sleep(); 5980 5981 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5982 retry_lock: 5983 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5984 == QLA_SUCCESS) { 5985 if (data) { 5986 /* Setting lock-id to our function-number */ 5987 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5988 ha->portnum); 5989 } else { 5990 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5991 &lock_owner); 5992 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5993 "Failed to acquire IDC lock, acquired by %d, " 5994 "retrying...\n", lock_owner); 5995 5996 /* Retry/Perform IDC-Lock recovery */ 5997 if (qla83xx_idc_lock_recovery(base_vha) 5998 == QLA_SUCCESS) { 5999 msleep(QLA83XX_WAIT_LOGIC_MS); 6000 goto retry_lock; 6001 } else 6002 ql_log(ql_log_warn, base_vha, 0xb075, 6003 "IDC Lock recovery FAILED.\n"); 6004 } 6005 6006 } 6007 6008 return; 6009 } 6010 6011 static bool 6012 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 6013 struct purex_entry_24xx *purex) 6014 { 6015 char fwstr[16]; 6016 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 6017 struct port_database_24xx *pdb; 6018 6019 /* Domain Controller is always logged-out. */ 6020 /* if RDP request is not from Domain Controller: */ 6021 if (sid != 0xfffc01) 6022 return false; 6023 6024 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 6025 6026 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6027 if (!pdb) { 6028 ql_dbg(ql_dbg_init, vha, 0x0181, 6029 "%s: Failed allocate pdb\n", __func__); 6030 } else if (qla24xx_get_port_database(vha, 6031 le16_to_cpu(purex->nport_handle), pdb)) { 6032 ql_dbg(ql_dbg_init, vha, 0x0181, 6033 "%s: Failed get pdb sid=%x\n", __func__, sid); 6034 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6035 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6036 ql_dbg(ql_dbg_init, vha, 0x0181, 6037 "%s: Port not logged in sid=%#x\n", __func__, sid); 6038 } else { 6039 /* RDP request is from logged in port */ 6040 kfree(pdb); 6041 return false; 6042 } 6043 kfree(pdb); 6044 6045 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6046 fwstr[strcspn(fwstr, " ")] = 0; 6047 /* if FW version allows RDP response length upto 2048 bytes: */ 6048 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6049 return false; 6050 6051 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6052 6053 /* RDP response length is to be reduced to maximum 256 bytes */ 6054 return true; 6055 } 6056 6057 /* 6058 * Function Name: qla24xx_process_purex_iocb 6059 * 6060 * Description: 6061 * Prepare a RDP response and send to Fabric switch 6062 * 6063 * PARAMETERS: 6064 * vha: SCSI qla host 6065 * purex: RDP request received by HBA 6066 */ 6067 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6068 struct purex_item *item) 6069 { 6070 struct qla_hw_data *ha = vha->hw; 6071 struct purex_entry_24xx *purex = 6072 (struct purex_entry_24xx *)&item->iocb; 6073 dma_addr_t rsp_els_dma; 6074 dma_addr_t rsp_payload_dma; 6075 dma_addr_t stat_dma; 6076 dma_addr_t sfp_dma; 6077 struct els_entry_24xx *rsp_els = NULL; 6078 struct rdp_rsp_payload *rsp_payload = NULL; 6079 struct link_statistics *stat = NULL; 6080 uint8_t *sfp = NULL; 6081 uint16_t sfp_flags = 0; 6082 uint rsp_payload_length = sizeof(*rsp_payload); 6083 int rval; 6084 6085 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6086 "%s: Enter\n", __func__); 6087 6088 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6089 "-------- ELS REQ -------\n"); 6090 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6091 purex, sizeof(*purex)); 6092 6093 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6094 rsp_payload_length = 6095 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6096 ql_dbg(ql_dbg_init, vha, 0x0181, 6097 "Reducing RSP payload length to %u bytes...\n", 6098 rsp_payload_length); 6099 } 6100 6101 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6102 &rsp_els_dma, GFP_KERNEL); 6103 if (!rsp_els) { 6104 ql_log(ql_log_warn, vha, 0x0183, 6105 "Failed allocate dma buffer ELS RSP.\n"); 6106 goto dealloc; 6107 } 6108 6109 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6110 &rsp_payload_dma, GFP_KERNEL); 6111 if (!rsp_payload) { 6112 ql_log(ql_log_warn, vha, 0x0184, 6113 "Failed allocate dma buffer ELS RSP payload.\n"); 6114 goto dealloc; 6115 } 6116 6117 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6118 &sfp_dma, GFP_KERNEL); 6119 6120 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6121 &stat_dma, GFP_KERNEL); 6122 6123 /* Prepare Response IOCB */ 6124 rsp_els->entry_type = ELS_IOCB_TYPE; 6125 rsp_els->entry_count = 1; 6126 rsp_els->sys_define = 0; 6127 rsp_els->entry_status = 0; 6128 rsp_els->handle = 0; 6129 rsp_els->nport_handle = purex->nport_handle; 6130 rsp_els->tx_dsd_count = cpu_to_le16(1); 6131 rsp_els->vp_index = purex->vp_idx; 6132 rsp_els->sof_type = EST_SOFI3; 6133 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6134 rsp_els->rx_dsd_count = 0; 6135 rsp_els->opcode = purex->els_frame_payload[0]; 6136 6137 rsp_els->d_id[0] = purex->s_id[0]; 6138 rsp_els->d_id[1] = purex->s_id[1]; 6139 rsp_els->d_id[2] = purex->s_id[2]; 6140 6141 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6142 rsp_els->rx_byte_count = 0; 6143 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6144 6145 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6146 rsp_els->tx_len = rsp_els->tx_byte_count; 6147 6148 rsp_els->rx_address = 0; 6149 rsp_els->rx_len = 0; 6150 6151 /* Prepare Response Payload */ 6152 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6153 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6154 sizeof(rsp_payload->hdr)); 6155 6156 /* Link service Request Info Descriptor */ 6157 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6158 rsp_payload->ls_req_info_desc.desc_len = 6159 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6160 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6161 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6162 6163 /* Link service Request Info Descriptor 2 */ 6164 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6165 rsp_payload->ls_req_info_desc2.desc_len = 6166 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6167 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6168 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6169 6170 6171 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6172 rsp_payload->sfp_diag_desc.desc_len = 6173 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6174 6175 if (sfp) { 6176 /* SFP Flags */ 6177 memset(sfp, 0, SFP_RTDI_LEN); 6178 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6179 if (!rval) { 6180 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6181 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6182 sfp_flags |= BIT_0; /* short wave */ 6183 else if (sfp[0] & BIT_1) 6184 sfp_flags |= BIT_1; /* long wave 1310nm */ 6185 else if (sfp[1] & BIT_4) 6186 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6187 } 6188 6189 /* SFP Type */ 6190 memset(sfp, 0, SFP_RTDI_LEN); 6191 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6192 if (!rval) { 6193 sfp_flags |= BIT_4; /* optical */ 6194 if (sfp[0] == 0x3) 6195 sfp_flags |= BIT_6; /* sfp+ */ 6196 } 6197 6198 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6199 6200 /* SFP Diagnostics */ 6201 memset(sfp, 0, SFP_RTDI_LEN); 6202 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6203 if (!rval) { 6204 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6205 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6206 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6207 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6208 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6209 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6210 } 6211 } 6212 6213 /* Port Speed Descriptor */ 6214 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6215 rsp_payload->port_speed_desc.desc_len = 6216 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6217 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6218 qla25xx_fdmi_port_speed_capability(ha)); 6219 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6220 qla25xx_fdmi_port_speed_currently(ha)); 6221 6222 /* Link Error Status Descriptor */ 6223 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6224 rsp_payload->ls_err_desc.desc_len = 6225 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6226 6227 if (stat) { 6228 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6229 if (!rval) { 6230 rsp_payload->ls_err_desc.link_fail_cnt = 6231 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6232 rsp_payload->ls_err_desc.loss_sync_cnt = 6233 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6234 rsp_payload->ls_err_desc.loss_sig_cnt = 6235 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6236 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6237 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6238 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6239 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6240 rsp_payload->ls_err_desc.inval_crc_cnt = 6241 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6242 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6243 } 6244 } 6245 6246 /* Portname Descriptor */ 6247 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6248 rsp_payload->port_name_diag_desc.desc_len = 6249 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6250 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6251 vha->node_name, 6252 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6253 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6254 vha->port_name, 6255 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6256 6257 /* F-Port Portname Descriptor */ 6258 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6259 rsp_payload->port_name_direct_desc.desc_len = 6260 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6261 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6262 vha->fabric_node_name, 6263 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6264 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6265 vha->fabric_port_name, 6266 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6267 6268 /* Bufer Credit Descriptor */ 6269 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6270 rsp_payload->buffer_credit_desc.desc_len = 6271 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6272 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6273 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6274 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6275 6276 if (ha->flags.plogi_template_valid) { 6277 uint32_t tmp = 6278 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6279 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6280 } 6281 6282 if (rsp_payload_length < sizeof(*rsp_payload)) 6283 goto send; 6284 6285 /* Optical Element Descriptor, Temperature */ 6286 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6287 rsp_payload->optical_elmt_desc[0].desc_len = 6288 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6289 /* Optical Element Descriptor, Voltage */ 6290 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6291 rsp_payload->optical_elmt_desc[1].desc_len = 6292 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6293 /* Optical Element Descriptor, Tx Bias Current */ 6294 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6295 rsp_payload->optical_elmt_desc[2].desc_len = 6296 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6297 /* Optical Element Descriptor, Tx Power */ 6298 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6299 rsp_payload->optical_elmt_desc[3].desc_len = 6300 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6301 /* Optical Element Descriptor, Rx Power */ 6302 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6303 rsp_payload->optical_elmt_desc[4].desc_len = 6304 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6305 6306 if (sfp) { 6307 memset(sfp, 0, SFP_RTDI_LEN); 6308 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6309 if (!rval) { 6310 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6311 6312 /* Optical Element Descriptor, Temperature */ 6313 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6314 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6315 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6316 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6317 rsp_payload->optical_elmt_desc[0].element_flags = 6318 cpu_to_be32(1 << 28); 6319 6320 /* Optical Element Descriptor, Voltage */ 6321 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6322 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6323 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6324 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6325 rsp_payload->optical_elmt_desc[1].element_flags = 6326 cpu_to_be32(2 << 28); 6327 6328 /* Optical Element Descriptor, Tx Bias Current */ 6329 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6330 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6331 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6332 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6333 rsp_payload->optical_elmt_desc[2].element_flags = 6334 cpu_to_be32(3 << 28); 6335 6336 /* Optical Element Descriptor, Tx Power */ 6337 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6338 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6339 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6340 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6341 rsp_payload->optical_elmt_desc[3].element_flags = 6342 cpu_to_be32(4 << 28); 6343 6344 /* Optical Element Descriptor, Rx Power */ 6345 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6346 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6347 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6348 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6349 rsp_payload->optical_elmt_desc[4].element_flags = 6350 cpu_to_be32(5 << 28); 6351 } 6352 6353 memset(sfp, 0, SFP_RTDI_LEN); 6354 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6355 if (!rval) { 6356 /* Temperature high/low alarm/warning */ 6357 rsp_payload->optical_elmt_desc[0].element_flags |= 6358 cpu_to_be32( 6359 (sfp[0] >> 7 & 1) << 3 | 6360 (sfp[0] >> 6 & 1) << 2 | 6361 (sfp[4] >> 7 & 1) << 1 | 6362 (sfp[4] >> 6 & 1) << 0); 6363 6364 /* Voltage high/low alarm/warning */ 6365 rsp_payload->optical_elmt_desc[1].element_flags |= 6366 cpu_to_be32( 6367 (sfp[0] >> 5 & 1) << 3 | 6368 (sfp[0] >> 4 & 1) << 2 | 6369 (sfp[4] >> 5 & 1) << 1 | 6370 (sfp[4] >> 4 & 1) << 0); 6371 6372 /* Tx Bias Current high/low alarm/warning */ 6373 rsp_payload->optical_elmt_desc[2].element_flags |= 6374 cpu_to_be32( 6375 (sfp[0] >> 3 & 1) << 3 | 6376 (sfp[0] >> 2 & 1) << 2 | 6377 (sfp[4] >> 3 & 1) << 1 | 6378 (sfp[4] >> 2 & 1) << 0); 6379 6380 /* Tx Power high/low alarm/warning */ 6381 rsp_payload->optical_elmt_desc[3].element_flags |= 6382 cpu_to_be32( 6383 (sfp[0] >> 1 & 1) << 3 | 6384 (sfp[0] >> 0 & 1) << 2 | 6385 (sfp[4] >> 1 & 1) << 1 | 6386 (sfp[4] >> 0 & 1) << 0); 6387 6388 /* Rx Power high/low alarm/warning */ 6389 rsp_payload->optical_elmt_desc[4].element_flags |= 6390 cpu_to_be32( 6391 (sfp[1] >> 7 & 1) << 3 | 6392 (sfp[1] >> 6 & 1) << 2 | 6393 (sfp[5] >> 7 & 1) << 1 | 6394 (sfp[5] >> 6 & 1) << 0); 6395 } 6396 } 6397 6398 /* Optical Product Data Descriptor */ 6399 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6400 rsp_payload->optical_prod_desc.desc_len = 6401 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6402 6403 if (sfp) { 6404 memset(sfp, 0, SFP_RTDI_LEN); 6405 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6406 if (!rval) { 6407 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6408 sfp + 0, 6409 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6410 memcpy(rsp_payload->optical_prod_desc.part_number, 6411 sfp + 20, 6412 sizeof(rsp_payload->optical_prod_desc.part_number)); 6413 memcpy(rsp_payload->optical_prod_desc.revision, 6414 sfp + 36, 6415 sizeof(rsp_payload->optical_prod_desc.revision)); 6416 memcpy(rsp_payload->optical_prod_desc.serial_number, 6417 sfp + 48, 6418 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6419 } 6420 6421 memset(sfp, 0, SFP_RTDI_LEN); 6422 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6423 if (!rval) { 6424 memcpy(rsp_payload->optical_prod_desc.date, 6425 sfp + 0, 6426 sizeof(rsp_payload->optical_prod_desc.date)); 6427 } 6428 } 6429 6430 send: 6431 ql_dbg(ql_dbg_init, vha, 0x0183, 6432 "Sending ELS Response to RDP Request...\n"); 6433 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6434 "-------- ELS RSP -------\n"); 6435 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6436 rsp_els, sizeof(*rsp_els)); 6437 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6438 "-------- ELS RSP PAYLOAD -------\n"); 6439 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6440 rsp_payload, rsp_payload_length); 6441 6442 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6443 6444 if (rval) { 6445 ql_log(ql_log_warn, vha, 0x0188, 6446 "%s: iocb failed to execute -> %x\n", __func__, rval); 6447 } else if (rsp_els->comp_status) { 6448 ql_log(ql_log_warn, vha, 0x0189, 6449 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6450 __func__, rsp_els->comp_status, 6451 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6452 } else { 6453 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6454 } 6455 6456 dealloc: 6457 if (stat) 6458 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6459 stat, stat_dma); 6460 if (sfp) 6461 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6462 sfp, sfp_dma); 6463 if (rsp_payload) 6464 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6465 rsp_payload, rsp_payload_dma); 6466 if (rsp_els) 6467 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6468 rsp_els, rsp_els_dma); 6469 } 6470 6471 void 6472 qla24xx_free_purex_item(struct purex_item *item) 6473 { 6474 if (item == &item->vha->default_item) 6475 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6476 else 6477 kfree(item); 6478 } 6479 6480 void qla24xx_process_purex_list(struct purex_list *list) 6481 { 6482 struct list_head head = LIST_HEAD_INIT(head); 6483 struct purex_item *item, *next; 6484 ulong flags; 6485 6486 spin_lock_irqsave(&list->lock, flags); 6487 list_splice_init(&list->head, &head); 6488 spin_unlock_irqrestore(&list->lock, flags); 6489 6490 list_for_each_entry_safe(item, next, &head, list) { 6491 list_del(&item->list); 6492 item->process_item(item->vha, item); 6493 qla24xx_free_purex_item(item); 6494 } 6495 } 6496 6497 /* 6498 * Context: task, can sleep 6499 */ 6500 void 6501 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6502 { 6503 #if 0 6504 uint16_t options = (requester_id << 15) | BIT_7; 6505 #endif 6506 uint16_t retry; 6507 uint32_t data; 6508 struct qla_hw_data *ha = base_vha->hw; 6509 6510 might_sleep(); 6511 6512 /* IDC-unlock implementation using driver-unlock/lock-id 6513 * remote registers 6514 */ 6515 retry = 0; 6516 retry_unlock: 6517 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6518 == QLA_SUCCESS) { 6519 if (data == ha->portnum) { 6520 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6521 /* Clearing lock-id by setting 0xff */ 6522 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6523 } else if (retry < 10) { 6524 /* SV: XXX: IDC unlock retrying needed here? */ 6525 6526 /* Retry for IDC-unlock */ 6527 msleep(QLA83XX_WAIT_LOGIC_MS); 6528 retry++; 6529 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6530 "Failed to release IDC lock, retrying=%d\n", retry); 6531 goto retry_unlock; 6532 } 6533 } else if (retry < 10) { 6534 /* Retry for IDC-unlock */ 6535 msleep(QLA83XX_WAIT_LOGIC_MS); 6536 retry++; 6537 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6538 "Failed to read drv-lockid, retrying=%d\n", retry); 6539 goto retry_unlock; 6540 } 6541 6542 return; 6543 6544 #if 0 6545 /* XXX: IDC-unlock implementation using access-control mbx */ 6546 retry = 0; 6547 retry_unlock2: 6548 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6549 if (retry < 10) { 6550 /* Retry for IDC-unlock */ 6551 msleep(QLA83XX_WAIT_LOGIC_MS); 6552 retry++; 6553 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6554 "Failed to release IDC lock, retrying=%d\n", retry); 6555 goto retry_unlock2; 6556 } 6557 } 6558 6559 return; 6560 #endif 6561 } 6562 6563 int 6564 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6565 { 6566 int rval = QLA_SUCCESS; 6567 struct qla_hw_data *ha = vha->hw; 6568 uint32_t drv_presence; 6569 6570 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6571 if (rval == QLA_SUCCESS) { 6572 drv_presence |= (1 << ha->portnum); 6573 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6574 drv_presence); 6575 } 6576 6577 return rval; 6578 } 6579 6580 int 6581 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6582 { 6583 int rval = QLA_SUCCESS; 6584 6585 qla83xx_idc_lock(vha, 0); 6586 rval = __qla83xx_set_drv_presence(vha); 6587 qla83xx_idc_unlock(vha, 0); 6588 6589 return rval; 6590 } 6591 6592 int 6593 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6594 { 6595 int rval = QLA_SUCCESS; 6596 struct qla_hw_data *ha = vha->hw; 6597 uint32_t drv_presence; 6598 6599 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6600 if (rval == QLA_SUCCESS) { 6601 drv_presence &= ~(1 << ha->portnum); 6602 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6603 drv_presence); 6604 } 6605 6606 return rval; 6607 } 6608 6609 int 6610 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6611 { 6612 int rval = QLA_SUCCESS; 6613 6614 qla83xx_idc_lock(vha, 0); 6615 rval = __qla83xx_clear_drv_presence(vha); 6616 qla83xx_idc_unlock(vha, 0); 6617 6618 return rval; 6619 } 6620 6621 static void 6622 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6623 { 6624 struct qla_hw_data *ha = vha->hw; 6625 uint32_t drv_ack, drv_presence; 6626 unsigned long ack_timeout; 6627 6628 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6629 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6630 while (1) { 6631 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6632 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6633 if ((drv_ack & drv_presence) == drv_presence) 6634 break; 6635 6636 if (time_after_eq(jiffies, ack_timeout)) { 6637 ql_log(ql_log_warn, vha, 0xb067, 6638 "RESET ACK TIMEOUT! drv_presence=0x%x " 6639 "drv_ack=0x%x\n", drv_presence, drv_ack); 6640 /* 6641 * The function(s) which did not ack in time are forced 6642 * to withdraw any further participation in the IDC 6643 * reset. 6644 */ 6645 if (drv_ack != drv_presence) 6646 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6647 drv_ack); 6648 break; 6649 } 6650 6651 qla83xx_idc_unlock(vha, 0); 6652 msleep(1000); 6653 qla83xx_idc_lock(vha, 0); 6654 } 6655 6656 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6657 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6658 } 6659 6660 static int 6661 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6662 { 6663 int rval = QLA_SUCCESS; 6664 uint32_t idc_control; 6665 6666 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6667 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6668 6669 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6670 __qla83xx_get_idc_control(vha, &idc_control); 6671 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6672 __qla83xx_set_idc_control(vha, 0); 6673 6674 qla83xx_idc_unlock(vha, 0); 6675 rval = qla83xx_restart_nic_firmware(vha); 6676 qla83xx_idc_lock(vha, 0); 6677 6678 if (rval != QLA_SUCCESS) { 6679 ql_log(ql_log_fatal, vha, 0xb06a, 6680 "Failed to restart NIC f/w.\n"); 6681 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6682 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6683 } else { 6684 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6685 "Success in restarting nic f/w.\n"); 6686 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6687 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6688 } 6689 6690 return rval; 6691 } 6692 6693 /* Assumes idc_lock always held on entry */ 6694 int 6695 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6696 { 6697 struct qla_hw_data *ha = base_vha->hw; 6698 int rval = QLA_SUCCESS; 6699 unsigned long dev_init_timeout; 6700 uint32_t dev_state; 6701 6702 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6703 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6704 6705 while (1) { 6706 6707 if (time_after_eq(jiffies, dev_init_timeout)) { 6708 ql_log(ql_log_warn, base_vha, 0xb06e, 6709 "Initialization TIMEOUT!\n"); 6710 /* Init timeout. Disable further NIC Core 6711 * communication. 6712 */ 6713 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6714 QLA8XXX_DEV_FAILED); 6715 ql_log(ql_log_info, base_vha, 0xb06f, 6716 "HW State: FAILED.\n"); 6717 } 6718 6719 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6720 switch (dev_state) { 6721 case QLA8XXX_DEV_READY: 6722 if (ha->flags.nic_core_reset_owner) 6723 qla83xx_idc_audit(base_vha, 6724 IDC_AUDIT_COMPLETION); 6725 ha->flags.nic_core_reset_owner = 0; 6726 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6727 "Reset_owner reset by 0x%x.\n", 6728 ha->portnum); 6729 goto exit; 6730 case QLA8XXX_DEV_COLD: 6731 if (ha->flags.nic_core_reset_owner) 6732 rval = qla83xx_device_bootstrap(base_vha); 6733 else { 6734 /* Wait for AEN to change device-state */ 6735 qla83xx_idc_unlock(base_vha, 0); 6736 msleep(1000); 6737 qla83xx_idc_lock(base_vha, 0); 6738 } 6739 break; 6740 case QLA8XXX_DEV_INITIALIZING: 6741 /* Wait for AEN to change device-state */ 6742 qla83xx_idc_unlock(base_vha, 0); 6743 msleep(1000); 6744 qla83xx_idc_lock(base_vha, 0); 6745 break; 6746 case QLA8XXX_DEV_NEED_RESET: 6747 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6748 qla83xx_need_reset_handler(base_vha); 6749 else { 6750 /* Wait for AEN to change device-state */ 6751 qla83xx_idc_unlock(base_vha, 0); 6752 msleep(1000); 6753 qla83xx_idc_lock(base_vha, 0); 6754 } 6755 /* reset timeout value after need reset handler */ 6756 dev_init_timeout = jiffies + 6757 (ha->fcoe_dev_init_timeout * HZ); 6758 break; 6759 case QLA8XXX_DEV_NEED_QUIESCENT: 6760 /* XXX: DEBUG for now */ 6761 qla83xx_idc_unlock(base_vha, 0); 6762 msleep(1000); 6763 qla83xx_idc_lock(base_vha, 0); 6764 break; 6765 case QLA8XXX_DEV_QUIESCENT: 6766 /* XXX: DEBUG for now */ 6767 if (ha->flags.quiesce_owner) 6768 goto exit; 6769 6770 qla83xx_idc_unlock(base_vha, 0); 6771 msleep(1000); 6772 qla83xx_idc_lock(base_vha, 0); 6773 dev_init_timeout = jiffies + 6774 (ha->fcoe_dev_init_timeout * HZ); 6775 break; 6776 case QLA8XXX_DEV_FAILED: 6777 if (ha->flags.nic_core_reset_owner) 6778 qla83xx_idc_audit(base_vha, 6779 IDC_AUDIT_COMPLETION); 6780 ha->flags.nic_core_reset_owner = 0; 6781 __qla83xx_clear_drv_presence(base_vha); 6782 qla83xx_idc_unlock(base_vha, 0); 6783 qla8xxx_dev_failed_handler(base_vha); 6784 rval = QLA_FUNCTION_FAILED; 6785 qla83xx_idc_lock(base_vha, 0); 6786 goto exit; 6787 case QLA8XXX_BAD_VALUE: 6788 qla83xx_idc_unlock(base_vha, 0); 6789 msleep(1000); 6790 qla83xx_idc_lock(base_vha, 0); 6791 break; 6792 default: 6793 ql_log(ql_log_warn, base_vha, 0xb071, 6794 "Unknown Device State: %x.\n", dev_state); 6795 qla83xx_idc_unlock(base_vha, 0); 6796 qla8xxx_dev_failed_handler(base_vha); 6797 rval = QLA_FUNCTION_FAILED; 6798 qla83xx_idc_lock(base_vha, 0); 6799 goto exit; 6800 } 6801 } 6802 6803 exit: 6804 return rval; 6805 } 6806 6807 void 6808 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6809 { 6810 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6811 board_disable); 6812 struct pci_dev *pdev = ha->pdev; 6813 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6814 6815 ql_log(ql_log_warn, base_vha, 0x015b, 6816 "Disabling adapter.\n"); 6817 6818 if (!atomic_read(&pdev->enable_cnt)) { 6819 ql_log(ql_log_info, base_vha, 0xfffc, 6820 "PCI device disabled, no action req for PCI error=%lx\n", 6821 base_vha->pci_flags); 6822 return; 6823 } 6824 6825 /* 6826 * if UNLOADING flag is already set, then continue unload, 6827 * where it was set first. 6828 */ 6829 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6830 return; 6831 6832 qla2x00_wait_for_sess_deletion(base_vha); 6833 6834 qla2x00_delete_all_vps(ha, base_vha); 6835 6836 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6837 6838 qla2x00_dfs_remove(base_vha); 6839 6840 qla84xx_put_chip(base_vha); 6841 6842 if (base_vha->timer_active) 6843 qla2x00_stop_timer(base_vha); 6844 6845 base_vha->flags.online = 0; 6846 6847 qla2x00_destroy_deferred_work(ha); 6848 6849 /* 6850 * Do not try to stop beacon blink as it will issue a mailbox 6851 * command. 6852 */ 6853 qla2x00_free_sysfs_attr(base_vha, false); 6854 6855 fc_remove_host(base_vha->host); 6856 6857 scsi_remove_host(base_vha->host); 6858 6859 base_vha->flags.init_done = 0; 6860 qla25xx_delete_queues(base_vha); 6861 qla2x00_free_fcports(base_vha); 6862 qla2x00_free_irqs(base_vha); 6863 qla2x00_mem_free(ha); 6864 qla82xx_md_free(base_vha); 6865 qla2x00_free_queues(ha); 6866 6867 qla2x00_unmap_iobases(ha); 6868 6869 pci_release_selected_regions(ha->pdev, ha->bars); 6870 pci_disable_device(pdev); 6871 6872 /* 6873 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6874 */ 6875 } 6876 6877 /************************************************************************** 6878 * qla2x00_do_dpc 6879 * This kernel thread is a task that is schedule by the interrupt handler 6880 * to perform the background processing for interrupts. 6881 * 6882 * Notes: 6883 * This task always run in the context of a kernel thread. It 6884 * is kick-off by the driver's detect code and starts up 6885 * up one per adapter. It immediately goes to sleep and waits for 6886 * some fibre event. When either the interrupt handler or 6887 * the timer routine detects a event it will one of the task 6888 * bits then wake us up. 6889 **************************************************************************/ 6890 static int 6891 qla2x00_do_dpc(void *data) 6892 { 6893 scsi_qla_host_t *base_vha; 6894 struct qla_hw_data *ha; 6895 uint32_t online; 6896 struct qla_qpair *qpair; 6897 6898 ha = (struct qla_hw_data *)data; 6899 base_vha = pci_get_drvdata(ha->pdev); 6900 6901 set_user_nice(current, MIN_NICE); 6902 6903 set_current_state(TASK_INTERRUPTIBLE); 6904 while (1) { 6905 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6906 "DPC handler sleeping.\n"); 6907 6908 schedule(); 6909 6910 if (kthread_should_stop()) 6911 break; 6912 6913 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6914 qla_pci_set_eeh_busy(base_vha); 6915 6916 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6917 goto end_loop; 6918 6919 if (ha->flags.eeh_busy) { 6920 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6921 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6922 goto end_loop; 6923 } 6924 6925 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6926 /* don't do any work. Wait to be terminated by kthread_stop */ 6927 goto end_loop; 6928 6929 ha->dpc_active = 1; 6930 6931 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6932 "DPC handler waking up, dpc_flags=0x%lx.\n", 6933 base_vha->dpc_flags); 6934 6935 if (IS_P3P_TYPE(ha)) { 6936 if (IS_QLA8044(ha)) { 6937 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6938 &base_vha->dpc_flags)) { 6939 qla8044_idc_lock(ha); 6940 qla8044_wr_direct(base_vha, 6941 QLA8044_CRB_DEV_STATE_INDEX, 6942 QLA8XXX_DEV_FAILED); 6943 qla8044_idc_unlock(ha); 6944 ql_log(ql_log_info, base_vha, 0x4004, 6945 "HW State: FAILED.\n"); 6946 qla8044_device_state_handler(base_vha); 6947 continue; 6948 } 6949 6950 } else { 6951 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6952 &base_vha->dpc_flags)) { 6953 qla82xx_idc_lock(ha); 6954 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6955 QLA8XXX_DEV_FAILED); 6956 qla82xx_idc_unlock(ha); 6957 ql_log(ql_log_info, base_vha, 0x0151, 6958 "HW State: FAILED.\n"); 6959 qla82xx_device_state_handler(base_vha); 6960 continue; 6961 } 6962 } 6963 6964 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6965 &base_vha->dpc_flags)) { 6966 6967 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6968 "FCoE context reset scheduled.\n"); 6969 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6970 &base_vha->dpc_flags))) { 6971 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6972 /* FCoE-ctx reset failed. 6973 * Escalate to chip-reset 6974 */ 6975 set_bit(ISP_ABORT_NEEDED, 6976 &base_vha->dpc_flags); 6977 } 6978 clear_bit(ABORT_ISP_ACTIVE, 6979 &base_vha->dpc_flags); 6980 } 6981 6982 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6983 "FCoE context reset end.\n"); 6984 } 6985 } else if (IS_QLAFX00(ha)) { 6986 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6987 &base_vha->dpc_flags)) { 6988 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6989 "Firmware Reset Recovery\n"); 6990 if (qlafx00_reset_initialize(base_vha)) { 6991 /* Failed. Abort isp later. */ 6992 if (!test_bit(UNLOADING, 6993 &base_vha->dpc_flags)) { 6994 set_bit(ISP_UNRECOVERABLE, 6995 &base_vha->dpc_flags); 6996 ql_dbg(ql_dbg_dpc, base_vha, 6997 0x4021, 6998 "Reset Recovery Failed\n"); 6999 } 7000 } 7001 } 7002 7003 if (test_and_clear_bit(FX00_TARGET_SCAN, 7004 &base_vha->dpc_flags)) { 7005 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 7006 "ISPFx00 Target Scan scheduled\n"); 7007 if (qlafx00_rescan_isp(base_vha)) { 7008 if (!test_bit(UNLOADING, 7009 &base_vha->dpc_flags)) 7010 set_bit(ISP_UNRECOVERABLE, 7011 &base_vha->dpc_flags); 7012 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 7013 "ISPFx00 Target Scan Failed\n"); 7014 } 7015 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 7016 "ISPFx00 Target Scan End\n"); 7017 } 7018 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 7019 &base_vha->dpc_flags)) { 7020 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 7021 "ISPFx00 Host Info resend scheduled\n"); 7022 qlafx00_fx_disc(base_vha, 7023 &base_vha->hw->mr.fcport, 7024 FXDISC_REG_HOST_INFO); 7025 } 7026 } 7027 7028 if (test_and_clear_bit(DETECT_SFP_CHANGE, 7029 &base_vha->dpc_flags)) { 7030 /* Semantic: 7031 * - NO-OP -- await next ISP-ABORT. Preferred method 7032 * to minimize disruptions that will occur 7033 * when a forced chip-reset occurs. 7034 * - Force -- ISP-ABORT scheduled. 7035 */ 7036 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7037 } 7038 7039 if (test_and_clear_bit 7040 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7041 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7042 bool do_reset = true; 7043 7044 switch (base_vha->qlini_mode) { 7045 case QLA2XXX_INI_MODE_ENABLED: 7046 break; 7047 case QLA2XXX_INI_MODE_DISABLED: 7048 if (!qla_tgt_mode_enabled(base_vha) && 7049 !ha->flags.fw_started) 7050 do_reset = false; 7051 break; 7052 case QLA2XXX_INI_MODE_DUAL: 7053 if (!qla_dual_mode_enabled(base_vha) && 7054 !ha->flags.fw_started) 7055 do_reset = false; 7056 break; 7057 default: 7058 break; 7059 } 7060 7061 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7062 &base_vha->dpc_flags))) { 7063 base_vha->flags.online = 1; 7064 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7065 "ISP abort scheduled.\n"); 7066 if (ha->isp_ops->abort_isp(base_vha)) { 7067 /* failed. retry later */ 7068 set_bit(ISP_ABORT_NEEDED, 7069 &base_vha->dpc_flags); 7070 } 7071 clear_bit(ABORT_ISP_ACTIVE, 7072 &base_vha->dpc_flags); 7073 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7074 "ISP abort end.\n"); 7075 } 7076 } 7077 7078 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7079 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7080 qla24xx_process_purex_list 7081 (&base_vha->purex_list); 7082 clear_bit(PROCESS_PUREX_IOCB, 7083 &base_vha->dpc_flags); 7084 } 7085 } 7086 7087 if (IS_QLAFX00(ha)) 7088 goto loop_resync_check; 7089 7090 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7091 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7092 "Quiescence mode scheduled.\n"); 7093 if (IS_P3P_TYPE(ha)) { 7094 if (IS_QLA82XX(ha)) 7095 qla82xx_device_state_handler(base_vha); 7096 if (IS_QLA8044(ha)) 7097 qla8044_device_state_handler(base_vha); 7098 clear_bit(ISP_QUIESCE_NEEDED, 7099 &base_vha->dpc_flags); 7100 if (!ha->flags.quiesce_owner) { 7101 qla2x00_perform_loop_resync(base_vha); 7102 if (IS_QLA82XX(ha)) { 7103 qla82xx_idc_lock(ha); 7104 qla82xx_clear_qsnt_ready( 7105 base_vha); 7106 qla82xx_idc_unlock(ha); 7107 } else if (IS_QLA8044(ha)) { 7108 qla8044_idc_lock(ha); 7109 qla8044_clear_qsnt_ready( 7110 base_vha); 7111 qla8044_idc_unlock(ha); 7112 } 7113 } 7114 } else { 7115 clear_bit(ISP_QUIESCE_NEEDED, 7116 &base_vha->dpc_flags); 7117 qla2x00_quiesce_io(base_vha); 7118 } 7119 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7120 "Quiescence mode end.\n"); 7121 } 7122 7123 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7124 &base_vha->dpc_flags) && 7125 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7126 7127 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7128 "Reset marker scheduled.\n"); 7129 qla2x00_rst_aen(base_vha); 7130 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7131 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7132 "Reset marker end.\n"); 7133 } 7134 7135 /* Retry each device up to login retry count */ 7136 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7137 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7138 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7139 7140 if (!base_vha->relogin_jif || 7141 time_after_eq(jiffies, base_vha->relogin_jif)) { 7142 base_vha->relogin_jif = jiffies + HZ; 7143 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7144 7145 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7146 "Relogin scheduled.\n"); 7147 qla24xx_post_relogin_work(base_vha); 7148 } 7149 } 7150 loop_resync_check: 7151 if (!qla2x00_reset_active(base_vha) && 7152 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7153 &base_vha->dpc_flags)) { 7154 /* 7155 * Allow abort_isp to complete before moving on to scanning. 7156 */ 7157 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7158 "Loop resync scheduled.\n"); 7159 7160 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7161 &base_vha->dpc_flags))) { 7162 7163 qla2x00_loop_resync(base_vha); 7164 7165 clear_bit(LOOP_RESYNC_ACTIVE, 7166 &base_vha->dpc_flags); 7167 } 7168 7169 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7170 "Loop resync end.\n"); 7171 } 7172 7173 if (IS_QLAFX00(ha)) 7174 goto intr_on_check; 7175 7176 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7177 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7178 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7179 qla2xxx_flash_npiv_conf(base_vha); 7180 } 7181 7182 intr_on_check: 7183 if (!ha->interrupts_on) 7184 ha->isp_ops->enable_intrs(ha); 7185 7186 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7187 &base_vha->dpc_flags)) { 7188 if (ha->beacon_blink_led == 1) 7189 ha->isp_ops->beacon_blink(base_vha); 7190 } 7191 7192 /* qpair online check */ 7193 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7194 &base_vha->dpc_flags)) { 7195 if (ha->flags.eeh_busy || 7196 ha->flags.pci_channel_io_perm_failure) 7197 online = 0; 7198 else 7199 online = 1; 7200 7201 mutex_lock(&ha->mq_lock); 7202 list_for_each_entry(qpair, &base_vha->qp_list, 7203 qp_list_elem) 7204 qpair->online = online; 7205 mutex_unlock(&ha->mq_lock); 7206 } 7207 7208 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7209 &base_vha->dpc_flags)) { 7210 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7211 7212 if (threshold > ha->orig_fw_xcb_count) 7213 threshold = ha->orig_fw_xcb_count; 7214 7215 ql_log(ql_log_info, base_vha, 0xffffff, 7216 "SET ZIO Activity exchange threshold to %d.\n", 7217 threshold); 7218 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7219 ql_log(ql_log_info, base_vha, 0xffffff, 7220 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7221 threshold); 7222 } 7223 } 7224 7225 if (!IS_QLAFX00(ha)) 7226 qla2x00_do_dpc_all_vps(base_vha); 7227 7228 if (test_and_clear_bit(N2N_LINK_RESET, 7229 &base_vha->dpc_flags)) { 7230 qla2x00_lip_reset(base_vha); 7231 } 7232 7233 ha->dpc_active = 0; 7234 end_loop: 7235 set_current_state(TASK_INTERRUPTIBLE); 7236 } /* End of while(1) */ 7237 __set_current_state(TASK_RUNNING); 7238 7239 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7240 "DPC handler exiting.\n"); 7241 7242 /* 7243 * Make sure that nobody tries to wake us up again. 7244 */ 7245 ha->dpc_active = 0; 7246 7247 return 0; 7248 } 7249 7250 void 7251 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7252 { 7253 struct qla_hw_data *ha = vha->hw; 7254 struct task_struct *t = ha->dpc_thread; 7255 7256 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7257 wake_up_process(t); 7258 } 7259 7260 /* 7261 * qla2x00_rst_aen 7262 * Processes asynchronous reset. 7263 * 7264 * Input: 7265 * ha = adapter block pointer. 7266 */ 7267 static void 7268 qla2x00_rst_aen(scsi_qla_host_t *vha) 7269 { 7270 if (vha->flags.online && !vha->flags.reset_active && 7271 !atomic_read(&vha->loop_down_timer) && 7272 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7273 do { 7274 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7275 7276 /* 7277 * Issue marker command only when we are going to start 7278 * the I/O. 7279 */ 7280 vha->marker_needed = 1; 7281 } while (!atomic_read(&vha->loop_down_timer) && 7282 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7283 } 7284 } 7285 7286 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7287 { 7288 struct qla_hw_data *ha = vha->hw; 7289 u32 cmpl_cnt; 7290 u16 i; 7291 bool do_heartbeat = false; 7292 7293 /* 7294 * Allow do_heartbeat only if we don’t have any active interrupts, 7295 * but there are still IOs outstanding with firmware. 7296 */ 7297 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7298 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7299 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7300 do_heartbeat = true; 7301 goto skip; 7302 } 7303 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7304 7305 for (i = 0; i < ha->max_qpairs; i++) { 7306 if (ha->queue_pair_map[i]) { 7307 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7308 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7309 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7310 do_heartbeat = true; 7311 break; 7312 } 7313 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7314 } 7315 } 7316 7317 skip: 7318 return do_heartbeat; 7319 } 7320 7321 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7322 { 7323 struct qla_hw_data *ha = vha->hw; 7324 7325 if (vha->vp_idx) 7326 return; 7327 7328 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7329 return; 7330 7331 /* 7332 * dpc thread cannot run if heartbeat is running at the same time. 7333 * We also do not want to starve heartbeat task. Therefore, do 7334 * heartbeat task at least once every 5 seconds. 7335 */ 7336 if (dpc_started && 7337 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7338 return; 7339 7340 if (qla_do_heartbeat(vha)) { 7341 ha->last_heartbeat_run_jiffies = jiffies; 7342 queue_work(ha->wq, &ha->heartbeat_work); 7343 } 7344 } 7345 7346 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7347 { 7348 struct qla_hw_data *ha = vha->hw; 7349 7350 if (!ha->flags.eeh_busy) 7351 return; 7352 if (ha->pci_error_state) 7353 /* system is trying to recover */ 7354 return; 7355 7356 /* 7357 * Current system is not handling PCIE error. At this point, this is 7358 * best effort to wind down the adapter. 7359 */ 7360 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7361 !ha->flags.eeh_flush) { 7362 ql_log(ql_log_info, vha, 0x9009, 7363 "PCI Error detected, attempting to reset hardware.\n"); 7364 7365 ha->isp_ops->reset_chip(vha); 7366 ha->isp_ops->disable_intrs(ha); 7367 7368 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7369 ha->eeh_jif = jiffies; 7370 7371 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7372 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7373 pci_clear_master(ha->pdev); 7374 7375 /* flush all command */ 7376 qla2x00_abort_isp_cleanup(vha); 7377 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7378 7379 ql_log(ql_log_info, vha, 0x900a, 7380 "PCI Error handling complete, all IOs aborted.\n"); 7381 } 7382 } 7383 7384 /************************************************************************** 7385 * qla2x00_timer 7386 * 7387 * Description: 7388 * One second timer 7389 * 7390 * Context: Interrupt 7391 ***************************************************************************/ 7392 void 7393 qla2x00_timer(struct timer_list *t) 7394 { 7395 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7396 unsigned long cpu_flags = 0; 7397 int start_dpc = 0; 7398 int index; 7399 srb_t *sp; 7400 uint16_t w; 7401 struct qla_hw_data *ha = vha->hw; 7402 struct req_que *req; 7403 unsigned long flags; 7404 fc_port_t *fcport = NULL; 7405 7406 if (ha->flags.eeh_busy) { 7407 qla_wind_down_chip(vha); 7408 7409 ql_dbg(ql_dbg_timer, vha, 0x6000, 7410 "EEH = %d, restarting timer.\n", 7411 ha->flags.eeh_busy); 7412 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7413 return; 7414 } 7415 7416 /* 7417 * Hardware read to raise pending EEH errors during mailbox waits. If 7418 * the read returns -1 then disable the board. 7419 */ 7420 if (!pci_channel_offline(ha->pdev)) { 7421 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7422 qla2x00_check_reg16_for_disconnect(vha, w); 7423 } 7424 7425 /* Make sure qla82xx_watchdog is run only for physical port */ 7426 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7427 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7428 start_dpc++; 7429 if (IS_QLA82XX(ha)) 7430 qla82xx_watchdog(vha); 7431 else if (IS_QLA8044(ha)) 7432 qla8044_watchdog(vha); 7433 } 7434 7435 if (!vha->vp_idx && IS_QLAFX00(ha)) 7436 qlafx00_timer_routine(vha); 7437 7438 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7439 vha->link_down_time++; 7440 7441 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7442 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7443 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7444 fcport->tgt_link_down_time++; 7445 } 7446 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7447 7448 /* Loop down handler. */ 7449 if (atomic_read(&vha->loop_down_timer) > 0 && 7450 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7451 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7452 && vha->flags.online) { 7453 7454 if (atomic_read(&vha->loop_down_timer) == 7455 vha->loop_down_abort_time) { 7456 7457 ql_log(ql_log_info, vha, 0x6008, 7458 "Loop down - aborting the queues before time expires.\n"); 7459 7460 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7461 atomic_set(&vha->loop_state, LOOP_DEAD); 7462 7463 /* 7464 * Schedule an ISP abort to return any FCP2-device 7465 * commands. 7466 */ 7467 /* NPIV - scan physical port only */ 7468 if (!vha->vp_idx) { 7469 spin_lock_irqsave(&ha->hardware_lock, 7470 cpu_flags); 7471 req = ha->req_q_map[0]; 7472 for (index = 1; 7473 index < req->num_outstanding_cmds; 7474 index++) { 7475 fc_port_t *sfcp; 7476 7477 sp = req->outstanding_cmds[index]; 7478 if (!sp) 7479 continue; 7480 if (sp->cmd_type != TYPE_SRB) 7481 continue; 7482 if (sp->type != SRB_SCSI_CMD) 7483 continue; 7484 sfcp = sp->fcport; 7485 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7486 continue; 7487 7488 if (IS_QLA82XX(ha)) 7489 set_bit(FCOE_CTX_RESET_NEEDED, 7490 &vha->dpc_flags); 7491 else 7492 set_bit(ISP_ABORT_NEEDED, 7493 &vha->dpc_flags); 7494 break; 7495 } 7496 spin_unlock_irqrestore(&ha->hardware_lock, 7497 cpu_flags); 7498 } 7499 start_dpc++; 7500 } 7501 7502 /* if the loop has been down for 4 minutes, reinit adapter */ 7503 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7504 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7505 ql_log(ql_log_warn, vha, 0x6009, 7506 "Loop down - aborting ISP.\n"); 7507 7508 if (IS_QLA82XX(ha)) 7509 set_bit(FCOE_CTX_RESET_NEEDED, 7510 &vha->dpc_flags); 7511 else 7512 set_bit(ISP_ABORT_NEEDED, 7513 &vha->dpc_flags); 7514 } 7515 } 7516 ql_dbg(ql_dbg_timer, vha, 0x600a, 7517 "Loop down - seconds remaining %d.\n", 7518 atomic_read(&vha->loop_down_timer)); 7519 } 7520 /* Check if beacon LED needs to be blinked for physical host only */ 7521 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7522 /* There is no beacon_blink function for ISP82xx */ 7523 if (!IS_P3P_TYPE(ha)) { 7524 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7525 start_dpc++; 7526 } 7527 } 7528 7529 /* check if edif running */ 7530 if (vha->hw->flags.edif_enabled) 7531 qla_edif_timer(vha); 7532 7533 /* Process any deferred work. */ 7534 if (!list_empty(&vha->work_list)) { 7535 unsigned long flags; 7536 bool q = false; 7537 7538 spin_lock_irqsave(&vha->work_lock, flags); 7539 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7540 q = true; 7541 spin_unlock_irqrestore(&vha->work_lock, flags); 7542 if (q) 7543 queue_work(vha->hw->wq, &vha->iocb_work); 7544 } 7545 7546 /* 7547 * FC-NVME 7548 * see if the active AEN count has changed from what was last reported. 7549 */ 7550 index = atomic_read(&ha->nvme_active_aen_cnt); 7551 if (!vha->vp_idx && 7552 (index != ha->nvme_last_rptd_aen) && 7553 ha->zio_mode == QLA_ZIO_MODE_6 && 7554 !ha->flags.host_shutting_down) { 7555 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7556 ql_log(ql_log_info, vha, 0x3002, 7557 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7558 ha->nvme_last_rptd_aen); 7559 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7560 start_dpc++; 7561 } 7562 7563 if (!vha->vp_idx && 7564 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7565 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7566 ql_log(ql_log_info, vha, 0x3002, 7567 "Sched: Set ZIO exchange threshold to %d.\n", 7568 ha->last_zio_threshold); 7569 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7570 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7571 start_dpc++; 7572 } 7573 qla_adjust_buf(vha); 7574 7575 /* borrowing w to signify dpc will run */ 7576 w = 0; 7577 /* Schedule the DPC routine if needed */ 7578 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7579 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7580 start_dpc || 7581 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7582 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7583 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7584 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7585 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7586 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7587 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7588 ql_dbg(ql_dbg_timer, vha, 0x600b, 7589 "isp_abort_needed=%d loop_resync_needed=%d " 7590 "start_dpc=%d reset_marker_needed=%d", 7591 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7592 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7593 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7594 ql_dbg(ql_dbg_timer, vha, 0x600c, 7595 "beacon_blink_needed=%d isp_unrecoverable=%d " 7596 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7597 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7598 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7599 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7600 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7601 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7602 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7603 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7604 qla2xxx_wake_dpc(vha); 7605 w = 1; 7606 } 7607 7608 qla_heart_beat(vha, w); 7609 7610 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7611 } 7612 7613 /* Firmware interface routines. */ 7614 7615 #define FW_ISP21XX 0 7616 #define FW_ISP22XX 1 7617 #define FW_ISP2300 2 7618 #define FW_ISP2322 3 7619 #define FW_ISP24XX 4 7620 #define FW_ISP25XX 5 7621 #define FW_ISP81XX 6 7622 #define FW_ISP82XX 7 7623 #define FW_ISP2031 8 7624 #define FW_ISP8031 9 7625 #define FW_ISP27XX 10 7626 #define FW_ISP28XX 11 7627 7628 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7629 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7630 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7631 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7632 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7633 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7634 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7635 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7636 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7637 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7638 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7639 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7640 7641 7642 static DEFINE_MUTEX(qla_fw_lock); 7643 7644 static struct fw_blob qla_fw_blobs[] = { 7645 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7646 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7647 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7648 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7649 { .name = FW_FILE_ISP24XX, }, 7650 { .name = FW_FILE_ISP25XX, }, 7651 { .name = FW_FILE_ISP81XX, }, 7652 { .name = FW_FILE_ISP82XX, }, 7653 { .name = FW_FILE_ISP2031, }, 7654 { .name = FW_FILE_ISP8031, }, 7655 { .name = FW_FILE_ISP27XX, }, 7656 { .name = FW_FILE_ISP28XX, }, 7657 { .name = NULL, }, 7658 }; 7659 7660 struct fw_blob * 7661 qla2x00_request_firmware(scsi_qla_host_t *vha) 7662 { 7663 struct qla_hw_data *ha = vha->hw; 7664 struct fw_blob *blob; 7665 7666 if (IS_QLA2100(ha)) { 7667 blob = &qla_fw_blobs[FW_ISP21XX]; 7668 } else if (IS_QLA2200(ha)) { 7669 blob = &qla_fw_blobs[FW_ISP22XX]; 7670 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7671 blob = &qla_fw_blobs[FW_ISP2300]; 7672 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7673 blob = &qla_fw_blobs[FW_ISP2322]; 7674 } else if (IS_QLA24XX_TYPE(ha)) { 7675 blob = &qla_fw_blobs[FW_ISP24XX]; 7676 } else if (IS_QLA25XX(ha)) { 7677 blob = &qla_fw_blobs[FW_ISP25XX]; 7678 } else if (IS_QLA81XX(ha)) { 7679 blob = &qla_fw_blobs[FW_ISP81XX]; 7680 } else if (IS_QLA82XX(ha)) { 7681 blob = &qla_fw_blobs[FW_ISP82XX]; 7682 } else if (IS_QLA2031(ha)) { 7683 blob = &qla_fw_blobs[FW_ISP2031]; 7684 } else if (IS_QLA8031(ha)) { 7685 blob = &qla_fw_blobs[FW_ISP8031]; 7686 } else if (IS_QLA27XX(ha)) { 7687 blob = &qla_fw_blobs[FW_ISP27XX]; 7688 } else if (IS_QLA28XX(ha)) { 7689 blob = &qla_fw_blobs[FW_ISP28XX]; 7690 } else { 7691 return NULL; 7692 } 7693 7694 if (!blob->name) 7695 return NULL; 7696 7697 mutex_lock(&qla_fw_lock); 7698 if (blob->fw) 7699 goto out; 7700 7701 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7702 ql_log(ql_log_warn, vha, 0x0063, 7703 "Failed to load firmware image (%s).\n", blob->name); 7704 blob->fw = NULL; 7705 blob = NULL; 7706 } 7707 7708 out: 7709 mutex_unlock(&qla_fw_lock); 7710 return blob; 7711 } 7712 7713 static void 7714 qla2x00_release_firmware(void) 7715 { 7716 struct fw_blob *blob; 7717 7718 mutex_lock(&qla_fw_lock); 7719 for (blob = qla_fw_blobs; blob->name; blob++) 7720 release_firmware(blob->fw); 7721 mutex_unlock(&qla_fw_lock); 7722 } 7723 7724 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7725 { 7726 struct qla_hw_data *ha = vha->hw; 7727 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7728 struct qla_qpair *qpair = NULL; 7729 struct scsi_qla_host *vp, *tvp; 7730 fc_port_t *fcport; 7731 int i; 7732 unsigned long flags; 7733 7734 ql_dbg(ql_dbg_aer, vha, 0x9000, 7735 "%s\n", __func__); 7736 ha->chip_reset++; 7737 7738 ha->base_qpair->chip_reset = ha->chip_reset; 7739 for (i = 0; i < ha->max_qpairs; i++) { 7740 if (ha->queue_pair_map[i]) 7741 ha->queue_pair_map[i]->chip_reset = 7742 ha->base_qpair->chip_reset; 7743 } 7744 7745 /* 7746 * purge mailbox might take a while. Slot Reset/chip reset 7747 * will take care of the purge 7748 */ 7749 7750 mutex_lock(&ha->mq_lock); 7751 ha->base_qpair->online = 0; 7752 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7753 qpair->online = 0; 7754 wmb(); 7755 mutex_unlock(&ha->mq_lock); 7756 7757 qla2x00_mark_all_devices_lost(vha); 7758 7759 spin_lock_irqsave(&ha->vport_slock, flags); 7760 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7761 atomic_inc(&vp->vref_count); 7762 spin_unlock_irqrestore(&ha->vport_slock, flags); 7763 qla2x00_mark_all_devices_lost(vp); 7764 spin_lock_irqsave(&ha->vport_slock, flags); 7765 atomic_dec(&vp->vref_count); 7766 } 7767 spin_unlock_irqrestore(&ha->vport_slock, flags); 7768 7769 /* Clear all async request states across all VPs. */ 7770 list_for_each_entry(fcport, &vha->vp_fcports, list) 7771 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7772 7773 spin_lock_irqsave(&ha->vport_slock, flags); 7774 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7775 atomic_inc(&vp->vref_count); 7776 spin_unlock_irqrestore(&ha->vport_slock, flags); 7777 list_for_each_entry(fcport, &vp->vp_fcports, list) 7778 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7779 spin_lock_irqsave(&ha->vport_slock, flags); 7780 atomic_dec(&vp->vref_count); 7781 } 7782 spin_unlock_irqrestore(&ha->vport_slock, flags); 7783 } 7784 7785 7786 static pci_ers_result_t 7787 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7788 { 7789 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7790 struct qla_hw_data *ha = vha->hw; 7791 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7792 7793 ql_log(ql_log_warn, vha, 0x9000, 7794 "PCI error detected, state %x.\n", state); 7795 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7796 7797 if (!atomic_read(&pdev->enable_cnt)) { 7798 ql_log(ql_log_info, vha, 0xffff, 7799 "PCI device is disabled,state %x\n", state); 7800 ret = PCI_ERS_RESULT_NEED_RESET; 7801 goto out; 7802 } 7803 7804 switch (state) { 7805 case pci_channel_io_normal: 7806 qla_pci_set_eeh_busy(vha); 7807 if (ql2xmqsupport || ql2xnvmeenable) { 7808 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7809 qla2xxx_wake_dpc(vha); 7810 } 7811 ret = PCI_ERS_RESULT_CAN_RECOVER; 7812 break; 7813 case pci_channel_io_frozen: 7814 qla_pci_set_eeh_busy(vha); 7815 ret = PCI_ERS_RESULT_NEED_RESET; 7816 break; 7817 case pci_channel_io_perm_failure: 7818 ha->flags.pci_channel_io_perm_failure = 1; 7819 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7820 if (ql2xmqsupport || ql2xnvmeenable) { 7821 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7822 qla2xxx_wake_dpc(vha); 7823 } 7824 ret = PCI_ERS_RESULT_DISCONNECT; 7825 } 7826 out: 7827 ql_dbg(ql_dbg_aer, vha, 0x600d, 7828 "PCI error detected returning [%x].\n", ret); 7829 return ret; 7830 } 7831 7832 static pci_ers_result_t 7833 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7834 { 7835 int risc_paused = 0; 7836 uint32_t stat; 7837 unsigned long flags; 7838 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7839 struct qla_hw_data *ha = base_vha->hw; 7840 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7841 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7842 7843 ql_log(ql_log_warn, base_vha, 0x9000, 7844 "mmio enabled\n"); 7845 7846 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7847 7848 if (IS_QLA82XX(ha)) 7849 return PCI_ERS_RESULT_RECOVERED; 7850 7851 if (qla2x00_isp_reg_stat(ha)) { 7852 ql_log(ql_log_info, base_vha, 0x803f, 7853 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7854 goto out; 7855 } 7856 7857 spin_lock_irqsave(&ha->hardware_lock, flags); 7858 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7859 stat = rd_reg_word(®->hccr); 7860 if (stat & HCCR_RISC_PAUSE) 7861 risc_paused = 1; 7862 } else if (IS_QLA23XX(ha)) { 7863 stat = rd_reg_dword(®->u.isp2300.host_status); 7864 if (stat & HSR_RISC_PAUSED) 7865 risc_paused = 1; 7866 } else if (IS_FWI2_CAPABLE(ha)) { 7867 stat = rd_reg_dword(®24->host_status); 7868 if (stat & HSRX_RISC_PAUSED) 7869 risc_paused = 1; 7870 } 7871 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7872 7873 if (risc_paused) { 7874 ql_log(ql_log_info, base_vha, 0x9003, 7875 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7876 qla2xxx_dump_fw(base_vha); 7877 } 7878 out: 7879 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7880 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7881 "mmio enabled returning.\n"); 7882 return PCI_ERS_RESULT_NEED_RESET; 7883 } 7884 7885 static pci_ers_result_t 7886 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7887 { 7888 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7889 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7890 struct qla_hw_data *ha = base_vha->hw; 7891 int rc; 7892 struct qla_qpair *qpair = NULL; 7893 7894 ql_log(ql_log_warn, base_vha, 0x9004, 7895 "Slot Reset.\n"); 7896 7897 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7898 /* Workaround: qla2xxx driver which access hardware earlier 7899 * needs error state to be pci_channel_io_online. 7900 * Otherwise mailbox command timesout. 7901 */ 7902 pdev->error_state = pci_channel_io_normal; 7903 7904 pci_restore_state(pdev); 7905 7906 /* pci_restore_state() clears the saved_state flag of the device 7907 * save restored state which resets saved_state flag 7908 */ 7909 pci_save_state(pdev); 7910 7911 if (ha->mem_only) 7912 rc = pci_enable_device_mem(pdev); 7913 else 7914 rc = pci_enable_device(pdev); 7915 7916 if (rc) { 7917 ql_log(ql_log_warn, base_vha, 0x9005, 7918 "Can't re-enable PCI device after reset.\n"); 7919 goto exit_slot_reset; 7920 } 7921 7922 7923 if (ha->isp_ops->pci_config(base_vha)) 7924 goto exit_slot_reset; 7925 7926 mutex_lock(&ha->mq_lock); 7927 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7928 qpair->online = 1; 7929 mutex_unlock(&ha->mq_lock); 7930 7931 ha->flags.eeh_busy = 0; 7932 base_vha->flags.online = 1; 7933 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7934 ha->isp_ops->abort_isp(base_vha); 7935 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7936 7937 if (qla2x00_isp_reg_stat(ha)) { 7938 ha->flags.eeh_busy = 1; 7939 qla_pci_error_cleanup(base_vha); 7940 ql_log(ql_log_warn, base_vha, 0x9005, 7941 "Device unable to recover from PCI error.\n"); 7942 } else { 7943 ret = PCI_ERS_RESULT_RECOVERED; 7944 } 7945 7946 exit_slot_reset: 7947 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7948 "Slot Reset returning %x.\n", ret); 7949 7950 return ret; 7951 } 7952 7953 static void 7954 qla2xxx_pci_resume(struct pci_dev *pdev) 7955 { 7956 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7957 struct qla_hw_data *ha = base_vha->hw; 7958 int ret; 7959 7960 ql_log(ql_log_warn, base_vha, 0x900f, 7961 "Pci Resume.\n"); 7962 7963 7964 ret = qla2x00_wait_for_hba_online(base_vha); 7965 if (ret != QLA_SUCCESS) { 7966 ql_log(ql_log_fatal, base_vha, 0x9002, 7967 "The device failed to resume I/O from slot/link_reset.\n"); 7968 } 7969 ha->pci_error_state = QLA_PCI_RESUME; 7970 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7971 "Pci Resume returning.\n"); 7972 } 7973 7974 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7975 { 7976 struct qla_hw_data *ha = vha->hw; 7977 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7978 bool do_cleanup = false; 7979 unsigned long flags; 7980 7981 if (ha->flags.eeh_busy) 7982 return; 7983 7984 spin_lock_irqsave(&base_vha->work_lock, flags); 7985 if (!ha->flags.eeh_busy) { 7986 ha->eeh_jif = jiffies; 7987 ha->flags.eeh_flush = 0; 7988 7989 ha->flags.eeh_busy = 1; 7990 do_cleanup = true; 7991 } 7992 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7993 7994 if (do_cleanup) 7995 qla_pci_error_cleanup(base_vha); 7996 } 7997 7998 /* 7999 * this routine will schedule a task to pause IO from interrupt context 8000 * if caller sees a PCIE error event (register read = 0xf's) 8001 */ 8002 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 8003 { 8004 struct qla_hw_data *ha = vha->hw; 8005 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8006 8007 if (ha->flags.eeh_busy) 8008 return; 8009 8010 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 8011 qla2xxx_wake_dpc(base_vha); 8012 } 8013 8014 static void 8015 qla_pci_reset_prepare(struct pci_dev *pdev) 8016 { 8017 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8018 struct qla_hw_data *ha = base_vha->hw; 8019 struct qla_qpair *qpair; 8020 8021 ql_log(ql_log_warn, base_vha, 0xffff, 8022 "%s.\n", __func__); 8023 8024 /* 8025 * PCI FLR/function reset is about to reset the 8026 * slot. Stop the chip to stop all DMA access. 8027 * It is assumed that pci_reset_done will be called 8028 * after FLR to resume Chip operation. 8029 */ 8030 ha->flags.eeh_busy = 1; 8031 mutex_lock(&ha->mq_lock); 8032 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8033 qpair->online = 0; 8034 mutex_unlock(&ha->mq_lock); 8035 8036 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8037 qla2x00_abort_isp_cleanup(base_vha); 8038 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8039 } 8040 8041 static void 8042 qla_pci_reset_done(struct pci_dev *pdev) 8043 { 8044 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8045 struct qla_hw_data *ha = base_vha->hw; 8046 struct qla_qpair *qpair; 8047 8048 ql_log(ql_log_warn, base_vha, 0xffff, 8049 "%s.\n", __func__); 8050 8051 /* 8052 * FLR just completed by PCI layer. Resume adapter 8053 */ 8054 ha->flags.eeh_busy = 0; 8055 mutex_lock(&ha->mq_lock); 8056 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8057 qpair->online = 1; 8058 mutex_unlock(&ha->mq_lock); 8059 8060 base_vha->flags.online = 1; 8061 ha->isp_ops->abort_isp(base_vha); 8062 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8063 } 8064 8065 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8066 { 8067 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8068 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8069 8070 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8071 blk_mq_map_queues(qmap); 8072 else 8073 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev, 8074 vha->irq_offset); 8075 } 8076 8077 struct scsi_host_template qla2xxx_driver_template = { 8078 .module = THIS_MODULE, 8079 .name = QLA2XXX_DRIVER_NAME, 8080 .queuecommand = qla2xxx_queuecommand, 8081 8082 .eh_timed_out = fc_eh_timed_out, 8083 .eh_abort_handler = qla2xxx_eh_abort, 8084 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8085 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8086 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8087 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8088 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8089 8090 .slave_configure = qla2xxx_slave_configure, 8091 8092 .slave_alloc = qla2xxx_slave_alloc, 8093 .slave_destroy = qla2xxx_slave_destroy, 8094 .scan_finished = qla2xxx_scan_finished, 8095 .scan_start = qla2xxx_scan_start, 8096 .change_queue_depth = scsi_change_queue_depth, 8097 .map_queues = qla2xxx_map_queues, 8098 .this_id = -1, 8099 .cmd_per_lun = 3, 8100 .sg_tablesize = SG_ALL, 8101 8102 .max_sectors = 0xFFFF, 8103 .shost_groups = qla2x00_host_groups, 8104 8105 .supported_mode = MODE_INITIATOR, 8106 .track_queue_depth = 1, 8107 .cmd_size = sizeof(srb_t), 8108 }; 8109 8110 static const struct pci_error_handlers qla2xxx_err_handler = { 8111 .error_detected = qla2xxx_pci_error_detected, 8112 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8113 .slot_reset = qla2xxx_pci_slot_reset, 8114 .resume = qla2xxx_pci_resume, 8115 .reset_prepare = qla_pci_reset_prepare, 8116 .reset_done = qla_pci_reset_done, 8117 }; 8118 8119 static struct pci_device_id qla2xxx_pci_tbl[] = { 8120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8124 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8130 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8144 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8145 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8147 { 0 }, 8148 }; 8149 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8150 8151 static struct pci_driver qla2xxx_pci_driver = { 8152 .name = QLA2XXX_DRIVER_NAME, 8153 .id_table = qla2xxx_pci_tbl, 8154 .probe = qla2x00_probe_one, 8155 .remove = qla2x00_remove_one, 8156 .shutdown = qla2x00_shutdown, 8157 .err_handler = &qla2xxx_err_handler, 8158 }; 8159 8160 static const struct file_operations apidev_fops = { 8161 .owner = THIS_MODULE, 8162 .llseek = noop_llseek, 8163 }; 8164 8165 /** 8166 * qla2x00_module_init - Module initialization. 8167 **/ 8168 static int __init 8169 qla2x00_module_init(void) 8170 { 8171 int ret = 0; 8172 8173 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8174 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8175 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8176 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8177 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8178 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8179 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8180 BUILD_BUG_ON(sizeof(request_t) != 64); 8181 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8182 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8183 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8184 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8185 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8186 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8187 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8188 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8189 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8190 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8191 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8192 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8193 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8194 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8195 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8196 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8197 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8198 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8199 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8200 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8201 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8202 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8203 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8204 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8205 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8206 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8207 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8208 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8209 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8210 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8211 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8212 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8213 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8214 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8215 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8216 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8217 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8218 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8219 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8220 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8221 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8222 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8223 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8224 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8225 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8226 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8227 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8228 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8229 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8230 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8231 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8232 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8233 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8234 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8235 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8236 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8237 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8238 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8239 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8240 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8241 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8242 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8243 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8244 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8245 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8246 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8247 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8248 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8249 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8250 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8251 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8252 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8253 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8254 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8255 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8256 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8257 8258 qla_trace_init(); 8259 8260 /* Allocate cache for SRBs. */ 8261 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8262 SLAB_HWCACHE_ALIGN, NULL); 8263 if (srb_cachep == NULL) { 8264 ql_log(ql_log_fatal, NULL, 0x0001, 8265 "Unable to allocate SRB cache...Failing load!.\n"); 8266 return -ENOMEM; 8267 } 8268 8269 /* Initialize target kmem_cache and mem_pools */ 8270 ret = qlt_init(); 8271 if (ret < 0) { 8272 goto destroy_cache; 8273 } else if (ret > 0) { 8274 /* 8275 * If initiator mode is explictly disabled by qlt_init(), 8276 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8277 * performing scsi_scan_target() during LOOP UP event. 8278 */ 8279 qla2xxx_transport_functions.disable_target_scan = 1; 8280 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8281 } 8282 8283 /* Derive version string. */ 8284 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8285 if (ql2xextended_error_logging) 8286 strcat(qla2x00_version_str, "-debug"); 8287 if (ql2xextended_error_logging == 1) 8288 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8289 8290 qla2xxx_transport_template = 8291 fc_attach_transport(&qla2xxx_transport_functions); 8292 if (!qla2xxx_transport_template) { 8293 ql_log(ql_log_fatal, NULL, 0x0002, 8294 "fc_attach_transport failed...Failing load!.\n"); 8295 ret = -ENODEV; 8296 goto qlt_exit; 8297 } 8298 8299 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8300 if (apidev_major < 0) { 8301 ql_log(ql_log_fatal, NULL, 0x0003, 8302 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8303 } 8304 8305 qla2xxx_transport_vport_template = 8306 fc_attach_transport(&qla2xxx_transport_vport_functions); 8307 if (!qla2xxx_transport_vport_template) { 8308 ql_log(ql_log_fatal, NULL, 0x0004, 8309 "fc_attach_transport vport failed...Failing load!.\n"); 8310 ret = -ENODEV; 8311 goto unreg_chrdev; 8312 } 8313 ql_log(ql_log_info, NULL, 0x0005, 8314 "QLogic Fibre Channel HBA Driver: %s.\n", 8315 qla2x00_version_str); 8316 ret = pci_register_driver(&qla2xxx_pci_driver); 8317 if (ret) { 8318 ql_log(ql_log_fatal, NULL, 0x0006, 8319 "pci_register_driver failed...ret=%d Failing load!.\n", 8320 ret); 8321 goto release_vport_transport; 8322 } 8323 return ret; 8324 8325 release_vport_transport: 8326 fc_release_transport(qla2xxx_transport_vport_template); 8327 8328 unreg_chrdev: 8329 if (apidev_major >= 0) 8330 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8331 fc_release_transport(qla2xxx_transport_template); 8332 8333 qlt_exit: 8334 qlt_exit(); 8335 8336 destroy_cache: 8337 kmem_cache_destroy(srb_cachep); 8338 8339 qla_trace_uninit(); 8340 return ret; 8341 } 8342 8343 /** 8344 * qla2x00_module_exit - Module cleanup. 8345 **/ 8346 static void __exit 8347 qla2x00_module_exit(void) 8348 { 8349 pci_unregister_driver(&qla2xxx_pci_driver); 8350 qla2x00_release_firmware(); 8351 kmem_cache_destroy(ctx_cachep); 8352 fc_release_transport(qla2xxx_transport_vport_template); 8353 if (apidev_major >= 0) 8354 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8355 fc_release_transport(qla2xxx_transport_template); 8356 qlt_exit(); 8357 kmem_cache_destroy(srb_cachep); 8358 qla_trace_uninit(); 8359 } 8360 8361 module_init(qla2x00_module_init); 8362 module_exit(qla2x00_module_exit); 8363 8364 MODULE_AUTHOR("QLogic Corporation"); 8365 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8366 MODULE_LICENSE("GPL"); 8367 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8368 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8369 MODULE_FIRMWARE(FW_FILE_ISP2300); 8370 MODULE_FIRMWARE(FW_FILE_ISP2322); 8371 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8372 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8373