1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 static void qla82xx_crb_addr_transform_setup(void) 46 { 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103 } 104 105 struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260 }; 261 262 /* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265 unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330 }; 331 332 /* Device states */ 333 char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342 }; 343 344 char *qdev_state(uint32_t dev_state) 345 { 346 return q_dev_state[dev_state]; 347 } 348 349 /* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356 { 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368 if (win_read != ha->crb_win) { 369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 "%s: Written crbwin (0x%x) " 371 "!= Read crbwin (0x%x), off=0x%lx.\n", 372 __func__, ha->crb_win, win_read, *off); 373 } 374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375 } 376 377 static inline unsigned long 378 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379 { 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381 /* See if we are currently pointing to the region we want to use next */ 382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383 /* No need to change window. PCIX and PCIEregs are in both 384 * regs are in both windows. 385 */ 386 return off; 387 } 388 389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390 /* We are in first CRB window */ 391 if (ha->curr_window != 0) 392 WARN_ON(1); 393 return off; 394 } 395 396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397 /* We are in second CRB window */ 398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399 400 if (ha->curr_window != 1) 401 return off; 402 403 /* We are in the QM or direct access 404 * register region - do nothing 405 */ 406 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407 (off < QLA82XX_PCI_CAMQM_MAX)) 408 return off; 409 } 410 /* strange address given */ 411 ql_dbg(ql_dbg_p3p, vha, 0xb001, 412 "%s: Warning: unm_nic_pci_set_crbwindow " 413 "called with an unknown address(%llx).\n", 414 QLA2XXX_DRIVER_NAME, off); 415 return off; 416 } 417 418 static int 419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 420 { 421 struct crb_128M_2M_sub_block_map *m; 422 423 if (*off >= QLA82XX_CRB_MAX) 424 return -1; 425 426 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 427 *off = (*off - QLA82XX_PCI_CAMQM) + 428 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 429 return 0; 430 } 431 432 if (*off < QLA82XX_PCI_CRBSPACE) 433 return -1; 434 435 *off -= QLA82XX_PCI_CRBSPACE; 436 437 /* Try direct map */ 438 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 439 440 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 441 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 442 return 0; 443 } 444 /* Not in direct map, use crb window */ 445 return 1; 446 } 447 448 #define CRB_WIN_LOCK_TIMEOUT 100000000 449 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 450 { 451 int done = 0, timeout = 0; 452 453 while (!done) { 454 /* acquire semaphore3 from PCI HW block */ 455 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 456 if (done == 1) 457 break; 458 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 459 return -1; 460 timeout++; 461 } 462 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 463 return 0; 464 } 465 466 int 467 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468 { 469 unsigned long flags = 0; 470 int rv; 471 472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473 474 BUG_ON(rv == -1); 475 476 if (rv == 1) { 477 write_lock_irqsave(&ha->hw_lock, flags); 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, &off); 480 } 481 482 writel(data, (void __iomem *)off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 } 488 return 0; 489 } 490 491 int 492 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493 { 494 unsigned long flags = 0; 495 int rv; 496 u32 data; 497 498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499 500 BUG_ON(rv == -1); 501 502 if (rv == 1) { 503 write_lock_irqsave(&ha->hw_lock, flags); 504 qla82xx_crb_win_lock(ha); 505 qla82xx_pci_set_crbwindow_2M(ha, &off); 506 } 507 data = RD_REG_DWORD((void __iomem *)off); 508 509 if (rv == 1) { 510 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511 write_unlock_irqrestore(&ha->hw_lock, flags); 512 } 513 return data; 514 } 515 516 #define IDC_LOCK_TIMEOUT 100000000 517 int qla82xx_idc_lock(struct qla_hw_data *ha) 518 { 519 int i; 520 int done = 0, timeout = 0; 521 522 while (!done) { 523 /* acquire semaphore5 from PCI HW block */ 524 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525 if (done == 1) 526 break; 527 if (timeout >= IDC_LOCK_TIMEOUT) 528 return -1; 529 530 timeout++; 531 532 /* Yield CPU */ 533 if (!in_interrupt()) 534 schedule(); 535 else { 536 for (i = 0; i < 20; i++) 537 cpu_relax(); 538 } 539 } 540 541 return 0; 542 } 543 544 void qla82xx_idc_unlock(struct qla_hw_data *ha) 545 { 546 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547 } 548 549 /* PCI Windowing for DDR regions. */ 550 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551 (((addr) <= (high)) && ((addr) >= (low))) 552 /* 553 * check memory access boundary. 554 * used by test agent. support ddr access only for now 555 */ 556 static unsigned long 557 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558 unsigned long long addr, int size) 559 { 560 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561 QLA82XX_ADDR_DDR_NET_MAX) || 562 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563 QLA82XX_ADDR_DDR_NET_MAX) || 564 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565 return 0; 566 else 567 return 1; 568 } 569 570 int qla82xx_pci_set_window_warning_count; 571 572 static unsigned long 573 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574 { 575 int window; 576 u32 win_read; 577 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578 579 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580 QLA82XX_ADDR_DDR_NET_MAX)) { 581 /* DDR network side */ 582 window = MN_WIN(addr); 583 ha->ddr_mn_window = window; 584 qla82xx_wr_32(ha, 585 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586 win_read = qla82xx_rd_32(ha, 587 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588 if ((win_read << 17) != window) { 589 ql_dbg(ql_dbg_p3p, vha, 0xb003, 590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591 __func__, window, win_read); 592 } 593 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595 QLA82XX_ADDR_OCM0_MAX)) { 596 unsigned int temp1; 597 if ((addr & 0x00ff800) == 0xff800) { 598 ql_log(ql_log_warn, vha, 0xb004, 599 "%s: QM access not handled.\n", __func__); 600 addr = -1UL; 601 } 602 window = OCM_WIN(addr); 603 ha->ddr_mn_window = window; 604 qla82xx_wr_32(ha, 605 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606 win_read = qla82xx_rd_32(ha, 607 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608 temp1 = ((window & 0x1FF) << 7) | 609 ((window & 0x0FFFE0000) >> 17); 610 if (win_read != temp1) { 611 ql_log(ql_log_warn, vha, 0xb005, 612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613 __func__, temp1, win_read); 614 } 615 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616 617 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619 /* QDR network side */ 620 window = MS_WIN(addr); 621 ha->qdr_sn_window = window; 622 qla82xx_wr_32(ha, 623 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624 win_read = qla82xx_rd_32(ha, 625 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626 if (win_read != window) { 627 ql_log(ql_log_warn, vha, 0xb006, 628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629 __func__, window, win_read); 630 } 631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632 } else { 633 /* 634 * peg gdb frequently accesses memory that doesn't exist, 635 * this limits the chit chat so debugging isn't slowed down. 636 */ 637 if ((qla82xx_pci_set_window_warning_count++ < 8) || 638 (qla82xx_pci_set_window_warning_count%64 == 0)) { 639 ql_log(ql_log_warn, vha, 0xb007, 640 "%s: Warning:%s Unknown address range!.\n", 641 __func__, QLA2XXX_DRIVER_NAME); 642 } 643 addr = -1UL; 644 } 645 return addr; 646 } 647 648 /* check if address is in the same windows as the previous access */ 649 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650 unsigned long long addr) 651 { 652 int window; 653 unsigned long long qdr_max; 654 655 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656 657 /* DDR network side */ 658 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659 QLA82XX_ADDR_DDR_NET_MAX)) 660 BUG(); 661 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662 QLA82XX_ADDR_OCM0_MAX)) 663 return 1; 664 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665 QLA82XX_ADDR_OCM1_MAX)) 666 return 1; 667 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668 /* QDR network side */ 669 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670 if (ha->qdr_sn_window == window) 671 return 1; 672 } 673 return 0; 674 } 675 676 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677 u64 off, void *data, int size) 678 { 679 unsigned long flags; 680 void *addr = NULL; 681 int ret = 0; 682 u64 start; 683 uint8_t *mem_ptr = NULL; 684 unsigned long mem_base; 685 unsigned long mem_page; 686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687 688 write_lock_irqsave(&ha->hw_lock, flags); 689 690 /* 691 * If attempting to access unknown address or straddle hw windows, 692 * do not access. 693 */ 694 start = qla82xx_pci_set_window(ha, off); 695 if ((start == -1UL) || 696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697 write_unlock_irqrestore(&ha->hw_lock, flags); 698 ql_log(ql_log_fatal, vha, 0xb008, 699 "%s out of bound pci memory " 700 "access, offset is 0x%llx.\n", 701 QLA2XXX_DRIVER_NAME, off); 702 return -1; 703 } 704 705 write_unlock_irqrestore(&ha->hw_lock, flags); 706 mem_base = pci_resource_start(ha->pdev, 0); 707 mem_page = start & PAGE_MASK; 708 /* Map two pages whenever user tries to access addresses in two 709 * consecutive pages. 710 */ 711 if (mem_page != ((start + size - 1) & PAGE_MASK)) 712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713 else 714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715 if (mem_ptr == 0UL) { 716 *(u8 *)data = 0; 717 return -1; 718 } 719 addr = mem_ptr; 720 addr += start & (PAGE_SIZE - 1); 721 write_lock_irqsave(&ha->hw_lock, flags); 722 723 switch (size) { 724 case 1: 725 *(u8 *)data = readb(addr); 726 break; 727 case 2: 728 *(u16 *)data = readw(addr); 729 break; 730 case 4: 731 *(u32 *)data = readl(addr); 732 break; 733 case 8: 734 *(u64 *)data = readq(addr); 735 break; 736 default: 737 ret = -1; 738 break; 739 } 740 write_unlock_irqrestore(&ha->hw_lock, flags); 741 742 if (mem_ptr) 743 iounmap(mem_ptr); 744 return ret; 745 } 746 747 static int 748 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749 u64 off, void *data, int size) 750 { 751 unsigned long flags; 752 void *addr = NULL; 753 int ret = 0; 754 u64 start; 755 uint8_t *mem_ptr = NULL; 756 unsigned long mem_base; 757 unsigned long mem_page; 758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759 760 write_lock_irqsave(&ha->hw_lock, flags); 761 762 /* 763 * If attempting to access unknown address or straddle hw windows, 764 * do not access. 765 */ 766 start = qla82xx_pci_set_window(ha, off); 767 if ((start == -1UL) || 768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769 write_unlock_irqrestore(&ha->hw_lock, flags); 770 ql_log(ql_log_fatal, vha, 0xb009, 771 "%s out of bount memory " 772 "access, offset is 0x%llx.\n", 773 QLA2XXX_DRIVER_NAME, off); 774 return -1; 775 } 776 777 write_unlock_irqrestore(&ha->hw_lock, flags); 778 mem_base = pci_resource_start(ha->pdev, 0); 779 mem_page = start & PAGE_MASK; 780 /* Map two pages whenever user tries to access addresses in two 781 * consecutive pages. 782 */ 783 if (mem_page != ((start + size - 1) & PAGE_MASK)) 784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785 else 786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787 if (mem_ptr == 0UL) 788 return -1; 789 790 addr = mem_ptr; 791 addr += start & (PAGE_SIZE - 1); 792 write_lock_irqsave(&ha->hw_lock, flags); 793 794 switch (size) { 795 case 1: 796 writeb(*(u8 *)data, addr); 797 break; 798 case 2: 799 writew(*(u16 *)data, addr); 800 break; 801 case 4: 802 writel(*(u32 *)data, addr); 803 break; 804 case 8: 805 writeq(*(u64 *)data, addr); 806 break; 807 default: 808 ret = -1; 809 break; 810 } 811 write_unlock_irqrestore(&ha->hw_lock, flags); 812 if (mem_ptr) 813 iounmap(mem_ptr); 814 return ret; 815 } 816 817 #define MTU_FUDGE_FACTOR 100 818 static unsigned long 819 qla82xx_decode_crb_addr(unsigned long addr) 820 { 821 int i; 822 unsigned long base_addr, offset, pci_base; 823 824 if (!qla82xx_crb_table_initialized) 825 qla82xx_crb_addr_transform_setup(); 826 827 pci_base = ADDR_ERROR; 828 base_addr = addr & 0xfff00000; 829 offset = addr & 0x000fffff; 830 831 for (i = 0; i < MAX_CRB_XFORM; i++) { 832 if (crb_addr_xform[i] == base_addr) { 833 pci_base = i << 20; 834 break; 835 } 836 } 837 if (pci_base == ADDR_ERROR) 838 return pci_base; 839 return pci_base + offset; 840 } 841 842 static long rom_max_timeout = 100; 843 static long qla82xx_rom_lock_timeout = 100; 844 845 static int 846 qla82xx_rom_lock(struct qla_hw_data *ha) 847 { 848 int done = 0, timeout = 0; 849 850 while (!done) { 851 /* acquire semaphore2 from PCI HW block */ 852 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853 if (done == 1) 854 break; 855 if (timeout >= qla82xx_rom_lock_timeout) 856 return -1; 857 timeout++; 858 } 859 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860 return 0; 861 } 862 863 static void 864 qla82xx_rom_unlock(struct qla_hw_data *ha) 865 { 866 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867 } 868 869 static int 870 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871 { 872 long timeout = 0; 873 long done = 0 ; 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875 876 while (done == 0) { 877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 4; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 882 "%s: Timeout reached waiting for rom busy.\n", 883 QLA2XXX_DRIVER_NAME); 884 return -1; 885 } 886 } 887 return 0; 888 } 889 890 static int 891 qla82xx_wait_rom_done(struct qla_hw_data *ha) 892 { 893 long timeout = 0; 894 long done = 0 ; 895 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896 897 while (done == 0) { 898 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899 done &= 2; 900 timeout++; 901 if (timeout >= rom_max_timeout) { 902 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 903 "%s: Timeout reached waiting for rom done.\n", 904 QLA2XXX_DRIVER_NAME); 905 return -1; 906 } 907 } 908 return 0; 909 } 910 911 static int 912 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913 { 914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 915 916 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 917 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 918 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 919 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 920 qla82xx_wait_rom_busy(ha); 921 if (qla82xx_wait_rom_done(ha)) { 922 ql_log(ql_log_fatal, vha, 0x00ba, 923 "Error waiting for rom done.\n"); 924 return -1; 925 } 926 /* Reset abyte_cnt and dummy_byte_cnt */ 927 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 928 udelay(10); 929 cond_resched(); 930 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 931 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 932 return 0; 933 } 934 935 static int 936 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937 { 938 int ret, loops = 0; 939 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 940 941 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 942 udelay(100); 943 schedule(); 944 loops++; 945 } 946 if (loops >= 50000) { 947 ql_log(ql_log_fatal, vha, 0x00b9, 948 "Failed to aquire SEM2 lock.\n"); 949 return -1; 950 } 951 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 952 qla82xx_rom_unlock(ha); 953 return ret; 954 } 955 956 static int 957 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 958 { 959 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 960 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 961 qla82xx_wait_rom_busy(ha); 962 if (qla82xx_wait_rom_done(ha)) { 963 ql_log(ql_log_warn, vha, 0xb00c, 964 "Error waiting for rom done.\n"); 965 return -1; 966 } 967 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 968 return 0; 969 } 970 971 static int 972 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 973 { 974 long timeout = 0; 975 uint32_t done = 1 ; 976 uint32_t val; 977 int ret = 0; 978 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979 980 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 981 while ((done != 0) && (ret == 0)) { 982 ret = qla82xx_read_status_reg(ha, &val); 983 done = val & 1; 984 timeout++; 985 udelay(10); 986 cond_resched(); 987 if (timeout >= 50000) { 988 ql_log(ql_log_warn, vha, 0xb00d, 989 "Timeout reached waiting for write finish.\n"); 990 return -1; 991 } 992 } 993 return ret; 994 } 995 996 static int 997 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 998 { 999 uint32_t val; 1000 qla82xx_wait_rom_busy(ha); 1001 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1002 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1003 qla82xx_wait_rom_busy(ha); 1004 if (qla82xx_wait_rom_done(ha)) 1005 return -1; 1006 if (qla82xx_read_status_reg(ha, &val) != 0) 1007 return -1; 1008 if ((val & 2) != 2) 1009 return -1; 1010 return 0; 1011 } 1012 1013 static int 1014 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1015 { 1016 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1017 if (qla82xx_flash_set_write_enable(ha)) 1018 return -1; 1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1021 if (qla82xx_wait_rom_done(ha)) { 1022 ql_log(ql_log_warn, vha, 0xb00e, 1023 "Error waiting for rom done.\n"); 1024 return -1; 1025 } 1026 return qla82xx_flash_wait_write_finish(ha); 1027 } 1028 1029 static int 1030 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1031 { 1032 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1033 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1034 if (qla82xx_wait_rom_done(ha)) { 1035 ql_log(ql_log_warn, vha, 0xb00f, 1036 "Error waiting for rom done.\n"); 1037 return -1; 1038 } 1039 return 0; 1040 } 1041 1042 static int 1043 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1044 { 1045 int loops = 0; 1046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1047 1048 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1049 udelay(100); 1050 cond_resched(); 1051 loops++; 1052 } 1053 if (loops >= 50000) { 1054 ql_log(ql_log_warn, vha, 0xb010, 1055 "ROM lock failed.\n"); 1056 return -1; 1057 } 1058 return 0; 1059 } 1060 1061 static int 1062 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063 uint32_t data) 1064 { 1065 int ret = 0; 1066 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067 1068 ret = ql82xx_rom_lock_d(ha); 1069 if (ret < 0) { 1070 ql_log(ql_log_warn, vha, 0xb011, 1071 "ROM lock failed.\n"); 1072 return ret; 1073 } 1074 1075 if (qla82xx_flash_set_write_enable(ha)) 1076 goto done_write; 1077 1078 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082 qla82xx_wait_rom_busy(ha); 1083 if (qla82xx_wait_rom_done(ha)) { 1084 ql_log(ql_log_warn, vha, 0xb012, 1085 "Error waiting for rom done.\n"); 1086 ret = -1; 1087 goto done_write; 1088 } 1089 1090 ret = qla82xx_flash_wait_write_finish(ha); 1091 1092 done_write: 1093 qla82xx_rom_unlock(ha); 1094 return ret; 1095 } 1096 1097 /* This routine does CRB initialize sequence 1098 * to put the ISP into operational state 1099 */ 1100 static int 1101 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102 { 1103 int addr, val; 1104 int i ; 1105 struct crb_addr_pair *buf; 1106 unsigned long off; 1107 unsigned offset, n; 1108 struct qla_hw_data *ha = vha->hw; 1109 1110 struct crb_addr_pair { 1111 long addr; 1112 long data; 1113 }; 1114 1115 /* Halt all the indiviual PEGs and other blocks of the ISP */ 1116 qla82xx_rom_lock(ha); 1117 1118 /* disable all I2Q */ 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1120 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1121 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1122 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1123 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1124 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1125 1126 /* disable all niu interrupts */ 1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128 /* disable xge rx/tx */ 1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130 /* disable xg1 rx/tx */ 1131 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1132 /* disable sideband mac */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1134 /* disable ap0 mac */ 1135 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1136 /* disable ap1 mac */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138 1139 /* halt sre */ 1140 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142 1143 /* halt epg */ 1144 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145 1146 /* halt timers */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153 1154 /* halt pegs */ 1155 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1160 msleep(20); 1161 1162 /* big hammer */ 1163 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164 /* don't reset CAM block on reset */ 1165 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166 else 1167 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168 1169 /* reset ms */ 1170 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1171 val |= (1 << 1); 1172 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1173 msleep(20); 1174 1175 /* unreset ms */ 1176 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1177 val &= ~(1 << 1); 1178 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1179 msleep(20); 1180 1181 qla82xx_rom_unlock(ha); 1182 1183 /* Read the signature value from the flash. 1184 * Offset 0: Contain signature (0xcafecafe) 1185 * Offset 4: Offset and number of addr/value pairs 1186 * that present in CRB initialize sequence 1187 */ 1188 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1189 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1190 ql_log(ql_log_fatal, vha, 0x006e, 1191 "Error Reading crb_init area: n: %08x.\n", n); 1192 return -1; 1193 } 1194 1195 /* Offset in flash = lower 16 bits 1196 * Number of enteries = upper 16 bits 1197 */ 1198 offset = n & 0xffffU; 1199 n = (n >> 16) & 0xffffU; 1200 1201 /* number of addr/value pair should not exceed 1024 enteries */ 1202 if (n >= 1024) { 1203 ql_log(ql_log_fatal, vha, 0x0071, 1204 "Card flash not initialized:n=0x%x.\n", n); 1205 return -1; 1206 } 1207 1208 ql_log(ql_log_info, vha, 0x0072, 1209 "%d CRB init values found in ROM.\n", n); 1210 1211 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1212 if (buf == NULL) { 1213 ql_log(ql_log_fatal, vha, 0x010c, 1214 "Unable to allocate memory.\n"); 1215 return -1; 1216 } 1217 1218 for (i = 0; i < n; i++) { 1219 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1220 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1221 kfree(buf); 1222 return -1; 1223 } 1224 1225 buf[i].addr = addr; 1226 buf[i].data = val; 1227 } 1228 1229 for (i = 0; i < n; i++) { 1230 /* Translate internal CRB initialization 1231 * address to PCI bus address 1232 */ 1233 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1234 QLA82XX_PCI_CRBSPACE; 1235 /* Not all CRB addr/value pair to be written, 1236 * some of them are skipped 1237 */ 1238 1239 /* skipping cold reboot MAGIC */ 1240 if (off == QLA82XX_CAM_RAM(0x1fc)) 1241 continue; 1242 1243 /* do not reset PCI */ 1244 if (off == (ROMUSB_GLB + 0xbc)) 1245 continue; 1246 1247 /* skip core clock, so that firmware can increase the clock */ 1248 if (off == (ROMUSB_GLB + 0xc8)) 1249 continue; 1250 1251 /* skip the function enable register */ 1252 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1253 continue; 1254 1255 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1256 continue; 1257 1258 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1259 continue; 1260 1261 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1262 continue; 1263 1264 if (off == ADDR_ERROR) { 1265 ql_log(ql_log_fatal, vha, 0x0116, 1266 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1267 continue; 1268 } 1269 1270 qla82xx_wr_32(ha, off, buf[i].data); 1271 1272 /* ISP requires much bigger delay to settle down, 1273 * else crb_window returns 0xffffffff 1274 */ 1275 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1276 msleep(1000); 1277 1278 /* ISP requires millisec delay between 1279 * successive CRB register updation 1280 */ 1281 msleep(1); 1282 } 1283 1284 kfree(buf); 1285 1286 /* Resetting the data and instruction cache */ 1287 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1288 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1290 1291 /* Clear all protocol processing engines */ 1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1300 return 0; 1301 } 1302 1303 static int 1304 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1305 u64 off, void *data, int size) 1306 { 1307 int i, j, ret = 0, loop, sz[2], off0; 1308 int scale, shift_amount, startword; 1309 uint32_t temp; 1310 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1311 1312 /* 1313 * If not MN, go check for MS or invalid. 1314 */ 1315 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1316 mem_crb = QLA82XX_CRB_QDR_NET; 1317 else { 1318 mem_crb = QLA82XX_CRB_DDR_NET; 1319 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1320 return qla82xx_pci_mem_write_direct(ha, 1321 off, data, size); 1322 } 1323 1324 off0 = off & 0x7; 1325 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1326 sz[1] = size - sz[0]; 1327 1328 off8 = off & 0xfffffff0; 1329 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1330 shift_amount = 4; 1331 scale = 2; 1332 startword = (off & 0xf)/8; 1333 1334 for (i = 0; i < loop; i++) { 1335 if (qla82xx_pci_mem_read_2M(ha, off8 + 1336 (i << shift_amount), &word[i * scale], 8)) 1337 return -1; 1338 } 1339 1340 switch (size) { 1341 case 1: 1342 tmpw = *((uint8_t *)data); 1343 break; 1344 case 2: 1345 tmpw = *((uint16_t *)data); 1346 break; 1347 case 4: 1348 tmpw = *((uint32_t *)data); 1349 break; 1350 case 8: 1351 default: 1352 tmpw = *((uint64_t *)data); 1353 break; 1354 } 1355 1356 if (sz[0] == 8) { 1357 word[startword] = tmpw; 1358 } else { 1359 word[startword] &= 1360 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1361 word[startword] |= tmpw << (off0 * 8); 1362 } 1363 if (sz[1] != 0) { 1364 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1365 word[startword+1] |= tmpw >> (sz[0] * 8); 1366 } 1367 1368 for (i = 0; i < loop; i++) { 1369 temp = off8 + (i << shift_amount); 1370 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1371 temp = 0; 1372 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1373 temp = word[i * scale] & 0xffffffff; 1374 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1375 temp = (word[i * scale] >> 32) & 0xffffffff; 1376 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1377 temp = word[i*scale + 1] & 0xffffffff; 1378 qla82xx_wr_32(ha, mem_crb + 1379 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1380 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1381 qla82xx_wr_32(ha, mem_crb + 1382 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1383 1384 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1385 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1386 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1387 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1388 1389 for (j = 0; j < MAX_CTL_CHECK; j++) { 1390 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1391 if ((temp & MIU_TA_CTL_BUSY) == 0) 1392 break; 1393 } 1394 1395 if (j >= MAX_CTL_CHECK) { 1396 if (printk_ratelimit()) 1397 dev_err(&ha->pdev->dev, 1398 "failed to write through agent.\n"); 1399 ret = -1; 1400 break; 1401 } 1402 } 1403 1404 return ret; 1405 } 1406 1407 static int 1408 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1409 { 1410 int i; 1411 long size = 0; 1412 long flashaddr = ha->flt_region_bootload << 2; 1413 long memaddr = BOOTLD_START; 1414 u64 data; 1415 u32 high, low; 1416 size = (IMAGE_START - BOOTLD_START) / 8; 1417 1418 for (i = 0; i < size; i++) { 1419 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1420 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1421 return -1; 1422 } 1423 data = ((u64)high << 32) | low ; 1424 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1425 flashaddr += 8; 1426 memaddr += 8; 1427 1428 if (i % 0x1000 == 0) 1429 msleep(1); 1430 } 1431 udelay(100); 1432 read_lock(&ha->hw_lock); 1433 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1435 read_unlock(&ha->hw_lock); 1436 return 0; 1437 } 1438 1439 int 1440 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1441 u64 off, void *data, int size) 1442 { 1443 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1444 int shift_amount; 1445 uint32_t temp; 1446 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1447 1448 /* 1449 * If not MN, go check for MS or invalid. 1450 */ 1451 1452 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1453 mem_crb = QLA82XX_CRB_QDR_NET; 1454 else { 1455 mem_crb = QLA82XX_CRB_DDR_NET; 1456 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1457 return qla82xx_pci_mem_read_direct(ha, 1458 off, data, size); 1459 } 1460 1461 off8 = off & 0xfffffff0; 1462 off0[0] = off & 0xf; 1463 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1464 shift_amount = 4; 1465 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1466 off0[1] = 0; 1467 sz[1] = size - sz[0]; 1468 1469 for (i = 0; i < loop; i++) { 1470 temp = off8 + (i << shift_amount); 1471 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1472 temp = 0; 1473 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1474 temp = MIU_TA_CTL_ENABLE; 1475 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1476 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1477 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1478 1479 for (j = 0; j < MAX_CTL_CHECK; j++) { 1480 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1481 if ((temp & MIU_TA_CTL_BUSY) == 0) 1482 break; 1483 } 1484 1485 if (j >= MAX_CTL_CHECK) { 1486 if (printk_ratelimit()) 1487 dev_err(&ha->pdev->dev, 1488 "failed to read through agent.\n"); 1489 break; 1490 } 1491 1492 start = off0[i] >> 2; 1493 end = (off0[i] + sz[i] - 1) >> 2; 1494 for (k = start; k <= end; k++) { 1495 temp = qla82xx_rd_32(ha, 1496 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1497 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1498 } 1499 } 1500 1501 if (j >= MAX_CTL_CHECK) 1502 return -1; 1503 1504 if ((off0[0] & 7) == 0) { 1505 val = word[0]; 1506 } else { 1507 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1508 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1509 } 1510 1511 switch (size) { 1512 case 1: 1513 *(uint8_t *)data = val; 1514 break; 1515 case 2: 1516 *(uint16_t *)data = val; 1517 break; 1518 case 4: 1519 *(uint32_t *)data = val; 1520 break; 1521 case 8: 1522 *(uint64_t *)data = val; 1523 break; 1524 } 1525 return 0; 1526 } 1527 1528 1529 static struct qla82xx_uri_table_desc * 1530 qla82xx_get_table_desc(const u8 *unirom, int section) 1531 { 1532 uint32_t i; 1533 struct qla82xx_uri_table_desc *directory = 1534 (struct qla82xx_uri_table_desc *)&unirom[0]; 1535 __le32 offset; 1536 __le32 tab_type; 1537 __le32 entries = cpu_to_le32(directory->num_entries); 1538 1539 for (i = 0; i < entries; i++) { 1540 offset = cpu_to_le32(directory->findex) + 1541 (i * cpu_to_le32(directory->entry_size)); 1542 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1543 1544 if (tab_type == section) 1545 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1546 } 1547 1548 return NULL; 1549 } 1550 1551 static struct qla82xx_uri_data_desc * 1552 qla82xx_get_data_desc(struct qla_hw_data *ha, 1553 u32 section, u32 idx_offset) 1554 { 1555 const u8 *unirom = ha->hablob->fw->data; 1556 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1557 struct qla82xx_uri_table_desc *tab_desc = NULL; 1558 __le32 offset; 1559 1560 tab_desc = qla82xx_get_table_desc(unirom, section); 1561 if (!tab_desc) 1562 return NULL; 1563 1564 offset = cpu_to_le32(tab_desc->findex) + 1565 (cpu_to_le32(tab_desc->entry_size) * idx); 1566 1567 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1568 } 1569 1570 static u8 * 1571 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1572 { 1573 u32 offset = BOOTLD_START; 1574 struct qla82xx_uri_data_desc *uri_desc = NULL; 1575 1576 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1577 uri_desc = qla82xx_get_data_desc(ha, 1578 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1579 if (uri_desc) 1580 offset = cpu_to_le32(uri_desc->findex); 1581 } 1582 1583 return (u8 *)&ha->hablob->fw->data[offset]; 1584 } 1585 1586 static __le32 1587 qla82xx_get_fw_size(struct qla_hw_data *ha) 1588 { 1589 struct qla82xx_uri_data_desc *uri_desc = NULL; 1590 1591 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1592 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1593 QLA82XX_URI_FIRMWARE_IDX_OFF); 1594 if (uri_desc) 1595 return cpu_to_le32(uri_desc->size); 1596 } 1597 1598 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1599 } 1600 1601 static u8 * 1602 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1603 { 1604 u32 offset = IMAGE_START; 1605 struct qla82xx_uri_data_desc *uri_desc = NULL; 1606 1607 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1608 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1609 QLA82XX_URI_FIRMWARE_IDX_OFF); 1610 if (uri_desc) 1611 offset = cpu_to_le32(uri_desc->findex); 1612 } 1613 1614 return (u8 *)&ha->hablob->fw->data[offset]; 1615 } 1616 1617 /* PCI related functions */ 1618 char * 1619 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1620 { 1621 int pcie_reg; 1622 struct qla_hw_data *ha = vha->hw; 1623 char lwstr[6]; 1624 uint16_t lnk; 1625 1626 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1627 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1628 ha->link_width = (lnk >> 4) & 0x3f; 1629 1630 strcpy(str, "PCIe ("); 1631 strcat(str, "2.5Gb/s "); 1632 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1633 strcat(str, lwstr); 1634 return str; 1635 } 1636 1637 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1638 { 1639 unsigned long val = 0; 1640 u32 control; 1641 1642 switch (region) { 1643 case 0: 1644 val = 0; 1645 break; 1646 case 1: 1647 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1648 val = control + QLA82XX_MSIX_TBL_SPACE; 1649 break; 1650 } 1651 return val; 1652 } 1653 1654 1655 int 1656 qla82xx_iospace_config(struct qla_hw_data *ha) 1657 { 1658 uint32_t len = 0; 1659 1660 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1661 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1662 "Failed to reserver selected regions.\n"); 1663 goto iospace_error_exit; 1664 } 1665 1666 /* Use MMIO operations for all accesses. */ 1667 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1668 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1669 "Region #0 not an MMIO resource, aborting.\n"); 1670 goto iospace_error_exit; 1671 } 1672 1673 len = pci_resource_len(ha->pdev, 0); 1674 ha->nx_pcibase = 1675 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1676 if (!ha->nx_pcibase) { 1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1678 "Cannot remap pcibase MMIO, aborting.\n"); 1679 pci_release_regions(ha->pdev); 1680 goto iospace_error_exit; 1681 } 1682 1683 /* Mapping of IO base pointer */ 1684 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1685 0xbc000 + (ha->pdev->devfn << 11)); 1686 1687 if (!ql2xdbwr) { 1688 ha->nxdb_wr_ptr = 1689 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1690 (ha->pdev->devfn << 12)), 4); 1691 if (!ha->nxdb_wr_ptr) { 1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1693 "Cannot remap MMIO, aborting.\n"); 1694 pci_release_regions(ha->pdev); 1695 goto iospace_error_exit; 1696 } 1697 1698 /* Mapping of IO base pointer, 1699 * door bell read and write pointer 1700 */ 1701 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1702 (ha->pdev->devfn * 8); 1703 } else { 1704 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1705 QLA82XX_CAMRAM_DB1 : 1706 QLA82XX_CAMRAM_DB2); 1707 } 1708 1709 ha->max_req_queues = ha->max_rsp_queues = 1; 1710 ha->msix_count = ha->max_rsp_queues + 1; 1711 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1712 "nx_pci_base=%p iobase=%p " 1713 "max_req_queues=%d msix_count=%d.\n", 1714 (void *)ha->nx_pcibase, ha->iobase, 1715 ha->max_req_queues, ha->msix_count); 1716 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1717 "nx_pci_base=%p iobase=%p " 1718 "max_req_queues=%d msix_count=%d.\n", 1719 (void *)ha->nx_pcibase, ha->iobase, 1720 ha->max_req_queues, ha->msix_count); 1721 return 0; 1722 1723 iospace_error_exit: 1724 return -ENOMEM; 1725 } 1726 1727 /* GS related functions */ 1728 1729 /* Initialization related functions */ 1730 1731 /** 1732 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1733 * @ha: HA context 1734 * 1735 * Returns 0 on success. 1736 */ 1737 int 1738 qla82xx_pci_config(scsi_qla_host_t *vha) 1739 { 1740 struct qla_hw_data *ha = vha->hw; 1741 int ret; 1742 1743 pci_set_master(ha->pdev); 1744 ret = pci_set_mwi(ha->pdev); 1745 ha->chip_revision = ha->pdev->revision; 1746 ql_dbg(ql_dbg_init, vha, 0x0043, 1747 "Chip revision:%d.\n", 1748 ha->chip_revision); 1749 return 0; 1750 } 1751 1752 /** 1753 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1754 * @ha: HA context 1755 * 1756 * Returns 0 on success. 1757 */ 1758 void 1759 qla82xx_reset_chip(scsi_qla_host_t *vha) 1760 { 1761 struct qla_hw_data *ha = vha->hw; 1762 ha->isp_ops->disable_intrs(ha); 1763 } 1764 1765 void qla82xx_config_rings(struct scsi_qla_host *vha) 1766 { 1767 struct qla_hw_data *ha = vha->hw; 1768 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1769 struct init_cb_81xx *icb; 1770 struct req_que *req = ha->req_q_map[0]; 1771 struct rsp_que *rsp = ha->rsp_q_map[0]; 1772 1773 /* Setup ring parameters in initialization control block. */ 1774 icb = (struct init_cb_81xx *)ha->init_cb; 1775 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1776 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1777 icb->request_q_length = cpu_to_le16(req->length); 1778 icb->response_q_length = cpu_to_le16(rsp->length); 1779 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1780 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1781 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1782 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1783 1784 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1785 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1786 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1787 } 1788 1789 void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1790 { 1791 struct qla_hw_data *ha = vha->hw; 1792 vha->flags.online = 0; 1793 qla2x00_try_to_stop_firmware(vha); 1794 ha->isp_ops->disable_intrs(ha); 1795 } 1796 1797 static int 1798 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1799 { 1800 u64 *ptr64; 1801 u32 i, flashaddr, size; 1802 __le64 data; 1803 1804 size = (IMAGE_START - BOOTLD_START) / 8; 1805 1806 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1807 flashaddr = BOOTLD_START; 1808 1809 for (i = 0; i < size; i++) { 1810 data = cpu_to_le64(ptr64[i]); 1811 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1812 return -EIO; 1813 flashaddr += 8; 1814 } 1815 1816 flashaddr = FLASH_ADDR_START; 1817 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1818 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1819 1820 for (i = 0; i < size; i++) { 1821 data = cpu_to_le64(ptr64[i]); 1822 1823 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1824 return -EIO; 1825 flashaddr += 8; 1826 } 1827 udelay(100); 1828 1829 /* Write a magic value to CAMRAM register 1830 * at a specified offset to indicate 1831 * that all data is written and 1832 * ready for firmware to initialize. 1833 */ 1834 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1835 1836 read_lock(&ha->hw_lock); 1837 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1838 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1839 read_unlock(&ha->hw_lock); 1840 return 0; 1841 } 1842 1843 static int 1844 qla82xx_set_product_offset(struct qla_hw_data *ha) 1845 { 1846 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1847 const uint8_t *unirom = ha->hablob->fw->data; 1848 uint32_t i; 1849 __le32 entries; 1850 __le32 flags, file_chiprev, offset; 1851 uint8_t chiprev = ha->chip_revision; 1852 /* Hardcoding mn_present flag for P3P */ 1853 int mn_present = 0; 1854 uint32_t flagbit; 1855 1856 ptab_desc = qla82xx_get_table_desc(unirom, 1857 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1858 if (!ptab_desc) 1859 return -1; 1860 1861 entries = cpu_to_le32(ptab_desc->num_entries); 1862 1863 for (i = 0; i < entries; i++) { 1864 offset = cpu_to_le32(ptab_desc->findex) + 1865 (i * cpu_to_le32(ptab_desc->entry_size)); 1866 flags = cpu_to_le32(*((int *)&unirom[offset] + 1867 QLA82XX_URI_FLAGS_OFF)); 1868 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1869 QLA82XX_URI_CHIP_REV_OFF)); 1870 1871 flagbit = mn_present ? 1 : 2; 1872 1873 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1874 ha->file_prd_off = offset; 1875 return 0; 1876 } 1877 } 1878 return -1; 1879 } 1880 1881 int 1882 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1883 { 1884 __le32 val; 1885 uint32_t min_size; 1886 struct qla_hw_data *ha = vha->hw; 1887 const struct firmware *fw = ha->hablob->fw; 1888 1889 ha->fw_type = fw_type; 1890 1891 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1892 if (qla82xx_set_product_offset(ha)) 1893 return -EINVAL; 1894 1895 min_size = QLA82XX_URI_FW_MIN_SIZE; 1896 } else { 1897 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1898 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1899 return -EINVAL; 1900 1901 min_size = QLA82XX_FW_MIN_SIZE; 1902 } 1903 1904 if (fw->size < min_size) 1905 return -EINVAL; 1906 return 0; 1907 } 1908 1909 static int 1910 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1911 { 1912 u32 val = 0; 1913 int retries = 60; 1914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1915 1916 do { 1917 read_lock(&ha->hw_lock); 1918 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1919 read_unlock(&ha->hw_lock); 1920 1921 switch (val) { 1922 case PHAN_INITIALIZE_COMPLETE: 1923 case PHAN_INITIALIZE_ACK: 1924 return QLA_SUCCESS; 1925 case PHAN_INITIALIZE_FAILED: 1926 break; 1927 default: 1928 break; 1929 } 1930 ql_log(ql_log_info, vha, 0x00a8, 1931 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1932 val, retries); 1933 1934 msleep(500); 1935 1936 } while (--retries); 1937 1938 ql_log(ql_log_fatal, vha, 0x00a9, 1939 "Cmd Peg initialization failed: 0x%x.\n", val); 1940 1941 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1942 read_lock(&ha->hw_lock); 1943 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1944 read_unlock(&ha->hw_lock); 1945 return QLA_FUNCTION_FAILED; 1946 } 1947 1948 static int 1949 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1950 { 1951 u32 val = 0; 1952 int retries = 60; 1953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1954 1955 do { 1956 read_lock(&ha->hw_lock); 1957 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1958 read_unlock(&ha->hw_lock); 1959 1960 switch (val) { 1961 case PHAN_INITIALIZE_COMPLETE: 1962 case PHAN_INITIALIZE_ACK: 1963 return QLA_SUCCESS; 1964 case PHAN_INITIALIZE_FAILED: 1965 break; 1966 default: 1967 break; 1968 } 1969 ql_log(ql_log_info, vha, 0x00ab, 1970 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1971 val, retries); 1972 1973 msleep(500); 1974 1975 } while (--retries); 1976 1977 ql_log(ql_log_fatal, vha, 0x00ac, 1978 "Rcv Peg initializatin failed: 0x%x.\n", val); 1979 read_lock(&ha->hw_lock); 1980 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1981 read_unlock(&ha->hw_lock); 1982 return QLA_FUNCTION_FAILED; 1983 } 1984 1985 /* ISR related functions */ 1986 uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1987 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1988 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1989 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1990 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1991 }; 1992 1993 uint32_t qla82xx_isr_int_target_status[8] = { 1994 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1995 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1996 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1997 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1998 }; 1999 2000 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 2001 QLA82XX_LEGACY_INTR_CONFIG; 2002 2003 /* 2004 * qla82xx_mbx_completion() - Process mailbox command completions. 2005 * @ha: SCSI driver HA context 2006 * @mb0: Mailbox0 register 2007 */ 2008 static void 2009 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2010 { 2011 uint16_t cnt; 2012 uint16_t __iomem *wptr; 2013 struct qla_hw_data *ha = vha->hw; 2014 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2015 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2016 2017 /* Load return mailbox registers. */ 2018 ha->flags.mbox_int = 1; 2019 ha->mailbox_out[0] = mb0; 2020 2021 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2022 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2023 wptr++; 2024 } 2025 2026 if (!ha->mcp) 2027 ql_dbg(ql_dbg_async, vha, 0x5053, 2028 "MBX pointer ERROR.\n"); 2029 } 2030 2031 /* 2032 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2033 * @irq: 2034 * @dev_id: SCSI driver HA context 2035 * @regs: 2036 * 2037 * Called by system whenever the host adapter generates an interrupt. 2038 * 2039 * Returns handled flag. 2040 */ 2041 irqreturn_t 2042 qla82xx_intr_handler(int irq, void *dev_id) 2043 { 2044 scsi_qla_host_t *vha; 2045 struct qla_hw_data *ha; 2046 struct rsp_que *rsp; 2047 struct device_reg_82xx __iomem *reg; 2048 int status = 0, status1 = 0; 2049 unsigned long flags; 2050 unsigned long iter; 2051 uint32_t stat = 0; 2052 uint16_t mb[4]; 2053 2054 rsp = (struct rsp_que *) dev_id; 2055 if (!rsp) { 2056 printk(KERN_INFO 2057 "%s(): NULL response queue pointer.\n", __func__); 2058 return IRQ_NONE; 2059 } 2060 ha = rsp->hw; 2061 2062 if (!ha->flags.msi_enabled) { 2063 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2064 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2065 return IRQ_NONE; 2066 2067 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2068 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2069 return IRQ_NONE; 2070 } 2071 2072 /* clear the interrupt */ 2073 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2074 2075 /* read twice to ensure write is flushed */ 2076 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2077 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2078 2079 reg = &ha->iobase->isp82; 2080 2081 spin_lock_irqsave(&ha->hardware_lock, flags); 2082 vha = pci_get_drvdata(ha->pdev); 2083 for (iter = 1; iter--; ) { 2084 2085 if (RD_REG_DWORD(®->host_int)) { 2086 stat = RD_REG_DWORD(®->host_status); 2087 2088 switch (stat & 0xff) { 2089 case 0x1: 2090 case 0x2: 2091 case 0x10: 2092 case 0x11: 2093 qla82xx_mbx_completion(vha, MSW(stat)); 2094 status |= MBX_INTERRUPT; 2095 break; 2096 case 0x12: 2097 mb[0] = MSW(stat); 2098 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2099 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2100 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2101 qla2x00_async_event(vha, rsp, mb); 2102 break; 2103 case 0x13: 2104 qla24xx_process_response_queue(vha, rsp); 2105 break; 2106 default: 2107 ql_dbg(ql_dbg_async, vha, 0x5054, 2108 "Unrecognized interrupt type (%d).\n", 2109 stat & 0xff); 2110 break; 2111 } 2112 } 2113 WRT_REG_DWORD(®->host_int, 0); 2114 } 2115 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2116 if (!ha->flags.msi_enabled) 2117 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2118 2119 #ifdef QL_DEBUG_LEVEL_17 2120 if (!irq && ha->flags.eeh_busy) 2121 ql_log(ql_log_warn, vha, 0x503d, 2122 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2123 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2124 #endif 2125 2126 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2127 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2128 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2129 complete(&ha->mbx_intr_comp); 2130 } 2131 return IRQ_HANDLED; 2132 } 2133 2134 irqreturn_t 2135 qla82xx_msix_default(int irq, void *dev_id) 2136 { 2137 scsi_qla_host_t *vha; 2138 struct qla_hw_data *ha; 2139 struct rsp_que *rsp; 2140 struct device_reg_82xx __iomem *reg; 2141 int status = 0; 2142 unsigned long flags; 2143 uint32_t stat = 0; 2144 uint16_t mb[4]; 2145 2146 rsp = (struct rsp_que *) dev_id; 2147 if (!rsp) { 2148 printk(KERN_INFO 2149 "%s(): NULL response queue pointer.\n", __func__); 2150 return IRQ_NONE; 2151 } 2152 ha = rsp->hw; 2153 2154 reg = &ha->iobase->isp82; 2155 2156 spin_lock_irqsave(&ha->hardware_lock, flags); 2157 vha = pci_get_drvdata(ha->pdev); 2158 do { 2159 if (RD_REG_DWORD(®->host_int)) { 2160 stat = RD_REG_DWORD(®->host_status); 2161 2162 switch (stat & 0xff) { 2163 case 0x1: 2164 case 0x2: 2165 case 0x10: 2166 case 0x11: 2167 qla82xx_mbx_completion(vha, MSW(stat)); 2168 status |= MBX_INTERRUPT; 2169 break; 2170 case 0x12: 2171 mb[0] = MSW(stat); 2172 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2173 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2174 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2175 qla2x00_async_event(vha, rsp, mb); 2176 break; 2177 case 0x13: 2178 qla24xx_process_response_queue(vha, rsp); 2179 break; 2180 default: 2181 ql_dbg(ql_dbg_async, vha, 0x5041, 2182 "Unrecognized interrupt type (%d).\n", 2183 stat & 0xff); 2184 break; 2185 } 2186 } 2187 WRT_REG_DWORD(®->host_int, 0); 2188 } while (0); 2189 2190 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2191 2192 #ifdef QL_DEBUG_LEVEL_17 2193 if (!irq && ha->flags.eeh_busy) 2194 ql_log(ql_log_warn, vha, 0x5044, 2195 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2196 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2197 #endif 2198 2199 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2200 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2201 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2202 complete(&ha->mbx_intr_comp); 2203 } 2204 return IRQ_HANDLED; 2205 } 2206 2207 irqreturn_t 2208 qla82xx_msix_rsp_q(int irq, void *dev_id) 2209 { 2210 scsi_qla_host_t *vha; 2211 struct qla_hw_data *ha; 2212 struct rsp_que *rsp; 2213 struct device_reg_82xx __iomem *reg; 2214 unsigned long flags; 2215 2216 rsp = (struct rsp_que *) dev_id; 2217 if (!rsp) { 2218 printk(KERN_INFO 2219 "%s(): NULL response queue pointer.\n", __func__); 2220 return IRQ_NONE; 2221 } 2222 2223 ha = rsp->hw; 2224 reg = &ha->iobase->isp82; 2225 spin_lock_irqsave(&ha->hardware_lock, flags); 2226 vha = pci_get_drvdata(ha->pdev); 2227 qla24xx_process_response_queue(vha, rsp); 2228 WRT_REG_DWORD(®->host_int, 0); 2229 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2230 return IRQ_HANDLED; 2231 } 2232 2233 void 2234 qla82xx_poll(int irq, void *dev_id) 2235 { 2236 scsi_qla_host_t *vha; 2237 struct qla_hw_data *ha; 2238 struct rsp_que *rsp; 2239 struct device_reg_82xx __iomem *reg; 2240 int status = 0; 2241 uint32_t stat; 2242 uint16_t mb[4]; 2243 unsigned long flags; 2244 2245 rsp = (struct rsp_que *) dev_id; 2246 if (!rsp) { 2247 printk(KERN_INFO 2248 "%s(): NULL response queue pointer.\n", __func__); 2249 return; 2250 } 2251 ha = rsp->hw; 2252 2253 reg = &ha->iobase->isp82; 2254 spin_lock_irqsave(&ha->hardware_lock, flags); 2255 vha = pci_get_drvdata(ha->pdev); 2256 2257 if (RD_REG_DWORD(®->host_int)) { 2258 stat = RD_REG_DWORD(®->host_status); 2259 switch (stat & 0xff) { 2260 case 0x1: 2261 case 0x2: 2262 case 0x10: 2263 case 0x11: 2264 qla82xx_mbx_completion(vha, MSW(stat)); 2265 status |= MBX_INTERRUPT; 2266 break; 2267 case 0x12: 2268 mb[0] = MSW(stat); 2269 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2270 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2271 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2272 qla2x00_async_event(vha, rsp, mb); 2273 break; 2274 case 0x13: 2275 qla24xx_process_response_queue(vha, rsp); 2276 break; 2277 default: 2278 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2279 "Unrecognized interrupt type (%d).\n", 2280 stat * 0xff); 2281 break; 2282 } 2283 } 2284 WRT_REG_DWORD(®->host_int, 0); 2285 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2286 } 2287 2288 void 2289 qla82xx_enable_intrs(struct qla_hw_data *ha) 2290 { 2291 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2292 qla82xx_mbx_intr_enable(vha); 2293 spin_lock_irq(&ha->hardware_lock); 2294 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2295 spin_unlock_irq(&ha->hardware_lock); 2296 ha->interrupts_on = 1; 2297 } 2298 2299 void 2300 qla82xx_disable_intrs(struct qla_hw_data *ha) 2301 { 2302 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2303 qla82xx_mbx_intr_disable(vha); 2304 spin_lock_irq(&ha->hardware_lock); 2305 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2306 spin_unlock_irq(&ha->hardware_lock); 2307 ha->interrupts_on = 0; 2308 } 2309 2310 void qla82xx_init_flags(struct qla_hw_data *ha) 2311 { 2312 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2313 2314 /* ISP 8021 initializations */ 2315 rwlock_init(&ha->hw_lock); 2316 ha->qdr_sn_window = -1; 2317 ha->ddr_mn_window = -1; 2318 ha->curr_window = 255; 2319 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2320 nx_legacy_intr = &legacy_intr[ha->portnum]; 2321 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2322 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2323 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2324 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2325 } 2326 2327 inline void 2328 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2329 { 2330 uint32_t drv_active; 2331 struct qla_hw_data *ha = vha->hw; 2332 2333 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2334 2335 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2336 if (drv_active == 0xffffffff) { 2337 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2338 QLA82XX_DRV_NOT_ACTIVE); 2339 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2340 } 2341 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2342 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2343 } 2344 2345 inline void 2346 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2347 { 2348 uint32_t drv_active; 2349 2350 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2351 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2352 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2353 } 2354 2355 static inline int 2356 qla82xx_need_reset(struct qla_hw_data *ha) 2357 { 2358 uint32_t drv_state; 2359 int rval; 2360 2361 if (ha->flags.isp82xx_reset_owner) 2362 return 1; 2363 else { 2364 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2365 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2366 return rval; 2367 } 2368 } 2369 2370 static inline void 2371 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2372 { 2373 uint32_t drv_state; 2374 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2375 2376 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2377 2378 /* If reset value is all FF's, initialize DRV_STATE */ 2379 if (drv_state == 0xffffffff) { 2380 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2381 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382 } 2383 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2384 ql_dbg(ql_dbg_init, vha, 0x00bb, 2385 "drv_state = 0x%08x.\n", drv_state); 2386 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2387 } 2388 2389 static inline void 2390 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2391 { 2392 uint32_t drv_state; 2393 2394 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2395 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2396 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2397 } 2398 2399 static inline void 2400 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2401 { 2402 uint32_t qsnt_state; 2403 2404 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2405 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2406 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2407 } 2408 2409 void 2410 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2411 { 2412 struct qla_hw_data *ha = vha->hw; 2413 uint32_t qsnt_state; 2414 2415 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2416 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2417 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2418 } 2419 2420 static int 2421 qla82xx_load_fw(scsi_qla_host_t *vha) 2422 { 2423 int rst; 2424 struct fw_blob *blob; 2425 struct qla_hw_data *ha = vha->hw; 2426 2427 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2428 ql_log(ql_log_fatal, vha, 0x009f, 2429 "Error during CRB initialization.\n"); 2430 return QLA_FUNCTION_FAILED; 2431 } 2432 udelay(500); 2433 2434 /* Bring QM and CAMRAM out of reset */ 2435 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2436 rst &= ~((1 << 28) | (1 << 24)); 2437 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2438 2439 /* 2440 * FW Load priority: 2441 * 1) Operational firmware residing in flash. 2442 * 2) Firmware via request-firmware interface (.bin file). 2443 */ 2444 if (ql2xfwloadbin == 2) 2445 goto try_blob_fw; 2446 2447 ql_log(ql_log_info, vha, 0x00a0, 2448 "Attempting to load firmware from flash.\n"); 2449 2450 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2451 ql_log(ql_log_info, vha, 0x00a1, 2452 "Firmware loaded successully from flash.\n"); 2453 return QLA_SUCCESS; 2454 } else { 2455 ql_log(ql_log_warn, vha, 0x0108, 2456 "Firmware load from flash failed.\n"); 2457 } 2458 2459 try_blob_fw: 2460 ql_log(ql_log_info, vha, 0x00a2, 2461 "Attempting to load firmware from blob.\n"); 2462 2463 /* Load firmware blob. */ 2464 blob = ha->hablob = qla2x00_request_firmware(vha); 2465 if (!blob) { 2466 ql_log(ql_log_fatal, vha, 0x00a3, 2467 "Firmware image not preset.\n"); 2468 goto fw_load_failed; 2469 } 2470 2471 /* Validating firmware blob */ 2472 if (qla82xx_validate_firmware_blob(vha, 2473 QLA82XX_FLASH_ROMIMAGE)) { 2474 /* Fallback to URI format */ 2475 if (qla82xx_validate_firmware_blob(vha, 2476 QLA82XX_UNIFIED_ROMIMAGE)) { 2477 ql_log(ql_log_fatal, vha, 0x00a4, 2478 "No valid firmware image found.\n"); 2479 return QLA_FUNCTION_FAILED; 2480 } 2481 } 2482 2483 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2484 ql_log(ql_log_info, vha, 0x00a5, 2485 "Firmware loaded successfully from binary blob.\n"); 2486 return QLA_SUCCESS; 2487 } else { 2488 ql_log(ql_log_fatal, vha, 0x00a6, 2489 "Firmware load failed for binary blob.\n"); 2490 blob->fw = NULL; 2491 blob = NULL; 2492 goto fw_load_failed; 2493 } 2494 return QLA_SUCCESS; 2495 2496 fw_load_failed: 2497 return QLA_FUNCTION_FAILED; 2498 } 2499 2500 int 2501 qla82xx_start_firmware(scsi_qla_host_t *vha) 2502 { 2503 int pcie_cap; 2504 uint16_t lnk; 2505 struct qla_hw_data *ha = vha->hw; 2506 2507 /* scrub dma mask expansion register */ 2508 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2509 2510 /* Put both the PEG CMD and RCV PEG to default state 2511 * of 0 before resetting the hardware 2512 */ 2513 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2514 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2515 2516 /* Overwrite stale initialization register values */ 2517 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2518 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2519 2520 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2521 ql_log(ql_log_fatal, vha, 0x00a7, 2522 "Error trying to start fw.\n"); 2523 return QLA_FUNCTION_FAILED; 2524 } 2525 2526 /* Handshake with the card before we register the devices. */ 2527 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2528 ql_log(ql_log_fatal, vha, 0x00aa, 2529 "Error during card handshake.\n"); 2530 return QLA_FUNCTION_FAILED; 2531 } 2532 2533 /* Negotiated Link width */ 2534 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2535 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2536 ha->link_width = (lnk >> 4) & 0x3f; 2537 2538 /* Synchronize with Receive peg */ 2539 return qla82xx_check_rcvpeg_state(ha); 2540 } 2541 2542 static uint32_t * 2543 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2544 uint32_t length) 2545 { 2546 uint32_t i; 2547 uint32_t val; 2548 struct qla_hw_data *ha = vha->hw; 2549 2550 /* Dword reads to flash. */ 2551 for (i = 0; i < length/4; i++, faddr += 4) { 2552 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2553 ql_log(ql_log_warn, vha, 0x0106, 2554 "Do ROM fast read failed.\n"); 2555 goto done_read; 2556 } 2557 dwptr[i] = __constant_cpu_to_le32(val); 2558 } 2559 done_read: 2560 return dwptr; 2561 } 2562 2563 static int 2564 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2565 { 2566 int ret; 2567 uint32_t val; 2568 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2569 2570 ret = ql82xx_rom_lock_d(ha); 2571 if (ret < 0) { 2572 ql_log(ql_log_warn, vha, 0xb014, 2573 "ROM Lock failed.\n"); 2574 return ret; 2575 } 2576 2577 ret = qla82xx_read_status_reg(ha, &val); 2578 if (ret < 0) 2579 goto done_unprotect; 2580 2581 val &= ~(BLOCK_PROTECT_BITS << 2); 2582 ret = qla82xx_write_status_reg(ha, val); 2583 if (ret < 0) { 2584 val |= (BLOCK_PROTECT_BITS << 2); 2585 qla82xx_write_status_reg(ha, val); 2586 } 2587 2588 if (qla82xx_write_disable_flash(ha) != 0) 2589 ql_log(ql_log_warn, vha, 0xb015, 2590 "Write disable failed.\n"); 2591 2592 done_unprotect: 2593 qla82xx_rom_unlock(ha); 2594 return ret; 2595 } 2596 2597 static int 2598 qla82xx_protect_flash(struct qla_hw_data *ha) 2599 { 2600 int ret; 2601 uint32_t val; 2602 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2603 2604 ret = ql82xx_rom_lock_d(ha); 2605 if (ret < 0) { 2606 ql_log(ql_log_warn, vha, 0xb016, 2607 "ROM Lock failed.\n"); 2608 return ret; 2609 } 2610 2611 ret = qla82xx_read_status_reg(ha, &val); 2612 if (ret < 0) 2613 goto done_protect; 2614 2615 val |= (BLOCK_PROTECT_BITS << 2); 2616 /* LOCK all sectors */ 2617 ret = qla82xx_write_status_reg(ha, val); 2618 if (ret < 0) 2619 ql_log(ql_log_warn, vha, 0xb017, 2620 "Write status register failed.\n"); 2621 2622 if (qla82xx_write_disable_flash(ha) != 0) 2623 ql_log(ql_log_warn, vha, 0xb018, 2624 "Write disable failed.\n"); 2625 done_protect: 2626 qla82xx_rom_unlock(ha); 2627 return ret; 2628 } 2629 2630 static int 2631 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2632 { 2633 int ret = 0; 2634 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2635 2636 ret = ql82xx_rom_lock_d(ha); 2637 if (ret < 0) { 2638 ql_log(ql_log_warn, vha, 0xb019, 2639 "ROM Lock failed.\n"); 2640 return ret; 2641 } 2642 2643 qla82xx_flash_set_write_enable(ha); 2644 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2645 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2646 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2647 2648 if (qla82xx_wait_rom_done(ha)) { 2649 ql_log(ql_log_warn, vha, 0xb01a, 2650 "Error waiting for rom done.\n"); 2651 ret = -1; 2652 goto done; 2653 } 2654 ret = qla82xx_flash_wait_write_finish(ha); 2655 done: 2656 qla82xx_rom_unlock(ha); 2657 return ret; 2658 } 2659 2660 /* 2661 * Address and length are byte address 2662 */ 2663 uint8_t * 2664 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2665 uint32_t offset, uint32_t length) 2666 { 2667 scsi_block_requests(vha->host); 2668 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2669 scsi_unblock_requests(vha->host); 2670 return buf; 2671 } 2672 2673 static int 2674 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2675 uint32_t faddr, uint32_t dwords) 2676 { 2677 int ret; 2678 uint32_t liter; 2679 uint32_t sec_mask, rest_addr; 2680 dma_addr_t optrom_dma; 2681 void *optrom = NULL; 2682 int page_mode = 0; 2683 struct qla_hw_data *ha = vha->hw; 2684 2685 ret = -1; 2686 2687 /* Prepare burst-capable write on supported ISPs. */ 2688 if (page_mode && !(faddr & 0xfff) && 2689 dwords > OPTROM_BURST_DWORDS) { 2690 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2691 &optrom_dma, GFP_KERNEL); 2692 if (!optrom) { 2693 ql_log(ql_log_warn, vha, 0xb01b, 2694 "Unable to allocate memory " 2695 "for optron burst write (%x KB).\n", 2696 OPTROM_BURST_SIZE / 1024); 2697 } 2698 } 2699 2700 rest_addr = ha->fdt_block_size - 1; 2701 sec_mask = ~rest_addr; 2702 2703 ret = qla82xx_unprotect_flash(ha); 2704 if (ret) { 2705 ql_log(ql_log_warn, vha, 0xb01c, 2706 "Unable to unprotect flash for update.\n"); 2707 goto write_done; 2708 } 2709 2710 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2711 /* Are we at the beginning of a sector? */ 2712 if ((faddr & rest_addr) == 0) { 2713 2714 ret = qla82xx_erase_sector(ha, faddr); 2715 if (ret) { 2716 ql_log(ql_log_warn, vha, 0xb01d, 2717 "Unable to erase sector: address=%x.\n", 2718 faddr); 2719 break; 2720 } 2721 } 2722 2723 /* Go with burst-write. */ 2724 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2725 /* Copy data to DMA'ble buffer. */ 2726 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2727 2728 ret = qla2x00_load_ram(vha, optrom_dma, 2729 (ha->flash_data_off | faddr), 2730 OPTROM_BURST_DWORDS); 2731 if (ret != QLA_SUCCESS) { 2732 ql_log(ql_log_warn, vha, 0xb01e, 2733 "Unable to burst-write optrom segment " 2734 "(%x/%x/%llx).\n", ret, 2735 (ha->flash_data_off | faddr), 2736 (unsigned long long)optrom_dma); 2737 ql_log(ql_log_warn, vha, 0xb01f, 2738 "Reverting to slow-write.\n"); 2739 2740 dma_free_coherent(&ha->pdev->dev, 2741 OPTROM_BURST_SIZE, optrom, optrom_dma); 2742 optrom = NULL; 2743 } else { 2744 liter += OPTROM_BURST_DWORDS - 1; 2745 faddr += OPTROM_BURST_DWORDS - 1; 2746 dwptr += OPTROM_BURST_DWORDS - 1; 2747 continue; 2748 } 2749 } 2750 2751 ret = qla82xx_write_flash_dword(ha, faddr, 2752 cpu_to_le32(*dwptr)); 2753 if (ret) { 2754 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2755 "Unable to program flash address=%x data=%x.\n", 2756 faddr, *dwptr); 2757 break; 2758 } 2759 } 2760 2761 ret = qla82xx_protect_flash(ha); 2762 if (ret) 2763 ql_log(ql_log_warn, vha, 0xb021, 2764 "Unable to protect flash after update.\n"); 2765 write_done: 2766 if (optrom) 2767 dma_free_coherent(&ha->pdev->dev, 2768 OPTROM_BURST_SIZE, optrom, optrom_dma); 2769 return ret; 2770 } 2771 2772 int 2773 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2774 uint32_t offset, uint32_t length) 2775 { 2776 int rval; 2777 2778 /* Suspend HBA. */ 2779 scsi_block_requests(vha->host); 2780 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2781 length >> 2); 2782 scsi_unblock_requests(vha->host); 2783 2784 /* Convert return ISP82xx to generic */ 2785 if (rval) 2786 rval = QLA_FUNCTION_FAILED; 2787 else 2788 rval = QLA_SUCCESS; 2789 return rval; 2790 } 2791 2792 void 2793 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2794 { 2795 struct qla_hw_data *ha = vha->hw; 2796 struct req_que *req = ha->req_q_map[0]; 2797 struct device_reg_82xx __iomem *reg; 2798 uint32_t dbval; 2799 2800 /* Adjust ring index. */ 2801 req->ring_index++; 2802 if (req->ring_index == req->length) { 2803 req->ring_index = 0; 2804 req->ring_ptr = req->ring; 2805 } else 2806 req->ring_ptr++; 2807 2808 reg = &ha->iobase->isp82; 2809 dbval = 0x04 | (ha->portnum << 5); 2810 2811 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2812 if (ql2xdbwr) 2813 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2814 else { 2815 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2816 wmb(); 2817 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2818 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2819 dbval); 2820 wmb(); 2821 } 2822 } 2823 } 2824 2825 void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2826 { 2827 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2828 2829 if (qla82xx_rom_lock(ha)) 2830 /* Someone else is holding the lock. */ 2831 ql_log(ql_log_info, vha, 0xb022, 2832 "Resetting rom_lock.\n"); 2833 2834 /* 2835 * Either we got the lock, or someone 2836 * else died while holding it. 2837 * In either case, unlock. 2838 */ 2839 qla82xx_rom_unlock(ha); 2840 } 2841 2842 /* 2843 * qla82xx_device_bootstrap 2844 * Initialize device, set DEV_READY, start fw 2845 * 2846 * Note: 2847 * IDC lock must be held upon entry 2848 * 2849 * Return: 2850 * Success : 0 2851 * Failed : 1 2852 */ 2853 static int 2854 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2855 { 2856 int rval = QLA_SUCCESS; 2857 int i, timeout; 2858 uint32_t old_count, count; 2859 struct qla_hw_data *ha = vha->hw; 2860 int need_reset = 0, peg_stuck = 1; 2861 2862 need_reset = qla82xx_need_reset(ha); 2863 2864 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2865 2866 for (i = 0; i < 10; i++) { 2867 timeout = msleep_interruptible(200); 2868 if (timeout) { 2869 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2870 QLA82XX_DEV_FAILED); 2871 return QLA_FUNCTION_FAILED; 2872 } 2873 2874 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2875 if (count != old_count) 2876 peg_stuck = 0; 2877 } 2878 2879 if (need_reset) { 2880 /* We are trying to perform a recovery here. */ 2881 if (peg_stuck) 2882 qla82xx_rom_lock_recovery(ha); 2883 goto dev_initialize; 2884 } else { 2885 /* Start of day for this ha context. */ 2886 if (peg_stuck) { 2887 /* Either we are the first or recovery in progress. */ 2888 qla82xx_rom_lock_recovery(ha); 2889 goto dev_initialize; 2890 } else 2891 /* Firmware already running. */ 2892 goto dev_ready; 2893 } 2894 2895 return rval; 2896 2897 dev_initialize: 2898 /* set to DEV_INITIALIZING */ 2899 ql_log(ql_log_info, vha, 0x009e, 2900 "HW State: INITIALIZING.\n"); 2901 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2902 2903 /* Driver that sets device state to initializating sets IDC version */ 2904 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2905 2906 qla82xx_idc_unlock(ha); 2907 rval = qla82xx_start_firmware(vha); 2908 qla82xx_idc_lock(ha); 2909 2910 if (rval != QLA_SUCCESS) { 2911 ql_log(ql_log_fatal, vha, 0x00ad, 2912 "HW State: FAILED.\n"); 2913 qla82xx_clear_drv_active(ha); 2914 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2915 return rval; 2916 } 2917 2918 dev_ready: 2919 ql_log(ql_log_info, vha, 0x00ae, 2920 "HW State: READY.\n"); 2921 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2922 2923 return QLA_SUCCESS; 2924 } 2925 2926 /* 2927 * qla82xx_need_qsnt_handler 2928 * Code to start quiescence sequence 2929 * 2930 * Note: 2931 * IDC lock must be held upon entry 2932 * 2933 * Return: void 2934 */ 2935 2936 static void 2937 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2938 { 2939 struct qla_hw_data *ha = vha->hw; 2940 uint32_t dev_state, drv_state, drv_active; 2941 unsigned long reset_timeout; 2942 2943 if (vha->flags.online) { 2944 /*Block any further I/O and wait for pending cmnds to complete*/ 2945 qla82xx_quiescent_state_cleanup(vha); 2946 } 2947 2948 /* Set the quiescence ready bit */ 2949 qla82xx_set_qsnt_ready(ha); 2950 2951 /*wait for 30 secs for other functions to ack */ 2952 reset_timeout = jiffies + (30 * HZ); 2953 2954 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2955 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2956 /* Its 2 that is written when qsnt is acked, moving one bit */ 2957 drv_active = drv_active << 0x01; 2958 2959 while (drv_state != drv_active) { 2960 2961 if (time_after_eq(jiffies, reset_timeout)) { 2962 /* quiescence timeout, other functions didn't ack 2963 * changing the state to DEV_READY 2964 */ 2965 ql_log(ql_log_info, vha, 0xb023, 2966 "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 2967 ql_log(ql_log_info, vha, 0xb024, 2968 "DRV_ACTIVE:%d DRV_STATE:%d.\n", 2969 drv_active, drv_state); 2970 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2971 QLA82XX_DEV_READY); 2972 ql_log(ql_log_info, vha, 0xb025, 2973 "HW State: DEV_READY.\n"); 2974 qla82xx_idc_unlock(ha); 2975 qla2x00_perform_loop_resync(vha); 2976 qla82xx_idc_lock(ha); 2977 2978 qla82xx_clear_qsnt_ready(vha); 2979 return; 2980 } 2981 2982 qla82xx_idc_unlock(ha); 2983 msleep(1000); 2984 qla82xx_idc_lock(ha); 2985 2986 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2987 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2988 drv_active = drv_active << 0x01; 2989 } 2990 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2991 /* everyone acked so set the state to DEV_QUIESCENCE */ 2992 if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 2993 ql_log(ql_log_info, vha, 0xb026, 2994 "HW State: DEV_QUIESCENT.\n"); 2995 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 2996 } 2997 } 2998 2999 /* 3000 * qla82xx_wait_for_state_change 3001 * Wait for device state to change from given current state 3002 * 3003 * Note: 3004 * IDC lock must not be held upon entry 3005 * 3006 * Return: 3007 * Changed device state. 3008 */ 3009 uint32_t 3010 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3011 { 3012 struct qla_hw_data *ha = vha->hw; 3013 uint32_t dev_state; 3014 3015 do { 3016 msleep(1000); 3017 qla82xx_idc_lock(ha); 3018 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3019 qla82xx_idc_unlock(ha); 3020 } while (dev_state == curr_state); 3021 3022 return dev_state; 3023 } 3024 3025 static void 3026 qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3027 { 3028 struct qla_hw_data *ha = vha->hw; 3029 3030 /* Disable the board */ 3031 ql_log(ql_log_fatal, vha, 0x00b8, 3032 "Disabling the board.\n"); 3033 3034 qla82xx_idc_lock(ha); 3035 qla82xx_clear_drv_active(ha); 3036 qla82xx_idc_unlock(ha); 3037 3038 /* Set DEV_FAILED flag to disable timer */ 3039 vha->device_flags |= DFLG_DEV_FAILED; 3040 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3041 qla2x00_mark_all_devices_lost(vha, 0); 3042 vha->flags.online = 0; 3043 vha->flags.init_done = 0; 3044 } 3045 3046 /* 3047 * qla82xx_need_reset_handler 3048 * Code to start reset sequence 3049 * 3050 * Note: 3051 * IDC lock must be held upon entry 3052 * 3053 * Return: 3054 * Success : 0 3055 * Failed : 1 3056 */ 3057 static void 3058 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3059 { 3060 uint32_t dev_state, drv_state, drv_active; 3061 uint32_t active_mask = 0; 3062 unsigned long reset_timeout; 3063 struct qla_hw_data *ha = vha->hw; 3064 struct req_que *req = ha->req_q_map[0]; 3065 3066 if (vha->flags.online) { 3067 qla82xx_idc_unlock(ha); 3068 qla2x00_abort_isp_cleanup(vha); 3069 ha->isp_ops->get_flash_version(vha, req->ring); 3070 ha->isp_ops->nvram_config(vha); 3071 qla82xx_idc_lock(ha); 3072 } 3073 3074 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3075 if (!ha->flags.isp82xx_reset_owner) { 3076 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3077 "reset_acknowledged by 0x%x\n", ha->portnum); 3078 qla82xx_set_rst_ready(ha); 3079 } else { 3080 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3081 drv_active &= active_mask; 3082 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3083 "active_mask: 0x%08x\n", active_mask); 3084 } 3085 3086 /* wait for 10 seconds for reset ack from all functions */ 3087 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3088 3089 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3090 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3091 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3092 3093 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3094 "drv_state: 0x%08x, drv_active: 0x%08x, " 3095 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3096 drv_state, drv_active, dev_state, active_mask); 3097 3098 while (drv_state != drv_active && 3099 dev_state != QLA82XX_DEV_INITIALIZING) { 3100 if (time_after_eq(jiffies, reset_timeout)) { 3101 ql_log(ql_log_warn, vha, 0x00b5, 3102 "Reset timeout.\n"); 3103 break; 3104 } 3105 qla82xx_idc_unlock(ha); 3106 msleep(1000); 3107 qla82xx_idc_lock(ha); 3108 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3109 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3110 if (ha->flags.isp82xx_reset_owner) 3111 drv_active &= active_mask; 3112 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3113 } 3114 3115 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3116 "drv_state: 0x%08x, drv_active: 0x%08x, " 3117 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3118 drv_state, drv_active, dev_state, active_mask); 3119 3120 ql_log(ql_log_info, vha, 0x00b6, 3121 "Device state is 0x%x = %s.\n", 3122 dev_state, 3123 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3124 3125 /* Force to DEV_COLD unless someone else is starting a reset */ 3126 if (dev_state != QLA82XX_DEV_INITIALIZING && 3127 dev_state != QLA82XX_DEV_COLD) { 3128 ql_log(ql_log_info, vha, 0x00b7, 3129 "HW State: COLD/RE-INIT.\n"); 3130 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3131 if (ql2xmdenable) { 3132 if (qla82xx_md_collect(vha)) 3133 ql_log(ql_log_warn, vha, 0xb02c, 3134 "Not able to collect minidump.\n"); 3135 } else 3136 ql_log(ql_log_warn, vha, 0xb04f, 3137 "Minidump disabled.\n"); 3138 } 3139 } 3140 3141 int 3142 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3143 { 3144 struct qla_hw_data *ha = vha->hw; 3145 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3146 int rval = QLA_SUCCESS; 3147 3148 fw_major_version = ha->fw_major_version; 3149 fw_minor_version = ha->fw_minor_version; 3150 fw_subminor_version = ha->fw_subminor_version; 3151 3152 rval = qla2x00_get_fw_version(vha, &ha->fw_major_version, 3153 &ha->fw_minor_version, &ha->fw_subminor_version, 3154 &ha->fw_attributes, &ha->fw_memory_size, 3155 ha->mpi_version, &ha->mpi_capabilities, 3156 ha->phy_version); 3157 3158 if (rval != QLA_SUCCESS) 3159 return rval; 3160 3161 if (ql2xmdenable) { 3162 if (!ha->fw_dumped) { 3163 if (fw_major_version != ha->fw_major_version || 3164 fw_minor_version != ha->fw_minor_version || 3165 fw_subminor_version != ha->fw_subminor_version) { 3166 3167 ql_log(ql_log_info, vha, 0xb02d, 3168 "Firmware version differs " 3169 "Previous version: %d:%d:%d - " 3170 "New version: %d:%d:%d\n", 3171 ha->fw_major_version, 3172 ha->fw_minor_version, 3173 ha->fw_subminor_version, 3174 fw_major_version, fw_minor_version, 3175 fw_subminor_version); 3176 /* Release MiniDump resources */ 3177 qla82xx_md_free(vha); 3178 /* ALlocate MiniDump resources */ 3179 qla82xx_md_prep(vha); 3180 } 3181 } else 3182 ql_log(ql_log_info, vha, 0xb02e, 3183 "Firmware dump available to retrieve\n"); 3184 } 3185 return rval; 3186 } 3187 3188 3189 int 3190 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3191 { 3192 uint32_t fw_heartbeat_counter; 3193 int status = 0; 3194 3195 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3196 QLA82XX_PEG_ALIVE_COUNTER); 3197 /* all 0xff, assume AER/EEH in progress, ignore */ 3198 if (fw_heartbeat_counter == 0xffffffff) { 3199 ql_dbg(ql_dbg_timer, vha, 0x6003, 3200 "FW heartbeat counter is 0xffffffff, " 3201 "returning status=%d.\n", status); 3202 return status; 3203 } 3204 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3205 vha->seconds_since_last_heartbeat++; 3206 /* FW not alive after 2 seconds */ 3207 if (vha->seconds_since_last_heartbeat == 2) { 3208 vha->seconds_since_last_heartbeat = 0; 3209 status = 1; 3210 } 3211 } else 3212 vha->seconds_since_last_heartbeat = 0; 3213 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3214 if (status) 3215 ql_dbg(ql_dbg_timer, vha, 0x6004, 3216 "Returning status=%d.\n", status); 3217 return status; 3218 } 3219 3220 /* 3221 * qla82xx_device_state_handler 3222 * Main state handler 3223 * 3224 * Note: 3225 * IDC lock must be held upon entry 3226 * 3227 * Return: 3228 * Success : 0 3229 * Failed : 1 3230 */ 3231 int 3232 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3233 { 3234 uint32_t dev_state; 3235 uint32_t old_dev_state; 3236 int rval = QLA_SUCCESS; 3237 unsigned long dev_init_timeout; 3238 struct qla_hw_data *ha = vha->hw; 3239 int loopcount = 0; 3240 3241 qla82xx_idc_lock(ha); 3242 if (!vha->flags.init_done) 3243 qla82xx_set_drv_active(vha); 3244 3245 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3246 old_dev_state = dev_state; 3247 ql_log(ql_log_info, vha, 0x009b, 3248 "Device state is 0x%x = %s.\n", 3249 dev_state, 3250 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3251 3252 /* wait for 30 seconds for device to go ready */ 3253 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3254 3255 while (1) { 3256 3257 if (time_after_eq(jiffies, dev_init_timeout)) { 3258 ql_log(ql_log_fatal, vha, 0x009c, 3259 "Device init failed.\n"); 3260 rval = QLA_FUNCTION_FAILED; 3261 break; 3262 } 3263 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3264 if (old_dev_state != dev_state) { 3265 loopcount = 0; 3266 old_dev_state = dev_state; 3267 } 3268 if (loopcount < 5) { 3269 ql_log(ql_log_info, vha, 0x009d, 3270 "Device state is 0x%x = %s.\n", 3271 dev_state, 3272 dev_state < MAX_STATES ? qdev_state(dev_state) : 3273 "Unknown"); 3274 } 3275 3276 switch (dev_state) { 3277 case QLA82XX_DEV_READY: 3278 ha->flags.isp82xx_reset_owner = 0; 3279 goto exit; 3280 case QLA82XX_DEV_COLD: 3281 rval = qla82xx_device_bootstrap(vha); 3282 break; 3283 case QLA82XX_DEV_INITIALIZING: 3284 qla82xx_idc_unlock(ha); 3285 msleep(1000); 3286 qla82xx_idc_lock(ha); 3287 break; 3288 case QLA82XX_DEV_NEED_RESET: 3289 if (!ql2xdontresethba) 3290 qla82xx_need_reset_handler(vha); 3291 else { 3292 qla82xx_idc_unlock(ha); 3293 msleep(1000); 3294 qla82xx_idc_lock(ha); 3295 } 3296 dev_init_timeout = jiffies + 3297 (ha->nx_dev_init_timeout * HZ); 3298 break; 3299 case QLA82XX_DEV_NEED_QUIESCENT: 3300 qla82xx_need_qsnt_handler(vha); 3301 /* Reset timeout value after quiescence handler */ 3302 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3303 * HZ); 3304 break; 3305 case QLA82XX_DEV_QUIESCENT: 3306 /* Owner will exit and other will wait for the state 3307 * to get changed 3308 */ 3309 if (ha->flags.quiesce_owner) 3310 goto exit; 3311 3312 qla82xx_idc_unlock(ha); 3313 msleep(1000); 3314 qla82xx_idc_lock(ha); 3315 3316 /* Reset timeout value after quiescence handler */ 3317 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3318 * HZ); 3319 break; 3320 case QLA82XX_DEV_FAILED: 3321 qla82xx_dev_failed_handler(vha); 3322 rval = QLA_FUNCTION_FAILED; 3323 goto exit; 3324 default: 3325 qla82xx_idc_unlock(ha); 3326 msleep(1000); 3327 qla82xx_idc_lock(ha); 3328 } 3329 loopcount++; 3330 } 3331 exit: 3332 qla82xx_idc_unlock(ha); 3333 return rval; 3334 } 3335 3336 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3337 { 3338 struct qla_hw_data *ha = vha->hw; 3339 3340 if (ha->flags.mbox_busy) { 3341 ha->flags.mbox_int = 1; 3342 ha->flags.mbox_busy = 0; 3343 ql_log(ql_log_warn, vha, 0x6010, 3344 "Doing premature completion of mbx command.\n"); 3345 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3346 complete(&ha->mbx_intr_comp); 3347 } 3348 } 3349 3350 void qla82xx_watchdog(scsi_qla_host_t *vha) 3351 { 3352 uint32_t dev_state, halt_status; 3353 struct qla_hw_data *ha = vha->hw; 3354 3355 /* don't poll if reset is going on */ 3356 if (!ha->flags.isp82xx_reset_hdlr_active) { 3357 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3358 if (dev_state == QLA82XX_DEV_NEED_RESET && 3359 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3360 ql_log(ql_log_warn, vha, 0x6001, 3361 "Adapter reset needed.\n"); 3362 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3363 qla2xxx_wake_dpc(vha); 3364 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3365 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3366 ql_log(ql_log_warn, vha, 0x6002, 3367 "Quiescent needed.\n"); 3368 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3369 qla2xxx_wake_dpc(vha); 3370 } else { 3371 if (qla82xx_check_fw_alive(vha)) { 3372 ql_dbg(ql_dbg_timer, vha, 0x6011, 3373 "disabling pause transmit on port 0 & 1.\n"); 3374 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3375 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3376 halt_status = qla82xx_rd_32(ha, 3377 QLA82XX_PEG_HALT_STATUS1); 3378 ql_log(ql_log_info, vha, 0x6005, 3379 "dumping hw/fw registers:.\n " 3380 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3381 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3382 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3383 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3384 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3385 qla82xx_rd_32(ha, 3386 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3387 qla82xx_rd_32(ha, 3388 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3389 qla82xx_rd_32(ha, 3390 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3391 qla82xx_rd_32(ha, 3392 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3393 qla82xx_rd_32(ha, 3394 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3395 if (LSW(MSB(halt_status)) == 0x67) 3396 ql_log(ql_log_warn, vha, 0xb052, 3397 "Firmware aborted with " 3398 "error code 0x00006700. Device is " 3399 "being reset.\n"); 3400 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3401 set_bit(ISP_UNRECOVERABLE, 3402 &vha->dpc_flags); 3403 } else { 3404 ql_log(ql_log_info, vha, 0x6006, 3405 "Detect abort needed.\n"); 3406 set_bit(ISP_ABORT_NEEDED, 3407 &vha->dpc_flags); 3408 } 3409 qla2xxx_wake_dpc(vha); 3410 ha->flags.isp82xx_fw_hung = 1; 3411 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3412 qla82xx_clear_pending_mbx(vha); 3413 } 3414 } 3415 } 3416 } 3417 3418 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3419 { 3420 int rval; 3421 rval = qla82xx_device_state_handler(vha); 3422 return rval; 3423 } 3424 3425 void 3426 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3427 { 3428 struct qla_hw_data *ha = vha->hw; 3429 uint32_t dev_state; 3430 3431 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3432 if (dev_state == QLA82XX_DEV_READY) { 3433 ql_log(ql_log_info, vha, 0xb02f, 3434 "HW State: NEED RESET\n"); 3435 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3436 QLA82XX_DEV_NEED_RESET); 3437 ha->flags.isp82xx_reset_owner = 1; 3438 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3439 "reset_owner is 0x%x\n", ha->portnum); 3440 } else 3441 ql_log(ql_log_info, vha, 0xb031, 3442 "Device state is 0x%x = %s.\n", 3443 dev_state, 3444 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3445 } 3446 3447 /* 3448 * qla82xx_abort_isp 3449 * Resets ISP and aborts all outstanding commands. 3450 * 3451 * Input: 3452 * ha = adapter block pointer. 3453 * 3454 * Returns: 3455 * 0 = success 3456 */ 3457 int 3458 qla82xx_abort_isp(scsi_qla_host_t *vha) 3459 { 3460 int rval; 3461 struct qla_hw_data *ha = vha->hw; 3462 3463 if (vha->device_flags & DFLG_DEV_FAILED) { 3464 ql_log(ql_log_warn, vha, 0x8024, 3465 "Device in failed state, exiting.\n"); 3466 return QLA_SUCCESS; 3467 } 3468 ha->flags.isp82xx_reset_hdlr_active = 1; 3469 3470 qla82xx_idc_lock(ha); 3471 qla82xx_set_reset_owner(vha); 3472 qla82xx_idc_unlock(ha); 3473 3474 rval = qla82xx_device_state_handler(vha); 3475 3476 qla82xx_idc_lock(ha); 3477 qla82xx_clear_rst_ready(ha); 3478 qla82xx_idc_unlock(ha); 3479 3480 if (rval == QLA_SUCCESS) { 3481 ha->flags.isp82xx_fw_hung = 0; 3482 ha->flags.isp82xx_reset_hdlr_active = 0; 3483 qla82xx_restart_isp(vha); 3484 } 3485 3486 if (rval) { 3487 vha->flags.online = 1; 3488 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3489 if (ha->isp_abort_cnt == 0) { 3490 ql_log(ql_log_warn, vha, 0x8027, 3491 "ISP error recover failed - board " 3492 "disabled.\n"); 3493 /* 3494 * The next call disables the board 3495 * completely. 3496 */ 3497 ha->isp_ops->reset_adapter(vha); 3498 vha->flags.online = 0; 3499 clear_bit(ISP_ABORT_RETRY, 3500 &vha->dpc_flags); 3501 rval = QLA_SUCCESS; 3502 } else { /* schedule another ISP abort */ 3503 ha->isp_abort_cnt--; 3504 ql_log(ql_log_warn, vha, 0x8036, 3505 "ISP abort - retry remaining %d.\n", 3506 ha->isp_abort_cnt); 3507 rval = QLA_FUNCTION_FAILED; 3508 } 3509 } else { 3510 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3511 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3512 "ISP error recovery - retrying (%d) more times.\n", 3513 ha->isp_abort_cnt); 3514 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3515 rval = QLA_FUNCTION_FAILED; 3516 } 3517 } 3518 return rval; 3519 } 3520 3521 /* 3522 * qla82xx_fcoe_ctx_reset 3523 * Perform a quick reset and aborts all outstanding commands. 3524 * This will only perform an FCoE context reset and avoids a full blown 3525 * chip reset. 3526 * 3527 * Input: 3528 * ha = adapter block pointer. 3529 * is_reset_path = flag for identifying the reset path. 3530 * 3531 * Returns: 3532 * 0 = success 3533 */ 3534 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3535 { 3536 int rval = QLA_FUNCTION_FAILED; 3537 3538 if (vha->flags.online) { 3539 /* Abort all outstanding commands, so as to be requeued later */ 3540 qla2x00_abort_isp_cleanup(vha); 3541 } 3542 3543 /* Stop currently executing firmware. 3544 * This will destroy existing FCoE context at the F/W end. 3545 */ 3546 qla2x00_try_to_stop_firmware(vha); 3547 3548 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3549 rval = qla82xx_restart_isp(vha); 3550 3551 return rval; 3552 } 3553 3554 /* 3555 * qla2x00_wait_for_fcoe_ctx_reset 3556 * Wait till the FCoE context is reset. 3557 * 3558 * Note: 3559 * Does context switching here. 3560 * Release SPIN_LOCK (if any) before calling this routine. 3561 * 3562 * Return: 3563 * Success (fcoe_ctx reset is done) : 0 3564 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3565 */ 3566 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3567 { 3568 int status = QLA_FUNCTION_FAILED; 3569 unsigned long wait_reset; 3570 3571 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3572 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3573 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3574 && time_before(jiffies, wait_reset)) { 3575 3576 set_current_state(TASK_UNINTERRUPTIBLE); 3577 schedule_timeout(HZ); 3578 3579 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3580 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3581 status = QLA_SUCCESS; 3582 break; 3583 } 3584 } 3585 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3586 "%s: status=%d.\n", __func__, status); 3587 3588 return status; 3589 } 3590 3591 void 3592 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3593 { 3594 int i; 3595 unsigned long flags; 3596 struct qla_hw_data *ha = vha->hw; 3597 3598 /* Check if 82XX firmware is alive or not 3599 * We may have arrived here from NEED_RESET 3600 * detection only 3601 */ 3602 if (!ha->flags.isp82xx_fw_hung) { 3603 for (i = 0; i < 2; i++) { 3604 msleep(1000); 3605 if (qla82xx_check_fw_alive(vha)) { 3606 ha->flags.isp82xx_fw_hung = 1; 3607 qla82xx_clear_pending_mbx(vha); 3608 break; 3609 } 3610 } 3611 } 3612 ql_dbg(ql_dbg_init, vha, 0x00b0, 3613 "Entered %s fw_hung=%d.\n", 3614 __func__, ha->flags.isp82xx_fw_hung); 3615 3616 /* Abort all commands gracefully if fw NOT hung */ 3617 if (!ha->flags.isp82xx_fw_hung) { 3618 int cnt, que; 3619 srb_t *sp; 3620 struct req_que *req; 3621 3622 spin_lock_irqsave(&ha->hardware_lock, flags); 3623 for (que = 0; que < ha->max_req_queues; que++) { 3624 req = ha->req_q_map[que]; 3625 if (!req) 3626 continue; 3627 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 3628 sp = req->outstanding_cmds[cnt]; 3629 if (sp) { 3630 if (!sp->ctx || 3631 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3632 spin_unlock_irqrestore( 3633 &ha->hardware_lock, flags); 3634 if (ha->isp_ops->abort_command(sp)) { 3635 ql_log(ql_log_info, vha, 3636 0x00b1, 3637 "mbx abort failed.\n"); 3638 } else { 3639 ql_log(ql_log_info, vha, 3640 0x00b2, 3641 "mbx abort success.\n"); 3642 } 3643 spin_lock_irqsave(&ha->hardware_lock, flags); 3644 } 3645 } 3646 } 3647 } 3648 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3649 3650 /* Wait for pending cmds (physical and virtual) to complete */ 3651 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3652 WAIT_HOST) == QLA_SUCCESS) { 3653 ql_dbg(ql_dbg_init, vha, 0x00b3, 3654 "Done wait for " 3655 "pending commands.\n"); 3656 } 3657 } 3658 } 3659 3660 /* Minidump related functions */ 3661 int 3662 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 3663 { 3664 uint32_t off_value, rval = 0; 3665 3666 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 3667 (off & 0xFFFF0000)); 3668 3669 /* Read back value to make sure write has gone through */ 3670 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 3671 off_value = (off & 0x0000FFFF); 3672 3673 if (flag) 3674 WRT_REG_DWORD((void *) 3675 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 3676 data); 3677 else 3678 rval = RD_REG_DWORD((void *) 3679 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 3680 3681 return rval; 3682 } 3683 3684 static int 3685 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3686 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3687 { 3688 struct qla_hw_data *ha = vha->hw; 3689 struct qla82xx_md_entry_crb *crb_entry; 3690 uint32_t read_value, opcode, poll_time; 3691 uint32_t addr, index, crb_addr; 3692 unsigned long wtime; 3693 struct qla82xx_md_template_hdr *tmplt_hdr; 3694 uint32_t rval = QLA_SUCCESS; 3695 int i; 3696 3697 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3698 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3699 crb_addr = crb_entry->addr; 3700 3701 for (i = 0; i < crb_entry->op_count; i++) { 3702 opcode = crb_entry->crb_ctrl.opcode; 3703 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3704 qla82xx_md_rw_32(ha, crb_addr, 3705 crb_entry->value_1, 1); 3706 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3707 } 3708 3709 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3710 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3711 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3712 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3713 } 3714 3715 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3716 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3717 read_value &= crb_entry->value_2; 3718 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3719 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3720 read_value |= crb_entry->value_3; 3721 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3722 } 3723 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3724 } 3725 3726 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3727 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3728 read_value |= crb_entry->value_3; 3729 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3730 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3731 } 3732 3733 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3734 poll_time = crb_entry->crb_strd.poll_timeout; 3735 wtime = jiffies + poll_time; 3736 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3737 3738 do { 3739 if ((read_value & crb_entry->value_2) 3740 == crb_entry->value_1) 3741 break; 3742 else if (time_after_eq(jiffies, wtime)) { 3743 /* capturing dump failed */ 3744 rval = QLA_FUNCTION_FAILED; 3745 break; 3746 } else 3747 read_value = qla82xx_md_rw_32(ha, 3748 crb_addr, 0, 0); 3749 } while (1); 3750 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3751 } 3752 3753 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3754 if (crb_entry->crb_strd.state_index_a) { 3755 index = crb_entry->crb_strd.state_index_a; 3756 addr = tmplt_hdr->saved_state_array[index]; 3757 } else 3758 addr = crb_addr; 3759 3760 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3761 index = crb_entry->crb_ctrl.state_index_v; 3762 tmplt_hdr->saved_state_array[index] = read_value; 3763 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3764 } 3765 3766 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3767 if (crb_entry->crb_strd.state_index_a) { 3768 index = crb_entry->crb_strd.state_index_a; 3769 addr = tmplt_hdr->saved_state_array[index]; 3770 } else 3771 addr = crb_addr; 3772 3773 if (crb_entry->crb_ctrl.state_index_v) { 3774 index = crb_entry->crb_ctrl.state_index_v; 3775 read_value = 3776 tmplt_hdr->saved_state_array[index]; 3777 } else 3778 read_value = crb_entry->value_1; 3779 3780 qla82xx_md_rw_32(ha, addr, read_value, 1); 3781 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3782 } 3783 3784 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3785 index = crb_entry->crb_ctrl.state_index_v; 3786 read_value = tmplt_hdr->saved_state_array[index]; 3787 read_value <<= crb_entry->crb_ctrl.shl; 3788 read_value >>= crb_entry->crb_ctrl.shr; 3789 if (crb_entry->value_2) 3790 read_value &= crb_entry->value_2; 3791 read_value |= crb_entry->value_3; 3792 read_value += crb_entry->value_1; 3793 tmplt_hdr->saved_state_array[index] = read_value; 3794 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3795 } 3796 crb_addr += crb_entry->crb_strd.addr_stride; 3797 } 3798 return rval; 3799 } 3800 3801 static void 3802 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3803 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3804 { 3805 struct qla_hw_data *ha = vha->hw; 3806 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3807 struct qla82xx_md_entry_rdocm *ocm_hdr; 3808 uint32_t *data_ptr = *d_ptr; 3809 3810 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3811 r_addr = ocm_hdr->read_addr; 3812 r_stride = ocm_hdr->read_addr_stride; 3813 loop_cnt = ocm_hdr->op_count; 3814 3815 for (i = 0; i < loop_cnt; i++) { 3816 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 3817 *data_ptr++ = cpu_to_le32(r_value); 3818 r_addr += r_stride; 3819 } 3820 *d_ptr = data_ptr; 3821 } 3822 3823 static void 3824 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3825 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3826 { 3827 struct qla_hw_data *ha = vha->hw; 3828 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3829 struct qla82xx_md_entry_mux *mux_hdr; 3830 uint32_t *data_ptr = *d_ptr; 3831 3832 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3833 r_addr = mux_hdr->read_addr; 3834 s_addr = mux_hdr->select_addr; 3835 s_stride = mux_hdr->select_value_stride; 3836 s_value = mux_hdr->select_value; 3837 loop_cnt = mux_hdr->op_count; 3838 3839 for (i = 0; i < loop_cnt; i++) { 3840 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3841 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3842 *data_ptr++ = cpu_to_le32(s_value); 3843 *data_ptr++ = cpu_to_le32(r_value); 3844 s_value += s_stride; 3845 } 3846 *d_ptr = data_ptr; 3847 } 3848 3849 static void 3850 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3851 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3852 { 3853 struct qla_hw_data *ha = vha->hw; 3854 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3855 struct qla82xx_md_entry_crb *crb_hdr; 3856 uint32_t *data_ptr = *d_ptr; 3857 3858 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3859 r_addr = crb_hdr->addr; 3860 r_stride = crb_hdr->crb_strd.addr_stride; 3861 loop_cnt = crb_hdr->op_count; 3862 3863 for (i = 0; i < loop_cnt; i++) { 3864 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3865 *data_ptr++ = cpu_to_le32(r_addr); 3866 *data_ptr++ = cpu_to_le32(r_value); 3867 r_addr += r_stride; 3868 } 3869 *d_ptr = data_ptr; 3870 } 3871 3872 static int 3873 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3874 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3875 { 3876 struct qla_hw_data *ha = vha->hw; 3877 uint32_t addr, r_addr, c_addr, t_r_addr; 3878 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3879 unsigned long p_wait, w_time, p_mask; 3880 uint32_t c_value_w, c_value_r; 3881 struct qla82xx_md_entry_cache *cache_hdr; 3882 int rval = QLA_FUNCTION_FAILED; 3883 uint32_t *data_ptr = *d_ptr; 3884 3885 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3886 loop_count = cache_hdr->op_count; 3887 r_addr = cache_hdr->read_addr; 3888 c_addr = cache_hdr->control_addr; 3889 c_value_w = cache_hdr->cache_ctrl.write_value; 3890 3891 t_r_addr = cache_hdr->tag_reg_addr; 3892 t_value = cache_hdr->addr_ctrl.init_tag_value; 3893 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3894 p_wait = cache_hdr->cache_ctrl.poll_wait; 3895 p_mask = cache_hdr->cache_ctrl.poll_mask; 3896 3897 for (i = 0; i < loop_count; i++) { 3898 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3899 if (c_value_w) 3900 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3901 3902 if (p_mask) { 3903 w_time = jiffies + p_wait; 3904 do { 3905 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3906 if ((c_value_r & p_mask) == 0) 3907 break; 3908 else if (time_after_eq(jiffies, w_time)) { 3909 /* capturing dump failed */ 3910 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3911 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3912 "w_time: 0x%lx\n", 3913 c_value_r, p_mask, w_time); 3914 return rval; 3915 } 3916 } while (1); 3917 } 3918 3919 addr = r_addr; 3920 for (k = 0; k < r_cnt; k++) { 3921 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3922 *data_ptr++ = cpu_to_le32(r_value); 3923 addr += cache_hdr->read_ctrl.read_addr_stride; 3924 } 3925 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3926 } 3927 *d_ptr = data_ptr; 3928 return QLA_SUCCESS; 3929 } 3930 3931 static void 3932 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3933 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3934 { 3935 struct qla_hw_data *ha = vha->hw; 3936 uint32_t addr, r_addr, c_addr, t_r_addr; 3937 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3938 uint32_t c_value_w; 3939 struct qla82xx_md_entry_cache *cache_hdr; 3940 uint32_t *data_ptr = *d_ptr; 3941 3942 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3943 loop_count = cache_hdr->op_count; 3944 r_addr = cache_hdr->read_addr; 3945 c_addr = cache_hdr->control_addr; 3946 c_value_w = cache_hdr->cache_ctrl.write_value; 3947 3948 t_r_addr = cache_hdr->tag_reg_addr; 3949 t_value = cache_hdr->addr_ctrl.init_tag_value; 3950 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3951 3952 for (i = 0; i < loop_count; i++) { 3953 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3954 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3955 addr = r_addr; 3956 for (k = 0; k < r_cnt; k++) { 3957 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3958 *data_ptr++ = cpu_to_le32(r_value); 3959 addr += cache_hdr->read_ctrl.read_addr_stride; 3960 } 3961 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3962 } 3963 *d_ptr = data_ptr; 3964 } 3965 3966 static void 3967 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3968 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3969 { 3970 struct qla_hw_data *ha = vha->hw; 3971 uint32_t s_addr, r_addr; 3972 uint32_t r_stride, r_value, r_cnt, qid = 0; 3973 uint32_t i, k, loop_cnt; 3974 struct qla82xx_md_entry_queue *q_hdr; 3975 uint32_t *data_ptr = *d_ptr; 3976 3977 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3978 s_addr = q_hdr->select_addr; 3979 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3980 r_stride = q_hdr->rd_strd.read_addr_stride; 3981 loop_cnt = q_hdr->op_count; 3982 3983 for (i = 0; i < loop_cnt; i++) { 3984 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3985 r_addr = q_hdr->read_addr; 3986 for (k = 0; k < r_cnt; k++) { 3987 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3988 *data_ptr++ = cpu_to_le32(r_value); 3989 r_addr += r_stride; 3990 } 3991 qid += q_hdr->q_strd.queue_id_stride; 3992 } 3993 *d_ptr = data_ptr; 3994 } 3995 3996 static void 3997 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3998 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3999 { 4000 struct qla_hw_data *ha = vha->hw; 4001 uint32_t r_addr, r_value; 4002 uint32_t i, loop_cnt; 4003 struct qla82xx_md_entry_rdrom *rom_hdr; 4004 uint32_t *data_ptr = *d_ptr; 4005 4006 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4007 r_addr = rom_hdr->read_addr; 4008 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4009 4010 for (i = 0; i < loop_cnt; i++) { 4011 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4012 (r_addr & 0xFFFF0000), 1); 4013 r_value = qla82xx_md_rw_32(ha, 4014 MD_DIRECT_ROM_READ_BASE + 4015 (r_addr & 0x0000FFFF), 0, 0); 4016 *data_ptr++ = cpu_to_le32(r_value); 4017 r_addr += sizeof(uint32_t); 4018 } 4019 *d_ptr = data_ptr; 4020 } 4021 4022 static int 4023 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4024 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4025 { 4026 struct qla_hw_data *ha = vha->hw; 4027 uint32_t r_addr, r_value, r_data; 4028 uint32_t i, j, loop_cnt; 4029 struct qla82xx_md_entry_rdmem *m_hdr; 4030 unsigned long flags; 4031 int rval = QLA_FUNCTION_FAILED; 4032 uint32_t *data_ptr = *d_ptr; 4033 4034 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4035 r_addr = m_hdr->read_addr; 4036 loop_cnt = m_hdr->read_data_size/16; 4037 4038 if (r_addr & 0xf) { 4039 ql_log(ql_log_warn, vha, 0xb033, 4040 "Read addr 0x%x not 16 bytes alligned\n", r_addr); 4041 return rval; 4042 } 4043 4044 if (m_hdr->read_data_size % 16) { 4045 ql_log(ql_log_warn, vha, 0xb034, 4046 "Read data[0x%x] not multiple of 16 bytes\n", 4047 m_hdr->read_data_size); 4048 return rval; 4049 } 4050 4051 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4052 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4053 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4054 4055 write_lock_irqsave(&ha->hw_lock, flags); 4056 for (i = 0; i < loop_cnt; i++) { 4057 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4058 r_value = 0; 4059 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4060 r_value = MIU_TA_CTL_ENABLE; 4061 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4062 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4063 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4064 4065 for (j = 0; j < MAX_CTL_CHECK; j++) { 4066 r_value = qla82xx_md_rw_32(ha, 4067 MD_MIU_TEST_AGT_CTRL, 0, 0); 4068 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4069 break; 4070 } 4071 4072 if (j >= MAX_CTL_CHECK) { 4073 printk_ratelimited(KERN_ERR 4074 "failed to read through agent\n"); 4075 write_unlock_irqrestore(&ha->hw_lock, flags); 4076 return rval; 4077 } 4078 4079 for (j = 0; j < 4; j++) { 4080 r_data = qla82xx_md_rw_32(ha, 4081 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4082 *data_ptr++ = cpu_to_le32(r_data); 4083 } 4084 r_addr += 16; 4085 } 4086 write_unlock_irqrestore(&ha->hw_lock, flags); 4087 *d_ptr = data_ptr; 4088 return QLA_SUCCESS; 4089 } 4090 4091 static int 4092 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4093 { 4094 struct qla_hw_data *ha = vha->hw; 4095 uint64_t chksum = 0; 4096 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4097 int count = ha->md_template_size/sizeof(uint32_t); 4098 4099 while (count-- > 0) 4100 chksum += *d_ptr++; 4101 while (chksum >> 32) 4102 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4103 return ~chksum; 4104 } 4105 4106 static void 4107 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4108 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4109 { 4110 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4111 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4112 "Skipping entry[%d]: " 4113 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4114 index, entry_hdr->entry_type, 4115 entry_hdr->d_ctrl.entry_capture_mask); 4116 } 4117 4118 int 4119 qla82xx_md_collect(scsi_qla_host_t *vha) 4120 { 4121 struct qla_hw_data *ha = vha->hw; 4122 int no_entry_hdr = 0; 4123 qla82xx_md_entry_hdr_t *entry_hdr; 4124 struct qla82xx_md_template_hdr *tmplt_hdr; 4125 uint32_t *data_ptr; 4126 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4127 int i = 0, rval = QLA_FUNCTION_FAILED; 4128 4129 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4130 data_ptr = (uint32_t *)ha->md_dump; 4131 4132 if (ha->fw_dumped) { 4133 ql_log(ql_log_info, vha, 0xb037, 4134 "Firmware dump available to retrive\n"); 4135 goto md_failed; 4136 } 4137 4138 ha->fw_dumped = 0; 4139 4140 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4141 ql_log(ql_log_warn, vha, 0xb038, 4142 "Memory not allocated for minidump capture\n"); 4143 goto md_failed; 4144 } 4145 4146 if (qla82xx_validate_template_chksum(vha)) { 4147 ql_log(ql_log_info, vha, 0xb039, 4148 "Template checksum validation error\n"); 4149 goto md_failed; 4150 } 4151 4152 no_entry_hdr = tmplt_hdr->num_of_entries; 4153 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4154 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4155 4156 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4157 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4158 4159 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4160 4161 /* Validate whether required debug level is set */ 4162 if ((f_capture_mask & 0x3) != 0x3) { 4163 ql_log(ql_log_warn, vha, 0xb03c, 4164 "Minimum required capture mask[0x%x] level not set\n", 4165 f_capture_mask); 4166 goto md_failed; 4167 } 4168 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4169 4170 tmplt_hdr->driver_info[0] = vha->host_no; 4171 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4172 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4173 QLA_DRIVER_BETA_VER; 4174 4175 total_data_size = ha->md_dump_size; 4176 4177 ql_dbg(ql_log_info, vha, 0xb03d, 4178 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4179 4180 /* Check whether template obtained is valid */ 4181 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4182 ql_log(ql_log_warn, vha, 0xb04e, 4183 "Bad template header entry type: 0x%x obtained\n", 4184 tmplt_hdr->entry_type); 4185 goto md_failed; 4186 } 4187 4188 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4189 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4190 4191 /* Walk through the entry headers */ 4192 for (i = 0; i < no_entry_hdr; i++) { 4193 4194 if (data_collected > total_data_size) { 4195 ql_log(ql_log_warn, vha, 0xb03e, 4196 "More MiniDump data collected: [0x%x]\n", 4197 data_collected); 4198 goto md_failed; 4199 } 4200 4201 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4202 ql2xmdcapmask)) { 4203 entry_hdr->d_ctrl.driver_flags |= 4204 QLA82XX_DBG_SKIPPED_FLAG; 4205 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4206 "Skipping entry[%d]: " 4207 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4208 i, entry_hdr->entry_type, 4209 entry_hdr->d_ctrl.entry_capture_mask); 4210 goto skip_nxt_entry; 4211 } 4212 4213 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4214 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4215 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4216 __func__, i, data_ptr, entry_hdr, 4217 entry_hdr->entry_type, 4218 entry_hdr->d_ctrl.entry_capture_mask); 4219 4220 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4221 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4222 data_collected, (ha->md_dump_size - data_collected)); 4223 4224 /* Decode the entry type and take 4225 * required action to capture debug data */ 4226 switch (entry_hdr->entry_type) { 4227 case QLA82XX_RDEND: 4228 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4229 break; 4230 case QLA82XX_CNTRL: 4231 rval = qla82xx_minidump_process_control(vha, 4232 entry_hdr, &data_ptr); 4233 if (rval != QLA_SUCCESS) { 4234 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4235 goto md_failed; 4236 } 4237 break; 4238 case QLA82XX_RDCRB: 4239 qla82xx_minidump_process_rdcrb(vha, 4240 entry_hdr, &data_ptr); 4241 break; 4242 case QLA82XX_RDMEM: 4243 rval = qla82xx_minidump_process_rdmem(vha, 4244 entry_hdr, &data_ptr); 4245 if (rval != QLA_SUCCESS) { 4246 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4247 goto md_failed; 4248 } 4249 break; 4250 case QLA82XX_BOARD: 4251 case QLA82XX_RDROM: 4252 qla82xx_minidump_process_rdrom(vha, 4253 entry_hdr, &data_ptr); 4254 break; 4255 case QLA82XX_L2DTG: 4256 case QLA82XX_L2ITG: 4257 case QLA82XX_L2DAT: 4258 case QLA82XX_L2INS: 4259 rval = qla82xx_minidump_process_l2tag(vha, 4260 entry_hdr, &data_ptr); 4261 if (rval != QLA_SUCCESS) { 4262 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4263 goto md_failed; 4264 } 4265 break; 4266 case QLA82XX_L1DAT: 4267 case QLA82XX_L1INS: 4268 qla82xx_minidump_process_l1cache(vha, 4269 entry_hdr, &data_ptr); 4270 break; 4271 case QLA82XX_RDOCM: 4272 qla82xx_minidump_process_rdocm(vha, 4273 entry_hdr, &data_ptr); 4274 break; 4275 case QLA82XX_RDMUX: 4276 qla82xx_minidump_process_rdmux(vha, 4277 entry_hdr, &data_ptr); 4278 break; 4279 case QLA82XX_QUEUE: 4280 qla82xx_minidump_process_queue(vha, 4281 entry_hdr, &data_ptr); 4282 break; 4283 case QLA82XX_RDNOP: 4284 default: 4285 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4286 break; 4287 } 4288 4289 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4290 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4291 4292 data_collected = (uint8_t *)data_ptr - 4293 (uint8_t *)ha->md_dump; 4294 skip_nxt_entry: 4295 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4296 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4297 } 4298 4299 if (data_collected != total_data_size) { 4300 ql_dbg(ql_log_warn, vha, 0xb043, 4301 "MiniDump data mismatch: Data collected: [0x%x]," 4302 "total_data_size:[0x%x]\n", 4303 data_collected, total_data_size); 4304 goto md_failed; 4305 } 4306 4307 ql_log(ql_log_info, vha, 0xb044, 4308 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4309 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4310 ha->fw_dumped = 1; 4311 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4312 4313 md_failed: 4314 return rval; 4315 } 4316 4317 int 4318 qla82xx_md_alloc(scsi_qla_host_t *vha) 4319 { 4320 struct qla_hw_data *ha = vha->hw; 4321 int i, k; 4322 struct qla82xx_md_template_hdr *tmplt_hdr; 4323 4324 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4325 4326 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4327 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4328 ql_log(ql_log_info, vha, 0xb045, 4329 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4330 ql2xmdcapmask); 4331 } 4332 4333 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4334 if (i & ql2xmdcapmask) 4335 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4336 } 4337 4338 if (ha->md_dump) { 4339 ql_log(ql_log_warn, vha, 0xb046, 4340 "Firmware dump previously allocated.\n"); 4341 return 1; 4342 } 4343 4344 ha->md_dump = vmalloc(ha->md_dump_size); 4345 if (ha->md_dump == NULL) { 4346 ql_log(ql_log_warn, vha, 0xb047, 4347 "Unable to allocate memory for Minidump size " 4348 "(0x%x).\n", ha->md_dump_size); 4349 return 1; 4350 } 4351 return 0; 4352 } 4353 4354 void 4355 qla82xx_md_free(scsi_qla_host_t *vha) 4356 { 4357 struct qla_hw_data *ha = vha->hw; 4358 4359 /* Release the template header allocated */ 4360 if (ha->md_tmplt_hdr) { 4361 ql_log(ql_log_info, vha, 0xb048, 4362 "Free MiniDump template: %p, size (%d KB)\n", 4363 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4364 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4365 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4366 ha->md_tmplt_hdr = 0; 4367 } 4368 4369 /* Release the template data buffer allocated */ 4370 if (ha->md_dump) { 4371 ql_log(ql_log_info, vha, 0xb049, 4372 "Free MiniDump memory: %p, size (%d KB)\n", 4373 ha->md_dump, ha->md_dump_size / 1024); 4374 vfree(ha->md_dump); 4375 ha->md_dump_size = 0; 4376 ha->md_dump = 0; 4377 } 4378 } 4379 4380 void 4381 qla82xx_md_prep(scsi_qla_host_t *vha) 4382 { 4383 struct qla_hw_data *ha = vha->hw; 4384 int rval; 4385 4386 /* Get Minidump template size */ 4387 rval = qla82xx_md_get_template_size(vha); 4388 if (rval == QLA_SUCCESS) { 4389 ql_log(ql_log_info, vha, 0xb04a, 4390 "MiniDump Template size obtained (%d KB)\n", 4391 ha->md_template_size / 1024); 4392 4393 /* Get Minidump template */ 4394 rval = qla82xx_md_get_template(vha); 4395 if (rval == QLA_SUCCESS) { 4396 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4397 "MiniDump Template obtained\n"); 4398 4399 /* Allocate memory for minidump */ 4400 rval = qla82xx_md_alloc(vha); 4401 if (rval == QLA_SUCCESS) 4402 ql_log(ql_log_info, vha, 0xb04c, 4403 "MiniDump memory allocated (%d KB)\n", 4404 ha->md_dump_size / 1024); 4405 else { 4406 ql_log(ql_log_info, vha, 0xb04d, 4407 "Free MiniDump template: %p, size: (%d KB)\n", 4408 ha->md_tmplt_hdr, 4409 ha->md_template_size / 1024); 4410 dma_free_coherent(&ha->pdev->dev, 4411 ha->md_template_size, 4412 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4413 ha->md_tmplt_hdr = 0; 4414 } 4415 4416 } 4417 } 4418 } 4419 4420 int 4421 qla82xx_beacon_on(struct scsi_qla_host *vha) 4422 { 4423 4424 int rval; 4425 struct qla_hw_data *ha = vha->hw; 4426 qla82xx_idc_lock(ha); 4427 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4428 4429 if (rval) { 4430 ql_log(ql_log_warn, vha, 0xb050, 4431 "mbx set led config failed in %s\n", __func__); 4432 goto exit; 4433 } 4434 ha->beacon_blink_led = 1; 4435 exit: 4436 qla82xx_idc_unlock(ha); 4437 return rval; 4438 } 4439 4440 int 4441 qla82xx_beacon_off(struct scsi_qla_host *vha) 4442 { 4443 4444 int rval; 4445 struct qla_hw_data *ha = vha->hw; 4446 qla82xx_idc_lock(ha); 4447 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4448 4449 if (rval) { 4450 ql_log(ql_log_warn, vha, 0xb051, 4451 "mbx set led config failed in %s\n", __func__); 4452 goto exit; 4453 } 4454 ha->beacon_blink_led = 0; 4455 exit: 4456 qla82xx_idc_unlock(ha); 4457 return rval; 4458 } 4459