1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 static void qla82xx_crb_addr_transform_setup(void) 46 { 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103 } 104 105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260 }; 261 262 /* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265 static unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330 }; 331 332 /* Device states */ 333 static char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342 }; 343 344 char *qdev_state(uint32_t dev_state) 345 { 346 return q_dev_state[dev_state]; 347 } 348 349 /* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356 { 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void __iomem *) 368 (CRB_WINDOW_2M + ha->nx_pcibase)); 369 if (win_read != ha->crb_win) { 370 ql_dbg(ql_dbg_p3p, vha, 0xb000, 371 "%s: Written crbwin (0x%x) " 372 "!= Read crbwin (0x%x), off=0x%lx.\n", 373 __func__, ha->crb_win, win_read, *off); 374 } 375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376 } 377 378 static inline unsigned long 379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380 { 381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382 /* See if we are currently pointing to the region we want to use next */ 383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384 /* No need to change window. PCIX and PCIEregs are in both 385 * regs are in both windows. 386 */ 387 return off; 388 } 389 390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391 /* We are in first CRB window */ 392 if (ha->curr_window != 0) 393 WARN_ON(1); 394 return off; 395 } 396 397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398 /* We are in second CRB window */ 399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400 401 if (ha->curr_window != 1) 402 return off; 403 404 /* We are in the QM or direct access 405 * register region - do nothing 406 */ 407 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408 (off < QLA82XX_PCI_CAMQM_MAX)) 409 return off; 410 } 411 /* strange address given */ 412 ql_dbg(ql_dbg_p3p, vha, 0xb001, 413 "%s: Warning: unm_nic_pci_set_crbwindow " 414 "called with an unknown address(%llx).\n", 415 QLA2XXX_DRIVER_NAME, off); 416 return off; 417 } 418 419 static int 420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 421 { 422 struct crb_128M_2M_sub_block_map *m; 423 424 if (*off >= QLA82XX_CRB_MAX) 425 return -1; 426 427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 428 *off = (*off - QLA82XX_PCI_CAMQM) + 429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 430 return 0; 431 } 432 433 if (*off < QLA82XX_PCI_CRBSPACE) 434 return -1; 435 436 *off -= QLA82XX_PCI_CRBSPACE; 437 438 /* Try direct map */ 439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 440 441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 443 return 0; 444 } 445 /* Not in direct map, use crb window */ 446 return 1; 447 } 448 449 #define CRB_WIN_LOCK_TIMEOUT 100000000 450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 451 { 452 int done = 0, timeout = 0; 453 454 while (!done) { 455 /* acquire semaphore3 from PCI HW block */ 456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 457 if (done == 1) 458 break; 459 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 460 return -1; 461 timeout++; 462 } 463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 464 return 0; 465 } 466 467 int 468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469 { 470 unsigned long flags = 0; 471 int rv; 472 473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474 475 BUG_ON(rv == -1); 476 477 if (rv == 1) { 478 write_lock_irqsave(&ha->hw_lock, flags); 479 qla82xx_crb_win_lock(ha); 480 qla82xx_pci_set_crbwindow_2M(ha, &off); 481 } 482 483 writel(data, (void __iomem *)off); 484 485 if (rv == 1) { 486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487 write_unlock_irqrestore(&ha->hw_lock, flags); 488 } 489 return 0; 490 } 491 492 int 493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494 { 495 unsigned long flags = 0; 496 int rv; 497 u32 data; 498 499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500 501 BUG_ON(rv == -1); 502 503 if (rv == 1) { 504 write_lock_irqsave(&ha->hw_lock, flags); 505 qla82xx_crb_win_lock(ha); 506 qla82xx_pci_set_crbwindow_2M(ha, &off); 507 } 508 data = RD_REG_DWORD((void __iomem *)off); 509 510 if (rv == 1) { 511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512 write_unlock_irqrestore(&ha->hw_lock, flags); 513 } 514 return data; 515 } 516 517 #define IDC_LOCK_TIMEOUT 100000000 518 int qla82xx_idc_lock(struct qla_hw_data *ha) 519 { 520 int i; 521 int done = 0, timeout = 0; 522 523 while (!done) { 524 /* acquire semaphore5 from PCI HW block */ 525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526 if (done == 1) 527 break; 528 if (timeout >= IDC_LOCK_TIMEOUT) 529 return -1; 530 531 timeout++; 532 533 /* Yield CPU */ 534 if (!in_interrupt()) 535 schedule(); 536 else { 537 for (i = 0; i < 20; i++) 538 cpu_relax(); 539 } 540 } 541 542 return 0; 543 } 544 545 void qla82xx_idc_unlock(struct qla_hw_data *ha) 546 { 547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548 } 549 550 /* PCI Windowing for DDR regions. */ 551 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 552 (((addr) <= (high)) && ((addr) >= (low))) 553 /* 554 * check memory access boundary. 555 * used by test agent. support ddr access only for now 556 */ 557 static unsigned long 558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 559 unsigned long long addr, int size) 560 { 561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 562 QLA82XX_ADDR_DDR_NET_MAX) || 563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 564 QLA82XX_ADDR_DDR_NET_MAX) || 565 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 566 return 0; 567 else 568 return 1; 569 } 570 571 static int qla82xx_pci_set_window_warning_count; 572 573 static unsigned long 574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 575 { 576 int window; 577 u32 win_read; 578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 579 580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 581 QLA82XX_ADDR_DDR_NET_MAX)) { 582 /* DDR network side */ 583 window = MN_WIN(addr); 584 ha->ddr_mn_window = window; 585 qla82xx_wr_32(ha, 586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 587 win_read = qla82xx_rd_32(ha, 588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 589 if ((win_read << 17) != window) { 590 ql_dbg(ql_dbg_p3p, vha, 0xb003, 591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 592 __func__, window, win_read); 593 } 594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 596 QLA82XX_ADDR_OCM0_MAX)) { 597 unsigned int temp1; 598 if ((addr & 0x00ff800) == 0xff800) { 599 ql_log(ql_log_warn, vha, 0xb004, 600 "%s: QM access not handled.\n", __func__); 601 addr = -1UL; 602 } 603 window = OCM_WIN(addr); 604 ha->ddr_mn_window = window; 605 qla82xx_wr_32(ha, 606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 607 win_read = qla82xx_rd_32(ha, 608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 609 temp1 = ((window & 0x1FF) << 7) | 610 ((window & 0x0FFFE0000) >> 17); 611 if (win_read != temp1) { 612 ql_log(ql_log_warn, vha, 0xb005, 613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 614 __func__, temp1, win_read); 615 } 616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 617 618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 619 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 620 /* QDR network side */ 621 window = MS_WIN(addr); 622 ha->qdr_sn_window = window; 623 qla82xx_wr_32(ha, 624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 625 win_read = qla82xx_rd_32(ha, 626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 627 if (win_read != window) { 628 ql_log(ql_log_warn, vha, 0xb006, 629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 630 __func__, window, win_read); 631 } 632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 633 } else { 634 /* 635 * peg gdb frequently accesses memory that doesn't exist, 636 * this limits the chit chat so debugging isn't slowed down. 637 */ 638 if ((qla82xx_pci_set_window_warning_count++ < 8) || 639 (qla82xx_pci_set_window_warning_count%64 == 0)) { 640 ql_log(ql_log_warn, vha, 0xb007, 641 "%s: Warning:%s Unknown address range!.\n", 642 __func__, QLA2XXX_DRIVER_NAME); 643 } 644 addr = -1UL; 645 } 646 return addr; 647 } 648 649 /* check if address is in the same windows as the previous access */ 650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 651 unsigned long long addr) 652 { 653 int window; 654 unsigned long long qdr_max; 655 656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 657 658 /* DDR network side */ 659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 660 QLA82XX_ADDR_DDR_NET_MAX)) 661 BUG(); 662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 663 QLA82XX_ADDR_OCM0_MAX)) 664 return 1; 665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 666 QLA82XX_ADDR_OCM1_MAX)) 667 return 1; 668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 669 /* QDR network side */ 670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 671 if (ha->qdr_sn_window == window) 672 return 1; 673 } 674 return 0; 675 } 676 677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 678 u64 off, void *data, int size) 679 { 680 unsigned long flags; 681 void __iomem *addr = NULL; 682 int ret = 0; 683 u64 start; 684 uint8_t __iomem *mem_ptr = NULL; 685 unsigned long mem_base; 686 unsigned long mem_page; 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 688 689 write_lock_irqsave(&ha->hw_lock, flags); 690 691 /* 692 * If attempting to access unknown address or straddle hw windows, 693 * do not access. 694 */ 695 start = qla82xx_pci_set_window(ha, off); 696 if ((start == -1UL) || 697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 698 write_unlock_irqrestore(&ha->hw_lock, flags); 699 ql_log(ql_log_fatal, vha, 0xb008, 700 "%s out of bound pci memory " 701 "access, offset is 0x%llx.\n", 702 QLA2XXX_DRIVER_NAME, off); 703 return -1; 704 } 705 706 write_unlock_irqrestore(&ha->hw_lock, flags); 707 mem_base = pci_resource_start(ha->pdev, 0); 708 mem_page = start & PAGE_MASK; 709 /* Map two pages whenever user tries to access addresses in two 710 * consecutive pages. 711 */ 712 if (mem_page != ((start + size - 1) & PAGE_MASK)) 713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 714 else 715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 716 if (mem_ptr == NULL) { 717 *(u8 *)data = 0; 718 return -1; 719 } 720 addr = mem_ptr; 721 addr += start & (PAGE_SIZE - 1); 722 write_lock_irqsave(&ha->hw_lock, flags); 723 724 switch (size) { 725 case 1: 726 *(u8 *)data = readb(addr); 727 break; 728 case 2: 729 *(u16 *)data = readw(addr); 730 break; 731 case 4: 732 *(u32 *)data = readl(addr); 733 break; 734 case 8: 735 *(u64 *)data = readq(addr); 736 break; 737 default: 738 ret = -1; 739 break; 740 } 741 write_unlock_irqrestore(&ha->hw_lock, flags); 742 743 if (mem_ptr) 744 iounmap(mem_ptr); 745 return ret; 746 } 747 748 static int 749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 750 u64 off, void *data, int size) 751 { 752 unsigned long flags; 753 void __iomem *addr = NULL; 754 int ret = 0; 755 u64 start; 756 uint8_t __iomem *mem_ptr = NULL; 757 unsigned long mem_base; 758 unsigned long mem_page; 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 760 761 write_lock_irqsave(&ha->hw_lock, flags); 762 763 /* 764 * If attempting to access unknown address or straddle hw windows, 765 * do not access. 766 */ 767 start = qla82xx_pci_set_window(ha, off); 768 if ((start == -1UL) || 769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 770 write_unlock_irqrestore(&ha->hw_lock, flags); 771 ql_log(ql_log_fatal, vha, 0xb009, 772 "%s out of bount memory " 773 "access, offset is 0x%llx.\n", 774 QLA2XXX_DRIVER_NAME, off); 775 return -1; 776 } 777 778 write_unlock_irqrestore(&ha->hw_lock, flags); 779 mem_base = pci_resource_start(ha->pdev, 0); 780 mem_page = start & PAGE_MASK; 781 /* Map two pages whenever user tries to access addresses in two 782 * consecutive pages. 783 */ 784 if (mem_page != ((start + size - 1) & PAGE_MASK)) 785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 786 else 787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 788 if (mem_ptr == NULL) 789 return -1; 790 791 addr = mem_ptr; 792 addr += start & (PAGE_SIZE - 1); 793 write_lock_irqsave(&ha->hw_lock, flags); 794 795 switch (size) { 796 case 1: 797 writeb(*(u8 *)data, addr); 798 break; 799 case 2: 800 writew(*(u16 *)data, addr); 801 break; 802 case 4: 803 writel(*(u32 *)data, addr); 804 break; 805 case 8: 806 writeq(*(u64 *)data, addr); 807 break; 808 default: 809 ret = -1; 810 break; 811 } 812 write_unlock_irqrestore(&ha->hw_lock, flags); 813 if (mem_ptr) 814 iounmap(mem_ptr); 815 return ret; 816 } 817 818 #define MTU_FUDGE_FACTOR 100 819 static unsigned long 820 qla82xx_decode_crb_addr(unsigned long addr) 821 { 822 int i; 823 unsigned long base_addr, offset, pci_base; 824 825 if (!qla82xx_crb_table_initialized) 826 qla82xx_crb_addr_transform_setup(); 827 828 pci_base = ADDR_ERROR; 829 base_addr = addr & 0xfff00000; 830 offset = addr & 0x000fffff; 831 832 for (i = 0; i < MAX_CRB_XFORM; i++) { 833 if (crb_addr_xform[i] == base_addr) { 834 pci_base = i << 20; 835 break; 836 } 837 } 838 if (pci_base == ADDR_ERROR) 839 return pci_base; 840 return pci_base + offset; 841 } 842 843 static long rom_max_timeout = 100; 844 static long qla82xx_rom_lock_timeout = 100; 845 846 static int 847 qla82xx_rom_lock(struct qla_hw_data *ha) 848 { 849 int done = 0, timeout = 0; 850 uint32_t lock_owner = 0; 851 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 852 853 while (!done) { 854 /* acquire semaphore2 from PCI HW block */ 855 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 856 if (done == 1) 857 break; 858 if (timeout >= qla82xx_rom_lock_timeout) { 859 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 860 ql_dbg(ql_dbg_p3p, vha, 0xb085, 861 "Failed to acquire rom lock, acquired by %d.\n", 862 lock_owner); 863 return -1; 864 } 865 timeout++; 866 } 867 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 868 return 0; 869 } 870 871 static void 872 qla82xx_rom_unlock(struct qla_hw_data *ha) 873 { 874 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 875 } 876 877 static int 878 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 879 { 880 long timeout = 0; 881 long done = 0 ; 882 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 883 884 while (done == 0) { 885 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 886 done &= 4; 887 timeout++; 888 if (timeout >= rom_max_timeout) { 889 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 890 "%s: Timeout reached waiting for rom busy.\n", 891 QLA2XXX_DRIVER_NAME); 892 return -1; 893 } 894 } 895 return 0; 896 } 897 898 static int 899 qla82xx_wait_rom_done(struct qla_hw_data *ha) 900 { 901 long timeout = 0; 902 long done = 0 ; 903 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 904 905 while (done == 0) { 906 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 907 done &= 2; 908 timeout++; 909 if (timeout >= rom_max_timeout) { 910 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 911 "%s: Timeout reached waiting for rom done.\n", 912 QLA2XXX_DRIVER_NAME); 913 return -1; 914 } 915 } 916 return 0; 917 } 918 919 static int 920 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 921 { 922 uint32_t off_value, rval = 0; 923 924 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 925 (off & 0xFFFF0000)); 926 927 /* Read back value to make sure write has gone through */ 928 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 929 off_value = (off & 0x0000FFFF); 930 931 if (flag) 932 WRT_REG_DWORD((void __iomem *) 933 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 934 data); 935 else 936 rval = RD_REG_DWORD((void __iomem *) 937 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 938 939 return rval; 940 } 941 942 static int 943 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 944 { 945 /* Dword reads to flash. */ 946 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 947 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 948 (addr & 0x0000FFFF), 0, 0); 949 950 return 0; 951 } 952 953 static int 954 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 955 { 956 int ret, loops = 0; 957 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 958 959 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 960 udelay(100); 961 schedule(); 962 loops++; 963 } 964 if (loops >= 50000) { 965 ql_log(ql_log_fatal, vha, 0x00b9, 966 "Failed to acquire SEM2 lock.\n"); 967 return -1; 968 } 969 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 970 qla82xx_rom_unlock(ha); 971 return ret; 972 } 973 974 static int 975 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 976 { 977 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 978 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 979 qla82xx_wait_rom_busy(ha); 980 if (qla82xx_wait_rom_done(ha)) { 981 ql_log(ql_log_warn, vha, 0xb00c, 982 "Error waiting for rom done.\n"); 983 return -1; 984 } 985 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 986 return 0; 987 } 988 989 static int 990 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 991 { 992 long timeout = 0; 993 uint32_t done = 1 ; 994 uint32_t val; 995 int ret = 0; 996 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 997 998 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 999 while ((done != 0) && (ret == 0)) { 1000 ret = qla82xx_read_status_reg(ha, &val); 1001 done = val & 1; 1002 timeout++; 1003 udelay(10); 1004 cond_resched(); 1005 if (timeout >= 50000) { 1006 ql_log(ql_log_warn, vha, 0xb00d, 1007 "Timeout reached waiting for write finish.\n"); 1008 return -1; 1009 } 1010 } 1011 return ret; 1012 } 1013 1014 static int 1015 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1016 { 1017 uint32_t val; 1018 qla82xx_wait_rom_busy(ha); 1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1021 qla82xx_wait_rom_busy(ha); 1022 if (qla82xx_wait_rom_done(ha)) 1023 return -1; 1024 if (qla82xx_read_status_reg(ha, &val) != 0) 1025 return -1; 1026 if ((val & 2) != 2) 1027 return -1; 1028 return 0; 1029 } 1030 1031 static int 1032 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1033 { 1034 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1035 if (qla82xx_flash_set_write_enable(ha)) 1036 return -1; 1037 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1038 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1039 if (qla82xx_wait_rom_done(ha)) { 1040 ql_log(ql_log_warn, vha, 0xb00e, 1041 "Error waiting for rom done.\n"); 1042 return -1; 1043 } 1044 return qla82xx_flash_wait_write_finish(ha); 1045 } 1046 1047 static int 1048 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1049 { 1050 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1051 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1052 if (qla82xx_wait_rom_done(ha)) { 1053 ql_log(ql_log_warn, vha, 0xb00f, 1054 "Error waiting for rom done.\n"); 1055 return -1; 1056 } 1057 return 0; 1058 } 1059 1060 static int 1061 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1062 { 1063 int loops = 0; 1064 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1065 1066 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1067 udelay(100); 1068 cond_resched(); 1069 loops++; 1070 } 1071 if (loops >= 50000) { 1072 ql_log(ql_log_warn, vha, 0xb010, 1073 "ROM lock failed.\n"); 1074 return -1; 1075 } 1076 return 0; 1077 } 1078 1079 static int 1080 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1081 uint32_t data) 1082 { 1083 int ret = 0; 1084 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1085 1086 ret = ql82xx_rom_lock_d(ha); 1087 if (ret < 0) { 1088 ql_log(ql_log_warn, vha, 0xb011, 1089 "ROM lock failed.\n"); 1090 return ret; 1091 } 1092 1093 if (qla82xx_flash_set_write_enable(ha)) 1094 goto done_write; 1095 1096 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1097 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1098 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1099 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1100 qla82xx_wait_rom_busy(ha); 1101 if (qla82xx_wait_rom_done(ha)) { 1102 ql_log(ql_log_warn, vha, 0xb012, 1103 "Error waiting for rom done.\n"); 1104 ret = -1; 1105 goto done_write; 1106 } 1107 1108 ret = qla82xx_flash_wait_write_finish(ha); 1109 1110 done_write: 1111 qla82xx_rom_unlock(ha); 1112 return ret; 1113 } 1114 1115 /* This routine does CRB initialize sequence 1116 * to put the ISP into operational state 1117 */ 1118 static int 1119 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1120 { 1121 int addr, val; 1122 int i ; 1123 struct crb_addr_pair *buf; 1124 unsigned long off; 1125 unsigned offset, n; 1126 struct qla_hw_data *ha = vha->hw; 1127 1128 struct crb_addr_pair { 1129 long addr; 1130 long data; 1131 }; 1132 1133 /* Halt all the individual PEGs and other blocks of the ISP */ 1134 qla82xx_rom_lock(ha); 1135 1136 /* disable all I2Q */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1138 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1139 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1140 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1142 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1143 1144 /* disable all niu interrupts */ 1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1146 /* disable xge rx/tx */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1148 /* disable xg1 rx/tx */ 1149 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1150 /* disable sideband mac */ 1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1152 /* disable ap0 mac */ 1153 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1154 /* disable ap1 mac */ 1155 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1156 1157 /* halt sre */ 1158 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1160 1161 /* halt epg */ 1162 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1163 1164 /* halt timers */ 1165 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1166 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1167 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1168 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1169 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1170 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1171 1172 /* halt pegs */ 1173 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1174 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1175 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1176 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1177 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1178 msleep(20); 1179 1180 /* big hammer */ 1181 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1182 /* don't reset CAM block on reset */ 1183 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1184 else 1185 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1186 qla82xx_rom_unlock(ha); 1187 1188 /* Read the signature value from the flash. 1189 * Offset 0: Contain signature (0xcafecafe) 1190 * Offset 4: Offset and number of addr/value pairs 1191 * that present in CRB initialize sequence 1192 */ 1193 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1194 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1195 ql_log(ql_log_fatal, vha, 0x006e, 1196 "Error Reading crb_init area: n: %08x.\n", n); 1197 return -1; 1198 } 1199 1200 /* Offset in flash = lower 16 bits 1201 * Number of entries = upper 16 bits 1202 */ 1203 offset = n & 0xffffU; 1204 n = (n >> 16) & 0xffffU; 1205 1206 /* number of addr/value pair should not exceed 1024 entries */ 1207 if (n >= 1024) { 1208 ql_log(ql_log_fatal, vha, 0x0071, 1209 "Card flash not initialized:n=0x%x.\n", n); 1210 return -1; 1211 } 1212 1213 ql_log(ql_log_info, vha, 0x0072, 1214 "%d CRB init values found in ROM.\n", n); 1215 1216 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1217 if (buf == NULL) { 1218 ql_log(ql_log_fatal, vha, 0x010c, 1219 "Unable to allocate memory.\n"); 1220 return -1; 1221 } 1222 1223 for (i = 0; i < n; i++) { 1224 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1225 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1226 kfree(buf); 1227 return -1; 1228 } 1229 1230 buf[i].addr = addr; 1231 buf[i].data = val; 1232 } 1233 1234 for (i = 0; i < n; i++) { 1235 /* Translate internal CRB initialization 1236 * address to PCI bus address 1237 */ 1238 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1239 QLA82XX_PCI_CRBSPACE; 1240 /* Not all CRB addr/value pair to be written, 1241 * some of them are skipped 1242 */ 1243 1244 /* skipping cold reboot MAGIC */ 1245 if (off == QLA82XX_CAM_RAM(0x1fc)) 1246 continue; 1247 1248 /* do not reset PCI */ 1249 if (off == (ROMUSB_GLB + 0xbc)) 1250 continue; 1251 1252 /* skip core clock, so that firmware can increase the clock */ 1253 if (off == (ROMUSB_GLB + 0xc8)) 1254 continue; 1255 1256 /* skip the function enable register */ 1257 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1258 continue; 1259 1260 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1261 continue; 1262 1263 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1264 continue; 1265 1266 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1267 continue; 1268 1269 if (off == ADDR_ERROR) { 1270 ql_log(ql_log_fatal, vha, 0x0116, 1271 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1272 continue; 1273 } 1274 1275 qla82xx_wr_32(ha, off, buf[i].data); 1276 1277 /* ISP requires much bigger delay to settle down, 1278 * else crb_window returns 0xffffffff 1279 */ 1280 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1281 msleep(1000); 1282 1283 /* ISP requires millisec delay between 1284 * successive CRB register updation 1285 */ 1286 msleep(1); 1287 } 1288 1289 kfree(buf); 1290 1291 /* Resetting the data and instruction cache */ 1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1295 1296 /* Clear all protocol processing engines */ 1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1301 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1302 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1305 return 0; 1306 } 1307 1308 static int 1309 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1310 u64 off, void *data, int size) 1311 { 1312 int i, j, ret = 0, loop, sz[2], off0; 1313 int scale, shift_amount, startword; 1314 uint32_t temp; 1315 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1316 1317 /* 1318 * If not MN, go check for MS or invalid. 1319 */ 1320 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1321 mem_crb = QLA82XX_CRB_QDR_NET; 1322 else { 1323 mem_crb = QLA82XX_CRB_DDR_NET; 1324 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1325 return qla82xx_pci_mem_write_direct(ha, 1326 off, data, size); 1327 } 1328 1329 off0 = off & 0x7; 1330 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1331 sz[1] = size - sz[0]; 1332 1333 off8 = off & 0xfffffff0; 1334 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1335 shift_amount = 4; 1336 scale = 2; 1337 startword = (off & 0xf)/8; 1338 1339 for (i = 0; i < loop; i++) { 1340 if (qla82xx_pci_mem_read_2M(ha, off8 + 1341 (i << shift_amount), &word[i * scale], 8)) 1342 return -1; 1343 } 1344 1345 switch (size) { 1346 case 1: 1347 tmpw = *((uint8_t *)data); 1348 break; 1349 case 2: 1350 tmpw = *((uint16_t *)data); 1351 break; 1352 case 4: 1353 tmpw = *((uint32_t *)data); 1354 break; 1355 case 8: 1356 default: 1357 tmpw = *((uint64_t *)data); 1358 break; 1359 } 1360 1361 if (sz[0] == 8) { 1362 word[startword] = tmpw; 1363 } else { 1364 word[startword] &= 1365 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1366 word[startword] |= tmpw << (off0 * 8); 1367 } 1368 if (sz[1] != 0) { 1369 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1370 word[startword+1] |= tmpw >> (sz[0] * 8); 1371 } 1372 1373 for (i = 0; i < loop; i++) { 1374 temp = off8 + (i << shift_amount); 1375 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1376 temp = 0; 1377 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1378 temp = word[i * scale] & 0xffffffff; 1379 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1380 temp = (word[i * scale] >> 32) & 0xffffffff; 1381 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1382 temp = word[i*scale + 1] & 0xffffffff; 1383 qla82xx_wr_32(ha, mem_crb + 1384 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1385 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1386 qla82xx_wr_32(ha, mem_crb + 1387 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1388 1389 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1390 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1391 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1392 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1393 1394 for (j = 0; j < MAX_CTL_CHECK; j++) { 1395 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1396 if ((temp & MIU_TA_CTL_BUSY) == 0) 1397 break; 1398 } 1399 1400 if (j >= MAX_CTL_CHECK) { 1401 if (printk_ratelimit()) 1402 dev_err(&ha->pdev->dev, 1403 "failed to write through agent.\n"); 1404 ret = -1; 1405 break; 1406 } 1407 } 1408 1409 return ret; 1410 } 1411 1412 static int 1413 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1414 { 1415 int i; 1416 long size = 0; 1417 long flashaddr = ha->flt_region_bootload << 2; 1418 long memaddr = BOOTLD_START; 1419 u64 data; 1420 u32 high, low; 1421 size = (IMAGE_START - BOOTLD_START) / 8; 1422 1423 for (i = 0; i < size; i++) { 1424 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1425 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1426 return -1; 1427 } 1428 data = ((u64)high << 32) | low ; 1429 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1430 flashaddr += 8; 1431 memaddr += 8; 1432 1433 if (i % 0x1000 == 0) 1434 msleep(1); 1435 } 1436 udelay(100); 1437 read_lock(&ha->hw_lock); 1438 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1439 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1440 read_unlock(&ha->hw_lock); 1441 return 0; 1442 } 1443 1444 int 1445 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1446 u64 off, void *data, int size) 1447 { 1448 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1449 int shift_amount; 1450 uint32_t temp; 1451 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1452 1453 /* 1454 * If not MN, go check for MS or invalid. 1455 */ 1456 1457 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1458 mem_crb = QLA82XX_CRB_QDR_NET; 1459 else { 1460 mem_crb = QLA82XX_CRB_DDR_NET; 1461 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1462 return qla82xx_pci_mem_read_direct(ha, 1463 off, data, size); 1464 } 1465 1466 off8 = off & 0xfffffff0; 1467 off0[0] = off & 0xf; 1468 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1469 shift_amount = 4; 1470 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1471 off0[1] = 0; 1472 sz[1] = size - sz[0]; 1473 1474 for (i = 0; i < loop; i++) { 1475 temp = off8 + (i << shift_amount); 1476 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1477 temp = 0; 1478 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1479 temp = MIU_TA_CTL_ENABLE; 1480 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1481 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1482 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1483 1484 for (j = 0; j < MAX_CTL_CHECK; j++) { 1485 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1486 if ((temp & MIU_TA_CTL_BUSY) == 0) 1487 break; 1488 } 1489 1490 if (j >= MAX_CTL_CHECK) { 1491 if (printk_ratelimit()) 1492 dev_err(&ha->pdev->dev, 1493 "failed to read through agent.\n"); 1494 break; 1495 } 1496 1497 start = off0[i] >> 2; 1498 end = (off0[i] + sz[i] - 1) >> 2; 1499 for (k = start; k <= end; k++) { 1500 temp = qla82xx_rd_32(ha, 1501 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1502 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1503 } 1504 } 1505 1506 if (j >= MAX_CTL_CHECK) 1507 return -1; 1508 1509 if ((off0[0] & 7) == 0) { 1510 val = word[0]; 1511 } else { 1512 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1513 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1514 } 1515 1516 switch (size) { 1517 case 1: 1518 *(uint8_t *)data = val; 1519 break; 1520 case 2: 1521 *(uint16_t *)data = val; 1522 break; 1523 case 4: 1524 *(uint32_t *)data = val; 1525 break; 1526 case 8: 1527 *(uint64_t *)data = val; 1528 break; 1529 } 1530 return 0; 1531 } 1532 1533 1534 static struct qla82xx_uri_table_desc * 1535 qla82xx_get_table_desc(const u8 *unirom, int section) 1536 { 1537 uint32_t i; 1538 struct qla82xx_uri_table_desc *directory = 1539 (struct qla82xx_uri_table_desc *)&unirom[0]; 1540 __le32 offset; 1541 __le32 tab_type; 1542 __le32 entries = cpu_to_le32(directory->num_entries); 1543 1544 for (i = 0; i < entries; i++) { 1545 offset = cpu_to_le32(directory->findex) + 1546 (i * cpu_to_le32(directory->entry_size)); 1547 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1548 1549 if (tab_type == section) 1550 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1551 } 1552 1553 return NULL; 1554 } 1555 1556 static struct qla82xx_uri_data_desc * 1557 qla82xx_get_data_desc(struct qla_hw_data *ha, 1558 u32 section, u32 idx_offset) 1559 { 1560 const u8 *unirom = ha->hablob->fw->data; 1561 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1562 struct qla82xx_uri_table_desc *tab_desc = NULL; 1563 __le32 offset; 1564 1565 tab_desc = qla82xx_get_table_desc(unirom, section); 1566 if (!tab_desc) 1567 return NULL; 1568 1569 offset = cpu_to_le32(tab_desc->findex) + 1570 (cpu_to_le32(tab_desc->entry_size) * idx); 1571 1572 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1573 } 1574 1575 static u8 * 1576 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1577 { 1578 u32 offset = BOOTLD_START; 1579 struct qla82xx_uri_data_desc *uri_desc = NULL; 1580 1581 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1582 uri_desc = qla82xx_get_data_desc(ha, 1583 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1584 if (uri_desc) 1585 offset = cpu_to_le32(uri_desc->findex); 1586 } 1587 1588 return (u8 *)&ha->hablob->fw->data[offset]; 1589 } 1590 1591 static __le32 1592 qla82xx_get_fw_size(struct qla_hw_data *ha) 1593 { 1594 struct qla82xx_uri_data_desc *uri_desc = NULL; 1595 1596 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1597 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1598 QLA82XX_URI_FIRMWARE_IDX_OFF); 1599 if (uri_desc) 1600 return cpu_to_le32(uri_desc->size); 1601 } 1602 1603 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1604 } 1605 1606 static u8 * 1607 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1608 { 1609 u32 offset = IMAGE_START; 1610 struct qla82xx_uri_data_desc *uri_desc = NULL; 1611 1612 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1613 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1614 QLA82XX_URI_FIRMWARE_IDX_OFF); 1615 if (uri_desc) 1616 offset = cpu_to_le32(uri_desc->findex); 1617 } 1618 1619 return (u8 *)&ha->hablob->fw->data[offset]; 1620 } 1621 1622 /* PCI related functions */ 1623 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1624 { 1625 unsigned long val = 0; 1626 u32 control; 1627 1628 switch (region) { 1629 case 0: 1630 val = 0; 1631 break; 1632 case 1: 1633 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1634 val = control + QLA82XX_MSIX_TBL_SPACE; 1635 break; 1636 } 1637 return val; 1638 } 1639 1640 1641 int 1642 qla82xx_iospace_config(struct qla_hw_data *ha) 1643 { 1644 uint32_t len = 0; 1645 1646 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1648 "Failed to reserver selected regions.\n"); 1649 goto iospace_error_exit; 1650 } 1651 1652 /* Use MMIO operations for all accesses. */ 1653 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1654 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1655 "Region #0 not an MMIO resource, aborting.\n"); 1656 goto iospace_error_exit; 1657 } 1658 1659 len = pci_resource_len(ha->pdev, 0); 1660 ha->nx_pcibase = 1661 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1662 if (!ha->nx_pcibase) { 1663 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1664 "Cannot remap pcibase MMIO, aborting.\n"); 1665 goto iospace_error_exit; 1666 } 1667 1668 /* Mapping of IO base pointer */ 1669 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1670 0xbc000 + (ha->pdev->devfn << 11)); 1671 1672 if (!ql2xdbwr) { 1673 ha->nxdb_wr_ptr = 1674 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1675 (ha->pdev->devfn << 12)), 4); 1676 if (!ha->nxdb_wr_ptr) { 1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1678 "Cannot remap MMIO, aborting.\n"); 1679 goto iospace_error_exit; 1680 } 1681 1682 /* Mapping of IO base pointer, 1683 * door bell read and write pointer 1684 */ 1685 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1686 (ha->pdev->devfn * 8); 1687 } else { 1688 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1689 QLA82XX_CAMRAM_DB1 : 1690 QLA82XX_CAMRAM_DB2); 1691 } 1692 1693 ha->max_req_queues = ha->max_rsp_queues = 1; 1694 ha->msix_count = ha->max_rsp_queues + 1; 1695 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1696 "nx_pci_base=%p iobase=%p " 1697 "max_req_queues=%d msix_count=%d.\n", 1698 (void *)ha->nx_pcibase, ha->iobase, 1699 ha->max_req_queues, ha->msix_count); 1700 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1701 "nx_pci_base=%p iobase=%p " 1702 "max_req_queues=%d msix_count=%d.\n", 1703 (void *)ha->nx_pcibase, ha->iobase, 1704 ha->max_req_queues, ha->msix_count); 1705 return 0; 1706 1707 iospace_error_exit: 1708 return -ENOMEM; 1709 } 1710 1711 /* GS related functions */ 1712 1713 /* Initialization related functions */ 1714 1715 /** 1716 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1717 * @ha: HA context 1718 * 1719 * Returns 0 on success. 1720 */ 1721 int 1722 qla82xx_pci_config(scsi_qla_host_t *vha) 1723 { 1724 struct qla_hw_data *ha = vha->hw; 1725 int ret; 1726 1727 pci_set_master(ha->pdev); 1728 ret = pci_set_mwi(ha->pdev); 1729 ha->chip_revision = ha->pdev->revision; 1730 ql_dbg(ql_dbg_init, vha, 0x0043, 1731 "Chip revision:%d.\n", 1732 ha->chip_revision); 1733 return 0; 1734 } 1735 1736 /** 1737 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1738 * @ha: HA context 1739 * 1740 * Returns 0 on success. 1741 */ 1742 void 1743 qla82xx_reset_chip(scsi_qla_host_t *vha) 1744 { 1745 struct qla_hw_data *ha = vha->hw; 1746 ha->isp_ops->disable_intrs(ha); 1747 } 1748 1749 void qla82xx_config_rings(struct scsi_qla_host *vha) 1750 { 1751 struct qla_hw_data *ha = vha->hw; 1752 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1753 struct init_cb_81xx *icb; 1754 struct req_que *req = ha->req_q_map[0]; 1755 struct rsp_que *rsp = ha->rsp_q_map[0]; 1756 1757 /* Setup ring parameters in initialization control block. */ 1758 icb = (struct init_cb_81xx *)ha->init_cb; 1759 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1760 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1761 icb->request_q_length = cpu_to_le16(req->length); 1762 icb->response_q_length = cpu_to_le16(rsp->length); 1763 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1764 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1765 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1766 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1767 1768 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1769 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1770 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1771 } 1772 1773 static int 1774 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1775 { 1776 u64 *ptr64; 1777 u32 i, flashaddr, size; 1778 __le64 data; 1779 1780 size = (IMAGE_START - BOOTLD_START) / 8; 1781 1782 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1783 flashaddr = BOOTLD_START; 1784 1785 for (i = 0; i < size; i++) { 1786 data = cpu_to_le64(ptr64[i]); 1787 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1788 return -EIO; 1789 flashaddr += 8; 1790 } 1791 1792 flashaddr = FLASH_ADDR_START; 1793 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1794 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1795 1796 for (i = 0; i < size; i++) { 1797 data = cpu_to_le64(ptr64[i]); 1798 1799 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1800 return -EIO; 1801 flashaddr += 8; 1802 } 1803 udelay(100); 1804 1805 /* Write a magic value to CAMRAM register 1806 * at a specified offset to indicate 1807 * that all data is written and 1808 * ready for firmware to initialize. 1809 */ 1810 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1811 1812 read_lock(&ha->hw_lock); 1813 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1814 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1815 read_unlock(&ha->hw_lock); 1816 return 0; 1817 } 1818 1819 static int 1820 qla82xx_set_product_offset(struct qla_hw_data *ha) 1821 { 1822 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1823 const uint8_t *unirom = ha->hablob->fw->data; 1824 uint32_t i; 1825 __le32 entries; 1826 __le32 flags, file_chiprev, offset; 1827 uint8_t chiprev = ha->chip_revision; 1828 /* Hardcoding mn_present flag for P3P */ 1829 int mn_present = 0; 1830 uint32_t flagbit; 1831 1832 ptab_desc = qla82xx_get_table_desc(unirom, 1833 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1834 if (!ptab_desc) 1835 return -1; 1836 1837 entries = cpu_to_le32(ptab_desc->num_entries); 1838 1839 for (i = 0; i < entries; i++) { 1840 offset = cpu_to_le32(ptab_desc->findex) + 1841 (i * cpu_to_le32(ptab_desc->entry_size)); 1842 flags = cpu_to_le32(*((int *)&unirom[offset] + 1843 QLA82XX_URI_FLAGS_OFF)); 1844 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1845 QLA82XX_URI_CHIP_REV_OFF)); 1846 1847 flagbit = mn_present ? 1 : 2; 1848 1849 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1850 ha->file_prd_off = offset; 1851 return 0; 1852 } 1853 } 1854 return -1; 1855 } 1856 1857 static int 1858 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1859 { 1860 __le32 val; 1861 uint32_t min_size; 1862 struct qla_hw_data *ha = vha->hw; 1863 const struct firmware *fw = ha->hablob->fw; 1864 1865 ha->fw_type = fw_type; 1866 1867 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1868 if (qla82xx_set_product_offset(ha)) 1869 return -EINVAL; 1870 1871 min_size = QLA82XX_URI_FW_MIN_SIZE; 1872 } else { 1873 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1874 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1875 return -EINVAL; 1876 1877 min_size = QLA82XX_FW_MIN_SIZE; 1878 } 1879 1880 if (fw->size < min_size) 1881 return -EINVAL; 1882 return 0; 1883 } 1884 1885 static int 1886 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1887 { 1888 u32 val = 0; 1889 int retries = 60; 1890 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1891 1892 do { 1893 read_lock(&ha->hw_lock); 1894 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1895 read_unlock(&ha->hw_lock); 1896 1897 switch (val) { 1898 case PHAN_INITIALIZE_COMPLETE: 1899 case PHAN_INITIALIZE_ACK: 1900 return QLA_SUCCESS; 1901 case PHAN_INITIALIZE_FAILED: 1902 break; 1903 default: 1904 break; 1905 } 1906 ql_log(ql_log_info, vha, 0x00a8, 1907 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1908 val, retries); 1909 1910 msleep(500); 1911 1912 } while (--retries); 1913 1914 ql_log(ql_log_fatal, vha, 0x00a9, 1915 "Cmd Peg initialization failed: 0x%x.\n", val); 1916 1917 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1918 read_lock(&ha->hw_lock); 1919 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1920 read_unlock(&ha->hw_lock); 1921 return QLA_FUNCTION_FAILED; 1922 } 1923 1924 static int 1925 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1926 { 1927 u32 val = 0; 1928 int retries = 60; 1929 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1930 1931 do { 1932 read_lock(&ha->hw_lock); 1933 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1934 read_unlock(&ha->hw_lock); 1935 1936 switch (val) { 1937 case PHAN_INITIALIZE_COMPLETE: 1938 case PHAN_INITIALIZE_ACK: 1939 return QLA_SUCCESS; 1940 case PHAN_INITIALIZE_FAILED: 1941 break; 1942 default: 1943 break; 1944 } 1945 ql_log(ql_log_info, vha, 0x00ab, 1946 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1947 val, retries); 1948 1949 msleep(500); 1950 1951 } while (--retries); 1952 1953 ql_log(ql_log_fatal, vha, 0x00ac, 1954 "Rcv Peg initializatin failed: 0x%x.\n", val); 1955 read_lock(&ha->hw_lock); 1956 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1957 read_unlock(&ha->hw_lock); 1958 return QLA_FUNCTION_FAILED; 1959 } 1960 1961 /* ISR related functions */ 1962 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1963 QLA82XX_LEGACY_INTR_CONFIG; 1964 1965 /* 1966 * qla82xx_mbx_completion() - Process mailbox command completions. 1967 * @ha: SCSI driver HA context 1968 * @mb0: Mailbox0 register 1969 */ 1970 static void 1971 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1972 { 1973 uint16_t cnt; 1974 uint16_t __iomem *wptr; 1975 struct qla_hw_data *ha = vha->hw; 1976 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1977 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1978 1979 /* Load return mailbox registers. */ 1980 ha->flags.mbox_int = 1; 1981 ha->mailbox_out[0] = mb0; 1982 1983 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1984 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1985 wptr++; 1986 } 1987 1988 if (!ha->mcp) 1989 ql_dbg(ql_dbg_async, vha, 0x5053, 1990 "MBX pointer ERROR.\n"); 1991 } 1992 1993 /* 1994 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1995 * @irq: 1996 * @dev_id: SCSI driver HA context 1997 * @regs: 1998 * 1999 * Called by system whenever the host adapter generates an interrupt. 2000 * 2001 * Returns handled flag. 2002 */ 2003 irqreturn_t 2004 qla82xx_intr_handler(int irq, void *dev_id) 2005 { 2006 scsi_qla_host_t *vha; 2007 struct qla_hw_data *ha; 2008 struct rsp_que *rsp; 2009 struct device_reg_82xx __iomem *reg; 2010 int status = 0, status1 = 0; 2011 unsigned long flags; 2012 unsigned long iter; 2013 uint32_t stat = 0; 2014 uint16_t mb[4]; 2015 2016 rsp = (struct rsp_que *) dev_id; 2017 if (!rsp) { 2018 ql_log(ql_log_info, NULL, 0xb053, 2019 "%s: NULL response queue pointer.\n", __func__); 2020 return IRQ_NONE; 2021 } 2022 ha = rsp->hw; 2023 2024 if (!ha->flags.msi_enabled) { 2025 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2026 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2027 return IRQ_NONE; 2028 2029 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2030 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2031 return IRQ_NONE; 2032 } 2033 2034 /* clear the interrupt */ 2035 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2036 2037 /* read twice to ensure write is flushed */ 2038 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2039 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2040 2041 reg = &ha->iobase->isp82; 2042 2043 spin_lock_irqsave(&ha->hardware_lock, flags); 2044 vha = pci_get_drvdata(ha->pdev); 2045 for (iter = 1; iter--; ) { 2046 2047 if (RD_REG_DWORD(®->host_int)) { 2048 stat = RD_REG_DWORD(®->host_status); 2049 2050 switch (stat & 0xff) { 2051 case 0x1: 2052 case 0x2: 2053 case 0x10: 2054 case 0x11: 2055 qla82xx_mbx_completion(vha, MSW(stat)); 2056 status |= MBX_INTERRUPT; 2057 break; 2058 case 0x12: 2059 mb[0] = MSW(stat); 2060 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2061 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2062 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2063 qla2x00_async_event(vha, rsp, mb); 2064 break; 2065 case 0x13: 2066 qla24xx_process_response_queue(vha, rsp); 2067 break; 2068 default: 2069 ql_dbg(ql_dbg_async, vha, 0x5054, 2070 "Unrecognized interrupt type (%d).\n", 2071 stat & 0xff); 2072 break; 2073 } 2074 } 2075 WRT_REG_DWORD(®->host_int, 0); 2076 } 2077 2078 #ifdef QL_DEBUG_LEVEL_17 2079 if (!irq && ha->flags.eeh_busy) 2080 ql_log(ql_log_warn, vha, 0x503d, 2081 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2082 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2083 #endif 2084 2085 qla2x00_handle_mbx_completion(ha, status); 2086 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2087 2088 if (!ha->flags.msi_enabled) 2089 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2090 2091 return IRQ_HANDLED; 2092 } 2093 2094 irqreturn_t 2095 qla82xx_msix_default(int irq, void *dev_id) 2096 { 2097 scsi_qla_host_t *vha; 2098 struct qla_hw_data *ha; 2099 struct rsp_que *rsp; 2100 struct device_reg_82xx __iomem *reg; 2101 int status = 0; 2102 unsigned long flags; 2103 uint32_t stat = 0; 2104 uint16_t mb[4]; 2105 2106 rsp = (struct rsp_que *) dev_id; 2107 if (!rsp) { 2108 printk(KERN_INFO 2109 "%s(): NULL response queue pointer.\n", __func__); 2110 return IRQ_NONE; 2111 } 2112 ha = rsp->hw; 2113 2114 reg = &ha->iobase->isp82; 2115 2116 spin_lock_irqsave(&ha->hardware_lock, flags); 2117 vha = pci_get_drvdata(ha->pdev); 2118 do { 2119 if (RD_REG_DWORD(®->host_int)) { 2120 stat = RD_REG_DWORD(®->host_status); 2121 2122 switch (stat & 0xff) { 2123 case 0x1: 2124 case 0x2: 2125 case 0x10: 2126 case 0x11: 2127 qla82xx_mbx_completion(vha, MSW(stat)); 2128 status |= MBX_INTERRUPT; 2129 break; 2130 case 0x12: 2131 mb[0] = MSW(stat); 2132 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2133 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2134 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2135 qla2x00_async_event(vha, rsp, mb); 2136 break; 2137 case 0x13: 2138 qla24xx_process_response_queue(vha, rsp); 2139 break; 2140 default: 2141 ql_dbg(ql_dbg_async, vha, 0x5041, 2142 "Unrecognized interrupt type (%d).\n", 2143 stat & 0xff); 2144 break; 2145 } 2146 } 2147 WRT_REG_DWORD(®->host_int, 0); 2148 } while (0); 2149 2150 #ifdef QL_DEBUG_LEVEL_17 2151 if (!irq && ha->flags.eeh_busy) 2152 ql_log(ql_log_warn, vha, 0x5044, 2153 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2154 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2155 #endif 2156 2157 qla2x00_handle_mbx_completion(ha, status); 2158 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2159 2160 return IRQ_HANDLED; 2161 } 2162 2163 irqreturn_t 2164 qla82xx_msix_rsp_q(int irq, void *dev_id) 2165 { 2166 scsi_qla_host_t *vha; 2167 struct qla_hw_data *ha; 2168 struct rsp_que *rsp; 2169 struct device_reg_82xx __iomem *reg; 2170 unsigned long flags; 2171 2172 rsp = (struct rsp_que *) dev_id; 2173 if (!rsp) { 2174 printk(KERN_INFO 2175 "%s(): NULL response queue pointer.\n", __func__); 2176 return IRQ_NONE; 2177 } 2178 2179 ha = rsp->hw; 2180 reg = &ha->iobase->isp82; 2181 spin_lock_irqsave(&ha->hardware_lock, flags); 2182 vha = pci_get_drvdata(ha->pdev); 2183 qla24xx_process_response_queue(vha, rsp); 2184 WRT_REG_DWORD(®->host_int, 0); 2185 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2186 return IRQ_HANDLED; 2187 } 2188 2189 void 2190 qla82xx_poll(int irq, void *dev_id) 2191 { 2192 scsi_qla_host_t *vha; 2193 struct qla_hw_data *ha; 2194 struct rsp_que *rsp; 2195 struct device_reg_82xx __iomem *reg; 2196 int status = 0; 2197 uint32_t stat; 2198 uint16_t mb[4]; 2199 unsigned long flags; 2200 2201 rsp = (struct rsp_que *) dev_id; 2202 if (!rsp) { 2203 printk(KERN_INFO 2204 "%s(): NULL response queue pointer.\n", __func__); 2205 return; 2206 } 2207 ha = rsp->hw; 2208 2209 reg = &ha->iobase->isp82; 2210 spin_lock_irqsave(&ha->hardware_lock, flags); 2211 vha = pci_get_drvdata(ha->pdev); 2212 2213 if (RD_REG_DWORD(®->host_int)) { 2214 stat = RD_REG_DWORD(®->host_status); 2215 switch (stat & 0xff) { 2216 case 0x1: 2217 case 0x2: 2218 case 0x10: 2219 case 0x11: 2220 qla82xx_mbx_completion(vha, MSW(stat)); 2221 status |= MBX_INTERRUPT; 2222 break; 2223 case 0x12: 2224 mb[0] = MSW(stat); 2225 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2226 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2227 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2228 qla2x00_async_event(vha, rsp, mb); 2229 break; 2230 case 0x13: 2231 qla24xx_process_response_queue(vha, rsp); 2232 break; 2233 default: 2234 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2235 "Unrecognized interrupt type (%d).\n", 2236 stat * 0xff); 2237 break; 2238 } 2239 } 2240 WRT_REG_DWORD(®->host_int, 0); 2241 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2242 } 2243 2244 void 2245 qla82xx_enable_intrs(struct qla_hw_data *ha) 2246 { 2247 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2248 qla82xx_mbx_intr_enable(vha); 2249 spin_lock_irq(&ha->hardware_lock); 2250 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2251 spin_unlock_irq(&ha->hardware_lock); 2252 ha->interrupts_on = 1; 2253 } 2254 2255 void 2256 qla82xx_disable_intrs(struct qla_hw_data *ha) 2257 { 2258 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2259 qla82xx_mbx_intr_disable(vha); 2260 spin_lock_irq(&ha->hardware_lock); 2261 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2262 spin_unlock_irq(&ha->hardware_lock); 2263 ha->interrupts_on = 0; 2264 } 2265 2266 void qla82xx_init_flags(struct qla_hw_data *ha) 2267 { 2268 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2269 2270 /* ISP 8021 initializations */ 2271 rwlock_init(&ha->hw_lock); 2272 ha->qdr_sn_window = -1; 2273 ha->ddr_mn_window = -1; 2274 ha->curr_window = 255; 2275 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2276 nx_legacy_intr = &legacy_intr[ha->portnum]; 2277 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2278 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2279 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2280 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2281 } 2282 2283 inline void 2284 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2285 { 2286 int idc_ver; 2287 uint32_t drv_active; 2288 struct qla_hw_data *ha = vha->hw; 2289 2290 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2291 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2292 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2293 QLA82XX_IDC_VERSION); 2294 ql_log(ql_log_info, vha, 0xb082, 2295 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2296 } else { 2297 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2298 if (idc_ver != QLA82XX_IDC_VERSION) 2299 ql_log(ql_log_info, vha, 0xb083, 2300 "qla2xxx driver IDC version %d is not compatible " 2301 "with IDC version %d of the other drivers\n", 2302 QLA82XX_IDC_VERSION, idc_ver); 2303 } 2304 } 2305 2306 inline void 2307 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2308 { 2309 uint32_t drv_active; 2310 struct qla_hw_data *ha = vha->hw; 2311 2312 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2313 2314 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2315 if (drv_active == 0xffffffff) { 2316 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2317 QLA82XX_DRV_NOT_ACTIVE); 2318 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2319 } 2320 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2321 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2322 } 2323 2324 inline void 2325 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2326 { 2327 uint32_t drv_active; 2328 2329 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2330 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2331 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2332 } 2333 2334 static inline int 2335 qla82xx_need_reset(struct qla_hw_data *ha) 2336 { 2337 uint32_t drv_state; 2338 int rval; 2339 2340 if (ha->flags.nic_core_reset_owner) 2341 return 1; 2342 else { 2343 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2344 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2345 return rval; 2346 } 2347 } 2348 2349 static inline void 2350 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2351 { 2352 uint32_t drv_state; 2353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2354 2355 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2356 2357 /* If reset value is all FF's, initialize DRV_STATE */ 2358 if (drv_state == 0xffffffff) { 2359 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2360 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2361 } 2362 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2363 ql_dbg(ql_dbg_init, vha, 0x00bb, 2364 "drv_state = 0x%08x.\n", drv_state); 2365 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2366 } 2367 2368 static inline void 2369 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2370 { 2371 uint32_t drv_state; 2372 2373 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2374 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2375 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2376 } 2377 2378 static inline void 2379 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2380 { 2381 uint32_t qsnt_state; 2382 2383 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2384 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2385 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2386 } 2387 2388 void 2389 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2390 { 2391 struct qla_hw_data *ha = vha->hw; 2392 uint32_t qsnt_state; 2393 2394 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2395 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2396 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2397 } 2398 2399 static int 2400 qla82xx_load_fw(scsi_qla_host_t *vha) 2401 { 2402 int rst; 2403 struct fw_blob *blob; 2404 struct qla_hw_data *ha = vha->hw; 2405 2406 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2407 ql_log(ql_log_fatal, vha, 0x009f, 2408 "Error during CRB initialization.\n"); 2409 return QLA_FUNCTION_FAILED; 2410 } 2411 udelay(500); 2412 2413 /* Bring QM and CAMRAM out of reset */ 2414 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2415 rst &= ~((1 << 28) | (1 << 24)); 2416 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2417 2418 /* 2419 * FW Load priority: 2420 * 1) Operational firmware residing in flash. 2421 * 2) Firmware via request-firmware interface (.bin file). 2422 */ 2423 if (ql2xfwloadbin == 2) 2424 goto try_blob_fw; 2425 2426 ql_log(ql_log_info, vha, 0x00a0, 2427 "Attempting to load firmware from flash.\n"); 2428 2429 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2430 ql_log(ql_log_info, vha, 0x00a1, 2431 "Firmware loaded successfully from flash.\n"); 2432 return QLA_SUCCESS; 2433 } else { 2434 ql_log(ql_log_warn, vha, 0x0108, 2435 "Firmware load from flash failed.\n"); 2436 } 2437 2438 try_blob_fw: 2439 ql_log(ql_log_info, vha, 0x00a2, 2440 "Attempting to load firmware from blob.\n"); 2441 2442 /* Load firmware blob. */ 2443 blob = ha->hablob = qla2x00_request_firmware(vha); 2444 if (!blob) { 2445 ql_log(ql_log_fatal, vha, 0x00a3, 2446 "Firmware image not present.\n"); 2447 goto fw_load_failed; 2448 } 2449 2450 /* Validating firmware blob */ 2451 if (qla82xx_validate_firmware_blob(vha, 2452 QLA82XX_FLASH_ROMIMAGE)) { 2453 /* Fallback to URI format */ 2454 if (qla82xx_validate_firmware_blob(vha, 2455 QLA82XX_UNIFIED_ROMIMAGE)) { 2456 ql_log(ql_log_fatal, vha, 0x00a4, 2457 "No valid firmware image found.\n"); 2458 return QLA_FUNCTION_FAILED; 2459 } 2460 } 2461 2462 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2463 ql_log(ql_log_info, vha, 0x00a5, 2464 "Firmware loaded successfully from binary blob.\n"); 2465 return QLA_SUCCESS; 2466 } else { 2467 ql_log(ql_log_fatal, vha, 0x00a6, 2468 "Firmware load failed for binary blob.\n"); 2469 blob->fw = NULL; 2470 blob = NULL; 2471 goto fw_load_failed; 2472 } 2473 return QLA_SUCCESS; 2474 2475 fw_load_failed: 2476 return QLA_FUNCTION_FAILED; 2477 } 2478 2479 int 2480 qla82xx_start_firmware(scsi_qla_host_t *vha) 2481 { 2482 uint16_t lnk; 2483 struct qla_hw_data *ha = vha->hw; 2484 2485 /* scrub dma mask expansion register */ 2486 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2487 2488 /* Put both the PEG CMD and RCV PEG to default state 2489 * of 0 before resetting the hardware 2490 */ 2491 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2492 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2493 2494 /* Overwrite stale initialization register values */ 2495 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2496 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2497 2498 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2499 ql_log(ql_log_fatal, vha, 0x00a7, 2500 "Error trying to start fw.\n"); 2501 return QLA_FUNCTION_FAILED; 2502 } 2503 2504 /* Handshake with the card before we register the devices. */ 2505 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2506 ql_log(ql_log_fatal, vha, 0x00aa, 2507 "Error during card handshake.\n"); 2508 return QLA_FUNCTION_FAILED; 2509 } 2510 2511 /* Negotiated Link width */ 2512 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2513 ha->link_width = (lnk >> 4) & 0x3f; 2514 2515 /* Synchronize with Receive peg */ 2516 return qla82xx_check_rcvpeg_state(ha); 2517 } 2518 2519 static uint32_t * 2520 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2521 uint32_t length) 2522 { 2523 uint32_t i; 2524 uint32_t val; 2525 struct qla_hw_data *ha = vha->hw; 2526 2527 /* Dword reads to flash. */ 2528 for (i = 0; i < length/4; i++, faddr += 4) { 2529 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2530 ql_log(ql_log_warn, vha, 0x0106, 2531 "Do ROM fast read failed.\n"); 2532 goto done_read; 2533 } 2534 dwptr[i] = __constant_cpu_to_le32(val); 2535 } 2536 done_read: 2537 return dwptr; 2538 } 2539 2540 static int 2541 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2542 { 2543 int ret; 2544 uint32_t val; 2545 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2546 2547 ret = ql82xx_rom_lock_d(ha); 2548 if (ret < 0) { 2549 ql_log(ql_log_warn, vha, 0xb014, 2550 "ROM Lock failed.\n"); 2551 return ret; 2552 } 2553 2554 ret = qla82xx_read_status_reg(ha, &val); 2555 if (ret < 0) 2556 goto done_unprotect; 2557 2558 val &= ~(BLOCK_PROTECT_BITS << 2); 2559 ret = qla82xx_write_status_reg(ha, val); 2560 if (ret < 0) { 2561 val |= (BLOCK_PROTECT_BITS << 2); 2562 qla82xx_write_status_reg(ha, val); 2563 } 2564 2565 if (qla82xx_write_disable_flash(ha) != 0) 2566 ql_log(ql_log_warn, vha, 0xb015, 2567 "Write disable failed.\n"); 2568 2569 done_unprotect: 2570 qla82xx_rom_unlock(ha); 2571 return ret; 2572 } 2573 2574 static int 2575 qla82xx_protect_flash(struct qla_hw_data *ha) 2576 { 2577 int ret; 2578 uint32_t val; 2579 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2580 2581 ret = ql82xx_rom_lock_d(ha); 2582 if (ret < 0) { 2583 ql_log(ql_log_warn, vha, 0xb016, 2584 "ROM Lock failed.\n"); 2585 return ret; 2586 } 2587 2588 ret = qla82xx_read_status_reg(ha, &val); 2589 if (ret < 0) 2590 goto done_protect; 2591 2592 val |= (BLOCK_PROTECT_BITS << 2); 2593 /* LOCK all sectors */ 2594 ret = qla82xx_write_status_reg(ha, val); 2595 if (ret < 0) 2596 ql_log(ql_log_warn, vha, 0xb017, 2597 "Write status register failed.\n"); 2598 2599 if (qla82xx_write_disable_flash(ha) != 0) 2600 ql_log(ql_log_warn, vha, 0xb018, 2601 "Write disable failed.\n"); 2602 done_protect: 2603 qla82xx_rom_unlock(ha); 2604 return ret; 2605 } 2606 2607 static int 2608 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2609 { 2610 int ret = 0; 2611 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2612 2613 ret = ql82xx_rom_lock_d(ha); 2614 if (ret < 0) { 2615 ql_log(ql_log_warn, vha, 0xb019, 2616 "ROM Lock failed.\n"); 2617 return ret; 2618 } 2619 2620 qla82xx_flash_set_write_enable(ha); 2621 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2622 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2623 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2624 2625 if (qla82xx_wait_rom_done(ha)) { 2626 ql_log(ql_log_warn, vha, 0xb01a, 2627 "Error waiting for rom done.\n"); 2628 ret = -1; 2629 goto done; 2630 } 2631 ret = qla82xx_flash_wait_write_finish(ha); 2632 done: 2633 qla82xx_rom_unlock(ha); 2634 return ret; 2635 } 2636 2637 /* 2638 * Address and length are byte address 2639 */ 2640 uint8_t * 2641 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2642 uint32_t offset, uint32_t length) 2643 { 2644 scsi_block_requests(vha->host); 2645 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2646 scsi_unblock_requests(vha->host); 2647 return buf; 2648 } 2649 2650 static int 2651 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2652 uint32_t faddr, uint32_t dwords) 2653 { 2654 int ret; 2655 uint32_t liter; 2656 uint32_t sec_mask, rest_addr; 2657 dma_addr_t optrom_dma; 2658 void *optrom = NULL; 2659 int page_mode = 0; 2660 struct qla_hw_data *ha = vha->hw; 2661 2662 ret = -1; 2663 2664 /* Prepare burst-capable write on supported ISPs. */ 2665 if (page_mode && !(faddr & 0xfff) && 2666 dwords > OPTROM_BURST_DWORDS) { 2667 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2668 &optrom_dma, GFP_KERNEL); 2669 if (!optrom) { 2670 ql_log(ql_log_warn, vha, 0xb01b, 2671 "Unable to allocate memory " 2672 "for optrom burst write (%x KB).\n", 2673 OPTROM_BURST_SIZE / 1024); 2674 } 2675 } 2676 2677 rest_addr = ha->fdt_block_size - 1; 2678 sec_mask = ~rest_addr; 2679 2680 ret = qla82xx_unprotect_flash(ha); 2681 if (ret) { 2682 ql_log(ql_log_warn, vha, 0xb01c, 2683 "Unable to unprotect flash for update.\n"); 2684 goto write_done; 2685 } 2686 2687 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2688 /* Are we at the beginning of a sector? */ 2689 if ((faddr & rest_addr) == 0) { 2690 2691 ret = qla82xx_erase_sector(ha, faddr); 2692 if (ret) { 2693 ql_log(ql_log_warn, vha, 0xb01d, 2694 "Unable to erase sector: address=%x.\n", 2695 faddr); 2696 break; 2697 } 2698 } 2699 2700 /* Go with burst-write. */ 2701 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2702 /* Copy data to DMA'ble buffer. */ 2703 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2704 2705 ret = qla2x00_load_ram(vha, optrom_dma, 2706 (ha->flash_data_off | faddr), 2707 OPTROM_BURST_DWORDS); 2708 if (ret != QLA_SUCCESS) { 2709 ql_log(ql_log_warn, vha, 0xb01e, 2710 "Unable to burst-write optrom segment " 2711 "(%x/%x/%llx).\n", ret, 2712 (ha->flash_data_off | faddr), 2713 (unsigned long long)optrom_dma); 2714 ql_log(ql_log_warn, vha, 0xb01f, 2715 "Reverting to slow-write.\n"); 2716 2717 dma_free_coherent(&ha->pdev->dev, 2718 OPTROM_BURST_SIZE, optrom, optrom_dma); 2719 optrom = NULL; 2720 } else { 2721 liter += OPTROM_BURST_DWORDS - 1; 2722 faddr += OPTROM_BURST_DWORDS - 1; 2723 dwptr += OPTROM_BURST_DWORDS - 1; 2724 continue; 2725 } 2726 } 2727 2728 ret = qla82xx_write_flash_dword(ha, faddr, 2729 cpu_to_le32(*dwptr)); 2730 if (ret) { 2731 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2732 "Unable to program flash address=%x data=%x.\n", 2733 faddr, *dwptr); 2734 break; 2735 } 2736 } 2737 2738 ret = qla82xx_protect_flash(ha); 2739 if (ret) 2740 ql_log(ql_log_warn, vha, 0xb021, 2741 "Unable to protect flash after update.\n"); 2742 write_done: 2743 if (optrom) 2744 dma_free_coherent(&ha->pdev->dev, 2745 OPTROM_BURST_SIZE, optrom, optrom_dma); 2746 return ret; 2747 } 2748 2749 int 2750 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2751 uint32_t offset, uint32_t length) 2752 { 2753 int rval; 2754 2755 /* Suspend HBA. */ 2756 scsi_block_requests(vha->host); 2757 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2758 length >> 2); 2759 scsi_unblock_requests(vha->host); 2760 2761 /* Convert return ISP82xx to generic */ 2762 if (rval) 2763 rval = QLA_FUNCTION_FAILED; 2764 else 2765 rval = QLA_SUCCESS; 2766 return rval; 2767 } 2768 2769 void 2770 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2771 { 2772 struct qla_hw_data *ha = vha->hw; 2773 struct req_que *req = ha->req_q_map[0]; 2774 struct device_reg_82xx __iomem *reg; 2775 uint32_t dbval; 2776 2777 /* Adjust ring index. */ 2778 req->ring_index++; 2779 if (req->ring_index == req->length) { 2780 req->ring_index = 0; 2781 req->ring_ptr = req->ring; 2782 } else 2783 req->ring_ptr++; 2784 2785 reg = &ha->iobase->isp82; 2786 dbval = 0x04 | (ha->portnum << 5); 2787 2788 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2789 if (ql2xdbwr) 2790 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2791 else { 2792 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2793 wmb(); 2794 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 2795 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2796 dbval); 2797 wmb(); 2798 } 2799 } 2800 } 2801 2802 static void 2803 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2804 { 2805 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2806 2807 if (qla82xx_rom_lock(ha)) 2808 /* Someone else is holding the lock. */ 2809 ql_log(ql_log_info, vha, 0xb022, 2810 "Resetting rom_lock.\n"); 2811 2812 /* 2813 * Either we got the lock, or someone 2814 * else died while holding it. 2815 * In either case, unlock. 2816 */ 2817 qla82xx_rom_unlock(ha); 2818 } 2819 2820 /* 2821 * qla82xx_device_bootstrap 2822 * Initialize device, set DEV_READY, start fw 2823 * 2824 * Note: 2825 * IDC lock must be held upon entry 2826 * 2827 * Return: 2828 * Success : 0 2829 * Failed : 1 2830 */ 2831 static int 2832 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2833 { 2834 int rval = QLA_SUCCESS; 2835 int i, timeout; 2836 uint32_t old_count, count; 2837 struct qla_hw_data *ha = vha->hw; 2838 int need_reset = 0, peg_stuck = 1; 2839 2840 need_reset = qla82xx_need_reset(ha); 2841 2842 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2843 2844 for (i = 0; i < 10; i++) { 2845 timeout = msleep_interruptible(200); 2846 if (timeout) { 2847 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2848 QLA8XXX_DEV_FAILED); 2849 return QLA_FUNCTION_FAILED; 2850 } 2851 2852 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2853 if (count != old_count) 2854 peg_stuck = 0; 2855 } 2856 2857 if (need_reset) { 2858 /* We are trying to perform a recovery here. */ 2859 if (peg_stuck) 2860 qla82xx_rom_lock_recovery(ha); 2861 goto dev_initialize; 2862 } else { 2863 /* Start of day for this ha context. */ 2864 if (peg_stuck) { 2865 /* Either we are the first or recovery in progress. */ 2866 qla82xx_rom_lock_recovery(ha); 2867 goto dev_initialize; 2868 } else 2869 /* Firmware already running. */ 2870 goto dev_ready; 2871 } 2872 2873 return rval; 2874 2875 dev_initialize: 2876 /* set to DEV_INITIALIZING */ 2877 ql_log(ql_log_info, vha, 0x009e, 2878 "HW State: INITIALIZING.\n"); 2879 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2880 2881 qla82xx_idc_unlock(ha); 2882 rval = qla82xx_start_firmware(vha); 2883 qla82xx_idc_lock(ha); 2884 2885 if (rval != QLA_SUCCESS) { 2886 ql_log(ql_log_fatal, vha, 0x00ad, 2887 "HW State: FAILED.\n"); 2888 qla82xx_clear_drv_active(ha); 2889 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2890 return rval; 2891 } 2892 2893 dev_ready: 2894 ql_log(ql_log_info, vha, 0x00ae, 2895 "HW State: READY.\n"); 2896 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2897 2898 return QLA_SUCCESS; 2899 } 2900 2901 /* 2902 * qla82xx_need_qsnt_handler 2903 * Code to start quiescence sequence 2904 * 2905 * Note: 2906 * IDC lock must be held upon entry 2907 * 2908 * Return: void 2909 */ 2910 2911 static void 2912 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2913 { 2914 struct qla_hw_data *ha = vha->hw; 2915 uint32_t dev_state, drv_state, drv_active; 2916 unsigned long reset_timeout; 2917 2918 if (vha->flags.online) { 2919 /*Block any further I/O and wait for pending cmnds to complete*/ 2920 qla2x00_quiesce_io(vha); 2921 } 2922 2923 /* Set the quiescence ready bit */ 2924 qla82xx_set_qsnt_ready(ha); 2925 2926 /*wait for 30 secs for other functions to ack */ 2927 reset_timeout = jiffies + (30 * HZ); 2928 2929 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2930 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2931 /* Its 2 that is written when qsnt is acked, moving one bit */ 2932 drv_active = drv_active << 0x01; 2933 2934 while (drv_state != drv_active) { 2935 2936 if (time_after_eq(jiffies, reset_timeout)) { 2937 /* quiescence timeout, other functions didn't ack 2938 * changing the state to DEV_READY 2939 */ 2940 ql_log(ql_log_info, vha, 0xb023, 2941 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2942 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2943 drv_active, drv_state); 2944 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2945 QLA8XXX_DEV_READY); 2946 ql_log(ql_log_info, vha, 0xb025, 2947 "HW State: DEV_READY.\n"); 2948 qla82xx_idc_unlock(ha); 2949 qla2x00_perform_loop_resync(vha); 2950 qla82xx_idc_lock(ha); 2951 2952 qla82xx_clear_qsnt_ready(vha); 2953 return; 2954 } 2955 2956 qla82xx_idc_unlock(ha); 2957 msleep(1000); 2958 qla82xx_idc_lock(ha); 2959 2960 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2961 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2962 drv_active = drv_active << 0x01; 2963 } 2964 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2965 /* everyone acked so set the state to DEV_QUIESCENCE */ 2966 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2967 ql_log(ql_log_info, vha, 0xb026, 2968 "HW State: DEV_QUIESCENT.\n"); 2969 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2970 } 2971 } 2972 2973 /* 2974 * qla82xx_wait_for_state_change 2975 * Wait for device state to change from given current state 2976 * 2977 * Note: 2978 * IDC lock must not be held upon entry 2979 * 2980 * Return: 2981 * Changed device state. 2982 */ 2983 uint32_t 2984 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2985 { 2986 struct qla_hw_data *ha = vha->hw; 2987 uint32_t dev_state; 2988 2989 do { 2990 msleep(1000); 2991 qla82xx_idc_lock(ha); 2992 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2993 qla82xx_idc_unlock(ha); 2994 } while (dev_state == curr_state); 2995 2996 return dev_state; 2997 } 2998 2999 void 3000 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3001 { 3002 struct qla_hw_data *ha = vha->hw; 3003 3004 /* Disable the board */ 3005 ql_log(ql_log_fatal, vha, 0x00b8, 3006 "Disabling the board.\n"); 3007 3008 if (IS_QLA82XX(ha)) { 3009 qla82xx_clear_drv_active(ha); 3010 qla82xx_idc_unlock(ha); 3011 } 3012 3013 /* Set DEV_FAILED flag to disable timer */ 3014 vha->device_flags |= DFLG_DEV_FAILED; 3015 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3016 qla2x00_mark_all_devices_lost(vha, 0); 3017 vha->flags.online = 0; 3018 vha->flags.init_done = 0; 3019 } 3020 3021 /* 3022 * qla82xx_need_reset_handler 3023 * Code to start reset sequence 3024 * 3025 * Note: 3026 * IDC lock must be held upon entry 3027 * 3028 * Return: 3029 * Success : 0 3030 * Failed : 1 3031 */ 3032 static void 3033 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3034 { 3035 uint32_t dev_state, drv_state, drv_active; 3036 uint32_t active_mask = 0; 3037 unsigned long reset_timeout; 3038 struct qla_hw_data *ha = vha->hw; 3039 struct req_que *req = ha->req_q_map[0]; 3040 3041 if (vha->flags.online) { 3042 qla82xx_idc_unlock(ha); 3043 qla2x00_abort_isp_cleanup(vha); 3044 ha->isp_ops->get_flash_version(vha, req->ring); 3045 ha->isp_ops->nvram_config(vha); 3046 qla82xx_idc_lock(ha); 3047 } 3048 3049 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3050 if (!ha->flags.nic_core_reset_owner) { 3051 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3052 "reset_acknowledged by 0x%x\n", ha->portnum); 3053 qla82xx_set_rst_ready(ha); 3054 } else { 3055 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3056 drv_active &= active_mask; 3057 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3058 "active_mask: 0x%08x\n", active_mask); 3059 } 3060 3061 /* wait for 10 seconds for reset ack from all functions */ 3062 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3063 3064 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3065 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3066 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3067 3068 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3069 "drv_state: 0x%08x, drv_active: 0x%08x, " 3070 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3071 drv_state, drv_active, dev_state, active_mask); 3072 3073 while (drv_state != drv_active && 3074 dev_state != QLA8XXX_DEV_INITIALIZING) { 3075 if (time_after_eq(jiffies, reset_timeout)) { 3076 ql_log(ql_log_warn, vha, 0x00b5, 3077 "Reset timeout.\n"); 3078 break; 3079 } 3080 qla82xx_idc_unlock(ha); 3081 msleep(1000); 3082 qla82xx_idc_lock(ha); 3083 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3084 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3085 if (ha->flags.nic_core_reset_owner) 3086 drv_active &= active_mask; 3087 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3088 } 3089 3090 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3091 "drv_state: 0x%08x, drv_active: 0x%08x, " 3092 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3093 drv_state, drv_active, dev_state, active_mask); 3094 3095 ql_log(ql_log_info, vha, 0x00b6, 3096 "Device state is 0x%x = %s.\n", 3097 dev_state, 3098 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3099 3100 /* Force to DEV_COLD unless someone else is starting a reset */ 3101 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3102 dev_state != QLA8XXX_DEV_COLD) { 3103 ql_log(ql_log_info, vha, 0x00b7, 3104 "HW State: COLD/RE-INIT.\n"); 3105 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3106 qla82xx_set_rst_ready(ha); 3107 if (ql2xmdenable) { 3108 if (qla82xx_md_collect(vha)) 3109 ql_log(ql_log_warn, vha, 0xb02c, 3110 "Minidump not collected.\n"); 3111 } else 3112 ql_log(ql_log_warn, vha, 0xb04f, 3113 "Minidump disabled.\n"); 3114 } 3115 } 3116 3117 int 3118 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3119 { 3120 struct qla_hw_data *ha = vha->hw; 3121 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3122 int rval = QLA_SUCCESS; 3123 3124 fw_major_version = ha->fw_major_version; 3125 fw_minor_version = ha->fw_minor_version; 3126 fw_subminor_version = ha->fw_subminor_version; 3127 3128 rval = qla2x00_get_fw_version(vha); 3129 if (rval != QLA_SUCCESS) 3130 return rval; 3131 3132 if (ql2xmdenable) { 3133 if (!ha->fw_dumped) { 3134 if (fw_major_version != ha->fw_major_version || 3135 fw_minor_version != ha->fw_minor_version || 3136 fw_subminor_version != ha->fw_subminor_version) { 3137 ql_log(ql_log_info, vha, 0xb02d, 3138 "Firmware version differs " 3139 "Previous version: %d:%d:%d - " 3140 "New version: %d:%d:%d\n", 3141 fw_major_version, fw_minor_version, 3142 fw_subminor_version, 3143 ha->fw_major_version, 3144 ha->fw_minor_version, 3145 ha->fw_subminor_version); 3146 /* Release MiniDump resources */ 3147 qla82xx_md_free(vha); 3148 /* ALlocate MiniDump resources */ 3149 qla82xx_md_prep(vha); 3150 } 3151 } else 3152 ql_log(ql_log_info, vha, 0xb02e, 3153 "Firmware dump available to retrieve\n"); 3154 } 3155 return rval; 3156 } 3157 3158 3159 static int 3160 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3161 { 3162 uint32_t fw_heartbeat_counter; 3163 int status = 0; 3164 3165 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3166 QLA82XX_PEG_ALIVE_COUNTER); 3167 /* all 0xff, assume AER/EEH in progress, ignore */ 3168 if (fw_heartbeat_counter == 0xffffffff) { 3169 ql_dbg(ql_dbg_timer, vha, 0x6003, 3170 "FW heartbeat counter is 0xffffffff, " 3171 "returning status=%d.\n", status); 3172 return status; 3173 } 3174 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3175 vha->seconds_since_last_heartbeat++; 3176 /* FW not alive after 2 seconds */ 3177 if (vha->seconds_since_last_heartbeat == 2) { 3178 vha->seconds_since_last_heartbeat = 0; 3179 status = 1; 3180 } 3181 } else 3182 vha->seconds_since_last_heartbeat = 0; 3183 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3184 if (status) 3185 ql_dbg(ql_dbg_timer, vha, 0x6004, 3186 "Returning status=%d.\n", status); 3187 return status; 3188 } 3189 3190 /* 3191 * qla82xx_device_state_handler 3192 * Main state handler 3193 * 3194 * Note: 3195 * IDC lock must be held upon entry 3196 * 3197 * Return: 3198 * Success : 0 3199 * Failed : 1 3200 */ 3201 int 3202 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3203 { 3204 uint32_t dev_state; 3205 uint32_t old_dev_state; 3206 int rval = QLA_SUCCESS; 3207 unsigned long dev_init_timeout; 3208 struct qla_hw_data *ha = vha->hw; 3209 int loopcount = 0; 3210 3211 qla82xx_idc_lock(ha); 3212 if (!vha->flags.init_done) { 3213 qla82xx_set_drv_active(vha); 3214 qla82xx_set_idc_version(vha); 3215 } 3216 3217 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3218 old_dev_state = dev_state; 3219 ql_log(ql_log_info, vha, 0x009b, 3220 "Device state is 0x%x = %s.\n", 3221 dev_state, 3222 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3223 3224 /* wait for 30 seconds for device to go ready */ 3225 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3226 3227 while (1) { 3228 3229 if (time_after_eq(jiffies, dev_init_timeout)) { 3230 ql_log(ql_log_fatal, vha, 0x009c, 3231 "Device init failed.\n"); 3232 rval = QLA_FUNCTION_FAILED; 3233 break; 3234 } 3235 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3236 if (old_dev_state != dev_state) { 3237 loopcount = 0; 3238 old_dev_state = dev_state; 3239 } 3240 if (loopcount < 5) { 3241 ql_log(ql_log_info, vha, 0x009d, 3242 "Device state is 0x%x = %s.\n", 3243 dev_state, 3244 dev_state < MAX_STATES ? qdev_state(dev_state) : 3245 "Unknown"); 3246 } 3247 3248 switch (dev_state) { 3249 case QLA8XXX_DEV_READY: 3250 ha->flags.nic_core_reset_owner = 0; 3251 goto rel_lock; 3252 case QLA8XXX_DEV_COLD: 3253 rval = qla82xx_device_bootstrap(vha); 3254 break; 3255 case QLA8XXX_DEV_INITIALIZING: 3256 qla82xx_idc_unlock(ha); 3257 msleep(1000); 3258 qla82xx_idc_lock(ha); 3259 break; 3260 case QLA8XXX_DEV_NEED_RESET: 3261 if (!ql2xdontresethba) 3262 qla82xx_need_reset_handler(vha); 3263 else { 3264 qla82xx_idc_unlock(ha); 3265 msleep(1000); 3266 qla82xx_idc_lock(ha); 3267 } 3268 dev_init_timeout = jiffies + 3269 (ha->fcoe_dev_init_timeout * HZ); 3270 break; 3271 case QLA8XXX_DEV_NEED_QUIESCENT: 3272 qla82xx_need_qsnt_handler(vha); 3273 /* Reset timeout value after quiescence handler */ 3274 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3275 * HZ); 3276 break; 3277 case QLA8XXX_DEV_QUIESCENT: 3278 /* Owner will exit and other will wait for the state 3279 * to get changed 3280 */ 3281 if (ha->flags.quiesce_owner) 3282 goto rel_lock; 3283 3284 qla82xx_idc_unlock(ha); 3285 msleep(1000); 3286 qla82xx_idc_lock(ha); 3287 3288 /* Reset timeout value after quiescence handler */ 3289 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3290 * HZ); 3291 break; 3292 case QLA8XXX_DEV_FAILED: 3293 qla8xxx_dev_failed_handler(vha); 3294 rval = QLA_FUNCTION_FAILED; 3295 goto exit; 3296 default: 3297 qla82xx_idc_unlock(ha); 3298 msleep(1000); 3299 qla82xx_idc_lock(ha); 3300 } 3301 loopcount++; 3302 } 3303 rel_lock: 3304 qla82xx_idc_unlock(ha); 3305 exit: 3306 return rval; 3307 } 3308 3309 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3310 { 3311 uint32_t temp, temp_state, temp_val; 3312 struct qla_hw_data *ha = vha->hw; 3313 3314 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3315 temp_state = qla82xx_get_temp_state(temp); 3316 temp_val = qla82xx_get_temp_val(temp); 3317 3318 if (temp_state == QLA82XX_TEMP_PANIC) { 3319 ql_log(ql_log_warn, vha, 0x600e, 3320 "Device temperature %d degrees C exceeds " 3321 " maximum allowed. Hardware has been shut down.\n", 3322 temp_val); 3323 return 1; 3324 } else if (temp_state == QLA82XX_TEMP_WARN) { 3325 ql_log(ql_log_warn, vha, 0x600f, 3326 "Device temperature %d degrees C exceeds " 3327 "operating range. Immediate action needed.\n", 3328 temp_val); 3329 } 3330 return 0; 3331 } 3332 3333 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3334 { 3335 struct qla_hw_data *ha = vha->hw; 3336 3337 if (ha->flags.mbox_busy) { 3338 ha->flags.mbox_int = 1; 3339 ha->flags.mbox_busy = 0; 3340 ql_log(ql_log_warn, vha, 0x6010, 3341 "Doing premature completion of mbx command.\n"); 3342 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3343 complete(&ha->mbx_intr_comp); 3344 } 3345 } 3346 3347 void qla82xx_watchdog(scsi_qla_host_t *vha) 3348 { 3349 uint32_t dev_state, halt_status; 3350 struct qla_hw_data *ha = vha->hw; 3351 3352 /* don't poll if reset is going on */ 3353 if (!ha->flags.nic_core_reset_hdlr_active) { 3354 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3355 if (qla82xx_check_temp(vha)) { 3356 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3357 ha->flags.isp82xx_fw_hung = 1; 3358 qla82xx_clear_pending_mbx(vha); 3359 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3360 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3361 ql_log(ql_log_warn, vha, 0x6001, 3362 "Adapter reset needed.\n"); 3363 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3364 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3365 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3366 ql_log(ql_log_warn, vha, 0x6002, 3367 "Quiescent needed.\n"); 3368 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3369 } else if (dev_state == QLA8XXX_DEV_FAILED && 3370 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3371 vha->flags.online == 1) { 3372 ql_log(ql_log_warn, vha, 0xb055, 3373 "Adapter state is failed. Offlining.\n"); 3374 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3375 ha->flags.isp82xx_fw_hung = 1; 3376 qla82xx_clear_pending_mbx(vha); 3377 } else { 3378 if (qla82xx_check_fw_alive(vha)) { 3379 ql_dbg(ql_dbg_timer, vha, 0x6011, 3380 "disabling pause transmit on port 0 & 1.\n"); 3381 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3382 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3383 halt_status = qla82xx_rd_32(ha, 3384 QLA82XX_PEG_HALT_STATUS1); 3385 ql_log(ql_log_info, vha, 0x6005, 3386 "dumping hw/fw registers:.\n " 3387 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3388 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3389 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3390 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3391 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3392 qla82xx_rd_32(ha, 3393 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3394 qla82xx_rd_32(ha, 3395 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3396 qla82xx_rd_32(ha, 3397 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3398 qla82xx_rd_32(ha, 3399 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3400 qla82xx_rd_32(ha, 3401 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3402 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3403 ql_log(ql_log_warn, vha, 0xb052, 3404 "Firmware aborted with " 3405 "error code 0x00006700. Device is " 3406 "being reset.\n"); 3407 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3408 set_bit(ISP_UNRECOVERABLE, 3409 &vha->dpc_flags); 3410 } else { 3411 ql_log(ql_log_info, vha, 0x6006, 3412 "Detect abort needed.\n"); 3413 set_bit(ISP_ABORT_NEEDED, 3414 &vha->dpc_flags); 3415 } 3416 ha->flags.isp82xx_fw_hung = 1; 3417 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3418 qla82xx_clear_pending_mbx(vha); 3419 } 3420 } 3421 } 3422 } 3423 3424 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3425 { 3426 int rval; 3427 rval = qla82xx_device_state_handler(vha); 3428 return rval; 3429 } 3430 3431 void 3432 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3433 { 3434 struct qla_hw_data *ha = vha->hw; 3435 uint32_t dev_state; 3436 3437 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3438 if (dev_state == QLA8XXX_DEV_READY) { 3439 ql_log(ql_log_info, vha, 0xb02f, 3440 "HW State: NEED RESET\n"); 3441 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3442 QLA8XXX_DEV_NEED_RESET); 3443 ha->flags.nic_core_reset_owner = 1; 3444 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3445 "reset_owner is 0x%x\n", ha->portnum); 3446 } else 3447 ql_log(ql_log_info, vha, 0xb031, 3448 "Device state is 0x%x = %s.\n", 3449 dev_state, 3450 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3451 } 3452 3453 /* 3454 * qla82xx_abort_isp 3455 * Resets ISP and aborts all outstanding commands. 3456 * 3457 * Input: 3458 * ha = adapter block pointer. 3459 * 3460 * Returns: 3461 * 0 = success 3462 */ 3463 int 3464 qla82xx_abort_isp(scsi_qla_host_t *vha) 3465 { 3466 int rval; 3467 struct qla_hw_data *ha = vha->hw; 3468 3469 if (vha->device_flags & DFLG_DEV_FAILED) { 3470 ql_log(ql_log_warn, vha, 0x8024, 3471 "Device in failed state, exiting.\n"); 3472 return QLA_SUCCESS; 3473 } 3474 ha->flags.nic_core_reset_hdlr_active = 1; 3475 3476 qla82xx_idc_lock(ha); 3477 qla82xx_set_reset_owner(vha); 3478 qla82xx_idc_unlock(ha); 3479 3480 rval = qla82xx_device_state_handler(vha); 3481 3482 qla82xx_idc_lock(ha); 3483 qla82xx_clear_rst_ready(ha); 3484 qla82xx_idc_unlock(ha); 3485 3486 if (rval == QLA_SUCCESS) { 3487 ha->flags.isp82xx_fw_hung = 0; 3488 ha->flags.nic_core_reset_hdlr_active = 0; 3489 qla82xx_restart_isp(vha); 3490 } 3491 3492 if (rval) { 3493 vha->flags.online = 1; 3494 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3495 if (ha->isp_abort_cnt == 0) { 3496 ql_log(ql_log_warn, vha, 0x8027, 3497 "ISP error recover failed - board " 3498 "disabled.\n"); 3499 /* 3500 * The next call disables the board 3501 * completely. 3502 */ 3503 ha->isp_ops->reset_adapter(vha); 3504 vha->flags.online = 0; 3505 clear_bit(ISP_ABORT_RETRY, 3506 &vha->dpc_flags); 3507 rval = QLA_SUCCESS; 3508 } else { /* schedule another ISP abort */ 3509 ha->isp_abort_cnt--; 3510 ql_log(ql_log_warn, vha, 0x8036, 3511 "ISP abort - retry remaining %d.\n", 3512 ha->isp_abort_cnt); 3513 rval = QLA_FUNCTION_FAILED; 3514 } 3515 } else { 3516 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3517 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3518 "ISP error recovery - retrying (%d) more times.\n", 3519 ha->isp_abort_cnt); 3520 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3521 rval = QLA_FUNCTION_FAILED; 3522 } 3523 } 3524 return rval; 3525 } 3526 3527 /* 3528 * qla82xx_fcoe_ctx_reset 3529 * Perform a quick reset and aborts all outstanding commands. 3530 * This will only perform an FCoE context reset and avoids a full blown 3531 * chip reset. 3532 * 3533 * Input: 3534 * ha = adapter block pointer. 3535 * is_reset_path = flag for identifying the reset path. 3536 * 3537 * Returns: 3538 * 0 = success 3539 */ 3540 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3541 { 3542 int rval = QLA_FUNCTION_FAILED; 3543 3544 if (vha->flags.online) { 3545 /* Abort all outstanding commands, so as to be requeued later */ 3546 qla2x00_abort_isp_cleanup(vha); 3547 } 3548 3549 /* Stop currently executing firmware. 3550 * This will destroy existing FCoE context at the F/W end. 3551 */ 3552 qla2x00_try_to_stop_firmware(vha); 3553 3554 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3555 rval = qla82xx_restart_isp(vha); 3556 3557 return rval; 3558 } 3559 3560 /* 3561 * qla2x00_wait_for_fcoe_ctx_reset 3562 * Wait till the FCoE context is reset. 3563 * 3564 * Note: 3565 * Does context switching here. 3566 * Release SPIN_LOCK (if any) before calling this routine. 3567 * 3568 * Return: 3569 * Success (fcoe_ctx reset is done) : 0 3570 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3571 */ 3572 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3573 { 3574 int status = QLA_FUNCTION_FAILED; 3575 unsigned long wait_reset; 3576 3577 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3578 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3579 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3580 && time_before(jiffies, wait_reset)) { 3581 3582 set_current_state(TASK_UNINTERRUPTIBLE); 3583 schedule_timeout(HZ); 3584 3585 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3586 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3587 status = QLA_SUCCESS; 3588 break; 3589 } 3590 } 3591 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3592 "%s: status=%d.\n", __func__, status); 3593 3594 return status; 3595 } 3596 3597 void 3598 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3599 { 3600 int i; 3601 unsigned long flags; 3602 struct qla_hw_data *ha = vha->hw; 3603 3604 /* Check if 82XX firmware is alive or not 3605 * We may have arrived here from NEED_RESET 3606 * detection only 3607 */ 3608 if (!ha->flags.isp82xx_fw_hung) { 3609 for (i = 0; i < 2; i++) { 3610 msleep(1000); 3611 if (qla82xx_check_fw_alive(vha)) { 3612 ha->flags.isp82xx_fw_hung = 1; 3613 qla82xx_clear_pending_mbx(vha); 3614 break; 3615 } 3616 } 3617 } 3618 ql_dbg(ql_dbg_init, vha, 0x00b0, 3619 "Entered %s fw_hung=%d.\n", 3620 __func__, ha->flags.isp82xx_fw_hung); 3621 3622 /* Abort all commands gracefully if fw NOT hung */ 3623 if (!ha->flags.isp82xx_fw_hung) { 3624 int cnt, que; 3625 srb_t *sp; 3626 struct req_que *req; 3627 3628 spin_lock_irqsave(&ha->hardware_lock, flags); 3629 for (que = 0; que < ha->max_req_queues; que++) { 3630 req = ha->req_q_map[que]; 3631 if (!req) 3632 continue; 3633 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3634 sp = req->outstanding_cmds[cnt]; 3635 if (sp) { 3636 if (!sp->u.scmd.ctx || 3637 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3638 spin_unlock_irqrestore( 3639 &ha->hardware_lock, flags); 3640 if (ha->isp_ops->abort_command(sp)) { 3641 ql_log(ql_log_info, vha, 3642 0x00b1, 3643 "mbx abort failed.\n"); 3644 } else { 3645 ql_log(ql_log_info, vha, 3646 0x00b2, 3647 "mbx abort success.\n"); 3648 } 3649 spin_lock_irqsave(&ha->hardware_lock, flags); 3650 } 3651 } 3652 } 3653 } 3654 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3655 3656 /* Wait for pending cmds (physical and virtual) to complete */ 3657 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3658 WAIT_HOST) == QLA_SUCCESS) { 3659 ql_dbg(ql_dbg_init, vha, 0x00b3, 3660 "Done wait for " 3661 "pending commands.\n"); 3662 } 3663 } 3664 } 3665 3666 /* Minidump related functions */ 3667 static int 3668 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3669 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3670 { 3671 struct qla_hw_data *ha = vha->hw; 3672 struct qla82xx_md_entry_crb *crb_entry; 3673 uint32_t read_value, opcode, poll_time; 3674 uint32_t addr, index, crb_addr; 3675 unsigned long wtime; 3676 struct qla82xx_md_template_hdr *tmplt_hdr; 3677 uint32_t rval = QLA_SUCCESS; 3678 int i; 3679 3680 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3681 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3682 crb_addr = crb_entry->addr; 3683 3684 for (i = 0; i < crb_entry->op_count; i++) { 3685 opcode = crb_entry->crb_ctrl.opcode; 3686 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3687 qla82xx_md_rw_32(ha, crb_addr, 3688 crb_entry->value_1, 1); 3689 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3690 } 3691 3692 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3693 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3694 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3695 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3696 } 3697 3698 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3699 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3700 read_value &= crb_entry->value_2; 3701 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3702 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3703 read_value |= crb_entry->value_3; 3704 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3705 } 3706 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3707 } 3708 3709 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3710 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3711 read_value |= crb_entry->value_3; 3712 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3713 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3714 } 3715 3716 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3717 poll_time = crb_entry->crb_strd.poll_timeout; 3718 wtime = jiffies + poll_time; 3719 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3720 3721 do { 3722 if ((read_value & crb_entry->value_2) 3723 == crb_entry->value_1) 3724 break; 3725 else if (time_after_eq(jiffies, wtime)) { 3726 /* capturing dump failed */ 3727 rval = QLA_FUNCTION_FAILED; 3728 break; 3729 } else 3730 read_value = qla82xx_md_rw_32(ha, 3731 crb_addr, 0, 0); 3732 } while (1); 3733 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3734 } 3735 3736 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3737 if (crb_entry->crb_strd.state_index_a) { 3738 index = crb_entry->crb_strd.state_index_a; 3739 addr = tmplt_hdr->saved_state_array[index]; 3740 } else 3741 addr = crb_addr; 3742 3743 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3744 index = crb_entry->crb_ctrl.state_index_v; 3745 tmplt_hdr->saved_state_array[index] = read_value; 3746 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3747 } 3748 3749 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3750 if (crb_entry->crb_strd.state_index_a) { 3751 index = crb_entry->crb_strd.state_index_a; 3752 addr = tmplt_hdr->saved_state_array[index]; 3753 } else 3754 addr = crb_addr; 3755 3756 if (crb_entry->crb_ctrl.state_index_v) { 3757 index = crb_entry->crb_ctrl.state_index_v; 3758 read_value = 3759 tmplt_hdr->saved_state_array[index]; 3760 } else 3761 read_value = crb_entry->value_1; 3762 3763 qla82xx_md_rw_32(ha, addr, read_value, 1); 3764 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3765 } 3766 3767 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3768 index = crb_entry->crb_ctrl.state_index_v; 3769 read_value = tmplt_hdr->saved_state_array[index]; 3770 read_value <<= crb_entry->crb_ctrl.shl; 3771 read_value >>= crb_entry->crb_ctrl.shr; 3772 if (crb_entry->value_2) 3773 read_value &= crb_entry->value_2; 3774 read_value |= crb_entry->value_3; 3775 read_value += crb_entry->value_1; 3776 tmplt_hdr->saved_state_array[index] = read_value; 3777 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3778 } 3779 crb_addr += crb_entry->crb_strd.addr_stride; 3780 } 3781 return rval; 3782 } 3783 3784 static void 3785 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3786 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3787 { 3788 struct qla_hw_data *ha = vha->hw; 3789 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3790 struct qla82xx_md_entry_rdocm *ocm_hdr; 3791 uint32_t *data_ptr = *d_ptr; 3792 3793 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3794 r_addr = ocm_hdr->read_addr; 3795 r_stride = ocm_hdr->read_addr_stride; 3796 loop_cnt = ocm_hdr->op_count; 3797 3798 for (i = 0; i < loop_cnt; i++) { 3799 r_value = RD_REG_DWORD((void __iomem *) 3800 (r_addr + ha->nx_pcibase)); 3801 *data_ptr++ = cpu_to_le32(r_value); 3802 r_addr += r_stride; 3803 } 3804 *d_ptr = data_ptr; 3805 } 3806 3807 static void 3808 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3809 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3810 { 3811 struct qla_hw_data *ha = vha->hw; 3812 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3813 struct qla82xx_md_entry_mux *mux_hdr; 3814 uint32_t *data_ptr = *d_ptr; 3815 3816 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3817 r_addr = mux_hdr->read_addr; 3818 s_addr = mux_hdr->select_addr; 3819 s_stride = mux_hdr->select_value_stride; 3820 s_value = mux_hdr->select_value; 3821 loop_cnt = mux_hdr->op_count; 3822 3823 for (i = 0; i < loop_cnt; i++) { 3824 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3825 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3826 *data_ptr++ = cpu_to_le32(s_value); 3827 *data_ptr++ = cpu_to_le32(r_value); 3828 s_value += s_stride; 3829 } 3830 *d_ptr = data_ptr; 3831 } 3832 3833 static void 3834 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3835 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3836 { 3837 struct qla_hw_data *ha = vha->hw; 3838 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3839 struct qla82xx_md_entry_crb *crb_hdr; 3840 uint32_t *data_ptr = *d_ptr; 3841 3842 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3843 r_addr = crb_hdr->addr; 3844 r_stride = crb_hdr->crb_strd.addr_stride; 3845 loop_cnt = crb_hdr->op_count; 3846 3847 for (i = 0; i < loop_cnt; i++) { 3848 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3849 *data_ptr++ = cpu_to_le32(r_addr); 3850 *data_ptr++ = cpu_to_le32(r_value); 3851 r_addr += r_stride; 3852 } 3853 *d_ptr = data_ptr; 3854 } 3855 3856 static int 3857 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3858 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3859 { 3860 struct qla_hw_data *ha = vha->hw; 3861 uint32_t addr, r_addr, c_addr, t_r_addr; 3862 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3863 unsigned long p_wait, w_time, p_mask; 3864 uint32_t c_value_w, c_value_r; 3865 struct qla82xx_md_entry_cache *cache_hdr; 3866 int rval = QLA_FUNCTION_FAILED; 3867 uint32_t *data_ptr = *d_ptr; 3868 3869 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3870 loop_count = cache_hdr->op_count; 3871 r_addr = cache_hdr->read_addr; 3872 c_addr = cache_hdr->control_addr; 3873 c_value_w = cache_hdr->cache_ctrl.write_value; 3874 3875 t_r_addr = cache_hdr->tag_reg_addr; 3876 t_value = cache_hdr->addr_ctrl.init_tag_value; 3877 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3878 p_wait = cache_hdr->cache_ctrl.poll_wait; 3879 p_mask = cache_hdr->cache_ctrl.poll_mask; 3880 3881 for (i = 0; i < loop_count; i++) { 3882 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3883 if (c_value_w) 3884 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3885 3886 if (p_mask) { 3887 w_time = jiffies + p_wait; 3888 do { 3889 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3890 if ((c_value_r & p_mask) == 0) 3891 break; 3892 else if (time_after_eq(jiffies, w_time)) { 3893 /* capturing dump failed */ 3894 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3895 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3896 "w_time: 0x%lx\n", 3897 c_value_r, p_mask, w_time); 3898 return rval; 3899 } 3900 } while (1); 3901 } 3902 3903 addr = r_addr; 3904 for (k = 0; k < r_cnt; k++) { 3905 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3906 *data_ptr++ = cpu_to_le32(r_value); 3907 addr += cache_hdr->read_ctrl.read_addr_stride; 3908 } 3909 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3910 } 3911 *d_ptr = data_ptr; 3912 return QLA_SUCCESS; 3913 } 3914 3915 static void 3916 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3917 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3918 { 3919 struct qla_hw_data *ha = vha->hw; 3920 uint32_t addr, r_addr, c_addr, t_r_addr; 3921 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3922 uint32_t c_value_w; 3923 struct qla82xx_md_entry_cache *cache_hdr; 3924 uint32_t *data_ptr = *d_ptr; 3925 3926 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3927 loop_count = cache_hdr->op_count; 3928 r_addr = cache_hdr->read_addr; 3929 c_addr = cache_hdr->control_addr; 3930 c_value_w = cache_hdr->cache_ctrl.write_value; 3931 3932 t_r_addr = cache_hdr->tag_reg_addr; 3933 t_value = cache_hdr->addr_ctrl.init_tag_value; 3934 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3935 3936 for (i = 0; i < loop_count; i++) { 3937 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3938 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3939 addr = r_addr; 3940 for (k = 0; k < r_cnt; k++) { 3941 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3942 *data_ptr++ = cpu_to_le32(r_value); 3943 addr += cache_hdr->read_ctrl.read_addr_stride; 3944 } 3945 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3946 } 3947 *d_ptr = data_ptr; 3948 } 3949 3950 static void 3951 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3952 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3953 { 3954 struct qla_hw_data *ha = vha->hw; 3955 uint32_t s_addr, r_addr; 3956 uint32_t r_stride, r_value, r_cnt, qid = 0; 3957 uint32_t i, k, loop_cnt; 3958 struct qla82xx_md_entry_queue *q_hdr; 3959 uint32_t *data_ptr = *d_ptr; 3960 3961 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3962 s_addr = q_hdr->select_addr; 3963 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3964 r_stride = q_hdr->rd_strd.read_addr_stride; 3965 loop_cnt = q_hdr->op_count; 3966 3967 for (i = 0; i < loop_cnt; i++) { 3968 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3969 r_addr = q_hdr->read_addr; 3970 for (k = 0; k < r_cnt; k++) { 3971 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3972 *data_ptr++ = cpu_to_le32(r_value); 3973 r_addr += r_stride; 3974 } 3975 qid += q_hdr->q_strd.queue_id_stride; 3976 } 3977 *d_ptr = data_ptr; 3978 } 3979 3980 static void 3981 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3982 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3983 { 3984 struct qla_hw_data *ha = vha->hw; 3985 uint32_t r_addr, r_value; 3986 uint32_t i, loop_cnt; 3987 struct qla82xx_md_entry_rdrom *rom_hdr; 3988 uint32_t *data_ptr = *d_ptr; 3989 3990 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 3991 r_addr = rom_hdr->read_addr; 3992 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 3993 3994 for (i = 0; i < loop_cnt; i++) { 3995 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 3996 (r_addr & 0xFFFF0000), 1); 3997 r_value = qla82xx_md_rw_32(ha, 3998 MD_DIRECT_ROM_READ_BASE + 3999 (r_addr & 0x0000FFFF), 0, 0); 4000 *data_ptr++ = cpu_to_le32(r_value); 4001 r_addr += sizeof(uint32_t); 4002 } 4003 *d_ptr = data_ptr; 4004 } 4005 4006 static int 4007 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4008 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4009 { 4010 struct qla_hw_data *ha = vha->hw; 4011 uint32_t r_addr, r_value, r_data; 4012 uint32_t i, j, loop_cnt; 4013 struct qla82xx_md_entry_rdmem *m_hdr; 4014 unsigned long flags; 4015 int rval = QLA_FUNCTION_FAILED; 4016 uint32_t *data_ptr = *d_ptr; 4017 4018 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4019 r_addr = m_hdr->read_addr; 4020 loop_cnt = m_hdr->read_data_size/16; 4021 4022 if (r_addr & 0xf) { 4023 ql_log(ql_log_warn, vha, 0xb033, 4024 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4025 return rval; 4026 } 4027 4028 if (m_hdr->read_data_size % 16) { 4029 ql_log(ql_log_warn, vha, 0xb034, 4030 "Read data[0x%x] not multiple of 16 bytes\n", 4031 m_hdr->read_data_size); 4032 return rval; 4033 } 4034 4035 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4036 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4037 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4038 4039 write_lock_irqsave(&ha->hw_lock, flags); 4040 for (i = 0; i < loop_cnt; i++) { 4041 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4042 r_value = 0; 4043 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4044 r_value = MIU_TA_CTL_ENABLE; 4045 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4046 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4047 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4048 4049 for (j = 0; j < MAX_CTL_CHECK; j++) { 4050 r_value = qla82xx_md_rw_32(ha, 4051 MD_MIU_TEST_AGT_CTRL, 0, 0); 4052 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4053 break; 4054 } 4055 4056 if (j >= MAX_CTL_CHECK) { 4057 printk_ratelimited(KERN_ERR 4058 "failed to read through agent\n"); 4059 write_unlock_irqrestore(&ha->hw_lock, flags); 4060 return rval; 4061 } 4062 4063 for (j = 0; j < 4; j++) { 4064 r_data = qla82xx_md_rw_32(ha, 4065 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4066 *data_ptr++ = cpu_to_le32(r_data); 4067 } 4068 r_addr += 16; 4069 } 4070 write_unlock_irqrestore(&ha->hw_lock, flags); 4071 *d_ptr = data_ptr; 4072 return QLA_SUCCESS; 4073 } 4074 4075 static int 4076 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4077 { 4078 struct qla_hw_data *ha = vha->hw; 4079 uint64_t chksum = 0; 4080 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4081 int count = ha->md_template_size/sizeof(uint32_t); 4082 4083 while (count-- > 0) 4084 chksum += *d_ptr++; 4085 while (chksum >> 32) 4086 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4087 return ~chksum; 4088 } 4089 4090 static void 4091 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4092 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4093 { 4094 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4095 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4096 "Skipping entry[%d]: " 4097 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4098 index, entry_hdr->entry_type, 4099 entry_hdr->d_ctrl.entry_capture_mask); 4100 } 4101 4102 int 4103 qla82xx_md_collect(scsi_qla_host_t *vha) 4104 { 4105 struct qla_hw_data *ha = vha->hw; 4106 int no_entry_hdr = 0; 4107 qla82xx_md_entry_hdr_t *entry_hdr; 4108 struct qla82xx_md_template_hdr *tmplt_hdr; 4109 uint32_t *data_ptr; 4110 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4111 int i = 0, rval = QLA_FUNCTION_FAILED; 4112 4113 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4114 data_ptr = (uint32_t *)ha->md_dump; 4115 4116 if (ha->fw_dumped) { 4117 ql_log(ql_log_warn, vha, 0xb037, 4118 "Firmware has been previously dumped (%p) " 4119 "-- ignoring request.\n", ha->fw_dump); 4120 goto md_failed; 4121 } 4122 4123 ha->fw_dumped = 0; 4124 4125 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4126 ql_log(ql_log_warn, vha, 0xb038, 4127 "Memory not allocated for minidump capture\n"); 4128 goto md_failed; 4129 } 4130 4131 if (ha->flags.isp82xx_no_md_cap) { 4132 ql_log(ql_log_warn, vha, 0xb054, 4133 "Forced reset from application, " 4134 "ignore minidump capture\n"); 4135 ha->flags.isp82xx_no_md_cap = 0; 4136 goto md_failed; 4137 } 4138 4139 if (qla82xx_validate_template_chksum(vha)) { 4140 ql_log(ql_log_info, vha, 0xb039, 4141 "Template checksum validation error\n"); 4142 goto md_failed; 4143 } 4144 4145 no_entry_hdr = tmplt_hdr->num_of_entries; 4146 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4147 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4148 4149 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4150 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4151 4152 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4153 4154 /* Validate whether required debug level is set */ 4155 if ((f_capture_mask & 0x3) != 0x3) { 4156 ql_log(ql_log_warn, vha, 0xb03c, 4157 "Minimum required capture mask[0x%x] level not set\n", 4158 f_capture_mask); 4159 goto md_failed; 4160 } 4161 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4162 4163 tmplt_hdr->driver_info[0] = vha->host_no; 4164 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4165 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4166 QLA_DRIVER_BETA_VER; 4167 4168 total_data_size = ha->md_dump_size; 4169 4170 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4171 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4172 4173 /* Check whether template obtained is valid */ 4174 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4175 ql_log(ql_log_warn, vha, 0xb04e, 4176 "Bad template header entry type: 0x%x obtained\n", 4177 tmplt_hdr->entry_type); 4178 goto md_failed; 4179 } 4180 4181 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4182 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4183 4184 /* Walk through the entry headers */ 4185 for (i = 0; i < no_entry_hdr; i++) { 4186 4187 if (data_collected > total_data_size) { 4188 ql_log(ql_log_warn, vha, 0xb03e, 4189 "More MiniDump data collected: [0x%x]\n", 4190 data_collected); 4191 goto md_failed; 4192 } 4193 4194 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4195 ql2xmdcapmask)) { 4196 entry_hdr->d_ctrl.driver_flags |= 4197 QLA82XX_DBG_SKIPPED_FLAG; 4198 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4199 "Skipping entry[%d]: " 4200 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4201 i, entry_hdr->entry_type, 4202 entry_hdr->d_ctrl.entry_capture_mask); 4203 goto skip_nxt_entry; 4204 } 4205 4206 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4207 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4208 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4209 __func__, i, data_ptr, entry_hdr, 4210 entry_hdr->entry_type, 4211 entry_hdr->d_ctrl.entry_capture_mask); 4212 4213 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4214 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4215 data_collected, (ha->md_dump_size - data_collected)); 4216 4217 /* Decode the entry type and take 4218 * required action to capture debug data */ 4219 switch (entry_hdr->entry_type) { 4220 case QLA82XX_RDEND: 4221 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4222 break; 4223 case QLA82XX_CNTRL: 4224 rval = qla82xx_minidump_process_control(vha, 4225 entry_hdr, &data_ptr); 4226 if (rval != QLA_SUCCESS) { 4227 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4228 goto md_failed; 4229 } 4230 break; 4231 case QLA82XX_RDCRB: 4232 qla82xx_minidump_process_rdcrb(vha, 4233 entry_hdr, &data_ptr); 4234 break; 4235 case QLA82XX_RDMEM: 4236 rval = qla82xx_minidump_process_rdmem(vha, 4237 entry_hdr, &data_ptr); 4238 if (rval != QLA_SUCCESS) { 4239 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4240 goto md_failed; 4241 } 4242 break; 4243 case QLA82XX_BOARD: 4244 case QLA82XX_RDROM: 4245 qla82xx_minidump_process_rdrom(vha, 4246 entry_hdr, &data_ptr); 4247 break; 4248 case QLA82XX_L2DTG: 4249 case QLA82XX_L2ITG: 4250 case QLA82XX_L2DAT: 4251 case QLA82XX_L2INS: 4252 rval = qla82xx_minidump_process_l2tag(vha, 4253 entry_hdr, &data_ptr); 4254 if (rval != QLA_SUCCESS) { 4255 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4256 goto md_failed; 4257 } 4258 break; 4259 case QLA82XX_L1DAT: 4260 case QLA82XX_L1INS: 4261 qla82xx_minidump_process_l1cache(vha, 4262 entry_hdr, &data_ptr); 4263 break; 4264 case QLA82XX_RDOCM: 4265 qla82xx_minidump_process_rdocm(vha, 4266 entry_hdr, &data_ptr); 4267 break; 4268 case QLA82XX_RDMUX: 4269 qla82xx_minidump_process_rdmux(vha, 4270 entry_hdr, &data_ptr); 4271 break; 4272 case QLA82XX_QUEUE: 4273 qla82xx_minidump_process_queue(vha, 4274 entry_hdr, &data_ptr); 4275 break; 4276 case QLA82XX_RDNOP: 4277 default: 4278 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4279 break; 4280 } 4281 4282 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4283 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4284 4285 data_collected = (uint8_t *)data_ptr - 4286 (uint8_t *)ha->md_dump; 4287 skip_nxt_entry: 4288 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4289 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4290 } 4291 4292 if (data_collected != total_data_size) { 4293 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4294 "MiniDump data mismatch: Data collected: [0x%x]," 4295 "total_data_size:[0x%x]\n", 4296 data_collected, total_data_size); 4297 goto md_failed; 4298 } 4299 4300 ql_log(ql_log_info, vha, 0xb044, 4301 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4302 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4303 ha->fw_dumped = 1; 4304 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4305 4306 md_failed: 4307 return rval; 4308 } 4309 4310 int 4311 qla82xx_md_alloc(scsi_qla_host_t *vha) 4312 { 4313 struct qla_hw_data *ha = vha->hw; 4314 int i, k; 4315 struct qla82xx_md_template_hdr *tmplt_hdr; 4316 4317 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4318 4319 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4320 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4321 ql_log(ql_log_info, vha, 0xb045, 4322 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4323 ql2xmdcapmask); 4324 } 4325 4326 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4327 if (i & ql2xmdcapmask) 4328 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4329 } 4330 4331 if (ha->md_dump) { 4332 ql_log(ql_log_warn, vha, 0xb046, 4333 "Firmware dump previously allocated.\n"); 4334 return 1; 4335 } 4336 4337 ha->md_dump = vmalloc(ha->md_dump_size); 4338 if (ha->md_dump == NULL) { 4339 ql_log(ql_log_warn, vha, 0xb047, 4340 "Unable to allocate memory for Minidump size " 4341 "(0x%x).\n", ha->md_dump_size); 4342 return 1; 4343 } 4344 return 0; 4345 } 4346 4347 void 4348 qla82xx_md_free(scsi_qla_host_t *vha) 4349 { 4350 struct qla_hw_data *ha = vha->hw; 4351 4352 /* Release the template header allocated */ 4353 if (ha->md_tmplt_hdr) { 4354 ql_log(ql_log_info, vha, 0xb048, 4355 "Free MiniDump template: %p, size (%d KB)\n", 4356 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4357 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4358 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4359 ha->md_tmplt_hdr = NULL; 4360 } 4361 4362 /* Release the template data buffer allocated */ 4363 if (ha->md_dump) { 4364 ql_log(ql_log_info, vha, 0xb049, 4365 "Free MiniDump memory: %p, size (%d KB)\n", 4366 ha->md_dump, ha->md_dump_size / 1024); 4367 vfree(ha->md_dump); 4368 ha->md_dump_size = 0; 4369 ha->md_dump = NULL; 4370 } 4371 } 4372 4373 void 4374 qla82xx_md_prep(scsi_qla_host_t *vha) 4375 { 4376 struct qla_hw_data *ha = vha->hw; 4377 int rval; 4378 4379 /* Get Minidump template size */ 4380 rval = qla82xx_md_get_template_size(vha); 4381 if (rval == QLA_SUCCESS) { 4382 ql_log(ql_log_info, vha, 0xb04a, 4383 "MiniDump Template size obtained (%d KB)\n", 4384 ha->md_template_size / 1024); 4385 4386 /* Get Minidump template */ 4387 rval = qla82xx_md_get_template(vha); 4388 if (rval == QLA_SUCCESS) { 4389 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4390 "MiniDump Template obtained\n"); 4391 4392 /* Allocate memory for minidump */ 4393 rval = qla82xx_md_alloc(vha); 4394 if (rval == QLA_SUCCESS) 4395 ql_log(ql_log_info, vha, 0xb04c, 4396 "MiniDump memory allocated (%d KB)\n", 4397 ha->md_dump_size / 1024); 4398 else { 4399 ql_log(ql_log_info, vha, 0xb04d, 4400 "Free MiniDump template: %p, size: (%d KB)\n", 4401 ha->md_tmplt_hdr, 4402 ha->md_template_size / 1024); 4403 dma_free_coherent(&ha->pdev->dev, 4404 ha->md_template_size, 4405 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4406 ha->md_tmplt_hdr = NULL; 4407 } 4408 4409 } 4410 } 4411 } 4412 4413 int 4414 qla82xx_beacon_on(struct scsi_qla_host *vha) 4415 { 4416 4417 int rval; 4418 struct qla_hw_data *ha = vha->hw; 4419 qla82xx_idc_lock(ha); 4420 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4421 4422 if (rval) { 4423 ql_log(ql_log_warn, vha, 0xb050, 4424 "mbx set led config failed in %s\n", __func__); 4425 goto exit; 4426 } 4427 ha->beacon_blink_led = 1; 4428 exit: 4429 qla82xx_idc_unlock(ha); 4430 return rval; 4431 } 4432 4433 int 4434 qla82xx_beacon_off(struct scsi_qla_host *vha) 4435 { 4436 4437 int rval; 4438 struct qla_hw_data *ha = vha->hw; 4439 qla82xx_idc_lock(ha); 4440 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4441 4442 if (rval) { 4443 ql_log(ql_log_warn, vha, 0xb051, 4444 "mbx set led config failed in %s\n", __func__); 4445 goto exit; 4446 } 4447 ha->beacon_blink_led = 0; 4448 exit: 4449 qla82xx_idc_unlock(ha); 4450 return rval; 4451 } 4452