1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include "qla_gbl.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 13 #include "qla_devtbl.h" 14 15 #ifdef CONFIG_SPARC 16 #include <asm/prom.h> 17 #endif 18 19 #include "qla_target.h" 20 21 /* 22 * QLogic ISP2x00 Hardware Support Function Prototypes. 23 */ 24 static int qla2x00_isp_firmware(scsi_qla_host_t *); 25 static int qla2x00_setup_chip(scsi_qla_host_t *); 26 static int qla2x00_fw_ready(scsi_qla_host_t *); 27 static int qla2x00_configure_hba(scsi_qla_host_t *); 28 static int qla2x00_configure_loop(scsi_qla_host_t *); 29 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 30 static int qla2x00_configure_fabric(scsi_qla_host_t *); 31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 32 static int qla2x00_restart_isp(scsi_qla_host_t *); 33 34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 35 static int qla84xx_init_chip(scsi_qla_host_t *); 36 static int qla25xx_init_queues(struct qla_hw_data *); 37 static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *); 38 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, 39 struct event_arg *ea); 40 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *, 41 struct event_arg *); 42 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *); 43 44 /* SRB Extensions ---------------------------------------------------------- */ 45 46 void 47 qla2x00_sp_timeout(struct timer_list *t) 48 { 49 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer); 50 struct srb_iocb *iocb; 51 52 WARN_ON(irqs_disabled()); 53 iocb = &sp->u.iocb_cmd; 54 iocb->timeout(sp); 55 } 56 57 void qla2x00_sp_free(srb_t *sp) 58 { 59 struct srb_iocb *iocb = &sp->u.iocb_cmd; 60 61 del_timer(&iocb->timer); 62 qla2x00_rel_sp(sp); 63 } 64 65 void qla2xxx_rel_done_warning(srb_t *sp, int res) 66 { 67 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp); 68 } 69 70 void qla2xxx_rel_free_warning(srb_t *sp) 71 { 72 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp); 73 } 74 75 /* Asynchronous Login/Logout Routines -------------------------------------- */ 76 77 unsigned long 78 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 79 { 80 unsigned long tmo; 81 struct qla_hw_data *ha = vha->hw; 82 83 /* Firmware should use switch negotiated r_a_tov for timeout. */ 84 tmo = ha->r_a_tov / 10 * 2; 85 if (IS_QLAFX00(ha)) { 86 tmo = FX00_DEF_RATOV * 2; 87 } else if (!IS_FWI2_CAPABLE(ha)) { 88 /* 89 * Except for earlier ISPs where the timeout is seeded from the 90 * initialization control block. 91 */ 92 tmo = ha->login_timeout; 93 } 94 return tmo; 95 } 96 97 static void qla24xx_abort_iocb_timeout(void *data) 98 { 99 srb_t *sp = data; 100 struct srb_iocb *abt = &sp->u.iocb_cmd; 101 struct qla_qpair *qpair = sp->qpair; 102 u32 handle; 103 unsigned long flags; 104 105 if (sp->cmd_sp) 106 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 107 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n", 108 sp->cmd_sp->handle, sp->cmd_sp->type, 109 sp->handle, sp->type); 110 else 111 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 112 "Abort timeout 2 - hdl=%x, type=%x\n", 113 sp->handle, sp->type); 114 115 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 116 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) { 117 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] == 118 sp->cmd_sp)) 119 qpair->req->outstanding_cmds[handle] = NULL; 120 121 /* removing the abort */ 122 if (qpair->req->outstanding_cmds[handle] == sp) { 123 qpair->req->outstanding_cmds[handle] = NULL; 124 break; 125 } 126 } 127 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 128 129 if (sp->cmd_sp) 130 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED); 131 132 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT); 133 sp->done(sp, QLA_OS_TIMER_EXPIRED); 134 } 135 136 static void qla24xx_abort_sp_done(srb_t *sp, int res) 137 { 138 struct srb_iocb *abt = &sp->u.iocb_cmd; 139 srb_t *orig_sp = sp->cmd_sp; 140 141 if (orig_sp) 142 qla_wait_nvme_release_cmd_kref(orig_sp); 143 144 del_timer(&sp->u.iocb_cmd.timer); 145 if (sp->flags & SRB_WAKEUP_ON_COMP) 146 complete(&abt->u.abt.comp); 147 else 148 sp->free(sp); 149 } 150 151 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait) 152 { 153 scsi_qla_host_t *vha = cmd_sp->vha; 154 struct srb_iocb *abt_iocb; 155 srb_t *sp; 156 int rval = QLA_FUNCTION_FAILED; 157 158 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport, 159 GFP_ATOMIC); 160 if (!sp) 161 return rval; 162 163 abt_iocb = &sp->u.iocb_cmd; 164 sp->type = SRB_ABT_CMD; 165 sp->name = "abort"; 166 sp->qpair = cmd_sp->qpair; 167 sp->cmd_sp = cmd_sp; 168 if (wait) 169 sp->flags = SRB_WAKEUP_ON_COMP; 170 171 abt_iocb->timeout = qla24xx_abort_iocb_timeout; 172 init_completion(&abt_iocb->u.abt.comp); 173 /* FW can send 2 x ABTS's timeout/20s */ 174 qla2x00_init_timer(sp, 42); 175 176 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 177 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id); 178 179 sp->done = qla24xx_abort_sp_done; 180 181 ql_dbg(ql_dbg_async, vha, 0x507c, 182 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle, 183 cmd_sp->type); 184 185 rval = qla2x00_start_sp(sp); 186 if (rval != QLA_SUCCESS) { 187 sp->free(sp); 188 return rval; 189 } 190 191 if (wait) { 192 wait_for_completion(&abt_iocb->u.abt.comp); 193 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 194 QLA_SUCCESS : QLA_FUNCTION_FAILED; 195 sp->free(sp); 196 } 197 198 return rval; 199 } 200 201 void 202 qla2x00_async_iocb_timeout(void *data) 203 { 204 srb_t *sp = data; 205 fc_port_t *fcport = sp->fcport; 206 struct srb_iocb *lio = &sp->u.iocb_cmd; 207 int rc, h; 208 unsigned long flags; 209 210 if (fcport) { 211 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 212 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 213 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 214 215 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 216 } else { 217 pr_info("Async-%s timeout - hdl=%x.\n", 218 sp->name, sp->handle); 219 } 220 221 switch (sp->type) { 222 case SRB_LOGIN_CMD: 223 rc = qla24xx_async_abort_cmd(sp, false); 224 if (rc) { 225 /* Retry as needed. */ 226 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 227 lio->u.logio.data[1] = 228 lio->u.logio.flags & SRB_LOGIN_RETRIED ? 229 QLA_LOGIO_LOGIN_RETRIED : 0; 230 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 231 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 232 h++) { 233 if (sp->qpair->req->outstanding_cmds[h] == 234 sp) { 235 sp->qpair->req->outstanding_cmds[h] = 236 NULL; 237 break; 238 } 239 } 240 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 241 sp->done(sp, QLA_FUNCTION_TIMEOUT); 242 } 243 break; 244 case SRB_LOGOUT_CMD: 245 case SRB_CT_PTHRU_CMD: 246 case SRB_MB_IOCB: 247 case SRB_NACK_PLOGI: 248 case SRB_NACK_PRLI: 249 case SRB_NACK_LOGO: 250 case SRB_CTRL_VP: 251 default: 252 rc = qla24xx_async_abort_cmd(sp, false); 253 if (rc) { 254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 256 h++) { 257 if (sp->qpair->req->outstanding_cmds[h] == 258 sp) { 259 sp->qpair->req->outstanding_cmds[h] = 260 NULL; 261 break; 262 } 263 } 264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 265 sp->done(sp, QLA_FUNCTION_TIMEOUT); 266 } 267 break; 268 } 269 } 270 271 static void qla2x00_async_login_sp_done(srb_t *sp, int res) 272 { 273 struct scsi_qla_host *vha = sp->vha; 274 struct srb_iocb *lio = &sp->u.iocb_cmd; 275 struct event_arg ea; 276 277 ql_dbg(ql_dbg_disc, vha, 0x20dd, 278 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 279 280 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 281 282 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 283 memset(&ea, 0, sizeof(ea)); 284 ea.fcport = sp->fcport; 285 ea.data[0] = lio->u.logio.data[0]; 286 ea.data[1] = lio->u.logio.data[1]; 287 ea.iop[0] = lio->u.logio.iop[0]; 288 ea.iop[1] = lio->u.logio.iop[1]; 289 ea.sp = sp; 290 qla24xx_handle_plogi_done_event(vha, &ea); 291 } 292 293 sp->free(sp); 294 } 295 296 static inline bool 297 fcport_is_smaller(fc_port_t *fcport) 298 { 299 if (wwn_to_u64(fcport->port_name) < 300 wwn_to_u64(fcport->vha->port_name)) 301 return true; 302 else 303 return false; 304 } 305 306 static inline bool 307 fcport_is_bigger(fc_port_t *fcport) 308 { 309 return !fcport_is_smaller(fcport); 310 } 311 312 int 313 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 314 uint16_t *data) 315 { 316 srb_t *sp; 317 struct srb_iocb *lio; 318 int rval = QLA_FUNCTION_FAILED; 319 320 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 321 fcport->loop_id == FC_NO_LOOP_ID) { 322 ql_log(ql_log_warn, vha, 0xffff, 323 "%s: %8phC - not sending command.\n", 324 __func__, fcport->port_name); 325 return rval; 326 } 327 328 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 329 if (!sp) 330 goto done; 331 332 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 333 fcport->flags |= FCF_ASYNC_SENT; 334 fcport->logout_completed = 0; 335 336 sp->type = SRB_LOGIN_CMD; 337 sp->name = "login"; 338 sp->gen1 = fcport->rscn_gen; 339 sp->gen2 = fcport->login_gen; 340 341 lio = &sp->u.iocb_cmd; 342 lio->timeout = qla2x00_async_iocb_timeout; 343 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 344 345 sp->done = qla2x00_async_login_sp_done; 346 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) 347 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY; 348 else 349 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 350 351 if (NVME_TARGET(vha->hw, fcport)) 352 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI; 353 354 ql_log(ql_log_warn, vha, 0x2072, 355 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x retries=%d.\n", 356 fcport->port_name, sp->handle, fcport->loop_id, 357 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 358 fcport->login_retry); 359 360 rval = qla2x00_start_sp(sp); 361 if (rval != QLA_SUCCESS) { 362 fcport->flags |= FCF_LOGIN_NEEDED; 363 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 364 goto done_free_sp; 365 } 366 367 return rval; 368 369 done_free_sp: 370 sp->free(sp); 371 fcport->flags &= ~FCF_ASYNC_SENT; 372 done: 373 fcport->flags &= ~FCF_ASYNC_ACTIVE; 374 return rval; 375 } 376 377 static void qla2x00_async_logout_sp_done(srb_t *sp, int res) 378 { 379 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 380 sp->fcport->login_gen++; 381 qlt_logo_completion_handler(sp->fcport, res); 382 sp->free(sp); 383 } 384 385 int 386 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 387 { 388 srb_t *sp; 389 struct srb_iocb *lio; 390 int rval = QLA_FUNCTION_FAILED; 391 392 fcport->flags |= FCF_ASYNC_SENT; 393 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 394 if (!sp) 395 goto done; 396 397 sp->type = SRB_LOGOUT_CMD; 398 sp->name = "logout"; 399 400 lio = &sp->u.iocb_cmd; 401 lio->timeout = qla2x00_async_iocb_timeout; 402 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 403 404 sp->done = qla2x00_async_logout_sp_done; 405 406 ql_dbg(ql_dbg_disc, vha, 0x2070, 407 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n", 408 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 409 fcport->d_id.b.area, fcport->d_id.b.al_pa, 410 fcport->port_name); 411 412 rval = qla2x00_start_sp(sp); 413 if (rval != QLA_SUCCESS) 414 goto done_free_sp; 415 return rval; 416 417 done_free_sp: 418 sp->free(sp); 419 done: 420 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 421 return rval; 422 } 423 424 void 425 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport, 426 uint16_t *data) 427 { 428 fcport->flags &= ~FCF_ASYNC_ACTIVE; 429 /* Don't re-login in target mode */ 430 if (!fcport->tgt_session) 431 qla2x00_mark_device_lost(vha, fcport, 1); 432 qlt_logo_completion_handler(fcport, data[0]); 433 } 434 435 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res) 436 { 437 struct srb_iocb *lio = &sp->u.iocb_cmd; 438 struct scsi_qla_host *vha = sp->vha; 439 440 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE; 441 if (!test_bit(UNLOADING, &vha->dpc_flags)) 442 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport, 443 lio->u.logio.data); 444 sp->free(sp); 445 } 446 447 int 448 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport) 449 { 450 srb_t *sp; 451 struct srb_iocb *lio; 452 int rval; 453 454 rval = QLA_FUNCTION_FAILED; 455 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 456 if (!sp) 457 goto done; 458 459 sp->type = SRB_PRLO_CMD; 460 sp->name = "prlo"; 461 462 lio = &sp->u.iocb_cmd; 463 lio->timeout = qla2x00_async_iocb_timeout; 464 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 465 466 sp->done = qla2x00_async_prlo_sp_done; 467 468 ql_dbg(ql_dbg_disc, vha, 0x2070, 469 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 470 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 471 fcport->d_id.b.area, fcport->d_id.b.al_pa); 472 473 rval = qla2x00_start_sp(sp); 474 if (rval != QLA_SUCCESS) 475 goto done_free_sp; 476 477 return rval; 478 479 done_free_sp: 480 sp->free(sp); 481 done: 482 fcport->flags &= ~FCF_ASYNC_ACTIVE; 483 return rval; 484 } 485 486 static 487 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea) 488 { 489 struct fc_port *fcport = ea->fcport; 490 491 ql_dbg(ql_dbg_disc, vha, 0x20d2, 492 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n", 493 __func__, fcport->port_name, fcport->disc_state, 494 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2, 495 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id); 496 497 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 498 ea->data[0]); 499 500 if (ea->data[0] != MBS_COMMAND_COMPLETE) { 501 ql_dbg(ql_dbg_disc, vha, 0x2066, 502 "%s %8phC: adisc fail: post delete\n", 503 __func__, ea->fcport->port_name); 504 /* deleted = 0 & logout_on_delete = force fw cleanup */ 505 fcport->deleted = 0; 506 fcport->logout_on_delete = 1; 507 qlt_schedule_sess_for_deletion(ea->fcport); 508 return; 509 } 510 511 if (ea->fcport->disc_state == DSC_DELETE_PEND) 512 return; 513 514 if (ea->sp->gen2 != ea->fcport->login_gen) { 515 /* target side must have changed it. */ 516 ql_dbg(ql_dbg_disc, vha, 0x20d3, 517 "%s %8phC generation changed\n", 518 __func__, ea->fcport->port_name); 519 return; 520 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) { 521 qla_rscn_replay(fcport); 522 qlt_schedule_sess_for_deletion(fcport); 523 return; 524 } 525 526 __qla24xx_handle_gpdb_event(vha, ea); 527 } 528 529 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport) 530 { 531 struct qla_work_evt *e; 532 533 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI); 534 if (!e) 535 return QLA_FUNCTION_FAILED; 536 537 e->u.fcport.fcport = fcport; 538 fcport->flags |= FCF_ASYNC_ACTIVE; 539 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 540 return qla2x00_post_work(vha, e); 541 } 542 543 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res) 544 { 545 struct scsi_qla_host *vha = sp->vha; 546 struct event_arg ea; 547 struct srb_iocb *lio = &sp->u.iocb_cmd; 548 549 ql_dbg(ql_dbg_disc, vha, 0x2066, 550 "Async done-%s res %x %8phC\n", 551 sp->name, res, sp->fcport->port_name); 552 553 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 554 555 memset(&ea, 0, sizeof(ea)); 556 ea.rc = res; 557 ea.data[0] = lio->u.logio.data[0]; 558 ea.data[1] = lio->u.logio.data[1]; 559 ea.iop[0] = lio->u.logio.iop[0]; 560 ea.iop[1] = lio->u.logio.iop[1]; 561 ea.fcport = sp->fcport; 562 ea.sp = sp; 563 564 qla24xx_handle_adisc_event(vha, &ea); 565 566 sp->free(sp); 567 } 568 569 int 570 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 571 uint16_t *data) 572 { 573 srb_t *sp; 574 struct srb_iocb *lio; 575 int rval = QLA_FUNCTION_FAILED; 576 577 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 578 return rval; 579 580 fcport->flags |= FCF_ASYNC_SENT; 581 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 582 if (!sp) 583 goto done; 584 585 sp->type = SRB_ADISC_CMD; 586 sp->name = "adisc"; 587 588 lio = &sp->u.iocb_cmd; 589 lio->timeout = qla2x00_async_iocb_timeout; 590 sp->gen1 = fcport->rscn_gen; 591 sp->gen2 = fcport->login_gen; 592 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 593 594 sp->done = qla2x00_async_adisc_sp_done; 595 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 596 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 597 598 ql_dbg(ql_dbg_disc, vha, 0x206f, 599 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n", 600 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name); 601 602 rval = qla2x00_start_sp(sp); 603 if (rval != QLA_SUCCESS) 604 goto done_free_sp; 605 606 return rval; 607 608 done_free_sp: 609 sp->free(sp); 610 done: 611 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 612 qla2x00_post_async_adisc_work(vha, fcport, data); 613 return rval; 614 } 615 616 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id) 617 { 618 struct qla_hw_data *ha = vha->hw; 619 620 if (IS_FWI2_CAPABLE(ha)) 621 return loop_id > NPH_LAST_HANDLE; 622 623 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) || 624 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST; 625 } 626 627 /** 628 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID 629 * @vha: adapter state pointer. 630 * @dev: port structure pointer. 631 * 632 * Returns: 633 * qla2x00 local function return status code. 634 * 635 * Context: 636 * Kernel context. 637 */ 638 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 639 { 640 int rval; 641 struct qla_hw_data *ha = vha->hw; 642 unsigned long flags = 0; 643 644 rval = QLA_SUCCESS; 645 646 spin_lock_irqsave(&ha->vport_slock, flags); 647 648 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE); 649 if (dev->loop_id >= LOOPID_MAP_SIZE || 650 qla2x00_is_reserved_id(vha, dev->loop_id)) { 651 dev->loop_id = FC_NO_LOOP_ID; 652 rval = QLA_FUNCTION_FAILED; 653 } else { 654 set_bit(dev->loop_id, ha->loop_id_map); 655 } 656 spin_unlock_irqrestore(&ha->vport_slock, flags); 657 658 if (rval == QLA_SUCCESS) 659 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 660 "Assigning new loopid=%x, portid=%x.\n", 661 dev->loop_id, dev->d_id.b24); 662 else 663 ql_log(ql_log_warn, dev->vha, 0x2087, 664 "No loop_id's available, portid=%x.\n", 665 dev->d_id.b24); 666 667 return rval; 668 } 669 670 void qla2x00_clear_loop_id(fc_port_t *fcport) 671 { 672 struct qla_hw_data *ha = fcport->vha->hw; 673 674 if (fcport->loop_id == FC_NO_LOOP_ID || 675 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id)) 676 return; 677 678 clear_bit(fcport->loop_id, ha->loop_id_map); 679 fcport->loop_id = FC_NO_LOOP_ID; 680 } 681 682 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 683 struct event_arg *ea) 684 { 685 fc_port_t *fcport, *conflict_fcport; 686 struct get_name_list_extended *e; 687 u16 i, n, found = 0, loop_id; 688 port_id_t id; 689 u64 wwn; 690 u16 data[2]; 691 u8 current_login_state, nvme_cls; 692 693 fcport = ea->fcport; 694 ql_dbg(ql_dbg_disc, vha, 0xffff, 695 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n", 696 __func__, fcport->port_name, fcport->disc_state, 697 fcport->fw_login_state, ea->rc, 698 fcport->login_gen, fcport->last_login_gen, 699 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id); 700 701 if (fcport->disc_state == DSC_DELETE_PEND) 702 return; 703 704 if (ea->rc) { /* rval */ 705 if (fcport->login_retry == 0) { 706 ql_dbg(ql_dbg_disc, vha, 0x20de, 707 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 708 fcport->port_name, fcport->login_retry); 709 } 710 return; 711 } 712 713 if (fcport->last_rscn_gen != fcport->rscn_gen) { 714 qla_rscn_replay(fcport); 715 qlt_schedule_sess_for_deletion(fcport); 716 return; 717 } else if (fcport->last_login_gen != fcport->login_gen) { 718 ql_dbg(ql_dbg_disc, vha, 0x20e0, 719 "%s %8phC login gen changed\n", 720 __func__, fcport->port_name); 721 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 722 return; 723 } 724 725 n = ea->data[0] / sizeof(struct get_name_list_extended); 726 727 ql_dbg(ql_dbg_disc, vha, 0x20e1, 728 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 729 __func__, __LINE__, fcport->port_name, n, 730 fcport->d_id.b.domain, fcport->d_id.b.area, 731 fcport->d_id.b.al_pa, fcport->loop_id); 732 733 for (i = 0; i < n; i++) { 734 e = &vha->gnl.l[i]; 735 wwn = wwn_to_u64(e->port_name); 736 id.b.domain = e->port_id[2]; 737 id.b.area = e->port_id[1]; 738 id.b.al_pa = e->port_id[0]; 739 id.b.rsvd_1 = 0; 740 741 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 742 continue; 743 744 if (IS_SW_RESV_ADDR(id)) 745 continue; 746 747 found = 1; 748 749 loop_id = le16_to_cpu(e->nport_handle); 750 loop_id = (loop_id & 0x7fff); 751 nvme_cls = e->current_login_state >> 4; 752 current_login_state = e->current_login_state & 0xf; 753 754 if (PRLI_PHASE(nvme_cls)) { 755 current_login_state = nvme_cls; 756 fcport->fc4_type &= ~FS_FC4TYPE_FCP; 757 fcport->fc4_type |= FS_FC4TYPE_NVME; 758 } else if (PRLI_PHASE(current_login_state)) { 759 fcport->fc4_type |= FS_FC4TYPE_FCP; 760 fcport->fc4_type &= ~FS_FC4TYPE_NVME; 761 } 762 763 ql_dbg(ql_dbg_disc, vha, 0x20e2, 764 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n", 765 __func__, fcport->port_name, 766 e->current_login_state, fcport->fw_login_state, 767 fcport->fc4_type, id.b24, fcport->d_id.b24, 768 loop_id, fcport->loop_id); 769 770 switch (fcport->disc_state) { 771 case DSC_DELETE_PEND: 772 case DSC_DELETED: 773 break; 774 default: 775 if ((id.b24 != fcport->d_id.b24 && 776 fcport->d_id.b24 && 777 fcport->loop_id != FC_NO_LOOP_ID) || 778 (fcport->loop_id != FC_NO_LOOP_ID && 779 fcport->loop_id != loop_id)) { 780 ql_dbg(ql_dbg_disc, vha, 0x20e3, 781 "%s %d %8phC post del sess\n", 782 __func__, __LINE__, fcport->port_name); 783 if (fcport->n2n_flag) 784 fcport->d_id.b24 = 0; 785 qlt_schedule_sess_for_deletion(fcport); 786 return; 787 } 788 break; 789 } 790 791 fcport->loop_id = loop_id; 792 if (fcport->n2n_flag) 793 fcport->d_id.b24 = id.b24; 794 795 wwn = wwn_to_u64(fcport->port_name); 796 qlt_find_sess_invalidate_other(vha, wwn, 797 id, loop_id, &conflict_fcport); 798 799 if (conflict_fcport) { 800 /* 801 * Another share fcport share the same loop_id & 802 * nport id. Conflict fcport needs to finish 803 * cleanup before this fcport can proceed to login. 804 */ 805 conflict_fcport->conflict = fcport; 806 fcport->login_pause = 1; 807 } 808 809 switch (vha->hw->current_topology) { 810 default: 811 switch (current_login_state) { 812 case DSC_LS_PRLI_COMP: 813 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 814 vha, 0x20e4, "%s %d %8phC post gpdb\n", 815 __func__, __LINE__, fcport->port_name); 816 817 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 818 fcport->port_type = FCT_INITIATOR; 819 else 820 fcport->port_type = FCT_TARGET; 821 data[0] = data[1] = 0; 822 qla2x00_post_async_adisc_work(vha, fcport, 823 data); 824 break; 825 case DSC_LS_PORT_UNAVAIL: 826 default: 827 if (fcport->loop_id == FC_NO_LOOP_ID) { 828 qla2x00_find_new_loop_id(vha, fcport); 829 fcport->fw_login_state = 830 DSC_LS_PORT_UNAVAIL; 831 } 832 ql_dbg(ql_dbg_disc, vha, 0x20e5, 833 "%s %d %8phC\n", __func__, __LINE__, 834 fcport->port_name); 835 qla24xx_fcport_handle_login(vha, fcport); 836 break; 837 } 838 break; 839 case ISP_CFG_N: 840 fcport->fw_login_state = current_login_state; 841 fcport->d_id = id; 842 switch (current_login_state) { 843 case DSC_LS_PRLI_PEND: 844 /* 845 * In the middle of PRLI. Let it finish. 846 * Allow relogin code to recheck state again 847 * with GNL. Push disc_state back to DELETED 848 * so GNL can go out again 849 */ 850 qla2x00_set_fcport_disc_state(fcport, 851 DSC_DELETED); 852 break; 853 case DSC_LS_PRLI_COMP: 854 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 855 fcport->port_type = FCT_INITIATOR; 856 else 857 fcport->port_type = FCT_TARGET; 858 859 data[0] = data[1] = 0; 860 qla2x00_post_async_adisc_work(vha, fcport, 861 data); 862 break; 863 case DSC_LS_PLOGI_COMP: 864 if (fcport_is_bigger(fcport)) { 865 /* local adapter is smaller */ 866 if (fcport->loop_id != FC_NO_LOOP_ID) 867 qla2x00_clear_loop_id(fcport); 868 869 fcport->loop_id = loop_id; 870 qla24xx_fcport_handle_login(vha, 871 fcport); 872 break; 873 } 874 fallthrough; 875 default: 876 if (fcport_is_smaller(fcport)) { 877 /* local adapter is bigger */ 878 if (fcport->loop_id != FC_NO_LOOP_ID) 879 qla2x00_clear_loop_id(fcport); 880 881 fcport->loop_id = loop_id; 882 qla24xx_fcport_handle_login(vha, 883 fcport); 884 } 885 break; 886 } 887 break; 888 } /* switch (ha->current_topology) */ 889 } 890 891 if (!found) { 892 switch (vha->hw->current_topology) { 893 case ISP_CFG_F: 894 case ISP_CFG_FL: 895 for (i = 0; i < n; i++) { 896 e = &vha->gnl.l[i]; 897 id.b.domain = e->port_id[0]; 898 id.b.area = e->port_id[1]; 899 id.b.al_pa = e->port_id[2]; 900 id.b.rsvd_1 = 0; 901 loop_id = le16_to_cpu(e->nport_handle); 902 903 if (fcport->d_id.b24 == id.b24) { 904 conflict_fcport = 905 qla2x00_find_fcport_by_wwpn(vha, 906 e->port_name, 0); 907 if (conflict_fcport) { 908 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 909 vha, 0x20e5, 910 "%s %d %8phC post del sess\n", 911 __func__, __LINE__, 912 conflict_fcport->port_name); 913 qlt_schedule_sess_for_deletion 914 (conflict_fcport); 915 } 916 } 917 /* 918 * FW already picked this loop id for 919 * another fcport 920 */ 921 if (fcport->loop_id == loop_id) 922 fcport->loop_id = FC_NO_LOOP_ID; 923 } 924 qla24xx_fcport_handle_login(vha, fcport); 925 break; 926 case ISP_CFG_N: 927 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 928 if (time_after_eq(jiffies, fcport->dm_login_expire)) { 929 if (fcport->n2n_link_reset_cnt < 2) { 930 fcport->n2n_link_reset_cnt++; 931 /* 932 * remote port is not sending PLOGI. 933 * Reset link to kick start his state 934 * machine 935 */ 936 set_bit(N2N_LINK_RESET, 937 &vha->dpc_flags); 938 } else { 939 if (fcport->n2n_chip_reset < 1) { 940 ql_log(ql_log_info, vha, 0x705d, 941 "Chip reset to bring laser down"); 942 set_bit(ISP_ABORT_NEEDED, 943 &vha->dpc_flags); 944 fcport->n2n_chip_reset++; 945 } else { 946 ql_log(ql_log_info, vha, 0x705d, 947 "Remote port %8ph is not coming back\n", 948 fcport->port_name); 949 fcport->scan_state = 0; 950 } 951 } 952 qla2xxx_wake_dpc(vha); 953 } else { 954 /* 955 * report port suppose to do PLOGI. Give him 956 * more time. FW will catch it. 957 */ 958 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 959 } 960 break; 961 default: 962 break; 963 } 964 } 965 } /* gnl_event */ 966 967 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res) 968 { 969 struct scsi_qla_host *vha = sp->vha; 970 unsigned long flags; 971 struct fc_port *fcport = NULL, *tf; 972 u16 i, n = 0, loop_id; 973 struct event_arg ea; 974 struct get_name_list_extended *e; 975 u64 wwn; 976 struct list_head h; 977 bool found = false; 978 979 ql_dbg(ql_dbg_disc, vha, 0x20e7, 980 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 981 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 982 sp->u.iocb_cmd.u.mbx.in_mb[2]); 983 984 if (res == QLA_FUNCTION_TIMEOUT) 985 return; 986 987 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE); 988 memset(&ea, 0, sizeof(ea)); 989 ea.sp = sp; 990 ea.rc = res; 991 992 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 993 sizeof(struct get_name_list_extended)) { 994 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 995 sizeof(struct get_name_list_extended); 996 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 997 } 998 999 for (i = 0; i < n; i++) { 1000 e = &vha->gnl.l[i]; 1001 loop_id = le16_to_cpu(e->nport_handle); 1002 /* mask out reserve bit */ 1003 loop_id = (loop_id & 0x7fff); 1004 set_bit(loop_id, vha->hw->loop_id_map); 1005 wwn = wwn_to_u64(e->port_name); 1006 1007 ql_dbg(ql_dbg_disc, vha, 0x20e8, 1008 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n", 1009 __func__, &wwn, e->port_id[2], e->port_id[1], 1010 e->port_id[0], e->current_login_state, e->last_login_state, 1011 (loop_id & 0x7fff)); 1012 } 1013 1014 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1015 1016 INIT_LIST_HEAD(&h); 1017 fcport = tf = NULL; 1018 if (!list_empty(&vha->gnl.fcports)) 1019 list_splice_init(&vha->gnl.fcports, &h); 1020 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1021 1022 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 1023 list_del_init(&fcport->gnl_entry); 1024 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1025 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1026 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1027 ea.fcport = fcport; 1028 1029 qla24xx_handle_gnl_done_event(vha, &ea); 1030 } 1031 1032 /* create new fcport if fw has knowledge of new sessions */ 1033 for (i = 0; i < n; i++) { 1034 port_id_t id; 1035 u64 wwnn; 1036 1037 e = &vha->gnl.l[i]; 1038 wwn = wwn_to_u64(e->port_name); 1039 1040 found = false; 1041 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) { 1042 if (!memcmp((u8 *)&wwn, fcport->port_name, 1043 WWN_SIZE)) { 1044 found = true; 1045 break; 1046 } 1047 } 1048 1049 id.b.domain = e->port_id[2]; 1050 id.b.area = e->port_id[1]; 1051 id.b.al_pa = e->port_id[0]; 1052 id.b.rsvd_1 = 0; 1053 1054 if (!found && wwn && !IS_SW_RESV_ADDR(id)) { 1055 ql_dbg(ql_dbg_disc, vha, 0x2065, 1056 "%s %d %8phC %06x post new sess\n", 1057 __func__, __LINE__, (u8 *)&wwn, id.b24); 1058 wwnn = wwn_to_u64(e->node_name); 1059 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn, 1060 (u8 *)&wwnn, NULL, 0); 1061 } 1062 } 1063 1064 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1065 vha->gnl.sent = 0; 1066 if (!list_empty(&vha->gnl.fcports)) { 1067 /* retrigger gnl */ 1068 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports, 1069 gnl_entry) { 1070 list_del_init(&fcport->gnl_entry); 1071 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1072 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS) 1073 break; 1074 } 1075 } 1076 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1077 1078 sp->free(sp); 1079 } 1080 1081 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 1082 { 1083 srb_t *sp; 1084 struct srb_iocb *mbx; 1085 int rval = QLA_FUNCTION_FAILED; 1086 unsigned long flags; 1087 u16 *mb; 1088 1089 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 1090 return rval; 1091 1092 ql_dbg(ql_dbg_disc, vha, 0x20d9, 1093 "Async-gnlist WWPN %8phC \n", fcport->port_name); 1094 1095 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1096 fcport->flags |= FCF_ASYNC_SENT; 1097 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1098 fcport->last_rscn_gen = fcport->rscn_gen; 1099 fcport->last_login_gen = fcport->login_gen; 1100 1101 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 1102 if (vha->gnl.sent) { 1103 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1104 return QLA_SUCCESS; 1105 } 1106 vha->gnl.sent = 1; 1107 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1108 1109 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1110 if (!sp) 1111 goto done; 1112 1113 sp->type = SRB_MB_IOCB; 1114 sp->name = "gnlist"; 1115 sp->gen1 = fcport->rscn_gen; 1116 sp->gen2 = fcport->login_gen; 1117 1118 mbx = &sp->u.iocb_cmd; 1119 mbx->timeout = qla2x00_async_iocb_timeout; 1120 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2); 1121 1122 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1123 mb[0] = MBC_PORT_NODE_NAME_LIST; 1124 mb[1] = BIT_2 | BIT_3; 1125 mb[2] = MSW(vha->gnl.ldma); 1126 mb[3] = LSW(vha->gnl.ldma); 1127 mb[6] = MSW(MSD(vha->gnl.ldma)); 1128 mb[7] = LSW(MSD(vha->gnl.ldma)); 1129 mb[8] = vha->gnl.size; 1130 mb[9] = vha->vp_idx; 1131 1132 sp->done = qla24xx_async_gnl_sp_done; 1133 1134 ql_dbg(ql_dbg_disc, vha, 0x20da, 1135 "Async-%s - OUT WWPN %8phC hndl %x\n", 1136 sp->name, fcport->port_name, sp->handle); 1137 1138 rval = qla2x00_start_sp(sp); 1139 if (rval != QLA_SUCCESS) 1140 goto done_free_sp; 1141 1142 return rval; 1143 1144 done_free_sp: 1145 sp->free(sp); 1146 done: 1147 fcport->flags &= ~(FCF_ASYNC_ACTIVE | FCF_ASYNC_SENT); 1148 return rval; 1149 } 1150 1151 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1152 { 1153 struct qla_work_evt *e; 1154 1155 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 1156 if (!e) 1157 return QLA_FUNCTION_FAILED; 1158 1159 e->u.fcport.fcport = fcport; 1160 fcport->flags |= FCF_ASYNC_ACTIVE; 1161 return qla2x00_post_work(vha, e); 1162 } 1163 1164 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res) 1165 { 1166 struct scsi_qla_host *vha = sp->vha; 1167 struct qla_hw_data *ha = vha->hw; 1168 fc_port_t *fcport = sp->fcport; 1169 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 1170 struct event_arg ea; 1171 1172 ql_dbg(ql_dbg_disc, vha, 0x20db, 1173 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 1174 sp->name, res, fcport->port_name, mb[1], mb[2]); 1175 1176 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1177 1178 if (res == QLA_FUNCTION_TIMEOUT) 1179 goto done; 1180 1181 memset(&ea, 0, sizeof(ea)); 1182 ea.fcport = fcport; 1183 ea.sp = sp; 1184 1185 qla24xx_handle_gpdb_event(vha, &ea); 1186 1187 done: 1188 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 1189 sp->u.iocb_cmd.u.mbx.in_dma); 1190 1191 sp->free(sp); 1192 } 1193 1194 static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1195 { 1196 struct qla_work_evt *e; 1197 1198 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI); 1199 if (!e) 1200 return QLA_FUNCTION_FAILED; 1201 1202 e->u.fcport.fcport = fcport; 1203 1204 return qla2x00_post_work(vha, e); 1205 } 1206 1207 static void qla2x00_async_prli_sp_done(srb_t *sp, int res) 1208 { 1209 struct scsi_qla_host *vha = sp->vha; 1210 struct srb_iocb *lio = &sp->u.iocb_cmd; 1211 struct event_arg ea; 1212 1213 ql_dbg(ql_dbg_disc, vha, 0x2129, 1214 "%s %8phC res %d \n", __func__, 1215 sp->fcport->port_name, res); 1216 1217 sp->fcport->flags &= ~FCF_ASYNC_SENT; 1218 1219 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 1220 memset(&ea, 0, sizeof(ea)); 1221 ea.fcport = sp->fcport; 1222 ea.data[0] = lio->u.logio.data[0]; 1223 ea.data[1] = lio->u.logio.data[1]; 1224 ea.iop[0] = lio->u.logio.iop[0]; 1225 ea.iop[1] = lio->u.logio.iop[1]; 1226 ea.sp = sp; 1227 1228 qla24xx_handle_prli_done_event(vha, &ea); 1229 } 1230 1231 sp->free(sp); 1232 } 1233 1234 int 1235 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport) 1236 { 1237 srb_t *sp; 1238 struct srb_iocb *lio; 1239 int rval = QLA_FUNCTION_FAILED; 1240 1241 if (!vha->flags.online) { 1242 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1243 __func__, __LINE__, fcport->port_name); 1244 return rval; 1245 } 1246 1247 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND || 1248 fcport->fw_login_state == DSC_LS_PRLI_PEND) && 1249 qla_dual_mode_enabled(vha)) { 1250 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1251 __func__, __LINE__, fcport->port_name); 1252 return rval; 1253 } 1254 1255 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1256 if (!sp) 1257 return rval; 1258 1259 fcport->flags |= FCF_ASYNC_SENT; 1260 fcport->logout_completed = 0; 1261 1262 sp->type = SRB_PRLI_CMD; 1263 sp->name = "prli"; 1264 1265 lio = &sp->u.iocb_cmd; 1266 lio->timeout = qla2x00_async_iocb_timeout; 1267 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1268 1269 sp->done = qla2x00_async_prli_sp_done; 1270 lio->u.logio.flags = 0; 1271 1272 if (NVME_TARGET(vha->hw, fcport)) 1273 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI; 1274 1275 ql_dbg(ql_dbg_disc, vha, 0x211b, 1276 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n", 1277 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24, 1278 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority, 1279 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp"); 1280 1281 rval = qla2x00_start_sp(sp); 1282 if (rval != QLA_SUCCESS) { 1283 fcport->flags |= FCF_LOGIN_NEEDED; 1284 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1285 goto done_free_sp; 1286 } 1287 1288 return rval; 1289 1290 done_free_sp: 1291 sp->free(sp); 1292 fcport->flags &= ~FCF_ASYNC_SENT; 1293 return rval; 1294 } 1295 1296 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1297 { 1298 struct qla_work_evt *e; 1299 1300 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 1301 if (!e) 1302 return QLA_FUNCTION_FAILED; 1303 1304 e->u.fcport.fcport = fcport; 1305 e->u.fcport.opt = opt; 1306 fcport->flags |= FCF_ASYNC_ACTIVE; 1307 return qla2x00_post_work(vha, e); 1308 } 1309 1310 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1311 { 1312 srb_t *sp; 1313 struct srb_iocb *mbx; 1314 int rval = QLA_FUNCTION_FAILED; 1315 u16 *mb; 1316 dma_addr_t pd_dma; 1317 struct port_database_24xx *pd; 1318 struct qla_hw_data *ha = vha->hw; 1319 1320 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 1321 fcport->loop_id == FC_NO_LOOP_ID) { 1322 ql_log(ql_log_warn, vha, 0xffff, 1323 "%s: %8phC - not sending command.\n", 1324 __func__, fcport->port_name); 1325 return rval; 1326 } 1327 1328 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1329 if (!sp) 1330 goto done; 1331 1332 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB); 1333 1334 fcport->flags |= FCF_ASYNC_SENT; 1335 sp->type = SRB_MB_IOCB; 1336 sp->name = "gpdb"; 1337 sp->gen1 = fcport->rscn_gen; 1338 sp->gen2 = fcport->login_gen; 1339 1340 mbx = &sp->u.iocb_cmd; 1341 mbx->timeout = qla2x00_async_iocb_timeout; 1342 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1343 1344 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1345 if (pd == NULL) { 1346 ql_log(ql_log_warn, vha, 0xd043, 1347 "Failed to allocate port database structure.\n"); 1348 goto done_free_sp; 1349 } 1350 1351 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1352 mb[0] = MBC_GET_PORT_DATABASE; 1353 mb[1] = fcport->loop_id; 1354 mb[2] = MSW(pd_dma); 1355 mb[3] = LSW(pd_dma); 1356 mb[6] = MSW(MSD(pd_dma)); 1357 mb[7] = LSW(MSD(pd_dma)); 1358 mb[9] = vha->vp_idx; 1359 mb[10] = opt; 1360 1361 mbx->u.mbx.in = pd; 1362 mbx->u.mbx.in_dma = pd_dma; 1363 1364 sp->done = qla24xx_async_gpdb_sp_done; 1365 1366 ql_dbg(ql_dbg_disc, vha, 0x20dc, 1367 "Async-%s %8phC hndl %x opt %x\n", 1368 sp->name, fcport->port_name, sp->handle, opt); 1369 1370 rval = qla2x00_start_sp(sp); 1371 if (rval != QLA_SUCCESS) 1372 goto done_free_sp; 1373 return rval; 1374 1375 done_free_sp: 1376 if (pd) 1377 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1378 1379 sp->free(sp); 1380 fcport->flags &= ~FCF_ASYNC_SENT; 1381 done: 1382 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1383 qla24xx_post_gpdb_work(vha, fcport, opt); 1384 return rval; 1385 } 1386 1387 static 1388 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1389 { 1390 unsigned long flags; 1391 1392 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1393 ea->fcport->login_gen++; 1394 ea->fcport->deleted = 0; 1395 ea->fcport->logout_on_delete = 1; 1396 1397 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 1398 vha->fcport_count++; 1399 ea->fcport->login_succ = 1; 1400 1401 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1402 qla24xx_sched_upd_fcport(ea->fcport); 1403 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1404 } else if (ea->fcport->login_succ) { 1405 /* 1406 * We have an existing session. A late RSCN delivery 1407 * must have triggered the session to be re-validate. 1408 * Session is still valid. 1409 */ 1410 ql_dbg(ql_dbg_disc, vha, 0x20d6, 1411 "%s %d %8phC session revalidate success\n", 1412 __func__, __LINE__, ea->fcport->port_name); 1413 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE); 1414 } 1415 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1416 } 1417 1418 static 1419 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1420 { 1421 fc_port_t *fcport = ea->fcport; 1422 struct port_database_24xx *pd; 1423 struct srb *sp = ea->sp; 1424 uint8_t ls; 1425 1426 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 1427 1428 fcport->flags &= ~FCF_ASYNC_SENT; 1429 1430 ql_dbg(ql_dbg_disc, vha, 0x20d2, 1431 "%s %8phC DS %d LS %d fc4_type %x rc %d\n", __func__, 1432 fcport->port_name, fcport->disc_state, pd->current_login_state, 1433 fcport->fc4_type, ea->rc); 1434 1435 if (fcport->disc_state == DSC_DELETE_PEND) 1436 return; 1437 1438 if (NVME_TARGET(vha->hw, fcport)) 1439 ls = pd->current_login_state >> 4; 1440 else 1441 ls = pd->current_login_state & 0xf; 1442 1443 if (ea->sp->gen2 != fcport->login_gen) { 1444 /* target side must have changed it. */ 1445 1446 ql_dbg(ql_dbg_disc, vha, 0x20d3, 1447 "%s %8phC generation changed\n", 1448 __func__, fcport->port_name); 1449 return; 1450 } else if (ea->sp->gen1 != fcport->rscn_gen) { 1451 qla_rscn_replay(fcport); 1452 qlt_schedule_sess_for_deletion(fcport); 1453 return; 1454 } 1455 1456 switch (ls) { 1457 case PDS_PRLI_COMPLETE: 1458 __qla24xx_parse_gpdb(vha, fcport, pd); 1459 break; 1460 case PDS_PLOGI_PENDING: 1461 case PDS_PLOGI_COMPLETE: 1462 case PDS_PRLI_PENDING: 1463 case PDS_PRLI2_PENDING: 1464 /* Set discovery state back to GNL to Relogin attempt */ 1465 if (qla_dual_mode_enabled(vha) || 1466 qla_ini_mode_enabled(vha)) { 1467 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1468 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1469 } 1470 return; 1471 case PDS_LOGO_PENDING: 1472 case PDS_PORT_UNAVAILABLE: 1473 default: 1474 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n", 1475 __func__, __LINE__, fcport->port_name); 1476 qlt_schedule_sess_for_deletion(fcport); 1477 return; 1478 } 1479 __qla24xx_handle_gpdb_event(vha, ea); 1480 } /* gpdb event */ 1481 1482 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1483 { 1484 u8 login = 0; 1485 int rc; 1486 1487 if (qla_tgt_mode_enabled(vha)) 1488 return; 1489 1490 if (qla_dual_mode_enabled(vha)) { 1491 if (N2N_TOPO(vha->hw)) { 1492 u64 mywwn, wwn; 1493 1494 mywwn = wwn_to_u64(vha->port_name); 1495 wwn = wwn_to_u64(fcport->port_name); 1496 if (mywwn > wwn) 1497 login = 1; 1498 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1499 && time_after_eq(jiffies, 1500 fcport->plogi_nack_done_deadline)) 1501 login = 1; 1502 } else { 1503 login = 1; 1504 } 1505 } else { 1506 /* initiator mode */ 1507 login = 1; 1508 } 1509 1510 if (login && fcport->login_retry) { 1511 fcport->login_retry--; 1512 if (fcport->loop_id == FC_NO_LOOP_ID) { 1513 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 1514 rc = qla2x00_find_new_loop_id(vha, fcport); 1515 if (rc) { 1516 ql_dbg(ql_dbg_disc, vha, 0x20e6, 1517 "%s %d %8phC post del sess - out of loopid\n", 1518 __func__, __LINE__, fcport->port_name); 1519 fcport->scan_state = 0; 1520 qlt_schedule_sess_for_deletion(fcport); 1521 return; 1522 } 1523 } 1524 ql_dbg(ql_dbg_disc, vha, 0x20bf, 1525 "%s %d %8phC post login\n", 1526 __func__, __LINE__, fcport->port_name); 1527 qla2x00_post_async_login_work(vha, fcport, NULL); 1528 } 1529 } 1530 1531 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1532 { 1533 u16 data[2]; 1534 u64 wwn; 1535 u16 sec; 1536 1537 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1538 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n", 1539 __func__, fcport->port_name, fcport->disc_state, 1540 fcport->fw_login_state, fcport->login_pause, fcport->flags, 1541 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 1542 fcport->login_gen, fcport->loop_id, fcport->scan_state); 1543 1544 if (fcport->scan_state != QLA_FCPORT_FOUND) 1545 return 0; 1546 1547 if ((fcport->loop_id != FC_NO_LOOP_ID) && 1548 qla_dual_mode_enabled(vha) && 1549 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1550 (fcport->fw_login_state == DSC_LS_PRLI_PEND))) 1551 return 0; 1552 1553 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP && 1554 !N2N_TOPO(vha->hw)) { 1555 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) { 1556 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1557 return 0; 1558 } 1559 } 1560 1561 /* Target won't initiate port login if fabric is present */ 1562 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw)) 1563 return 0; 1564 1565 if (fcport->flags & FCF_ASYNC_SENT) { 1566 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1567 return 0; 1568 } 1569 1570 switch (fcport->disc_state) { 1571 case DSC_DELETED: 1572 wwn = wwn_to_u64(fcport->node_name); 1573 switch (vha->hw->current_topology) { 1574 case ISP_CFG_N: 1575 if (fcport_is_smaller(fcport)) { 1576 /* this adapter is bigger */ 1577 if (fcport->login_retry) { 1578 if (fcport->loop_id == FC_NO_LOOP_ID) { 1579 qla2x00_find_new_loop_id(vha, 1580 fcport); 1581 fcport->fw_login_state = 1582 DSC_LS_PORT_UNAVAIL; 1583 } 1584 fcport->login_retry--; 1585 qla_post_els_plogi_work(vha, fcport); 1586 } else { 1587 ql_log(ql_log_info, vha, 0x705d, 1588 "Unable to reach remote port %8phC", 1589 fcport->port_name); 1590 } 1591 } else { 1592 qla24xx_post_gnl_work(vha, fcport); 1593 } 1594 break; 1595 default: 1596 if (wwn == 0) { 1597 ql_dbg(ql_dbg_disc, vha, 0xffff, 1598 "%s %d %8phC post GNNID\n", 1599 __func__, __LINE__, fcport->port_name); 1600 qla24xx_post_gnnid_work(vha, fcport); 1601 } else if (fcport->loop_id == FC_NO_LOOP_ID) { 1602 ql_dbg(ql_dbg_disc, vha, 0x20bd, 1603 "%s %d %8phC post gnl\n", 1604 __func__, __LINE__, fcport->port_name); 1605 qla24xx_post_gnl_work(vha, fcport); 1606 } else { 1607 qla_chk_n2n_b4_login(vha, fcport); 1608 } 1609 break; 1610 } 1611 break; 1612 1613 case DSC_GNL: 1614 switch (vha->hw->current_topology) { 1615 case ISP_CFG_N: 1616 if ((fcport->current_login_state & 0xf) == 0x6) { 1617 ql_dbg(ql_dbg_disc, vha, 0x2118, 1618 "%s %d %8phC post GPDB work\n", 1619 __func__, __LINE__, fcport->port_name); 1620 fcport->chip_reset = 1621 vha->hw->base_qpair->chip_reset; 1622 qla24xx_post_gpdb_work(vha, fcport, 0); 1623 } else { 1624 ql_dbg(ql_dbg_disc, vha, 0x2118, 1625 "%s %d %8phC post %s PRLI\n", 1626 __func__, __LINE__, fcport->port_name, 1627 NVME_TARGET(vha->hw, fcport) ? "NVME" : 1628 "FC"); 1629 qla24xx_post_prli_work(vha, fcport); 1630 } 1631 break; 1632 default: 1633 if (fcport->login_pause) { 1634 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1635 "%s %d %8phC exit\n", 1636 __func__, __LINE__, 1637 fcport->port_name); 1638 fcport->last_rscn_gen = fcport->rscn_gen; 1639 fcport->last_login_gen = fcport->login_gen; 1640 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1641 break; 1642 } 1643 qla_chk_n2n_b4_login(vha, fcport); 1644 break; 1645 } 1646 break; 1647 1648 case DSC_LOGIN_FAILED: 1649 if (N2N_TOPO(vha->hw)) 1650 qla_chk_n2n_b4_login(vha, fcport); 1651 else 1652 qlt_schedule_sess_for_deletion(fcport); 1653 break; 1654 1655 case DSC_LOGIN_COMPLETE: 1656 /* recheck login state */ 1657 data[0] = data[1] = 0; 1658 qla2x00_post_async_adisc_work(vha, fcport, data); 1659 break; 1660 1661 case DSC_LOGIN_PEND: 1662 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1663 qla24xx_post_prli_work(vha, fcport); 1664 break; 1665 1666 case DSC_UPD_FCPORT: 1667 sec = jiffies_to_msecs(jiffies - 1668 fcport->jiffies_at_registration)/1000; 1669 if (fcport->sec_since_registration < sec && sec && 1670 !(sec % 60)) { 1671 fcport->sec_since_registration = sec; 1672 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 1673 "%s %8phC - Slow Rport registration(%d Sec)\n", 1674 __func__, fcport->port_name, sec); 1675 } 1676 1677 if (fcport->next_disc_state != DSC_DELETE_PEND) 1678 fcport->next_disc_state = DSC_ADISC; 1679 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1680 break; 1681 1682 default: 1683 break; 1684 } 1685 1686 return 0; 1687 } 1688 1689 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 1690 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type) 1691 { 1692 struct qla_work_evt *e; 1693 1694 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 1695 if (!e) 1696 return QLA_FUNCTION_FAILED; 1697 1698 e->u.new_sess.id = *id; 1699 e->u.new_sess.pla = pla; 1700 e->u.new_sess.fc4_type = fc4_type; 1701 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 1702 if (node_name) 1703 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE); 1704 1705 return qla2x00_post_work(vha, e); 1706 } 1707 1708 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea) 1709 { 1710 fc_port_t *fcport; 1711 unsigned long flags; 1712 1713 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1714 if (fcport) { 1715 fcport->scan_needed = 1; 1716 fcport->rscn_gen++; 1717 } 1718 1719 spin_lock_irqsave(&vha->work_lock, flags); 1720 if (vha->scan.scan_flags == 0) { 1721 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__); 1722 vha->scan.scan_flags |= SF_QUEUED; 1723 schedule_delayed_work(&vha->scan.scan_work, 5); 1724 } 1725 spin_unlock_irqrestore(&vha->work_lock, flags); 1726 } 1727 1728 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 1729 struct event_arg *ea) 1730 { 1731 fc_port_t *fcport = ea->fcport; 1732 1733 if (test_bit(UNLOADING, &vha->dpc_flags)) 1734 return; 1735 1736 ql_dbg(ql_dbg_disc, vha, 0x2102, 1737 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 1738 __func__, fcport->port_name, fcport->disc_state, 1739 fcport->fw_login_state, fcport->login_pause, 1740 fcport->deleted, fcport->conflict, 1741 fcport->last_rscn_gen, fcport->rscn_gen, 1742 fcport->last_login_gen, fcport->login_gen, 1743 fcport->flags); 1744 1745 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1746 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n", 1747 __func__, __LINE__, fcport->port_name); 1748 qla24xx_post_gnl_work(vha, fcport); 1749 return; 1750 } 1751 1752 qla24xx_fcport_handle_login(vha, fcport); 1753 } 1754 1755 void qla_handle_els_plogi_done(scsi_qla_host_t *vha, 1756 struct event_arg *ea) 1757 { 1758 /* for pure Target Mode, PRLI will not be initiated */ 1759 if (vha->host->active_mode == MODE_TARGET) 1760 return; 1761 1762 ql_dbg(ql_dbg_disc, vha, 0x2118, 1763 "%s %d %8phC post PRLI\n", 1764 __func__, __LINE__, ea->fcport->port_name); 1765 qla24xx_post_prli_work(vha, ea->fcport); 1766 } 1767 1768 /* 1769 * RSCN(s) came in for this fcport, but the RSCN(s) was not able 1770 * to be consumed by the fcport 1771 */ 1772 void qla_rscn_replay(fc_port_t *fcport) 1773 { 1774 struct event_arg ea; 1775 1776 switch (fcport->disc_state) { 1777 case DSC_DELETE_PEND: 1778 return; 1779 default: 1780 break; 1781 } 1782 1783 if (fcport->scan_needed) { 1784 memset(&ea, 0, sizeof(ea)); 1785 ea.id = fcport->d_id; 1786 ea.id.b.rsvd_1 = RSCN_PORT_ADDR; 1787 qla2x00_handle_rscn(fcport->vha, &ea); 1788 } 1789 } 1790 1791 static void 1792 qla2x00_tmf_iocb_timeout(void *data) 1793 { 1794 srb_t *sp = data; 1795 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1796 int rc, h; 1797 unsigned long flags; 1798 1799 rc = qla24xx_async_abort_cmd(sp, false); 1800 if (rc) { 1801 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 1802 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) { 1803 if (sp->qpair->req->outstanding_cmds[h] == sp) { 1804 sp->qpair->req->outstanding_cmds[h] = NULL; 1805 break; 1806 } 1807 } 1808 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 1809 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT); 1810 tmf->u.tmf.data = QLA_FUNCTION_FAILED; 1811 complete(&tmf->u.tmf.comp); 1812 } 1813 } 1814 1815 static void qla2x00_tmf_sp_done(srb_t *sp, int res) 1816 { 1817 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1818 1819 complete(&tmf->u.tmf.comp); 1820 } 1821 1822 int 1823 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, 1824 uint32_t tag) 1825 { 1826 struct scsi_qla_host *vha = fcport->vha; 1827 struct srb_iocb *tm_iocb; 1828 srb_t *sp; 1829 int rval = QLA_FUNCTION_FAILED; 1830 1831 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1832 if (!sp) 1833 goto done; 1834 1835 tm_iocb = &sp->u.iocb_cmd; 1836 sp->type = SRB_TM_CMD; 1837 sp->name = "tmf"; 1838 1839 tm_iocb->timeout = qla2x00_tmf_iocb_timeout; 1840 init_completion(&tm_iocb->u.tmf.comp); 1841 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 1842 1843 tm_iocb->u.tmf.flags = flags; 1844 tm_iocb->u.tmf.lun = lun; 1845 tm_iocb->u.tmf.data = tag; 1846 sp->done = qla2x00_tmf_sp_done; 1847 1848 ql_dbg(ql_dbg_taskm, vha, 0x802f, 1849 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 1850 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 1851 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1852 1853 rval = qla2x00_start_sp(sp); 1854 if (rval != QLA_SUCCESS) 1855 goto done_free_sp; 1856 wait_for_completion(&tm_iocb->u.tmf.comp); 1857 1858 rval = tm_iocb->u.tmf.data; 1859 1860 if (rval != QLA_SUCCESS) { 1861 ql_log(ql_log_warn, vha, 0x8030, 1862 "TM IOCB failed (%x).\n", rval); 1863 } 1864 1865 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 1866 flags = tm_iocb->u.tmf.flags; 1867 lun = (uint16_t)tm_iocb->u.tmf.lun; 1868 1869 /* Issue Marker IOCB */ 1870 qla2x00_marker(vha, vha->hw->base_qpair, 1871 fcport->loop_id, lun, 1872 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 1873 } 1874 1875 done_free_sp: 1876 sp->free(sp); 1877 fcport->flags &= ~FCF_ASYNC_SENT; 1878 done: 1879 return rval; 1880 } 1881 1882 int 1883 qla24xx_async_abort_command(srb_t *sp) 1884 { 1885 unsigned long flags = 0; 1886 1887 uint32_t handle; 1888 fc_port_t *fcport = sp->fcport; 1889 struct qla_qpair *qpair = sp->qpair; 1890 struct scsi_qla_host *vha = fcport->vha; 1891 struct req_que *req = qpair->req; 1892 1893 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1894 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1895 if (req->outstanding_cmds[handle] == sp) 1896 break; 1897 } 1898 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1899 1900 if (handle == req->num_outstanding_cmds) { 1901 /* Command not found. */ 1902 return QLA_FUNCTION_FAILED; 1903 } 1904 if (sp->type == SRB_FXIOCB_DCMD) 1905 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 1906 FXDISC_ABORT_IOCTL); 1907 1908 return qla24xx_async_abort_cmd(sp, true); 1909 } 1910 1911 static void 1912 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1913 { 1914 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 1915 ea->data[0]); 1916 1917 switch (ea->data[0]) { 1918 case MBS_COMMAND_COMPLETE: 1919 ql_dbg(ql_dbg_disc, vha, 0x2118, 1920 "%s %d %8phC post gpdb\n", 1921 __func__, __LINE__, ea->fcport->port_name); 1922 1923 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 1924 ea->fcport->logout_on_delete = 1; 1925 ea->fcport->nvme_prli_service_param = ea->iop[0]; 1926 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST) 1927 ea->fcport->nvme_first_burst_size = 1928 (ea->iop[1] & 0xffff) * 512; 1929 else 1930 ea->fcport->nvme_first_burst_size = 0; 1931 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1932 break; 1933 default: 1934 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) && 1935 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */ 1936 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1937 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP; 1938 break; 1939 } 1940 1941 ql_dbg(ql_dbg_disc, vha, 0x2118, 1942 "%s %d %8phC priority %s, fc4type %x\n", 1943 __func__, __LINE__, ea->fcport->port_name, 1944 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ? 1945 "FCP" : "NVMe", ea->fcport->fc4_type); 1946 1947 if (N2N_TOPO(vha->hw)) { 1948 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) { 1949 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1950 ea->fcport->fc4_type |= FS_FC4TYPE_FCP; 1951 } else { 1952 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1953 ea->fcport->fc4_type |= FS_FC4TYPE_NVME; 1954 } 1955 1956 if (ea->fcport->n2n_link_reset_cnt < 3) { 1957 ea->fcport->n2n_link_reset_cnt++; 1958 vha->relogin_jif = jiffies + 2 * HZ; 1959 /* 1960 * PRLI failed. Reset link to kick start 1961 * state machine 1962 */ 1963 set_bit(N2N_LINK_RESET, &vha->dpc_flags); 1964 } else { 1965 ql_log(ql_log_warn, vha, 0x2119, 1966 "%s %d %8phC Unable to reconnect\n", 1967 __func__, __LINE__, 1968 ea->fcport->port_name); 1969 } 1970 } else { 1971 /* 1972 * switch connect. login failed. Take connection down 1973 * and allow relogin to retrigger 1974 */ 1975 if (NVME_FCP_TARGET(ea->fcport)) { 1976 ql_dbg(ql_dbg_disc, vha, 0x2118, 1977 "%s %d %8phC post %s prli\n", 1978 __func__, __LINE__, 1979 ea->fcport->port_name, 1980 (ea->fcport->fc4_type & FS_FC4TYPE_NVME) 1981 ? "NVMe" : "FCP"); 1982 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) 1983 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1984 else 1985 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1986 } 1987 1988 ea->fcport->flags &= ~FCF_ASYNC_SENT; 1989 ea->fcport->keep_nport_handle = 0; 1990 ea->fcport->logout_on_delete = 1; 1991 qlt_schedule_sess_for_deletion(ea->fcport); 1992 } 1993 break; 1994 } 1995 } 1996 1997 void 1998 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1999 { 2000 port_id_t cid; /* conflict Nport id */ 2001 u16 lid; 2002 struct fc_port *conflict_fcport; 2003 unsigned long flags; 2004 struct fc_port *fcport = ea->fcport; 2005 2006 ql_dbg(ql_dbg_disc, vha, 0xffff, 2007 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n", 2008 __func__, fcport->port_name, fcport->disc_state, 2009 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen, 2010 ea->sp->gen1, fcport->rscn_gen, 2011 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]); 2012 2013 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 2014 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) { 2015 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2016 "%s %d %8phC Remote is trying to login\n", 2017 __func__, __LINE__, fcport->port_name); 2018 return; 2019 } 2020 2021 if ((fcport->disc_state == DSC_DELETE_PEND) || 2022 (fcport->disc_state == DSC_DELETED)) { 2023 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2024 return; 2025 } 2026 2027 if (ea->sp->gen2 != fcport->login_gen) { 2028 /* target side must have changed it. */ 2029 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2030 "%s %8phC generation changed\n", 2031 __func__, fcport->port_name); 2032 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2033 return; 2034 } else if (ea->sp->gen1 != fcport->rscn_gen) { 2035 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2036 "%s %8phC RSCN generation changed\n", 2037 __func__, fcport->port_name); 2038 qla_rscn_replay(fcport); 2039 qlt_schedule_sess_for_deletion(fcport); 2040 return; 2041 } 2042 2043 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2044 ea->data[0]); 2045 2046 switch (ea->data[0]) { 2047 case MBS_COMMAND_COMPLETE: 2048 /* 2049 * Driver must validate login state - If PRLI not complete, 2050 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 2051 * requests. 2052 */ 2053 if (NVME_TARGET(vha->hw, ea->fcport)) { 2054 ql_dbg(ql_dbg_disc, vha, 0x2117, 2055 "%s %d %8phC post prli\n", 2056 __func__, __LINE__, ea->fcport->port_name); 2057 qla24xx_post_prli_work(vha, ea->fcport); 2058 } else { 2059 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2060 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n", 2061 __func__, __LINE__, ea->fcport->port_name, 2062 ea->fcport->loop_id, ea->fcport->d_id.b24); 2063 2064 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2065 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2066 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2067 ea->fcport->logout_on_delete = 1; 2068 ea->fcport->send_els_logo = 0; 2069 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP; 2070 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2071 2072 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2073 } 2074 break; 2075 case MBS_COMMAND_ERROR: 2076 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n", 2077 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 2078 2079 ea->fcport->flags &= ~FCF_ASYNC_SENT; 2080 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_FAILED); 2081 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED) 2082 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2083 else 2084 qla2x00_mark_device_lost(vha, ea->fcport, 1); 2085 break; 2086 case MBS_LOOP_ID_USED: 2087 /* data[1] = IO PARAM 1 = nport ID */ 2088 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 2089 cid.b.area = (ea->iop[1] >> 8) & 0xff; 2090 cid.b.al_pa = ea->iop[1] & 0xff; 2091 cid.b.rsvd_1 = 0; 2092 2093 ql_dbg(ql_dbg_disc, vha, 0x20ec, 2094 "%s %d %8phC lid %#x in use with pid %06x post gnl\n", 2095 __func__, __LINE__, ea->fcport->port_name, 2096 ea->fcport->loop_id, cid.b24); 2097 2098 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2099 ea->fcport->loop_id = FC_NO_LOOP_ID; 2100 qla24xx_post_gnl_work(vha, ea->fcport); 2101 break; 2102 case MBS_PORT_ID_USED: 2103 lid = ea->iop[1] & 0xffff; 2104 qlt_find_sess_invalidate_other(vha, 2105 wwn_to_u64(ea->fcport->port_name), 2106 ea->fcport->d_id, lid, &conflict_fcport); 2107 2108 if (conflict_fcport) { 2109 /* 2110 * Another fcport share the same loop_id/nport id. 2111 * Conflict fcport needs to finish cleanup before this 2112 * fcport can proceed to login. 2113 */ 2114 conflict_fcport->conflict = ea->fcport; 2115 ea->fcport->login_pause = 1; 2116 2117 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2118 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n", 2119 __func__, __LINE__, ea->fcport->port_name, 2120 ea->fcport->d_id.b24, lid); 2121 } else { 2122 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2123 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n", 2124 __func__, __LINE__, ea->fcport->port_name, 2125 ea->fcport->d_id.b24, lid); 2126 2127 qla2x00_clear_loop_id(ea->fcport); 2128 set_bit(lid, vha->hw->loop_id_map); 2129 ea->fcport->loop_id = lid; 2130 ea->fcport->keep_nport_handle = 0; 2131 ea->fcport->logout_on_delete = 1; 2132 qlt_schedule_sess_for_deletion(ea->fcport); 2133 } 2134 break; 2135 } 2136 return; 2137 } 2138 2139 /****************************************************************************/ 2140 /* QLogic ISP2x00 Hardware Support Functions. */ 2141 /****************************************************************************/ 2142 2143 static int 2144 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 2145 { 2146 int rval = QLA_SUCCESS; 2147 struct qla_hw_data *ha = vha->hw; 2148 uint32_t idc_major_ver, idc_minor_ver; 2149 uint16_t config[4]; 2150 2151 qla83xx_idc_lock(vha, 0); 2152 2153 /* SV: TODO: Assign initialization timeout from 2154 * flash-info / other param 2155 */ 2156 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 2157 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 2158 2159 /* Set our fcoe function presence */ 2160 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 2161 ql_dbg(ql_dbg_p3p, vha, 0xb077, 2162 "Error while setting DRV-Presence.\n"); 2163 rval = QLA_FUNCTION_FAILED; 2164 goto exit; 2165 } 2166 2167 /* Decide the reset ownership */ 2168 qla83xx_reset_ownership(vha); 2169 2170 /* 2171 * On first protocol driver load: 2172 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 2173 * register. 2174 * Others: Check compatibility with current IDC Major version. 2175 */ 2176 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 2177 if (ha->flags.nic_core_reset_owner) { 2178 /* Set IDC Major version */ 2179 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 2180 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 2181 2182 /* Clearing IDC-Lock-Recovery register */ 2183 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 2184 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 2185 /* 2186 * Clear further IDC participation if we are not compatible with 2187 * the current IDC Major Version. 2188 */ 2189 ql_log(ql_log_warn, vha, 0xb07d, 2190 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 2191 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 2192 __qla83xx_clear_drv_presence(vha); 2193 rval = QLA_FUNCTION_FAILED; 2194 goto exit; 2195 } 2196 /* Each function sets its supported Minor version. */ 2197 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 2198 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 2199 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 2200 2201 if (ha->flags.nic_core_reset_owner) { 2202 memset(config, 0, sizeof(config)); 2203 if (!qla81xx_get_port_config(vha, config)) 2204 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 2205 QLA8XXX_DEV_READY); 2206 } 2207 2208 rval = qla83xx_idc_state_handler(vha); 2209 2210 exit: 2211 qla83xx_idc_unlock(vha, 0); 2212 2213 return rval; 2214 } 2215 2216 /* 2217 * qla2x00_initialize_adapter 2218 * Initialize board. 2219 * 2220 * Input: 2221 * ha = adapter block pointer. 2222 * 2223 * Returns: 2224 * 0 = success 2225 */ 2226 int 2227 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 2228 { 2229 int rval; 2230 struct qla_hw_data *ha = vha->hw; 2231 struct req_que *req = ha->req_q_map[0]; 2232 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2233 2234 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 2235 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 2236 2237 /* Clear adapter flags. */ 2238 vha->flags.online = 0; 2239 ha->flags.chip_reset_done = 0; 2240 vha->flags.reset_active = 0; 2241 ha->flags.pci_channel_io_perm_failure = 0; 2242 ha->flags.eeh_busy = 0; 2243 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 2244 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2245 atomic_set(&vha->loop_state, LOOP_DOWN); 2246 vha->device_flags = DFLG_NO_CABLE; 2247 vha->dpc_flags = 0; 2248 vha->flags.management_server_logged_in = 0; 2249 vha->marker_needed = 0; 2250 ha->isp_abort_cnt = 0; 2251 ha->beacon_blink_led = 0; 2252 2253 set_bit(0, ha->req_qid_map); 2254 set_bit(0, ha->rsp_qid_map); 2255 2256 ql_dbg(ql_dbg_init, vha, 0x0040, 2257 "Configuring PCI space...\n"); 2258 rval = ha->isp_ops->pci_config(vha); 2259 if (rval) { 2260 ql_log(ql_log_warn, vha, 0x0044, 2261 "Unable to configure PCI space.\n"); 2262 return (rval); 2263 } 2264 2265 ha->isp_ops->reset_chip(vha); 2266 2267 /* Check for secure flash support */ 2268 if (IS_QLA28XX(ha)) { 2269 if (rd_reg_word(®->mailbox12) & BIT_0) 2270 ha->flags.secure_adapter = 1; 2271 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n", 2272 (ha->flags.secure_adapter) ? "Yes" : "No"); 2273 } 2274 2275 2276 rval = qla2xxx_get_flash_info(vha); 2277 if (rval) { 2278 ql_log(ql_log_fatal, vha, 0x004f, 2279 "Unable to validate FLASH data.\n"); 2280 return rval; 2281 } 2282 2283 if (IS_QLA8044(ha)) { 2284 qla8044_read_reset_template(vha); 2285 2286 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 2287 * If DONRESET_BIT0 is set, drivers should not set dev_state 2288 * to NEED_RESET. But if NEED_RESET is set, drivers should 2289 * should honor the reset. */ 2290 if (ql2xdontresethba == 1) 2291 qla8044_set_idc_dontreset(vha); 2292 } 2293 2294 ha->isp_ops->get_flash_version(vha, req->ring); 2295 ql_dbg(ql_dbg_init, vha, 0x0061, 2296 "Configure NVRAM parameters...\n"); 2297 2298 /* Let priority default to FCP, can be overridden by nvram_config */ 2299 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2300 2301 ha->isp_ops->nvram_config(vha); 2302 2303 if (ha->fc4_type_priority != FC4_PRIORITY_FCP && 2304 ha->fc4_type_priority != FC4_PRIORITY_NVME) 2305 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2306 2307 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n", 2308 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe"); 2309 2310 if (ha->flags.disable_serdes) { 2311 /* Mask HBA via NVRAM settings? */ 2312 ql_log(ql_log_info, vha, 0x0077, 2313 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 2314 return QLA_FUNCTION_FAILED; 2315 } 2316 2317 ql_dbg(ql_dbg_init, vha, 0x0078, 2318 "Verifying loaded RISC code...\n"); 2319 2320 /* If smartsan enabled then require fdmi and rdp enabled */ 2321 if (ql2xsmartsan) { 2322 ql2xfdmienable = 1; 2323 ql2xrdpenable = 1; 2324 } 2325 2326 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 2327 rval = ha->isp_ops->chip_diag(vha); 2328 if (rval) 2329 return (rval); 2330 rval = qla2x00_setup_chip(vha); 2331 if (rval) 2332 return (rval); 2333 } 2334 2335 if (IS_QLA84XX(ha)) { 2336 ha->cs84xx = qla84xx_get_chip(vha); 2337 if (!ha->cs84xx) { 2338 ql_log(ql_log_warn, vha, 0x00d0, 2339 "Unable to configure ISP84XX.\n"); 2340 return QLA_FUNCTION_FAILED; 2341 } 2342 } 2343 2344 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 2345 rval = qla2x00_init_rings(vha); 2346 2347 /* No point in continuing if firmware initialization failed. */ 2348 if (rval != QLA_SUCCESS) 2349 return rval; 2350 2351 ha->flags.chip_reset_done = 1; 2352 2353 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 2354 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 2355 rval = qla84xx_init_chip(vha); 2356 if (rval != QLA_SUCCESS) { 2357 ql_log(ql_log_warn, vha, 0x00d4, 2358 "Unable to initialize ISP84XX.\n"); 2359 qla84xx_put_chip(vha); 2360 } 2361 } 2362 2363 /* Load the NIC Core f/w if we are the first protocol driver. */ 2364 if (IS_QLA8031(ha)) { 2365 rval = qla83xx_nic_core_fw_load(vha); 2366 if (rval) 2367 ql_log(ql_log_warn, vha, 0x0124, 2368 "Error in initializing NIC Core f/w.\n"); 2369 } 2370 2371 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 2372 qla24xx_read_fcp_prio_cfg(vha); 2373 2374 if (IS_P3P_TYPE(ha)) 2375 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 2376 else 2377 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 2378 2379 return (rval); 2380 } 2381 2382 /** 2383 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 2384 * @vha: HA context 2385 * 2386 * Returns 0 on success. 2387 */ 2388 int 2389 qla2100_pci_config(scsi_qla_host_t *vha) 2390 { 2391 uint16_t w; 2392 unsigned long flags; 2393 struct qla_hw_data *ha = vha->hw; 2394 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2395 2396 pci_set_master(ha->pdev); 2397 pci_try_set_mwi(ha->pdev); 2398 2399 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2400 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2401 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2402 2403 pci_disable_rom(ha->pdev); 2404 2405 /* Get PCI bus information. */ 2406 spin_lock_irqsave(&ha->hardware_lock, flags); 2407 ha->pci_attr = rd_reg_word(®->ctrl_status); 2408 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2409 2410 return QLA_SUCCESS; 2411 } 2412 2413 /** 2414 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 2415 * @vha: HA context 2416 * 2417 * Returns 0 on success. 2418 */ 2419 int 2420 qla2300_pci_config(scsi_qla_host_t *vha) 2421 { 2422 uint16_t w; 2423 unsigned long flags = 0; 2424 uint32_t cnt; 2425 struct qla_hw_data *ha = vha->hw; 2426 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2427 2428 pci_set_master(ha->pdev); 2429 pci_try_set_mwi(ha->pdev); 2430 2431 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2432 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2433 2434 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2435 w &= ~PCI_COMMAND_INTX_DISABLE; 2436 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2437 2438 /* 2439 * If this is a 2300 card and not 2312, reset the 2440 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 2441 * the 2310 also reports itself as a 2300 so we need to get the 2442 * fb revision level -- a 6 indicates it really is a 2300 and 2443 * not a 2310. 2444 */ 2445 if (IS_QLA2300(ha)) { 2446 spin_lock_irqsave(&ha->hardware_lock, flags); 2447 2448 /* Pause RISC. */ 2449 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2450 for (cnt = 0; cnt < 30000; cnt++) { 2451 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2452 break; 2453 2454 udelay(10); 2455 } 2456 2457 /* Select FPM registers. */ 2458 wrt_reg_word(®->ctrl_status, 0x20); 2459 rd_reg_word(®->ctrl_status); 2460 2461 /* Get the fb rev level */ 2462 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 2463 2464 if (ha->fb_rev == FPM_2300) 2465 pci_clear_mwi(ha->pdev); 2466 2467 /* Deselect FPM registers. */ 2468 wrt_reg_word(®->ctrl_status, 0x0); 2469 rd_reg_word(®->ctrl_status); 2470 2471 /* Release RISC module. */ 2472 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2473 for (cnt = 0; cnt < 30000; cnt++) { 2474 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) 2475 break; 2476 2477 udelay(10); 2478 } 2479 2480 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2481 } 2482 2483 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2484 2485 pci_disable_rom(ha->pdev); 2486 2487 /* Get PCI bus information. */ 2488 spin_lock_irqsave(&ha->hardware_lock, flags); 2489 ha->pci_attr = rd_reg_word(®->ctrl_status); 2490 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2491 2492 return QLA_SUCCESS; 2493 } 2494 2495 /** 2496 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 2497 * @vha: HA context 2498 * 2499 * Returns 0 on success. 2500 */ 2501 int 2502 qla24xx_pci_config(scsi_qla_host_t *vha) 2503 { 2504 uint16_t w; 2505 unsigned long flags = 0; 2506 struct qla_hw_data *ha = vha->hw; 2507 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2508 2509 pci_set_master(ha->pdev); 2510 pci_try_set_mwi(ha->pdev); 2511 2512 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2513 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2514 w &= ~PCI_COMMAND_INTX_DISABLE; 2515 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2516 2517 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2518 2519 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 2520 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 2521 pcix_set_mmrbc(ha->pdev, 2048); 2522 2523 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2524 if (pci_is_pcie(ha->pdev)) 2525 pcie_set_readrq(ha->pdev, 4096); 2526 2527 pci_disable_rom(ha->pdev); 2528 2529 ha->chip_revision = ha->pdev->revision; 2530 2531 /* Get PCI bus information. */ 2532 spin_lock_irqsave(&ha->hardware_lock, flags); 2533 ha->pci_attr = rd_reg_dword(®->ctrl_status); 2534 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2535 2536 return QLA_SUCCESS; 2537 } 2538 2539 /** 2540 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 2541 * @vha: HA context 2542 * 2543 * Returns 0 on success. 2544 */ 2545 int 2546 qla25xx_pci_config(scsi_qla_host_t *vha) 2547 { 2548 uint16_t w; 2549 struct qla_hw_data *ha = vha->hw; 2550 2551 pci_set_master(ha->pdev); 2552 pci_try_set_mwi(ha->pdev); 2553 2554 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2555 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2556 w &= ~PCI_COMMAND_INTX_DISABLE; 2557 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2558 2559 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2560 if (pci_is_pcie(ha->pdev)) 2561 pcie_set_readrq(ha->pdev, 4096); 2562 2563 pci_disable_rom(ha->pdev); 2564 2565 ha->chip_revision = ha->pdev->revision; 2566 2567 return QLA_SUCCESS; 2568 } 2569 2570 /** 2571 * qla2x00_isp_firmware() - Choose firmware image. 2572 * @vha: HA context 2573 * 2574 * Returns 0 on success. 2575 */ 2576 static int 2577 qla2x00_isp_firmware(scsi_qla_host_t *vha) 2578 { 2579 int rval; 2580 uint16_t loop_id, topo, sw_cap; 2581 uint8_t domain, area, al_pa; 2582 struct qla_hw_data *ha = vha->hw; 2583 2584 /* Assume loading risc code */ 2585 rval = QLA_FUNCTION_FAILED; 2586 2587 if (ha->flags.disable_risc_code_load) { 2588 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 2589 2590 /* Verify checksum of loaded RISC code. */ 2591 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 2592 if (rval == QLA_SUCCESS) { 2593 /* And, verify we are not in ROM code. */ 2594 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 2595 &area, &domain, &topo, &sw_cap); 2596 } 2597 } 2598 2599 if (rval) 2600 ql_dbg(ql_dbg_init, vha, 0x007a, 2601 "**** Load RISC code ****.\n"); 2602 2603 return (rval); 2604 } 2605 2606 /** 2607 * qla2x00_reset_chip() - Reset ISP chip. 2608 * @vha: HA context 2609 * 2610 * Returns 0 on success. 2611 */ 2612 int 2613 qla2x00_reset_chip(scsi_qla_host_t *vha) 2614 { 2615 unsigned long flags = 0; 2616 struct qla_hw_data *ha = vha->hw; 2617 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2618 uint32_t cnt; 2619 uint16_t cmd; 2620 int rval = QLA_FUNCTION_FAILED; 2621 2622 if (unlikely(pci_channel_offline(ha->pdev))) 2623 return rval; 2624 2625 ha->isp_ops->disable_intrs(ha); 2626 2627 spin_lock_irqsave(&ha->hardware_lock, flags); 2628 2629 /* Turn off master enable */ 2630 cmd = 0; 2631 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 2632 cmd &= ~PCI_COMMAND_MASTER; 2633 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2634 2635 if (!IS_QLA2100(ha)) { 2636 /* Pause RISC. */ 2637 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2638 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 2639 for (cnt = 0; cnt < 30000; cnt++) { 2640 if ((rd_reg_word(®->hccr) & 2641 HCCR_RISC_PAUSE) != 0) 2642 break; 2643 udelay(100); 2644 } 2645 } else { 2646 rd_reg_word(®->hccr); /* PCI Posting. */ 2647 udelay(10); 2648 } 2649 2650 /* Select FPM registers. */ 2651 wrt_reg_word(®->ctrl_status, 0x20); 2652 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2653 2654 /* FPM Soft Reset. */ 2655 wrt_reg_word(®->fpm_diag_config, 0x100); 2656 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2657 2658 /* Toggle Fpm Reset. */ 2659 if (!IS_QLA2200(ha)) { 2660 wrt_reg_word(®->fpm_diag_config, 0x0); 2661 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2662 } 2663 2664 /* Select frame buffer registers. */ 2665 wrt_reg_word(®->ctrl_status, 0x10); 2666 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2667 2668 /* Reset frame buffer FIFOs. */ 2669 if (IS_QLA2200(ha)) { 2670 WRT_FB_CMD_REG(ha, reg, 0xa000); 2671 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 2672 } else { 2673 WRT_FB_CMD_REG(ha, reg, 0x00fc); 2674 2675 /* Read back fb_cmd until zero or 3 seconds max */ 2676 for (cnt = 0; cnt < 3000; cnt++) { 2677 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 2678 break; 2679 udelay(100); 2680 } 2681 } 2682 2683 /* Select RISC module registers. */ 2684 wrt_reg_word(®->ctrl_status, 0); 2685 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2686 2687 /* Reset RISC processor. */ 2688 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2689 rd_reg_word(®->hccr); /* PCI Posting. */ 2690 2691 /* Release RISC processor. */ 2692 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2693 rd_reg_word(®->hccr); /* PCI Posting. */ 2694 } 2695 2696 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 2697 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT); 2698 2699 /* Reset ISP chip. */ 2700 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2701 2702 /* Wait for RISC to recover from reset. */ 2703 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2704 /* 2705 * It is necessary to for a delay here since the card doesn't 2706 * respond to PCI reads during a reset. On some architectures 2707 * this will result in an MCA. 2708 */ 2709 udelay(20); 2710 for (cnt = 30000; cnt; cnt--) { 2711 if ((rd_reg_word(®->ctrl_status) & 2712 CSR_ISP_SOFT_RESET) == 0) 2713 break; 2714 udelay(100); 2715 } 2716 } else 2717 udelay(10); 2718 2719 /* Reset RISC processor. */ 2720 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2721 2722 wrt_reg_word(®->semaphore, 0); 2723 2724 /* Release RISC processor. */ 2725 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2726 rd_reg_word(®->hccr); /* PCI Posting. */ 2727 2728 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2729 for (cnt = 0; cnt < 30000; cnt++) { 2730 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 2731 break; 2732 2733 udelay(100); 2734 } 2735 } else 2736 udelay(100); 2737 2738 /* Turn on master enable */ 2739 cmd |= PCI_COMMAND_MASTER; 2740 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2741 2742 /* Disable RISC pause on FPM parity error. */ 2743 if (!IS_QLA2100(ha)) { 2744 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 2745 rd_reg_word(®->hccr); /* PCI Posting. */ 2746 } 2747 2748 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2749 2750 return QLA_SUCCESS; 2751 } 2752 2753 /** 2754 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 2755 * @vha: HA context 2756 * 2757 * Returns 0 on success. 2758 */ 2759 static int 2760 qla81xx_reset_mpi(scsi_qla_host_t *vha) 2761 { 2762 uint16_t mb[4] = {0x1010, 0, 1, 0}; 2763 2764 if (!IS_QLA81XX(vha->hw)) 2765 return QLA_SUCCESS; 2766 2767 return qla81xx_write_mpi_register(vha, mb); 2768 } 2769 2770 static int 2771 qla_chk_risc_recovery(scsi_qla_host_t *vha) 2772 { 2773 struct qla_hw_data *ha = vha->hw; 2774 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2775 __le16 __iomem *mbptr = ®->mailbox0; 2776 int i; 2777 u16 mb[32]; 2778 int rc = QLA_SUCCESS; 2779 2780 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 2781 return rc; 2782 2783 /* this check is only valid after RISC reset */ 2784 mb[0] = rd_reg_word(mbptr); 2785 mbptr++; 2786 if (mb[0] == 0xf) { 2787 rc = QLA_FUNCTION_FAILED; 2788 2789 for (i = 1; i < 32; i++) { 2790 mb[i] = rd_reg_word(mbptr); 2791 mbptr++; 2792 } 2793 2794 ql_log(ql_log_warn, vha, 0x1015, 2795 "RISC reset failed. mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2796 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]); 2797 ql_log(ql_log_warn, vha, 0x1015, 2798 "RISC reset failed. mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2799 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14], 2800 mb[15]); 2801 ql_log(ql_log_warn, vha, 0x1015, 2802 "RISC reset failed. mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2803 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22], 2804 mb[23]); 2805 ql_log(ql_log_warn, vha, 0x1015, 2806 "RISC reset failed. mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2807 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30], 2808 mb[31]); 2809 } 2810 return rc; 2811 } 2812 2813 /** 2814 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 2815 * @vha: HA context 2816 * 2817 * Returns 0 on success. 2818 */ 2819 static inline int 2820 qla24xx_reset_risc(scsi_qla_host_t *vha) 2821 { 2822 unsigned long flags = 0; 2823 struct qla_hw_data *ha = vha->hw; 2824 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2825 uint32_t cnt; 2826 uint16_t wd; 2827 static int abts_cnt; /* ISP abort retry counts */ 2828 int rval = QLA_SUCCESS; 2829 int print = 1; 2830 2831 spin_lock_irqsave(&ha->hardware_lock, flags); 2832 2833 /* Reset RISC. */ 2834 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2835 for (cnt = 0; cnt < 30000; cnt++) { 2836 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 2837 break; 2838 2839 udelay(10); 2840 } 2841 2842 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 2843 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 2844 2845 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 2846 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 2847 rd_reg_dword(®->hccr), 2848 rd_reg_dword(®->ctrl_status), 2849 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); 2850 2851 wrt_reg_dword(®->ctrl_status, 2852 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2853 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2854 2855 udelay(100); 2856 2857 /* Wait for firmware to complete NVRAM accesses. */ 2858 rd_reg_word(®->mailbox0); 2859 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 2860 rval == QLA_SUCCESS; cnt--) { 2861 barrier(); 2862 if (cnt) 2863 udelay(5); 2864 else 2865 rval = QLA_FUNCTION_TIMEOUT; 2866 } 2867 2868 if (rval == QLA_SUCCESS) 2869 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 2870 2871 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 2872 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 2873 rd_reg_dword(®->hccr), 2874 rd_reg_word(®->mailbox0)); 2875 2876 /* Wait for soft-reset to complete. */ 2877 rd_reg_dword(®->ctrl_status); 2878 for (cnt = 0; cnt < 60; cnt++) { 2879 barrier(); 2880 if ((rd_reg_dword(®->ctrl_status) & 2881 CSRX_ISP_SOFT_RESET) == 0) 2882 break; 2883 2884 udelay(5); 2885 } 2886 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 2887 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 2888 2889 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 2890 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 2891 rd_reg_dword(®->hccr), 2892 rd_reg_dword(®->ctrl_status)); 2893 2894 /* If required, do an MPI FW reset now */ 2895 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 2896 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 2897 if (++abts_cnt < 5) { 2898 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2899 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 2900 } else { 2901 /* 2902 * We exhausted the ISP abort retries. We have to 2903 * set the board offline. 2904 */ 2905 abts_cnt = 0; 2906 vha->flags.online = 0; 2907 } 2908 } 2909 } 2910 2911 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 2912 rd_reg_dword(®->hccr); 2913 2914 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 2915 rd_reg_dword(®->hccr); 2916 2917 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 2918 mdelay(10); 2919 rd_reg_dword(®->hccr); 2920 2921 wd = rd_reg_word(®->mailbox0); 2922 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) { 2923 barrier(); 2924 if (cnt) { 2925 mdelay(1); 2926 if (print && qla_chk_risc_recovery(vha)) 2927 print = 0; 2928 2929 wd = rd_reg_word(®->mailbox0); 2930 } else { 2931 rval = QLA_FUNCTION_TIMEOUT; 2932 2933 ql_log(ql_log_warn, vha, 0x015e, 2934 "RISC reset timeout\n"); 2935 } 2936 } 2937 2938 if (rval == QLA_SUCCESS) 2939 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2940 2941 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 2942 "Host Risc 0x%x, mailbox0 0x%x\n", 2943 rd_reg_dword(®->hccr), 2944 rd_reg_word(®->mailbox0)); 2945 2946 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2947 2948 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 2949 "Driver in %s mode\n", 2950 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 2951 2952 if (IS_NOPOLLING_TYPE(ha)) 2953 ha->isp_ops->enable_intrs(ha); 2954 2955 return rval; 2956 } 2957 2958 static void 2959 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 2960 { 2961 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2962 2963 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2964 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET); 2965 } 2966 2967 static void 2968 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 2969 { 2970 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2971 2972 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2973 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data); 2974 } 2975 2976 static void 2977 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 2978 { 2979 uint32_t wd32 = 0; 2980 uint delta_msec = 100; 2981 uint elapsed_msec = 0; 2982 uint timeout_msec; 2983 ulong n; 2984 2985 if (vha->hw->pdev->subsystem_device != 0x0175 && 2986 vha->hw->pdev->subsystem_device != 0x0240) 2987 return; 2988 2989 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 2990 udelay(100); 2991 2992 attempt: 2993 timeout_msec = TIMEOUT_SEMAPHORE; 2994 n = timeout_msec / delta_msec; 2995 while (n--) { 2996 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 2997 qla25xx_read_risc_sema_reg(vha, &wd32); 2998 if (wd32 & RISC_SEMAPHORE) 2999 break; 3000 msleep(delta_msec); 3001 elapsed_msec += delta_msec; 3002 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3003 goto force; 3004 } 3005 3006 if (!(wd32 & RISC_SEMAPHORE)) 3007 goto force; 3008 3009 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3010 goto acquired; 3011 3012 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 3013 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 3014 n = timeout_msec / delta_msec; 3015 while (n--) { 3016 qla25xx_read_risc_sema_reg(vha, &wd32); 3017 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3018 break; 3019 msleep(delta_msec); 3020 elapsed_msec += delta_msec; 3021 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3022 goto force; 3023 } 3024 3025 if (wd32 & RISC_SEMAPHORE_FORCE) 3026 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 3027 3028 goto attempt; 3029 3030 force: 3031 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 3032 3033 acquired: 3034 return; 3035 } 3036 3037 /** 3038 * qla24xx_reset_chip() - Reset ISP24xx chip. 3039 * @vha: HA context 3040 * 3041 * Returns 0 on success. 3042 */ 3043 int 3044 qla24xx_reset_chip(scsi_qla_host_t *vha) 3045 { 3046 struct qla_hw_data *ha = vha->hw; 3047 int rval = QLA_FUNCTION_FAILED; 3048 3049 if (pci_channel_offline(ha->pdev) && 3050 ha->flags.pci_channel_io_perm_failure) { 3051 return rval; 3052 } 3053 3054 ha->isp_ops->disable_intrs(ha); 3055 3056 qla25xx_manipulate_risc_semaphore(vha); 3057 3058 /* Perform RISC reset. */ 3059 rval = qla24xx_reset_risc(vha); 3060 3061 return rval; 3062 } 3063 3064 /** 3065 * qla2x00_chip_diag() - Test chip for proper operation. 3066 * @vha: HA context 3067 * 3068 * Returns 0 on success. 3069 */ 3070 int 3071 qla2x00_chip_diag(scsi_qla_host_t *vha) 3072 { 3073 int rval; 3074 struct qla_hw_data *ha = vha->hw; 3075 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3076 unsigned long flags = 0; 3077 uint16_t data; 3078 uint32_t cnt; 3079 uint16_t mb[5]; 3080 struct req_que *req = ha->req_q_map[0]; 3081 3082 /* Assume a failed state */ 3083 rval = QLA_FUNCTION_FAILED; 3084 3085 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n", 3086 ®->flash_address); 3087 3088 spin_lock_irqsave(&ha->hardware_lock, flags); 3089 3090 /* Reset ISP chip. */ 3091 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3092 3093 /* 3094 * We need to have a delay here since the card will not respond while 3095 * in reset causing an MCA on some architectures. 3096 */ 3097 udelay(20); 3098 data = qla2x00_debounce_register(®->ctrl_status); 3099 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 3100 udelay(5); 3101 data = rd_reg_word(®->ctrl_status); 3102 barrier(); 3103 } 3104 3105 if (!cnt) 3106 goto chip_diag_failed; 3107 3108 ql_dbg(ql_dbg_init, vha, 0x007c, 3109 "Reset register cleared by chip reset.\n"); 3110 3111 /* Reset RISC processor. */ 3112 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3113 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3114 3115 /* Workaround for QLA2312 PCI parity error */ 3116 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3117 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 3118 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 3119 udelay(5); 3120 data = RD_MAILBOX_REG(ha, reg, 0); 3121 barrier(); 3122 } 3123 } else 3124 udelay(10); 3125 3126 if (!cnt) 3127 goto chip_diag_failed; 3128 3129 /* Check product ID of chip */ 3130 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n"); 3131 3132 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 3133 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 3134 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 3135 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 3136 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 3137 mb[3] != PROD_ID_3) { 3138 ql_log(ql_log_warn, vha, 0x0062, 3139 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 3140 mb[1], mb[2], mb[3]); 3141 3142 goto chip_diag_failed; 3143 } 3144 ha->product_id[0] = mb[1]; 3145 ha->product_id[1] = mb[2]; 3146 ha->product_id[2] = mb[3]; 3147 ha->product_id[3] = mb[4]; 3148 3149 /* Adjust fw RISC transfer size */ 3150 if (req->length > 1024) 3151 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 3152 else 3153 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 3154 req->length; 3155 3156 if (IS_QLA2200(ha) && 3157 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 3158 /* Limit firmware transfer size with a 2200A */ 3159 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 3160 3161 ha->device_type |= DT_ISP2200A; 3162 ha->fw_transfer_size = 128; 3163 } 3164 3165 /* Wrap Incoming Mailboxes Test. */ 3166 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3167 3168 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 3169 rval = qla2x00_mbx_reg_test(vha); 3170 if (rval) 3171 ql_log(ql_log_warn, vha, 0x0080, 3172 "Failed mailbox send register test.\n"); 3173 else 3174 /* Flag a successful rval */ 3175 rval = QLA_SUCCESS; 3176 spin_lock_irqsave(&ha->hardware_lock, flags); 3177 3178 chip_diag_failed: 3179 if (rval) 3180 ql_log(ql_log_info, vha, 0x0081, 3181 "Chip diagnostics **** FAILED ****.\n"); 3182 3183 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3184 3185 return (rval); 3186 } 3187 3188 /** 3189 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 3190 * @vha: HA context 3191 * 3192 * Returns 0 on success. 3193 */ 3194 int 3195 qla24xx_chip_diag(scsi_qla_host_t *vha) 3196 { 3197 int rval; 3198 struct qla_hw_data *ha = vha->hw; 3199 struct req_que *req = ha->req_q_map[0]; 3200 3201 if (IS_P3P_TYPE(ha)) 3202 return QLA_SUCCESS; 3203 3204 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 3205 3206 rval = qla2x00_mbx_reg_test(vha); 3207 if (rval) { 3208 ql_log(ql_log_warn, vha, 0x0082, 3209 "Failed mailbox send register test.\n"); 3210 } else { 3211 /* Flag a successful rval */ 3212 rval = QLA_SUCCESS; 3213 } 3214 3215 return rval; 3216 } 3217 3218 static void 3219 qla2x00_init_fce_trace(scsi_qla_host_t *vha) 3220 { 3221 int rval; 3222 dma_addr_t tc_dma; 3223 void *tc; 3224 struct qla_hw_data *ha = vha->hw; 3225 3226 if (!IS_FWI2_CAPABLE(ha)) 3227 return; 3228 3229 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 3230 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 3231 return; 3232 3233 if (ha->fce) { 3234 ql_dbg(ql_dbg_init, vha, 0x00bd, 3235 "%s: FCE Mem is already allocated.\n", 3236 __func__); 3237 return; 3238 } 3239 3240 /* Allocate memory for Fibre Channel Event Buffer. */ 3241 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 3242 GFP_KERNEL); 3243 if (!tc) { 3244 ql_log(ql_log_warn, vha, 0x00be, 3245 "Unable to allocate (%d KB) for FCE.\n", 3246 FCE_SIZE / 1024); 3247 return; 3248 } 3249 3250 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 3251 ha->fce_mb, &ha->fce_bufs); 3252 if (rval) { 3253 ql_log(ql_log_warn, vha, 0x00bf, 3254 "Unable to initialize FCE (%d).\n", rval); 3255 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, tc_dma); 3256 return; 3257 } 3258 3259 ql_dbg(ql_dbg_init, vha, 0x00c0, 3260 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024); 3261 3262 ha->flags.fce_enabled = 1; 3263 ha->fce_dma = tc_dma; 3264 ha->fce = tc; 3265 } 3266 3267 static void 3268 qla2x00_init_eft_trace(scsi_qla_host_t *vha) 3269 { 3270 int rval; 3271 dma_addr_t tc_dma; 3272 void *tc; 3273 struct qla_hw_data *ha = vha->hw; 3274 3275 if (!IS_FWI2_CAPABLE(ha)) 3276 return; 3277 3278 if (ha->eft) { 3279 ql_dbg(ql_dbg_init, vha, 0x00bd, 3280 "%s: EFT Mem is already allocated.\n", 3281 __func__); 3282 return; 3283 } 3284 3285 /* Allocate memory for Extended Trace Buffer. */ 3286 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 3287 GFP_KERNEL); 3288 if (!tc) { 3289 ql_log(ql_log_warn, vha, 0x00c1, 3290 "Unable to allocate (%d KB) for EFT.\n", 3291 EFT_SIZE / 1024); 3292 return; 3293 } 3294 3295 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 3296 if (rval) { 3297 ql_log(ql_log_warn, vha, 0x00c2, 3298 "Unable to initialize EFT (%d).\n", rval); 3299 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, tc_dma); 3300 return; 3301 } 3302 3303 ql_dbg(ql_dbg_init, vha, 0x00c3, 3304 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 3305 3306 ha->eft_dma = tc_dma; 3307 ha->eft = tc; 3308 } 3309 3310 static void 3311 qla2x00_alloc_offload_mem(scsi_qla_host_t *vha) 3312 { 3313 qla2x00_init_fce_trace(vha); 3314 qla2x00_init_eft_trace(vha); 3315 } 3316 3317 void 3318 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 3319 { 3320 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 3321 eft_size, fce_size, mq_size; 3322 struct qla_hw_data *ha = vha->hw; 3323 struct req_que *req = ha->req_q_map[0]; 3324 struct rsp_que *rsp = ha->rsp_q_map[0]; 3325 struct qla2xxx_fw_dump *fw_dump; 3326 3327 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 3328 req_q_size = rsp_q_size = 0; 3329 3330 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3331 fixed_size = sizeof(struct qla2100_fw_dump); 3332 } else if (IS_QLA23XX(ha)) { 3333 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 3334 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 3335 sizeof(uint16_t); 3336 } else if (IS_FWI2_CAPABLE(ha)) { 3337 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3338 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 3339 else if (IS_QLA81XX(ha)) 3340 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 3341 else if (IS_QLA25XX(ha)) 3342 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 3343 else 3344 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 3345 3346 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 3347 sizeof(uint32_t); 3348 if (ha->mqenable) { 3349 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && 3350 !IS_QLA28XX(ha)) 3351 mq_size = sizeof(struct qla2xxx_mq_chain); 3352 /* 3353 * Allocate maximum buffer size for all queues - Q0. 3354 * Resizing must be done at end-of-dump processing. 3355 */ 3356 mq_size += (ha->max_req_queues - 1) * 3357 (req->length * sizeof(request_t)); 3358 mq_size += (ha->max_rsp_queues - 1) * 3359 (rsp->length * sizeof(response_t)); 3360 } 3361 if (ha->tgt.atio_ring) 3362 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 3363 3364 qla2x00_init_fce_trace(vha); 3365 if (ha->fce) 3366 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 3367 qla2x00_init_eft_trace(vha); 3368 if (ha->eft) 3369 eft_size = EFT_SIZE; 3370 } 3371 3372 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3373 struct fwdt *fwdt = ha->fwdt; 3374 uint j; 3375 3376 for (j = 0; j < 2; j++, fwdt++) { 3377 if (!fwdt->template) { 3378 ql_dbg(ql_dbg_init, vha, 0x00ba, 3379 "-> fwdt%u no template\n", j); 3380 continue; 3381 } 3382 ql_dbg(ql_dbg_init, vha, 0x00fa, 3383 "-> fwdt%u calculating fwdump size...\n", j); 3384 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size( 3385 vha, fwdt->template); 3386 ql_dbg(ql_dbg_init, vha, 0x00fa, 3387 "-> fwdt%u calculated fwdump size = %#lx bytes\n", 3388 j, fwdt->dump_size); 3389 dump_size += fwdt->dump_size; 3390 } 3391 /* Add space for spare MPI fw dump. */ 3392 dump_size += ha->fwdt[1].dump_size; 3393 } else { 3394 req_q_size = req->length * sizeof(request_t); 3395 rsp_q_size = rsp->length * sizeof(response_t); 3396 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 3397 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size 3398 + eft_size; 3399 ha->chain_offset = dump_size; 3400 dump_size += mq_size + fce_size; 3401 if (ha->exchoffld_buf) 3402 dump_size += sizeof(struct qla2xxx_offld_chain) + 3403 ha->exchoffld_size; 3404 if (ha->exlogin_buf) 3405 dump_size += sizeof(struct qla2xxx_offld_chain) + 3406 ha->exlogin_size; 3407 } 3408 3409 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) { 3410 3411 ql_dbg(ql_dbg_init, vha, 0x00c5, 3412 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n", 3413 __func__, dump_size, ha->fw_dump_len, 3414 ha->fw_dump_alloc_len); 3415 3416 fw_dump = vmalloc(dump_size); 3417 if (!fw_dump) { 3418 ql_log(ql_log_warn, vha, 0x00c4, 3419 "Unable to allocate (%d KB) for firmware dump.\n", 3420 dump_size / 1024); 3421 } else { 3422 mutex_lock(&ha->optrom_mutex); 3423 if (ha->fw_dumped) { 3424 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len); 3425 vfree(ha->fw_dump); 3426 ha->fw_dump = fw_dump; 3427 ha->fw_dump_alloc_len = dump_size; 3428 ql_dbg(ql_dbg_init, vha, 0x00c5, 3429 "Re-Allocated (%d KB) and save firmware dump.\n", 3430 dump_size / 1024); 3431 } else { 3432 vfree(ha->fw_dump); 3433 ha->fw_dump = fw_dump; 3434 3435 ha->fw_dump_len = ha->fw_dump_alloc_len = 3436 dump_size; 3437 ql_dbg(ql_dbg_init, vha, 0x00c5, 3438 "Allocated (%d KB) for firmware dump.\n", 3439 dump_size / 1024); 3440 3441 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3442 ha->mpi_fw_dump = (char *)fw_dump + 3443 ha->fwdt[1].dump_size; 3444 mutex_unlock(&ha->optrom_mutex); 3445 return; 3446 } 3447 3448 ha->fw_dump->signature[0] = 'Q'; 3449 ha->fw_dump->signature[1] = 'L'; 3450 ha->fw_dump->signature[2] = 'G'; 3451 ha->fw_dump->signature[3] = 'C'; 3452 ha->fw_dump->version = htonl(1); 3453 3454 ha->fw_dump->fixed_size = htonl(fixed_size); 3455 ha->fw_dump->mem_size = htonl(mem_size); 3456 ha->fw_dump->req_q_size = htonl(req_q_size); 3457 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 3458 3459 ha->fw_dump->eft_size = htonl(eft_size); 3460 ha->fw_dump->eft_addr_l = 3461 htonl(LSD(ha->eft_dma)); 3462 ha->fw_dump->eft_addr_h = 3463 htonl(MSD(ha->eft_dma)); 3464 3465 ha->fw_dump->header_size = 3466 htonl(offsetof 3467 (struct qla2xxx_fw_dump, isp)); 3468 } 3469 mutex_unlock(&ha->optrom_mutex); 3470 } 3471 } 3472 } 3473 3474 static int 3475 qla81xx_mpi_sync(scsi_qla_host_t *vha) 3476 { 3477 #define MPS_MASK 0xe0 3478 int rval; 3479 uint16_t dc; 3480 uint32_t dw; 3481 3482 if (!IS_QLA81XX(vha->hw)) 3483 return QLA_SUCCESS; 3484 3485 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 3486 if (rval != QLA_SUCCESS) { 3487 ql_log(ql_log_warn, vha, 0x0105, 3488 "Unable to acquire semaphore.\n"); 3489 goto done; 3490 } 3491 3492 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 3493 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 3494 if (rval != QLA_SUCCESS) { 3495 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 3496 goto done_release; 3497 } 3498 3499 dc &= MPS_MASK; 3500 if (dc == (dw & MPS_MASK)) 3501 goto done_release; 3502 3503 dw &= ~MPS_MASK; 3504 dw |= dc; 3505 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 3506 if (rval != QLA_SUCCESS) { 3507 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 3508 } 3509 3510 done_release: 3511 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 3512 if (rval != QLA_SUCCESS) { 3513 ql_log(ql_log_warn, vha, 0x006d, 3514 "Unable to release semaphore.\n"); 3515 } 3516 3517 done: 3518 return rval; 3519 } 3520 3521 int 3522 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 3523 { 3524 /* Don't try to reallocate the array */ 3525 if (req->outstanding_cmds) 3526 return QLA_SUCCESS; 3527 3528 if (!IS_FWI2_CAPABLE(ha)) 3529 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 3530 else { 3531 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 3532 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 3533 else 3534 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 3535 } 3536 3537 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3538 sizeof(srb_t *), 3539 GFP_KERNEL); 3540 3541 if (!req->outstanding_cmds) { 3542 /* 3543 * Try to allocate a minimal size just so we can get through 3544 * initialization. 3545 */ 3546 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 3547 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3548 sizeof(srb_t *), 3549 GFP_KERNEL); 3550 3551 if (!req->outstanding_cmds) { 3552 ql_log(ql_log_fatal, NULL, 0x0126, 3553 "Failed to allocate memory for " 3554 "outstanding_cmds for req_que %p.\n", req); 3555 req->num_outstanding_cmds = 0; 3556 return QLA_FUNCTION_FAILED; 3557 } 3558 } 3559 3560 return QLA_SUCCESS; 3561 } 3562 3563 #define PRINT_FIELD(_field, _flag, _str) { \ 3564 if (a0->_field & _flag) {\ 3565 if (p) {\ 3566 strcat(ptr, "|");\ 3567 ptr++;\ 3568 leftover--;\ 3569 } \ 3570 len = snprintf(ptr, leftover, "%s", _str); \ 3571 p = 1;\ 3572 leftover -= len;\ 3573 ptr += len; \ 3574 } \ 3575 } 3576 3577 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha) 3578 { 3579 #define STR_LEN 64 3580 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data; 3581 u8 str[STR_LEN], *ptr, p; 3582 int leftover, len; 3583 3584 memset(str, 0, STR_LEN); 3585 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name); 3586 ql_dbg(ql_dbg_init, vha, 0x015a, 3587 "SFP MFG Name: %s\n", str); 3588 3589 memset(str, 0, STR_LEN); 3590 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn); 3591 ql_dbg(ql_dbg_init, vha, 0x015c, 3592 "SFP Part Name: %s\n", str); 3593 3594 /* media */ 3595 memset(str, 0, STR_LEN); 3596 ptr = str; 3597 leftover = STR_LEN; 3598 p = len = 0; 3599 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX"); 3600 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair"); 3601 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax"); 3602 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax"); 3603 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um"); 3604 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um"); 3605 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode"); 3606 ql_dbg(ql_dbg_init, vha, 0x0160, 3607 "SFP Media: %s\n", str); 3608 3609 /* link length */ 3610 memset(str, 0, STR_LEN); 3611 ptr = str; 3612 leftover = STR_LEN; 3613 p = len = 0; 3614 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long"); 3615 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short"); 3616 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate"); 3617 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long"); 3618 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium"); 3619 ql_dbg(ql_dbg_init, vha, 0x0196, 3620 "SFP Link Length: %s\n", str); 3621 3622 memset(str, 0, STR_LEN); 3623 ptr = str; 3624 leftover = STR_LEN; 3625 p = len = 0; 3626 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)"); 3627 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)"); 3628 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)"); 3629 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)"); 3630 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)"); 3631 ql_dbg(ql_dbg_init, vha, 0x016e, 3632 "SFP FC Link Tech: %s\n", str); 3633 3634 if (a0->length_km) 3635 ql_dbg(ql_dbg_init, vha, 0x016f, 3636 "SFP Distant: %d km\n", a0->length_km); 3637 if (a0->length_100m) 3638 ql_dbg(ql_dbg_init, vha, 0x0170, 3639 "SFP Distant: %d m\n", a0->length_100m*100); 3640 if (a0->length_50um_10m) 3641 ql_dbg(ql_dbg_init, vha, 0x0189, 3642 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10); 3643 if (a0->length_62um_10m) 3644 ql_dbg(ql_dbg_init, vha, 0x018a, 3645 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10); 3646 if (a0->length_om4_10m) 3647 ql_dbg(ql_dbg_init, vha, 0x0194, 3648 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10); 3649 if (a0->length_om3_10m) 3650 ql_dbg(ql_dbg_init, vha, 0x0195, 3651 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10); 3652 } 3653 3654 3655 /** 3656 * qla24xx_detect_sfp() 3657 * 3658 * @vha: adapter state pointer. 3659 * 3660 * @return 3661 * 0 -- Configure firmware to use short-range settings -- normal 3662 * buffer-to-buffer credits. 3663 * 3664 * 1 -- Configure firmware to use long-range settings -- extra 3665 * buffer-to-buffer credits should be allocated with 3666 * ha->lr_distance containing distance settings from NVRAM or SFP 3667 * (if supported). 3668 */ 3669 int 3670 qla24xx_detect_sfp(scsi_qla_host_t *vha) 3671 { 3672 int rc, used_nvram; 3673 struct sff_8247_a0 *a; 3674 struct qla_hw_data *ha = vha->hw; 3675 struct nvram_81xx *nv = ha->nvram; 3676 #define LR_DISTANCE_UNKNOWN 2 3677 static const char * const types[] = { "Short", "Long" }; 3678 static const char * const lengths[] = { "(10km)", "(5km)", "" }; 3679 u8 ll = 0; 3680 3681 /* Seed with NVRAM settings. */ 3682 used_nvram = 0; 3683 ha->flags.lr_detected = 0; 3684 if (IS_BPM_RANGE_CAPABLE(ha) && 3685 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) { 3686 used_nvram = 1; 3687 ha->flags.lr_detected = 1; 3688 ha->lr_distance = 3689 (nv->enhanced_features >> LR_DIST_NV_POS) 3690 & LR_DIST_NV_MASK; 3691 } 3692 3693 if (!IS_BPM_ENABLED(vha)) 3694 goto out; 3695 /* Determine SR/LR capabilities of SFP/Transceiver. */ 3696 rc = qla2x00_read_sfp_dev(vha, NULL, 0); 3697 if (rc) 3698 goto out; 3699 3700 used_nvram = 0; 3701 a = (struct sff_8247_a0 *)vha->hw->sfp_data; 3702 qla2xxx_print_sfp_info(vha); 3703 3704 ha->flags.lr_detected = 0; 3705 ll = a->fc_ll_cc7; 3706 if (ll & FC_LL_VL || ll & FC_LL_L) { 3707 /* Long range, track length. */ 3708 ha->flags.lr_detected = 1; 3709 3710 if (a->length_km > 5 || a->length_100m > 50) 3711 ha->lr_distance = LR_DISTANCE_10K; 3712 else 3713 ha->lr_distance = LR_DISTANCE_5K; 3714 } 3715 3716 out: 3717 ql_dbg(ql_dbg_async, vha, 0x507b, 3718 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n", 3719 types[ha->flags.lr_detected], 3720 ha->flags.lr_detected ? lengths[ha->lr_distance] : 3721 lengths[LR_DISTANCE_UNKNOWN], 3722 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance); 3723 return ha->flags.lr_detected; 3724 } 3725 3726 void qla_init_iocb_limit(scsi_qla_host_t *vha) 3727 { 3728 u16 i, num_qps; 3729 u32 limit; 3730 struct qla_hw_data *ha = vha->hw; 3731 3732 num_qps = ha->num_qpairs + 1; 3733 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 3734 3735 ha->base_qpair->fwres.iocbs_total = ha->orig_fw_iocb_count; 3736 ha->base_qpair->fwres.iocbs_limit = limit; 3737 ha->base_qpair->fwres.iocbs_qp_limit = limit / num_qps; 3738 ha->base_qpair->fwres.iocbs_used = 0; 3739 for (i = 0; i < ha->max_qpairs; i++) { 3740 if (ha->queue_pair_map[i]) { 3741 ha->queue_pair_map[i]->fwres.iocbs_total = 3742 ha->orig_fw_iocb_count; 3743 ha->queue_pair_map[i]->fwres.iocbs_limit = limit; 3744 ha->queue_pair_map[i]->fwres.iocbs_qp_limit = 3745 limit / num_qps; 3746 ha->queue_pair_map[i]->fwres.iocbs_used = 0; 3747 } 3748 } 3749 } 3750 3751 /** 3752 * qla2x00_setup_chip() - Load and start RISC firmware. 3753 * @vha: HA context 3754 * 3755 * Returns 0 on success. 3756 */ 3757 static int 3758 qla2x00_setup_chip(scsi_qla_host_t *vha) 3759 { 3760 int rval; 3761 uint32_t srisc_address = 0; 3762 struct qla_hw_data *ha = vha->hw; 3763 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3764 unsigned long flags; 3765 uint16_t fw_major_version; 3766 int done_once = 0; 3767 3768 if (IS_P3P_TYPE(ha)) { 3769 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3770 if (rval == QLA_SUCCESS) { 3771 qla2x00_stop_firmware(vha); 3772 goto enable_82xx_npiv; 3773 } else 3774 goto failed; 3775 } 3776 3777 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3778 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 3779 spin_lock_irqsave(&ha->hardware_lock, flags); 3780 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 3781 rd_reg_word(®->hccr); 3782 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3783 } 3784 3785 qla81xx_mpi_sync(vha); 3786 3787 execute_fw_with_lr: 3788 /* Load firmware sequences */ 3789 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3790 if (rval == QLA_SUCCESS) { 3791 ql_dbg(ql_dbg_init, vha, 0x00c9, 3792 "Verifying Checksum of loaded RISC code.\n"); 3793 3794 rval = qla2x00_verify_checksum(vha, srisc_address); 3795 if (rval == QLA_SUCCESS) { 3796 /* Start firmware execution. */ 3797 ql_dbg(ql_dbg_init, vha, 0x00ca, 3798 "Starting firmware.\n"); 3799 3800 if (ql2xexlogins) 3801 ha->flags.exlogins_enabled = 1; 3802 3803 if (qla_is_exch_offld_enabled(vha)) 3804 ha->flags.exchoffld_enabled = 1; 3805 3806 rval = qla2x00_execute_fw(vha, srisc_address); 3807 /* Retrieve firmware information. */ 3808 if (rval == QLA_SUCCESS) { 3809 /* Enable BPM support? */ 3810 if (!done_once++ && qla24xx_detect_sfp(vha)) { 3811 ql_dbg(ql_dbg_init, vha, 0x00ca, 3812 "Re-starting firmware -- BPM.\n"); 3813 /* Best-effort - re-init. */ 3814 ha->isp_ops->reset_chip(vha); 3815 ha->isp_ops->chip_diag(vha); 3816 goto execute_fw_with_lr; 3817 } 3818 3819 if (IS_ZIO_THRESHOLD_CAPABLE(ha)) 3820 qla27xx_set_zio_threshold(vha, 3821 ha->last_zio_threshold); 3822 3823 rval = qla2x00_set_exlogins_buffer(vha); 3824 if (rval != QLA_SUCCESS) 3825 goto failed; 3826 3827 rval = qla2x00_set_exchoffld_buffer(vha); 3828 if (rval != QLA_SUCCESS) 3829 goto failed; 3830 3831 enable_82xx_npiv: 3832 fw_major_version = ha->fw_major_version; 3833 if (IS_P3P_TYPE(ha)) 3834 qla82xx_check_md_needed(vha); 3835 else 3836 rval = qla2x00_get_fw_version(vha); 3837 if (rval != QLA_SUCCESS) 3838 goto failed; 3839 ha->flags.npiv_supported = 0; 3840 if (IS_QLA2XXX_MIDTYPE(ha) && 3841 (ha->fw_attributes & BIT_2)) { 3842 ha->flags.npiv_supported = 1; 3843 if ((!ha->max_npiv_vports) || 3844 ((ha->max_npiv_vports + 1) % 3845 MIN_MULTI_ID_FABRIC)) 3846 ha->max_npiv_vports = 3847 MIN_MULTI_ID_FABRIC - 1; 3848 } 3849 qla2x00_get_resource_cnts(vha); 3850 qla_init_iocb_limit(vha); 3851 3852 /* 3853 * Allocate the array of outstanding commands 3854 * now that we know the firmware resources. 3855 */ 3856 rval = qla2x00_alloc_outstanding_cmds(ha, 3857 vha->req); 3858 if (rval != QLA_SUCCESS) 3859 goto failed; 3860 3861 if (!fw_major_version && !(IS_P3P_TYPE(ha))) 3862 qla2x00_alloc_offload_mem(vha); 3863 3864 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha))) 3865 qla2x00_alloc_fw_dump(vha); 3866 3867 } else { 3868 goto failed; 3869 } 3870 } else { 3871 ql_log(ql_log_fatal, vha, 0x00cd, 3872 "ISP Firmware failed checksum.\n"); 3873 goto failed; 3874 } 3875 3876 /* Enable PUREX PASSTHRU */ 3877 if (ql2xrdpenable || ha->flags.scm_supported_f) 3878 qla25xx_set_els_cmds_supported(vha); 3879 } else 3880 goto failed; 3881 3882 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3883 /* Enable proper parity. */ 3884 spin_lock_irqsave(&ha->hardware_lock, flags); 3885 if (IS_QLA2300(ha)) 3886 /* SRAM parity */ 3887 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1); 3888 else 3889 /* SRAM, Instruction RAM and GP RAM parity */ 3890 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7); 3891 rd_reg_word(®->hccr); 3892 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3893 } 3894 3895 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3896 ha->flags.fac_supported = 1; 3897 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 3898 uint32_t size; 3899 3900 rval = qla81xx_fac_get_sector_size(vha, &size); 3901 if (rval == QLA_SUCCESS) { 3902 ha->flags.fac_supported = 1; 3903 ha->fdt_block_size = size << 2; 3904 } else { 3905 ql_log(ql_log_warn, vha, 0x00ce, 3906 "Unsupported FAC firmware (%d.%02d.%02d).\n", 3907 ha->fw_major_version, ha->fw_minor_version, 3908 ha->fw_subminor_version); 3909 3910 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3911 IS_QLA28XX(ha)) { 3912 ha->flags.fac_supported = 0; 3913 rval = QLA_SUCCESS; 3914 } 3915 } 3916 } 3917 failed: 3918 if (rval) { 3919 ql_log(ql_log_fatal, vha, 0x00cf, 3920 "Setup chip ****FAILED****.\n"); 3921 } 3922 3923 return (rval); 3924 } 3925 3926 /** 3927 * qla2x00_init_response_q_entries() - Initializes response queue entries. 3928 * @rsp: response queue 3929 * 3930 * Beginning of request ring has initialization control block already built 3931 * by nvram config routine. 3932 * 3933 * Returns 0 on success. 3934 */ 3935 void 3936 qla2x00_init_response_q_entries(struct rsp_que *rsp) 3937 { 3938 uint16_t cnt; 3939 response_t *pkt; 3940 3941 rsp->ring_ptr = rsp->ring; 3942 rsp->ring_index = 0; 3943 rsp->status_srb = NULL; 3944 pkt = rsp->ring_ptr; 3945 for (cnt = 0; cnt < rsp->length; cnt++) { 3946 pkt->signature = RESPONSE_PROCESSED; 3947 pkt++; 3948 } 3949 } 3950 3951 /** 3952 * qla2x00_update_fw_options() - Read and process firmware options. 3953 * @vha: HA context 3954 * 3955 * Returns 0 on success. 3956 */ 3957 void 3958 qla2x00_update_fw_options(scsi_qla_host_t *vha) 3959 { 3960 uint16_t swing, emphasis, tx_sens, rx_sens; 3961 struct qla_hw_data *ha = vha->hw; 3962 3963 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 3964 qla2x00_get_fw_options(vha, ha->fw_options); 3965 3966 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 3967 return; 3968 3969 /* Serial Link options. */ 3970 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 3971 "Serial link options.\n"); 3972 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 3973 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options)); 3974 3975 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 3976 if (ha->fw_seriallink_options[3] & BIT_2) { 3977 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 3978 3979 /* 1G settings */ 3980 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 3981 emphasis = (ha->fw_seriallink_options[2] & 3982 (BIT_4 | BIT_3)) >> 3; 3983 tx_sens = ha->fw_seriallink_options[0] & 3984 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 3985 rx_sens = (ha->fw_seriallink_options[0] & 3986 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 3987 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 3988 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 3989 if (rx_sens == 0x0) 3990 rx_sens = 0x3; 3991 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 3992 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3993 ha->fw_options[10] |= BIT_5 | 3994 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 3995 (tx_sens & (BIT_1 | BIT_0)); 3996 3997 /* 2G settings */ 3998 swing = (ha->fw_seriallink_options[2] & 3999 (BIT_7 | BIT_6 | BIT_5)) >> 5; 4000 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 4001 tx_sens = ha->fw_seriallink_options[1] & 4002 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4003 rx_sens = (ha->fw_seriallink_options[1] & 4004 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4005 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 4006 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4007 if (rx_sens == 0x0) 4008 rx_sens = 0x3; 4009 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 4010 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4011 ha->fw_options[11] |= BIT_5 | 4012 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4013 (tx_sens & (BIT_1 | BIT_0)); 4014 } 4015 4016 /* FCP2 options. */ 4017 /* Return command IOCBs without waiting for an ABTS to complete. */ 4018 ha->fw_options[3] |= BIT_13; 4019 4020 /* LED scheme. */ 4021 if (ha->flags.enable_led_scheme) 4022 ha->fw_options[2] |= BIT_12; 4023 4024 /* Detect ISP6312. */ 4025 if (IS_QLA6312(ha)) 4026 ha->fw_options[2] |= BIT_13; 4027 4028 /* Set Retry FLOGI in case of P2P connection */ 4029 if (ha->operating_mode == P2P) { 4030 ha->fw_options[2] |= BIT_3; 4031 ql_dbg(ql_dbg_disc, vha, 0x2100, 4032 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4033 __func__, ha->fw_options[2]); 4034 } 4035 4036 /* Update firmware options. */ 4037 qla2x00_set_fw_options(vha, ha->fw_options); 4038 } 4039 4040 void 4041 qla24xx_update_fw_options(scsi_qla_host_t *vha) 4042 { 4043 int rval; 4044 struct qla_hw_data *ha = vha->hw; 4045 4046 if (IS_P3P_TYPE(ha)) 4047 return; 4048 4049 /* Hold status IOCBs until ABTS response received. */ 4050 if (ql2xfwholdabts) 4051 ha->fw_options[3] |= BIT_12; 4052 4053 /* Set Retry FLOGI in case of P2P connection */ 4054 if (ha->operating_mode == P2P) { 4055 ha->fw_options[2] |= BIT_3; 4056 ql_dbg(ql_dbg_disc, vha, 0x2101, 4057 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4058 __func__, ha->fw_options[2]); 4059 } 4060 4061 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 4062 if (ql2xmvasynctoatio && 4063 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 4064 if (qla_tgt_mode_enabled(vha) || 4065 qla_dual_mode_enabled(vha)) 4066 ha->fw_options[2] |= BIT_11; 4067 else 4068 ha->fw_options[2] &= ~BIT_11; 4069 } 4070 4071 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4072 IS_QLA28XX(ha)) { 4073 /* 4074 * Tell FW to track each exchange to prevent 4075 * driver from using stale exchange. 4076 */ 4077 if (qla_tgt_mode_enabled(vha) || 4078 qla_dual_mode_enabled(vha)) 4079 ha->fw_options[2] |= BIT_4; 4080 else 4081 ha->fw_options[2] &= ~BIT_4; 4082 4083 /* Reserve 1/2 of emergency exchanges for ELS.*/ 4084 if (qla2xuseresexchforels) 4085 ha->fw_options[2] |= BIT_8; 4086 else 4087 ha->fw_options[2] &= ~BIT_8; 4088 } 4089 4090 if (ql2xrdpenable || ha->flags.scm_supported_f) 4091 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB; 4092 4093 /* Enable Async 8130/8131 events -- transceiver insertion/removal */ 4094 if (IS_BPM_RANGE_CAPABLE(ha)) 4095 ha->fw_options[3] |= BIT_10; 4096 4097 ql_dbg(ql_dbg_init, vha, 0x00e8, 4098 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 4099 __func__, ha->fw_options[1], ha->fw_options[2], 4100 ha->fw_options[3], vha->host->active_mode); 4101 4102 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3]) 4103 qla2x00_set_fw_options(vha, ha->fw_options); 4104 4105 /* Update Serial Link options. */ 4106 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 4107 return; 4108 4109 rval = qla2x00_set_serdes_params(vha, 4110 le16_to_cpu(ha->fw_seriallink_options24[1]), 4111 le16_to_cpu(ha->fw_seriallink_options24[2]), 4112 le16_to_cpu(ha->fw_seriallink_options24[3])); 4113 if (rval != QLA_SUCCESS) { 4114 ql_log(ql_log_warn, vha, 0x0104, 4115 "Unable to update Serial Link options (%x).\n", rval); 4116 } 4117 } 4118 4119 void 4120 qla2x00_config_rings(struct scsi_qla_host *vha) 4121 { 4122 struct qla_hw_data *ha = vha->hw; 4123 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4124 struct req_que *req = ha->req_q_map[0]; 4125 struct rsp_que *rsp = ha->rsp_q_map[0]; 4126 4127 /* Setup ring parameters in initialization control block. */ 4128 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 4129 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 4130 ha->init_cb->request_q_length = cpu_to_le16(req->length); 4131 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 4132 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address); 4133 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address); 4134 4135 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0); 4136 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0); 4137 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0); 4138 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0); 4139 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 4140 } 4141 4142 void 4143 qla24xx_config_rings(struct scsi_qla_host *vha) 4144 { 4145 struct qla_hw_data *ha = vha->hw; 4146 device_reg_t *reg = ISP_QUE_REG(ha, 0); 4147 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 4148 struct qla_msix_entry *msix; 4149 struct init_cb_24xx *icb; 4150 uint16_t rid = 0; 4151 struct req_que *req = ha->req_q_map[0]; 4152 struct rsp_que *rsp = ha->rsp_q_map[0]; 4153 4154 /* Setup ring parameters in initialization control block. */ 4155 icb = (struct init_cb_24xx *)ha->init_cb; 4156 icb->request_q_outpointer = cpu_to_le16(0); 4157 icb->response_q_inpointer = cpu_to_le16(0); 4158 icb->request_q_length = cpu_to_le16(req->length); 4159 icb->response_q_length = cpu_to_le16(rsp->length); 4160 put_unaligned_le64(req->dma, &icb->request_q_address); 4161 put_unaligned_le64(rsp->dma, &icb->response_q_address); 4162 4163 /* Setup ATIO queue dma pointers for target mode */ 4164 icb->atio_q_inpointer = cpu_to_le16(0); 4165 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 4166 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address); 4167 4168 if (IS_SHADOW_REG_CAPABLE(ha)) 4169 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 4170 4171 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4172 IS_QLA28XX(ha)) { 4173 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 4174 icb->rid = cpu_to_le16(rid); 4175 if (ha->flags.msix_enabled) { 4176 msix = &ha->msix_entries[1]; 4177 ql_dbg(ql_dbg_init, vha, 0x0019, 4178 "Registering vector 0x%x for base que.\n", 4179 msix->entry); 4180 icb->msix = cpu_to_le16(msix->entry); 4181 } 4182 /* Use alternate PCI bus number */ 4183 if (MSB(rid)) 4184 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 4185 /* Use alternate PCI devfn */ 4186 if (LSB(rid)) 4187 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 4188 4189 /* Use Disable MSIX Handshake mode for capable adapters */ 4190 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 4191 (ha->flags.msix_enabled)) { 4192 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 4193 ha->flags.disable_msix_handshake = 1; 4194 ql_dbg(ql_dbg_init, vha, 0x00fe, 4195 "MSIX Handshake Disable Mode turned on.\n"); 4196 } else { 4197 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 4198 } 4199 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 4200 4201 wrt_reg_dword(®->isp25mq.req_q_in, 0); 4202 wrt_reg_dword(®->isp25mq.req_q_out, 0); 4203 wrt_reg_dword(®->isp25mq.rsp_q_in, 0); 4204 wrt_reg_dword(®->isp25mq.rsp_q_out, 0); 4205 } else { 4206 wrt_reg_dword(®->isp24.req_q_in, 0); 4207 wrt_reg_dword(®->isp24.req_q_out, 0); 4208 wrt_reg_dword(®->isp24.rsp_q_in, 0); 4209 wrt_reg_dword(®->isp24.rsp_q_out, 0); 4210 } 4211 4212 qlt_24xx_config_rings(vha); 4213 4214 /* If the user has configured the speed, set it here */ 4215 if (ha->set_data_rate) { 4216 ql_dbg(ql_dbg_init, vha, 0x00fd, 4217 "Speed set by user : %s Gbps \n", 4218 qla2x00_get_link_speed_str(ha, ha->set_data_rate)); 4219 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13); 4220 } 4221 4222 /* PCI posting */ 4223 rd_reg_word(&ioreg->hccr); 4224 } 4225 4226 /** 4227 * qla2x00_init_rings() - Initializes firmware. 4228 * @vha: HA context 4229 * 4230 * Beginning of request ring has initialization control block already built 4231 * by nvram config routine. 4232 * 4233 * Returns 0 on success. 4234 */ 4235 int 4236 qla2x00_init_rings(scsi_qla_host_t *vha) 4237 { 4238 int rval; 4239 unsigned long flags = 0; 4240 int cnt, que; 4241 struct qla_hw_data *ha = vha->hw; 4242 struct req_que *req; 4243 struct rsp_que *rsp; 4244 struct mid_init_cb_24xx *mid_init_cb = 4245 (struct mid_init_cb_24xx *) ha->init_cb; 4246 4247 spin_lock_irqsave(&ha->hardware_lock, flags); 4248 4249 /* Clear outstanding commands array. */ 4250 for (que = 0; que < ha->max_req_queues; que++) { 4251 req = ha->req_q_map[que]; 4252 if (!req || !test_bit(que, ha->req_qid_map)) 4253 continue; 4254 req->out_ptr = (uint16_t *)(req->ring + req->length); 4255 *req->out_ptr = 0; 4256 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 4257 req->outstanding_cmds[cnt] = NULL; 4258 4259 req->current_outstanding_cmd = 1; 4260 4261 /* Initialize firmware. */ 4262 req->ring_ptr = req->ring; 4263 req->ring_index = 0; 4264 req->cnt = req->length; 4265 } 4266 4267 for (que = 0; que < ha->max_rsp_queues; que++) { 4268 rsp = ha->rsp_q_map[que]; 4269 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 4270 continue; 4271 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length); 4272 *rsp->in_ptr = 0; 4273 /* Initialize response queue entries */ 4274 if (IS_QLAFX00(ha)) 4275 qlafx00_init_response_q_entries(rsp); 4276 else 4277 qla2x00_init_response_q_entries(rsp); 4278 } 4279 4280 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 4281 ha->tgt.atio_ring_index = 0; 4282 /* Initialize ATIO queue entries */ 4283 qlt_init_atio_q_entries(vha); 4284 4285 ha->isp_ops->config_rings(vha); 4286 4287 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4288 4289 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 4290 4291 if (IS_QLAFX00(ha)) { 4292 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 4293 goto next_check; 4294 } 4295 4296 /* Update any ISP specific firmware options before initialization. */ 4297 ha->isp_ops->update_fw_options(vha); 4298 4299 if (ha->flags.npiv_supported) { 4300 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 4301 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 4302 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 4303 } 4304 4305 if (IS_FWI2_CAPABLE(ha)) { 4306 mid_init_cb->options = cpu_to_le16(BIT_1); 4307 mid_init_cb->init_cb.execution_throttle = 4308 cpu_to_le16(ha->cur_fw_xcb_count); 4309 ha->flags.dport_enabled = 4310 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4311 BIT_7) != 0; 4312 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 4313 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 4314 /* FA-WWPN Status */ 4315 ha->flags.fawwpn_enabled = 4316 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4317 BIT_6) != 0; 4318 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n", 4319 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 4320 } 4321 4322 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 4323 next_check: 4324 if (rval) { 4325 ql_log(ql_log_fatal, vha, 0x00d2, 4326 "Init Firmware **** FAILED ****.\n"); 4327 } else { 4328 ql_dbg(ql_dbg_init, vha, 0x00d3, 4329 "Init Firmware -- success.\n"); 4330 QLA_FW_STARTED(ha); 4331 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0; 4332 } 4333 4334 return (rval); 4335 } 4336 4337 /** 4338 * qla2x00_fw_ready() - Waits for firmware ready. 4339 * @vha: HA context 4340 * 4341 * Returns 0 on success. 4342 */ 4343 static int 4344 qla2x00_fw_ready(scsi_qla_host_t *vha) 4345 { 4346 int rval; 4347 unsigned long wtime, mtime, cs84xx_time; 4348 uint16_t min_wait; /* Minimum wait time if loop is down */ 4349 uint16_t wait_time; /* Wait time if loop is coming ready */ 4350 uint16_t state[6]; 4351 struct qla_hw_data *ha = vha->hw; 4352 4353 if (IS_QLAFX00(vha->hw)) 4354 return qlafx00_fw_ready(vha); 4355 4356 rval = QLA_SUCCESS; 4357 4358 /* Time to wait for loop down */ 4359 if (IS_P3P_TYPE(ha)) 4360 min_wait = 30; 4361 else 4362 min_wait = 20; 4363 4364 /* 4365 * Firmware should take at most one RATOV to login, plus 5 seconds for 4366 * our own processing. 4367 */ 4368 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 4369 wait_time = min_wait; 4370 } 4371 4372 /* Min wait time if loop down */ 4373 mtime = jiffies + (min_wait * HZ); 4374 4375 /* wait time before firmware ready */ 4376 wtime = jiffies + (wait_time * HZ); 4377 4378 /* Wait for ISP to finish LIP */ 4379 if (!vha->flags.init_done) 4380 ql_log(ql_log_info, vha, 0x801e, 4381 "Waiting for LIP to complete.\n"); 4382 4383 do { 4384 memset(state, -1, sizeof(state)); 4385 rval = qla2x00_get_firmware_state(vha, state); 4386 if (rval == QLA_SUCCESS) { 4387 if (state[0] < FSTATE_LOSS_OF_SYNC) { 4388 vha->device_flags &= ~DFLG_NO_CABLE; 4389 } 4390 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 4391 ql_dbg(ql_dbg_taskm, vha, 0x801f, 4392 "fw_state=%x 84xx=%x.\n", state[0], 4393 state[2]); 4394 if ((state[2] & FSTATE_LOGGED_IN) && 4395 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 4396 ql_dbg(ql_dbg_taskm, vha, 0x8028, 4397 "Sending verify iocb.\n"); 4398 4399 cs84xx_time = jiffies; 4400 rval = qla84xx_init_chip(vha); 4401 if (rval != QLA_SUCCESS) { 4402 ql_log(ql_log_warn, 4403 vha, 0x8007, 4404 "Init chip failed.\n"); 4405 break; 4406 } 4407 4408 /* Add time taken to initialize. */ 4409 cs84xx_time = jiffies - cs84xx_time; 4410 wtime += cs84xx_time; 4411 mtime += cs84xx_time; 4412 ql_dbg(ql_dbg_taskm, vha, 0x8008, 4413 "Increasing wait time by %ld. " 4414 "New time %ld.\n", cs84xx_time, 4415 wtime); 4416 } 4417 } else if (state[0] == FSTATE_READY) { 4418 ql_dbg(ql_dbg_taskm, vha, 0x8037, 4419 "F/W Ready - OK.\n"); 4420 4421 qla2x00_get_retry_cnt(vha, &ha->retry_count, 4422 &ha->login_timeout, &ha->r_a_tov); 4423 4424 rval = QLA_SUCCESS; 4425 break; 4426 } 4427 4428 rval = QLA_FUNCTION_FAILED; 4429 4430 if (atomic_read(&vha->loop_down_timer) && 4431 state[0] != FSTATE_READY) { 4432 /* Loop down. Timeout on min_wait for states 4433 * other than Wait for Login. 4434 */ 4435 if (time_after_eq(jiffies, mtime)) { 4436 ql_log(ql_log_info, vha, 0x8038, 4437 "Cable is unplugged...\n"); 4438 4439 vha->device_flags |= DFLG_NO_CABLE; 4440 break; 4441 } 4442 } 4443 } else { 4444 /* Mailbox cmd failed. Timeout on min_wait. */ 4445 if (time_after_eq(jiffies, mtime) || 4446 ha->flags.isp82xx_fw_hung) 4447 break; 4448 } 4449 4450 if (time_after_eq(jiffies, wtime)) 4451 break; 4452 4453 /* Delay for a while */ 4454 msleep(500); 4455 } while (1); 4456 4457 ql_dbg(ql_dbg_taskm, vha, 0x803a, 4458 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 4459 state[1], state[2], state[3], state[4], state[5], jiffies); 4460 4461 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 4462 ql_log(ql_log_warn, vha, 0x803b, 4463 "Firmware ready **** FAILED ****.\n"); 4464 } 4465 4466 return (rval); 4467 } 4468 4469 /* 4470 * qla2x00_configure_hba 4471 * Setup adapter context. 4472 * 4473 * Input: 4474 * ha = adapter state pointer. 4475 * 4476 * Returns: 4477 * 0 = success 4478 * 4479 * Context: 4480 * Kernel context. 4481 */ 4482 static int 4483 qla2x00_configure_hba(scsi_qla_host_t *vha) 4484 { 4485 int rval; 4486 uint16_t loop_id; 4487 uint16_t topo; 4488 uint16_t sw_cap; 4489 uint8_t al_pa; 4490 uint8_t area; 4491 uint8_t domain; 4492 char connect_type[22]; 4493 struct qla_hw_data *ha = vha->hw; 4494 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4495 port_id_t id; 4496 unsigned long flags; 4497 4498 /* Get host addresses. */ 4499 rval = qla2x00_get_adapter_id(vha, 4500 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 4501 if (rval != QLA_SUCCESS) { 4502 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 4503 IS_CNA_CAPABLE(ha) || 4504 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 4505 ql_dbg(ql_dbg_disc, vha, 0x2008, 4506 "Loop is in a transition state.\n"); 4507 } else { 4508 ql_log(ql_log_warn, vha, 0x2009, 4509 "Unable to get host loop ID.\n"); 4510 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 4511 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 4512 ql_log(ql_log_warn, vha, 0x1151, 4513 "Doing link init.\n"); 4514 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 4515 return rval; 4516 } 4517 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 4518 } 4519 return (rval); 4520 } 4521 4522 if (topo == 4) { 4523 ql_log(ql_log_info, vha, 0x200a, 4524 "Cannot get topology - retrying.\n"); 4525 return (QLA_FUNCTION_FAILED); 4526 } 4527 4528 vha->loop_id = loop_id; 4529 4530 /* initialize */ 4531 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 4532 ha->operating_mode = LOOP; 4533 ha->switch_cap = 0; 4534 4535 switch (topo) { 4536 case 0: 4537 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 4538 ha->current_topology = ISP_CFG_NL; 4539 strcpy(connect_type, "(Loop)"); 4540 break; 4541 4542 case 1: 4543 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 4544 ha->switch_cap = sw_cap; 4545 ha->current_topology = ISP_CFG_FL; 4546 strcpy(connect_type, "(FL_Port)"); 4547 break; 4548 4549 case 2: 4550 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 4551 ha->operating_mode = P2P; 4552 ha->current_topology = ISP_CFG_N; 4553 strcpy(connect_type, "(N_Port-to-N_Port)"); 4554 break; 4555 4556 case 3: 4557 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 4558 ha->switch_cap = sw_cap; 4559 ha->operating_mode = P2P; 4560 ha->current_topology = ISP_CFG_F; 4561 strcpy(connect_type, "(F_Port)"); 4562 break; 4563 4564 default: 4565 ql_dbg(ql_dbg_disc, vha, 0x200f, 4566 "HBA in unknown topology %x, using NL.\n", topo); 4567 ha->current_topology = ISP_CFG_NL; 4568 strcpy(connect_type, "(Loop)"); 4569 break; 4570 } 4571 4572 /* Save Host port and loop ID. */ 4573 /* byte order - Big Endian */ 4574 id.b.domain = domain; 4575 id.b.area = area; 4576 id.b.al_pa = al_pa; 4577 id.b.rsvd_1 = 0; 4578 spin_lock_irqsave(&ha->hardware_lock, flags); 4579 if (!(topo == 2 && ha->flags.n2n_bigger)) 4580 qlt_update_host_map(vha, id); 4581 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4582 4583 if (!vha->flags.init_done) 4584 ql_log(ql_log_info, vha, 0x2010, 4585 "Topology - %s, Host Loop address 0x%x.\n", 4586 connect_type, vha->loop_id); 4587 4588 return(rval); 4589 } 4590 4591 inline void 4592 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 4593 const char *def) 4594 { 4595 char *st, *en; 4596 uint16_t index; 4597 uint64_t zero[2] = { 0 }; 4598 struct qla_hw_data *ha = vha->hw; 4599 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 4600 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 4601 4602 if (len > sizeof(zero)) 4603 len = sizeof(zero); 4604 if (memcmp(model, &zero, len) != 0) { 4605 memcpy(ha->model_number, model, len); 4606 st = en = ha->model_number; 4607 en += len - 1; 4608 while (en > st) { 4609 if (*en != 0x20 && *en != 0x00) 4610 break; 4611 *en-- = '\0'; 4612 } 4613 4614 index = (ha->pdev->subsystem_device & 0xff); 4615 if (use_tbl && 4616 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4617 index < QLA_MODEL_NAMES) 4618 strlcpy(ha->model_desc, 4619 qla2x00_model_name[index * 2 + 1], 4620 sizeof(ha->model_desc)); 4621 } else { 4622 index = (ha->pdev->subsystem_device & 0xff); 4623 if (use_tbl && 4624 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4625 index < QLA_MODEL_NAMES) { 4626 strlcpy(ha->model_number, 4627 qla2x00_model_name[index * 2], 4628 sizeof(ha->model_number)); 4629 strlcpy(ha->model_desc, 4630 qla2x00_model_name[index * 2 + 1], 4631 sizeof(ha->model_desc)); 4632 } else { 4633 strlcpy(ha->model_number, def, 4634 sizeof(ha->model_number)); 4635 } 4636 } 4637 if (IS_FWI2_CAPABLE(ha)) 4638 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 4639 sizeof(ha->model_desc)); 4640 } 4641 4642 /* On sparc systems, obtain port and node WWN from firmware 4643 * properties. 4644 */ 4645 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 4646 { 4647 #ifdef CONFIG_SPARC 4648 struct qla_hw_data *ha = vha->hw; 4649 struct pci_dev *pdev = ha->pdev; 4650 struct device_node *dp = pci_device_to_OF_node(pdev); 4651 const u8 *val; 4652 int len; 4653 4654 val = of_get_property(dp, "port-wwn", &len); 4655 if (val && len >= WWN_SIZE) 4656 memcpy(nv->port_name, val, WWN_SIZE); 4657 4658 val = of_get_property(dp, "node-wwn", &len); 4659 if (val && len >= WWN_SIZE) 4660 memcpy(nv->node_name, val, WWN_SIZE); 4661 #endif 4662 } 4663 4664 /* 4665 * NVRAM configuration for ISP 2xxx 4666 * 4667 * Input: 4668 * ha = adapter block pointer. 4669 * 4670 * Output: 4671 * initialization control block in response_ring 4672 * host adapters parameters in host adapter block 4673 * 4674 * Returns: 4675 * 0 = success. 4676 */ 4677 int 4678 qla2x00_nvram_config(scsi_qla_host_t *vha) 4679 { 4680 int rval; 4681 uint8_t chksum = 0; 4682 uint16_t cnt; 4683 uint8_t *dptr1, *dptr2; 4684 struct qla_hw_data *ha = vha->hw; 4685 init_cb_t *icb = ha->init_cb; 4686 nvram_t *nv = ha->nvram; 4687 uint8_t *ptr = ha->nvram; 4688 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4689 4690 rval = QLA_SUCCESS; 4691 4692 /* Determine NVRAM starting address. */ 4693 ha->nvram_size = sizeof(*nv); 4694 ha->nvram_base = 0; 4695 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 4696 if ((rd_reg_word(®->ctrl_status) >> 14) == 1) 4697 ha->nvram_base = 0x80; 4698 4699 /* Get NVRAM data and calculate checksum. */ 4700 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 4701 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 4702 chksum += *ptr++; 4703 4704 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 4705 "Contents of NVRAM.\n"); 4706 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 4707 nv, ha->nvram_size); 4708 4709 /* Bad NVRAM data, set defaults parameters. */ 4710 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 4711 nv->nvram_version < 1) { 4712 /* Reset NVRAM data. */ 4713 ql_log(ql_log_warn, vha, 0x0064, 4714 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n", 4715 chksum, nv->id, nv->nvram_version); 4716 ql_log(ql_log_warn, vha, 0x0065, 4717 "Falling back to " 4718 "functioning (yet invalid -- WWPN) defaults.\n"); 4719 4720 /* 4721 * Set default initialization control block. 4722 */ 4723 memset(nv, 0, ha->nvram_size); 4724 nv->parameter_block_version = ICB_VERSION; 4725 4726 if (IS_QLA23XX(ha)) { 4727 nv->firmware_options[0] = BIT_2 | BIT_1; 4728 nv->firmware_options[1] = BIT_7 | BIT_5; 4729 nv->add_firmware_options[0] = BIT_5; 4730 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4731 nv->frame_payload_size = cpu_to_le16(2048); 4732 nv->special_options[1] = BIT_7; 4733 } else if (IS_QLA2200(ha)) { 4734 nv->firmware_options[0] = BIT_2 | BIT_1; 4735 nv->firmware_options[1] = BIT_7 | BIT_5; 4736 nv->add_firmware_options[0] = BIT_5; 4737 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4738 nv->frame_payload_size = cpu_to_le16(1024); 4739 } else if (IS_QLA2100(ha)) { 4740 nv->firmware_options[0] = BIT_3 | BIT_1; 4741 nv->firmware_options[1] = BIT_5; 4742 nv->frame_payload_size = cpu_to_le16(1024); 4743 } 4744 4745 nv->max_iocb_allocation = cpu_to_le16(256); 4746 nv->execution_throttle = cpu_to_le16(16); 4747 nv->retry_count = 8; 4748 nv->retry_delay = 1; 4749 4750 nv->port_name[0] = 33; 4751 nv->port_name[3] = 224; 4752 nv->port_name[4] = 139; 4753 4754 qla2xxx_nvram_wwn_from_ofw(vha, nv); 4755 4756 nv->login_timeout = 4; 4757 4758 /* 4759 * Set default host adapter parameters 4760 */ 4761 nv->host_p[1] = BIT_2; 4762 nv->reset_delay = 5; 4763 nv->port_down_retry_count = 8; 4764 nv->max_luns_per_target = cpu_to_le16(8); 4765 nv->link_down_timeout = 60; 4766 4767 rval = 1; 4768 } 4769 4770 /* Reset Initialization control block */ 4771 memset(icb, 0, ha->init_cb_size); 4772 4773 /* 4774 * Setup driver NVRAM options. 4775 */ 4776 nv->firmware_options[0] |= (BIT_6 | BIT_1); 4777 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 4778 nv->firmware_options[1] |= (BIT_5 | BIT_0); 4779 nv->firmware_options[1] &= ~BIT_4; 4780 4781 if (IS_QLA23XX(ha)) { 4782 nv->firmware_options[0] |= BIT_2; 4783 nv->firmware_options[0] &= ~BIT_3; 4784 nv->special_options[0] &= ~BIT_6; 4785 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 4786 4787 if (IS_QLA2300(ha)) { 4788 if (ha->fb_rev == FPM_2310) { 4789 strcpy(ha->model_number, "QLA2310"); 4790 } else { 4791 strcpy(ha->model_number, "QLA2300"); 4792 } 4793 } else { 4794 qla2x00_set_model_info(vha, nv->model_number, 4795 sizeof(nv->model_number), "QLA23xx"); 4796 } 4797 } else if (IS_QLA2200(ha)) { 4798 nv->firmware_options[0] |= BIT_2; 4799 /* 4800 * 'Point-to-point preferred, else loop' is not a safe 4801 * connection mode setting. 4802 */ 4803 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 4804 (BIT_5 | BIT_4)) { 4805 /* Force 'loop preferred, else point-to-point'. */ 4806 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 4807 nv->add_firmware_options[0] |= BIT_5; 4808 } 4809 strcpy(ha->model_number, "QLA22xx"); 4810 } else /*if (IS_QLA2100(ha))*/ { 4811 strcpy(ha->model_number, "QLA2100"); 4812 } 4813 4814 /* 4815 * Copy over NVRAM RISC parameter block to initialization control block. 4816 */ 4817 dptr1 = (uint8_t *)icb; 4818 dptr2 = (uint8_t *)&nv->parameter_block_version; 4819 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 4820 while (cnt--) 4821 *dptr1++ = *dptr2++; 4822 4823 /* Copy 2nd half. */ 4824 dptr1 = (uint8_t *)icb->add_firmware_options; 4825 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 4826 while (cnt--) 4827 *dptr1++ = *dptr2++; 4828 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 4829 /* Use alternate WWN? */ 4830 if (nv->host_p[1] & BIT_7) { 4831 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 4832 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 4833 } 4834 4835 /* Prepare nodename */ 4836 if ((icb->firmware_options[1] & BIT_6) == 0) { 4837 /* 4838 * Firmware will apply the following mask if the nodename was 4839 * not provided. 4840 */ 4841 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 4842 icb->node_name[0] &= 0xF0; 4843 } 4844 4845 /* 4846 * Set host adapter parameters. 4847 */ 4848 4849 /* 4850 * BIT_7 in the host-parameters section allows for modification to 4851 * internal driver logging. 4852 */ 4853 if (nv->host_p[0] & BIT_7) 4854 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 4855 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 4856 /* Always load RISC code on non ISP2[12]00 chips. */ 4857 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 4858 ha->flags.disable_risc_code_load = 0; 4859 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 4860 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 4861 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 4862 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 4863 ha->flags.disable_serdes = 0; 4864 4865 ha->operating_mode = 4866 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 4867 4868 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 4869 sizeof(ha->fw_seriallink_options)); 4870 4871 /* save HBA serial number */ 4872 ha->serial0 = icb->port_name[5]; 4873 ha->serial1 = icb->port_name[6]; 4874 ha->serial2 = icb->port_name[7]; 4875 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 4876 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 4877 4878 icb->execution_throttle = cpu_to_le16(0xFFFF); 4879 4880 ha->retry_count = nv->retry_count; 4881 4882 /* Set minimum login_timeout to 4 seconds. */ 4883 if (nv->login_timeout != ql2xlogintimeout) 4884 nv->login_timeout = ql2xlogintimeout; 4885 if (nv->login_timeout < 4) 4886 nv->login_timeout = 4; 4887 ha->login_timeout = nv->login_timeout; 4888 4889 /* Set minimum RATOV to 100 tenths of a second. */ 4890 ha->r_a_tov = 100; 4891 4892 ha->loop_reset_delay = nv->reset_delay; 4893 4894 /* Link Down Timeout = 0: 4895 * 4896 * When Port Down timer expires we will start returning 4897 * I/O's to OS with "DID_NO_CONNECT". 4898 * 4899 * Link Down Timeout != 0: 4900 * 4901 * The driver waits for the link to come up after link down 4902 * before returning I/Os to OS with "DID_NO_CONNECT". 4903 */ 4904 if (nv->link_down_timeout == 0) { 4905 ha->loop_down_abort_time = 4906 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 4907 } else { 4908 ha->link_down_timeout = nv->link_down_timeout; 4909 ha->loop_down_abort_time = 4910 (LOOP_DOWN_TIME - ha->link_down_timeout); 4911 } 4912 4913 /* 4914 * Need enough time to try and get the port back. 4915 */ 4916 ha->port_down_retry_count = nv->port_down_retry_count; 4917 if (qlport_down_retry) 4918 ha->port_down_retry_count = qlport_down_retry; 4919 /* Set login_retry_count */ 4920 ha->login_retry_count = nv->retry_count; 4921 if (ha->port_down_retry_count == nv->port_down_retry_count && 4922 ha->port_down_retry_count > 3) 4923 ha->login_retry_count = ha->port_down_retry_count; 4924 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 4925 ha->login_retry_count = ha->port_down_retry_count; 4926 if (ql2xloginretrycount) 4927 ha->login_retry_count = ql2xloginretrycount; 4928 4929 icb->lun_enables = cpu_to_le16(0); 4930 icb->command_resource_count = 0; 4931 icb->immediate_notify_resource_count = 0; 4932 icb->timeout = cpu_to_le16(0); 4933 4934 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4935 /* Enable RIO */ 4936 icb->firmware_options[0] &= ~BIT_3; 4937 icb->add_firmware_options[0] &= 4938 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4939 icb->add_firmware_options[0] |= BIT_2; 4940 icb->response_accumulation_timer = 3; 4941 icb->interrupt_delay_timer = 5; 4942 4943 vha->flags.process_response_queue = 1; 4944 } else { 4945 /* Enable ZIO. */ 4946 if (!vha->flags.init_done) { 4947 ha->zio_mode = icb->add_firmware_options[0] & 4948 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4949 ha->zio_timer = icb->interrupt_delay_timer ? 4950 icb->interrupt_delay_timer : 2; 4951 } 4952 icb->add_firmware_options[0] &= 4953 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4954 vha->flags.process_response_queue = 0; 4955 if (ha->zio_mode != QLA_ZIO_DISABLED) { 4956 ha->zio_mode = QLA_ZIO_MODE_6; 4957 4958 ql_log(ql_log_info, vha, 0x0068, 4959 "ZIO mode %d enabled; timer delay (%d us).\n", 4960 ha->zio_mode, ha->zio_timer * 100); 4961 4962 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 4963 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 4964 vha->flags.process_response_queue = 1; 4965 } 4966 } 4967 4968 if (rval) { 4969 ql_log(ql_log_warn, vha, 0x0069, 4970 "NVRAM configuration failed.\n"); 4971 } 4972 return (rval); 4973 } 4974 4975 static void 4976 qla2x00_rport_del(void *data) 4977 { 4978 fc_port_t *fcport = data; 4979 struct fc_rport *rport; 4980 unsigned long flags; 4981 4982 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 4983 rport = fcport->drport ? fcport->drport : fcport->rport; 4984 fcport->drport = NULL; 4985 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 4986 if (rport) { 4987 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b, 4988 "%s %8phN. rport %p roles %x\n", 4989 __func__, fcport->port_name, rport, 4990 rport->roles); 4991 4992 fc_remote_port_delete(rport); 4993 } 4994 } 4995 4996 void qla2x00_set_fcport_state(fc_port_t *fcport, int state) 4997 { 4998 int old_state; 4999 5000 old_state = atomic_read(&fcport->state); 5001 atomic_set(&fcport->state, state); 5002 5003 /* Don't print state transitions during initial allocation of fcport */ 5004 if (old_state && old_state != state) { 5005 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d, 5006 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n", 5007 fcport->port_name, port_state_str[old_state], 5008 port_state_str[state], fcport->d_id.b.domain, 5009 fcport->d_id.b.area, fcport->d_id.b.al_pa); 5010 } 5011 } 5012 5013 /** 5014 * qla2x00_alloc_fcport() - Allocate a generic fcport. 5015 * @vha: HA context 5016 * @flags: allocation flags 5017 * 5018 * Returns a pointer to the allocated fcport, or NULL, if none available. 5019 */ 5020 fc_port_t * 5021 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 5022 { 5023 fc_port_t *fcport; 5024 5025 fcport = kzalloc(sizeof(fc_port_t), flags); 5026 if (!fcport) 5027 return NULL; 5028 5029 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 5030 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 5031 flags); 5032 if (!fcport->ct_desc.ct_sns) { 5033 ql_log(ql_log_warn, vha, 0xd049, 5034 "Failed to allocate ct_sns request.\n"); 5035 kfree(fcport); 5036 return NULL; 5037 } 5038 5039 /* Setup fcport template structure. */ 5040 fcport->vha = vha; 5041 fcport->port_type = FCT_UNKNOWN; 5042 fcport->loop_id = FC_NO_LOOP_ID; 5043 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 5044 fcport->supported_classes = FC_COS_UNSPECIFIED; 5045 fcport->fp_speed = PORT_SPEED_UNKNOWN; 5046 5047 fcport->disc_state = DSC_DELETED; 5048 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 5049 fcport->deleted = QLA_SESS_DELETED; 5050 fcport->login_retry = vha->hw->login_retry_count; 5051 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5052 fcport->logout_on_delete = 1; 5053 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5054 fcport->tgt_short_link_down_cnt = 0; 5055 fcport->dev_loss_tmo = 0; 5056 5057 if (!fcport->ct_desc.ct_sns) { 5058 ql_log(ql_log_warn, vha, 0xd049, 5059 "Failed to allocate ct_sns request.\n"); 5060 kfree(fcport); 5061 return NULL; 5062 } 5063 5064 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 5065 INIT_WORK(&fcport->free_work, qlt_free_session_done); 5066 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn); 5067 INIT_LIST_HEAD(&fcport->gnl_entry); 5068 INIT_LIST_HEAD(&fcport->list); 5069 5070 INIT_LIST_HEAD(&fcport->sess_cmd_list); 5071 spin_lock_init(&fcport->sess_cmd_lock); 5072 5073 return fcport; 5074 } 5075 5076 void 5077 qla2x00_free_fcport(fc_port_t *fcport) 5078 { 5079 if (fcport->ct_desc.ct_sns) { 5080 dma_free_coherent(&fcport->vha->hw->pdev->dev, 5081 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 5082 fcport->ct_desc.ct_sns_dma); 5083 5084 fcport->ct_desc.ct_sns = NULL; 5085 } 5086 list_del(&fcport->list); 5087 qla2x00_clear_loop_id(fcport); 5088 kfree(fcport); 5089 } 5090 5091 static void qla_get_login_template(scsi_qla_host_t *vha) 5092 { 5093 struct qla_hw_data *ha = vha->hw; 5094 int rval; 5095 u32 *bp, sz; 5096 __be32 *q; 5097 5098 memset(ha->init_cb, 0, ha->init_cb_size); 5099 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size); 5100 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma, 5101 ha->init_cb, sz); 5102 if (rval != QLA_SUCCESS) { 5103 ql_dbg(ql_dbg_init, vha, 0x00d1, 5104 "PLOGI ELS param read fail.\n"); 5105 return; 5106 } 5107 q = (__be32 *)&ha->plogi_els_payld.fl_csp; 5108 5109 bp = (uint32_t *)ha->init_cb; 5110 cpu_to_be32_array(q, bp, sz / 4); 5111 ha->flags.plogi_template_valid = 1; 5112 } 5113 5114 /* 5115 * qla2x00_configure_loop 5116 * Updates Fibre Channel Device Database with what is actually on loop. 5117 * 5118 * Input: 5119 * ha = adapter block pointer. 5120 * 5121 * Returns: 5122 * 0 = success. 5123 * 1 = error. 5124 * 2 = database was full and device was not configured. 5125 */ 5126 static int 5127 qla2x00_configure_loop(scsi_qla_host_t *vha) 5128 { 5129 int rval; 5130 unsigned long flags, save_flags; 5131 struct qla_hw_data *ha = vha->hw; 5132 5133 rval = QLA_SUCCESS; 5134 5135 /* Get Initiator ID */ 5136 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 5137 rval = qla2x00_configure_hba(vha); 5138 if (rval != QLA_SUCCESS) { 5139 ql_dbg(ql_dbg_disc, vha, 0x2013, 5140 "Unable to configure HBA.\n"); 5141 return (rval); 5142 } 5143 } 5144 5145 save_flags = flags = vha->dpc_flags; 5146 ql_dbg(ql_dbg_disc, vha, 0x2014, 5147 "Configure loop -- dpc flags = 0x%lx.\n", flags); 5148 5149 /* 5150 * If we have both an RSCN and PORT UPDATE pending then handle them 5151 * both at the same time. 5152 */ 5153 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5154 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 5155 5156 qla2x00_get_data_rate(vha); 5157 qla_get_login_template(vha); 5158 5159 /* Determine what we need to do */ 5160 if ((ha->current_topology == ISP_CFG_FL || 5161 ha->current_topology == ISP_CFG_F) && 5162 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 5163 5164 set_bit(RSCN_UPDATE, &flags); 5165 clear_bit(LOCAL_LOOP_UPDATE, &flags); 5166 5167 } else if (ha->current_topology == ISP_CFG_NL || 5168 ha->current_topology == ISP_CFG_N) { 5169 clear_bit(RSCN_UPDATE, &flags); 5170 set_bit(LOCAL_LOOP_UPDATE, &flags); 5171 } else if (!vha->flags.online || 5172 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 5173 set_bit(RSCN_UPDATE, &flags); 5174 set_bit(LOCAL_LOOP_UPDATE, &flags); 5175 } 5176 5177 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 5178 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5179 ql_dbg(ql_dbg_disc, vha, 0x2015, 5180 "Loop resync needed, failing.\n"); 5181 rval = QLA_FUNCTION_FAILED; 5182 } else 5183 rval = qla2x00_configure_local_loop(vha); 5184 } 5185 5186 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 5187 if (LOOP_TRANSITION(vha)) { 5188 ql_dbg(ql_dbg_disc, vha, 0x2099, 5189 "Needs RSCN update and loop transition.\n"); 5190 rval = QLA_FUNCTION_FAILED; 5191 } 5192 else 5193 rval = qla2x00_configure_fabric(vha); 5194 } 5195 5196 if (rval == QLA_SUCCESS) { 5197 if (atomic_read(&vha->loop_down_timer) || 5198 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5199 rval = QLA_FUNCTION_FAILED; 5200 } else { 5201 atomic_set(&vha->loop_state, LOOP_READY); 5202 ql_dbg(ql_dbg_disc, vha, 0x2069, 5203 "LOOP READY.\n"); 5204 ha->flags.fw_init_done = 1; 5205 5206 /* 5207 * Process any ATIO queue entries that came in 5208 * while we weren't online. 5209 */ 5210 if (qla_tgt_mode_enabled(vha) || 5211 qla_dual_mode_enabled(vha)) { 5212 spin_lock_irqsave(&ha->tgt.atio_lock, flags); 5213 qlt_24xx_process_atio_queue(vha, 0); 5214 spin_unlock_irqrestore(&ha->tgt.atio_lock, 5215 flags); 5216 } 5217 } 5218 } 5219 5220 if (rval) { 5221 ql_dbg(ql_dbg_disc, vha, 0x206a, 5222 "%s *** FAILED ***.\n", __func__); 5223 } else { 5224 ql_dbg(ql_dbg_disc, vha, 0x206b, 5225 "%s: exiting normally.\n", __func__); 5226 } 5227 5228 /* Restore state if a resync event occurred during processing */ 5229 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5230 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 5231 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5232 if (test_bit(RSCN_UPDATE, &save_flags)) { 5233 set_bit(RSCN_UPDATE, &vha->dpc_flags); 5234 } 5235 } 5236 5237 return (rval); 5238 } 5239 5240 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha) 5241 { 5242 unsigned long flags; 5243 fc_port_t *fcport; 5244 5245 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) 5246 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5247 5248 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5249 if (fcport->n2n_flag) { 5250 qla24xx_fcport_handle_login(vha, fcport); 5251 return QLA_SUCCESS; 5252 } 5253 } 5254 5255 spin_lock_irqsave(&vha->work_lock, flags); 5256 vha->scan.scan_retry++; 5257 spin_unlock_irqrestore(&vha->work_lock, flags); 5258 5259 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5260 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5261 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5262 } 5263 return QLA_FUNCTION_FAILED; 5264 } 5265 5266 /* 5267 * qla2x00_configure_local_loop 5268 * Updates Fibre Channel Device Database with local loop devices. 5269 * 5270 * Input: 5271 * ha = adapter block pointer. 5272 * 5273 * Returns: 5274 * 0 = success. 5275 */ 5276 static int 5277 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 5278 { 5279 int rval, rval2; 5280 int found_devs; 5281 int found; 5282 fc_port_t *fcport, *new_fcport; 5283 uint16_t index; 5284 uint16_t entries; 5285 struct gid_list_info *gid; 5286 uint16_t loop_id; 5287 uint8_t domain, area, al_pa; 5288 struct qla_hw_data *ha = vha->hw; 5289 unsigned long flags; 5290 5291 /* Inititae N2N login. */ 5292 if (N2N_TOPO(ha)) 5293 return qla2x00_configure_n2n_loop(vha); 5294 5295 found_devs = 0; 5296 new_fcport = NULL; 5297 entries = MAX_FIBRE_DEVICES_LOOP; 5298 5299 /* Get list of logged in devices. */ 5300 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 5301 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 5302 &entries); 5303 if (rval != QLA_SUCCESS) 5304 goto err; 5305 5306 ql_dbg(ql_dbg_disc, vha, 0x2011, 5307 "Entries in ID list (%d).\n", entries); 5308 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 5309 ha->gid_list, entries * sizeof(*ha->gid_list)); 5310 5311 if (entries == 0) { 5312 spin_lock_irqsave(&vha->work_lock, flags); 5313 vha->scan.scan_retry++; 5314 spin_unlock_irqrestore(&vha->work_lock, flags); 5315 5316 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5317 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5318 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5319 } 5320 } else { 5321 vha->scan.scan_retry = 0; 5322 } 5323 5324 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5325 fcport->scan_state = QLA_FCPORT_SCAN; 5326 } 5327 5328 /* Allocate temporary fcport for any new fcports discovered. */ 5329 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5330 if (new_fcport == NULL) { 5331 ql_log(ql_log_warn, vha, 0x2012, 5332 "Memory allocation failed for fcport.\n"); 5333 rval = QLA_MEMORY_ALLOC_FAILED; 5334 goto err; 5335 } 5336 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5337 5338 /* Add devices to port list. */ 5339 gid = ha->gid_list; 5340 for (index = 0; index < entries; index++) { 5341 domain = gid->domain; 5342 area = gid->area; 5343 al_pa = gid->al_pa; 5344 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 5345 loop_id = gid->loop_id_2100; 5346 else 5347 loop_id = le16_to_cpu(gid->loop_id); 5348 gid = (void *)gid + ha->gid_list_info_size; 5349 5350 /* Bypass reserved domain fields. */ 5351 if ((domain & 0xf0) == 0xf0) 5352 continue; 5353 5354 /* Bypass if not same domain and area of adapter. */ 5355 if (area && domain && ((area != vha->d_id.b.area) || 5356 (domain != vha->d_id.b.domain)) && 5357 (ha->current_topology == ISP_CFG_NL)) 5358 continue; 5359 5360 5361 /* Bypass invalid local loop ID. */ 5362 if (loop_id > LAST_LOCAL_LOOP_ID) 5363 continue; 5364 5365 memset(new_fcport->port_name, 0, WWN_SIZE); 5366 5367 /* Fill in member data. */ 5368 new_fcport->d_id.b.domain = domain; 5369 new_fcport->d_id.b.area = area; 5370 new_fcport->d_id.b.al_pa = al_pa; 5371 new_fcport->loop_id = loop_id; 5372 new_fcport->scan_state = QLA_FCPORT_FOUND; 5373 5374 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 5375 if (rval2 != QLA_SUCCESS) { 5376 ql_dbg(ql_dbg_disc, vha, 0x2097, 5377 "Failed to retrieve fcport information " 5378 "-- get_port_database=%x, loop_id=0x%04x.\n", 5379 rval2, new_fcport->loop_id); 5380 /* Skip retry if N2N */ 5381 if (ha->current_topology != ISP_CFG_N) { 5382 ql_dbg(ql_dbg_disc, vha, 0x2105, 5383 "Scheduling resync.\n"); 5384 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5385 continue; 5386 } 5387 } 5388 5389 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5390 /* Check for matching device in port list. */ 5391 found = 0; 5392 fcport = NULL; 5393 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5394 if (memcmp(new_fcport->port_name, fcport->port_name, 5395 WWN_SIZE)) 5396 continue; 5397 5398 fcport->flags &= ~FCF_FABRIC_DEVICE; 5399 fcport->loop_id = new_fcport->loop_id; 5400 fcport->port_type = new_fcport->port_type; 5401 fcport->d_id.b24 = new_fcport->d_id.b24; 5402 memcpy(fcport->node_name, new_fcport->node_name, 5403 WWN_SIZE); 5404 fcport->scan_state = QLA_FCPORT_FOUND; 5405 found++; 5406 break; 5407 } 5408 5409 if (!found) { 5410 /* New device, add to fcports list. */ 5411 list_add_tail(&new_fcport->list, &vha->vp_fcports); 5412 5413 /* Allocate a new replacement fcport. */ 5414 fcport = new_fcport; 5415 5416 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5417 5418 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5419 5420 if (new_fcport == NULL) { 5421 ql_log(ql_log_warn, vha, 0xd031, 5422 "Failed to allocate memory for fcport.\n"); 5423 rval = QLA_MEMORY_ALLOC_FAILED; 5424 goto err; 5425 } 5426 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5427 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5428 } 5429 5430 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5431 5432 /* Base iIDMA settings on HBA port speed. */ 5433 fcport->fp_speed = ha->link_data_rate; 5434 5435 found_devs++; 5436 } 5437 5438 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5439 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5440 break; 5441 5442 if (fcport->scan_state == QLA_FCPORT_SCAN) { 5443 if ((qla_dual_mode_enabled(vha) || 5444 qla_ini_mode_enabled(vha)) && 5445 atomic_read(&fcport->state) == FCS_ONLINE) { 5446 qla2x00_mark_device_lost(vha, fcport, 5447 ql2xplogiabsentdevice); 5448 if (fcport->loop_id != FC_NO_LOOP_ID && 5449 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 5450 fcport->port_type != FCT_INITIATOR && 5451 fcport->port_type != FCT_BROADCAST) { 5452 ql_dbg(ql_dbg_disc, vha, 0x20f0, 5453 "%s %d %8phC post del sess\n", 5454 __func__, __LINE__, 5455 fcport->port_name); 5456 5457 qlt_schedule_sess_for_deletion(fcport); 5458 continue; 5459 } 5460 } 5461 } 5462 5463 if (fcport->scan_state == QLA_FCPORT_FOUND) 5464 qla24xx_fcport_handle_login(vha, fcport); 5465 } 5466 5467 qla2x00_free_fcport(new_fcport); 5468 5469 return rval; 5470 5471 err: 5472 ql_dbg(ql_dbg_disc, vha, 0x2098, 5473 "Configure local loop error exit: rval=%x.\n", rval); 5474 return rval; 5475 } 5476 5477 static void 5478 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5479 { 5480 int rval; 5481 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5482 struct qla_hw_data *ha = vha->hw; 5483 5484 if (!IS_IIDMA_CAPABLE(ha)) 5485 return; 5486 5487 if (atomic_read(&fcport->state) != FCS_ONLINE) 5488 return; 5489 5490 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 5491 fcport->fp_speed > ha->link_data_rate || 5492 !ha->flags.gpsc_supported) 5493 return; 5494 5495 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 5496 mb); 5497 if (rval != QLA_SUCCESS) { 5498 ql_dbg(ql_dbg_disc, vha, 0x2004, 5499 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 5500 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 5501 } else { 5502 ql_dbg(ql_dbg_disc, vha, 0x2005, 5503 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n", 5504 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 5505 fcport->fp_speed, fcport->port_name); 5506 } 5507 } 5508 5509 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5510 { 5511 qla2x00_iidma_fcport(vha, fcport); 5512 qla24xx_update_fcport_fcp_prio(vha, fcport); 5513 } 5514 5515 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5516 { 5517 struct qla_work_evt *e; 5518 5519 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA); 5520 if (!e) 5521 return QLA_FUNCTION_FAILED; 5522 5523 e->u.fcport.fcport = fcport; 5524 return qla2x00_post_work(vha, e); 5525 } 5526 5527 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 5528 static void 5529 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 5530 { 5531 struct fc_rport_identifiers rport_ids; 5532 struct fc_rport *rport; 5533 unsigned long flags; 5534 5535 if (atomic_read(&fcport->state) == FCS_ONLINE) 5536 return; 5537 5538 rport_ids.node_name = wwn_to_u64(fcport->node_name); 5539 rport_ids.port_name = wwn_to_u64(fcport->port_name); 5540 rport_ids.port_id = fcport->d_id.b.domain << 16 | 5541 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 5542 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 5543 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 5544 if (!rport) { 5545 ql_log(ql_log_warn, vha, 0x2006, 5546 "Unable to allocate fc remote port.\n"); 5547 return; 5548 } 5549 5550 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 5551 *((fc_port_t **)rport->dd_data) = fcport; 5552 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 5553 fcport->dev_loss_tmo = rport->dev_loss_tmo; 5554 5555 rport->supported_classes = fcport->supported_classes; 5556 5557 rport_ids.roles = FC_PORT_ROLE_UNKNOWN; 5558 if (fcport->port_type == FCT_INITIATOR) 5559 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR; 5560 if (fcport->port_type == FCT_TARGET) 5561 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET; 5562 if (fcport->port_type & FCT_NVME_INITIATOR) 5563 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR; 5564 if (fcport->port_type & FCT_NVME_TARGET) 5565 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET; 5566 if (fcport->port_type & FCT_NVME_DISCOVERY) 5567 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY; 5568 5569 fc_remote_port_rolechg(rport, rport_ids.roles); 5570 5571 ql_dbg(ql_dbg_disc, vha, 0x20ee, 5572 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n", 5573 __func__, fcport->port_name, vha->host_no, 5574 rport->scsi_target_id, rport, 5575 (fcport->port_type == FCT_TARGET) ? "tgt" : 5576 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini")); 5577 } 5578 5579 /* 5580 * qla2x00_update_fcport 5581 * Updates device on list. 5582 * 5583 * Input: 5584 * ha = adapter block pointer. 5585 * fcport = port structure pointer. 5586 * 5587 * Return: 5588 * 0 - Success 5589 * BIT_0 - error 5590 * 5591 * Context: 5592 * Kernel context. 5593 */ 5594 void 5595 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5596 { 5597 if (IS_SW_RESV_ADDR(fcport->d_id)) 5598 return; 5599 5600 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n", 5601 __func__, fcport->port_name); 5602 5603 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5604 fcport->login_retry = vha->hw->login_retry_count; 5605 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 5606 fcport->deleted = 0; 5607 if (vha->hw->current_topology == ISP_CFG_NL) 5608 fcport->logout_on_delete = 0; 5609 else 5610 fcport->logout_on_delete = 1; 5611 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0; 5612 5613 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) { 5614 fcport->tgt_short_link_down_cnt++; 5615 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5616 } 5617 5618 switch (vha->hw->current_topology) { 5619 case ISP_CFG_N: 5620 case ISP_CFG_NL: 5621 fcport->keep_nport_handle = 1; 5622 break; 5623 default: 5624 break; 5625 } 5626 5627 qla2x00_iidma_fcport(vha, fcport); 5628 5629 qla2x00_dfs_create_rport(vha, fcport); 5630 5631 if (NVME_TARGET(vha->hw, fcport)) { 5632 qla_nvme_register_remote(vha, fcport); 5633 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5634 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5635 return; 5636 } 5637 5638 qla24xx_update_fcport_fcp_prio(vha, fcport); 5639 5640 switch (vha->host->active_mode) { 5641 case MODE_INITIATOR: 5642 qla2x00_reg_remote_port(vha, fcport); 5643 break; 5644 case MODE_TARGET: 5645 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5646 !vha->vha_tgt.qla_tgt->tgt_stopped) 5647 qlt_fc_port_added(vha, fcport); 5648 break; 5649 case MODE_DUAL: 5650 qla2x00_reg_remote_port(vha, fcport); 5651 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5652 !vha->vha_tgt.qla_tgt->tgt_stopped) 5653 qlt_fc_port_added(vha, fcport); 5654 break; 5655 default: 5656 break; 5657 } 5658 5659 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5660 5661 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) { 5662 if (fcport->id_changed) { 5663 fcport->id_changed = 0; 5664 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5665 "%s %d %8phC post gfpnid fcp_cnt %d\n", 5666 __func__, __LINE__, fcport->port_name, 5667 vha->fcport_count); 5668 qla24xx_post_gfpnid_work(vha, fcport); 5669 } else { 5670 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5671 "%s %d %8phC post gpsc fcp_cnt %d\n", 5672 __func__, __LINE__, fcport->port_name, 5673 vha->fcport_count); 5674 qla24xx_post_gpsc_work(vha, fcport); 5675 } 5676 } 5677 5678 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5679 } 5680 5681 void qla_register_fcport_fn(struct work_struct *work) 5682 { 5683 fc_port_t *fcport = container_of(work, struct fc_port, reg_work); 5684 u32 rscn_gen = fcport->rscn_gen; 5685 u16 data[2]; 5686 5687 if (IS_SW_RESV_ADDR(fcport->d_id)) 5688 return; 5689 5690 qla2x00_update_fcport(fcport->vha, fcport); 5691 5692 if (rscn_gen != fcport->rscn_gen) { 5693 /* RSCN(s) came in while registration */ 5694 switch (fcport->next_disc_state) { 5695 case DSC_DELETE_PEND: 5696 qlt_schedule_sess_for_deletion(fcport); 5697 break; 5698 case DSC_ADISC: 5699 data[0] = data[1] = 0; 5700 qla2x00_post_async_adisc_work(fcport->vha, fcport, 5701 data); 5702 break; 5703 default: 5704 break; 5705 } 5706 } 5707 } 5708 5709 /* 5710 * qla2x00_configure_fabric 5711 * Setup SNS devices with loop ID's. 5712 * 5713 * Input: 5714 * ha = adapter block pointer. 5715 * 5716 * Returns: 5717 * 0 = success. 5718 * BIT_0 = error 5719 */ 5720 static int 5721 qla2x00_configure_fabric(scsi_qla_host_t *vha) 5722 { 5723 int rval; 5724 fc_port_t *fcport; 5725 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5726 uint16_t loop_id; 5727 LIST_HEAD(new_fcports); 5728 struct qla_hw_data *ha = vha->hw; 5729 int discovery_gen; 5730 5731 /* If FL port exists, then SNS is present */ 5732 if (IS_FWI2_CAPABLE(ha)) 5733 loop_id = NPH_F_PORT; 5734 else 5735 loop_id = SNS_FL_PORT; 5736 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 5737 if (rval != QLA_SUCCESS) { 5738 ql_dbg(ql_dbg_disc, vha, 0x20a0, 5739 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 5740 5741 vha->device_flags &= ~SWITCH_FOUND; 5742 return (QLA_SUCCESS); 5743 } 5744 vha->device_flags |= SWITCH_FOUND; 5745 5746 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0); 5747 if (rval != QLA_SUCCESS) 5748 ql_dbg(ql_dbg_disc, vha, 0x20ff, 5749 "Failed to get Fabric Port Name\n"); 5750 5751 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 5752 rval = qla2x00_send_change_request(vha, 0x3, 0); 5753 if (rval != QLA_SUCCESS) 5754 ql_log(ql_log_warn, vha, 0x121, 5755 "Failed to enable receiving of RSCN requests: 0x%x.\n", 5756 rval); 5757 } 5758 5759 do { 5760 qla2x00_mgmt_svr_login(vha); 5761 5762 /* Ensure we are logged into the SNS. */ 5763 loop_id = NPH_SNS_LID(ha); 5764 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 5765 0xfc, mb, BIT_1|BIT_0); 5766 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 5767 ql_dbg(ql_dbg_disc, vha, 0x20a1, 5768 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n", 5769 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval); 5770 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5771 return rval; 5772 } 5773 5774 /* FDMI support. */ 5775 if (ql2xfdmienable && 5776 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 5777 qla2x00_fdmi_register(vha); 5778 5779 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 5780 if (qla2x00_rft_id(vha)) { 5781 /* EMPTY */ 5782 ql_dbg(ql_dbg_disc, vha, 0x20a2, 5783 "Register FC-4 TYPE failed.\n"); 5784 if (test_bit(LOOP_RESYNC_NEEDED, 5785 &vha->dpc_flags)) 5786 break; 5787 } 5788 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) { 5789 /* EMPTY */ 5790 ql_dbg(ql_dbg_disc, vha, 0x209a, 5791 "Register FC-4 Features failed.\n"); 5792 if (test_bit(LOOP_RESYNC_NEEDED, 5793 &vha->dpc_flags)) 5794 break; 5795 } 5796 if (vha->flags.nvme_enabled) { 5797 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) { 5798 ql_dbg(ql_dbg_disc, vha, 0x2049, 5799 "Register NVME FC Type Features failed.\n"); 5800 } 5801 } 5802 if (qla2x00_rnn_id(vha)) { 5803 /* EMPTY */ 5804 ql_dbg(ql_dbg_disc, vha, 0x2104, 5805 "Register Node Name failed.\n"); 5806 if (test_bit(LOOP_RESYNC_NEEDED, 5807 &vha->dpc_flags)) 5808 break; 5809 } else if (qla2x00_rsnn_nn(vha)) { 5810 /* EMPTY */ 5811 ql_dbg(ql_dbg_disc, vha, 0x209b, 5812 "Register Symbolic Node Name failed.\n"); 5813 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5814 break; 5815 } 5816 } 5817 5818 5819 /* Mark the time right before querying FW for connected ports. 5820 * This process is long, asynchronous and by the time it's done, 5821 * collected information might not be accurate anymore. E.g. 5822 * disconnected port might have re-connected and a brand new 5823 * session has been created. In this case session's generation 5824 * will be newer than discovery_gen. */ 5825 qlt_do_generation_tick(vha, &discovery_gen); 5826 5827 if (USE_ASYNC_SCAN(ha)) { 5828 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI, 5829 NULL); 5830 if (rval) 5831 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5832 } else { 5833 list_for_each_entry(fcport, &vha->vp_fcports, list) 5834 fcport->scan_state = QLA_FCPORT_SCAN; 5835 5836 rval = qla2x00_find_all_fabric_devs(vha); 5837 } 5838 if (rval != QLA_SUCCESS) 5839 break; 5840 } while (0); 5841 5842 if (!vha->nvme_local_port && vha->flags.nvme_enabled) 5843 qla_nvme_register_hba(vha); 5844 5845 if (rval) 5846 ql_dbg(ql_dbg_disc, vha, 0x2068, 5847 "Configure fabric error exit rval=%d.\n", rval); 5848 5849 return (rval); 5850 } 5851 5852 /* 5853 * qla2x00_find_all_fabric_devs 5854 * 5855 * Input: 5856 * ha = adapter block pointer. 5857 * dev = database device entry pointer. 5858 * 5859 * Returns: 5860 * 0 = success. 5861 * 5862 * Context: 5863 * Kernel context. 5864 */ 5865 static int 5866 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 5867 { 5868 int rval; 5869 uint16_t loop_id; 5870 fc_port_t *fcport, *new_fcport; 5871 int found; 5872 5873 sw_info_t *swl; 5874 int swl_idx; 5875 int first_dev, last_dev; 5876 port_id_t wrap = {}, nxt_d_id; 5877 struct qla_hw_data *ha = vha->hw; 5878 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5879 unsigned long flags; 5880 5881 rval = QLA_SUCCESS; 5882 5883 /* Try GID_PT to get device list, else GAN. */ 5884 if (!ha->swl) 5885 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 5886 GFP_KERNEL); 5887 swl = ha->swl; 5888 if (!swl) { 5889 /*EMPTY*/ 5890 ql_dbg(ql_dbg_disc, vha, 0x209c, 5891 "GID_PT allocations failed, fallback on GA_NXT.\n"); 5892 } else { 5893 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 5894 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 5895 swl = NULL; 5896 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5897 return rval; 5898 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 5899 swl = NULL; 5900 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5901 return rval; 5902 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 5903 swl = NULL; 5904 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5905 return rval; 5906 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 5907 swl = NULL; 5908 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5909 return rval; 5910 } 5911 5912 /* If other queries succeeded probe for FC-4 type */ 5913 if (swl) { 5914 qla2x00_gff_id(vha, swl); 5915 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5916 return rval; 5917 } 5918 } 5919 swl_idx = 0; 5920 5921 /* Allocate temporary fcport for any new fcports discovered. */ 5922 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5923 if (new_fcport == NULL) { 5924 ql_log(ql_log_warn, vha, 0x209d, 5925 "Failed to allocate memory for fcport.\n"); 5926 return (QLA_MEMORY_ALLOC_FAILED); 5927 } 5928 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 5929 /* Set start port ID scan at adapter ID. */ 5930 first_dev = 1; 5931 last_dev = 0; 5932 5933 /* Starting free loop ID. */ 5934 loop_id = ha->min_external_loopid; 5935 for (; loop_id <= ha->max_loop_id; loop_id++) { 5936 if (qla2x00_is_reserved_id(vha, loop_id)) 5937 continue; 5938 5939 if (ha->current_topology == ISP_CFG_FL && 5940 (atomic_read(&vha->loop_down_timer) || 5941 LOOP_TRANSITION(vha))) { 5942 atomic_set(&vha->loop_down_timer, 0); 5943 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5944 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5945 break; 5946 } 5947 5948 if (swl != NULL) { 5949 if (last_dev) { 5950 wrap.b24 = new_fcport->d_id.b24; 5951 } else { 5952 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 5953 memcpy(new_fcport->node_name, 5954 swl[swl_idx].node_name, WWN_SIZE); 5955 memcpy(new_fcport->port_name, 5956 swl[swl_idx].port_name, WWN_SIZE); 5957 memcpy(new_fcport->fabric_port_name, 5958 swl[swl_idx].fabric_port_name, WWN_SIZE); 5959 new_fcport->fp_speed = swl[swl_idx].fp_speed; 5960 new_fcport->fc4_type = swl[swl_idx].fc4_type; 5961 5962 new_fcport->nvme_flag = 0; 5963 if (vha->flags.nvme_enabled && 5964 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) { 5965 ql_log(ql_log_info, vha, 0x2131, 5966 "FOUND: NVME port %8phC as FC Type 28h\n", 5967 new_fcport->port_name); 5968 } 5969 5970 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 5971 last_dev = 1; 5972 } 5973 swl_idx++; 5974 } 5975 } else { 5976 /* Send GA_NXT to the switch */ 5977 rval = qla2x00_ga_nxt(vha, new_fcport); 5978 if (rval != QLA_SUCCESS) { 5979 ql_log(ql_log_warn, vha, 0x209e, 5980 "SNS scan failed -- assuming " 5981 "zero-entry result.\n"); 5982 rval = QLA_SUCCESS; 5983 break; 5984 } 5985 } 5986 5987 /* If wrap on switch device list, exit. */ 5988 if (first_dev) { 5989 wrap.b24 = new_fcport->d_id.b24; 5990 first_dev = 0; 5991 } else if (new_fcport->d_id.b24 == wrap.b24) { 5992 ql_dbg(ql_dbg_disc, vha, 0x209f, 5993 "Device wrap (%02x%02x%02x).\n", 5994 new_fcport->d_id.b.domain, 5995 new_fcport->d_id.b.area, 5996 new_fcport->d_id.b.al_pa); 5997 break; 5998 } 5999 6000 /* Bypass if same physical adapter. */ 6001 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 6002 continue; 6003 6004 /* Bypass virtual ports of the same host. */ 6005 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 6006 continue; 6007 6008 /* Bypass if same domain and area of adapter. */ 6009 if (((new_fcport->d_id.b24 & 0xffff00) == 6010 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 6011 ISP_CFG_FL) 6012 continue; 6013 6014 /* Bypass reserved domain fields. */ 6015 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 6016 continue; 6017 6018 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 6019 if (ql2xgffidenable && 6020 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) && 6021 new_fcport->fc4_type != 0)) 6022 continue; 6023 6024 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6025 6026 /* Locate matching device in database. */ 6027 found = 0; 6028 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6029 if (memcmp(new_fcport->port_name, fcport->port_name, 6030 WWN_SIZE)) 6031 continue; 6032 6033 fcport->scan_state = QLA_FCPORT_FOUND; 6034 6035 found++; 6036 6037 /* Update port state. */ 6038 memcpy(fcport->fabric_port_name, 6039 new_fcport->fabric_port_name, WWN_SIZE); 6040 fcport->fp_speed = new_fcport->fp_speed; 6041 6042 /* 6043 * If address the same and state FCS_ONLINE 6044 * (or in target mode), nothing changed. 6045 */ 6046 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 6047 (atomic_read(&fcport->state) == FCS_ONLINE || 6048 (vha->host->active_mode == MODE_TARGET))) { 6049 break; 6050 } 6051 6052 if (fcport->login_retry == 0) 6053 fcport->login_retry = 6054 vha->hw->login_retry_count; 6055 /* 6056 * If device was not a fabric device before. 6057 */ 6058 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 6059 fcport->d_id.b24 = new_fcport->d_id.b24; 6060 qla2x00_clear_loop_id(fcport); 6061 fcport->flags |= (FCF_FABRIC_DEVICE | 6062 FCF_LOGIN_NEEDED); 6063 break; 6064 } 6065 6066 /* 6067 * Port ID changed or device was marked to be updated; 6068 * Log it out if still logged in and mark it for 6069 * relogin later. 6070 */ 6071 if (qla_tgt_mode_enabled(base_vha)) { 6072 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 6073 "port changed FC ID, %8phC" 6074 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 6075 fcport->port_name, 6076 fcport->d_id.b.domain, 6077 fcport->d_id.b.area, 6078 fcport->d_id.b.al_pa, 6079 fcport->loop_id, 6080 new_fcport->d_id.b.domain, 6081 new_fcport->d_id.b.area, 6082 new_fcport->d_id.b.al_pa); 6083 fcport->d_id.b24 = new_fcport->d_id.b24; 6084 break; 6085 } 6086 6087 fcport->d_id.b24 = new_fcport->d_id.b24; 6088 fcport->flags |= FCF_LOGIN_NEEDED; 6089 break; 6090 } 6091 6092 if (found && NVME_TARGET(vha->hw, fcport)) { 6093 if (fcport->disc_state == DSC_DELETE_PEND) { 6094 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 6095 vha->fcport_count--; 6096 fcport->login_succ = 0; 6097 } 6098 } 6099 6100 if (found) { 6101 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6102 continue; 6103 } 6104 /* If device was not in our fcports list, then add it. */ 6105 new_fcport->scan_state = QLA_FCPORT_FOUND; 6106 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6107 6108 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6109 6110 6111 /* Allocate a new replacement fcport. */ 6112 nxt_d_id.b24 = new_fcport->d_id.b24; 6113 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6114 if (new_fcport == NULL) { 6115 ql_log(ql_log_warn, vha, 0xd032, 6116 "Memory allocation failed for fcport.\n"); 6117 return (QLA_MEMORY_ALLOC_FAILED); 6118 } 6119 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6120 new_fcport->d_id.b24 = nxt_d_id.b24; 6121 } 6122 6123 qla2x00_free_fcport(new_fcport); 6124 6125 /* 6126 * Logout all previous fabric dev marked lost, except FCP2 devices. 6127 */ 6128 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6129 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6130 break; 6131 6132 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 6133 continue; 6134 6135 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6136 if ((qla_dual_mode_enabled(vha) || 6137 qla_ini_mode_enabled(vha)) && 6138 atomic_read(&fcport->state) == FCS_ONLINE) { 6139 qla2x00_mark_device_lost(vha, fcport, 6140 ql2xplogiabsentdevice); 6141 if (fcport->loop_id != FC_NO_LOOP_ID && 6142 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6143 fcport->port_type != FCT_INITIATOR && 6144 fcport->port_type != FCT_BROADCAST) { 6145 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6146 "%s %d %8phC post del sess\n", 6147 __func__, __LINE__, 6148 fcport->port_name); 6149 qlt_schedule_sess_for_deletion(fcport); 6150 continue; 6151 } 6152 } 6153 } 6154 6155 if (fcport->scan_state == QLA_FCPORT_FOUND && 6156 (fcport->flags & FCF_LOGIN_NEEDED) != 0) 6157 qla24xx_fcport_handle_login(vha, fcport); 6158 } 6159 return (rval); 6160 } 6161 6162 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */ 6163 int 6164 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha) 6165 { 6166 int loop_id = FC_NO_LOOP_ID; 6167 int lid = NPH_MGMT_SERVER - vha->vp_idx; 6168 unsigned long flags; 6169 struct qla_hw_data *ha = vha->hw; 6170 6171 if (vha->vp_idx == 0) { 6172 set_bit(NPH_MGMT_SERVER, ha->loop_id_map); 6173 return NPH_MGMT_SERVER; 6174 } 6175 6176 /* pick id from high and work down to low */ 6177 spin_lock_irqsave(&ha->vport_slock, flags); 6178 for (; lid > 0; lid--) { 6179 if (!test_bit(lid, vha->hw->loop_id_map)) { 6180 set_bit(lid, vha->hw->loop_id_map); 6181 loop_id = lid; 6182 break; 6183 } 6184 } 6185 spin_unlock_irqrestore(&ha->vport_slock, flags); 6186 6187 return loop_id; 6188 } 6189 6190 /* 6191 * qla2x00_fabric_login 6192 * Issue fabric login command. 6193 * 6194 * Input: 6195 * ha = adapter block pointer. 6196 * device = pointer to FC device type structure. 6197 * 6198 * Returns: 6199 * 0 - Login successfully 6200 * 1 - Login failed 6201 * 2 - Initiator device 6202 * 3 - Fatal error 6203 */ 6204 int 6205 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 6206 uint16_t *next_loopid) 6207 { 6208 int rval; 6209 int retry; 6210 uint16_t tmp_loopid; 6211 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6212 struct qla_hw_data *ha = vha->hw; 6213 6214 retry = 0; 6215 tmp_loopid = 0; 6216 6217 for (;;) { 6218 ql_dbg(ql_dbg_disc, vha, 0x2000, 6219 "Trying Fabric Login w/loop id 0x%04x for port " 6220 "%02x%02x%02x.\n", 6221 fcport->loop_id, fcport->d_id.b.domain, 6222 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6223 6224 /* Login fcport on switch. */ 6225 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 6226 fcport->d_id.b.domain, fcport->d_id.b.area, 6227 fcport->d_id.b.al_pa, mb, BIT_0); 6228 if (rval != QLA_SUCCESS) { 6229 return rval; 6230 } 6231 if (mb[0] == MBS_PORT_ID_USED) { 6232 /* 6233 * Device has another loop ID. The firmware team 6234 * recommends the driver perform an implicit login with 6235 * the specified ID again. The ID we just used is save 6236 * here so we return with an ID that can be tried by 6237 * the next login. 6238 */ 6239 retry++; 6240 tmp_loopid = fcport->loop_id; 6241 fcport->loop_id = mb[1]; 6242 6243 ql_dbg(ql_dbg_disc, vha, 0x2001, 6244 "Fabric Login: port in use - next loop " 6245 "id=0x%04x, port id= %02x%02x%02x.\n", 6246 fcport->loop_id, fcport->d_id.b.domain, 6247 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6248 6249 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 6250 /* 6251 * Login succeeded. 6252 */ 6253 if (retry) { 6254 /* A retry occurred before. */ 6255 *next_loopid = tmp_loopid; 6256 } else { 6257 /* 6258 * No retry occurred before. Just increment the 6259 * ID value for next login. 6260 */ 6261 *next_loopid = (fcport->loop_id + 1); 6262 } 6263 6264 if (mb[1] & BIT_0) { 6265 fcport->port_type = FCT_INITIATOR; 6266 } else { 6267 fcport->port_type = FCT_TARGET; 6268 if (mb[1] & BIT_1) { 6269 fcport->flags |= FCF_FCP2_DEVICE; 6270 } 6271 } 6272 6273 if (mb[10] & BIT_0) 6274 fcport->supported_classes |= FC_COS_CLASS2; 6275 if (mb[10] & BIT_1) 6276 fcport->supported_classes |= FC_COS_CLASS3; 6277 6278 if (IS_FWI2_CAPABLE(ha)) { 6279 if (mb[10] & BIT_7) 6280 fcport->flags |= 6281 FCF_CONF_COMP_SUPPORTED; 6282 } 6283 6284 rval = QLA_SUCCESS; 6285 break; 6286 } else if (mb[0] == MBS_LOOP_ID_USED) { 6287 /* 6288 * Loop ID already used, try next loop ID. 6289 */ 6290 fcport->loop_id++; 6291 rval = qla2x00_find_new_loop_id(vha, fcport); 6292 if (rval != QLA_SUCCESS) { 6293 /* Ran out of loop IDs to use */ 6294 break; 6295 } 6296 } else if (mb[0] == MBS_COMMAND_ERROR) { 6297 /* 6298 * Firmware possibly timed out during login. If NO 6299 * retries are left to do then the device is declared 6300 * dead. 6301 */ 6302 *next_loopid = fcport->loop_id; 6303 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6304 fcport->d_id.b.domain, fcport->d_id.b.area, 6305 fcport->d_id.b.al_pa); 6306 qla2x00_mark_device_lost(vha, fcport, 1); 6307 6308 rval = 1; 6309 break; 6310 } else { 6311 /* 6312 * unrecoverable / not handled error 6313 */ 6314 ql_dbg(ql_dbg_disc, vha, 0x2002, 6315 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 6316 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 6317 fcport->d_id.b.area, fcport->d_id.b.al_pa, 6318 fcport->loop_id, jiffies); 6319 6320 *next_loopid = fcport->loop_id; 6321 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6322 fcport->d_id.b.domain, fcport->d_id.b.area, 6323 fcport->d_id.b.al_pa); 6324 qla2x00_clear_loop_id(fcport); 6325 fcport->login_retry = 0; 6326 6327 rval = 3; 6328 break; 6329 } 6330 } 6331 6332 return (rval); 6333 } 6334 6335 /* 6336 * qla2x00_local_device_login 6337 * Issue local device login command. 6338 * 6339 * Input: 6340 * ha = adapter block pointer. 6341 * loop_id = loop id of device to login to. 6342 * 6343 * Returns (Where's the #define!!!!): 6344 * 0 - Login successfully 6345 * 1 - Login failed 6346 * 3 - Fatal error 6347 */ 6348 int 6349 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 6350 { 6351 int rval; 6352 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6353 6354 memset(mb, 0, sizeof(mb)); 6355 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 6356 if (rval == QLA_SUCCESS) { 6357 /* Interrogate mailbox registers for any errors */ 6358 if (mb[0] == MBS_COMMAND_ERROR) 6359 rval = 1; 6360 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 6361 /* device not in PCB table */ 6362 rval = 3; 6363 } 6364 6365 return (rval); 6366 } 6367 6368 /* 6369 * qla2x00_loop_resync 6370 * Resync with fibre channel devices. 6371 * 6372 * Input: 6373 * ha = adapter block pointer. 6374 * 6375 * Returns: 6376 * 0 = success 6377 */ 6378 int 6379 qla2x00_loop_resync(scsi_qla_host_t *vha) 6380 { 6381 int rval = QLA_SUCCESS; 6382 uint32_t wait_time; 6383 6384 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6385 if (vha->flags.online) { 6386 if (!(rval = qla2x00_fw_ready(vha))) { 6387 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 6388 wait_time = 256; 6389 do { 6390 if (!IS_QLAFX00(vha->hw)) { 6391 /* 6392 * Issue a marker after FW becomes 6393 * ready. 6394 */ 6395 qla2x00_marker(vha, vha->hw->base_qpair, 6396 0, 0, MK_SYNC_ALL); 6397 vha->marker_needed = 0; 6398 } 6399 6400 /* Remap devices on Loop. */ 6401 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6402 6403 if (IS_QLAFX00(vha->hw)) 6404 qlafx00_configure_devices(vha); 6405 else 6406 qla2x00_configure_loop(vha); 6407 6408 wait_time--; 6409 } while (!atomic_read(&vha->loop_down_timer) && 6410 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6411 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 6412 &vha->dpc_flags))); 6413 } 6414 } 6415 6416 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6417 return (QLA_FUNCTION_FAILED); 6418 6419 if (rval) 6420 ql_dbg(ql_dbg_disc, vha, 0x206c, 6421 "%s *** FAILED ***.\n", __func__); 6422 6423 return (rval); 6424 } 6425 6426 /* 6427 * qla2x00_perform_loop_resync 6428 * Description: This function will set the appropriate flags and call 6429 * qla2x00_loop_resync. If successful loop will be resynced 6430 * Arguments : scsi_qla_host_t pointer 6431 * returm : Success or Failure 6432 */ 6433 6434 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 6435 { 6436 int32_t rval = 0; 6437 6438 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 6439 /*Configure the flags so that resync happens properly*/ 6440 atomic_set(&ha->loop_down_timer, 0); 6441 if (!(ha->device_flags & DFLG_NO_CABLE)) { 6442 atomic_set(&ha->loop_state, LOOP_UP); 6443 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 6444 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 6445 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 6446 6447 rval = qla2x00_loop_resync(ha); 6448 } else 6449 atomic_set(&ha->loop_state, LOOP_DEAD); 6450 6451 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 6452 } 6453 6454 return rval; 6455 } 6456 6457 void 6458 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 6459 { 6460 fc_port_t *fcport; 6461 struct scsi_qla_host *vha; 6462 struct qla_hw_data *ha = base_vha->hw; 6463 unsigned long flags; 6464 6465 spin_lock_irqsave(&ha->vport_slock, flags); 6466 /* Go with deferred removal of rport references. */ 6467 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 6468 atomic_inc(&vha->vref_count); 6469 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6470 if (fcport->drport && 6471 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 6472 spin_unlock_irqrestore(&ha->vport_slock, flags); 6473 qla2x00_rport_del(fcport); 6474 6475 spin_lock_irqsave(&ha->vport_slock, flags); 6476 } 6477 } 6478 atomic_dec(&vha->vref_count); 6479 wake_up(&vha->vref_waitq); 6480 } 6481 spin_unlock_irqrestore(&ha->vport_slock, flags); 6482 } 6483 6484 /* Assumes idc_lock always held on entry */ 6485 void 6486 qla83xx_reset_ownership(scsi_qla_host_t *vha) 6487 { 6488 struct qla_hw_data *ha = vha->hw; 6489 uint32_t drv_presence, drv_presence_mask; 6490 uint32_t dev_part_info1, dev_part_info2, class_type; 6491 uint32_t class_type_mask = 0x3; 6492 uint16_t fcoe_other_function = 0xffff, i; 6493 6494 if (IS_QLA8044(ha)) { 6495 drv_presence = qla8044_rd_direct(vha, 6496 QLA8044_CRB_DRV_ACTIVE_INDEX); 6497 dev_part_info1 = qla8044_rd_direct(vha, 6498 QLA8044_CRB_DEV_PART_INFO_INDEX); 6499 dev_part_info2 = qla8044_rd_direct(vha, 6500 QLA8044_CRB_DEV_PART_INFO2); 6501 } else { 6502 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6503 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 6504 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 6505 } 6506 for (i = 0; i < 8; i++) { 6507 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 6508 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6509 (i != ha->portnum)) { 6510 fcoe_other_function = i; 6511 break; 6512 } 6513 } 6514 if (fcoe_other_function == 0xffff) { 6515 for (i = 0; i < 8; i++) { 6516 class_type = ((dev_part_info2 >> (i * 4)) & 6517 class_type_mask); 6518 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6519 ((i + 8) != ha->portnum)) { 6520 fcoe_other_function = i + 8; 6521 break; 6522 } 6523 } 6524 } 6525 /* 6526 * Prepare drv-presence mask based on fcoe functions present. 6527 * However consider only valid physical fcoe function numbers (0-15). 6528 */ 6529 drv_presence_mask = ~((1 << (ha->portnum)) | 6530 ((fcoe_other_function == 0xffff) ? 6531 0 : (1 << (fcoe_other_function)))); 6532 6533 /* We are the reset owner iff: 6534 * - No other protocol drivers present. 6535 * - This is the lowest among fcoe functions. */ 6536 if (!(drv_presence & drv_presence_mask) && 6537 (ha->portnum < fcoe_other_function)) { 6538 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 6539 "This host is Reset owner.\n"); 6540 ha->flags.nic_core_reset_owner = 1; 6541 } 6542 } 6543 6544 static int 6545 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 6546 { 6547 int rval = QLA_SUCCESS; 6548 struct qla_hw_data *ha = vha->hw; 6549 uint32_t drv_ack; 6550 6551 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6552 if (rval == QLA_SUCCESS) { 6553 drv_ack |= (1 << ha->portnum); 6554 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6555 } 6556 6557 return rval; 6558 } 6559 6560 static int 6561 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 6562 { 6563 int rval = QLA_SUCCESS; 6564 struct qla_hw_data *ha = vha->hw; 6565 uint32_t drv_ack; 6566 6567 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6568 if (rval == QLA_SUCCESS) { 6569 drv_ack &= ~(1 << ha->portnum); 6570 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6571 } 6572 6573 return rval; 6574 } 6575 6576 static const char * 6577 qla83xx_dev_state_to_string(uint32_t dev_state) 6578 { 6579 switch (dev_state) { 6580 case QLA8XXX_DEV_COLD: 6581 return "COLD/RE-INIT"; 6582 case QLA8XXX_DEV_INITIALIZING: 6583 return "INITIALIZING"; 6584 case QLA8XXX_DEV_READY: 6585 return "READY"; 6586 case QLA8XXX_DEV_NEED_RESET: 6587 return "NEED RESET"; 6588 case QLA8XXX_DEV_NEED_QUIESCENT: 6589 return "NEED QUIESCENT"; 6590 case QLA8XXX_DEV_FAILED: 6591 return "FAILED"; 6592 case QLA8XXX_DEV_QUIESCENT: 6593 return "QUIESCENT"; 6594 default: 6595 return "Unknown"; 6596 } 6597 } 6598 6599 /* Assumes idc-lock always held on entry */ 6600 void 6601 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 6602 { 6603 struct qla_hw_data *ha = vha->hw; 6604 uint32_t idc_audit_reg = 0, duration_secs = 0; 6605 6606 switch (audit_type) { 6607 case IDC_AUDIT_TIMESTAMP: 6608 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 6609 idc_audit_reg = (ha->portnum) | 6610 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 6611 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6612 break; 6613 6614 case IDC_AUDIT_COMPLETION: 6615 duration_secs = ((jiffies_to_msecs(jiffies) - 6616 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 6617 idc_audit_reg = (ha->portnum) | 6618 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 6619 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6620 break; 6621 6622 default: 6623 ql_log(ql_log_warn, vha, 0xb078, 6624 "Invalid audit type specified.\n"); 6625 break; 6626 } 6627 } 6628 6629 /* Assumes idc_lock always held on entry */ 6630 static int 6631 qla83xx_initiating_reset(scsi_qla_host_t *vha) 6632 { 6633 struct qla_hw_data *ha = vha->hw; 6634 uint32_t idc_control, dev_state; 6635 6636 __qla83xx_get_idc_control(vha, &idc_control); 6637 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 6638 ql_log(ql_log_info, vha, 0xb080, 6639 "NIC Core reset has been disabled. idc-control=0x%x\n", 6640 idc_control); 6641 return QLA_FUNCTION_FAILED; 6642 } 6643 6644 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 6645 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6646 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 6647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 6648 QLA8XXX_DEV_NEED_RESET); 6649 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 6650 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 6651 } else { 6652 const char *state = qla83xx_dev_state_to_string(dev_state); 6653 6654 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 6655 6656 /* SV: XXX: Is timeout required here? */ 6657 /* Wait for IDC state change READY -> NEED_RESET */ 6658 while (dev_state == QLA8XXX_DEV_READY) { 6659 qla83xx_idc_unlock(vha, 0); 6660 msleep(200); 6661 qla83xx_idc_lock(vha, 0); 6662 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6663 } 6664 } 6665 6666 /* Send IDC ack by writing to drv-ack register */ 6667 __qla83xx_set_drv_ack(vha); 6668 6669 return QLA_SUCCESS; 6670 } 6671 6672 int 6673 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 6674 { 6675 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6676 } 6677 6678 int 6679 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 6680 { 6681 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6682 } 6683 6684 static int 6685 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 6686 { 6687 uint32_t drv_presence = 0; 6688 struct qla_hw_data *ha = vha->hw; 6689 6690 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6691 if (drv_presence & (1 << ha->portnum)) 6692 return QLA_SUCCESS; 6693 else 6694 return QLA_TEST_FAILED; 6695 } 6696 6697 int 6698 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 6699 { 6700 int rval = QLA_SUCCESS; 6701 struct qla_hw_data *ha = vha->hw; 6702 6703 ql_dbg(ql_dbg_p3p, vha, 0xb058, 6704 "Entered %s().\n", __func__); 6705 6706 if (vha->device_flags & DFLG_DEV_FAILED) { 6707 ql_log(ql_log_warn, vha, 0xb059, 6708 "Device in unrecoverable FAILED state.\n"); 6709 return QLA_FUNCTION_FAILED; 6710 } 6711 6712 qla83xx_idc_lock(vha, 0); 6713 6714 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 6715 ql_log(ql_log_warn, vha, 0xb05a, 6716 "Function=0x%x has been removed from IDC participation.\n", 6717 ha->portnum); 6718 rval = QLA_FUNCTION_FAILED; 6719 goto exit; 6720 } 6721 6722 qla83xx_reset_ownership(vha); 6723 6724 rval = qla83xx_initiating_reset(vha); 6725 6726 /* 6727 * Perform reset if we are the reset-owner, 6728 * else wait till IDC state changes to READY/FAILED. 6729 */ 6730 if (rval == QLA_SUCCESS) { 6731 rval = qla83xx_idc_state_handler(vha); 6732 6733 if (rval == QLA_SUCCESS) 6734 ha->flags.nic_core_hung = 0; 6735 __qla83xx_clear_drv_ack(vha); 6736 } 6737 6738 exit: 6739 qla83xx_idc_unlock(vha, 0); 6740 6741 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 6742 6743 return rval; 6744 } 6745 6746 int 6747 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 6748 { 6749 struct qla_hw_data *ha = vha->hw; 6750 int rval = QLA_FUNCTION_FAILED; 6751 6752 if (!IS_MCTP_CAPABLE(ha)) { 6753 /* This message can be removed from the final version */ 6754 ql_log(ql_log_info, vha, 0x506d, 6755 "This board is not MCTP capable\n"); 6756 return rval; 6757 } 6758 6759 if (!ha->mctp_dump) { 6760 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 6761 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 6762 6763 if (!ha->mctp_dump) { 6764 ql_log(ql_log_warn, vha, 0x506e, 6765 "Failed to allocate memory for mctp dump\n"); 6766 return rval; 6767 } 6768 } 6769 6770 #define MCTP_DUMP_STR_ADDR 0x00000000 6771 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 6772 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 6773 if (rval != QLA_SUCCESS) { 6774 ql_log(ql_log_warn, vha, 0x506f, 6775 "Failed to capture mctp dump\n"); 6776 } else { 6777 ql_log(ql_log_info, vha, 0x5070, 6778 "Mctp dump capture for host (%ld/%p).\n", 6779 vha->host_no, ha->mctp_dump); 6780 ha->mctp_dumped = 1; 6781 } 6782 6783 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 6784 ha->flags.nic_core_reset_hdlr_active = 1; 6785 rval = qla83xx_restart_nic_firmware(vha); 6786 if (rval) 6787 /* NIC Core reset failed. */ 6788 ql_log(ql_log_warn, vha, 0x5071, 6789 "Failed to restart nic firmware\n"); 6790 else 6791 ql_dbg(ql_dbg_p3p, vha, 0xb084, 6792 "Restarted NIC firmware successfully.\n"); 6793 ha->flags.nic_core_reset_hdlr_active = 0; 6794 } 6795 6796 return rval; 6797 6798 } 6799 6800 /* 6801 * qla2x00_quiesce_io 6802 * Description: This function will block the new I/Os 6803 * Its not aborting any I/Os as context 6804 * is not destroyed during quiescence 6805 * Arguments: scsi_qla_host_t 6806 * return : void 6807 */ 6808 void 6809 qla2x00_quiesce_io(scsi_qla_host_t *vha) 6810 { 6811 struct qla_hw_data *ha = vha->hw; 6812 struct scsi_qla_host *vp; 6813 6814 ql_dbg(ql_dbg_dpc, vha, 0x401d, 6815 "Quiescing I/O - ha=%p.\n", ha); 6816 6817 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 6818 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6819 atomic_set(&vha->loop_state, LOOP_DOWN); 6820 qla2x00_mark_all_devices_lost(vha); 6821 list_for_each_entry(vp, &ha->vp_list, list) 6822 qla2x00_mark_all_devices_lost(vp); 6823 } else { 6824 if (!atomic_read(&vha->loop_down_timer)) 6825 atomic_set(&vha->loop_down_timer, 6826 LOOP_DOWN_TIME); 6827 } 6828 /* Wait for pending cmds to complete */ 6829 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) 6830 != QLA_SUCCESS); 6831 } 6832 6833 void 6834 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 6835 { 6836 struct qla_hw_data *ha = vha->hw; 6837 struct scsi_qla_host *vp; 6838 unsigned long flags; 6839 fc_port_t *fcport; 6840 u16 i; 6841 6842 /* For ISP82XX, driver waits for completion of the commands. 6843 * online flag should be set. 6844 */ 6845 if (!(IS_P3P_TYPE(ha))) 6846 vha->flags.online = 0; 6847 ha->flags.chip_reset_done = 0; 6848 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 6849 vha->qla_stats.total_isp_aborts++; 6850 6851 ql_log(ql_log_info, vha, 0x00af, 6852 "Performing ISP error recovery - ha=%p.\n", ha); 6853 6854 ha->flags.purge_mbox = 1; 6855 /* For ISP82XX, reset_chip is just disabling interrupts. 6856 * Driver waits for the completion of the commands. 6857 * the interrupts need to be enabled. 6858 */ 6859 if (!(IS_P3P_TYPE(ha))) 6860 ha->isp_ops->reset_chip(vha); 6861 6862 ha->link_data_rate = PORT_SPEED_UNKNOWN; 6863 SAVE_TOPO(ha); 6864 ha->flags.rida_fmt2 = 0; 6865 ha->flags.n2n_ae = 0; 6866 ha->flags.lip_ae = 0; 6867 ha->current_topology = 0; 6868 QLA_FW_STOPPED(ha); 6869 ha->flags.fw_init_done = 0; 6870 ha->chip_reset++; 6871 ha->base_qpair->chip_reset = ha->chip_reset; 6872 for (i = 0; i < ha->max_qpairs; i++) { 6873 if (ha->queue_pair_map[i]) 6874 ha->queue_pair_map[i]->chip_reset = 6875 ha->base_qpair->chip_reset; 6876 } 6877 6878 /* purge MBox commands */ 6879 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6880 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6881 complete(&ha->mbx_intr_comp); 6882 } 6883 6884 i = 0; 6885 while (atomic_read(&ha->num_pend_mbx_stage3) || 6886 atomic_read(&ha->num_pend_mbx_stage2) || 6887 atomic_read(&ha->num_pend_mbx_stage1)) { 6888 msleep(20); 6889 i++; 6890 if (i > 50) 6891 break; 6892 } 6893 ha->flags.purge_mbox = 0; 6894 6895 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 6896 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6897 atomic_set(&vha->loop_state, LOOP_DOWN); 6898 qla2x00_mark_all_devices_lost(vha); 6899 6900 spin_lock_irqsave(&ha->vport_slock, flags); 6901 list_for_each_entry(vp, &ha->vp_list, list) { 6902 atomic_inc(&vp->vref_count); 6903 spin_unlock_irqrestore(&ha->vport_slock, flags); 6904 6905 qla2x00_mark_all_devices_lost(vp); 6906 6907 spin_lock_irqsave(&ha->vport_slock, flags); 6908 atomic_dec(&vp->vref_count); 6909 } 6910 spin_unlock_irqrestore(&ha->vport_slock, flags); 6911 } else { 6912 if (!atomic_read(&vha->loop_down_timer)) 6913 atomic_set(&vha->loop_down_timer, 6914 LOOP_DOWN_TIME); 6915 } 6916 6917 /* Clear all async request states across all VPs. */ 6918 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6919 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6920 fcport->scan_state = 0; 6921 } 6922 spin_lock_irqsave(&ha->vport_slock, flags); 6923 list_for_each_entry(vp, &ha->vp_list, list) { 6924 atomic_inc(&vp->vref_count); 6925 spin_unlock_irqrestore(&ha->vport_slock, flags); 6926 6927 list_for_each_entry(fcport, &vp->vp_fcports, list) 6928 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6929 6930 spin_lock_irqsave(&ha->vport_slock, flags); 6931 atomic_dec(&vp->vref_count); 6932 } 6933 spin_unlock_irqrestore(&ha->vport_slock, flags); 6934 6935 /* Make sure for ISP 82XX IO DMA is complete */ 6936 if (IS_P3P_TYPE(ha)) { 6937 qla82xx_chip_reset_cleanup(vha); 6938 ql_log(ql_log_info, vha, 0x00b4, 6939 "Done chip reset cleanup.\n"); 6940 6941 /* Done waiting for pending commands. Reset online flag */ 6942 vha->flags.online = 0; 6943 } 6944 6945 /* Requeue all commands in outstanding command list. */ 6946 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6947 /* memory barrier */ 6948 wmb(); 6949 } 6950 6951 /* 6952 * qla2x00_abort_isp 6953 * Resets ISP and aborts all outstanding commands. 6954 * 6955 * Input: 6956 * ha = adapter block pointer. 6957 * 6958 * Returns: 6959 * 0 = success 6960 */ 6961 int 6962 qla2x00_abort_isp(scsi_qla_host_t *vha) 6963 { 6964 int rval; 6965 uint8_t status = 0; 6966 struct qla_hw_data *ha = vha->hw; 6967 struct scsi_qla_host *vp; 6968 struct req_que *req = ha->req_q_map[0]; 6969 unsigned long flags; 6970 6971 if (vha->flags.online) { 6972 qla2x00_abort_isp_cleanup(vha); 6973 6974 if (vha->hw->flags.port_isolated) 6975 return status; 6976 6977 if (qla2x00_isp_reg_stat(ha)) { 6978 ql_log(ql_log_info, vha, 0x803f, 6979 "ISP Abort - ISP reg disconnect, exiting.\n"); 6980 return status; 6981 } 6982 6983 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) { 6984 ha->flags.chip_reset_done = 1; 6985 vha->flags.online = 1; 6986 status = 0; 6987 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6988 return status; 6989 } 6990 6991 if (IS_QLA8031(ha)) { 6992 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 6993 "Clearing fcoe driver presence.\n"); 6994 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 6995 ql_dbg(ql_dbg_p3p, vha, 0xb073, 6996 "Error while clearing DRV-Presence.\n"); 6997 } 6998 6999 if (unlikely(pci_channel_offline(ha->pdev) && 7000 ha->flags.pci_channel_io_perm_failure)) { 7001 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7002 status = 0; 7003 return status; 7004 } 7005 7006 switch (vha->qlini_mode) { 7007 case QLA2XXX_INI_MODE_DISABLED: 7008 if (!qla_tgt_mode_enabled(vha)) 7009 return 0; 7010 break; 7011 case QLA2XXX_INI_MODE_DUAL: 7012 if (!qla_dual_mode_enabled(vha)) 7013 return 0; 7014 break; 7015 case QLA2XXX_INI_MODE_ENABLED: 7016 default: 7017 break; 7018 } 7019 7020 ha->isp_ops->get_flash_version(vha, req->ring); 7021 7022 if (qla2x00_isp_reg_stat(ha)) { 7023 ql_log(ql_log_info, vha, 0x803f, 7024 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n"); 7025 return status; 7026 } 7027 ha->isp_ops->nvram_config(vha); 7028 7029 if (qla2x00_isp_reg_stat(ha)) { 7030 ql_log(ql_log_info, vha, 0x803f, 7031 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n"); 7032 return status; 7033 } 7034 if (!qla2x00_restart_isp(vha)) { 7035 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7036 7037 if (!atomic_read(&vha->loop_down_timer)) { 7038 /* 7039 * Issue marker command only when we are going 7040 * to start the I/O . 7041 */ 7042 vha->marker_needed = 1; 7043 } 7044 7045 vha->flags.online = 1; 7046 7047 ha->isp_ops->enable_intrs(ha); 7048 7049 ha->isp_abort_cnt = 0; 7050 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7051 7052 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 7053 qla2x00_get_fw_version(vha); 7054 if (ha->fce) { 7055 ha->flags.fce_enabled = 1; 7056 memset(ha->fce, 0, 7057 fce_calc_size(ha->fce_bufs)); 7058 rval = qla2x00_enable_fce_trace(vha, 7059 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 7060 &ha->fce_bufs); 7061 if (rval) { 7062 ql_log(ql_log_warn, vha, 0x8033, 7063 "Unable to reinitialize FCE " 7064 "(%d).\n", rval); 7065 ha->flags.fce_enabled = 0; 7066 } 7067 } 7068 7069 if (ha->eft) { 7070 memset(ha->eft, 0, EFT_SIZE); 7071 rval = qla2x00_enable_eft_trace(vha, 7072 ha->eft_dma, EFT_NUM_BUFFERS); 7073 if (rval) { 7074 ql_log(ql_log_warn, vha, 0x8034, 7075 "Unable to reinitialize EFT " 7076 "(%d).\n", rval); 7077 } 7078 } 7079 } else { /* failed the ISP abort */ 7080 vha->flags.online = 1; 7081 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 7082 if (ha->isp_abort_cnt == 0) { 7083 ql_log(ql_log_fatal, vha, 0x8035, 7084 "ISP error recover failed - " 7085 "board disabled.\n"); 7086 /* 7087 * The next call disables the board 7088 * completely. 7089 */ 7090 qla2x00_abort_isp_cleanup(vha); 7091 vha->flags.online = 0; 7092 clear_bit(ISP_ABORT_RETRY, 7093 &vha->dpc_flags); 7094 status = 0; 7095 } else { /* schedule another ISP abort */ 7096 ha->isp_abort_cnt--; 7097 ql_dbg(ql_dbg_taskm, vha, 0x8020, 7098 "ISP abort - retry remaining %d.\n", 7099 ha->isp_abort_cnt); 7100 status = 1; 7101 } 7102 } else { 7103 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 7104 ql_dbg(ql_dbg_taskm, vha, 0x8021, 7105 "ISP error recovery - retrying (%d) " 7106 "more times.\n", ha->isp_abort_cnt); 7107 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7108 status = 1; 7109 } 7110 } 7111 7112 } 7113 7114 if (vha->hw->flags.port_isolated) { 7115 qla2x00_abort_isp_cleanup(vha); 7116 return status; 7117 } 7118 7119 if (!status) { 7120 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 7121 qla2x00_configure_hba(vha); 7122 spin_lock_irqsave(&ha->vport_slock, flags); 7123 list_for_each_entry(vp, &ha->vp_list, list) { 7124 if (vp->vp_idx) { 7125 atomic_inc(&vp->vref_count); 7126 spin_unlock_irqrestore(&ha->vport_slock, flags); 7127 7128 qla2x00_vp_abort_isp(vp); 7129 7130 spin_lock_irqsave(&ha->vport_slock, flags); 7131 atomic_dec(&vp->vref_count); 7132 } 7133 } 7134 spin_unlock_irqrestore(&ha->vport_slock, flags); 7135 7136 if (IS_QLA8031(ha)) { 7137 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 7138 "Setting back fcoe driver presence.\n"); 7139 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 7140 ql_dbg(ql_dbg_p3p, vha, 0xb074, 7141 "Error while setting DRV-Presence.\n"); 7142 } 7143 } else { 7144 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 7145 __func__); 7146 } 7147 7148 return(status); 7149 } 7150 7151 /* 7152 * qla2x00_restart_isp 7153 * restarts the ISP after a reset 7154 * 7155 * Input: 7156 * ha = adapter block pointer. 7157 * 7158 * Returns: 7159 * 0 = success 7160 */ 7161 static int 7162 qla2x00_restart_isp(scsi_qla_host_t *vha) 7163 { 7164 int status; 7165 struct qla_hw_data *ha = vha->hw; 7166 7167 /* If firmware needs to be loaded */ 7168 if (qla2x00_isp_firmware(vha)) { 7169 vha->flags.online = 0; 7170 status = ha->isp_ops->chip_diag(vha); 7171 if (status) 7172 return status; 7173 status = qla2x00_setup_chip(vha); 7174 if (status) 7175 return status; 7176 } 7177 7178 status = qla2x00_init_rings(vha); 7179 if (status) 7180 return status; 7181 7182 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7183 ha->flags.chip_reset_done = 1; 7184 7185 /* Initialize the queues in use */ 7186 qla25xx_init_queues(ha); 7187 7188 status = qla2x00_fw_ready(vha); 7189 if (status) { 7190 /* if no cable then assume it's good */ 7191 return vha->device_flags & DFLG_NO_CABLE ? 0 : status; 7192 } 7193 7194 /* Issue a marker after FW becomes ready. */ 7195 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 7196 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7197 7198 return 0; 7199 } 7200 7201 static int 7202 qla25xx_init_queues(struct qla_hw_data *ha) 7203 { 7204 struct rsp_que *rsp = NULL; 7205 struct req_que *req = NULL; 7206 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7207 int ret = -1; 7208 int i; 7209 7210 for (i = 1; i < ha->max_rsp_queues; i++) { 7211 rsp = ha->rsp_q_map[i]; 7212 if (rsp && test_bit(i, ha->rsp_qid_map)) { 7213 rsp->options &= ~BIT_0; 7214 ret = qla25xx_init_rsp_que(base_vha, rsp); 7215 if (ret != QLA_SUCCESS) 7216 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 7217 "%s Rsp que: %d init failed.\n", 7218 __func__, rsp->id); 7219 else 7220 ql_dbg(ql_dbg_init, base_vha, 0x0100, 7221 "%s Rsp que: %d inited.\n", 7222 __func__, rsp->id); 7223 } 7224 } 7225 for (i = 1; i < ha->max_req_queues; i++) { 7226 req = ha->req_q_map[i]; 7227 if (req && test_bit(i, ha->req_qid_map)) { 7228 /* Clear outstanding commands array. */ 7229 req->options &= ~BIT_0; 7230 ret = qla25xx_init_req_que(base_vha, req); 7231 if (ret != QLA_SUCCESS) 7232 ql_dbg(ql_dbg_init, base_vha, 0x0101, 7233 "%s Req que: %d init failed.\n", 7234 __func__, req->id); 7235 else 7236 ql_dbg(ql_dbg_init, base_vha, 0x0102, 7237 "%s Req que: %d inited.\n", 7238 __func__, req->id); 7239 } 7240 } 7241 return ret; 7242 } 7243 7244 /* 7245 * qla2x00_reset_adapter 7246 * Reset adapter. 7247 * 7248 * Input: 7249 * ha = adapter block pointer. 7250 */ 7251 int 7252 qla2x00_reset_adapter(scsi_qla_host_t *vha) 7253 { 7254 unsigned long flags = 0; 7255 struct qla_hw_data *ha = vha->hw; 7256 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7257 7258 vha->flags.online = 0; 7259 ha->isp_ops->disable_intrs(ha); 7260 7261 spin_lock_irqsave(&ha->hardware_lock, flags); 7262 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 7263 rd_reg_word(®->hccr); /* PCI Posting. */ 7264 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 7265 rd_reg_word(®->hccr); /* PCI Posting. */ 7266 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7267 7268 return QLA_SUCCESS; 7269 } 7270 7271 int 7272 qla24xx_reset_adapter(scsi_qla_host_t *vha) 7273 { 7274 unsigned long flags = 0; 7275 struct qla_hw_data *ha = vha->hw; 7276 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 7277 7278 if (IS_P3P_TYPE(ha)) 7279 return QLA_SUCCESS; 7280 7281 vha->flags.online = 0; 7282 ha->isp_ops->disable_intrs(ha); 7283 7284 spin_lock_irqsave(&ha->hardware_lock, flags); 7285 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 7286 rd_reg_dword(®->hccr); 7287 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 7288 rd_reg_dword(®->hccr); 7289 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7290 7291 if (IS_NOPOLLING_TYPE(ha)) 7292 ha->isp_ops->enable_intrs(ha); 7293 7294 return QLA_SUCCESS; 7295 } 7296 7297 /* On sparc systems, obtain port and node WWN from firmware 7298 * properties. 7299 */ 7300 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 7301 struct nvram_24xx *nv) 7302 { 7303 #ifdef CONFIG_SPARC 7304 struct qla_hw_data *ha = vha->hw; 7305 struct pci_dev *pdev = ha->pdev; 7306 struct device_node *dp = pci_device_to_OF_node(pdev); 7307 const u8 *val; 7308 int len; 7309 7310 val = of_get_property(dp, "port-wwn", &len); 7311 if (val && len >= WWN_SIZE) 7312 memcpy(nv->port_name, val, WWN_SIZE); 7313 7314 val = of_get_property(dp, "node-wwn", &len); 7315 if (val && len >= WWN_SIZE) 7316 memcpy(nv->node_name, val, WWN_SIZE); 7317 #endif 7318 } 7319 7320 int 7321 qla24xx_nvram_config(scsi_qla_host_t *vha) 7322 { 7323 int rval; 7324 struct init_cb_24xx *icb; 7325 struct nvram_24xx *nv; 7326 __le32 *dptr; 7327 uint8_t *dptr1, *dptr2; 7328 uint32_t chksum; 7329 uint16_t cnt; 7330 struct qla_hw_data *ha = vha->hw; 7331 7332 rval = QLA_SUCCESS; 7333 icb = (struct init_cb_24xx *)ha->init_cb; 7334 nv = ha->nvram; 7335 7336 /* Determine NVRAM starting address. */ 7337 if (ha->port_no == 0) { 7338 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 7339 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 7340 } else { 7341 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 7342 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 7343 } 7344 7345 ha->nvram_size = sizeof(*nv); 7346 ha->vpd_size = FA_NVRAM_VPD_SIZE; 7347 7348 /* Get VPD data into cache */ 7349 ha->vpd = ha->nvram + VPD_OFFSET; 7350 ha->isp_ops->read_nvram(vha, ha->vpd, 7351 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 7352 7353 /* Get NVRAM data into cache and calculate checksum. */ 7354 dptr = (__force __le32 *)nv; 7355 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size); 7356 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 7357 chksum += le32_to_cpu(*dptr); 7358 7359 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 7360 "Contents of NVRAM\n"); 7361 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 7362 nv, ha->nvram_size); 7363 7364 /* Bad NVRAM data, set defaults parameters. */ 7365 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 7366 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 7367 /* Reset NVRAM data. */ 7368 ql_log(ql_log_warn, vha, 0x006b, 7369 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 7370 chksum, nv->id, nv->nvram_version); 7371 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv)); 7372 ql_log(ql_log_warn, vha, 0x006c, 7373 "Falling back to functioning (yet invalid -- WWPN) " 7374 "defaults.\n"); 7375 7376 /* 7377 * Set default initialization control block. 7378 */ 7379 memset(nv, 0, ha->nvram_size); 7380 nv->nvram_version = cpu_to_le16(ICB_VERSION); 7381 nv->version = cpu_to_le16(ICB_VERSION); 7382 nv->frame_payload_size = cpu_to_le16(2048); 7383 nv->execution_throttle = cpu_to_le16(0xFFFF); 7384 nv->exchange_count = cpu_to_le16(0); 7385 nv->hard_address = cpu_to_le16(124); 7386 nv->port_name[0] = 0x21; 7387 nv->port_name[1] = 0x00 + ha->port_no + 1; 7388 nv->port_name[2] = 0x00; 7389 nv->port_name[3] = 0xe0; 7390 nv->port_name[4] = 0x8b; 7391 nv->port_name[5] = 0x1c; 7392 nv->port_name[6] = 0x55; 7393 nv->port_name[7] = 0x86; 7394 nv->node_name[0] = 0x20; 7395 nv->node_name[1] = 0x00; 7396 nv->node_name[2] = 0x00; 7397 nv->node_name[3] = 0xe0; 7398 nv->node_name[4] = 0x8b; 7399 nv->node_name[5] = 0x1c; 7400 nv->node_name[6] = 0x55; 7401 nv->node_name[7] = 0x86; 7402 qla24xx_nvram_wwn_from_ofw(vha, nv); 7403 nv->login_retry_count = cpu_to_le16(8); 7404 nv->interrupt_delay_timer = cpu_to_le16(0); 7405 nv->login_timeout = cpu_to_le16(0); 7406 nv->firmware_options_1 = 7407 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 7408 nv->firmware_options_2 = cpu_to_le32(2 << 4); 7409 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 7410 nv->firmware_options_3 = cpu_to_le32(2 << 13); 7411 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 7412 nv->efi_parameters = cpu_to_le32(0); 7413 nv->reset_delay = 5; 7414 nv->max_luns_per_target = cpu_to_le16(128); 7415 nv->port_down_retry_count = cpu_to_le16(30); 7416 nv->link_down_timeout = cpu_to_le16(30); 7417 7418 rval = 1; 7419 } 7420 7421 if (qla_tgt_mode_enabled(vha)) { 7422 /* Don't enable full login after initial LIP */ 7423 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 7424 /* Don't enable LIP full login for initiator */ 7425 nv->host_p &= cpu_to_le32(~BIT_10); 7426 } 7427 7428 qlt_24xx_config_nvram_stage1(vha, nv); 7429 7430 /* Reset Initialization control block */ 7431 memset(icb, 0, ha->init_cb_size); 7432 7433 /* Copy 1st segment. */ 7434 dptr1 = (uint8_t *)icb; 7435 dptr2 = (uint8_t *)&nv->version; 7436 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 7437 while (cnt--) 7438 *dptr1++ = *dptr2++; 7439 7440 icb->login_retry_count = nv->login_retry_count; 7441 icb->link_down_on_nos = nv->link_down_on_nos; 7442 7443 /* Copy 2nd segment. */ 7444 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 7445 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 7446 cnt = (uint8_t *)&icb->reserved_3 - 7447 (uint8_t *)&icb->interrupt_delay_timer; 7448 while (cnt--) 7449 *dptr1++ = *dptr2++; 7450 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 7451 /* 7452 * Setup driver NVRAM options. 7453 */ 7454 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 7455 "QLA2462"); 7456 7457 qlt_24xx_config_nvram_stage2(vha, icb); 7458 7459 if (nv->host_p & cpu_to_le32(BIT_15)) { 7460 /* Use alternate WWN? */ 7461 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 7462 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 7463 } 7464 7465 /* Prepare nodename */ 7466 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 7467 /* 7468 * Firmware will apply the following mask if the nodename was 7469 * not provided. 7470 */ 7471 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 7472 icb->node_name[0] &= 0xF0; 7473 } 7474 7475 /* Set host adapter parameters. */ 7476 ha->flags.disable_risc_code_load = 0; 7477 ha->flags.enable_lip_reset = 0; 7478 ha->flags.enable_lip_full_login = 7479 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 7480 ha->flags.enable_target_reset = 7481 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 7482 ha->flags.enable_led_scheme = 0; 7483 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 7484 7485 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 7486 (BIT_6 | BIT_5 | BIT_4)) >> 4; 7487 7488 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 7489 sizeof(ha->fw_seriallink_options24)); 7490 7491 /* save HBA serial number */ 7492 ha->serial0 = icb->port_name[5]; 7493 ha->serial1 = icb->port_name[6]; 7494 ha->serial2 = icb->port_name[7]; 7495 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 7496 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 7497 7498 icb->execution_throttle = cpu_to_le16(0xFFFF); 7499 7500 ha->retry_count = le16_to_cpu(nv->login_retry_count); 7501 7502 /* Set minimum login_timeout to 4 seconds. */ 7503 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 7504 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 7505 if (le16_to_cpu(nv->login_timeout) < 4) 7506 nv->login_timeout = cpu_to_le16(4); 7507 ha->login_timeout = le16_to_cpu(nv->login_timeout); 7508 7509 /* Set minimum RATOV to 100 tenths of a second. */ 7510 ha->r_a_tov = 100; 7511 7512 ha->loop_reset_delay = nv->reset_delay; 7513 7514 /* Link Down Timeout = 0: 7515 * 7516 * When Port Down timer expires we will start returning 7517 * I/O's to OS with "DID_NO_CONNECT". 7518 * 7519 * Link Down Timeout != 0: 7520 * 7521 * The driver waits for the link to come up after link down 7522 * before returning I/Os to OS with "DID_NO_CONNECT". 7523 */ 7524 if (le16_to_cpu(nv->link_down_timeout) == 0) { 7525 ha->loop_down_abort_time = 7526 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 7527 } else { 7528 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 7529 ha->loop_down_abort_time = 7530 (LOOP_DOWN_TIME - ha->link_down_timeout); 7531 } 7532 7533 /* Need enough time to try and get the port back. */ 7534 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 7535 if (qlport_down_retry) 7536 ha->port_down_retry_count = qlport_down_retry; 7537 7538 /* Set login_retry_count */ 7539 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 7540 if (ha->port_down_retry_count == 7541 le16_to_cpu(nv->port_down_retry_count) && 7542 ha->port_down_retry_count > 3) 7543 ha->login_retry_count = ha->port_down_retry_count; 7544 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 7545 ha->login_retry_count = ha->port_down_retry_count; 7546 if (ql2xloginretrycount) 7547 ha->login_retry_count = ql2xloginretrycount; 7548 7549 /* N2N: driver will initiate Login instead of FW */ 7550 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 7551 7552 /* Enable ZIO. */ 7553 if (!vha->flags.init_done) { 7554 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 7555 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 7556 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 7557 le16_to_cpu(icb->interrupt_delay_timer) : 2; 7558 } 7559 icb->firmware_options_2 &= cpu_to_le32( 7560 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 7561 if (ha->zio_mode != QLA_ZIO_DISABLED) { 7562 ha->zio_mode = QLA_ZIO_MODE_6; 7563 7564 ql_log(ql_log_info, vha, 0x006f, 7565 "ZIO mode %d enabled; timer delay (%d us).\n", 7566 ha->zio_mode, ha->zio_timer * 100); 7567 7568 icb->firmware_options_2 |= cpu_to_le32( 7569 (uint32_t)ha->zio_mode); 7570 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 7571 } 7572 7573 if (rval) { 7574 ql_log(ql_log_warn, vha, 0x0070, 7575 "NVRAM configuration failed.\n"); 7576 } 7577 return (rval); 7578 } 7579 7580 static void 7581 qla27xx_print_image(struct scsi_qla_host *vha, char *name, 7582 struct qla27xx_image_status *image_status) 7583 { 7584 ql_dbg(ql_dbg_init, vha, 0x018b, 7585 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n", 7586 name, "status", 7587 image_status->image_status_mask, 7588 le16_to_cpu(image_status->generation), 7589 image_status->ver_major, 7590 image_status->ver_minor, 7591 image_status->bitmap, 7592 le32_to_cpu(image_status->checksum), 7593 le32_to_cpu(image_status->signature)); 7594 } 7595 7596 static bool 7597 qla28xx_check_aux_image_status_signature( 7598 struct qla27xx_image_status *image_status) 7599 { 7600 ulong signature = le32_to_cpu(image_status->signature); 7601 7602 return signature != QLA28XX_AUX_IMG_STATUS_SIGN; 7603 } 7604 7605 static bool 7606 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status) 7607 { 7608 ulong signature = le32_to_cpu(image_status->signature); 7609 7610 return 7611 signature != QLA27XX_IMG_STATUS_SIGN && 7612 signature != QLA28XX_IMG_STATUS_SIGN; 7613 } 7614 7615 static ulong 7616 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status) 7617 { 7618 __le32 *p = (__force __le32 *)image_status; 7619 uint n = sizeof(*image_status) / sizeof(*p); 7620 uint32_t sum = 0; 7621 7622 for ( ; n--; p++) 7623 sum += le32_to_cpup(p); 7624 7625 return sum; 7626 } 7627 7628 static inline uint 7629 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask) 7630 { 7631 return aux->bitmap & bitmask ? 7632 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE; 7633 } 7634 7635 static void 7636 qla28xx_component_status( 7637 struct active_regions *active_regions, struct qla27xx_image_status *aux) 7638 { 7639 active_regions->aux.board_config = 7640 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG); 7641 7642 active_regions->aux.vpd_nvram = 7643 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM); 7644 7645 active_regions->aux.npiv_config_0_1 = 7646 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1); 7647 7648 active_regions->aux.npiv_config_2_3 = 7649 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3); 7650 } 7651 7652 static int 7653 qla27xx_compare_image_generation( 7654 struct qla27xx_image_status *pri_image_status, 7655 struct qla27xx_image_status *sec_image_status) 7656 { 7657 /* calculate generation delta as uint16 (this accounts for wrap) */ 7658 int16_t delta = 7659 le16_to_cpu(pri_image_status->generation) - 7660 le16_to_cpu(sec_image_status->generation); 7661 7662 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta); 7663 7664 return delta; 7665 } 7666 7667 void 7668 qla28xx_get_aux_images( 7669 struct scsi_qla_host *vha, struct active_regions *active_regions) 7670 { 7671 struct qla_hw_data *ha = vha->hw; 7672 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status; 7673 bool valid_pri_image = false, valid_sec_image = false; 7674 bool active_pri_image = false, active_sec_image = false; 7675 7676 if (!ha->flt_region_aux_img_status_pri) { 7677 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n"); 7678 goto check_sec_image; 7679 } 7680 7681 qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status, 7682 ha->flt_region_aux_img_status_pri, 7683 sizeof(pri_aux_image_status) >> 2); 7684 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status); 7685 7686 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) { 7687 ql_dbg(ql_dbg_init, vha, 0x018b, 7688 "Primary aux image signature (%#x) not valid\n", 7689 le32_to_cpu(pri_aux_image_status.signature)); 7690 goto check_sec_image; 7691 } 7692 7693 if (qla27xx_image_status_checksum(&pri_aux_image_status)) { 7694 ql_dbg(ql_dbg_init, vha, 0x018c, 7695 "Primary aux image checksum failed\n"); 7696 goto check_sec_image; 7697 } 7698 7699 valid_pri_image = true; 7700 7701 if (pri_aux_image_status.image_status_mask & 1) { 7702 ql_dbg(ql_dbg_init, vha, 0x018d, 7703 "Primary aux image is active\n"); 7704 active_pri_image = true; 7705 } 7706 7707 check_sec_image: 7708 if (!ha->flt_region_aux_img_status_sec) { 7709 ql_dbg(ql_dbg_init, vha, 0x018a, 7710 "Secondary aux image not addressed\n"); 7711 goto check_valid_image; 7712 } 7713 7714 qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status, 7715 ha->flt_region_aux_img_status_sec, 7716 sizeof(sec_aux_image_status) >> 2); 7717 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status); 7718 7719 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) { 7720 ql_dbg(ql_dbg_init, vha, 0x018b, 7721 "Secondary aux image signature (%#x) not valid\n", 7722 le32_to_cpu(sec_aux_image_status.signature)); 7723 goto check_valid_image; 7724 } 7725 7726 if (qla27xx_image_status_checksum(&sec_aux_image_status)) { 7727 ql_dbg(ql_dbg_init, vha, 0x018c, 7728 "Secondary aux image checksum failed\n"); 7729 goto check_valid_image; 7730 } 7731 7732 valid_sec_image = true; 7733 7734 if (sec_aux_image_status.image_status_mask & 1) { 7735 ql_dbg(ql_dbg_init, vha, 0x018d, 7736 "Secondary aux image is active\n"); 7737 active_sec_image = true; 7738 } 7739 7740 check_valid_image: 7741 if (valid_pri_image && active_pri_image && 7742 valid_sec_image && active_sec_image) { 7743 if (qla27xx_compare_image_generation(&pri_aux_image_status, 7744 &sec_aux_image_status) >= 0) { 7745 qla28xx_component_status(active_regions, 7746 &pri_aux_image_status); 7747 } else { 7748 qla28xx_component_status(active_regions, 7749 &sec_aux_image_status); 7750 } 7751 } else if (valid_pri_image && active_pri_image) { 7752 qla28xx_component_status(active_regions, &pri_aux_image_status); 7753 } else if (valid_sec_image && active_sec_image) { 7754 qla28xx_component_status(active_regions, &sec_aux_image_status); 7755 } 7756 7757 ql_dbg(ql_dbg_init, vha, 0x018f, 7758 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n", 7759 active_regions->aux.board_config, 7760 active_regions->aux.vpd_nvram, 7761 active_regions->aux.npiv_config_0_1, 7762 active_regions->aux.npiv_config_2_3); 7763 } 7764 7765 void 7766 qla27xx_get_active_image(struct scsi_qla_host *vha, 7767 struct active_regions *active_regions) 7768 { 7769 struct qla_hw_data *ha = vha->hw; 7770 struct qla27xx_image_status pri_image_status, sec_image_status; 7771 bool valid_pri_image = false, valid_sec_image = false; 7772 bool active_pri_image = false, active_sec_image = false; 7773 7774 if (!ha->flt_region_img_status_pri) { 7775 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n"); 7776 goto check_sec_image; 7777 } 7778 7779 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status, 7780 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) != 7781 QLA_SUCCESS) { 7782 WARN_ON_ONCE(true); 7783 goto check_sec_image; 7784 } 7785 qla27xx_print_image(vha, "Primary image", &pri_image_status); 7786 7787 if (qla27xx_check_image_status_signature(&pri_image_status)) { 7788 ql_dbg(ql_dbg_init, vha, 0x018b, 7789 "Primary image signature (%#x) not valid\n", 7790 le32_to_cpu(pri_image_status.signature)); 7791 goto check_sec_image; 7792 } 7793 7794 if (qla27xx_image_status_checksum(&pri_image_status)) { 7795 ql_dbg(ql_dbg_init, vha, 0x018c, 7796 "Primary image checksum failed\n"); 7797 goto check_sec_image; 7798 } 7799 7800 valid_pri_image = true; 7801 7802 if (pri_image_status.image_status_mask & 1) { 7803 ql_dbg(ql_dbg_init, vha, 0x018d, 7804 "Primary image is active\n"); 7805 active_pri_image = true; 7806 } 7807 7808 check_sec_image: 7809 if (!ha->flt_region_img_status_sec) { 7810 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n"); 7811 goto check_valid_image; 7812 } 7813 7814 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 7815 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2); 7816 qla27xx_print_image(vha, "Secondary image", &sec_image_status); 7817 7818 if (qla27xx_check_image_status_signature(&sec_image_status)) { 7819 ql_dbg(ql_dbg_init, vha, 0x018b, 7820 "Secondary image signature (%#x) not valid\n", 7821 le32_to_cpu(sec_image_status.signature)); 7822 goto check_valid_image; 7823 } 7824 7825 if (qla27xx_image_status_checksum(&sec_image_status)) { 7826 ql_dbg(ql_dbg_init, vha, 0x018c, 7827 "Secondary image checksum failed\n"); 7828 goto check_valid_image; 7829 } 7830 7831 valid_sec_image = true; 7832 7833 if (sec_image_status.image_status_mask & 1) { 7834 ql_dbg(ql_dbg_init, vha, 0x018d, 7835 "Secondary image is active\n"); 7836 active_sec_image = true; 7837 } 7838 7839 check_valid_image: 7840 if (valid_pri_image && active_pri_image) 7841 active_regions->global = QLA27XX_PRIMARY_IMAGE; 7842 7843 if (valid_sec_image && active_sec_image) { 7844 if (!active_regions->global || 7845 qla27xx_compare_image_generation( 7846 &pri_image_status, &sec_image_status) < 0) { 7847 active_regions->global = QLA27XX_SECONDARY_IMAGE; 7848 } 7849 } 7850 7851 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n", 7852 active_regions->global == QLA27XX_DEFAULT_IMAGE ? 7853 "default (boot/fw)" : 7854 active_regions->global == QLA27XX_PRIMARY_IMAGE ? 7855 "primary" : 7856 active_regions->global == QLA27XX_SECONDARY_IMAGE ? 7857 "secondary" : "invalid", 7858 active_regions->global); 7859 } 7860 7861 bool qla24xx_risc_firmware_invalid(uint32_t *dword) 7862 { 7863 return 7864 !(dword[4] | dword[5] | dword[6] | dword[7]) || 7865 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]); 7866 } 7867 7868 static int 7869 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 7870 uint32_t faddr) 7871 { 7872 int rval; 7873 uint templates, segments, fragment; 7874 ulong i; 7875 uint j; 7876 ulong dlen; 7877 uint32_t *dcode; 7878 uint32_t risc_addr, risc_size, risc_attr = 0; 7879 struct qla_hw_data *ha = vha->hw; 7880 struct req_que *req = ha->req_q_map[0]; 7881 struct fwdt *fwdt = ha->fwdt; 7882 7883 ql_dbg(ql_dbg_init, vha, 0x008b, 7884 "FW: Loading firmware from flash (%x).\n", faddr); 7885 7886 dcode = (uint32_t *)req->ring; 7887 qla24xx_read_flash_data(vha, dcode, faddr, 8); 7888 if (qla24xx_risc_firmware_invalid(dcode)) { 7889 ql_log(ql_log_fatal, vha, 0x008c, 7890 "Unable to verify the integrity of flash firmware " 7891 "image.\n"); 7892 ql_log(ql_log_fatal, vha, 0x008d, 7893 "Firmware data: %08x %08x %08x %08x.\n", 7894 dcode[0], dcode[1], dcode[2], dcode[3]); 7895 7896 return QLA_FUNCTION_FAILED; 7897 } 7898 7899 dcode = (uint32_t *)req->ring; 7900 *srisc_addr = 0; 7901 segments = FA_RISC_CODE_SEGMENTS; 7902 for (j = 0; j < segments; j++) { 7903 ql_dbg(ql_dbg_init, vha, 0x008d, 7904 "-> Loading segment %u...\n", j); 7905 qla24xx_read_flash_data(vha, dcode, faddr, 10); 7906 risc_addr = be32_to_cpu((__force __be32)dcode[2]); 7907 risc_size = be32_to_cpu((__force __be32)dcode[3]); 7908 if (!*srisc_addr) { 7909 *srisc_addr = risc_addr; 7910 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 7911 } 7912 7913 dlen = ha->fw_transfer_size >> 2; 7914 for (fragment = 0; risc_size; fragment++) { 7915 if (dlen > risc_size) 7916 dlen = risc_size; 7917 7918 ql_dbg(ql_dbg_init, vha, 0x008e, 7919 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n", 7920 fragment, risc_addr, faddr, dlen); 7921 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 7922 for (i = 0; i < dlen; i++) 7923 dcode[i] = swab32(dcode[i]); 7924 7925 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 7926 if (rval) { 7927 ql_log(ql_log_fatal, vha, 0x008f, 7928 "-> Failed load firmware fragment %u.\n", 7929 fragment); 7930 return QLA_FUNCTION_FAILED; 7931 } 7932 7933 faddr += dlen; 7934 risc_addr += dlen; 7935 risc_size -= dlen; 7936 } 7937 } 7938 7939 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 7940 return QLA_SUCCESS; 7941 7942 templates = (risc_attr & BIT_9) ? 2 : 1; 7943 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates); 7944 for (j = 0; j < templates; j++, fwdt++) { 7945 vfree(fwdt->template); 7946 fwdt->template = NULL; 7947 fwdt->length = 0; 7948 7949 dcode = (uint32_t *)req->ring; 7950 qla24xx_read_flash_data(vha, dcode, faddr, 7); 7951 risc_size = be32_to_cpu((__force __be32)dcode[2]); 7952 ql_dbg(ql_dbg_init, vha, 0x0161, 7953 "-> fwdt%u template array at %#x (%#x dwords)\n", 7954 j, faddr, risc_size); 7955 if (!risc_size || !~risc_size) { 7956 ql_dbg(ql_dbg_init, vha, 0x0162, 7957 "-> fwdt%u failed to read array\n", j); 7958 goto failed; 7959 } 7960 7961 /* skip header and ignore checksum */ 7962 faddr += 7; 7963 risc_size -= 8; 7964 7965 ql_dbg(ql_dbg_init, vha, 0x0163, 7966 "-> fwdt%u template allocate template %#x words...\n", 7967 j, risc_size); 7968 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 7969 if (!fwdt->template) { 7970 ql_log(ql_log_warn, vha, 0x0164, 7971 "-> fwdt%u failed allocate template.\n", j); 7972 goto failed; 7973 } 7974 7975 dcode = fwdt->template; 7976 qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 7977 7978 if (!qla27xx_fwdt_template_valid(dcode)) { 7979 ql_log(ql_log_warn, vha, 0x0165, 7980 "-> fwdt%u failed template validate\n", j); 7981 goto failed; 7982 } 7983 7984 dlen = qla27xx_fwdt_template_size(dcode); 7985 ql_dbg(ql_dbg_init, vha, 0x0166, 7986 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 7987 j, dlen, dlen / sizeof(*dcode)); 7988 if (dlen > risc_size * sizeof(*dcode)) { 7989 ql_log(ql_log_warn, vha, 0x0167, 7990 "-> fwdt%u template exceeds array (%-lu bytes)\n", 7991 j, dlen - risc_size * sizeof(*dcode)); 7992 goto failed; 7993 } 7994 7995 fwdt->length = dlen; 7996 ql_dbg(ql_dbg_init, vha, 0x0168, 7997 "-> fwdt%u loaded template ok\n", j); 7998 7999 faddr += risc_size + 1; 8000 } 8001 8002 return QLA_SUCCESS; 8003 8004 failed: 8005 vfree(fwdt->template); 8006 fwdt->template = NULL; 8007 fwdt->length = 0; 8008 8009 return QLA_SUCCESS; 8010 } 8011 8012 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 8013 8014 int 8015 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8016 { 8017 int rval; 8018 int i, fragment; 8019 uint16_t *wcode; 8020 __be16 *fwcode; 8021 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 8022 struct fw_blob *blob; 8023 struct qla_hw_data *ha = vha->hw; 8024 struct req_que *req = ha->req_q_map[0]; 8025 8026 /* Load firmware blob. */ 8027 blob = qla2x00_request_firmware(vha); 8028 if (!blob) { 8029 ql_log(ql_log_info, vha, 0x0083, 8030 "Firmware image unavailable.\n"); 8031 ql_log(ql_log_info, vha, 0x0084, 8032 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 8033 return QLA_FUNCTION_FAILED; 8034 } 8035 8036 rval = QLA_SUCCESS; 8037 8038 wcode = (uint16_t *)req->ring; 8039 *srisc_addr = 0; 8040 fwcode = (__force __be16 *)blob->fw->data; 8041 fwclen = 0; 8042 8043 /* Validate firmware image by checking version. */ 8044 if (blob->fw->size < 8 * sizeof(uint16_t)) { 8045 ql_log(ql_log_fatal, vha, 0x0085, 8046 "Unable to verify integrity of firmware image (%zd).\n", 8047 blob->fw->size); 8048 goto fail_fw_integrity; 8049 } 8050 for (i = 0; i < 4; i++) 8051 wcode[i] = be16_to_cpu(fwcode[i + 4]); 8052 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 8053 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 8054 wcode[2] == 0 && wcode[3] == 0)) { 8055 ql_log(ql_log_fatal, vha, 0x0086, 8056 "Unable to verify integrity of firmware image.\n"); 8057 ql_log(ql_log_fatal, vha, 0x0087, 8058 "Firmware data: %04x %04x %04x %04x.\n", 8059 wcode[0], wcode[1], wcode[2], wcode[3]); 8060 goto fail_fw_integrity; 8061 } 8062 8063 seg = blob->segs; 8064 while (*seg && rval == QLA_SUCCESS) { 8065 risc_addr = *seg; 8066 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 8067 risc_size = be16_to_cpu(fwcode[3]); 8068 8069 /* Validate firmware image size. */ 8070 fwclen += risc_size * sizeof(uint16_t); 8071 if (blob->fw->size < fwclen) { 8072 ql_log(ql_log_fatal, vha, 0x0088, 8073 "Unable to verify integrity of firmware image " 8074 "(%zd).\n", blob->fw->size); 8075 goto fail_fw_integrity; 8076 } 8077 8078 fragment = 0; 8079 while (risc_size > 0 && rval == QLA_SUCCESS) { 8080 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 8081 if (wlen > risc_size) 8082 wlen = risc_size; 8083 ql_dbg(ql_dbg_init, vha, 0x0089, 8084 "Loading risc segment@ risc addr %x number of " 8085 "words 0x%x.\n", risc_addr, wlen); 8086 8087 for (i = 0; i < wlen; i++) 8088 wcode[i] = swab16((__force u32)fwcode[i]); 8089 8090 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8091 wlen); 8092 if (rval) { 8093 ql_log(ql_log_fatal, vha, 0x008a, 8094 "Failed to load segment %d of firmware.\n", 8095 fragment); 8096 break; 8097 } 8098 8099 fwcode += wlen; 8100 risc_addr += wlen; 8101 risc_size -= wlen; 8102 fragment++; 8103 } 8104 8105 /* Next segment. */ 8106 seg++; 8107 } 8108 return rval; 8109 8110 fail_fw_integrity: 8111 return QLA_FUNCTION_FAILED; 8112 } 8113 8114 static int 8115 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8116 { 8117 int rval; 8118 uint templates, segments, fragment; 8119 uint32_t *dcode; 8120 ulong dlen; 8121 uint32_t risc_addr, risc_size, risc_attr = 0; 8122 ulong i; 8123 uint j; 8124 struct fw_blob *blob; 8125 __be32 *fwcode; 8126 struct qla_hw_data *ha = vha->hw; 8127 struct req_que *req = ha->req_q_map[0]; 8128 struct fwdt *fwdt = ha->fwdt; 8129 8130 ql_dbg(ql_dbg_init, vha, 0x0090, 8131 "-> FW: Loading via request-firmware.\n"); 8132 8133 blob = qla2x00_request_firmware(vha); 8134 if (!blob) { 8135 ql_log(ql_log_warn, vha, 0x0092, 8136 "-> Firmware file not found.\n"); 8137 8138 return QLA_FUNCTION_FAILED; 8139 } 8140 8141 fwcode = (__force __be32 *)blob->fw->data; 8142 dcode = (__force uint32_t *)fwcode; 8143 if (qla24xx_risc_firmware_invalid(dcode)) { 8144 ql_log(ql_log_fatal, vha, 0x0093, 8145 "Unable to verify integrity of firmware image (%zd).\n", 8146 blob->fw->size); 8147 ql_log(ql_log_fatal, vha, 0x0095, 8148 "Firmware data: %08x %08x %08x %08x.\n", 8149 dcode[0], dcode[1], dcode[2], dcode[3]); 8150 return QLA_FUNCTION_FAILED; 8151 } 8152 8153 dcode = (uint32_t *)req->ring; 8154 *srisc_addr = 0; 8155 segments = FA_RISC_CODE_SEGMENTS; 8156 for (j = 0; j < segments; j++) { 8157 ql_dbg(ql_dbg_init, vha, 0x0096, 8158 "-> Loading segment %u...\n", j); 8159 risc_addr = be32_to_cpu(fwcode[2]); 8160 risc_size = be32_to_cpu(fwcode[3]); 8161 8162 if (!*srisc_addr) { 8163 *srisc_addr = risc_addr; 8164 risc_attr = be32_to_cpu(fwcode[9]); 8165 } 8166 8167 dlen = ha->fw_transfer_size >> 2; 8168 for (fragment = 0; risc_size; fragment++) { 8169 if (dlen > risc_size) 8170 dlen = risc_size; 8171 8172 ql_dbg(ql_dbg_init, vha, 0x0097, 8173 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n", 8174 fragment, risc_addr, 8175 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), 8176 dlen); 8177 8178 for (i = 0; i < dlen; i++) 8179 dcode[i] = swab32((__force u32)fwcode[i]); 8180 8181 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 8182 if (rval) { 8183 ql_log(ql_log_fatal, vha, 0x0098, 8184 "-> Failed load firmware fragment %u.\n", 8185 fragment); 8186 return QLA_FUNCTION_FAILED; 8187 } 8188 8189 fwcode += dlen; 8190 risc_addr += dlen; 8191 risc_size -= dlen; 8192 } 8193 } 8194 8195 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8196 return QLA_SUCCESS; 8197 8198 templates = (risc_attr & BIT_9) ? 2 : 1; 8199 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates); 8200 for (j = 0; j < templates; j++, fwdt++) { 8201 vfree(fwdt->template); 8202 fwdt->template = NULL; 8203 fwdt->length = 0; 8204 8205 risc_size = be32_to_cpu(fwcode[2]); 8206 ql_dbg(ql_dbg_init, vha, 0x0171, 8207 "-> fwdt%u template array at %#x (%#x dwords)\n", 8208 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), 8209 risc_size); 8210 if (!risc_size || !~risc_size) { 8211 ql_dbg(ql_dbg_init, vha, 0x0172, 8212 "-> fwdt%u failed to read array\n", j); 8213 goto failed; 8214 } 8215 8216 /* skip header and ignore checksum */ 8217 fwcode += 7; 8218 risc_size -= 8; 8219 8220 ql_dbg(ql_dbg_init, vha, 0x0173, 8221 "-> fwdt%u template allocate template %#x words...\n", 8222 j, risc_size); 8223 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 8224 if (!fwdt->template) { 8225 ql_log(ql_log_warn, vha, 0x0174, 8226 "-> fwdt%u failed allocate template.\n", j); 8227 goto failed; 8228 } 8229 8230 dcode = fwdt->template; 8231 for (i = 0; i < risc_size; i++) 8232 dcode[i] = (__force u32)fwcode[i]; 8233 8234 if (!qla27xx_fwdt_template_valid(dcode)) { 8235 ql_log(ql_log_warn, vha, 0x0175, 8236 "-> fwdt%u failed template validate\n", j); 8237 goto failed; 8238 } 8239 8240 dlen = qla27xx_fwdt_template_size(dcode); 8241 ql_dbg(ql_dbg_init, vha, 0x0176, 8242 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8243 j, dlen, dlen / sizeof(*dcode)); 8244 if (dlen > risc_size * sizeof(*dcode)) { 8245 ql_log(ql_log_warn, vha, 0x0177, 8246 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8247 j, dlen - risc_size * sizeof(*dcode)); 8248 goto failed; 8249 } 8250 8251 fwdt->length = dlen; 8252 ql_dbg(ql_dbg_init, vha, 0x0178, 8253 "-> fwdt%u loaded template ok\n", j); 8254 8255 fwcode += risc_size + 1; 8256 } 8257 8258 return QLA_SUCCESS; 8259 8260 failed: 8261 vfree(fwdt->template); 8262 fwdt->template = NULL; 8263 fwdt->length = 0; 8264 8265 return QLA_SUCCESS; 8266 } 8267 8268 int 8269 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8270 { 8271 int rval; 8272 8273 if (ql2xfwloadbin == 1) 8274 return qla81xx_load_risc(vha, srisc_addr); 8275 8276 /* 8277 * FW Load priority: 8278 * 1) Firmware via request-firmware interface (.bin file). 8279 * 2) Firmware residing in flash. 8280 */ 8281 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8282 if (rval == QLA_SUCCESS) 8283 return rval; 8284 8285 return qla24xx_load_risc_flash(vha, srisc_addr, 8286 vha->hw->flt_region_fw); 8287 } 8288 8289 int 8290 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8291 { 8292 int rval; 8293 struct qla_hw_data *ha = vha->hw; 8294 struct active_regions active_regions = { }; 8295 8296 if (ql2xfwloadbin == 2) 8297 goto try_blob_fw; 8298 8299 /* FW Load priority: 8300 * 1) Firmware residing in flash. 8301 * 2) Firmware via request-firmware interface (.bin file). 8302 * 3) Golden-Firmware residing in flash -- (limited operation). 8303 */ 8304 8305 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8306 goto try_primary_fw; 8307 8308 qla27xx_get_active_image(vha, &active_regions); 8309 8310 if (active_regions.global != QLA27XX_SECONDARY_IMAGE) 8311 goto try_primary_fw; 8312 8313 ql_dbg(ql_dbg_init, vha, 0x008b, 8314 "Loading secondary firmware image.\n"); 8315 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec); 8316 if (!rval) 8317 return rval; 8318 8319 try_primary_fw: 8320 ql_dbg(ql_dbg_init, vha, 0x008b, 8321 "Loading primary firmware image.\n"); 8322 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 8323 if (!rval) 8324 return rval; 8325 8326 try_blob_fw: 8327 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8328 if (!rval || !ha->flt_region_gold_fw) 8329 return rval; 8330 8331 ql_log(ql_log_info, vha, 0x0099, 8332 "Attempting to fallback to golden firmware.\n"); 8333 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 8334 if (rval) 8335 return rval; 8336 8337 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n"); 8338 ha->flags.running_gold_fw = 1; 8339 return rval; 8340 } 8341 8342 void 8343 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 8344 { 8345 int ret, retries; 8346 struct qla_hw_data *ha = vha->hw; 8347 8348 if (ha->flags.pci_channel_io_perm_failure) 8349 return; 8350 if (!IS_FWI2_CAPABLE(ha)) 8351 return; 8352 if (!ha->fw_major_version) 8353 return; 8354 if (!ha->flags.fw_started) 8355 return; 8356 8357 ret = qla2x00_stop_firmware(vha); 8358 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 8359 ret != QLA_INVALID_COMMAND && retries ; retries--) { 8360 ha->isp_ops->reset_chip(vha); 8361 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 8362 continue; 8363 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 8364 continue; 8365 ql_log(ql_log_info, vha, 0x8015, 8366 "Attempting retry of stop-firmware command.\n"); 8367 ret = qla2x00_stop_firmware(vha); 8368 } 8369 8370 QLA_FW_STOPPED(ha); 8371 ha->flags.fw_init_done = 0; 8372 } 8373 8374 int 8375 qla24xx_configure_vhba(scsi_qla_host_t *vha) 8376 { 8377 int rval = QLA_SUCCESS; 8378 int rval2; 8379 uint16_t mb[MAILBOX_REGISTER_COUNT]; 8380 struct qla_hw_data *ha = vha->hw; 8381 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8382 8383 if (!vha->vp_idx) 8384 return -EINVAL; 8385 8386 rval = qla2x00_fw_ready(base_vha); 8387 8388 if (rval == QLA_SUCCESS) { 8389 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8390 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8391 } 8392 8393 vha->flags.management_server_logged_in = 0; 8394 8395 /* Login to SNS first */ 8396 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 8397 BIT_1); 8398 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 8399 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 8400 ql_dbg(ql_dbg_init, vha, 0x0120, 8401 "Failed SNS login: loop_id=%x, rval2=%d\n", 8402 NPH_SNS, rval2); 8403 else 8404 ql_dbg(ql_dbg_init, vha, 0x0103, 8405 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 8406 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 8407 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 8408 return (QLA_FUNCTION_FAILED); 8409 } 8410 8411 atomic_set(&vha->loop_down_timer, 0); 8412 atomic_set(&vha->loop_state, LOOP_UP); 8413 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8414 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 8415 rval = qla2x00_loop_resync(base_vha); 8416 8417 return rval; 8418 } 8419 8420 /* 84XX Support **************************************************************/ 8421 8422 static LIST_HEAD(qla_cs84xx_list); 8423 static DEFINE_MUTEX(qla_cs84xx_mutex); 8424 8425 static struct qla_chip_state_84xx * 8426 qla84xx_get_chip(struct scsi_qla_host *vha) 8427 { 8428 struct qla_chip_state_84xx *cs84xx; 8429 struct qla_hw_data *ha = vha->hw; 8430 8431 mutex_lock(&qla_cs84xx_mutex); 8432 8433 /* Find any shared 84xx chip. */ 8434 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 8435 if (cs84xx->bus == ha->pdev->bus) { 8436 kref_get(&cs84xx->kref); 8437 goto done; 8438 } 8439 } 8440 8441 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 8442 if (!cs84xx) 8443 goto done; 8444 8445 kref_init(&cs84xx->kref); 8446 spin_lock_init(&cs84xx->access_lock); 8447 mutex_init(&cs84xx->fw_update_mutex); 8448 cs84xx->bus = ha->pdev->bus; 8449 8450 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 8451 done: 8452 mutex_unlock(&qla_cs84xx_mutex); 8453 return cs84xx; 8454 } 8455 8456 static void 8457 __qla84xx_chip_release(struct kref *kref) 8458 { 8459 struct qla_chip_state_84xx *cs84xx = 8460 container_of(kref, struct qla_chip_state_84xx, kref); 8461 8462 mutex_lock(&qla_cs84xx_mutex); 8463 list_del(&cs84xx->list); 8464 mutex_unlock(&qla_cs84xx_mutex); 8465 kfree(cs84xx); 8466 } 8467 8468 void 8469 qla84xx_put_chip(struct scsi_qla_host *vha) 8470 { 8471 struct qla_hw_data *ha = vha->hw; 8472 8473 if (ha->cs84xx) 8474 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 8475 } 8476 8477 static int 8478 qla84xx_init_chip(scsi_qla_host_t *vha) 8479 { 8480 int rval; 8481 uint16_t status[2]; 8482 struct qla_hw_data *ha = vha->hw; 8483 8484 mutex_lock(&ha->cs84xx->fw_update_mutex); 8485 8486 rval = qla84xx_verify_chip(vha, status); 8487 8488 mutex_unlock(&ha->cs84xx->fw_update_mutex); 8489 8490 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED : 8491 QLA_SUCCESS; 8492 } 8493 8494 /* 81XX Support **************************************************************/ 8495 8496 int 8497 qla81xx_nvram_config(scsi_qla_host_t *vha) 8498 { 8499 int rval; 8500 struct init_cb_81xx *icb; 8501 struct nvram_81xx *nv; 8502 __le32 *dptr; 8503 uint8_t *dptr1, *dptr2; 8504 uint32_t chksum; 8505 uint16_t cnt; 8506 struct qla_hw_data *ha = vha->hw; 8507 uint32_t faddr; 8508 struct active_regions active_regions = { }; 8509 8510 rval = QLA_SUCCESS; 8511 icb = (struct init_cb_81xx *)ha->init_cb; 8512 nv = ha->nvram; 8513 8514 /* Determine NVRAM starting address. */ 8515 ha->nvram_size = sizeof(*nv); 8516 ha->vpd_size = FA_NVRAM_VPD_SIZE; 8517 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 8518 ha->vpd_size = FA_VPD_SIZE_82XX; 8519 8520 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) 8521 qla28xx_get_aux_images(vha, &active_regions); 8522 8523 /* Get VPD data into cache */ 8524 ha->vpd = ha->nvram + VPD_OFFSET; 8525 8526 faddr = ha->flt_region_vpd; 8527 if (IS_QLA28XX(ha)) { 8528 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8529 faddr = ha->flt_region_vpd_sec; 8530 ql_dbg(ql_dbg_init, vha, 0x0110, 8531 "Loading %s nvram image.\n", 8532 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8533 "primary" : "secondary"); 8534 } 8535 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size); 8536 8537 /* Get NVRAM data into cache and calculate checksum. */ 8538 faddr = ha->flt_region_nvram; 8539 if (IS_QLA28XX(ha)) { 8540 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8541 faddr = ha->flt_region_nvram_sec; 8542 } 8543 ql_dbg(ql_dbg_init, vha, 0x0110, 8544 "Loading %s nvram image.\n", 8545 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8546 "primary" : "secondary"); 8547 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size); 8548 8549 dptr = (__force __le32 *)nv; 8550 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 8551 chksum += le32_to_cpu(*dptr); 8552 8553 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 8554 "Contents of NVRAM:\n"); 8555 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 8556 nv, ha->nvram_size); 8557 8558 /* Bad NVRAM data, set defaults parameters. */ 8559 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 8560 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 8561 /* Reset NVRAM data. */ 8562 ql_log(ql_log_info, vha, 0x0073, 8563 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 8564 chksum, nv->id, le16_to_cpu(nv->nvram_version)); 8565 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv)); 8566 ql_log(ql_log_info, vha, 0x0074, 8567 "Falling back to functioning (yet invalid -- WWPN) " 8568 "defaults.\n"); 8569 8570 /* 8571 * Set default initialization control block. 8572 */ 8573 memset(nv, 0, ha->nvram_size); 8574 nv->nvram_version = cpu_to_le16(ICB_VERSION); 8575 nv->version = cpu_to_le16(ICB_VERSION); 8576 nv->frame_payload_size = cpu_to_le16(2048); 8577 nv->execution_throttle = cpu_to_le16(0xFFFF); 8578 nv->exchange_count = cpu_to_le16(0); 8579 nv->port_name[0] = 0x21; 8580 nv->port_name[1] = 0x00 + ha->port_no + 1; 8581 nv->port_name[2] = 0x00; 8582 nv->port_name[3] = 0xe0; 8583 nv->port_name[4] = 0x8b; 8584 nv->port_name[5] = 0x1c; 8585 nv->port_name[6] = 0x55; 8586 nv->port_name[7] = 0x86; 8587 nv->node_name[0] = 0x20; 8588 nv->node_name[1] = 0x00; 8589 nv->node_name[2] = 0x00; 8590 nv->node_name[3] = 0xe0; 8591 nv->node_name[4] = 0x8b; 8592 nv->node_name[5] = 0x1c; 8593 nv->node_name[6] = 0x55; 8594 nv->node_name[7] = 0x86; 8595 nv->login_retry_count = cpu_to_le16(8); 8596 nv->interrupt_delay_timer = cpu_to_le16(0); 8597 nv->login_timeout = cpu_to_le16(0); 8598 nv->firmware_options_1 = 8599 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 8600 nv->firmware_options_2 = cpu_to_le32(2 << 4); 8601 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 8602 nv->firmware_options_3 = cpu_to_le32(2 << 13); 8603 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 8604 nv->efi_parameters = cpu_to_le32(0); 8605 nv->reset_delay = 5; 8606 nv->max_luns_per_target = cpu_to_le16(128); 8607 nv->port_down_retry_count = cpu_to_le16(30); 8608 nv->link_down_timeout = cpu_to_le16(180); 8609 nv->enode_mac[0] = 0x00; 8610 nv->enode_mac[1] = 0xC0; 8611 nv->enode_mac[2] = 0xDD; 8612 nv->enode_mac[3] = 0x04; 8613 nv->enode_mac[4] = 0x05; 8614 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 8615 8616 rval = 1; 8617 } 8618 8619 if (IS_T10_PI_CAPABLE(ha)) 8620 nv->frame_payload_size &= cpu_to_le16(~7); 8621 8622 qlt_81xx_config_nvram_stage1(vha, nv); 8623 8624 /* Reset Initialization control block */ 8625 memset(icb, 0, ha->init_cb_size); 8626 8627 /* Copy 1st segment. */ 8628 dptr1 = (uint8_t *)icb; 8629 dptr2 = (uint8_t *)&nv->version; 8630 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 8631 while (cnt--) 8632 *dptr1++ = *dptr2++; 8633 8634 icb->login_retry_count = nv->login_retry_count; 8635 8636 /* Copy 2nd segment. */ 8637 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 8638 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 8639 cnt = (uint8_t *)&icb->reserved_5 - 8640 (uint8_t *)&icb->interrupt_delay_timer; 8641 while (cnt--) 8642 *dptr1++ = *dptr2++; 8643 8644 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 8645 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 8646 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 8647 icb->enode_mac[0] = 0x00; 8648 icb->enode_mac[1] = 0xC0; 8649 icb->enode_mac[2] = 0xDD; 8650 icb->enode_mac[3] = 0x04; 8651 icb->enode_mac[4] = 0x05; 8652 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 8653 } 8654 8655 /* Use extended-initialization control block. */ 8656 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 8657 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 8658 /* 8659 * Setup driver NVRAM options. 8660 */ 8661 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 8662 "QLE8XXX"); 8663 8664 qlt_81xx_config_nvram_stage2(vha, icb); 8665 8666 /* Use alternate WWN? */ 8667 if (nv->host_p & cpu_to_le32(BIT_15)) { 8668 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 8669 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 8670 } 8671 8672 /* Prepare nodename */ 8673 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 8674 /* 8675 * Firmware will apply the following mask if the nodename was 8676 * not provided. 8677 */ 8678 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 8679 icb->node_name[0] &= 0xF0; 8680 } 8681 8682 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) { 8683 if ((nv->enhanced_features & BIT_7) == 0) 8684 ha->flags.scm_supported_a = 1; 8685 } 8686 8687 /* Set host adapter parameters. */ 8688 ha->flags.disable_risc_code_load = 0; 8689 ha->flags.enable_lip_reset = 0; 8690 ha->flags.enable_lip_full_login = 8691 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 8692 ha->flags.enable_target_reset = 8693 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 8694 ha->flags.enable_led_scheme = 0; 8695 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 8696 8697 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 8698 (BIT_6 | BIT_5 | BIT_4)) >> 4; 8699 8700 /* save HBA serial number */ 8701 ha->serial0 = icb->port_name[5]; 8702 ha->serial1 = icb->port_name[6]; 8703 ha->serial2 = icb->port_name[7]; 8704 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 8705 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 8706 8707 icb->execution_throttle = cpu_to_le16(0xFFFF); 8708 8709 ha->retry_count = le16_to_cpu(nv->login_retry_count); 8710 8711 /* Set minimum login_timeout to 4 seconds. */ 8712 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 8713 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 8714 if (le16_to_cpu(nv->login_timeout) < 4) 8715 nv->login_timeout = cpu_to_le16(4); 8716 ha->login_timeout = le16_to_cpu(nv->login_timeout); 8717 8718 /* Set minimum RATOV to 100 tenths of a second. */ 8719 ha->r_a_tov = 100; 8720 8721 ha->loop_reset_delay = nv->reset_delay; 8722 8723 /* Link Down Timeout = 0: 8724 * 8725 * When Port Down timer expires we will start returning 8726 * I/O's to OS with "DID_NO_CONNECT". 8727 * 8728 * Link Down Timeout != 0: 8729 * 8730 * The driver waits for the link to come up after link down 8731 * before returning I/Os to OS with "DID_NO_CONNECT". 8732 */ 8733 if (le16_to_cpu(nv->link_down_timeout) == 0) { 8734 ha->loop_down_abort_time = 8735 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 8736 } else { 8737 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 8738 ha->loop_down_abort_time = 8739 (LOOP_DOWN_TIME - ha->link_down_timeout); 8740 } 8741 8742 /* Need enough time to try and get the port back. */ 8743 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 8744 if (qlport_down_retry) 8745 ha->port_down_retry_count = qlport_down_retry; 8746 8747 /* Set login_retry_count */ 8748 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 8749 if (ha->port_down_retry_count == 8750 le16_to_cpu(nv->port_down_retry_count) && 8751 ha->port_down_retry_count > 3) 8752 ha->login_retry_count = ha->port_down_retry_count; 8753 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 8754 ha->login_retry_count = ha->port_down_retry_count; 8755 if (ql2xloginretrycount) 8756 ha->login_retry_count = ql2xloginretrycount; 8757 8758 /* if not running MSI-X we need handshaking on interrupts */ 8759 if (!vha->hw->flags.msix_enabled && 8760 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) 8761 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 8762 8763 /* Enable ZIO. */ 8764 if (!vha->flags.init_done) { 8765 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 8766 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 8767 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 8768 le16_to_cpu(icb->interrupt_delay_timer) : 2; 8769 } 8770 icb->firmware_options_2 &= cpu_to_le32( 8771 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 8772 vha->flags.process_response_queue = 0; 8773 if (ha->zio_mode != QLA_ZIO_DISABLED) { 8774 ha->zio_mode = QLA_ZIO_MODE_6; 8775 8776 ql_log(ql_log_info, vha, 0x0075, 8777 "ZIO mode %d enabled; timer delay (%d us).\n", 8778 ha->zio_mode, 8779 ha->zio_timer * 100); 8780 8781 icb->firmware_options_2 |= cpu_to_le32( 8782 (uint32_t)ha->zio_mode); 8783 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 8784 vha->flags.process_response_queue = 1; 8785 } 8786 8787 /* enable RIDA Format2 */ 8788 icb->firmware_options_3 |= cpu_to_le32(BIT_0); 8789 8790 /* N2N: driver will initiate Login instead of FW */ 8791 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 8792 8793 /* Determine NVMe/FCP priority for target ports */ 8794 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha); 8795 8796 if (rval) { 8797 ql_log(ql_log_warn, vha, 0x0076, 8798 "NVRAM configuration failed.\n"); 8799 } 8800 return (rval); 8801 } 8802 8803 int 8804 qla82xx_restart_isp(scsi_qla_host_t *vha) 8805 { 8806 int status, rval; 8807 struct qla_hw_data *ha = vha->hw; 8808 struct scsi_qla_host *vp; 8809 unsigned long flags; 8810 8811 status = qla2x00_init_rings(vha); 8812 if (!status) { 8813 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8814 ha->flags.chip_reset_done = 1; 8815 8816 status = qla2x00_fw_ready(vha); 8817 if (!status) { 8818 /* Issue a marker after FW becomes ready. */ 8819 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8820 vha->flags.online = 1; 8821 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8822 } 8823 8824 /* if no cable then assume it's good */ 8825 if ((vha->device_flags & DFLG_NO_CABLE)) 8826 status = 0; 8827 } 8828 8829 if (!status) { 8830 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8831 8832 if (!atomic_read(&vha->loop_down_timer)) { 8833 /* 8834 * Issue marker command only when we are going 8835 * to start the I/O . 8836 */ 8837 vha->marker_needed = 1; 8838 } 8839 8840 ha->isp_ops->enable_intrs(ha); 8841 8842 ha->isp_abort_cnt = 0; 8843 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 8844 8845 /* Update the firmware version */ 8846 status = qla82xx_check_md_needed(vha); 8847 8848 if (ha->fce) { 8849 ha->flags.fce_enabled = 1; 8850 memset(ha->fce, 0, 8851 fce_calc_size(ha->fce_bufs)); 8852 rval = qla2x00_enable_fce_trace(vha, 8853 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 8854 &ha->fce_bufs); 8855 if (rval) { 8856 ql_log(ql_log_warn, vha, 0x8001, 8857 "Unable to reinitialize FCE (%d).\n", 8858 rval); 8859 ha->flags.fce_enabled = 0; 8860 } 8861 } 8862 8863 if (ha->eft) { 8864 memset(ha->eft, 0, EFT_SIZE); 8865 rval = qla2x00_enable_eft_trace(vha, 8866 ha->eft_dma, EFT_NUM_BUFFERS); 8867 if (rval) { 8868 ql_log(ql_log_warn, vha, 0x8010, 8869 "Unable to reinitialize EFT (%d).\n", 8870 rval); 8871 } 8872 } 8873 } 8874 8875 if (!status) { 8876 ql_dbg(ql_dbg_taskm, vha, 0x8011, 8877 "qla82xx_restart_isp succeeded.\n"); 8878 8879 spin_lock_irqsave(&ha->vport_slock, flags); 8880 list_for_each_entry(vp, &ha->vp_list, list) { 8881 if (vp->vp_idx) { 8882 atomic_inc(&vp->vref_count); 8883 spin_unlock_irqrestore(&ha->vport_slock, flags); 8884 8885 qla2x00_vp_abort_isp(vp); 8886 8887 spin_lock_irqsave(&ha->vport_slock, flags); 8888 atomic_dec(&vp->vref_count); 8889 } 8890 } 8891 spin_unlock_irqrestore(&ha->vport_slock, flags); 8892 8893 } else { 8894 ql_log(ql_log_warn, vha, 0x8016, 8895 "qla82xx_restart_isp **** FAILED ****.\n"); 8896 } 8897 8898 return status; 8899 } 8900 8901 /* 8902 * qla24xx_get_fcp_prio 8903 * Gets the fcp cmd priority value for the logged in port. 8904 * Looks for a match of the port descriptors within 8905 * each of the fcp prio config entries. If a match is found, 8906 * the tag (priority) value is returned. 8907 * 8908 * Input: 8909 * vha = scsi host structure pointer. 8910 * fcport = port structure pointer. 8911 * 8912 * Return: 8913 * non-zero (if found) 8914 * -1 (if not found) 8915 * 8916 * Context: 8917 * Kernel context 8918 */ 8919 static int 8920 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 8921 { 8922 int i, entries; 8923 uint8_t pid_match, wwn_match; 8924 int priority; 8925 uint32_t pid1, pid2; 8926 uint64_t wwn1, wwn2; 8927 struct qla_fcp_prio_entry *pri_entry; 8928 struct qla_hw_data *ha = vha->hw; 8929 8930 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 8931 return -1; 8932 8933 priority = -1; 8934 entries = ha->fcp_prio_cfg->num_entries; 8935 pri_entry = &ha->fcp_prio_cfg->entry[0]; 8936 8937 for (i = 0; i < entries; i++) { 8938 pid_match = wwn_match = 0; 8939 8940 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 8941 pri_entry++; 8942 continue; 8943 } 8944 8945 /* check source pid for a match */ 8946 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 8947 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 8948 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 8949 if (pid1 == INVALID_PORT_ID) 8950 pid_match++; 8951 else if (pid1 == pid2) 8952 pid_match++; 8953 } 8954 8955 /* check destination pid for a match */ 8956 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 8957 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 8958 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 8959 if (pid1 == INVALID_PORT_ID) 8960 pid_match++; 8961 else if (pid1 == pid2) 8962 pid_match++; 8963 } 8964 8965 /* check source WWN for a match */ 8966 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 8967 wwn1 = wwn_to_u64(vha->port_name); 8968 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 8969 if (wwn2 == (uint64_t)-1) 8970 wwn_match++; 8971 else if (wwn1 == wwn2) 8972 wwn_match++; 8973 } 8974 8975 /* check destination WWN for a match */ 8976 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 8977 wwn1 = wwn_to_u64(fcport->port_name); 8978 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 8979 if (wwn2 == (uint64_t)-1) 8980 wwn_match++; 8981 else if (wwn1 == wwn2) 8982 wwn_match++; 8983 } 8984 8985 if (pid_match == 2 || wwn_match == 2) { 8986 /* Found a matching entry */ 8987 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 8988 priority = pri_entry->tag; 8989 break; 8990 } 8991 8992 pri_entry++; 8993 } 8994 8995 return priority; 8996 } 8997 8998 /* 8999 * qla24xx_update_fcport_fcp_prio 9000 * Activates fcp priority for the logged in fc port 9001 * 9002 * Input: 9003 * vha = scsi host structure pointer. 9004 * fcp = port structure pointer. 9005 * 9006 * Return: 9007 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9008 * 9009 * Context: 9010 * Kernel context. 9011 */ 9012 int 9013 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 9014 { 9015 int ret; 9016 int priority; 9017 uint16_t mb[5]; 9018 9019 if (fcport->port_type != FCT_TARGET || 9020 fcport->loop_id == FC_NO_LOOP_ID) 9021 return QLA_FUNCTION_FAILED; 9022 9023 priority = qla24xx_get_fcp_prio(vha, fcport); 9024 if (priority < 0) 9025 return QLA_FUNCTION_FAILED; 9026 9027 if (IS_P3P_TYPE(vha->hw)) { 9028 fcport->fcp_prio = priority & 0xf; 9029 return QLA_SUCCESS; 9030 } 9031 9032 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 9033 if (ret == QLA_SUCCESS) { 9034 if (fcport->fcp_prio != priority) 9035 ql_dbg(ql_dbg_user, vha, 0x709e, 9036 "Updated FCP_CMND priority - value=%d loop_id=%d " 9037 "port_id=%02x%02x%02x.\n", priority, 9038 fcport->loop_id, fcport->d_id.b.domain, 9039 fcport->d_id.b.area, fcport->d_id.b.al_pa); 9040 fcport->fcp_prio = priority & 0xf; 9041 } else 9042 ql_dbg(ql_dbg_user, vha, 0x704f, 9043 "Unable to update FCP_CMND priority - ret=0x%x for " 9044 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 9045 fcport->d_id.b.domain, fcport->d_id.b.area, 9046 fcport->d_id.b.al_pa); 9047 return ret; 9048 } 9049 9050 /* 9051 * qla24xx_update_all_fcp_prio 9052 * Activates fcp priority for all the logged in ports 9053 * 9054 * Input: 9055 * ha = adapter block pointer. 9056 * 9057 * Return: 9058 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9059 * 9060 * Context: 9061 * Kernel context. 9062 */ 9063 int 9064 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 9065 { 9066 int ret; 9067 fc_port_t *fcport; 9068 9069 ret = QLA_FUNCTION_FAILED; 9070 /* We need to set priority for all logged in ports */ 9071 list_for_each_entry(fcport, &vha->vp_fcports, list) 9072 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 9073 9074 return ret; 9075 } 9076 9077 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, 9078 int vp_idx, bool startqp) 9079 { 9080 int rsp_id = 0; 9081 int req_id = 0; 9082 int i; 9083 struct qla_hw_data *ha = vha->hw; 9084 uint16_t qpair_id = 0; 9085 struct qla_qpair *qpair = NULL; 9086 struct qla_msix_entry *msix; 9087 9088 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 9089 ql_log(ql_log_warn, vha, 0x00181, 9090 "FW/Driver is not multi-queue capable.\n"); 9091 return NULL; 9092 } 9093 9094 if (ql2xmqsupport || ql2xnvmeenable) { 9095 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 9096 if (qpair == NULL) { 9097 ql_log(ql_log_warn, vha, 0x0182, 9098 "Failed to allocate memory for queue pair.\n"); 9099 return NULL; 9100 } 9101 9102 qpair->hw = vha->hw; 9103 qpair->vha = vha; 9104 qpair->qp_lock_ptr = &qpair->qp_lock; 9105 spin_lock_init(&qpair->qp_lock); 9106 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 9107 9108 /* Assign available que pair id */ 9109 mutex_lock(&ha->mq_lock); 9110 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 9111 if (ha->num_qpairs >= ha->max_qpairs) { 9112 mutex_unlock(&ha->mq_lock); 9113 ql_log(ql_log_warn, vha, 0x0183, 9114 "No resources to create additional q pair.\n"); 9115 goto fail_qid_map; 9116 } 9117 ha->num_qpairs++; 9118 set_bit(qpair_id, ha->qpair_qid_map); 9119 ha->queue_pair_map[qpair_id] = qpair; 9120 qpair->id = qpair_id; 9121 qpair->vp_idx = vp_idx; 9122 qpair->fw_started = ha->flags.fw_started; 9123 INIT_LIST_HEAD(&qpair->hints_list); 9124 qpair->chip_reset = ha->base_qpair->chip_reset; 9125 qpair->enable_class_2 = ha->base_qpair->enable_class_2; 9126 qpair->enable_explicit_conf = 9127 ha->base_qpair->enable_explicit_conf; 9128 9129 for (i = 0; i < ha->msix_count; i++) { 9130 msix = &ha->msix_entries[i]; 9131 if (msix->in_use) 9132 continue; 9133 qpair->msix = msix; 9134 ql_dbg(ql_dbg_multiq, vha, 0xc00f, 9135 "Vector %x selected for qpair\n", msix->vector); 9136 break; 9137 } 9138 if (!qpair->msix) { 9139 ql_log(ql_log_warn, vha, 0x0184, 9140 "Out of MSI-X vectors!.\n"); 9141 goto fail_msix; 9142 } 9143 9144 qpair->msix->in_use = 1; 9145 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 9146 qpair->pdev = ha->pdev; 9147 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 9148 qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 9149 9150 mutex_unlock(&ha->mq_lock); 9151 9152 /* Create response queue first */ 9153 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp); 9154 if (!rsp_id) { 9155 ql_log(ql_log_warn, vha, 0x0185, 9156 "Failed to create response queue.\n"); 9157 goto fail_rsp; 9158 } 9159 9160 qpair->rsp = ha->rsp_q_map[rsp_id]; 9161 9162 /* Create request queue */ 9163 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos, 9164 startqp); 9165 if (!req_id) { 9166 ql_log(ql_log_warn, vha, 0x0186, 9167 "Failed to create request queue.\n"); 9168 goto fail_req; 9169 } 9170 9171 qpair->req = ha->req_q_map[req_id]; 9172 qpair->rsp->req = qpair->req; 9173 qpair->rsp->qpair = qpair; 9174 /* init qpair to this cpu. Will adjust at run time. */ 9175 qla_cpu_update(qpair, smp_processor_id()); 9176 9177 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 9178 if (ha->fw_attributes & BIT_4) 9179 qpair->difdix_supported = 1; 9180 } 9181 9182 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 9183 if (!qpair->srb_mempool) { 9184 ql_log(ql_log_warn, vha, 0xd036, 9185 "Failed to create srb mempool for qpair %d\n", 9186 qpair->id); 9187 goto fail_mempool; 9188 } 9189 9190 /* Mark as online */ 9191 qpair->online = 1; 9192 9193 if (!vha->flags.qpairs_available) 9194 vha->flags.qpairs_available = 1; 9195 9196 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 9197 "Request/Response queue pair created, id %d\n", 9198 qpair->id); 9199 ql_dbg(ql_dbg_init, vha, 0x0187, 9200 "Request/Response queue pair created, id %d\n", 9201 qpair->id); 9202 } 9203 return qpair; 9204 9205 fail_mempool: 9206 fail_req: 9207 qla25xx_delete_rsp_que(vha, qpair->rsp); 9208 fail_rsp: 9209 mutex_lock(&ha->mq_lock); 9210 qpair->msix->in_use = 0; 9211 list_del(&qpair->qp_list_elem); 9212 if (list_empty(&vha->qp_list)) 9213 vha->flags.qpairs_available = 0; 9214 fail_msix: 9215 ha->queue_pair_map[qpair_id] = NULL; 9216 clear_bit(qpair_id, ha->qpair_qid_map); 9217 ha->num_qpairs--; 9218 mutex_unlock(&ha->mq_lock); 9219 fail_qid_map: 9220 kfree(qpair); 9221 return NULL; 9222 } 9223 9224 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 9225 { 9226 int ret = QLA_FUNCTION_FAILED; 9227 struct qla_hw_data *ha = qpair->hw; 9228 9229 qpair->delete_in_progress = 1; 9230 9231 ret = qla25xx_delete_req_que(vha, qpair->req); 9232 if (ret != QLA_SUCCESS) 9233 goto fail; 9234 9235 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 9236 if (ret != QLA_SUCCESS) 9237 goto fail; 9238 9239 mutex_lock(&ha->mq_lock); 9240 ha->queue_pair_map[qpair->id] = NULL; 9241 clear_bit(qpair->id, ha->qpair_qid_map); 9242 ha->num_qpairs--; 9243 list_del(&qpair->qp_list_elem); 9244 if (list_empty(&vha->qp_list)) { 9245 vha->flags.qpairs_available = 0; 9246 vha->flags.qpairs_req_created = 0; 9247 vha->flags.qpairs_rsp_created = 0; 9248 } 9249 mempool_destroy(qpair->srb_mempool); 9250 kfree(qpair); 9251 mutex_unlock(&ha->mq_lock); 9252 9253 return QLA_SUCCESS; 9254 fail: 9255 return ret; 9256 } 9257 9258 uint64_t 9259 qla2x00_count_set_bits(uint32_t num) 9260 { 9261 /* Brian Kernighan's Algorithm */ 9262 u64 count = 0; 9263 9264 while (num) { 9265 num &= (num - 1); 9266 count++; 9267 } 9268 return count; 9269 } 9270 9271 uint64_t 9272 qla2x00_get_num_tgts(scsi_qla_host_t *vha) 9273 { 9274 fc_port_t *f, *tf; 9275 u64 count = 0; 9276 9277 f = NULL; 9278 tf = NULL; 9279 9280 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) { 9281 if (f->port_type != FCT_TARGET) 9282 continue; 9283 count++; 9284 } 9285 return count; 9286 } 9287 9288 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags) 9289 { 9290 scsi_qla_host_t *vha = shost_priv(host); 9291 fc_port_t *fcport = NULL; 9292 unsigned long int_flags; 9293 9294 if (flags & QLA2XX_HW_ERROR) 9295 vha->hw_err_cnt = 0; 9296 if (flags & QLA2XX_SHT_LNK_DWN) 9297 vha->short_link_down_cnt = 0; 9298 if (flags & QLA2XX_INT_ERR) 9299 vha->interface_err_cnt = 0; 9300 if (flags & QLA2XX_CMD_TIMEOUT) 9301 vha->cmd_timeout_cnt = 0; 9302 if (flags & QLA2XX_RESET_CMD_ERR) 9303 vha->reset_cmd_err_cnt = 0; 9304 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9305 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9306 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9307 fcport->tgt_short_link_down_cnt = 0; 9308 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9309 } 9310 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9311 } 9312 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9313 return 0; 9314 } 9315 9316 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags) 9317 { 9318 return qla2xxx_reset_stats(host, flags); 9319 } 9320 9321 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags) 9322 { 9323 return qla2xxx_reset_stats(host, flags); 9324 } 9325 9326 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags, 9327 void *data, u64 size) 9328 { 9329 scsi_qla_host_t *vha = shost_priv(host); 9330 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data; 9331 struct ql_vnd_stats *rsp_data = &resp->stats; 9332 u64 ini_entry_count = 0; 9333 u64 i = 0; 9334 u64 entry_count = 0; 9335 u64 num_tgt = 0; 9336 u32 tmp_stat_type = 0; 9337 fc_port_t *fcport = NULL; 9338 unsigned long int_flags; 9339 9340 /* Copy stat type to work on it */ 9341 tmp_stat_type = flags; 9342 9343 if (tmp_stat_type & BIT_17) { 9344 num_tgt = qla2x00_get_num_tgts(vha); 9345 /* unset BIT_17 */ 9346 tmp_stat_type &= ~(1 << 17); 9347 } 9348 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type); 9349 9350 entry_count = ini_entry_count + num_tgt; 9351 9352 rsp_data->entry_count = entry_count; 9353 9354 i = 0; 9355 if (flags & QLA2XX_HW_ERROR) { 9356 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR; 9357 rsp_data->entry[i].tgt_num = 0x0; 9358 rsp_data->entry[i].cnt = vha->hw_err_cnt; 9359 i++; 9360 } 9361 9362 if (flags & QLA2XX_SHT_LNK_DWN) { 9363 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN; 9364 rsp_data->entry[i].tgt_num = 0x0; 9365 rsp_data->entry[i].cnt = vha->short_link_down_cnt; 9366 i++; 9367 } 9368 9369 if (flags & QLA2XX_INT_ERR) { 9370 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR; 9371 rsp_data->entry[i].tgt_num = 0x0; 9372 rsp_data->entry[i].cnt = vha->interface_err_cnt; 9373 i++; 9374 } 9375 9376 if (flags & QLA2XX_CMD_TIMEOUT) { 9377 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT; 9378 rsp_data->entry[i].tgt_num = 0x0; 9379 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt; 9380 i++; 9381 } 9382 9383 if (flags & QLA2XX_RESET_CMD_ERR) { 9384 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR; 9385 rsp_data->entry[i].tgt_num = 0x0; 9386 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt; 9387 i++; 9388 } 9389 9390 /* i will continue from previous loop, as target 9391 * entries are after initiator 9392 */ 9393 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9394 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9395 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9396 if (fcport->port_type != FCT_TARGET) 9397 continue; 9398 if (!fcport->rport) 9399 continue; 9400 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN; 9401 rsp_data->entry[i].tgt_num = fcport->rport->number; 9402 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt; 9403 i++; 9404 } 9405 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9406 } 9407 resp->status = EXT_STATUS_OK; 9408 9409 return 0; 9410 } 9411 9412 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags, 9413 struct fc_rport *rport, void *data, u64 size) 9414 { 9415 struct ql_vnd_tgt_stats_resp *tgt_data = data; 9416 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 9417 9418 tgt_data->status = 0; 9419 tgt_data->stats.entry_count = 1; 9420 tgt_data->stats.entry[0].stat_type = flags; 9421 tgt_data->stats.entry[0].tgt_num = rport->number; 9422 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt; 9423 9424 return 0; 9425 } 9426 9427 int qla2xxx_disable_port(struct Scsi_Host *host) 9428 { 9429 scsi_qla_host_t *vha = shost_priv(host); 9430 9431 vha->hw->flags.port_isolated = 1; 9432 9433 if (qla2x00_chip_is_down(vha)) 9434 return 0; 9435 9436 if (vha->flags.online) { 9437 qla2x00_abort_isp_cleanup(vha); 9438 qla2x00_wait_for_sess_deletion(vha); 9439 } 9440 9441 return 0; 9442 } 9443 9444 int qla2xxx_enable_port(struct Scsi_Host *host) 9445 { 9446 scsi_qla_host_t *vha = shost_priv(host); 9447 9448 vha->hw->flags.port_isolated = 0; 9449 /* Set the flag to 1, so that isp_abort can proceed */ 9450 vha->flags.online = 1; 9451 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 9452 qla2xxx_wake_dpc(vha); 9453 9454 return 0; 9455 } 9456