1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 /* 59 * Data bit definitions 60 */ 61 #define BIT_0 0x1 62 #define BIT_1 0x2 63 #define BIT_2 0x4 64 #define BIT_3 0x8 65 #define BIT_4 0x10 66 #define BIT_5 0x20 67 #define BIT_6 0x40 68 #define BIT_7 0x80 69 #define BIT_8 0x100 70 #define BIT_9 0x200 71 #define BIT_10 0x400 72 #define BIT_11 0x800 73 #define BIT_12 0x1000 74 #define BIT_13 0x2000 75 #define BIT_14 0x4000 76 #define BIT_15 0x8000 77 #define BIT_16 0x10000 78 #define BIT_17 0x20000 79 #define BIT_18 0x40000 80 #define BIT_19 0x80000 81 #define BIT_20 0x100000 82 #define BIT_21 0x200000 83 #define BIT_22 0x400000 84 #define BIT_23 0x800000 85 #define BIT_24 0x1000000 86 #define BIT_25 0x2000000 87 #define BIT_26 0x4000000 88 #define BIT_27 0x8000000 89 #define BIT_28 0x10000000 90 #define BIT_29 0x20000000 91 #define BIT_30 0x40000000 92 #define BIT_31 0x80000000 93 94 #define LSB(x) ((uint8_t)(x)) 95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 96 97 #define LSW(x) ((uint16_t)(x)) 98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 99 100 #define LSD(x) ((uint32_t)((uint64_t)(x))) 101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 102 103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 104 105 /* 106 * I/O register 107 */ 108 109 #define RD_REG_BYTE(addr) readb(addr) 110 #define RD_REG_WORD(addr) readw(addr) 111 #define RD_REG_DWORD(addr) readl(addr) 112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 115 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 116 #define WRT_REG_WORD(addr, data) writew(data,addr) 117 #define WRT_REG_DWORD(addr, data) writel(data,addr) 118 119 /* 120 * ISP83XX specific remote register addresses 121 */ 122 #define QLA83XX_LED_PORT0 0x00201320 123 #define QLA83XX_LED_PORT1 0x00201328 124 #define QLA83XX_IDC_DEV_STATE 0x22102384 125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 129 #define QLA83XX_IDC_CONTROL 0x22102390 130 #define QLA83XX_IDC_AUDIT 0x22102394 131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 132 #define QLA83XX_DRIVER_LOCKID 0x22102104 133 #define QLA83XX_DRIVER_LOCK 0x8111c028 134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 135 #define QLA83XX_FLASH_LOCKID 0x22102100 136 #define QLA83XX_FLASH_LOCK 0x8111c010 137 #define QLA83XX_FLASH_UNLOCK 0x8111c014 138 #define QLA83XX_DEV_PARTINFO1 0x221023e0 139 #define QLA83XX_DEV_PARTINFO2 0x221023e4 140 #define QLA83XX_FW_HEARTBEAT 0x221020b0 141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 143 144 /* 83XX: Macros defining 8200 AEN Reason codes */ 145 #define IDC_DEVICE_STATE_CHANGE BIT_0 146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 148 #define IDC_HEARTBEAT_FAILURE BIT_3 149 150 /* 83XX: Macros defining 8200 AEN Error-levels */ 151 #define ERR_LEVEL_NON_FATAL 0x1 152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 154 155 /* 83XX: Macros for IDC Version */ 156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 158 159 /* 83XX: Macros for scheduling dpc tasks */ 160 #define QLA83XX_NIC_CORE_RESET 0x1 161 #define QLA83XX_IDC_STATE_HANDLER 0x2 162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 163 164 /* 83XX: Macros for defining IDC-Control bits */ 165 #define QLA83XX_IDC_RESET_DISABLED BIT_0 166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 167 168 /* 83XX: Macros for different timeouts */ 169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 172 173 /* 83XX: Macros for defining class in DEV-Partition Info register */ 174 #define QLA83XX_CLASS_TYPE_NONE 0x0 175 #define QLA83XX_CLASS_TYPE_NIC 0x1 176 #define QLA83XX_CLASS_TYPE_FCOE 0x2 177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 178 179 /* 83XX: Macros for IDC Lock-Recovery stages */ 180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 181 * lock-recovery 182 */ 183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 184 185 /* 83XX: Macros for IDC Audit type */ 186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 187 * dev-state change to NEED-RESET 188 * or NEED-QUIESCENT 189 */ 190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 191 * reset-recovery completion is 192 * second 193 */ 194 /* ISP2031: Values for laser on/off */ 195 #define PORT_0_2031 0x00201340 196 #define PORT_1_2031 0x00201350 197 #define LASER_ON_2031 0x01800100 198 #define LASER_OFF_2031 0x01800180 199 200 /* 201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 202 * 133Mhz slot. 203 */ 204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 206 207 /* 208 * Fibre Channel device definitions. 209 */ 210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 211 #define MAX_FIBRE_DEVICES_2100 512 212 #define MAX_FIBRE_DEVICES_2400 2048 213 #define MAX_FIBRE_DEVICES_LOOP 128 214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 216 #define MAX_FIBRE_LUNS 0xFFFF 217 #define MAX_HOST_COUNT 16 218 219 /* 220 * Host adapter default definitions. 221 */ 222 #define MAX_BUSES 1 /* We only have one bus today */ 223 #define MIN_LUNS 8 224 #define MAX_LUNS MAX_FIBRE_LUNS 225 #define MAX_CMDS_PER_LUN 255 226 227 /* 228 * Fibre Channel device definitions. 229 */ 230 #define SNS_LAST_LOOP_ID_2100 0xfe 231 #define SNS_LAST_LOOP_ID_2300 0x7ff 232 233 #define LAST_LOCAL_LOOP_ID 0x7d 234 #define SNS_FL_PORT 0x7e 235 #define FABRIC_CONTROLLER 0x7f 236 #define SIMPLE_NAME_SERVER 0x80 237 #define SNS_FIRST_LOOP_ID 0x81 238 #define MANAGEMENT_SERVER 0xfe 239 #define BROADCAST 0xff 240 241 /* 242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 243 * valid range of an N-PORT id is 0 through 0x7ef. 244 */ 245 #define NPH_LAST_HANDLE 0x7ef 246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 247 #define NPH_SNS 0x7fc /* FFFFFC */ 248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 249 #define NPH_F_PORT 0x7fe /* FFFFFE */ 250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 251 252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 253 #include "qla_fw.h" 254 /* 255 * Timeout timer counts in seconds 256 */ 257 #define PORT_RETRY_TIME 1 258 #define LOOP_DOWN_TIMEOUT 60 259 #define LOOP_DOWN_TIME 255 /* 240 */ 260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 261 262 #define DEFAULT_OUTSTANDING_COMMANDS 1024 263 #define MIN_OUTSTANDING_COMMANDS 128 264 265 /* ISP request and response entry counts (37-65535) */ 266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 270 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 271 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 272 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 273 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 274 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 275 276 struct req_que; 277 278 /* 279 * (sd.h is not exported, hence local inclusion) 280 * Data Integrity Field tuple. 281 */ 282 struct sd_dif_tuple { 283 __be16 guard_tag; /* Checksum */ 284 __be16 app_tag; /* Opaque storage */ 285 __be32 ref_tag; /* Target LBA or indirect LBA */ 286 }; 287 288 /* 289 * SCSI Request Block 290 */ 291 struct srb_cmd { 292 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 293 uint32_t request_sense_length; 294 uint32_t fw_sense_length; 295 uint8_t *request_sense_ptr; 296 void *ctx; 297 }; 298 299 /* 300 * SRB flag definitions 301 */ 302 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 303 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 304 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 305 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 306 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 307 308 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 309 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 310 311 /* 312 * SRB extensions. 313 */ 314 struct srb_iocb { 315 union { 316 struct { 317 uint16_t flags; 318 #define SRB_LOGIN_RETRIED BIT_0 319 #define SRB_LOGIN_COND_PLOGI BIT_1 320 #define SRB_LOGIN_SKIP_PRLI BIT_2 321 uint16_t data[2]; 322 } logio; 323 struct { 324 /* 325 * Values for flags field below are as 326 * defined in tsk_mgmt_entry struct 327 * for control_flags field in qla_fw.h. 328 */ 329 uint64_t lun; 330 uint32_t flags; 331 uint32_t data; 332 struct completion comp; 333 __le16 comp_status; 334 } tmf; 335 struct { 336 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 337 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 338 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 339 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 340 #define FXDISC_TIMEOUT 20 341 uint8_t flags; 342 uint32_t req_len; 343 uint32_t rsp_len; 344 void *req_addr; 345 void *rsp_addr; 346 dma_addr_t req_dma_handle; 347 dma_addr_t rsp_dma_handle; 348 __le32 adapter_id; 349 __le32 adapter_id_hi; 350 __le16 req_func_type; 351 __le32 req_data; 352 __le32 req_data_extra; 353 __le32 result; 354 __le32 seq_number; 355 __le16 fw_flags; 356 struct completion fxiocb_comp; 357 __le32 reserved_0; 358 uint8_t reserved_1; 359 } fxiocb; 360 struct { 361 uint32_t cmd_hndl; 362 __le16 comp_status; 363 struct completion comp; 364 } abt; 365 } u; 366 367 struct timer_list timer; 368 void (*timeout)(void *); 369 }; 370 371 /* Values for srb_ctx type */ 372 #define SRB_LOGIN_CMD 1 373 #define SRB_LOGOUT_CMD 2 374 #define SRB_ELS_CMD_RPT 3 375 #define SRB_ELS_CMD_HST 4 376 #define SRB_CT_CMD 5 377 #define SRB_ADISC_CMD 6 378 #define SRB_TM_CMD 7 379 #define SRB_SCSI_CMD 8 380 #define SRB_BIDI_CMD 9 381 #define SRB_FXIOCB_DCMD 10 382 #define SRB_FXIOCB_BCMD 11 383 #define SRB_ABT_CMD 12 384 385 386 typedef struct srb { 387 atomic_t ref_count; 388 struct fc_port *fcport; 389 uint32_t handle; 390 uint16_t flags; 391 uint16_t type; 392 char *name; 393 int iocbs; 394 union { 395 struct srb_iocb iocb_cmd; 396 struct fc_bsg_job *bsg_job; 397 struct srb_cmd scmd; 398 } u; 399 void (*done)(void *, void *, int); 400 void (*free)(void *, void *); 401 } srb_t; 402 403 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 404 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 405 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 406 407 #define GET_CMD_SENSE_LEN(sp) \ 408 (sp->u.scmd.request_sense_length) 409 #define SET_CMD_SENSE_LEN(sp, len) \ 410 (sp->u.scmd.request_sense_length = len) 411 #define GET_CMD_SENSE_PTR(sp) \ 412 (sp->u.scmd.request_sense_ptr) 413 #define SET_CMD_SENSE_PTR(sp, ptr) \ 414 (sp->u.scmd.request_sense_ptr = ptr) 415 #define GET_FW_SENSE_LEN(sp) \ 416 (sp->u.scmd.fw_sense_length) 417 #define SET_FW_SENSE_LEN(sp, len) \ 418 (sp->u.scmd.fw_sense_length = len) 419 420 struct msg_echo_lb { 421 dma_addr_t send_dma; 422 dma_addr_t rcv_dma; 423 uint16_t req_sg_cnt; 424 uint16_t rsp_sg_cnt; 425 uint16_t options; 426 uint32_t transfer_size; 427 uint32_t iteration_count; 428 }; 429 430 /* 431 * ISP I/O Register Set structure definitions. 432 */ 433 struct device_reg_2xxx { 434 uint16_t flash_address; /* Flash BIOS address */ 435 uint16_t flash_data; /* Flash BIOS data */ 436 uint16_t unused_1[1]; /* Gap */ 437 uint16_t ctrl_status; /* Control/Status */ 438 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 439 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 440 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 441 442 uint16_t ictrl; /* Interrupt control */ 443 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 444 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 445 446 uint16_t istatus; /* Interrupt status */ 447 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 448 449 uint16_t semaphore; /* Semaphore */ 450 uint16_t nvram; /* NVRAM register. */ 451 #define NVR_DESELECT 0 452 #define NVR_BUSY BIT_15 453 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 454 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 455 #define NVR_DATA_IN BIT_3 456 #define NVR_DATA_OUT BIT_2 457 #define NVR_SELECT BIT_1 458 #define NVR_CLOCK BIT_0 459 460 #define NVR_WAIT_CNT 20000 461 462 union { 463 struct { 464 uint16_t mailbox0; 465 uint16_t mailbox1; 466 uint16_t mailbox2; 467 uint16_t mailbox3; 468 uint16_t mailbox4; 469 uint16_t mailbox5; 470 uint16_t mailbox6; 471 uint16_t mailbox7; 472 uint16_t unused_2[59]; /* Gap */ 473 } __attribute__((packed)) isp2100; 474 struct { 475 /* Request Queue */ 476 uint16_t req_q_in; /* In-Pointer */ 477 uint16_t req_q_out; /* Out-Pointer */ 478 /* Response Queue */ 479 uint16_t rsp_q_in; /* In-Pointer */ 480 uint16_t rsp_q_out; /* Out-Pointer */ 481 482 /* RISC to Host Status */ 483 uint32_t host_status; 484 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 485 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 486 487 /* Host to Host Semaphore */ 488 uint16_t host_semaphore; 489 uint16_t unused_3[17]; /* Gap */ 490 uint16_t mailbox0; 491 uint16_t mailbox1; 492 uint16_t mailbox2; 493 uint16_t mailbox3; 494 uint16_t mailbox4; 495 uint16_t mailbox5; 496 uint16_t mailbox6; 497 uint16_t mailbox7; 498 uint16_t mailbox8; 499 uint16_t mailbox9; 500 uint16_t mailbox10; 501 uint16_t mailbox11; 502 uint16_t mailbox12; 503 uint16_t mailbox13; 504 uint16_t mailbox14; 505 uint16_t mailbox15; 506 uint16_t mailbox16; 507 uint16_t mailbox17; 508 uint16_t mailbox18; 509 uint16_t mailbox19; 510 uint16_t mailbox20; 511 uint16_t mailbox21; 512 uint16_t mailbox22; 513 uint16_t mailbox23; 514 uint16_t mailbox24; 515 uint16_t mailbox25; 516 uint16_t mailbox26; 517 uint16_t mailbox27; 518 uint16_t mailbox28; 519 uint16_t mailbox29; 520 uint16_t mailbox30; 521 uint16_t mailbox31; 522 uint16_t fb_cmd; 523 uint16_t unused_4[10]; /* Gap */ 524 } __attribute__((packed)) isp2300; 525 } u; 526 527 uint16_t fpm_diag_config; 528 uint16_t unused_5[0x4]; /* Gap */ 529 uint16_t risc_hw; 530 uint16_t unused_5_1; /* Gap */ 531 uint16_t pcr; /* Processor Control Register. */ 532 uint16_t unused_6[0x5]; /* Gap */ 533 uint16_t mctr; /* Memory Configuration and Timing. */ 534 uint16_t unused_7[0x3]; /* Gap */ 535 uint16_t fb_cmd_2100; /* Unused on 23XX */ 536 uint16_t unused_8[0x3]; /* Gap */ 537 uint16_t hccr; /* Host command & control register. */ 538 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 539 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 540 /* HCCR commands */ 541 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 542 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 543 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 544 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 545 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 546 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 547 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 548 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 549 550 uint16_t unused_9[5]; /* Gap */ 551 uint16_t gpiod; /* GPIO Data register. */ 552 uint16_t gpioe; /* GPIO Enable register. */ 553 #define GPIO_LED_MASK 0x00C0 554 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 555 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 556 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 557 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 558 #define GPIO_LED_ALL_OFF 0x0000 559 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 560 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 561 562 union { 563 struct { 564 uint16_t unused_10[8]; /* Gap */ 565 uint16_t mailbox8; 566 uint16_t mailbox9; 567 uint16_t mailbox10; 568 uint16_t mailbox11; 569 uint16_t mailbox12; 570 uint16_t mailbox13; 571 uint16_t mailbox14; 572 uint16_t mailbox15; 573 uint16_t mailbox16; 574 uint16_t mailbox17; 575 uint16_t mailbox18; 576 uint16_t mailbox19; 577 uint16_t mailbox20; 578 uint16_t mailbox21; 579 uint16_t mailbox22; 580 uint16_t mailbox23; /* Also probe reg. */ 581 } __attribute__((packed)) isp2200; 582 } u_end; 583 }; 584 585 struct device_reg_25xxmq { 586 uint32_t req_q_in; 587 uint32_t req_q_out; 588 uint32_t rsp_q_in; 589 uint32_t rsp_q_out; 590 uint32_t atio_q_in; 591 uint32_t atio_q_out; 592 }; 593 594 595 struct device_reg_fx00 { 596 uint32_t mailbox0; /* 00 */ 597 uint32_t mailbox1; /* 04 */ 598 uint32_t mailbox2; /* 08 */ 599 uint32_t mailbox3; /* 0C */ 600 uint32_t mailbox4; /* 10 */ 601 uint32_t mailbox5; /* 14 */ 602 uint32_t mailbox6; /* 18 */ 603 uint32_t mailbox7; /* 1C */ 604 uint32_t mailbox8; /* 20 */ 605 uint32_t mailbox9; /* 24 */ 606 uint32_t mailbox10; /* 28 */ 607 uint32_t mailbox11; 608 uint32_t mailbox12; 609 uint32_t mailbox13; 610 uint32_t mailbox14; 611 uint32_t mailbox15; 612 uint32_t mailbox16; 613 uint32_t mailbox17; 614 uint32_t mailbox18; 615 uint32_t mailbox19; 616 uint32_t mailbox20; 617 uint32_t mailbox21; 618 uint32_t mailbox22; 619 uint32_t mailbox23; 620 uint32_t mailbox24; 621 uint32_t mailbox25; 622 uint32_t mailbox26; 623 uint32_t mailbox27; 624 uint32_t mailbox28; 625 uint32_t mailbox29; 626 uint32_t mailbox30; 627 uint32_t mailbox31; 628 uint32_t aenmailbox0; 629 uint32_t aenmailbox1; 630 uint32_t aenmailbox2; 631 uint32_t aenmailbox3; 632 uint32_t aenmailbox4; 633 uint32_t aenmailbox5; 634 uint32_t aenmailbox6; 635 uint32_t aenmailbox7; 636 /* Request Queue. */ 637 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 638 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 639 /* Response Queue. */ 640 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 641 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 642 /* Init values shadowed on FW Up Event */ 643 uint32_t initval0; /* B0 */ 644 uint32_t initval1; /* B4 */ 645 uint32_t initval2; /* B8 */ 646 uint32_t initval3; /* BC */ 647 uint32_t initval4; /* C0 */ 648 uint32_t initval5; /* C4 */ 649 uint32_t initval6; /* C8 */ 650 uint32_t initval7; /* CC */ 651 uint32_t fwheartbeat; /* D0 */ 652 uint32_t pseudoaen; /* D4 */ 653 }; 654 655 656 657 typedef union { 658 struct device_reg_2xxx isp; 659 struct device_reg_24xx isp24; 660 struct device_reg_25xxmq isp25mq; 661 struct device_reg_82xx isp82; 662 struct device_reg_fx00 ispfx00; 663 } __iomem device_reg_t; 664 665 #define ISP_REQ_Q_IN(ha, reg) \ 666 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 667 &(reg)->u.isp2100.mailbox4 : \ 668 &(reg)->u.isp2300.req_q_in) 669 #define ISP_REQ_Q_OUT(ha, reg) \ 670 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 671 &(reg)->u.isp2100.mailbox4 : \ 672 &(reg)->u.isp2300.req_q_out) 673 #define ISP_RSP_Q_IN(ha, reg) \ 674 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 675 &(reg)->u.isp2100.mailbox5 : \ 676 &(reg)->u.isp2300.rsp_q_in) 677 #define ISP_RSP_Q_OUT(ha, reg) \ 678 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 679 &(reg)->u.isp2100.mailbox5 : \ 680 &(reg)->u.isp2300.rsp_q_out) 681 682 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 683 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 684 685 #define MAILBOX_REG(ha, reg, num) \ 686 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 687 (num < 8 ? \ 688 &(reg)->u.isp2100.mailbox0 + (num) : \ 689 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 690 &(reg)->u.isp2300.mailbox0 + (num)) 691 #define RD_MAILBOX_REG(ha, reg, num) \ 692 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 693 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 694 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 695 696 #define FB_CMD_REG(ha, reg) \ 697 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 698 &(reg)->fb_cmd_2100 : \ 699 &(reg)->u.isp2300.fb_cmd) 700 #define RD_FB_CMD_REG(ha, reg) \ 701 RD_REG_WORD(FB_CMD_REG(ha, reg)) 702 #define WRT_FB_CMD_REG(ha, reg, data) \ 703 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 704 705 typedef struct { 706 uint32_t out_mb; /* outbound from driver */ 707 uint32_t in_mb; /* Incoming from RISC */ 708 uint16_t mb[MAILBOX_REGISTER_COUNT]; 709 long buf_size; 710 void *bufp; 711 uint32_t tov; 712 uint8_t flags; 713 #define MBX_DMA_IN BIT_0 714 #define MBX_DMA_OUT BIT_1 715 #define IOCTL_CMD BIT_2 716 } mbx_cmd_t; 717 718 struct mbx_cmd_32 { 719 uint32_t out_mb; /* outbound from driver */ 720 uint32_t in_mb; /* Incoming from RISC */ 721 uint32_t mb[MAILBOX_REGISTER_COUNT]; 722 long buf_size; 723 void *bufp; 724 uint32_t tov; 725 uint8_t flags; 726 #define MBX_DMA_IN BIT_0 727 #define MBX_DMA_OUT BIT_1 728 #define IOCTL_CMD BIT_2 729 }; 730 731 732 #define MBX_TOV_SECONDS 30 733 734 /* 735 * ISP product identification definitions in mailboxes after reset. 736 */ 737 #define PROD_ID_1 0x4953 738 #define PROD_ID_2 0x0000 739 #define PROD_ID_2a 0x5020 740 #define PROD_ID_3 0x2020 741 742 /* 743 * ISP mailbox Self-Test status codes 744 */ 745 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 746 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 747 #define MBS_BUSY 4 /* Busy. */ 748 749 /* 750 * ISP mailbox command complete status codes 751 */ 752 #define MBS_COMMAND_COMPLETE 0x4000 753 #define MBS_INVALID_COMMAND 0x4001 754 #define MBS_HOST_INTERFACE_ERROR 0x4002 755 #define MBS_TEST_FAILED 0x4003 756 #define MBS_COMMAND_ERROR 0x4005 757 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 758 #define MBS_PORT_ID_USED 0x4007 759 #define MBS_LOOP_ID_USED 0x4008 760 #define MBS_ALL_IDS_IN_USE 0x4009 761 #define MBS_NOT_LOGGED_IN 0x400A 762 #define MBS_LINK_DOWN_ERROR 0x400B 763 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 764 765 /* 766 * ISP mailbox asynchronous event status codes 767 */ 768 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 769 #define MBA_RESET 0x8001 /* Reset Detected. */ 770 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 771 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 772 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 773 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 774 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 775 /* occurred. */ 776 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 777 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 778 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 779 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 780 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 781 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 782 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 783 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 784 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 785 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 786 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 787 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 788 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 789 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 790 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 791 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 792 /* used. */ 793 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 794 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 795 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 796 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 797 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 798 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 799 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 800 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 801 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 802 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 803 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 804 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 805 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 806 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 807 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 808 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 809 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 810 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 811 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 812 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 813 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 814 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 815 Notification */ 816 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 817 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 818 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 819 /* 83XX FCoE specific */ 820 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 821 822 /* Interrupt type codes */ 823 #define INTR_ROM_MB_SUCCESS 0x1 824 #define INTR_ROM_MB_FAILED 0x2 825 #define INTR_MB_SUCCESS 0x10 826 #define INTR_MB_FAILED 0x11 827 #define INTR_ASYNC_EVENT 0x12 828 #define INTR_RSP_QUE_UPDATE 0x13 829 #define INTR_RSP_QUE_UPDATE_83XX 0x14 830 #define INTR_ATIO_QUE_UPDATE 0x1C 831 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 832 833 /* ISP mailbox loopback echo diagnostic error code */ 834 #define MBS_LB_RESET 0x17 835 /* 836 * Firmware options 1, 2, 3. 837 */ 838 #define FO1_AE_ON_LIPF8 BIT_0 839 #define FO1_AE_ALL_LIP_RESET BIT_1 840 #define FO1_CTIO_RETRY BIT_3 841 #define FO1_DISABLE_LIP_F7_SW BIT_4 842 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 843 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 844 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 845 #define FO1_SET_EMPHASIS_SWING BIT_8 846 #define FO1_AE_AUTO_BYPASS BIT_9 847 #define FO1_ENABLE_PURE_IOCB BIT_10 848 #define FO1_AE_PLOGI_RJT BIT_11 849 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 850 #define FO1_AE_QUEUE_FULL BIT_13 851 852 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 853 #define FO2_REV_LOOPBACK BIT_1 854 855 #define FO3_ENABLE_EMERG_IOCB BIT_0 856 #define FO3_AE_RND_ERROR BIT_1 857 858 /* 24XX additional firmware options */ 859 #define ADD_FO_COUNT 3 860 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 861 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 862 863 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 864 865 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 866 867 /* 868 * ISP mailbox commands 869 */ 870 #define MBC_LOAD_RAM 1 /* Load RAM. */ 871 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 872 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 873 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 874 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 875 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 876 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 877 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 878 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 879 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 880 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 881 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 882 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 883 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 884 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 885 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 886 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 887 #define MBC_RESET 0x18 /* Reset. */ 888 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 889 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 890 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 891 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 892 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 893 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 894 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 895 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 896 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 897 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 898 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 899 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 900 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 901 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 902 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 903 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 904 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 905 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 906 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 907 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 908 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 909 #define MBC_DATA_RATE 0x5d /* Data Rate */ 910 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 911 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 912 /* Initialization Procedure */ 913 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 914 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 915 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 916 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 917 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 918 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 919 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 920 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 921 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 922 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 923 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 924 /* commandd. */ 925 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 926 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 927 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 928 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 929 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 930 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 931 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 932 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 933 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 934 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 935 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 936 937 /* 938 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 939 * should be defined with MBC_MR_* 940 */ 941 #define MBC_MR_DRV_SHUTDOWN 0x6A 942 943 /* 944 * ISP24xx mailbox commands 945 */ 946 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 947 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 948 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 949 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 950 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 951 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 952 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 953 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 954 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 955 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 956 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 957 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 958 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 959 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 960 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 961 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 962 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 963 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 964 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 965 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 966 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 967 #define MBC_PORT_RESET 0x120 /* Port Reset */ 968 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 969 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 970 971 /* 972 * ISP81xx mailbox commands 973 */ 974 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 975 976 /* 977 * ISP8044 mailbox commands 978 */ 979 #define MBC_SET_GET_ETH_SERDES_REG 0x150 980 #define HCS_WRITE_SERDES 0x3 981 #define HCS_READ_SERDES 0x4 982 983 /* Firmware return data sizes */ 984 #define FCAL_MAP_SIZE 128 985 986 /* Mailbox bit definitions for out_mb and in_mb */ 987 #define MBX_31 BIT_31 988 #define MBX_30 BIT_30 989 #define MBX_29 BIT_29 990 #define MBX_28 BIT_28 991 #define MBX_27 BIT_27 992 #define MBX_26 BIT_26 993 #define MBX_25 BIT_25 994 #define MBX_24 BIT_24 995 #define MBX_23 BIT_23 996 #define MBX_22 BIT_22 997 #define MBX_21 BIT_21 998 #define MBX_20 BIT_20 999 #define MBX_19 BIT_19 1000 #define MBX_18 BIT_18 1001 #define MBX_17 BIT_17 1002 #define MBX_16 BIT_16 1003 #define MBX_15 BIT_15 1004 #define MBX_14 BIT_14 1005 #define MBX_13 BIT_13 1006 #define MBX_12 BIT_12 1007 #define MBX_11 BIT_11 1008 #define MBX_10 BIT_10 1009 #define MBX_9 BIT_9 1010 #define MBX_8 BIT_8 1011 #define MBX_7 BIT_7 1012 #define MBX_6 BIT_6 1013 #define MBX_5 BIT_5 1014 #define MBX_4 BIT_4 1015 #define MBX_3 BIT_3 1016 #define MBX_2 BIT_2 1017 #define MBX_1 BIT_1 1018 #define MBX_0 BIT_0 1019 1020 #define RNID_TYPE_SET_VERSION 0x9 1021 #define RNID_TYPE_ASIC_TEMP 0xC 1022 1023 /* 1024 * Firmware state codes from get firmware state mailbox command 1025 */ 1026 #define FSTATE_CONFIG_WAIT 0 1027 #define FSTATE_WAIT_AL_PA 1 1028 #define FSTATE_WAIT_LOGIN 2 1029 #define FSTATE_READY 3 1030 #define FSTATE_LOSS_OF_SYNC 4 1031 #define FSTATE_ERROR 5 1032 #define FSTATE_REINIT 6 1033 #define FSTATE_NON_PART 7 1034 1035 #define FSTATE_CONFIG_CORRECT 0 1036 #define FSTATE_P2P_RCV_LIP 1 1037 #define FSTATE_P2P_CHOOSE_LOOP 2 1038 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1039 #define FSTATE_FATAL_ERROR 4 1040 #define FSTATE_LOOP_BACK_CONN 5 1041 1042 /* 1043 * Port Database structure definition 1044 * Little endian except where noted. 1045 */ 1046 #define PORT_DATABASE_SIZE 128 /* bytes */ 1047 typedef struct { 1048 uint8_t options; 1049 uint8_t control; 1050 uint8_t master_state; 1051 uint8_t slave_state; 1052 uint8_t reserved[2]; 1053 uint8_t hard_address; 1054 uint8_t reserved_1; 1055 uint8_t port_id[4]; 1056 uint8_t node_name[WWN_SIZE]; 1057 uint8_t port_name[WWN_SIZE]; 1058 uint16_t execution_throttle; 1059 uint16_t execution_count; 1060 uint8_t reset_count; 1061 uint8_t reserved_2; 1062 uint16_t resource_allocation; 1063 uint16_t current_allocation; 1064 uint16_t queue_head; 1065 uint16_t queue_tail; 1066 uint16_t transmit_execution_list_next; 1067 uint16_t transmit_execution_list_previous; 1068 uint16_t common_features; 1069 uint16_t total_concurrent_sequences; 1070 uint16_t RO_by_information_category; 1071 uint8_t recipient; 1072 uint8_t initiator; 1073 uint16_t receive_data_size; 1074 uint16_t concurrent_sequences; 1075 uint16_t open_sequences_per_exchange; 1076 uint16_t lun_abort_flags; 1077 uint16_t lun_stop_flags; 1078 uint16_t stop_queue_head; 1079 uint16_t stop_queue_tail; 1080 uint16_t port_retry_timer; 1081 uint16_t next_sequence_id; 1082 uint16_t frame_count; 1083 uint16_t PRLI_payload_length; 1084 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1085 /* Bits 15-0 of word 0 */ 1086 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1087 /* Bits 15-0 of word 3 */ 1088 uint16_t loop_id; 1089 uint16_t extended_lun_info_list_pointer; 1090 uint16_t extended_lun_stop_list_pointer; 1091 } port_database_t; 1092 1093 /* 1094 * Port database slave/master states 1095 */ 1096 #define PD_STATE_DISCOVERY 0 1097 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1098 #define PD_STATE_PORT_LOGIN 2 1099 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1100 #define PD_STATE_PROCESS_LOGIN 4 1101 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1102 #define PD_STATE_PORT_LOGGED_IN 6 1103 #define PD_STATE_PORT_UNAVAILABLE 7 1104 #define PD_STATE_PROCESS_LOGOUT 8 1105 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1106 #define PD_STATE_PORT_LOGOUT 10 1107 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1108 1109 1110 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1111 #define QLA_ZIO_DISABLED 0 1112 #define QLA_ZIO_DEFAULT_TIMER 2 1113 1114 /* 1115 * ISP Initialization Control Block. 1116 * Little endian except where noted. 1117 */ 1118 #define ICB_VERSION 1 1119 typedef struct { 1120 uint8_t version; 1121 uint8_t reserved_1; 1122 1123 /* 1124 * LSB BIT 0 = Enable Hard Loop Id 1125 * LSB BIT 1 = Enable Fairness 1126 * LSB BIT 2 = Enable Full-Duplex 1127 * LSB BIT 3 = Enable Fast Posting 1128 * LSB BIT 4 = Enable Target Mode 1129 * LSB BIT 5 = Disable Initiator Mode 1130 * LSB BIT 6 = Enable ADISC 1131 * LSB BIT 7 = Enable Target Inquiry Data 1132 * 1133 * MSB BIT 0 = Enable PDBC Notify 1134 * MSB BIT 1 = Non Participating LIP 1135 * MSB BIT 2 = Descending Loop ID Search 1136 * MSB BIT 3 = Acquire Loop ID in LIPA 1137 * MSB BIT 4 = Stop PortQ on Full Status 1138 * MSB BIT 5 = Full Login after LIP 1139 * MSB BIT 6 = Node Name Option 1140 * MSB BIT 7 = Ext IFWCB enable bit 1141 */ 1142 uint8_t firmware_options[2]; 1143 1144 uint16_t frame_payload_size; 1145 uint16_t max_iocb_allocation; 1146 uint16_t execution_throttle; 1147 uint8_t retry_count; 1148 uint8_t retry_delay; /* unused */ 1149 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1150 uint16_t hard_address; 1151 uint8_t inquiry_data; 1152 uint8_t login_timeout; 1153 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1154 1155 uint16_t request_q_outpointer; 1156 uint16_t response_q_inpointer; 1157 uint16_t request_q_length; 1158 uint16_t response_q_length; 1159 uint32_t request_q_address[2]; 1160 uint32_t response_q_address[2]; 1161 1162 uint16_t lun_enables; 1163 uint8_t command_resource_count; 1164 uint8_t immediate_notify_resource_count; 1165 uint16_t timeout; 1166 uint8_t reserved_2[2]; 1167 1168 /* 1169 * LSB BIT 0 = Timer Operation mode bit 0 1170 * LSB BIT 1 = Timer Operation mode bit 1 1171 * LSB BIT 2 = Timer Operation mode bit 2 1172 * LSB BIT 3 = Timer Operation mode bit 3 1173 * LSB BIT 4 = Init Config Mode bit 0 1174 * LSB BIT 5 = Init Config Mode bit 1 1175 * LSB BIT 6 = Init Config Mode bit 2 1176 * LSB BIT 7 = Enable Non part on LIHA failure 1177 * 1178 * MSB BIT 0 = Enable class 2 1179 * MSB BIT 1 = Enable ACK0 1180 * MSB BIT 2 = 1181 * MSB BIT 3 = 1182 * MSB BIT 4 = FC Tape Enable 1183 * MSB BIT 5 = Enable FC Confirm 1184 * MSB BIT 6 = Enable command queuing in target mode 1185 * MSB BIT 7 = No Logo On Link Down 1186 */ 1187 uint8_t add_firmware_options[2]; 1188 1189 uint8_t response_accumulation_timer; 1190 uint8_t interrupt_delay_timer; 1191 1192 /* 1193 * LSB BIT 0 = Enable Read xfr_rdy 1194 * LSB BIT 1 = Soft ID only 1195 * LSB BIT 2 = 1196 * LSB BIT 3 = 1197 * LSB BIT 4 = FCP RSP Payload [0] 1198 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1199 * LSB BIT 6 = Enable Out-of-Order frame handling 1200 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1201 * 1202 * MSB BIT 0 = Sbus enable - 2300 1203 * MSB BIT 1 = 1204 * MSB BIT 2 = 1205 * MSB BIT 3 = 1206 * MSB BIT 4 = LED mode 1207 * MSB BIT 5 = enable 50 ohm termination 1208 * MSB BIT 6 = Data Rate (2300 only) 1209 * MSB BIT 7 = Data Rate (2300 only) 1210 */ 1211 uint8_t special_options[2]; 1212 1213 uint8_t reserved_3[26]; 1214 } init_cb_t; 1215 1216 /* 1217 * Get Link Status mailbox command return buffer. 1218 */ 1219 #define GLSO_SEND_RPS BIT_0 1220 #define GLSO_USE_DID BIT_3 1221 1222 struct link_statistics { 1223 uint32_t link_fail_cnt; 1224 uint32_t loss_sync_cnt; 1225 uint32_t loss_sig_cnt; 1226 uint32_t prim_seq_err_cnt; 1227 uint32_t inval_xmit_word_cnt; 1228 uint32_t inval_crc_cnt; 1229 uint32_t lip_cnt; 1230 uint32_t unused1[0x1a]; 1231 uint32_t tx_frames; 1232 uint32_t rx_frames; 1233 uint32_t discarded_frames; 1234 uint32_t dropped_frames; 1235 uint32_t unused2[1]; 1236 uint32_t nos_rcvd; 1237 }; 1238 1239 /* 1240 * NVRAM Command values. 1241 */ 1242 #define NV_START_BIT BIT_2 1243 #define NV_WRITE_OP (BIT_26+BIT_24) 1244 #define NV_READ_OP (BIT_26+BIT_25) 1245 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1246 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1247 #define NV_DELAY_COUNT 10 1248 1249 /* 1250 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1251 */ 1252 typedef struct { 1253 /* 1254 * NVRAM header 1255 */ 1256 uint8_t id[4]; 1257 uint8_t nvram_version; 1258 uint8_t reserved_0; 1259 1260 /* 1261 * NVRAM RISC parameter block 1262 */ 1263 uint8_t parameter_block_version; 1264 uint8_t reserved_1; 1265 1266 /* 1267 * LSB BIT 0 = Enable Hard Loop Id 1268 * LSB BIT 1 = Enable Fairness 1269 * LSB BIT 2 = Enable Full-Duplex 1270 * LSB BIT 3 = Enable Fast Posting 1271 * LSB BIT 4 = Enable Target Mode 1272 * LSB BIT 5 = Disable Initiator Mode 1273 * LSB BIT 6 = Enable ADISC 1274 * LSB BIT 7 = Enable Target Inquiry Data 1275 * 1276 * MSB BIT 0 = Enable PDBC Notify 1277 * MSB BIT 1 = Non Participating LIP 1278 * MSB BIT 2 = Descending Loop ID Search 1279 * MSB BIT 3 = Acquire Loop ID in LIPA 1280 * MSB BIT 4 = Stop PortQ on Full Status 1281 * MSB BIT 5 = Full Login after LIP 1282 * MSB BIT 6 = Node Name Option 1283 * MSB BIT 7 = Ext IFWCB enable bit 1284 */ 1285 uint8_t firmware_options[2]; 1286 1287 uint16_t frame_payload_size; 1288 uint16_t max_iocb_allocation; 1289 uint16_t execution_throttle; 1290 uint8_t retry_count; 1291 uint8_t retry_delay; /* unused */ 1292 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1293 uint16_t hard_address; 1294 uint8_t inquiry_data; 1295 uint8_t login_timeout; 1296 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1297 1298 /* 1299 * LSB BIT 0 = Timer Operation mode bit 0 1300 * LSB BIT 1 = Timer Operation mode bit 1 1301 * LSB BIT 2 = Timer Operation mode bit 2 1302 * LSB BIT 3 = Timer Operation mode bit 3 1303 * LSB BIT 4 = Init Config Mode bit 0 1304 * LSB BIT 5 = Init Config Mode bit 1 1305 * LSB BIT 6 = Init Config Mode bit 2 1306 * LSB BIT 7 = Enable Non part on LIHA failure 1307 * 1308 * MSB BIT 0 = Enable class 2 1309 * MSB BIT 1 = Enable ACK0 1310 * MSB BIT 2 = 1311 * MSB BIT 3 = 1312 * MSB BIT 4 = FC Tape Enable 1313 * MSB BIT 5 = Enable FC Confirm 1314 * MSB BIT 6 = Enable command queuing in target mode 1315 * MSB BIT 7 = No Logo On Link Down 1316 */ 1317 uint8_t add_firmware_options[2]; 1318 1319 uint8_t response_accumulation_timer; 1320 uint8_t interrupt_delay_timer; 1321 1322 /* 1323 * LSB BIT 0 = Enable Read xfr_rdy 1324 * LSB BIT 1 = Soft ID only 1325 * LSB BIT 2 = 1326 * LSB BIT 3 = 1327 * LSB BIT 4 = FCP RSP Payload [0] 1328 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1329 * LSB BIT 6 = Enable Out-of-Order frame handling 1330 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1331 * 1332 * MSB BIT 0 = Sbus enable - 2300 1333 * MSB BIT 1 = 1334 * MSB BIT 2 = 1335 * MSB BIT 3 = 1336 * MSB BIT 4 = LED mode 1337 * MSB BIT 5 = enable 50 ohm termination 1338 * MSB BIT 6 = Data Rate (2300 only) 1339 * MSB BIT 7 = Data Rate (2300 only) 1340 */ 1341 uint8_t special_options[2]; 1342 1343 /* Reserved for expanded RISC parameter block */ 1344 uint8_t reserved_2[22]; 1345 1346 /* 1347 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1348 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1349 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1350 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1351 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1352 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1353 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1354 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1355 * 1356 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1357 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1358 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1359 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1360 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1361 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1362 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1363 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1364 * 1365 * LSB BIT 0 = Output Swing 1G bit 0 1366 * LSB BIT 1 = Output Swing 1G bit 1 1367 * LSB BIT 2 = Output Swing 1G bit 2 1368 * LSB BIT 3 = Output Emphasis 1G bit 0 1369 * LSB BIT 4 = Output Emphasis 1G bit 1 1370 * LSB BIT 5 = Output Swing 2G bit 0 1371 * LSB BIT 6 = Output Swing 2G bit 1 1372 * LSB BIT 7 = Output Swing 2G bit 2 1373 * 1374 * MSB BIT 0 = Output Emphasis 2G bit 0 1375 * MSB BIT 1 = Output Emphasis 2G bit 1 1376 * MSB BIT 2 = Output Enable 1377 * MSB BIT 3 = 1378 * MSB BIT 4 = 1379 * MSB BIT 5 = 1380 * MSB BIT 6 = 1381 * MSB BIT 7 = 1382 */ 1383 uint8_t seriallink_options[4]; 1384 1385 /* 1386 * NVRAM host parameter block 1387 * 1388 * LSB BIT 0 = Enable spinup delay 1389 * LSB BIT 1 = Disable BIOS 1390 * LSB BIT 2 = Enable Memory Map BIOS 1391 * LSB BIT 3 = Enable Selectable Boot 1392 * LSB BIT 4 = Disable RISC code load 1393 * LSB BIT 5 = Set cache line size 1 1394 * LSB BIT 6 = PCI Parity Disable 1395 * LSB BIT 7 = Enable extended logging 1396 * 1397 * MSB BIT 0 = Enable 64bit addressing 1398 * MSB BIT 1 = Enable lip reset 1399 * MSB BIT 2 = Enable lip full login 1400 * MSB BIT 3 = Enable target reset 1401 * MSB BIT 4 = Enable database storage 1402 * MSB BIT 5 = Enable cache flush read 1403 * MSB BIT 6 = Enable database load 1404 * MSB BIT 7 = Enable alternate WWN 1405 */ 1406 uint8_t host_p[2]; 1407 1408 uint8_t boot_node_name[WWN_SIZE]; 1409 uint8_t boot_lun_number; 1410 uint8_t reset_delay; 1411 uint8_t port_down_retry_count; 1412 uint8_t boot_id_number; 1413 uint16_t max_luns_per_target; 1414 uint8_t fcode_boot_port_name[WWN_SIZE]; 1415 uint8_t alternate_port_name[WWN_SIZE]; 1416 uint8_t alternate_node_name[WWN_SIZE]; 1417 1418 /* 1419 * BIT 0 = Selective Login 1420 * BIT 1 = Alt-Boot Enable 1421 * BIT 2 = 1422 * BIT 3 = Boot Order List 1423 * BIT 4 = 1424 * BIT 5 = Selective LUN 1425 * BIT 6 = 1426 * BIT 7 = unused 1427 */ 1428 uint8_t efi_parameters; 1429 1430 uint8_t link_down_timeout; 1431 1432 uint8_t adapter_id[16]; 1433 1434 uint8_t alt1_boot_node_name[WWN_SIZE]; 1435 uint16_t alt1_boot_lun_number; 1436 uint8_t alt2_boot_node_name[WWN_SIZE]; 1437 uint16_t alt2_boot_lun_number; 1438 uint8_t alt3_boot_node_name[WWN_SIZE]; 1439 uint16_t alt3_boot_lun_number; 1440 uint8_t alt4_boot_node_name[WWN_SIZE]; 1441 uint16_t alt4_boot_lun_number; 1442 uint8_t alt5_boot_node_name[WWN_SIZE]; 1443 uint16_t alt5_boot_lun_number; 1444 uint8_t alt6_boot_node_name[WWN_SIZE]; 1445 uint16_t alt6_boot_lun_number; 1446 uint8_t alt7_boot_node_name[WWN_SIZE]; 1447 uint16_t alt7_boot_lun_number; 1448 1449 uint8_t reserved_3[2]; 1450 1451 /* Offset 200-215 : Model Number */ 1452 uint8_t model_number[16]; 1453 1454 /* OEM related items */ 1455 uint8_t oem_specific[16]; 1456 1457 /* 1458 * NVRAM Adapter Features offset 232-239 1459 * 1460 * LSB BIT 0 = External GBIC 1461 * LSB BIT 1 = Risc RAM parity 1462 * LSB BIT 2 = Buffer Plus Module 1463 * LSB BIT 3 = Multi Chip Adapter 1464 * LSB BIT 4 = Internal connector 1465 * LSB BIT 5 = 1466 * LSB BIT 6 = 1467 * LSB BIT 7 = 1468 * 1469 * MSB BIT 0 = 1470 * MSB BIT 1 = 1471 * MSB BIT 2 = 1472 * MSB BIT 3 = 1473 * MSB BIT 4 = 1474 * MSB BIT 5 = 1475 * MSB BIT 6 = 1476 * MSB BIT 7 = 1477 */ 1478 uint8_t adapter_features[2]; 1479 1480 uint8_t reserved_4[16]; 1481 1482 /* Subsystem vendor ID for ISP2200 */ 1483 uint16_t subsystem_vendor_id_2200; 1484 1485 /* Subsystem device ID for ISP2200 */ 1486 uint16_t subsystem_device_id_2200; 1487 1488 uint8_t reserved_5; 1489 uint8_t checksum; 1490 } nvram_t; 1491 1492 /* 1493 * ISP queue - response queue entry definition. 1494 */ 1495 typedef struct { 1496 uint8_t entry_type; /* Entry type. */ 1497 uint8_t entry_count; /* Entry count. */ 1498 uint8_t sys_define; /* System defined. */ 1499 uint8_t entry_status; /* Entry Status. */ 1500 uint32_t handle; /* System defined handle */ 1501 uint8_t data[52]; 1502 uint32_t signature; 1503 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1504 } response_t; 1505 1506 /* 1507 * ISP queue - ATIO queue entry definition. 1508 */ 1509 struct atio { 1510 uint8_t entry_type; /* Entry type. */ 1511 uint8_t entry_count; /* Entry count. */ 1512 uint8_t data[58]; 1513 uint32_t signature; 1514 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1515 }; 1516 1517 typedef union { 1518 uint16_t extended; 1519 struct { 1520 uint8_t reserved; 1521 uint8_t standard; 1522 } id; 1523 } target_id_t; 1524 1525 #define SET_TARGET_ID(ha, to, from) \ 1526 do { \ 1527 if (HAS_EXTENDED_IDS(ha)) \ 1528 to.extended = cpu_to_le16(from); \ 1529 else \ 1530 to.id.standard = (uint8_t)from; \ 1531 } while (0) 1532 1533 /* 1534 * ISP queue - command entry structure definition. 1535 */ 1536 #define COMMAND_TYPE 0x11 /* Command entry */ 1537 typedef struct { 1538 uint8_t entry_type; /* Entry type. */ 1539 uint8_t entry_count; /* Entry count. */ 1540 uint8_t sys_define; /* System defined. */ 1541 uint8_t entry_status; /* Entry Status. */ 1542 uint32_t handle; /* System handle. */ 1543 target_id_t target; /* SCSI ID */ 1544 uint16_t lun; /* SCSI LUN */ 1545 uint16_t control_flags; /* Control flags. */ 1546 #define CF_WRITE BIT_6 1547 #define CF_READ BIT_5 1548 #define CF_SIMPLE_TAG BIT_3 1549 #define CF_ORDERED_TAG BIT_2 1550 #define CF_HEAD_TAG BIT_1 1551 uint16_t reserved_1; 1552 uint16_t timeout; /* Command timeout. */ 1553 uint16_t dseg_count; /* Data segment count. */ 1554 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1555 uint32_t byte_count; /* Total byte count. */ 1556 uint32_t dseg_0_address; /* Data segment 0 address. */ 1557 uint32_t dseg_0_length; /* Data segment 0 length. */ 1558 uint32_t dseg_1_address; /* Data segment 1 address. */ 1559 uint32_t dseg_1_length; /* Data segment 1 length. */ 1560 uint32_t dseg_2_address; /* Data segment 2 address. */ 1561 uint32_t dseg_2_length; /* Data segment 2 length. */ 1562 } cmd_entry_t; 1563 1564 /* 1565 * ISP queue - 64-Bit addressing, command entry structure definition. 1566 */ 1567 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1568 typedef struct { 1569 uint8_t entry_type; /* Entry type. */ 1570 uint8_t entry_count; /* Entry count. */ 1571 uint8_t sys_define; /* System defined. */ 1572 uint8_t entry_status; /* Entry Status. */ 1573 uint32_t handle; /* System handle. */ 1574 target_id_t target; /* SCSI ID */ 1575 uint16_t lun; /* SCSI LUN */ 1576 uint16_t control_flags; /* Control flags. */ 1577 uint16_t reserved_1; 1578 uint16_t timeout; /* Command timeout. */ 1579 uint16_t dseg_count; /* Data segment count. */ 1580 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1581 uint32_t byte_count; /* Total byte count. */ 1582 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1583 uint32_t dseg_0_length; /* Data segment 0 length. */ 1584 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1585 uint32_t dseg_1_length; /* Data segment 1 length. */ 1586 } cmd_a64_entry_t, request_t; 1587 1588 /* 1589 * ISP queue - continuation entry structure definition. 1590 */ 1591 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1592 typedef struct { 1593 uint8_t entry_type; /* Entry type. */ 1594 uint8_t entry_count; /* Entry count. */ 1595 uint8_t sys_define; /* System defined. */ 1596 uint8_t entry_status; /* Entry Status. */ 1597 uint32_t reserved; 1598 uint32_t dseg_0_address; /* Data segment 0 address. */ 1599 uint32_t dseg_0_length; /* Data segment 0 length. */ 1600 uint32_t dseg_1_address; /* Data segment 1 address. */ 1601 uint32_t dseg_1_length; /* Data segment 1 length. */ 1602 uint32_t dseg_2_address; /* Data segment 2 address. */ 1603 uint32_t dseg_2_length; /* Data segment 2 length. */ 1604 uint32_t dseg_3_address; /* Data segment 3 address. */ 1605 uint32_t dseg_3_length; /* Data segment 3 length. */ 1606 uint32_t dseg_4_address; /* Data segment 4 address. */ 1607 uint32_t dseg_4_length; /* Data segment 4 length. */ 1608 uint32_t dseg_5_address; /* Data segment 5 address. */ 1609 uint32_t dseg_5_length; /* Data segment 5 length. */ 1610 uint32_t dseg_6_address; /* Data segment 6 address. */ 1611 uint32_t dseg_6_length; /* Data segment 6 length. */ 1612 } cont_entry_t; 1613 1614 /* 1615 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1616 */ 1617 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1618 typedef struct { 1619 uint8_t entry_type; /* Entry type. */ 1620 uint8_t entry_count; /* Entry count. */ 1621 uint8_t sys_define; /* System defined. */ 1622 uint8_t entry_status; /* Entry Status. */ 1623 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1624 uint32_t dseg_0_length; /* Data segment 0 length. */ 1625 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1626 uint32_t dseg_1_length; /* Data segment 1 length. */ 1627 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1628 uint32_t dseg_2_length; /* Data segment 2 length. */ 1629 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1630 uint32_t dseg_3_length; /* Data segment 3 length. */ 1631 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1632 uint32_t dseg_4_length; /* Data segment 4 length. */ 1633 } cont_a64_entry_t; 1634 1635 #define PO_MODE_DIF_INSERT 0 1636 #define PO_MODE_DIF_REMOVE 1 1637 #define PO_MODE_DIF_PASS 2 1638 #define PO_MODE_DIF_REPLACE 3 1639 #define PO_MODE_DIF_TCP_CKSUM 6 1640 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1641 #define PO_DISABLE_GUARD_CHECK BIT_4 1642 #define PO_DISABLE_INCR_REF_TAG BIT_5 1643 #define PO_DIS_HEADER_MODE BIT_7 1644 #define PO_ENABLE_DIF_BUNDLING BIT_8 1645 #define PO_DIS_FRAME_MODE BIT_9 1646 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1647 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1648 1649 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1650 #define PO_DIS_REF_TAG_REPL BIT_13 1651 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1652 #define PO_DIS_REF_TAG_VALD BIT_15 1653 1654 /* 1655 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1656 */ 1657 struct crc_context { 1658 uint32_t handle; /* System handle. */ 1659 __le32 ref_tag; 1660 __le16 app_tag; 1661 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1662 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1663 __le16 guard_seed; /* Initial Guard Seed */ 1664 __le16 prot_opts; /* Requested Data Protection Mode */ 1665 __le16 blk_size; /* Data size in bytes */ 1666 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1667 * only) */ 1668 __le32 byte_count; /* Total byte count/ total data 1669 * transfer count */ 1670 union { 1671 struct { 1672 uint32_t reserved_1; 1673 uint16_t reserved_2; 1674 uint16_t reserved_3; 1675 uint32_t reserved_4; 1676 uint32_t data_address[2]; 1677 uint32_t data_length; 1678 uint32_t reserved_5[2]; 1679 uint32_t reserved_6; 1680 } nobundling; 1681 struct { 1682 __le32 dif_byte_count; /* Total DIF byte 1683 * count */ 1684 uint16_t reserved_1; 1685 __le16 dseg_count; /* Data segment count */ 1686 uint32_t reserved_2; 1687 uint32_t data_address[2]; 1688 uint32_t data_length; 1689 uint32_t dif_address[2]; 1690 uint32_t dif_length; /* Data segment 0 1691 * length */ 1692 } bundling; 1693 } u; 1694 1695 struct fcp_cmnd fcp_cmnd; 1696 dma_addr_t crc_ctx_dma; 1697 /* List of DMA context transfers */ 1698 struct list_head dsd_list; 1699 1700 /* This structure should not exceed 512 bytes */ 1701 }; 1702 1703 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1704 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1705 1706 /* 1707 * ISP queue - status entry structure definition. 1708 */ 1709 #define STATUS_TYPE 0x03 /* Status entry. */ 1710 typedef struct { 1711 uint8_t entry_type; /* Entry type. */ 1712 uint8_t entry_count; /* Entry count. */ 1713 uint8_t sys_define; /* System defined. */ 1714 uint8_t entry_status; /* Entry Status. */ 1715 uint32_t handle; /* System handle. */ 1716 uint16_t scsi_status; /* SCSI status. */ 1717 uint16_t comp_status; /* Completion status. */ 1718 uint16_t state_flags; /* State flags. */ 1719 uint16_t status_flags; /* Status flags. */ 1720 uint16_t rsp_info_len; /* Response Info Length. */ 1721 uint16_t req_sense_length; /* Request sense data length. */ 1722 uint32_t residual_length; /* Residual transfer length. */ 1723 uint8_t rsp_info[8]; /* FCP response information. */ 1724 uint8_t req_sense_data[32]; /* Request sense data. */ 1725 } sts_entry_t; 1726 1727 /* 1728 * Status entry entry status 1729 */ 1730 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1731 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1732 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1733 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1734 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1735 #define RF_BUSY BIT_1 /* Busy */ 1736 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1737 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1738 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1739 RF_INV_E_TYPE) 1740 1741 /* 1742 * Status entry SCSI status bit definitions. 1743 */ 1744 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1745 #define SS_RESIDUAL_UNDER BIT_11 1746 #define SS_RESIDUAL_OVER BIT_10 1747 #define SS_SENSE_LEN_VALID BIT_9 1748 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1749 1750 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1751 #define SS_BUSY_CONDITION BIT_3 1752 #define SS_CONDITION_MET BIT_2 1753 #define SS_CHECK_CONDITION BIT_1 1754 1755 /* 1756 * Status entry completion status 1757 */ 1758 #define CS_COMPLETE 0x0 /* No errors */ 1759 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1760 #define CS_DMA 0x2 /* A DMA direction error. */ 1761 #define CS_TRANSPORT 0x3 /* Transport error. */ 1762 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1763 #define CS_ABORTED 0x5 /* System aborted command. */ 1764 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1765 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1766 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1767 1768 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1769 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1770 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1771 /* (selection timeout) */ 1772 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1773 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1774 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1775 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1776 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1777 failure */ 1778 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1779 #define CS_UNKNOWN 0x81 /* Driver defined */ 1780 #define CS_RETRY 0x82 /* Driver defined */ 1781 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1782 1783 #define CS_BIDIR_RD_OVERRUN 0x700 1784 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1785 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1786 #define CS_BIDIR_RD_UNDERRUN 0x1500 1787 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1788 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1789 #define CS_BIDIR_DMA 0x200 1790 /* 1791 * Status entry status flags 1792 */ 1793 #define SF_ABTS_TERMINATED BIT_10 1794 #define SF_LOGOUT_SENT BIT_13 1795 1796 /* 1797 * ISP queue - status continuation entry structure definition. 1798 */ 1799 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1800 typedef struct { 1801 uint8_t entry_type; /* Entry type. */ 1802 uint8_t entry_count; /* Entry count. */ 1803 uint8_t sys_define; /* System defined. */ 1804 uint8_t entry_status; /* Entry Status. */ 1805 uint8_t data[60]; /* data */ 1806 } sts_cont_entry_t; 1807 1808 /* 1809 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1810 * structure definition. 1811 */ 1812 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1813 typedef struct { 1814 uint8_t entry_type; /* Entry type. */ 1815 uint8_t entry_count; /* Entry count. */ 1816 uint8_t handle_count; /* Handle count. */ 1817 uint8_t entry_status; /* Entry Status. */ 1818 uint32_t handle[15]; /* System handles. */ 1819 } sts21_entry_t; 1820 1821 /* 1822 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1823 * structure definition. 1824 */ 1825 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1826 typedef struct { 1827 uint8_t entry_type; /* Entry type. */ 1828 uint8_t entry_count; /* Entry count. */ 1829 uint8_t handle_count; /* Handle count. */ 1830 uint8_t entry_status; /* Entry Status. */ 1831 uint16_t handle[30]; /* System handles. */ 1832 } sts22_entry_t; 1833 1834 /* 1835 * ISP queue - marker entry structure definition. 1836 */ 1837 #define MARKER_TYPE 0x04 /* Marker entry. */ 1838 typedef struct { 1839 uint8_t entry_type; /* Entry type. */ 1840 uint8_t entry_count; /* Entry count. */ 1841 uint8_t handle_count; /* Handle count. */ 1842 uint8_t entry_status; /* Entry Status. */ 1843 uint32_t sys_define_2; /* System defined. */ 1844 target_id_t target; /* SCSI ID */ 1845 uint8_t modifier; /* Modifier (7-0). */ 1846 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1847 #define MK_SYNC_ID 1 /* Synchronize ID */ 1848 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1849 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1850 /* clear port changed, */ 1851 /* use sequence number. */ 1852 uint8_t reserved_1; 1853 uint16_t sequence_number; /* Sequence number of event */ 1854 uint16_t lun; /* SCSI LUN */ 1855 uint8_t reserved_2[48]; 1856 } mrk_entry_t; 1857 1858 /* 1859 * ISP queue - Management Server entry structure definition. 1860 */ 1861 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1862 typedef struct { 1863 uint8_t entry_type; /* Entry type. */ 1864 uint8_t entry_count; /* Entry count. */ 1865 uint8_t handle_count; /* Handle count. */ 1866 uint8_t entry_status; /* Entry Status. */ 1867 uint32_t handle1; /* System handle. */ 1868 target_id_t loop_id; 1869 uint16_t status; 1870 uint16_t control_flags; /* Control flags. */ 1871 uint16_t reserved2; 1872 uint16_t timeout; 1873 uint16_t cmd_dsd_count; 1874 uint16_t total_dsd_count; 1875 uint8_t type; 1876 uint8_t r_ctl; 1877 uint16_t rx_id; 1878 uint16_t reserved3; 1879 uint32_t handle2; 1880 uint32_t rsp_bytecount; 1881 uint32_t req_bytecount; 1882 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1883 uint32_t dseg_req_length; /* Data segment 0 length. */ 1884 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1885 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1886 } ms_iocb_entry_t; 1887 1888 1889 /* 1890 * ISP queue - Mailbox Command entry structure definition. 1891 */ 1892 #define MBX_IOCB_TYPE 0x39 1893 struct mbx_entry { 1894 uint8_t entry_type; 1895 uint8_t entry_count; 1896 uint8_t sys_define1; 1897 /* Use sys_define1 for source type */ 1898 #define SOURCE_SCSI 0x00 1899 #define SOURCE_IP 0x01 1900 #define SOURCE_VI 0x02 1901 #define SOURCE_SCTP 0x03 1902 #define SOURCE_MP 0x04 1903 #define SOURCE_MPIOCTL 0x05 1904 #define SOURCE_ASYNC_IOCB 0x07 1905 1906 uint8_t entry_status; 1907 1908 uint32_t handle; 1909 target_id_t loop_id; 1910 1911 uint16_t status; 1912 uint16_t state_flags; 1913 uint16_t status_flags; 1914 1915 uint32_t sys_define2[2]; 1916 1917 uint16_t mb0; 1918 uint16_t mb1; 1919 uint16_t mb2; 1920 uint16_t mb3; 1921 uint16_t mb6; 1922 uint16_t mb7; 1923 uint16_t mb9; 1924 uint16_t mb10; 1925 uint32_t reserved_2[2]; 1926 uint8_t node_name[WWN_SIZE]; 1927 uint8_t port_name[WWN_SIZE]; 1928 }; 1929 1930 /* 1931 * ISP request and response queue entry sizes 1932 */ 1933 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1934 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1935 1936 1937 /* 1938 * 24 bit port ID type definition. 1939 */ 1940 typedef union { 1941 uint32_t b24 : 24; 1942 1943 struct { 1944 #ifdef __BIG_ENDIAN 1945 uint8_t domain; 1946 uint8_t area; 1947 uint8_t al_pa; 1948 #elif defined(__LITTLE_ENDIAN) 1949 uint8_t al_pa; 1950 uint8_t area; 1951 uint8_t domain; 1952 #else 1953 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1954 #endif 1955 uint8_t rsvd_1; 1956 } b; 1957 } port_id_t; 1958 #define INVALID_PORT_ID 0xFFFFFF 1959 1960 /* 1961 * Switch info gathering structure. 1962 */ 1963 typedef struct { 1964 port_id_t d_id; 1965 uint8_t node_name[WWN_SIZE]; 1966 uint8_t port_name[WWN_SIZE]; 1967 uint8_t fabric_port_name[WWN_SIZE]; 1968 uint16_t fp_speed; 1969 uint8_t fc4_type; 1970 } sw_info_t; 1971 1972 /* FCP-4 types */ 1973 #define FC4_TYPE_FCP_SCSI 0x08 1974 #define FC4_TYPE_OTHER 0x0 1975 #define FC4_TYPE_UNKNOWN 0xff 1976 1977 /* 1978 * Fibre channel port type. 1979 */ 1980 typedef enum { 1981 FCT_UNKNOWN, 1982 FCT_RSCN, 1983 FCT_SWITCH, 1984 FCT_BROADCAST, 1985 FCT_INITIATOR, 1986 FCT_TARGET 1987 } fc_port_type_t; 1988 1989 /* 1990 * Fibre channel port structure. 1991 */ 1992 typedef struct fc_port { 1993 struct list_head list; 1994 struct scsi_qla_host *vha; 1995 1996 uint8_t node_name[WWN_SIZE]; 1997 uint8_t port_name[WWN_SIZE]; 1998 port_id_t d_id; 1999 uint16_t loop_id; 2000 uint16_t old_loop_id; 2001 2002 uint16_t tgt_id; 2003 uint16_t old_tgt_id; 2004 2005 uint8_t fcp_prio; 2006 2007 uint8_t fabric_port_name[WWN_SIZE]; 2008 uint16_t fp_speed; 2009 2010 fc_port_type_t port_type; 2011 2012 atomic_t state; 2013 uint32_t flags; 2014 2015 int login_retry; 2016 2017 struct fc_rport *rport, *drport; 2018 u32 supported_classes; 2019 2020 uint8_t fc4_type; 2021 uint8_t scan_state; 2022 2023 unsigned long last_queue_full; 2024 unsigned long last_ramp_up; 2025 2026 uint16_t port_id; 2027 2028 unsigned long retry_delay_timestamp; 2029 } fc_port_t; 2030 2031 #include "qla_mr.h" 2032 2033 /* 2034 * Fibre channel port/lun states. 2035 */ 2036 #define FCS_UNCONFIGURED 1 2037 #define FCS_DEVICE_DEAD 2 2038 #define FCS_DEVICE_LOST 3 2039 #define FCS_ONLINE 4 2040 2041 static const char * const port_state_str[] = { 2042 "Unknown", 2043 "UNCONFIGURED", 2044 "DEAD", 2045 "LOST", 2046 "ONLINE" 2047 }; 2048 2049 /* 2050 * FC port flags. 2051 */ 2052 #define FCF_FABRIC_DEVICE BIT_0 2053 #define FCF_LOGIN_NEEDED BIT_1 2054 #define FCF_FCP2_DEVICE BIT_2 2055 #define FCF_ASYNC_SENT BIT_3 2056 #define FCF_CONF_COMP_SUPPORTED BIT_4 2057 2058 /* No loop ID flag. */ 2059 #define FC_NO_LOOP_ID 0x1000 2060 2061 /* 2062 * FC-CT interface 2063 * 2064 * NOTE: All structures are big-endian in form. 2065 */ 2066 2067 #define CT_REJECT_RESPONSE 0x8001 2068 #define CT_ACCEPT_RESPONSE 0x8002 2069 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2070 #define CT_REASON_CANNOT_PERFORM 0x09 2071 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2072 #define CT_EXPL_ALREADY_REGISTERED 0x10 2073 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2074 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2075 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2076 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2077 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2078 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2079 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2080 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2081 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2082 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2083 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2084 2085 #define NS_N_PORT_TYPE 0x01 2086 #define NS_NL_PORT_TYPE 0x02 2087 #define NS_NX_PORT_TYPE 0x7F 2088 2089 #define GA_NXT_CMD 0x100 2090 #define GA_NXT_REQ_SIZE (16 + 4) 2091 #define GA_NXT_RSP_SIZE (16 + 620) 2092 2093 #define GID_PT_CMD 0x1A1 2094 #define GID_PT_REQ_SIZE (16 + 4) 2095 2096 #define GPN_ID_CMD 0x112 2097 #define GPN_ID_REQ_SIZE (16 + 4) 2098 #define GPN_ID_RSP_SIZE (16 + 8) 2099 2100 #define GNN_ID_CMD 0x113 2101 #define GNN_ID_REQ_SIZE (16 + 4) 2102 #define GNN_ID_RSP_SIZE (16 + 8) 2103 2104 #define GFT_ID_CMD 0x117 2105 #define GFT_ID_REQ_SIZE (16 + 4) 2106 #define GFT_ID_RSP_SIZE (16 + 32) 2107 2108 #define RFT_ID_CMD 0x217 2109 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2110 #define RFT_ID_RSP_SIZE 16 2111 2112 #define RFF_ID_CMD 0x21F 2113 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2114 #define RFF_ID_RSP_SIZE 16 2115 2116 #define RNN_ID_CMD 0x213 2117 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2118 #define RNN_ID_RSP_SIZE 16 2119 2120 #define RSNN_NN_CMD 0x239 2121 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2122 #define RSNN_NN_RSP_SIZE 16 2123 2124 #define GFPN_ID_CMD 0x11C 2125 #define GFPN_ID_REQ_SIZE (16 + 4) 2126 #define GFPN_ID_RSP_SIZE (16 + 8) 2127 2128 #define GPSC_CMD 0x127 2129 #define GPSC_REQ_SIZE (16 + 8) 2130 #define GPSC_RSP_SIZE (16 + 2 + 2) 2131 2132 #define GFF_ID_CMD 0x011F 2133 #define GFF_ID_REQ_SIZE (16 + 4) 2134 #define GFF_ID_RSP_SIZE (16 + 128) 2135 2136 /* 2137 * HBA attribute types. 2138 */ 2139 #define FDMI_HBA_ATTR_COUNT 9 2140 #define FDMIV2_HBA_ATTR_COUNT 17 2141 #define FDMI_HBA_NODE_NAME 0x1 2142 #define FDMI_HBA_MANUFACTURER 0x2 2143 #define FDMI_HBA_SERIAL_NUMBER 0x3 2144 #define FDMI_HBA_MODEL 0x4 2145 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2146 #define FDMI_HBA_HARDWARE_VERSION 0x6 2147 #define FDMI_HBA_DRIVER_VERSION 0x7 2148 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2149 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2150 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2151 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2152 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2153 #define FDMI_HBA_VENDOR_ID 0xd 2154 #define FDMI_HBA_NUM_PORTS 0xe 2155 #define FDMI_HBA_FABRIC_NAME 0xf 2156 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2157 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2158 2159 struct ct_fdmi_hba_attr { 2160 uint16_t type; 2161 uint16_t len; 2162 union { 2163 uint8_t node_name[WWN_SIZE]; 2164 uint8_t manufacturer[64]; 2165 uint8_t serial_num[32]; 2166 uint8_t model[16]; 2167 uint8_t model_desc[80]; 2168 uint8_t hw_version[32]; 2169 uint8_t driver_version[32]; 2170 uint8_t orom_version[16]; 2171 uint8_t fw_version[32]; 2172 uint8_t os_version[128]; 2173 uint32_t max_ct_len; 2174 } a; 2175 }; 2176 2177 struct ct_fdmi_hba_attributes { 2178 uint32_t count; 2179 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2180 }; 2181 2182 struct ct_fdmiv2_hba_attr { 2183 uint16_t type; 2184 uint16_t len; 2185 union { 2186 uint8_t node_name[WWN_SIZE]; 2187 uint8_t manufacturer[32]; 2188 uint8_t serial_num[32]; 2189 uint8_t model[16]; 2190 uint8_t model_desc[80]; 2191 uint8_t hw_version[16]; 2192 uint8_t driver_version[32]; 2193 uint8_t orom_version[16]; 2194 uint8_t fw_version[32]; 2195 uint8_t os_version[128]; 2196 uint32_t max_ct_len; 2197 uint8_t sym_name[256]; 2198 uint32_t vendor_id; 2199 uint32_t num_ports; 2200 uint8_t fabric_name[WWN_SIZE]; 2201 uint8_t bios_name[32]; 2202 uint8_t vendor_indentifer[8]; 2203 } a; 2204 }; 2205 2206 struct ct_fdmiv2_hba_attributes { 2207 uint32_t count; 2208 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2209 }; 2210 2211 /* 2212 * Port attribute types. 2213 */ 2214 #define FDMI_PORT_ATTR_COUNT 6 2215 #define FDMIV2_PORT_ATTR_COUNT 16 2216 #define FDMI_PORT_FC4_TYPES 0x1 2217 #define FDMI_PORT_SUPPORT_SPEED 0x2 2218 #define FDMI_PORT_CURRENT_SPEED 0x3 2219 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2220 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2221 #define FDMI_PORT_HOST_NAME 0x6 2222 #define FDMI_PORT_NODE_NAME 0x7 2223 #define FDMI_PORT_NAME 0x8 2224 #define FDMI_PORT_SYM_NAME 0x9 2225 #define FDMI_PORT_TYPE 0xa 2226 #define FDMI_PORT_SUPP_COS 0xb 2227 #define FDMI_PORT_FABRIC_NAME 0xc 2228 #define FDMI_PORT_FC4_TYPE 0xd 2229 #define FDMI_PORT_STATE 0x101 2230 #define FDMI_PORT_COUNT 0x102 2231 #define FDMI_PORT_ID 0x103 2232 2233 #define FDMI_PORT_SPEED_1GB 0x1 2234 #define FDMI_PORT_SPEED_2GB 0x2 2235 #define FDMI_PORT_SPEED_10GB 0x4 2236 #define FDMI_PORT_SPEED_4GB 0x8 2237 #define FDMI_PORT_SPEED_8GB 0x10 2238 #define FDMI_PORT_SPEED_16GB 0x20 2239 #define FDMI_PORT_SPEED_32GB 0x40 2240 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2241 2242 #define FC_CLASS_2 0x04 2243 #define FC_CLASS_3 0x08 2244 #define FC_CLASS_2_3 0x0C 2245 2246 struct ct_fdmiv2_port_attr { 2247 uint16_t type; 2248 uint16_t len; 2249 union { 2250 uint8_t fc4_types[32]; 2251 uint32_t sup_speed; 2252 uint32_t cur_speed; 2253 uint32_t max_frame_size; 2254 uint8_t os_dev_name[32]; 2255 uint8_t host_name[32]; 2256 uint8_t node_name[WWN_SIZE]; 2257 uint8_t port_name[WWN_SIZE]; 2258 uint8_t port_sym_name[128]; 2259 uint32_t port_type; 2260 uint32_t port_supported_cos; 2261 uint8_t fabric_name[WWN_SIZE]; 2262 uint8_t port_fc4_type[32]; 2263 uint32_t port_state; 2264 uint32_t num_ports; 2265 uint32_t port_id; 2266 } a; 2267 }; 2268 2269 /* 2270 * Port Attribute Block. 2271 */ 2272 struct ct_fdmiv2_port_attributes { 2273 uint32_t count; 2274 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2275 }; 2276 2277 struct ct_fdmi_port_attr { 2278 uint16_t type; 2279 uint16_t len; 2280 union { 2281 uint8_t fc4_types[32]; 2282 uint32_t sup_speed; 2283 uint32_t cur_speed; 2284 uint32_t max_frame_size; 2285 uint8_t os_dev_name[32]; 2286 uint8_t host_name[32]; 2287 } a; 2288 }; 2289 2290 struct ct_fdmi_port_attributes { 2291 uint32_t count; 2292 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2293 }; 2294 2295 /* FDMI definitions. */ 2296 #define GRHL_CMD 0x100 2297 #define GHAT_CMD 0x101 2298 #define GRPL_CMD 0x102 2299 #define GPAT_CMD 0x110 2300 2301 #define RHBA_CMD 0x200 2302 #define RHBA_RSP_SIZE 16 2303 2304 #define RHAT_CMD 0x201 2305 #define RPRT_CMD 0x210 2306 2307 #define RPA_CMD 0x211 2308 #define RPA_RSP_SIZE 16 2309 2310 #define DHBA_CMD 0x300 2311 #define DHBA_REQ_SIZE (16 + 8) 2312 #define DHBA_RSP_SIZE 16 2313 2314 #define DHAT_CMD 0x301 2315 #define DPRT_CMD 0x310 2316 #define DPA_CMD 0x311 2317 2318 /* CT command header -- request/response common fields */ 2319 struct ct_cmd_hdr { 2320 uint8_t revision; 2321 uint8_t in_id[3]; 2322 uint8_t gs_type; 2323 uint8_t gs_subtype; 2324 uint8_t options; 2325 uint8_t reserved; 2326 }; 2327 2328 /* CT command request */ 2329 struct ct_sns_req { 2330 struct ct_cmd_hdr header; 2331 uint16_t command; 2332 uint16_t max_rsp_size; 2333 uint8_t fragment_id; 2334 uint8_t reserved[3]; 2335 2336 union { 2337 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2338 struct { 2339 uint8_t reserved; 2340 uint8_t port_id[3]; 2341 } port_id; 2342 2343 struct { 2344 uint8_t port_type; 2345 uint8_t domain; 2346 uint8_t area; 2347 uint8_t reserved; 2348 } gid_pt; 2349 2350 struct { 2351 uint8_t reserved; 2352 uint8_t port_id[3]; 2353 uint8_t fc4_types[32]; 2354 } rft_id; 2355 2356 struct { 2357 uint8_t reserved; 2358 uint8_t port_id[3]; 2359 uint16_t reserved2; 2360 uint8_t fc4_feature; 2361 uint8_t fc4_type; 2362 } rff_id; 2363 2364 struct { 2365 uint8_t reserved; 2366 uint8_t port_id[3]; 2367 uint8_t node_name[8]; 2368 } rnn_id; 2369 2370 struct { 2371 uint8_t node_name[8]; 2372 uint8_t name_len; 2373 uint8_t sym_node_name[255]; 2374 } rsnn_nn; 2375 2376 struct { 2377 uint8_t hba_indentifier[8]; 2378 } ghat; 2379 2380 struct { 2381 uint8_t hba_identifier[8]; 2382 uint32_t entry_count; 2383 uint8_t port_name[8]; 2384 struct ct_fdmi_hba_attributes attrs; 2385 } rhba; 2386 2387 struct { 2388 uint8_t hba_identifier[8]; 2389 uint32_t entry_count; 2390 uint8_t port_name[8]; 2391 struct ct_fdmiv2_hba_attributes attrs; 2392 } rhba2; 2393 2394 struct { 2395 uint8_t hba_identifier[8]; 2396 struct ct_fdmi_hba_attributes attrs; 2397 } rhat; 2398 2399 struct { 2400 uint8_t port_name[8]; 2401 struct ct_fdmi_port_attributes attrs; 2402 } rpa; 2403 2404 struct { 2405 uint8_t port_name[8]; 2406 struct ct_fdmiv2_port_attributes attrs; 2407 } rpa2; 2408 2409 struct { 2410 uint8_t port_name[8]; 2411 } dhba; 2412 2413 struct { 2414 uint8_t port_name[8]; 2415 } dhat; 2416 2417 struct { 2418 uint8_t port_name[8]; 2419 } dprt; 2420 2421 struct { 2422 uint8_t port_name[8]; 2423 } dpa; 2424 2425 struct { 2426 uint8_t port_name[8]; 2427 } gpsc; 2428 2429 struct { 2430 uint8_t reserved; 2431 uint8_t port_name[3]; 2432 } gff_id; 2433 } req; 2434 }; 2435 2436 /* CT command response header */ 2437 struct ct_rsp_hdr { 2438 struct ct_cmd_hdr header; 2439 uint16_t response; 2440 uint16_t residual; 2441 uint8_t fragment_id; 2442 uint8_t reason_code; 2443 uint8_t explanation_code; 2444 uint8_t vendor_unique; 2445 }; 2446 2447 struct ct_sns_gid_pt_data { 2448 uint8_t control_byte; 2449 uint8_t port_id[3]; 2450 }; 2451 2452 struct ct_sns_rsp { 2453 struct ct_rsp_hdr header; 2454 2455 union { 2456 struct { 2457 uint8_t port_type; 2458 uint8_t port_id[3]; 2459 uint8_t port_name[8]; 2460 uint8_t sym_port_name_len; 2461 uint8_t sym_port_name[255]; 2462 uint8_t node_name[8]; 2463 uint8_t sym_node_name_len; 2464 uint8_t sym_node_name[255]; 2465 uint8_t init_proc_assoc[8]; 2466 uint8_t node_ip_addr[16]; 2467 uint8_t class_of_service[4]; 2468 uint8_t fc4_types[32]; 2469 uint8_t ip_address[16]; 2470 uint8_t fabric_port_name[8]; 2471 uint8_t reserved; 2472 uint8_t hard_address[3]; 2473 } ga_nxt; 2474 2475 struct { 2476 /* Assume the largest number of targets for the union */ 2477 struct ct_sns_gid_pt_data 2478 entries[MAX_FIBRE_DEVICES_MAX]; 2479 } gid_pt; 2480 2481 struct { 2482 uint8_t port_name[8]; 2483 } gpn_id; 2484 2485 struct { 2486 uint8_t node_name[8]; 2487 } gnn_id; 2488 2489 struct { 2490 uint8_t fc4_types[32]; 2491 } gft_id; 2492 2493 struct { 2494 uint32_t entry_count; 2495 uint8_t port_name[8]; 2496 struct ct_fdmi_hba_attributes attrs; 2497 } ghat; 2498 2499 struct { 2500 uint8_t port_name[8]; 2501 } gfpn_id; 2502 2503 struct { 2504 uint16_t speeds; 2505 uint16_t speed; 2506 } gpsc; 2507 2508 #define GFF_FCP_SCSI_OFFSET 7 2509 struct { 2510 uint8_t fc4_features[128]; 2511 } gff_id; 2512 } rsp; 2513 }; 2514 2515 struct ct_sns_pkt { 2516 union { 2517 struct ct_sns_req req; 2518 struct ct_sns_rsp rsp; 2519 } p; 2520 }; 2521 2522 /* 2523 * SNS command structures -- for 2200 compatibility. 2524 */ 2525 #define RFT_ID_SNS_SCMD_LEN 22 2526 #define RFT_ID_SNS_CMD_SIZE 60 2527 #define RFT_ID_SNS_DATA_SIZE 16 2528 2529 #define RNN_ID_SNS_SCMD_LEN 10 2530 #define RNN_ID_SNS_CMD_SIZE 36 2531 #define RNN_ID_SNS_DATA_SIZE 16 2532 2533 #define GA_NXT_SNS_SCMD_LEN 6 2534 #define GA_NXT_SNS_CMD_SIZE 28 2535 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2536 2537 #define GID_PT_SNS_SCMD_LEN 6 2538 #define GID_PT_SNS_CMD_SIZE 28 2539 /* 2540 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2541 * adapters. 2542 */ 2543 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2544 2545 #define GPN_ID_SNS_SCMD_LEN 6 2546 #define GPN_ID_SNS_CMD_SIZE 28 2547 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2548 2549 #define GNN_ID_SNS_SCMD_LEN 6 2550 #define GNN_ID_SNS_CMD_SIZE 28 2551 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2552 2553 struct sns_cmd_pkt { 2554 union { 2555 struct { 2556 uint16_t buffer_length; 2557 uint16_t reserved_1; 2558 uint32_t buffer_address[2]; 2559 uint16_t subcommand_length; 2560 uint16_t reserved_2; 2561 uint16_t subcommand; 2562 uint16_t size; 2563 uint32_t reserved_3; 2564 uint8_t param[36]; 2565 } cmd; 2566 2567 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2568 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2569 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2570 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2571 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2572 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2573 } p; 2574 }; 2575 2576 struct fw_blob { 2577 char *name; 2578 uint32_t segs[4]; 2579 const struct firmware *fw; 2580 }; 2581 2582 /* Return data from MBC_GET_ID_LIST call. */ 2583 struct gid_list_info { 2584 uint8_t al_pa; 2585 uint8_t area; 2586 uint8_t domain; 2587 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2588 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2589 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2590 }; 2591 2592 /* NPIV */ 2593 typedef struct vport_info { 2594 uint8_t port_name[WWN_SIZE]; 2595 uint8_t node_name[WWN_SIZE]; 2596 int vp_id; 2597 uint16_t loop_id; 2598 unsigned long host_no; 2599 uint8_t port_id[3]; 2600 int loop_state; 2601 } vport_info_t; 2602 2603 typedef struct vport_params { 2604 uint8_t port_name[WWN_SIZE]; 2605 uint8_t node_name[WWN_SIZE]; 2606 uint32_t options; 2607 #define VP_OPTS_RETRY_ENABLE BIT_0 2608 #define VP_OPTS_VP_DISABLE BIT_1 2609 } vport_params_t; 2610 2611 /* NPIV - return codes of VP create and modify */ 2612 #define VP_RET_CODE_OK 0 2613 #define VP_RET_CODE_FATAL 1 2614 #define VP_RET_CODE_WRONG_ID 2 2615 #define VP_RET_CODE_WWPN 3 2616 #define VP_RET_CODE_RESOURCES 4 2617 #define VP_RET_CODE_NO_MEM 5 2618 #define VP_RET_CODE_NOT_FOUND 6 2619 2620 struct qla_hw_data; 2621 struct rsp_que; 2622 /* 2623 * ISP operations 2624 */ 2625 struct isp_operations { 2626 2627 int (*pci_config) (struct scsi_qla_host *); 2628 void (*reset_chip) (struct scsi_qla_host *); 2629 int (*chip_diag) (struct scsi_qla_host *); 2630 void (*config_rings) (struct scsi_qla_host *); 2631 void (*reset_adapter) (struct scsi_qla_host *); 2632 int (*nvram_config) (struct scsi_qla_host *); 2633 void (*update_fw_options) (struct scsi_qla_host *); 2634 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2635 2636 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2637 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 2638 2639 irq_handler_t intr_handler; 2640 void (*enable_intrs) (struct qla_hw_data *); 2641 void (*disable_intrs) (struct qla_hw_data *); 2642 2643 int (*abort_command) (srb_t *); 2644 int (*target_reset) (struct fc_port *, uint64_t, int); 2645 int (*lun_reset) (struct fc_port *, uint64_t, int); 2646 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2647 uint8_t, uint8_t, uint16_t *, uint8_t); 2648 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2649 uint8_t, uint8_t); 2650 2651 uint16_t (*calc_req_entries) (uint16_t); 2652 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2653 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2654 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2655 uint32_t); 2656 2657 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2658 uint32_t, uint32_t); 2659 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2660 uint32_t); 2661 2662 void (*fw_dump) (struct scsi_qla_host *, int); 2663 2664 int (*beacon_on) (struct scsi_qla_host *); 2665 int (*beacon_off) (struct scsi_qla_host *); 2666 void (*beacon_blink) (struct scsi_qla_host *); 2667 2668 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2669 uint32_t, uint32_t); 2670 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2671 uint32_t); 2672 2673 int (*get_flash_version) (struct scsi_qla_host *, void *); 2674 int (*start_scsi) (srb_t *); 2675 int (*abort_isp) (struct scsi_qla_host *); 2676 int (*iospace_config)(struct qla_hw_data*); 2677 int (*initialize_adapter)(struct scsi_qla_host *); 2678 }; 2679 2680 /* MSI-X Support *************************************************************/ 2681 2682 #define QLA_MSIX_CHIP_REV_24XX 3 2683 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2684 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2685 2686 #define QLA_MSIX_DEFAULT 0x00 2687 #define QLA_MSIX_RSP_Q 0x01 2688 2689 #define QLA_MIDX_DEFAULT 0 2690 #define QLA_MIDX_RSP_Q 1 2691 #define QLA_PCI_MSIX_CONTROL 0xa2 2692 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2693 2694 struct scsi_qla_host; 2695 2696 struct qla_msix_entry { 2697 int have_irq; 2698 uint32_t vector; 2699 uint16_t entry; 2700 struct rsp_que *rsp; 2701 }; 2702 2703 #define WATCH_INTERVAL 1 /* number of seconds */ 2704 2705 /* Work events. */ 2706 enum qla_work_type { 2707 QLA_EVT_AEN, 2708 QLA_EVT_IDC_ACK, 2709 QLA_EVT_ASYNC_LOGIN, 2710 QLA_EVT_ASYNC_LOGIN_DONE, 2711 QLA_EVT_ASYNC_LOGOUT, 2712 QLA_EVT_ASYNC_LOGOUT_DONE, 2713 QLA_EVT_ASYNC_ADISC, 2714 QLA_EVT_ASYNC_ADISC_DONE, 2715 QLA_EVT_UEVENT, 2716 QLA_EVT_AENFX, 2717 }; 2718 2719 2720 struct qla_work_evt { 2721 struct list_head list; 2722 enum qla_work_type type; 2723 u32 flags; 2724 #define QLA_EVT_FLAG_FREE 0x1 2725 2726 union { 2727 struct { 2728 enum fc_host_event_code code; 2729 u32 data; 2730 } aen; 2731 struct { 2732 #define QLA_IDC_ACK_REGS 7 2733 uint16_t mb[QLA_IDC_ACK_REGS]; 2734 } idc_ack; 2735 struct { 2736 struct fc_port *fcport; 2737 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2738 u16 data[2]; 2739 } logio; 2740 struct { 2741 u32 code; 2742 #define QLA_UEVENT_CODE_FW_DUMP 0 2743 } uevent; 2744 struct { 2745 uint32_t evtcode; 2746 uint32_t mbx[8]; 2747 uint32_t count; 2748 } aenfx; 2749 struct { 2750 srb_t *sp; 2751 } iosb; 2752 } u; 2753 }; 2754 2755 struct qla_chip_state_84xx { 2756 struct list_head list; 2757 struct kref kref; 2758 2759 void *bus; 2760 spinlock_t access_lock; 2761 struct mutex fw_update_mutex; 2762 uint32_t fw_update; 2763 uint32_t op_fw_version; 2764 uint32_t op_fw_size; 2765 uint32_t op_fw_seq_size; 2766 uint32_t diag_fw_version; 2767 uint32_t gold_fw_version; 2768 }; 2769 2770 struct qla_statistics { 2771 uint32_t total_isp_aborts; 2772 uint64_t input_bytes; 2773 uint64_t output_bytes; 2774 uint64_t input_requests; 2775 uint64_t output_requests; 2776 uint32_t control_requests; 2777 2778 uint64_t jiffies_at_last_reset; 2779 uint32_t stat_max_pend_cmds; 2780 uint32_t stat_max_qfull_cmds_alloc; 2781 uint32_t stat_max_qfull_cmds_dropped; 2782 }; 2783 2784 struct bidi_statistics { 2785 unsigned long long io_count; 2786 unsigned long long transfer_bytes; 2787 }; 2788 2789 /* Multi queue support */ 2790 #define MBC_INITIALIZE_MULTIQ 0x1f 2791 #define QLA_QUE_PAGE 0X1000 2792 #define QLA_MQ_SIZE 32 2793 #define QLA_MAX_QUEUES 256 2794 #define ISP_QUE_REG(ha, id) \ 2795 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 2796 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 2797 ((void __iomem *)ha->iobase)) 2798 #define QLA_REQ_QUE_ID(tag) \ 2799 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2800 #define QLA_DEFAULT_QUE_QOS 5 2801 #define QLA_PRECONFIG_VPORTS 32 2802 #define QLA_MAX_VPORTS_QLA24XX 128 2803 #define QLA_MAX_VPORTS_QLA25XX 256 2804 /* Response queue data structure */ 2805 struct rsp_que { 2806 dma_addr_t dma; 2807 response_t *ring; 2808 response_t *ring_ptr; 2809 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2810 uint32_t __iomem *rsp_q_out; 2811 uint16_t ring_index; 2812 uint16_t out_ptr; 2813 uint16_t *in_ptr; /* queue shadow in index */ 2814 uint16_t length; 2815 uint16_t options; 2816 uint16_t rid; 2817 uint16_t id; 2818 uint16_t vp_idx; 2819 struct qla_hw_data *hw; 2820 struct qla_msix_entry *msix; 2821 struct req_que *req; 2822 srb_t *status_srb; /* status continuation entry */ 2823 struct work_struct q_work; 2824 2825 dma_addr_t dma_fx00; 2826 response_t *ring_fx00; 2827 uint16_t length_fx00; 2828 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2829 }; 2830 2831 /* Request queue data structure */ 2832 struct req_que { 2833 dma_addr_t dma; 2834 request_t *ring; 2835 request_t *ring_ptr; 2836 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2837 uint32_t __iomem *req_q_out; 2838 uint16_t ring_index; 2839 uint16_t in_ptr; 2840 uint16_t *out_ptr; /* queue shadow out index */ 2841 uint16_t cnt; 2842 uint16_t length; 2843 uint16_t options; 2844 uint16_t rid; 2845 uint16_t id; 2846 uint16_t qos; 2847 uint16_t vp_idx; 2848 struct rsp_que *rsp; 2849 srb_t **outstanding_cmds; 2850 uint32_t current_outstanding_cmd; 2851 uint16_t num_outstanding_cmds; 2852 int max_q_depth; 2853 2854 dma_addr_t dma_fx00; 2855 request_t *ring_fx00; 2856 uint16_t length_fx00; 2857 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2858 }; 2859 2860 /* Place holder for FW buffer parameters */ 2861 struct qlfc_fw { 2862 void *fw_buf; 2863 dma_addr_t fw_dma; 2864 uint32_t len; 2865 }; 2866 2867 struct scsi_qlt_host { 2868 void *target_lport_ptr; 2869 struct mutex tgt_mutex; 2870 struct mutex tgt_host_action_mutex; 2871 struct qla_tgt *qla_tgt; 2872 }; 2873 2874 struct qlt_hw_data { 2875 /* Protected by hw lock */ 2876 uint32_t enable_class_2:1; 2877 uint32_t enable_explicit_conf:1; 2878 uint32_t ini_mode_force_reverse:1; 2879 uint32_t node_name_set:1; 2880 2881 dma_addr_t atio_dma; /* Physical address. */ 2882 struct atio *atio_ring; /* Base virtual address */ 2883 struct atio *atio_ring_ptr; /* Current address. */ 2884 uint16_t atio_ring_index; /* Current index. */ 2885 uint16_t atio_q_length; 2886 uint32_t __iomem *atio_q_in; 2887 uint32_t __iomem *atio_q_out; 2888 2889 struct qla_tgt_func_tmpl *tgt_ops; 2890 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2891 uint16_t current_handle; 2892 2893 struct qla_tgt_vp_map *tgt_vp_map; 2894 2895 int saved_set; 2896 uint16_t saved_exchange_count; 2897 uint32_t saved_firmware_options_1; 2898 uint32_t saved_firmware_options_2; 2899 uint32_t saved_firmware_options_3; 2900 uint8_t saved_firmware_options[2]; 2901 uint8_t saved_add_firmware_options[2]; 2902 2903 uint8_t tgt_node_name[WWN_SIZE]; 2904 2905 struct list_head q_full_list; 2906 uint32_t num_pend_cmds; 2907 uint32_t num_qfull_cmds_alloc; 2908 uint32_t num_qfull_cmds_dropped; 2909 spinlock_t q_full_lock; 2910 uint32_t leak_exchg_thresh_hold; 2911 }; 2912 2913 #define MAX_QFULL_CMDS_ALLOC 8192 2914 #define Q_FULL_THRESH_HOLD_PERCENT 90 2915 #define Q_FULL_THRESH_HOLD(ha) \ 2916 ((ha->fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 2917 2918 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 2919 2920 /* 2921 * Qlogic host adapter specific data structure. 2922 */ 2923 struct qla_hw_data { 2924 struct pci_dev *pdev; 2925 /* SRB cache. */ 2926 #define SRB_MIN_REQ 128 2927 mempool_t *srb_mempool; 2928 2929 volatile struct { 2930 uint32_t mbox_int :1; 2931 uint32_t mbox_busy :1; 2932 uint32_t disable_risc_code_load :1; 2933 uint32_t enable_64bit_addressing :1; 2934 uint32_t enable_lip_reset :1; 2935 uint32_t enable_target_reset :1; 2936 uint32_t enable_lip_full_login :1; 2937 uint32_t enable_led_scheme :1; 2938 2939 uint32_t msi_enabled :1; 2940 uint32_t msix_enabled :1; 2941 uint32_t disable_serdes :1; 2942 uint32_t gpsc_supported :1; 2943 uint32_t npiv_supported :1; 2944 uint32_t pci_channel_io_perm_failure :1; 2945 uint32_t fce_enabled :1; 2946 uint32_t fac_supported :1; 2947 2948 uint32_t chip_reset_done :1; 2949 uint32_t running_gold_fw :1; 2950 uint32_t eeh_busy :1; 2951 uint32_t cpu_affinity_enabled :1; 2952 uint32_t disable_msix_handshake :1; 2953 uint32_t fcp_prio_enabled :1; 2954 uint32_t isp82xx_fw_hung:1; 2955 uint32_t nic_core_hung:1; 2956 2957 uint32_t quiesce_owner:1; 2958 uint32_t nic_core_reset_hdlr_active:1; 2959 uint32_t nic_core_reset_owner:1; 2960 uint32_t isp82xx_no_md_cap:1; 2961 uint32_t host_shutting_down:1; 2962 uint32_t idc_compl_status:1; 2963 2964 uint32_t mr_reset_hdlr_active:1; 2965 uint32_t mr_intr_valid:1; 2966 uint32_t fawwpn_enabled:1; 2967 /* 35 bits */ 2968 } flags; 2969 2970 /* This spinlock is used to protect "io transactions", you must 2971 * acquire it before doing any IO to the card, eg with RD_REG*() and 2972 * WRT_REG*() for the duration of your entire commandtransaction. 2973 * 2974 * This spinlock is of lower priority than the io request lock. 2975 */ 2976 2977 spinlock_t hardware_lock ____cacheline_aligned; 2978 int bars; 2979 int mem_only; 2980 device_reg_t *iobase; /* Base I/O address */ 2981 resource_size_t pio_address; 2982 2983 #define MIN_IOBASE_LEN 0x100 2984 dma_addr_t bar0_hdl; 2985 2986 void __iomem *cregbase; 2987 dma_addr_t bar2_hdl; 2988 #define BAR0_LEN_FX00 (1024 * 1024) 2989 #define BAR2_LEN_FX00 (128 * 1024) 2990 2991 uint32_t rqstq_intr_code; 2992 uint32_t mbx_intr_code; 2993 uint32_t req_que_len; 2994 uint32_t rsp_que_len; 2995 uint32_t req_que_off; 2996 uint32_t rsp_que_off; 2997 2998 /* Multi queue data structs */ 2999 device_reg_t *mqiobase; 3000 device_reg_t *msixbase; 3001 uint16_t msix_count; 3002 uint8_t mqenable; 3003 struct req_que **req_q_map; 3004 struct rsp_que **rsp_q_map; 3005 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3006 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3007 uint8_t max_req_queues; 3008 uint8_t max_rsp_queues; 3009 struct qla_npiv_entry *npiv_info; 3010 uint16_t nvram_npiv_size; 3011 3012 uint16_t switch_cap; 3013 #define FLOGI_SEQ_DEL BIT_8 3014 #define FLOGI_MID_SUPPORT BIT_10 3015 #define FLOGI_VSAN_SUPPORT BIT_12 3016 #define FLOGI_SP_SUPPORT BIT_13 3017 3018 uint8_t port_no; /* Physical port of adapter */ 3019 3020 /* Timeout timers. */ 3021 uint8_t loop_down_abort_time; /* port down timer */ 3022 atomic_t loop_down_timer; /* loop down timer */ 3023 uint8_t link_down_timeout; /* link down timeout */ 3024 uint16_t max_loop_id; 3025 uint16_t max_fibre_devices; /* Maximum number of targets */ 3026 3027 uint16_t fb_rev; 3028 uint16_t min_external_loopid; /* First external loop Id */ 3029 3030 #define PORT_SPEED_UNKNOWN 0xFFFF 3031 #define PORT_SPEED_1GB 0x00 3032 #define PORT_SPEED_2GB 0x01 3033 #define PORT_SPEED_4GB 0x03 3034 #define PORT_SPEED_8GB 0x04 3035 #define PORT_SPEED_16GB 0x05 3036 #define PORT_SPEED_32GB 0x06 3037 #define PORT_SPEED_10GB 0x13 3038 uint16_t link_data_rate; /* F/W operating speed */ 3039 3040 uint8_t current_topology; 3041 uint8_t prev_topology; 3042 #define ISP_CFG_NL 1 3043 #define ISP_CFG_N 2 3044 #define ISP_CFG_FL 4 3045 #define ISP_CFG_F 8 3046 3047 uint8_t operating_mode; /* F/W operating mode */ 3048 #define LOOP 0 3049 #define P2P 1 3050 #define LOOP_P2P 2 3051 #define P2P_LOOP 3 3052 uint8_t interrupts_on; 3053 uint32_t isp_abort_cnt; 3054 3055 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3056 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3057 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3058 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3059 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3060 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3061 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3062 3063 uint32_t device_type; 3064 #define DT_ISP2100 BIT_0 3065 #define DT_ISP2200 BIT_1 3066 #define DT_ISP2300 BIT_2 3067 #define DT_ISP2312 BIT_3 3068 #define DT_ISP2322 BIT_4 3069 #define DT_ISP6312 BIT_5 3070 #define DT_ISP6322 BIT_6 3071 #define DT_ISP2422 BIT_7 3072 #define DT_ISP2432 BIT_8 3073 #define DT_ISP5422 BIT_9 3074 #define DT_ISP5432 BIT_10 3075 #define DT_ISP2532 BIT_11 3076 #define DT_ISP8432 BIT_12 3077 #define DT_ISP8001 BIT_13 3078 #define DT_ISP8021 BIT_14 3079 #define DT_ISP2031 BIT_15 3080 #define DT_ISP8031 BIT_16 3081 #define DT_ISPFX00 BIT_17 3082 #define DT_ISP8044 BIT_18 3083 #define DT_ISP2071 BIT_19 3084 #define DT_ISP2271 BIT_20 3085 #define DT_ISP_LAST (DT_ISP2271 << 1) 3086 3087 #define DT_T10_PI BIT_25 3088 #define DT_IIDMA BIT_26 3089 #define DT_FWI2 BIT_27 3090 #define DT_ZIO_SUPPORTED BIT_28 3091 #define DT_OEM_001 BIT_29 3092 #define DT_ISP2200A BIT_30 3093 #define DT_EXTENDED_IDS BIT_31 3094 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 3095 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3096 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3097 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3098 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3099 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3100 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3101 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3102 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3103 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3104 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3105 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3106 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3107 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3108 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3109 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3110 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3111 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3112 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3113 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3114 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3115 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3116 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3117 3118 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3119 IS_QLA6312(ha) || IS_QLA6322(ha)) 3120 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3121 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3122 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3123 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3124 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3125 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha)) 3126 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3127 IS_QLA84XX(ha)) 3128 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3129 IS_QLA8031(ha) || IS_QLA8044(ha)) 3130 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3131 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3132 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3133 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3134 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3135 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 3136 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3137 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3138 IS_QLA27XX(ha)) 3139 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3140 IS_QLA27XX(ha)) 3141 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3142 3143 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3144 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3145 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3146 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3147 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3148 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3149 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3150 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3151 IS_QLA27XX(ha)) 3152 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3153 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3154 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3155 ((ha)->fw_attributes_ext[0] & BIT_0)) 3156 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha)) 3157 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha)) 3158 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3159 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha)) 3160 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3161 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3162 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha)) 3163 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3164 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3165 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3166 3167 /* HBA serial number */ 3168 uint8_t serial0; 3169 uint8_t serial1; 3170 uint8_t serial2; 3171 3172 /* NVRAM configuration data */ 3173 #define MAX_NVRAM_SIZE 4096 3174 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3175 uint16_t nvram_size; 3176 uint16_t nvram_base; 3177 void *nvram; 3178 uint16_t vpd_size; 3179 uint16_t vpd_base; 3180 void *vpd; 3181 3182 uint16_t loop_reset_delay; 3183 uint8_t retry_count; 3184 uint8_t login_timeout; 3185 uint16_t r_a_tov; 3186 int port_down_retry_count; 3187 uint8_t mbx_count; 3188 uint8_t aen_mbx_count; 3189 3190 uint32_t login_retry_count; 3191 /* SNS command interfaces. */ 3192 ms_iocb_entry_t *ms_iocb; 3193 dma_addr_t ms_iocb_dma; 3194 struct ct_sns_pkt *ct_sns; 3195 dma_addr_t ct_sns_dma; 3196 /* SNS command interfaces for 2200. */ 3197 struct sns_cmd_pkt *sns_cmd; 3198 dma_addr_t sns_cmd_dma; 3199 3200 #define SFP_DEV_SIZE 256 3201 #define SFP_BLOCK_SIZE 64 3202 void *sfp_data; 3203 dma_addr_t sfp_data_dma; 3204 3205 #define XGMAC_DATA_SIZE 4096 3206 void *xgmac_data; 3207 dma_addr_t xgmac_data_dma; 3208 3209 #define DCBX_TLV_DATA_SIZE 4096 3210 void *dcbx_tlv; 3211 dma_addr_t dcbx_tlv_dma; 3212 3213 struct task_struct *dpc_thread; 3214 uint8_t dpc_active; /* DPC routine is active */ 3215 3216 dma_addr_t gid_list_dma; 3217 struct gid_list_info *gid_list; 3218 int gid_list_info_size; 3219 3220 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3221 #define DMA_POOL_SIZE 256 3222 struct dma_pool *s_dma_pool; 3223 3224 dma_addr_t init_cb_dma; 3225 init_cb_t *init_cb; 3226 int init_cb_size; 3227 dma_addr_t ex_init_cb_dma; 3228 struct ex_init_cb_81xx *ex_init_cb; 3229 3230 void *async_pd; 3231 dma_addr_t async_pd_dma; 3232 3233 void *swl; 3234 3235 /* These are used by mailbox operations. */ 3236 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3237 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3238 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3239 3240 mbx_cmd_t *mcp; 3241 struct mbx_cmd_32 *mcp32; 3242 3243 unsigned long mbx_cmd_flags; 3244 #define MBX_INTERRUPT 1 3245 #define MBX_INTR_WAIT 2 3246 #define MBX_UPDATE_FLASH_ACTIVE 3 3247 3248 struct mutex vport_lock; /* Virtual port synchronization */ 3249 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3250 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3251 struct completion mbx_intr_comp; /* Used for completion notification */ 3252 struct completion dcbx_comp; /* For set port config notification */ 3253 struct completion lb_portup_comp; /* Used to wait for link up during 3254 * loopback */ 3255 #define DCBX_COMP_TIMEOUT 20 3256 #define LB_PORTUP_COMP_TIMEOUT 10 3257 3258 int notify_dcbx_comp; 3259 int notify_lb_portup_comp; 3260 struct mutex selflogin_lock; 3261 3262 /* Basic firmware related information. */ 3263 uint16_t fw_major_version; 3264 uint16_t fw_minor_version; 3265 uint16_t fw_subminor_version; 3266 uint16_t fw_attributes; 3267 uint16_t fw_attributes_h; 3268 uint16_t fw_attributes_ext[2]; 3269 uint32_t fw_memory_size; 3270 uint32_t fw_transfer_size; 3271 uint32_t fw_srisc_address; 3272 #define RISC_START_ADDRESS_2100 0x1000 3273 #define RISC_START_ADDRESS_2300 0x800 3274 #define RISC_START_ADDRESS_2400 0x100000 3275 uint16_t fw_xcb_count; 3276 uint16_t fw_iocb_count; 3277 3278 uint32_t fw_shared_ram_start; 3279 uint32_t fw_shared_ram_end; 3280 3281 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3282 uint8_t fw_seriallink_options[4]; 3283 uint16_t fw_seriallink_options24[4]; 3284 3285 uint8_t mpi_version[3]; 3286 uint32_t mpi_capabilities; 3287 uint8_t phy_version[3]; 3288 3289 /* Firmware dump template */ 3290 void *fw_dump_template; 3291 uint32_t fw_dump_template_len; 3292 /* Firmware dump information. */ 3293 struct qla2xxx_fw_dump *fw_dump; 3294 uint32_t fw_dump_len; 3295 int fw_dumped; 3296 unsigned long fw_dump_cap_flags; 3297 #define RISC_PAUSE_CMPL 0 3298 #define DMA_SHUTDOWN_CMPL 1 3299 #define ISP_RESET_CMPL 2 3300 #define RISC_RDY_AFT_RESET 3 3301 #define RISC_SRAM_DUMP_CMPL 4 3302 #define RISC_EXT_MEM_DUMP_CMPL 5 3303 int fw_dump_reading; 3304 int prev_minidump_failed; 3305 dma_addr_t eft_dma; 3306 void *eft; 3307 /* Current size of mctp dump is 0x086064 bytes */ 3308 #define MCTP_DUMP_SIZE 0x086064 3309 dma_addr_t mctp_dump_dma; 3310 void *mctp_dump; 3311 int mctp_dumped; 3312 int mctp_dump_reading; 3313 uint32_t chain_offset; 3314 struct dentry *dfs_dir; 3315 struct dentry *dfs_fce; 3316 dma_addr_t fce_dma; 3317 void *fce; 3318 uint32_t fce_bufs; 3319 uint16_t fce_mb[8]; 3320 uint64_t fce_wr, fce_rd; 3321 struct mutex fce_mutex; 3322 3323 uint32_t pci_attr; 3324 uint16_t chip_revision; 3325 3326 uint16_t product_id[4]; 3327 3328 uint8_t model_number[16+1]; 3329 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3330 char model_desc[80]; 3331 uint8_t adapter_id[16+1]; 3332 3333 /* Option ROM information. */ 3334 char *optrom_buffer; 3335 uint32_t optrom_size; 3336 int optrom_state; 3337 #define QLA_SWAITING 0 3338 #define QLA_SREADING 1 3339 #define QLA_SWRITING 2 3340 uint32_t optrom_region_start; 3341 uint32_t optrom_region_size; 3342 struct mutex optrom_mutex; 3343 3344 /* PCI expansion ROM image information. */ 3345 #define ROM_CODE_TYPE_BIOS 0 3346 #define ROM_CODE_TYPE_FCODE 1 3347 #define ROM_CODE_TYPE_EFI 3 3348 uint8_t bios_revision[2]; 3349 uint8_t efi_revision[2]; 3350 uint8_t fcode_revision[16]; 3351 uint32_t fw_revision[4]; 3352 3353 uint32_t gold_fw_version[4]; 3354 3355 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3356 uint32_t flash_conf_off; 3357 uint32_t flash_data_off; 3358 uint32_t nvram_conf_off; 3359 uint32_t nvram_data_off; 3360 3361 uint32_t fdt_wrt_disable; 3362 uint32_t fdt_wrt_enable; 3363 uint32_t fdt_erase_cmd; 3364 uint32_t fdt_block_size; 3365 uint32_t fdt_unprotect_sec_cmd; 3366 uint32_t fdt_protect_sec_cmd; 3367 uint32_t fdt_wrt_sts_reg_cmd; 3368 3369 uint32_t flt_region_flt; 3370 uint32_t flt_region_fdt; 3371 uint32_t flt_region_boot; 3372 uint32_t flt_region_fw; 3373 uint32_t flt_region_vpd_nvram; 3374 uint32_t flt_region_vpd; 3375 uint32_t flt_region_nvram; 3376 uint32_t flt_region_npiv_conf; 3377 uint32_t flt_region_gold_fw; 3378 uint32_t flt_region_fcp_prio; 3379 uint32_t flt_region_bootload; 3380 3381 /* Needed for BEACON */ 3382 uint16_t beacon_blink_led; 3383 uint8_t beacon_color_state; 3384 #define QLA_LED_GRN_ON 0x01 3385 #define QLA_LED_YLW_ON 0x02 3386 #define QLA_LED_ABR_ON 0x04 3387 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3388 /* ISP2322: red, green, amber. */ 3389 uint16_t zio_mode; 3390 uint16_t zio_timer; 3391 3392 struct qla_msix_entry *msix_entries; 3393 3394 struct list_head vp_list; /* list of VP */ 3395 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3396 sizeof(unsigned long)]; 3397 uint16_t num_vhosts; /* number of vports created */ 3398 uint16_t num_vsans; /* number of vsan created */ 3399 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3400 int cur_vport_count; 3401 3402 struct qla_chip_state_84xx *cs84xx; 3403 struct qla_statistics qla_stats; 3404 struct isp_operations *isp_ops; 3405 struct workqueue_struct *wq; 3406 struct qlfc_fw fw_buf; 3407 3408 /* FCP_CMND priority support */ 3409 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3410 3411 struct dma_pool *dl_dma_pool; 3412 #define DSD_LIST_DMA_POOL_SIZE 512 3413 3414 struct dma_pool *fcp_cmnd_dma_pool; 3415 mempool_t *ctx_mempool; 3416 #define FCP_CMND_DMA_POOL_SIZE 512 3417 3418 unsigned long nx_pcibase; /* Base I/O address */ 3419 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ 3420 unsigned long nxdb_wr_ptr; /* Door bell write pointer */ 3421 3422 uint32_t crb_win; 3423 uint32_t curr_window; 3424 uint32_t ddr_mn_window; 3425 unsigned long mn_win_crb; 3426 unsigned long ms_win_crb; 3427 int qdr_sn_window; 3428 uint32_t fcoe_dev_init_timeout; 3429 uint32_t fcoe_reset_timeout; 3430 rwlock_t hw_lock; 3431 uint16_t portnum; /* port number */ 3432 int link_width; 3433 struct fw_blob *hablob; 3434 struct qla82xx_legacy_intr_set nx_legacy_intr; 3435 3436 uint16_t gbl_dsd_inuse; 3437 uint16_t gbl_dsd_avail; 3438 struct list_head gbl_dsd_list; 3439 #define NUM_DSD_CHAIN 4096 3440 3441 uint8_t fw_type; 3442 __le32 file_prd_off; /* File firmware product offset */ 3443 3444 uint32_t md_template_size; 3445 void *md_tmplt_hdr; 3446 dma_addr_t md_tmplt_hdr_dma; 3447 void *md_dump; 3448 uint32_t md_dump_size; 3449 3450 void *loop_id_map; 3451 3452 /* QLA83XX IDC specific fields */ 3453 uint32_t idc_audit_ts; 3454 uint32_t idc_extend_tmo; 3455 3456 /* DPC low-priority workqueue */ 3457 struct workqueue_struct *dpc_lp_wq; 3458 struct work_struct idc_aen; 3459 /* DPC high-priority workqueue */ 3460 struct workqueue_struct *dpc_hp_wq; 3461 struct work_struct nic_core_reset; 3462 struct work_struct idc_state_handler; 3463 struct work_struct nic_core_unrecoverable; 3464 struct work_struct board_disable; 3465 3466 struct mr_data_fx00 mr; 3467 uint32_t chip_reset; 3468 3469 struct qlt_hw_data tgt; 3470 int allow_cna_fw_dump; 3471 }; 3472 3473 /* 3474 * Qlogic scsi host structure 3475 */ 3476 typedef struct scsi_qla_host { 3477 struct list_head list; 3478 struct list_head vp_fcports; /* list of fcports */ 3479 struct list_head work_list; 3480 spinlock_t work_lock; 3481 3482 /* Commonly used flags and state information. */ 3483 struct Scsi_Host *host; 3484 unsigned long host_no; 3485 uint8_t host_str[16]; 3486 3487 volatile struct { 3488 uint32_t init_done :1; 3489 uint32_t online :1; 3490 uint32_t reset_active :1; 3491 3492 uint32_t management_server_logged_in :1; 3493 uint32_t process_response_queue :1; 3494 uint32_t difdix_supported:1; 3495 uint32_t delete_progress:1; 3496 3497 uint32_t fw_tgt_reported:1; 3498 } flags; 3499 3500 atomic_t loop_state; 3501 #define LOOP_TIMEOUT 1 3502 #define LOOP_DOWN 2 3503 #define LOOP_UP 3 3504 #define LOOP_UPDATE 4 3505 #define LOOP_READY 5 3506 #define LOOP_DEAD 6 3507 3508 unsigned long dpc_flags; 3509 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3510 #define RESET_ACTIVE 1 3511 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3512 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3513 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3514 #define LOOP_RESYNC_ACTIVE 5 3515 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3516 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3517 #define RELOGIN_NEEDED 8 3518 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3519 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3520 #define BEACON_BLINK_NEEDED 11 3521 #define REGISTER_FDMI_NEEDED 12 3522 #define FCPORT_UPDATE_NEEDED 13 3523 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3524 #define UNLOADING 15 3525 #define NPIV_CONFIG_NEEDED 16 3526 #define ISP_UNRECOVERABLE 17 3527 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3528 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3529 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3530 #define SCR_PENDING 21 /* SCR in target mode */ 3531 #define PORT_UPDATE_NEEDED 22 3532 #define FX00_RESET_RECOVERY 23 3533 #define FX00_TARGET_SCAN 24 3534 #define FX00_CRITEMP_RECOVERY 25 3535 #define FX00_HOST_INFO_RESEND 26 3536 3537 unsigned long pci_flags; 3538 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 3539 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 3540 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 3541 3542 uint32_t device_flags; 3543 #define SWITCH_FOUND BIT_0 3544 #define DFLG_NO_CABLE BIT_1 3545 #define DFLG_DEV_FAILED BIT_5 3546 3547 /* ISP configuration data. */ 3548 uint16_t loop_id; /* Host adapter loop id */ 3549 uint16_t self_login_loop_id; /* host adapter loop id 3550 * get it on self login 3551 */ 3552 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3553 * no need of allocating it for 3554 * each command 3555 */ 3556 3557 port_id_t d_id; /* Host adapter port id */ 3558 uint8_t marker_needed; 3559 uint16_t mgmt_svr_loop_id; 3560 3561 3562 3563 /* Timeout timers. */ 3564 uint8_t loop_down_abort_time; /* port down timer */ 3565 atomic_t loop_down_timer; /* loop down timer */ 3566 uint8_t link_down_timeout; /* link down timeout */ 3567 3568 uint32_t timer_active; 3569 struct timer_list timer; 3570 3571 uint8_t node_name[WWN_SIZE]; 3572 uint8_t port_name[WWN_SIZE]; 3573 uint8_t fabric_node_name[WWN_SIZE]; 3574 3575 uint16_t fcoe_vlan_id; 3576 uint16_t fcoe_fcf_idx; 3577 uint8_t fcoe_vn_port_mac[6]; 3578 3579 uint32_t vp_abort_cnt; 3580 3581 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3582 uint16_t vp_idx; /* vport ID */ 3583 3584 unsigned long vp_flags; 3585 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3586 #define VP_CREATE_NEEDED 1 3587 #define VP_BIND_NEEDED 2 3588 #define VP_DELETE_NEEDED 3 3589 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3590 atomic_t vp_state; 3591 #define VP_OFFLINE 0 3592 #define VP_ACTIVE 1 3593 #define VP_FAILED 2 3594 // #define VP_DISABLE 3 3595 uint16_t vp_err_state; 3596 uint16_t vp_prev_err_state; 3597 #define VP_ERR_UNKWN 0 3598 #define VP_ERR_PORTDWN 1 3599 #define VP_ERR_FAB_UNSUPPORTED 2 3600 #define VP_ERR_FAB_NORESOURCES 3 3601 #define VP_ERR_FAB_LOGOUT 4 3602 #define VP_ERR_ADAP_NORESOURCES 5 3603 struct qla_hw_data *hw; 3604 struct scsi_qlt_host vha_tgt; 3605 struct req_que *req; 3606 int fw_heartbeat_counter; 3607 int seconds_since_last_heartbeat; 3608 struct fc_host_statistics fc_host_stat; 3609 struct qla_statistics qla_stats; 3610 struct bidi_statistics bidi_stats; 3611 3612 atomic_t vref_count; 3613 struct qla8044_reset_template reset_tmplt; 3614 } scsi_qla_host_t; 3615 3616 #define SET_VP_IDX 1 3617 #define SET_AL_PA 2 3618 #define RESET_VP_IDX 3 3619 #define RESET_AL_PA 4 3620 struct qla_tgt_vp_map { 3621 uint8_t idx; 3622 scsi_qla_host_t *vha; 3623 }; 3624 3625 /* 3626 * Macros to help code, maintain, etc. 3627 */ 3628 #define LOOP_TRANSITION(ha) \ 3629 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3630 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3631 atomic_read(&ha->loop_state) == LOOP_DOWN) 3632 3633 #define STATE_TRANSITION(ha) \ 3634 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3635 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3636 3637 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3638 atomic_inc(&__vha->vref_count); \ 3639 mb(); \ 3640 if (__vha->flags.delete_progress) { \ 3641 atomic_dec(&__vha->vref_count); \ 3642 __bail = 1; \ 3643 } else { \ 3644 __bail = 0; \ 3645 } \ 3646 } while (0) 3647 3648 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3649 atomic_dec(&__vha->vref_count); \ 3650 } while (0) 3651 3652 /* 3653 * qla2x00 local function return status codes 3654 */ 3655 #define MBS_MASK 0x3fff 3656 3657 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3658 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3659 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3660 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3661 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3662 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3663 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3664 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3665 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3666 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3667 3668 #define QLA_FUNCTION_TIMEOUT 0x100 3669 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3670 #define QLA_FUNCTION_FAILED 0x102 3671 #define QLA_MEMORY_ALLOC_FAILED 0x103 3672 #define QLA_LOCK_TIMEOUT 0x104 3673 #define QLA_ABORTED 0x105 3674 #define QLA_SUSPENDED 0x106 3675 #define QLA_BUSY 0x107 3676 #define QLA_ALREADY_REGISTERED 0x109 3677 3678 #define NVRAM_DELAY() udelay(10) 3679 3680 /* 3681 * Flash support definitions 3682 */ 3683 #define OPTROM_SIZE_2300 0x20000 3684 #define OPTROM_SIZE_2322 0x100000 3685 #define OPTROM_SIZE_24XX 0x100000 3686 #define OPTROM_SIZE_25XX 0x200000 3687 #define OPTROM_SIZE_81XX 0x400000 3688 #define OPTROM_SIZE_82XX 0x800000 3689 #define OPTROM_SIZE_83XX 0x1000000 3690 3691 #define OPTROM_BURST_SIZE 0x1000 3692 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3693 3694 #define QLA_DSDS_PER_IOCB 37 3695 3696 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3697 3698 #define QLA_SG_ALL 1024 3699 3700 enum nexus_wait_type { 3701 WAIT_HOST = 0, 3702 WAIT_TARGET, 3703 WAIT_LUN, 3704 }; 3705 3706 #include "qla_gbl.h" 3707 #include "qla_dbg.h" 3708 #include "qla_inline.h" 3709 #endif 3710