1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/aer.h> 26 #include <linux/mutex.h> 27 #include <linux/btree.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include <uapi/scsi/fc/fc_els.h> 37 38 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 39 typedef struct { 40 uint8_t domain; 41 uint8_t area; 42 uint8_t al_pa; 43 } be_id_t; 44 45 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 46 typedef struct { 47 uint8_t al_pa; 48 uint8_t area; 49 uint8_t domain; 50 } le_id_t; 51 52 /* 53 * 24 bit port ID type definition. 54 */ 55 typedef union { 56 uint32_t b24 : 24; 57 struct { 58 #ifdef __BIG_ENDIAN 59 uint8_t domain; 60 uint8_t area; 61 uint8_t al_pa; 62 #elif defined(__LITTLE_ENDIAN) 63 uint8_t al_pa; 64 uint8_t area; 65 uint8_t domain; 66 #else 67 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 68 #endif 69 uint8_t rsvd_1; 70 } b; 71 } port_id_t; 72 #define INVALID_PORT_ID 0xFFFFFF 73 74 #include "qla_bsg.h" 75 #include "qla_dsd.h" 76 #include "qla_nx.h" 77 #include "qla_nx2.h" 78 #include "qla_nvme.h" 79 #define QLA2XXX_DRIVER_NAME "qla2xxx" 80 #define QLA2XXX_APIDEV "ql2xapidev" 81 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 82 83 /* 84 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 85 * but that's fine as we don't look at the last 24 ones for 86 * ISP2100 HBAs. 87 */ 88 #define MAILBOX_REGISTER_COUNT_2100 8 89 #define MAILBOX_REGISTER_COUNT_2200 24 90 #define MAILBOX_REGISTER_COUNT 32 91 92 #define QLA2200A_RISC_ROM_VER 4 93 #define FPM_2300 6 94 #define FPM_2310 7 95 96 #include "qla_settings.h" 97 98 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 99 100 /* 101 * Data bit definitions 102 */ 103 #define BIT_0 0x1 104 #define BIT_1 0x2 105 #define BIT_2 0x4 106 #define BIT_3 0x8 107 #define BIT_4 0x10 108 #define BIT_5 0x20 109 #define BIT_6 0x40 110 #define BIT_7 0x80 111 #define BIT_8 0x100 112 #define BIT_9 0x200 113 #define BIT_10 0x400 114 #define BIT_11 0x800 115 #define BIT_12 0x1000 116 #define BIT_13 0x2000 117 #define BIT_14 0x4000 118 #define BIT_15 0x8000 119 #define BIT_16 0x10000 120 #define BIT_17 0x20000 121 #define BIT_18 0x40000 122 #define BIT_19 0x80000 123 #define BIT_20 0x100000 124 #define BIT_21 0x200000 125 #define BIT_22 0x400000 126 #define BIT_23 0x800000 127 #define BIT_24 0x1000000 128 #define BIT_25 0x2000000 129 #define BIT_26 0x4000000 130 #define BIT_27 0x8000000 131 #define BIT_28 0x10000000 132 #define BIT_29 0x20000000 133 #define BIT_30 0x40000000 134 #define BIT_31 0x80000000 135 136 #define LSB(x) ((uint8_t)(x)) 137 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 138 139 #define LSW(x) ((uint16_t)(x)) 140 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 141 142 #define LSD(x) ((uint32_t)((uint64_t)(x))) 143 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 144 145 static inline uint32_t make_handle(uint16_t x, uint16_t y) 146 { 147 return ((uint32_t)x << 16) | y; 148 } 149 150 /* 151 * I/O register 152 */ 153 154 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 155 { 156 return readb(addr); 157 } 158 159 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 160 { 161 return readw(addr); 162 } 163 164 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 165 { 166 return readl(addr); 167 } 168 169 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 170 { 171 return readb_relaxed(addr); 172 } 173 174 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 175 { 176 return readw_relaxed(addr); 177 } 178 179 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 180 { 181 return readl_relaxed(addr); 182 } 183 184 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 185 { 186 return writeb(data, addr); 187 } 188 189 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 190 { 191 return writew(data, addr); 192 } 193 194 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 195 { 196 return writel(data, addr); 197 } 198 199 /* 200 * ISP83XX specific remote register addresses 201 */ 202 #define QLA83XX_LED_PORT0 0x00201320 203 #define QLA83XX_LED_PORT1 0x00201328 204 #define QLA83XX_IDC_DEV_STATE 0x22102384 205 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 206 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 207 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 208 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 209 #define QLA83XX_IDC_CONTROL 0x22102390 210 #define QLA83XX_IDC_AUDIT 0x22102394 211 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 212 #define QLA83XX_DRIVER_LOCKID 0x22102104 213 #define QLA83XX_DRIVER_LOCK 0x8111c028 214 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 215 #define QLA83XX_FLASH_LOCKID 0x22102100 216 #define QLA83XX_FLASH_LOCK 0x8111c010 217 #define QLA83XX_FLASH_UNLOCK 0x8111c014 218 #define QLA83XX_DEV_PARTINFO1 0x221023e0 219 #define QLA83XX_DEV_PARTINFO2 0x221023e4 220 #define QLA83XX_FW_HEARTBEAT 0x221020b0 221 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 222 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 223 224 /* 83XX: Macros defining 8200 AEN Reason codes */ 225 #define IDC_DEVICE_STATE_CHANGE BIT_0 226 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 227 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 228 #define IDC_HEARTBEAT_FAILURE BIT_3 229 230 /* 83XX: Macros defining 8200 AEN Error-levels */ 231 #define ERR_LEVEL_NON_FATAL 0x1 232 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 233 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 234 235 /* 83XX: Macros for IDC Version */ 236 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 237 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 238 239 /* 83XX: Macros for scheduling dpc tasks */ 240 #define QLA83XX_NIC_CORE_RESET 0x1 241 #define QLA83XX_IDC_STATE_HANDLER 0x2 242 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 243 244 /* 83XX: Macros for defining IDC-Control bits */ 245 #define QLA83XX_IDC_RESET_DISABLED BIT_0 246 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 247 248 /* 83XX: Macros for different timeouts */ 249 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 250 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 251 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 252 253 /* 83XX: Macros for defining class in DEV-Partition Info register */ 254 #define QLA83XX_CLASS_TYPE_NONE 0x0 255 #define QLA83XX_CLASS_TYPE_NIC 0x1 256 #define QLA83XX_CLASS_TYPE_FCOE 0x2 257 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 258 259 /* 83XX: Macros for IDC Lock-Recovery stages */ 260 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 261 * lock-recovery 262 */ 263 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 264 265 /* 83XX: Macros for IDC Audit type */ 266 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 267 * dev-state change to NEED-RESET 268 * or NEED-QUIESCENT 269 */ 270 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 271 * reset-recovery completion is 272 * second 273 */ 274 /* ISP2031: Values for laser on/off */ 275 #define PORT_0_2031 0x00201340 276 #define PORT_1_2031 0x00201350 277 #define LASER_ON_2031 0x01800100 278 #define LASER_OFF_2031 0x01800180 279 280 /* 281 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 282 * 133Mhz slot. 283 */ 284 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 285 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 286 287 /* 288 * Fibre Channel device definitions. 289 */ 290 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 291 #define MAX_FIBRE_DEVICES_2100 512 292 #define MAX_FIBRE_DEVICES_2400 2048 293 #define MAX_FIBRE_DEVICES_LOOP 128 294 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 295 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 296 #define MAX_FIBRE_LUNS 0xFFFF 297 #define MAX_HOST_COUNT 16 298 299 /* 300 * Host adapter default definitions. 301 */ 302 #define MAX_BUSES 1 /* We only have one bus today */ 303 #define MIN_LUNS 8 304 #define MAX_LUNS MAX_FIBRE_LUNS 305 #define MAX_CMDS_PER_LUN 255 306 307 /* 308 * Fibre Channel device definitions. 309 */ 310 #define SNS_LAST_LOOP_ID_2100 0xfe 311 #define SNS_LAST_LOOP_ID_2300 0x7ff 312 313 #define LAST_LOCAL_LOOP_ID 0x7d 314 #define SNS_FL_PORT 0x7e 315 #define FABRIC_CONTROLLER 0x7f 316 #define SIMPLE_NAME_SERVER 0x80 317 #define SNS_FIRST_LOOP_ID 0x81 318 #define MANAGEMENT_SERVER 0xfe 319 #define BROADCAST 0xff 320 321 /* 322 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 323 * valid range of an N-PORT id is 0 through 0x7ef. 324 */ 325 #define NPH_LAST_HANDLE 0x7ee 326 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 327 #define NPH_SNS 0x7fc /* FFFFFC */ 328 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 329 #define NPH_F_PORT 0x7fe /* FFFFFE */ 330 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 331 332 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 333 334 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 335 #include "qla_fw.h" 336 337 struct name_list_extended { 338 struct get_name_list_extended *l; 339 dma_addr_t ldma; 340 struct list_head fcports; 341 u32 size; 342 u8 sent; 343 }; 344 345 struct els_reject { 346 struct fc_els_ls_rjt *c; 347 dma_addr_t cdma; 348 u16 size; 349 }; 350 351 /* 352 * Timeout timer counts in seconds 353 */ 354 #define PORT_RETRY_TIME 1 355 #define LOOP_DOWN_TIMEOUT 60 356 #define LOOP_DOWN_TIME 255 /* 240 */ 357 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 358 359 #define DEFAULT_OUTSTANDING_COMMANDS 4096 360 #define MIN_OUTSTANDING_COMMANDS 128 361 362 /* ISP request and response entry counts (37-65535) */ 363 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 364 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 365 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 366 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 367 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 368 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 369 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 370 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 371 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 372 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 373 #define FW_DEF_EXCHANGES_CNT 2048 374 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 375 #define REDUCE_EXCHANGES_CNT (8 * 1024) 376 377 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 378 379 struct req_que; 380 struct qla_tgt_sess; 381 382 /* 383 * SCSI Request Block 384 */ 385 struct srb_cmd { 386 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 387 uint32_t request_sense_length; 388 uint32_t fw_sense_length; 389 uint8_t *request_sense_ptr; 390 struct ct6_dsd *ct6_ctx; 391 struct crc_context *crc_ctx; 392 }; 393 394 /* 395 * SRB flag definitions 396 */ 397 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 398 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 399 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 400 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 401 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 402 #define SRB_WAKEUP_ON_COMP BIT_6 403 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 404 #define SRB_EDIF_CLEANUP_DELETE BIT_9 405 406 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 407 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 408 #define ISP_REG16_DISCONNECT 0xFFFF 409 410 static inline le_id_t be_id_to_le(be_id_t id) 411 { 412 le_id_t res; 413 414 res.domain = id.domain; 415 res.area = id.area; 416 res.al_pa = id.al_pa; 417 418 return res; 419 } 420 421 static inline be_id_t le_id_to_be(le_id_t id) 422 { 423 be_id_t res; 424 425 res.domain = id.domain; 426 res.area = id.area; 427 res.al_pa = id.al_pa; 428 429 return res; 430 } 431 432 static inline port_id_t be_to_port_id(be_id_t id) 433 { 434 port_id_t res; 435 436 res.b.domain = id.domain; 437 res.b.area = id.area; 438 res.b.al_pa = id.al_pa; 439 res.b.rsvd_1 = 0; 440 441 return res; 442 } 443 444 static inline be_id_t port_id_to_be_id(port_id_t port_id) 445 { 446 be_id_t res; 447 448 res.domain = port_id.b.domain; 449 res.area = port_id.b.area; 450 res.al_pa = port_id.b.al_pa; 451 452 return res; 453 } 454 455 struct els_logo_payload { 456 uint8_t opcode; 457 uint8_t rsvd[3]; 458 uint8_t s_id[3]; 459 uint8_t rsvd1[1]; 460 uint8_t wwpn[WWN_SIZE]; 461 }; 462 463 struct els_plogi_payload { 464 uint8_t opcode; 465 uint8_t rsvd[3]; 466 __be32 data[112 / 4]; 467 }; 468 469 struct ct_arg { 470 void *iocb; 471 u16 nport_handle; 472 dma_addr_t req_dma; 473 dma_addr_t rsp_dma; 474 u32 req_size; 475 u32 rsp_size; 476 u32 req_allocated_size; 477 u32 rsp_allocated_size; 478 void *req; 479 void *rsp; 480 port_id_t id; 481 }; 482 483 /* 484 * SRB extensions. 485 */ 486 struct srb_iocb { 487 union { 488 struct { 489 uint16_t flags; 490 #define SRB_LOGIN_RETRIED BIT_0 491 #define SRB_LOGIN_COND_PLOGI BIT_1 492 #define SRB_LOGIN_SKIP_PRLI BIT_2 493 #define SRB_LOGIN_NVME_PRLI BIT_3 494 #define SRB_LOGIN_PRLI_ONLY BIT_4 495 #define SRB_LOGIN_FCSP BIT_5 496 uint16_t data[2]; 497 u32 iop[2]; 498 } logio; 499 struct { 500 #define ELS_DCMD_TIMEOUT 20 501 #define ELS_DCMD_LOGO 0x5 502 uint32_t flags; 503 uint32_t els_cmd; 504 struct completion comp; 505 struct els_logo_payload *els_logo_pyld; 506 dma_addr_t els_logo_pyld_dma; 507 } els_logo; 508 struct els_plogi { 509 #define ELS_DCMD_PLOGI 0x3 510 uint32_t flags; 511 uint32_t els_cmd; 512 struct completion comp; 513 struct els_plogi_payload *els_plogi_pyld; 514 struct els_plogi_payload *els_resp_pyld; 515 u32 tx_size; 516 u32 rx_size; 517 dma_addr_t els_plogi_pyld_dma; 518 dma_addr_t els_resp_pyld_dma; 519 __le32 fw_status[3]; 520 __le16 comp_status; 521 __le16 len; 522 } els_plogi; 523 struct { 524 /* 525 * Values for flags field below are as 526 * defined in tsk_mgmt_entry struct 527 * for control_flags field in qla_fw.h. 528 */ 529 uint64_t lun; 530 uint32_t flags; 531 uint32_t data; 532 struct completion comp; 533 __le16 comp_status; 534 } tmf; 535 struct { 536 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 537 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 538 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 539 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 540 #define FXDISC_TIMEOUT 20 541 uint8_t flags; 542 uint32_t req_len; 543 uint32_t rsp_len; 544 void *req_addr; 545 void *rsp_addr; 546 dma_addr_t req_dma_handle; 547 dma_addr_t rsp_dma_handle; 548 __le32 adapter_id; 549 __le32 adapter_id_hi; 550 __le16 req_func_type; 551 __le32 req_data; 552 __le32 req_data_extra; 553 __le32 result; 554 __le32 seq_number; 555 __le16 fw_flags; 556 struct completion fxiocb_comp; 557 __le32 reserved_0; 558 uint8_t reserved_1; 559 } fxiocb; 560 struct { 561 uint32_t cmd_hndl; 562 __le16 comp_status; 563 __le16 req_que_no; 564 struct completion comp; 565 } abt; 566 struct ct_arg ctarg; 567 #define MAX_IOCB_MB_REG 28 568 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 569 struct { 570 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 571 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 572 void *out, *in; 573 dma_addr_t out_dma, in_dma; 574 struct completion comp; 575 int rc; 576 } mbx; 577 struct { 578 struct imm_ntfy_from_isp *ntfy; 579 } nack; 580 struct { 581 __le16 comp_status; 582 __le16 rsp_pyld_len; 583 uint8_t aen_op; 584 void *desc; 585 586 /* These are only used with ls4 requests */ 587 int cmd_len; 588 int rsp_len; 589 dma_addr_t cmd_dma; 590 dma_addr_t rsp_dma; 591 enum nvmefc_fcp_datadir dir; 592 uint32_t dl; 593 uint32_t timeout_sec; 594 struct list_head entry; 595 } nvme; 596 struct { 597 u16 cmd; 598 u16 vp_index; 599 } ctrlvp; 600 struct { 601 struct edif_sa_ctl *sa_ctl; 602 struct qla_sa_update_frame sa_frame; 603 } sa_update; 604 } u; 605 606 struct timer_list timer; 607 void (*timeout)(void *); 608 }; 609 610 /* Values for srb_ctx type */ 611 #define SRB_LOGIN_CMD 1 612 #define SRB_LOGOUT_CMD 2 613 #define SRB_ELS_CMD_RPT 3 614 #define SRB_ELS_CMD_HST 4 615 #define SRB_CT_CMD 5 616 #define SRB_ADISC_CMD 6 617 #define SRB_TM_CMD 7 618 #define SRB_SCSI_CMD 8 619 #define SRB_BIDI_CMD 9 620 #define SRB_FXIOCB_DCMD 10 621 #define SRB_FXIOCB_BCMD 11 622 #define SRB_ABT_CMD 12 623 #define SRB_ELS_DCMD 13 624 #define SRB_MB_IOCB 14 625 #define SRB_CT_PTHRU_CMD 15 626 #define SRB_NACK_PLOGI 16 627 #define SRB_NACK_PRLI 17 628 #define SRB_NACK_LOGO 18 629 #define SRB_NVME_CMD 19 630 #define SRB_NVME_LS 20 631 #define SRB_PRLI_CMD 21 632 #define SRB_CTRL_VP 22 633 #define SRB_PRLO_CMD 23 634 #define SRB_SA_UPDATE 25 635 #define SRB_ELS_CMD_HST_NOLOGIN 26 636 #define SRB_SA_REPLACE 27 637 638 struct qla_els_pt_arg { 639 u8 els_opcode; 640 u8 vp_idx; 641 __le16 nport_handle; 642 u16 control_flags, ox_id; 643 __le32 rx_xchg_address; 644 port_id_t did, sid; 645 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 646 dma_addr_t tx_addr, rx_addr; 647 648 }; 649 650 enum { 651 TYPE_SRB, 652 TYPE_TGT_CMD, 653 TYPE_TGT_TMCMD, /* task management */ 654 }; 655 656 struct iocb_resource { 657 u8 res_type; 658 u8 pad; 659 u16 iocb_cnt; 660 }; 661 662 struct bsg_cmd { 663 struct bsg_job *bsg_job; 664 union { 665 struct qla_els_pt_arg els_arg; 666 } u; 667 }; 668 669 typedef struct srb { 670 /* 671 * Do not move cmd_type field, it needs to 672 * line up with qla_tgt_cmd->cmd_type 673 */ 674 uint8_t cmd_type; 675 uint8_t pad[3]; 676 struct iocb_resource iores; 677 struct kref cmd_kref; /* need to migrate ref_count over to this */ 678 void *priv; 679 wait_queue_head_t nvme_ls_waitq; 680 struct fc_port *fcport; 681 struct scsi_qla_host *vha; 682 unsigned int start_timer:1; 683 684 uint32_t handle; 685 uint16_t flags; 686 uint16_t type; 687 const char *name; 688 int iocbs; 689 struct qla_qpair *qpair; 690 struct srb *cmd_sp; 691 struct list_head elem; 692 u32 gen1; /* scratch */ 693 u32 gen2; /* scratch */ 694 int rc; 695 int retry_count; 696 struct completion *comp; 697 union { 698 struct srb_iocb iocb_cmd; 699 struct bsg_job *bsg_job; 700 struct srb_cmd scmd; 701 struct bsg_cmd bsg_cmd; 702 } u; 703 struct { 704 bool remapped; 705 struct { 706 dma_addr_t dma; 707 void *buf; 708 uint len; 709 } req; 710 struct { 711 dma_addr_t dma; 712 void *buf; 713 uint len; 714 } rsp; 715 } remap; 716 /* 717 * Report completion status @res and call sp_put(@sp). @res is 718 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 719 * QLA_* status value. 720 */ 721 void (*done)(struct srb *sp, int res); 722 /* Stop the timer and free @sp. Only used by the FCP code. */ 723 void (*free)(struct srb *sp); 724 /* 725 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 726 * code. 727 */ 728 void (*put_fn)(struct kref *kref); 729 730 /* 731 * Report completion for asynchronous commands. 732 */ 733 void (*async_done)(struct srb *sp, int res); 734 } srb_t; 735 736 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 737 738 #define GET_CMD_SENSE_LEN(sp) \ 739 (sp->u.scmd.request_sense_length) 740 #define SET_CMD_SENSE_LEN(sp, len) \ 741 (sp->u.scmd.request_sense_length = len) 742 #define GET_CMD_SENSE_PTR(sp) \ 743 (sp->u.scmd.request_sense_ptr) 744 #define SET_CMD_SENSE_PTR(sp, ptr) \ 745 (sp->u.scmd.request_sense_ptr = ptr) 746 #define GET_FW_SENSE_LEN(sp) \ 747 (sp->u.scmd.fw_sense_length) 748 #define SET_FW_SENSE_LEN(sp, len) \ 749 (sp->u.scmd.fw_sense_length = len) 750 751 struct msg_echo_lb { 752 dma_addr_t send_dma; 753 dma_addr_t rcv_dma; 754 uint16_t req_sg_cnt; 755 uint16_t rsp_sg_cnt; 756 uint16_t options; 757 uint32_t transfer_size; 758 uint32_t iteration_count; 759 }; 760 761 /* 762 * ISP I/O Register Set structure definitions. 763 */ 764 struct device_reg_2xxx { 765 __le16 flash_address; /* Flash BIOS address */ 766 __le16 flash_data; /* Flash BIOS data */ 767 __le16 unused_1[1]; /* Gap */ 768 __le16 ctrl_status; /* Control/Status */ 769 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 770 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 771 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 772 773 __le16 ictrl; /* Interrupt control */ 774 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 775 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 776 777 __le16 istatus; /* Interrupt status */ 778 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 779 780 __le16 semaphore; /* Semaphore */ 781 __le16 nvram; /* NVRAM register. */ 782 #define NVR_DESELECT 0 783 #define NVR_BUSY BIT_15 784 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 785 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 786 #define NVR_DATA_IN BIT_3 787 #define NVR_DATA_OUT BIT_2 788 #define NVR_SELECT BIT_1 789 #define NVR_CLOCK BIT_0 790 791 #define NVR_WAIT_CNT 20000 792 793 union { 794 struct { 795 __le16 mailbox0; 796 __le16 mailbox1; 797 __le16 mailbox2; 798 __le16 mailbox3; 799 __le16 mailbox4; 800 __le16 mailbox5; 801 __le16 mailbox6; 802 __le16 mailbox7; 803 __le16 unused_2[59]; /* Gap */ 804 } __attribute__((packed)) isp2100; 805 struct { 806 /* Request Queue */ 807 __le16 req_q_in; /* In-Pointer */ 808 __le16 req_q_out; /* Out-Pointer */ 809 /* Response Queue */ 810 __le16 rsp_q_in; /* In-Pointer */ 811 __le16 rsp_q_out; /* Out-Pointer */ 812 813 /* RISC to Host Status */ 814 __le32 host_status; 815 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 816 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 817 818 /* Host to Host Semaphore */ 819 __le16 host_semaphore; 820 __le16 unused_3[17]; /* Gap */ 821 __le16 mailbox0; 822 __le16 mailbox1; 823 __le16 mailbox2; 824 __le16 mailbox3; 825 __le16 mailbox4; 826 __le16 mailbox5; 827 __le16 mailbox6; 828 __le16 mailbox7; 829 __le16 mailbox8; 830 __le16 mailbox9; 831 __le16 mailbox10; 832 __le16 mailbox11; 833 __le16 mailbox12; 834 __le16 mailbox13; 835 __le16 mailbox14; 836 __le16 mailbox15; 837 __le16 mailbox16; 838 __le16 mailbox17; 839 __le16 mailbox18; 840 __le16 mailbox19; 841 __le16 mailbox20; 842 __le16 mailbox21; 843 __le16 mailbox22; 844 __le16 mailbox23; 845 __le16 mailbox24; 846 __le16 mailbox25; 847 __le16 mailbox26; 848 __le16 mailbox27; 849 __le16 mailbox28; 850 __le16 mailbox29; 851 __le16 mailbox30; 852 __le16 mailbox31; 853 __le16 fb_cmd; 854 __le16 unused_4[10]; /* Gap */ 855 } __attribute__((packed)) isp2300; 856 } u; 857 858 __le16 fpm_diag_config; 859 __le16 unused_5[0x4]; /* Gap */ 860 __le16 risc_hw; 861 __le16 unused_5_1; /* Gap */ 862 __le16 pcr; /* Processor Control Register. */ 863 __le16 unused_6[0x5]; /* Gap */ 864 __le16 mctr; /* Memory Configuration and Timing. */ 865 __le16 unused_7[0x3]; /* Gap */ 866 __le16 fb_cmd_2100; /* Unused on 23XX */ 867 __le16 unused_8[0x3]; /* Gap */ 868 __le16 hccr; /* Host command & control register. */ 869 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 870 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 871 /* HCCR commands */ 872 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 873 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 874 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 875 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 876 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 877 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 878 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 879 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 880 881 __le16 unused_9[5]; /* Gap */ 882 __le16 gpiod; /* GPIO Data register. */ 883 __le16 gpioe; /* GPIO Enable register. */ 884 #define GPIO_LED_MASK 0x00C0 885 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 886 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 887 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 888 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 889 #define GPIO_LED_ALL_OFF 0x0000 890 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 891 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 892 893 union { 894 struct { 895 __le16 unused_10[8]; /* Gap */ 896 __le16 mailbox8; 897 __le16 mailbox9; 898 __le16 mailbox10; 899 __le16 mailbox11; 900 __le16 mailbox12; 901 __le16 mailbox13; 902 __le16 mailbox14; 903 __le16 mailbox15; 904 __le16 mailbox16; 905 __le16 mailbox17; 906 __le16 mailbox18; 907 __le16 mailbox19; 908 __le16 mailbox20; 909 __le16 mailbox21; 910 __le16 mailbox22; 911 __le16 mailbox23; /* Also probe reg. */ 912 } __attribute__((packed)) isp2200; 913 } u_end; 914 }; 915 916 struct device_reg_25xxmq { 917 __le32 req_q_in; 918 __le32 req_q_out; 919 __le32 rsp_q_in; 920 __le32 rsp_q_out; 921 __le32 atio_q_in; 922 __le32 atio_q_out; 923 }; 924 925 926 struct device_reg_fx00 { 927 __le32 mailbox0; /* 00 */ 928 __le32 mailbox1; /* 04 */ 929 __le32 mailbox2; /* 08 */ 930 __le32 mailbox3; /* 0C */ 931 __le32 mailbox4; /* 10 */ 932 __le32 mailbox5; /* 14 */ 933 __le32 mailbox6; /* 18 */ 934 __le32 mailbox7; /* 1C */ 935 __le32 mailbox8; /* 20 */ 936 __le32 mailbox9; /* 24 */ 937 __le32 mailbox10; /* 28 */ 938 __le32 mailbox11; 939 __le32 mailbox12; 940 __le32 mailbox13; 941 __le32 mailbox14; 942 __le32 mailbox15; 943 __le32 mailbox16; 944 __le32 mailbox17; 945 __le32 mailbox18; 946 __le32 mailbox19; 947 __le32 mailbox20; 948 __le32 mailbox21; 949 __le32 mailbox22; 950 __le32 mailbox23; 951 __le32 mailbox24; 952 __le32 mailbox25; 953 __le32 mailbox26; 954 __le32 mailbox27; 955 __le32 mailbox28; 956 __le32 mailbox29; 957 __le32 mailbox30; 958 __le32 mailbox31; 959 __le32 aenmailbox0; 960 __le32 aenmailbox1; 961 __le32 aenmailbox2; 962 __le32 aenmailbox3; 963 __le32 aenmailbox4; 964 __le32 aenmailbox5; 965 __le32 aenmailbox6; 966 __le32 aenmailbox7; 967 /* Request Queue. */ 968 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 969 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 970 /* Response Queue. */ 971 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 972 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 973 /* Init values shadowed on FW Up Event */ 974 __le32 initval0; /* B0 */ 975 __le32 initval1; /* B4 */ 976 __le32 initval2; /* B8 */ 977 __le32 initval3; /* BC */ 978 __le32 initval4; /* C0 */ 979 __le32 initval5; /* C4 */ 980 __le32 initval6; /* C8 */ 981 __le32 initval7; /* CC */ 982 __le32 fwheartbeat; /* D0 */ 983 __le32 pseudoaen; /* D4 */ 984 }; 985 986 987 988 typedef union { 989 struct device_reg_2xxx isp; 990 struct device_reg_24xx isp24; 991 struct device_reg_25xxmq isp25mq; 992 struct device_reg_82xx isp82; 993 struct device_reg_fx00 ispfx00; 994 } __iomem device_reg_t; 995 996 #define ISP_REQ_Q_IN(ha, reg) \ 997 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 998 &(reg)->u.isp2100.mailbox4 : \ 999 &(reg)->u.isp2300.req_q_in) 1000 #define ISP_REQ_Q_OUT(ha, reg) \ 1001 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1002 &(reg)->u.isp2100.mailbox4 : \ 1003 &(reg)->u.isp2300.req_q_out) 1004 #define ISP_RSP_Q_IN(ha, reg) \ 1005 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1006 &(reg)->u.isp2100.mailbox5 : \ 1007 &(reg)->u.isp2300.rsp_q_in) 1008 #define ISP_RSP_Q_OUT(ha, reg) \ 1009 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1010 &(reg)->u.isp2100.mailbox5 : \ 1011 &(reg)->u.isp2300.rsp_q_out) 1012 1013 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1014 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1015 1016 #define MAILBOX_REG(ha, reg, num) \ 1017 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1018 (num < 8 ? \ 1019 &(reg)->u.isp2100.mailbox0 + (num) : \ 1020 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1021 &(reg)->u.isp2300.mailbox0 + (num)) 1022 #define RD_MAILBOX_REG(ha, reg, num) \ 1023 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1024 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1025 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1026 1027 #define FB_CMD_REG(ha, reg) \ 1028 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1029 &(reg)->fb_cmd_2100 : \ 1030 &(reg)->u.isp2300.fb_cmd) 1031 #define RD_FB_CMD_REG(ha, reg) \ 1032 rd_reg_word(FB_CMD_REG(ha, reg)) 1033 #define WRT_FB_CMD_REG(ha, reg, data) \ 1034 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1035 1036 typedef struct { 1037 uint32_t out_mb; /* outbound from driver */ 1038 uint32_t in_mb; /* Incoming from RISC */ 1039 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1040 long buf_size; 1041 void *bufp; 1042 uint32_t tov; 1043 uint8_t flags; 1044 #define MBX_DMA_IN BIT_0 1045 #define MBX_DMA_OUT BIT_1 1046 #define IOCTL_CMD BIT_2 1047 } mbx_cmd_t; 1048 1049 struct mbx_cmd_32 { 1050 uint32_t out_mb; /* outbound from driver */ 1051 uint32_t in_mb; /* Incoming from RISC */ 1052 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1053 long buf_size; 1054 void *bufp; 1055 uint32_t tov; 1056 uint8_t flags; 1057 #define MBX_DMA_IN BIT_0 1058 #define MBX_DMA_OUT BIT_1 1059 #define IOCTL_CMD BIT_2 1060 }; 1061 1062 1063 #define MBX_TOV_SECONDS 30 1064 1065 /* 1066 * ISP product identification definitions in mailboxes after reset. 1067 */ 1068 #define PROD_ID_1 0x4953 1069 #define PROD_ID_2 0x0000 1070 #define PROD_ID_2a 0x5020 1071 #define PROD_ID_3 0x2020 1072 1073 /* 1074 * ISP mailbox Self-Test status codes 1075 */ 1076 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1077 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1078 #define MBS_BUSY 4 /* Busy. */ 1079 1080 /* 1081 * ISP mailbox command complete status codes 1082 */ 1083 #define MBS_COMMAND_COMPLETE 0x4000 1084 #define MBS_INVALID_COMMAND 0x4001 1085 #define MBS_HOST_INTERFACE_ERROR 0x4002 1086 #define MBS_TEST_FAILED 0x4003 1087 #define MBS_COMMAND_ERROR 0x4005 1088 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1089 #define MBS_PORT_ID_USED 0x4007 1090 #define MBS_LOOP_ID_USED 0x4008 1091 #define MBS_ALL_IDS_IN_USE 0x4009 1092 #define MBS_NOT_LOGGED_IN 0x400A 1093 #define MBS_LINK_DOWN_ERROR 0x400B 1094 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1095 1096 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1097 { 1098 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1099 } 1100 1101 /* 1102 * ISP mailbox asynchronous event status codes 1103 */ 1104 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1105 #define MBA_RESET 0x8001 /* Reset Detected. */ 1106 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1107 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1108 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1109 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1110 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1111 /* occurred. */ 1112 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1113 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1114 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1115 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1116 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1117 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1118 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1119 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1120 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1121 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1122 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1123 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1124 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1125 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1126 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1127 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1128 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1129 /* used. */ 1130 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1131 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1132 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1133 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1134 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1135 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1136 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1137 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1138 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1139 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1140 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1141 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1142 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1143 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1144 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1145 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1146 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1147 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1148 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1149 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1150 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1151 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1152 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1153 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1154 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1155 Notification */ 1156 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1157 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1158 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1159 /* 83XX FCoE specific */ 1160 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1161 1162 /* Interrupt type codes */ 1163 #define INTR_ROM_MB_SUCCESS 0x1 1164 #define INTR_ROM_MB_FAILED 0x2 1165 #define INTR_MB_SUCCESS 0x10 1166 #define INTR_MB_FAILED 0x11 1167 #define INTR_ASYNC_EVENT 0x12 1168 #define INTR_RSP_QUE_UPDATE 0x13 1169 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1170 #define INTR_ATIO_QUE_UPDATE 0x1C 1171 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1172 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1173 1174 /* ISP mailbox loopback echo diagnostic error code */ 1175 #define MBS_LB_RESET 0x17 1176 /* 1177 * Firmware options 1, 2, 3. 1178 */ 1179 #define FO1_AE_ON_LIPF8 BIT_0 1180 #define FO1_AE_ALL_LIP_RESET BIT_1 1181 #define FO1_CTIO_RETRY BIT_3 1182 #define FO1_DISABLE_LIP_F7_SW BIT_4 1183 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1184 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1185 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1186 #define FO1_SET_EMPHASIS_SWING BIT_8 1187 #define FO1_AE_AUTO_BYPASS BIT_9 1188 #define FO1_ENABLE_PURE_IOCB BIT_10 1189 #define FO1_AE_PLOGI_RJT BIT_11 1190 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1191 #define FO1_AE_QUEUE_FULL BIT_13 1192 1193 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1194 #define FO2_REV_LOOPBACK BIT_1 1195 1196 #define FO3_ENABLE_EMERG_IOCB BIT_0 1197 #define FO3_AE_RND_ERROR BIT_1 1198 1199 /* 24XX additional firmware options */ 1200 #define ADD_FO_COUNT 3 1201 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1202 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1203 1204 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1205 1206 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1207 1208 /* 1209 * ISP mailbox commands 1210 */ 1211 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1212 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1213 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1214 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1215 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1216 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1217 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1218 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1219 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1220 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1221 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1222 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1223 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1224 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1225 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1226 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1227 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1228 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1229 #define MBC_RESET 0x18 /* Reset. */ 1230 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1231 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1232 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1233 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1234 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1235 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1236 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1237 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1238 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1239 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1240 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1241 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1242 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1243 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1244 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1245 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1246 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1247 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1248 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1249 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1250 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1251 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1252 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1253 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1254 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1255 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1256 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1257 /* Initialization Procedure */ 1258 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1259 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1260 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1261 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1262 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1263 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1264 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1265 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1266 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1267 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1268 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1269 /* commandd. */ 1270 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1271 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1272 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1273 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1274 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1275 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1276 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1277 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1278 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1279 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1280 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1281 1282 /* 1283 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1284 * should be defined with MBC_MR_* 1285 */ 1286 #define MBC_MR_DRV_SHUTDOWN 0x6A 1287 1288 /* 1289 * ISP24xx mailbox commands 1290 */ 1291 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1292 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1293 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1294 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1295 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1296 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1297 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1298 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1299 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1300 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1301 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1302 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1303 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1304 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1305 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1306 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1307 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1308 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1309 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1310 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1311 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1312 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1313 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1314 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1315 1316 /* 1317 * ISP81xx mailbox commands 1318 */ 1319 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1320 1321 /* 1322 * ISP8044 mailbox commands 1323 */ 1324 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1325 #define HCS_WRITE_SERDES 0x3 1326 #define HCS_READ_SERDES 0x4 1327 1328 /* Firmware return data sizes */ 1329 #define FCAL_MAP_SIZE 128 1330 1331 /* Mailbox bit definitions for out_mb and in_mb */ 1332 #define MBX_31 BIT_31 1333 #define MBX_30 BIT_30 1334 #define MBX_29 BIT_29 1335 #define MBX_28 BIT_28 1336 #define MBX_27 BIT_27 1337 #define MBX_26 BIT_26 1338 #define MBX_25 BIT_25 1339 #define MBX_24 BIT_24 1340 #define MBX_23 BIT_23 1341 #define MBX_22 BIT_22 1342 #define MBX_21 BIT_21 1343 #define MBX_20 BIT_20 1344 #define MBX_19 BIT_19 1345 #define MBX_18 BIT_18 1346 #define MBX_17 BIT_17 1347 #define MBX_16 BIT_16 1348 #define MBX_15 BIT_15 1349 #define MBX_14 BIT_14 1350 #define MBX_13 BIT_13 1351 #define MBX_12 BIT_12 1352 #define MBX_11 BIT_11 1353 #define MBX_10 BIT_10 1354 #define MBX_9 BIT_9 1355 #define MBX_8 BIT_8 1356 #define MBX_7 BIT_7 1357 #define MBX_6 BIT_6 1358 #define MBX_5 BIT_5 1359 #define MBX_4 BIT_4 1360 #define MBX_3 BIT_3 1361 #define MBX_2 BIT_2 1362 #define MBX_1 BIT_1 1363 #define MBX_0 BIT_0 1364 1365 #define RNID_TYPE_ELS_CMD 0x5 1366 #define RNID_TYPE_PORT_LOGIN 0x7 1367 #define RNID_BUFFER_CREDITS 0x8 1368 #define RNID_TYPE_SET_VERSION 0x9 1369 #define RNID_TYPE_ASIC_TEMP 0xC 1370 1371 #define ELS_CMD_MAP_SIZE 32 1372 1373 /* 1374 * Firmware state codes from get firmware state mailbox command 1375 */ 1376 #define FSTATE_CONFIG_WAIT 0 1377 #define FSTATE_WAIT_AL_PA 1 1378 #define FSTATE_WAIT_LOGIN 2 1379 #define FSTATE_READY 3 1380 #define FSTATE_LOSS_OF_SYNC 4 1381 #define FSTATE_ERROR 5 1382 #define FSTATE_REINIT 6 1383 #define FSTATE_NON_PART 7 1384 1385 #define FSTATE_CONFIG_CORRECT 0 1386 #define FSTATE_P2P_RCV_LIP 1 1387 #define FSTATE_P2P_CHOOSE_LOOP 2 1388 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1389 #define FSTATE_FATAL_ERROR 4 1390 #define FSTATE_LOOP_BACK_CONN 5 1391 1392 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1393 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1394 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1395 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1396 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1397 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1398 #define QLA27XX_DEFAULT_IMAGE 0 1399 #define QLA27XX_PRIMARY_IMAGE 1 1400 #define QLA27XX_SECONDARY_IMAGE 2 1401 1402 /* 1403 * Port Database structure definition 1404 * Little endian except where noted. 1405 */ 1406 #define PORT_DATABASE_SIZE 128 /* bytes */ 1407 typedef struct { 1408 uint8_t options; 1409 uint8_t control; 1410 uint8_t master_state; 1411 uint8_t slave_state; 1412 uint8_t reserved[2]; 1413 uint8_t hard_address; 1414 uint8_t reserved_1; 1415 uint8_t port_id[4]; 1416 uint8_t node_name[WWN_SIZE]; 1417 uint8_t port_name[WWN_SIZE]; 1418 __le16 execution_throttle; 1419 uint16_t execution_count; 1420 uint8_t reset_count; 1421 uint8_t reserved_2; 1422 uint16_t resource_allocation; 1423 uint16_t current_allocation; 1424 uint16_t queue_head; 1425 uint16_t queue_tail; 1426 uint16_t transmit_execution_list_next; 1427 uint16_t transmit_execution_list_previous; 1428 uint16_t common_features; 1429 uint16_t total_concurrent_sequences; 1430 uint16_t RO_by_information_category; 1431 uint8_t recipient; 1432 uint8_t initiator; 1433 uint16_t receive_data_size; 1434 uint16_t concurrent_sequences; 1435 uint16_t open_sequences_per_exchange; 1436 uint16_t lun_abort_flags; 1437 uint16_t lun_stop_flags; 1438 uint16_t stop_queue_head; 1439 uint16_t stop_queue_tail; 1440 uint16_t port_retry_timer; 1441 uint16_t next_sequence_id; 1442 uint16_t frame_count; 1443 uint16_t PRLI_payload_length; 1444 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1445 /* Bits 15-0 of word 0 */ 1446 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1447 /* Bits 15-0 of word 3 */ 1448 uint16_t loop_id; 1449 uint16_t extended_lun_info_list_pointer; 1450 uint16_t extended_lun_stop_list_pointer; 1451 } port_database_t; 1452 1453 /* 1454 * Port database slave/master states 1455 */ 1456 #define PD_STATE_DISCOVERY 0 1457 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1458 #define PD_STATE_PORT_LOGIN 2 1459 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1460 #define PD_STATE_PROCESS_LOGIN 4 1461 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1462 #define PD_STATE_PORT_LOGGED_IN 6 1463 #define PD_STATE_PORT_UNAVAILABLE 7 1464 #define PD_STATE_PROCESS_LOGOUT 8 1465 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1466 #define PD_STATE_PORT_LOGOUT 10 1467 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1468 1469 1470 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1471 #define QLA_ZIO_DISABLED 0 1472 #define QLA_ZIO_DEFAULT_TIMER 2 1473 1474 /* 1475 * ISP Initialization Control Block. 1476 * Little endian except where noted. 1477 */ 1478 #define ICB_VERSION 1 1479 typedef struct { 1480 uint8_t version; 1481 uint8_t reserved_1; 1482 1483 /* 1484 * LSB BIT 0 = Enable Hard Loop Id 1485 * LSB BIT 1 = Enable Fairness 1486 * LSB BIT 2 = Enable Full-Duplex 1487 * LSB BIT 3 = Enable Fast Posting 1488 * LSB BIT 4 = Enable Target Mode 1489 * LSB BIT 5 = Disable Initiator Mode 1490 * LSB BIT 6 = Enable ADISC 1491 * LSB BIT 7 = Enable Target Inquiry Data 1492 * 1493 * MSB BIT 0 = Enable PDBC Notify 1494 * MSB BIT 1 = Non Participating LIP 1495 * MSB BIT 2 = Descending Loop ID Search 1496 * MSB BIT 3 = Acquire Loop ID in LIPA 1497 * MSB BIT 4 = Stop PortQ on Full Status 1498 * MSB BIT 5 = Full Login after LIP 1499 * MSB BIT 6 = Node Name Option 1500 * MSB BIT 7 = Ext IFWCB enable bit 1501 */ 1502 uint8_t firmware_options[2]; 1503 1504 __le16 frame_payload_size; 1505 __le16 max_iocb_allocation; 1506 __le16 execution_throttle; 1507 uint8_t retry_count; 1508 uint8_t retry_delay; /* unused */ 1509 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1510 uint16_t hard_address; 1511 uint8_t inquiry_data; 1512 uint8_t login_timeout; 1513 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1514 1515 __le16 request_q_outpointer; 1516 __le16 response_q_inpointer; 1517 __le16 request_q_length; 1518 __le16 response_q_length; 1519 __le64 request_q_address __packed; 1520 __le64 response_q_address __packed; 1521 1522 __le16 lun_enables; 1523 uint8_t command_resource_count; 1524 uint8_t immediate_notify_resource_count; 1525 __le16 timeout; 1526 uint8_t reserved_2[2]; 1527 1528 /* 1529 * LSB BIT 0 = Timer Operation mode bit 0 1530 * LSB BIT 1 = Timer Operation mode bit 1 1531 * LSB BIT 2 = Timer Operation mode bit 2 1532 * LSB BIT 3 = Timer Operation mode bit 3 1533 * LSB BIT 4 = Init Config Mode bit 0 1534 * LSB BIT 5 = Init Config Mode bit 1 1535 * LSB BIT 6 = Init Config Mode bit 2 1536 * LSB BIT 7 = Enable Non part on LIHA failure 1537 * 1538 * MSB BIT 0 = Enable class 2 1539 * MSB BIT 1 = Enable ACK0 1540 * MSB BIT 2 = 1541 * MSB BIT 3 = 1542 * MSB BIT 4 = FC Tape Enable 1543 * MSB BIT 5 = Enable FC Confirm 1544 * MSB BIT 6 = Enable command queuing in target mode 1545 * MSB BIT 7 = No Logo On Link Down 1546 */ 1547 uint8_t add_firmware_options[2]; 1548 1549 uint8_t response_accumulation_timer; 1550 uint8_t interrupt_delay_timer; 1551 1552 /* 1553 * LSB BIT 0 = Enable Read xfr_rdy 1554 * LSB BIT 1 = Soft ID only 1555 * LSB BIT 2 = 1556 * LSB BIT 3 = 1557 * LSB BIT 4 = FCP RSP Payload [0] 1558 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1559 * LSB BIT 6 = Enable Out-of-Order frame handling 1560 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1561 * 1562 * MSB BIT 0 = Sbus enable - 2300 1563 * MSB BIT 1 = 1564 * MSB BIT 2 = 1565 * MSB BIT 3 = 1566 * MSB BIT 4 = LED mode 1567 * MSB BIT 5 = enable 50 ohm termination 1568 * MSB BIT 6 = Data Rate (2300 only) 1569 * MSB BIT 7 = Data Rate (2300 only) 1570 */ 1571 uint8_t special_options[2]; 1572 1573 uint8_t reserved_3[26]; 1574 } init_cb_t; 1575 1576 /* Special Features Control Block */ 1577 struct init_sf_cb { 1578 uint8_t format; 1579 uint8_t reserved0; 1580 /* 1581 * BIT 15-14 = Reserved 1582 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1583 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1584 * BIT 11-0 = Reserved 1585 */ 1586 __le16 flags; 1587 uint8_t reserved1[32]; 1588 uint16_t discard_OHRB_timeout_value; 1589 uint16_t remote_write_opt_queue_num; 1590 uint8_t reserved2[40]; 1591 uint8_t scm_related_parameter[16]; 1592 uint8_t reserved3[32]; 1593 }; 1594 1595 /* 1596 * Get Link Status mailbox command return buffer. 1597 */ 1598 #define GLSO_SEND_RPS BIT_0 1599 #define GLSO_USE_DID BIT_3 1600 1601 struct link_statistics { 1602 __le32 link_fail_cnt; 1603 __le32 loss_sync_cnt; 1604 __le32 loss_sig_cnt; 1605 __le32 prim_seq_err_cnt; 1606 __le32 inval_xmit_word_cnt; 1607 __le32 inval_crc_cnt; 1608 __le32 lip_cnt; 1609 __le32 link_up_cnt; 1610 __le32 link_down_loop_init_tmo; 1611 __le32 link_down_los; 1612 __le32 link_down_loss_rcv_clk; 1613 uint32_t reserved0[5]; 1614 __le32 port_cfg_chg; 1615 uint32_t reserved1[11]; 1616 __le32 rsp_q_full; 1617 __le32 atio_q_full; 1618 __le32 drop_ae; 1619 __le32 els_proto_err; 1620 __le32 reserved2; 1621 __le32 tx_frames; 1622 __le32 rx_frames; 1623 __le32 discarded_frames; 1624 __le32 dropped_frames; 1625 uint32_t reserved3; 1626 __le32 nos_rcvd; 1627 uint32_t reserved4[4]; 1628 __le32 tx_prjt; 1629 __le32 rcv_exfail; 1630 __le32 rcv_abts; 1631 __le32 seq_frm_miss; 1632 __le32 corr_err; 1633 __le32 mb_rqst; 1634 __le32 nport_full; 1635 __le32 eofa; 1636 uint32_t reserved5; 1637 __le64 fpm_recv_word_cnt; 1638 __le64 fpm_disc_word_cnt; 1639 __le64 fpm_xmit_word_cnt; 1640 uint32_t reserved6[70]; 1641 }; 1642 1643 /* 1644 * NVRAM Command values. 1645 */ 1646 #define NV_START_BIT BIT_2 1647 #define NV_WRITE_OP (BIT_26+BIT_24) 1648 #define NV_READ_OP (BIT_26+BIT_25) 1649 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1650 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1651 #define NV_DELAY_COUNT 10 1652 1653 /* 1654 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1655 */ 1656 typedef struct { 1657 /* 1658 * NVRAM header 1659 */ 1660 uint8_t id[4]; 1661 uint8_t nvram_version; 1662 uint8_t reserved_0; 1663 1664 /* 1665 * NVRAM RISC parameter block 1666 */ 1667 uint8_t parameter_block_version; 1668 uint8_t reserved_1; 1669 1670 /* 1671 * LSB BIT 0 = Enable Hard Loop Id 1672 * LSB BIT 1 = Enable Fairness 1673 * LSB BIT 2 = Enable Full-Duplex 1674 * LSB BIT 3 = Enable Fast Posting 1675 * LSB BIT 4 = Enable Target Mode 1676 * LSB BIT 5 = Disable Initiator Mode 1677 * LSB BIT 6 = Enable ADISC 1678 * LSB BIT 7 = Enable Target Inquiry Data 1679 * 1680 * MSB BIT 0 = Enable PDBC Notify 1681 * MSB BIT 1 = Non Participating LIP 1682 * MSB BIT 2 = Descending Loop ID Search 1683 * MSB BIT 3 = Acquire Loop ID in LIPA 1684 * MSB BIT 4 = Stop PortQ on Full Status 1685 * MSB BIT 5 = Full Login after LIP 1686 * MSB BIT 6 = Node Name Option 1687 * MSB BIT 7 = Ext IFWCB enable bit 1688 */ 1689 uint8_t firmware_options[2]; 1690 1691 __le16 frame_payload_size; 1692 __le16 max_iocb_allocation; 1693 __le16 execution_throttle; 1694 uint8_t retry_count; 1695 uint8_t retry_delay; /* unused */ 1696 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1697 uint16_t hard_address; 1698 uint8_t inquiry_data; 1699 uint8_t login_timeout; 1700 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1701 1702 /* 1703 * LSB BIT 0 = Timer Operation mode bit 0 1704 * LSB BIT 1 = Timer Operation mode bit 1 1705 * LSB BIT 2 = Timer Operation mode bit 2 1706 * LSB BIT 3 = Timer Operation mode bit 3 1707 * LSB BIT 4 = Init Config Mode bit 0 1708 * LSB BIT 5 = Init Config Mode bit 1 1709 * LSB BIT 6 = Init Config Mode bit 2 1710 * LSB BIT 7 = Enable Non part on LIHA failure 1711 * 1712 * MSB BIT 0 = Enable class 2 1713 * MSB BIT 1 = Enable ACK0 1714 * MSB BIT 2 = 1715 * MSB BIT 3 = 1716 * MSB BIT 4 = FC Tape Enable 1717 * MSB BIT 5 = Enable FC Confirm 1718 * MSB BIT 6 = Enable command queuing in target mode 1719 * MSB BIT 7 = No Logo On Link Down 1720 */ 1721 uint8_t add_firmware_options[2]; 1722 1723 uint8_t response_accumulation_timer; 1724 uint8_t interrupt_delay_timer; 1725 1726 /* 1727 * LSB BIT 0 = Enable Read xfr_rdy 1728 * LSB BIT 1 = Soft ID only 1729 * LSB BIT 2 = 1730 * LSB BIT 3 = 1731 * LSB BIT 4 = FCP RSP Payload [0] 1732 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1733 * LSB BIT 6 = Enable Out-of-Order frame handling 1734 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1735 * 1736 * MSB BIT 0 = Sbus enable - 2300 1737 * MSB BIT 1 = 1738 * MSB BIT 2 = 1739 * MSB BIT 3 = 1740 * MSB BIT 4 = LED mode 1741 * MSB BIT 5 = enable 50 ohm termination 1742 * MSB BIT 6 = Data Rate (2300 only) 1743 * MSB BIT 7 = Data Rate (2300 only) 1744 */ 1745 uint8_t special_options[2]; 1746 1747 /* Reserved for expanded RISC parameter block */ 1748 uint8_t reserved_2[22]; 1749 1750 /* 1751 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1752 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1753 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1754 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1755 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1756 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1757 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1758 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1759 * 1760 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1761 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1762 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1763 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1764 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1765 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1766 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1767 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1768 * 1769 * LSB BIT 0 = Output Swing 1G bit 0 1770 * LSB BIT 1 = Output Swing 1G bit 1 1771 * LSB BIT 2 = Output Swing 1G bit 2 1772 * LSB BIT 3 = Output Emphasis 1G bit 0 1773 * LSB BIT 4 = Output Emphasis 1G bit 1 1774 * LSB BIT 5 = Output Swing 2G bit 0 1775 * LSB BIT 6 = Output Swing 2G bit 1 1776 * LSB BIT 7 = Output Swing 2G bit 2 1777 * 1778 * MSB BIT 0 = Output Emphasis 2G bit 0 1779 * MSB BIT 1 = Output Emphasis 2G bit 1 1780 * MSB BIT 2 = Output Enable 1781 * MSB BIT 3 = 1782 * MSB BIT 4 = 1783 * MSB BIT 5 = 1784 * MSB BIT 6 = 1785 * MSB BIT 7 = 1786 */ 1787 uint8_t seriallink_options[4]; 1788 1789 /* 1790 * NVRAM host parameter block 1791 * 1792 * LSB BIT 0 = Enable spinup delay 1793 * LSB BIT 1 = Disable BIOS 1794 * LSB BIT 2 = Enable Memory Map BIOS 1795 * LSB BIT 3 = Enable Selectable Boot 1796 * LSB BIT 4 = Disable RISC code load 1797 * LSB BIT 5 = Set cache line size 1 1798 * LSB BIT 6 = PCI Parity Disable 1799 * LSB BIT 7 = Enable extended logging 1800 * 1801 * MSB BIT 0 = Enable 64bit addressing 1802 * MSB BIT 1 = Enable lip reset 1803 * MSB BIT 2 = Enable lip full login 1804 * MSB BIT 3 = Enable target reset 1805 * MSB BIT 4 = Enable database storage 1806 * MSB BIT 5 = Enable cache flush read 1807 * MSB BIT 6 = Enable database load 1808 * MSB BIT 7 = Enable alternate WWN 1809 */ 1810 uint8_t host_p[2]; 1811 1812 uint8_t boot_node_name[WWN_SIZE]; 1813 uint8_t boot_lun_number; 1814 uint8_t reset_delay; 1815 uint8_t port_down_retry_count; 1816 uint8_t boot_id_number; 1817 __le16 max_luns_per_target; 1818 uint8_t fcode_boot_port_name[WWN_SIZE]; 1819 uint8_t alternate_port_name[WWN_SIZE]; 1820 uint8_t alternate_node_name[WWN_SIZE]; 1821 1822 /* 1823 * BIT 0 = Selective Login 1824 * BIT 1 = Alt-Boot Enable 1825 * BIT 2 = 1826 * BIT 3 = Boot Order List 1827 * BIT 4 = 1828 * BIT 5 = Selective LUN 1829 * BIT 6 = 1830 * BIT 7 = unused 1831 */ 1832 uint8_t efi_parameters; 1833 1834 uint8_t link_down_timeout; 1835 1836 uint8_t adapter_id[16]; 1837 1838 uint8_t alt1_boot_node_name[WWN_SIZE]; 1839 uint16_t alt1_boot_lun_number; 1840 uint8_t alt2_boot_node_name[WWN_SIZE]; 1841 uint16_t alt2_boot_lun_number; 1842 uint8_t alt3_boot_node_name[WWN_SIZE]; 1843 uint16_t alt3_boot_lun_number; 1844 uint8_t alt4_boot_node_name[WWN_SIZE]; 1845 uint16_t alt4_boot_lun_number; 1846 uint8_t alt5_boot_node_name[WWN_SIZE]; 1847 uint16_t alt5_boot_lun_number; 1848 uint8_t alt6_boot_node_name[WWN_SIZE]; 1849 uint16_t alt6_boot_lun_number; 1850 uint8_t alt7_boot_node_name[WWN_SIZE]; 1851 uint16_t alt7_boot_lun_number; 1852 1853 uint8_t reserved_3[2]; 1854 1855 /* Offset 200-215 : Model Number */ 1856 uint8_t model_number[16]; 1857 1858 /* OEM related items */ 1859 uint8_t oem_specific[16]; 1860 1861 /* 1862 * NVRAM Adapter Features offset 232-239 1863 * 1864 * LSB BIT 0 = External GBIC 1865 * LSB BIT 1 = Risc RAM parity 1866 * LSB BIT 2 = Buffer Plus Module 1867 * LSB BIT 3 = Multi Chip Adapter 1868 * LSB BIT 4 = Internal connector 1869 * LSB BIT 5 = 1870 * LSB BIT 6 = 1871 * LSB BIT 7 = 1872 * 1873 * MSB BIT 0 = 1874 * MSB BIT 1 = 1875 * MSB BIT 2 = 1876 * MSB BIT 3 = 1877 * MSB BIT 4 = 1878 * MSB BIT 5 = 1879 * MSB BIT 6 = 1880 * MSB BIT 7 = 1881 */ 1882 uint8_t adapter_features[2]; 1883 1884 uint8_t reserved_4[16]; 1885 1886 /* Subsystem vendor ID for ISP2200 */ 1887 uint16_t subsystem_vendor_id_2200; 1888 1889 /* Subsystem device ID for ISP2200 */ 1890 uint16_t subsystem_device_id_2200; 1891 1892 uint8_t reserved_5; 1893 uint8_t checksum; 1894 } nvram_t; 1895 1896 /* 1897 * ISP queue - response queue entry definition. 1898 */ 1899 typedef struct { 1900 uint8_t entry_type; /* Entry type. */ 1901 uint8_t entry_count; /* Entry count. */ 1902 uint8_t sys_define; /* System defined. */ 1903 uint8_t entry_status; /* Entry Status. */ 1904 uint32_t handle; /* System defined handle */ 1905 uint8_t data[52]; 1906 uint32_t signature; 1907 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1908 } response_t; 1909 1910 /* 1911 * ISP queue - ATIO queue entry definition. 1912 */ 1913 struct atio { 1914 uint8_t entry_type; /* Entry type. */ 1915 uint8_t entry_count; /* Entry count. */ 1916 __le16 attr_n_length; 1917 uint8_t data[56]; 1918 uint32_t signature; 1919 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1920 }; 1921 1922 typedef union { 1923 __le16 extended; 1924 struct { 1925 uint8_t reserved; 1926 uint8_t standard; 1927 } id; 1928 } target_id_t; 1929 1930 #define SET_TARGET_ID(ha, to, from) \ 1931 do { \ 1932 if (HAS_EXTENDED_IDS(ha)) \ 1933 to.extended = cpu_to_le16(from); \ 1934 else \ 1935 to.id.standard = (uint8_t)from; \ 1936 } while (0) 1937 1938 /* 1939 * ISP queue - command entry structure definition. 1940 */ 1941 #define COMMAND_TYPE 0x11 /* Command entry */ 1942 typedef struct { 1943 uint8_t entry_type; /* Entry type. */ 1944 uint8_t entry_count; /* Entry count. */ 1945 uint8_t sys_define; /* System defined. */ 1946 uint8_t entry_status; /* Entry Status. */ 1947 uint32_t handle; /* System handle. */ 1948 target_id_t target; /* SCSI ID */ 1949 __le16 lun; /* SCSI LUN */ 1950 __le16 control_flags; /* Control flags. */ 1951 #define CF_WRITE BIT_6 1952 #define CF_READ BIT_5 1953 #define CF_SIMPLE_TAG BIT_3 1954 #define CF_ORDERED_TAG BIT_2 1955 #define CF_HEAD_TAG BIT_1 1956 uint16_t reserved_1; 1957 __le16 timeout; /* Command timeout. */ 1958 __le16 dseg_count; /* Data segment count. */ 1959 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1960 __le32 byte_count; /* Total byte count. */ 1961 union { 1962 struct dsd32 dsd32[3]; 1963 struct dsd64 dsd64[2]; 1964 }; 1965 } cmd_entry_t; 1966 1967 /* 1968 * ISP queue - 64-Bit addressing, command entry structure definition. 1969 */ 1970 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1971 typedef struct { 1972 uint8_t entry_type; /* Entry type. */ 1973 uint8_t entry_count; /* Entry count. */ 1974 uint8_t sys_define; /* System defined. */ 1975 uint8_t entry_status; /* Entry Status. */ 1976 uint32_t handle; /* System handle. */ 1977 target_id_t target; /* SCSI ID */ 1978 __le16 lun; /* SCSI LUN */ 1979 __le16 control_flags; /* Control flags. */ 1980 uint16_t reserved_1; 1981 __le16 timeout; /* Command timeout. */ 1982 __le16 dseg_count; /* Data segment count. */ 1983 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1984 uint32_t byte_count; /* Total byte count. */ 1985 struct dsd64 dsd[2]; 1986 } cmd_a64_entry_t, request_t; 1987 1988 /* 1989 * ISP queue - continuation entry structure definition. 1990 */ 1991 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1992 typedef struct { 1993 uint8_t entry_type; /* Entry type. */ 1994 uint8_t entry_count; /* Entry count. */ 1995 uint8_t sys_define; /* System defined. */ 1996 uint8_t entry_status; /* Entry Status. */ 1997 uint32_t reserved; 1998 struct dsd32 dsd[7]; 1999 } cont_entry_t; 2000 2001 /* 2002 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2003 */ 2004 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2005 typedef struct { 2006 uint8_t entry_type; /* Entry type. */ 2007 uint8_t entry_count; /* Entry count. */ 2008 uint8_t sys_define; /* System defined. */ 2009 uint8_t entry_status; /* Entry Status. */ 2010 struct dsd64 dsd[5]; 2011 } cont_a64_entry_t; 2012 2013 #define PO_MODE_DIF_INSERT 0 2014 #define PO_MODE_DIF_REMOVE 1 2015 #define PO_MODE_DIF_PASS 2 2016 #define PO_MODE_DIF_REPLACE 3 2017 #define PO_MODE_DIF_TCP_CKSUM 6 2018 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2019 #define PO_DISABLE_GUARD_CHECK BIT_4 2020 #define PO_DISABLE_INCR_REF_TAG BIT_5 2021 #define PO_DIS_HEADER_MODE BIT_7 2022 #define PO_ENABLE_DIF_BUNDLING BIT_8 2023 #define PO_DIS_FRAME_MODE BIT_9 2024 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2025 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2026 2027 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2028 #define PO_DIS_REF_TAG_REPL BIT_13 2029 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2030 #define PO_DIS_REF_TAG_VALD BIT_15 2031 2032 /* 2033 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2034 */ 2035 struct crc_context { 2036 uint32_t handle; /* System handle. */ 2037 __le32 ref_tag; 2038 __le16 app_tag; 2039 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2040 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2041 __le16 guard_seed; /* Initial Guard Seed */ 2042 __le16 prot_opts; /* Requested Data Protection Mode */ 2043 __le16 blk_size; /* Data size in bytes */ 2044 __le16 runt_blk_guard; /* Guard value for runt block (tape 2045 * only) */ 2046 __le32 byte_count; /* Total byte count/ total data 2047 * transfer count */ 2048 union { 2049 struct { 2050 uint32_t reserved_1; 2051 uint16_t reserved_2; 2052 uint16_t reserved_3; 2053 uint32_t reserved_4; 2054 struct dsd64 data_dsd[1]; 2055 uint32_t reserved_5[2]; 2056 uint32_t reserved_6; 2057 } nobundling; 2058 struct { 2059 __le32 dif_byte_count; /* Total DIF byte 2060 * count */ 2061 uint16_t reserved_1; 2062 __le16 dseg_count; /* Data segment count */ 2063 uint32_t reserved_2; 2064 struct dsd64 data_dsd[1]; 2065 struct dsd64 dif_dsd; 2066 } bundling; 2067 } u; 2068 2069 struct fcp_cmnd fcp_cmnd; 2070 dma_addr_t crc_ctx_dma; 2071 /* List of DMA context transfers */ 2072 struct list_head dsd_list; 2073 2074 /* List of DIF Bundling context DMA address */ 2075 struct list_head ldif_dsd_list; 2076 u8 no_ldif_dsd; 2077 2078 struct list_head ldif_dma_hndl_list; 2079 u32 dif_bundl_len; 2080 u8 no_dif_bundl; 2081 /* This structure should not exceed 512 bytes */ 2082 }; 2083 2084 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2085 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2086 2087 /* 2088 * ISP queue - status entry structure definition. 2089 */ 2090 #define STATUS_TYPE 0x03 /* Status entry. */ 2091 typedef struct { 2092 uint8_t entry_type; /* Entry type. */ 2093 uint8_t entry_count; /* Entry count. */ 2094 uint8_t sys_define; /* System defined. */ 2095 uint8_t entry_status; /* Entry Status. */ 2096 uint32_t handle; /* System handle. */ 2097 __le16 scsi_status; /* SCSI status. */ 2098 __le16 comp_status; /* Completion status. */ 2099 __le16 state_flags; /* State flags. */ 2100 __le16 status_flags; /* Status flags. */ 2101 __le16 rsp_info_len; /* Response Info Length. */ 2102 __le16 req_sense_length; /* Request sense data length. */ 2103 __le32 residual_length; /* Residual transfer length. */ 2104 uint8_t rsp_info[8]; /* FCP response information. */ 2105 uint8_t req_sense_data[32]; /* Request sense data. */ 2106 } sts_entry_t; 2107 2108 /* 2109 * Status entry entry status 2110 */ 2111 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2112 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2113 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2114 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2115 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2116 #define RF_BUSY BIT_1 /* Busy */ 2117 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2118 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2119 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2120 RF_INV_E_TYPE) 2121 2122 /* 2123 * Status entry SCSI status bit definitions. 2124 */ 2125 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2126 #define SS_RESIDUAL_UNDER BIT_11 2127 #define SS_RESIDUAL_OVER BIT_10 2128 #define SS_SENSE_LEN_VALID BIT_9 2129 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2130 #define SS_SCSI_STATUS_BYTE 0xff 2131 2132 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2133 #define SS_BUSY_CONDITION BIT_3 2134 #define SS_CONDITION_MET BIT_2 2135 #define SS_CHECK_CONDITION BIT_1 2136 2137 /* 2138 * Status entry completion status 2139 */ 2140 #define CS_COMPLETE 0x0 /* No errors */ 2141 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2142 #define CS_DMA 0x2 /* A DMA direction error. */ 2143 #define CS_TRANSPORT 0x3 /* Transport error. */ 2144 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2145 #define CS_ABORTED 0x5 /* System aborted command. */ 2146 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2147 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2148 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2149 2150 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2151 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2152 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2153 /* (selection timeout) */ 2154 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2155 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2156 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2157 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2158 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2159 failure */ 2160 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2161 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2162 #define CS_UNKNOWN 0x81 /* Driver defined */ 2163 #define CS_RETRY 0x82 /* Driver defined */ 2164 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2165 2166 #define CS_BIDIR_RD_OVERRUN 0x700 2167 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2168 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2169 #define CS_BIDIR_RD_UNDERRUN 0x1500 2170 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2171 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2172 #define CS_BIDIR_DMA 0x200 2173 /* 2174 * Status entry status flags 2175 */ 2176 #define SF_ABTS_TERMINATED BIT_10 2177 #define SF_LOGOUT_SENT BIT_13 2178 2179 /* 2180 * ISP queue - status continuation entry structure definition. 2181 */ 2182 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2183 typedef struct { 2184 uint8_t entry_type; /* Entry type. */ 2185 uint8_t entry_count; /* Entry count. */ 2186 uint8_t sys_define; /* System defined. */ 2187 uint8_t entry_status; /* Entry Status. */ 2188 uint8_t data[60]; /* data */ 2189 } sts_cont_entry_t; 2190 2191 /* 2192 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2193 * structure definition. 2194 */ 2195 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2196 typedef struct { 2197 uint8_t entry_type; /* Entry type. */ 2198 uint8_t entry_count; /* Entry count. */ 2199 uint8_t handle_count; /* Handle count. */ 2200 uint8_t entry_status; /* Entry Status. */ 2201 uint32_t handle[15]; /* System handles. */ 2202 } sts21_entry_t; 2203 2204 /* 2205 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2206 * structure definition. 2207 */ 2208 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2209 typedef struct { 2210 uint8_t entry_type; /* Entry type. */ 2211 uint8_t entry_count; /* Entry count. */ 2212 uint8_t handle_count; /* Handle count. */ 2213 uint8_t entry_status; /* Entry Status. */ 2214 uint16_t handle[30]; /* System handles. */ 2215 } sts22_entry_t; 2216 2217 /* 2218 * ISP queue - marker entry structure definition. 2219 */ 2220 #define MARKER_TYPE 0x04 /* Marker entry. */ 2221 typedef struct { 2222 uint8_t entry_type; /* Entry type. */ 2223 uint8_t entry_count; /* Entry count. */ 2224 uint8_t handle_count; /* Handle count. */ 2225 uint8_t entry_status; /* Entry Status. */ 2226 uint32_t sys_define_2; /* System defined. */ 2227 target_id_t target; /* SCSI ID */ 2228 uint8_t modifier; /* Modifier (7-0). */ 2229 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2230 #define MK_SYNC_ID 1 /* Synchronize ID */ 2231 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2232 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2233 /* clear port changed, */ 2234 /* use sequence number. */ 2235 uint8_t reserved_1; 2236 __le16 sequence_number; /* Sequence number of event */ 2237 __le16 lun; /* SCSI LUN */ 2238 uint8_t reserved_2[48]; 2239 } mrk_entry_t; 2240 2241 /* 2242 * ISP queue - Management Server entry structure definition. 2243 */ 2244 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2245 typedef struct { 2246 uint8_t entry_type; /* Entry type. */ 2247 uint8_t entry_count; /* Entry count. */ 2248 uint8_t handle_count; /* Handle count. */ 2249 uint8_t entry_status; /* Entry Status. */ 2250 uint32_t handle1; /* System handle. */ 2251 target_id_t loop_id; 2252 __le16 status; 2253 __le16 control_flags; /* Control flags. */ 2254 uint16_t reserved2; 2255 __le16 timeout; 2256 __le16 cmd_dsd_count; 2257 __le16 total_dsd_count; 2258 uint8_t type; 2259 uint8_t r_ctl; 2260 __le16 rx_id; 2261 uint16_t reserved3; 2262 uint32_t handle2; 2263 __le32 rsp_bytecount; 2264 __le32 req_bytecount; 2265 struct dsd64 req_dsd; 2266 struct dsd64 rsp_dsd; 2267 } ms_iocb_entry_t; 2268 2269 #define SCM_EDC_ACC_RECEIVED BIT_6 2270 #define SCM_RDF_ACC_RECEIVED BIT_7 2271 2272 /* 2273 * ISP queue - Mailbox Command entry structure definition. 2274 */ 2275 #define MBX_IOCB_TYPE 0x39 2276 struct mbx_entry { 2277 uint8_t entry_type; 2278 uint8_t entry_count; 2279 uint8_t sys_define1; 2280 /* Use sys_define1 for source type */ 2281 #define SOURCE_SCSI 0x00 2282 #define SOURCE_IP 0x01 2283 #define SOURCE_VI 0x02 2284 #define SOURCE_SCTP 0x03 2285 #define SOURCE_MP 0x04 2286 #define SOURCE_MPIOCTL 0x05 2287 #define SOURCE_ASYNC_IOCB 0x07 2288 2289 uint8_t entry_status; 2290 2291 uint32_t handle; 2292 target_id_t loop_id; 2293 2294 __le16 status; 2295 __le16 state_flags; 2296 __le16 status_flags; 2297 2298 uint32_t sys_define2[2]; 2299 2300 __le16 mb0; 2301 __le16 mb1; 2302 __le16 mb2; 2303 __le16 mb3; 2304 __le16 mb6; 2305 __le16 mb7; 2306 __le16 mb9; 2307 __le16 mb10; 2308 uint32_t reserved_2[2]; 2309 uint8_t node_name[WWN_SIZE]; 2310 uint8_t port_name[WWN_SIZE]; 2311 }; 2312 2313 #ifndef IMMED_NOTIFY_TYPE 2314 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2315 /* 2316 * ISP queue - immediate notify entry structure definition. 2317 * This is sent by the ISP to the Target driver. 2318 * This IOCB would have report of events sent by the 2319 * initiator, that needs to be handled by the target 2320 * driver immediately. 2321 */ 2322 struct imm_ntfy_from_isp { 2323 uint8_t entry_type; /* Entry type. */ 2324 uint8_t entry_count; /* Entry count. */ 2325 uint8_t sys_define; /* System defined. */ 2326 uint8_t entry_status; /* Entry Status. */ 2327 union { 2328 struct { 2329 __le32 sys_define_2; /* System defined. */ 2330 target_id_t target; 2331 __le16 lun; 2332 uint8_t target_id; 2333 uint8_t reserved_1; 2334 __le16 status_modifier; 2335 __le16 status; 2336 __le16 task_flags; 2337 __le16 seq_id; 2338 __le16 srr_rx_id; 2339 __le32 srr_rel_offs; 2340 __le16 srr_ui; 2341 #define SRR_IU_DATA_IN 0x1 2342 #define SRR_IU_DATA_OUT 0x5 2343 #define SRR_IU_STATUS 0x7 2344 __le16 srr_ox_id; 2345 uint8_t reserved_2[28]; 2346 } isp2x; 2347 struct { 2348 uint32_t reserved; 2349 __le16 nport_handle; 2350 uint16_t reserved_2; 2351 __le16 flags; 2352 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2353 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2354 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2355 __le16 srr_rx_id; 2356 __le16 status; 2357 uint8_t status_subcode; 2358 uint8_t fw_handle; 2359 __le32 exchange_address; 2360 __le32 srr_rel_offs; 2361 __le16 srr_ui; 2362 __le16 srr_ox_id; 2363 union { 2364 struct { 2365 uint8_t node_name[8]; 2366 } plogi; /* PLOGI/ADISC/PDISC */ 2367 struct { 2368 /* PRLI word 3 bit 0-15 */ 2369 __le16 wd3_lo; 2370 uint8_t resv0[6]; 2371 } prli; 2372 struct { 2373 uint8_t port_id[3]; 2374 uint8_t resv1; 2375 __le16 nport_handle; 2376 uint16_t resv2; 2377 } req_els; 2378 } u; 2379 uint8_t port_name[8]; 2380 uint8_t resv3[3]; 2381 uint8_t vp_index; 2382 uint32_t reserved_5; 2383 uint8_t port_id[3]; 2384 uint8_t reserved_6; 2385 } isp24; 2386 } u; 2387 uint16_t reserved_7; 2388 __le16 ox_id; 2389 } __packed; 2390 #endif 2391 2392 /* 2393 * ISP request and response queue entry sizes 2394 */ 2395 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2396 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2397 2398 2399 2400 /* 2401 * Switch info gathering structure. 2402 */ 2403 typedef struct { 2404 port_id_t d_id; 2405 uint8_t node_name[WWN_SIZE]; 2406 uint8_t port_name[WWN_SIZE]; 2407 uint8_t fabric_port_name[WWN_SIZE]; 2408 uint16_t fp_speed; 2409 uint8_t fc4_type; 2410 uint8_t fc4_features; 2411 } sw_info_t; 2412 2413 /* FCP-4 types */ 2414 #define FC4_TYPE_FCP_SCSI 0x08 2415 #define FC4_TYPE_NVME 0x28 2416 #define FC4_TYPE_OTHER 0x0 2417 #define FC4_TYPE_UNKNOWN 0xff 2418 2419 /* mailbox command 4G & above */ 2420 struct mbx_24xx_entry { 2421 uint8_t entry_type; 2422 uint8_t entry_count; 2423 uint8_t sys_define1; 2424 uint8_t entry_status; 2425 uint32_t handle; 2426 uint16_t mb[28]; 2427 }; 2428 2429 #define IOCB_SIZE 64 2430 2431 /* 2432 * Fibre channel port type. 2433 */ 2434 typedef enum { 2435 FCT_UNKNOWN, 2436 FCT_BROADCAST = 0x01, 2437 FCT_INITIATOR = 0x02, 2438 FCT_TARGET = 0x04, 2439 FCT_NVME_INITIATOR = 0x10, 2440 FCT_NVME_TARGET = 0x20, 2441 FCT_NVME_DISCOVERY = 0x40, 2442 FCT_NVME = 0xf0, 2443 } fc_port_type_t; 2444 2445 enum qla_sess_deletion { 2446 QLA_SESS_DELETION_NONE = 0, 2447 QLA_SESS_DELETION_IN_PROGRESS, 2448 QLA_SESS_DELETED, 2449 }; 2450 2451 enum qlt_plogi_link_t { 2452 QLT_PLOGI_LINK_SAME_WWN, 2453 QLT_PLOGI_LINK_CONFLICT, 2454 QLT_PLOGI_LINK_MAX 2455 }; 2456 2457 struct qlt_plogi_ack_t { 2458 struct list_head list; 2459 struct imm_ntfy_from_isp iocb; 2460 port_id_t id; 2461 int ref_count; 2462 void *fcport; 2463 }; 2464 2465 struct ct_sns_desc { 2466 struct ct_sns_pkt *ct_sns; 2467 dma_addr_t ct_sns_dma; 2468 }; 2469 2470 enum discovery_state { 2471 DSC_DELETED, 2472 DSC_GNN_ID, 2473 DSC_GNL, 2474 DSC_LOGIN_PEND, 2475 DSC_LOGIN_FAILED, 2476 DSC_GPDB, 2477 DSC_UPD_FCPORT, 2478 DSC_LOGIN_COMPLETE, 2479 DSC_ADISC, 2480 DSC_DELETE_PEND, 2481 DSC_LOGIN_AUTH_PEND, 2482 }; 2483 2484 enum login_state { /* FW control Target side */ 2485 DSC_LS_LLIOCB_SENT = 2, 2486 DSC_LS_PLOGI_PEND, 2487 DSC_LS_PLOGI_COMP, 2488 DSC_LS_PRLI_PEND, 2489 DSC_LS_PRLI_COMP, 2490 DSC_LS_PORT_UNAVAIL, 2491 DSC_LS_PRLO_PEND = 9, 2492 DSC_LS_LOGO_PEND, 2493 }; 2494 2495 enum rscn_addr_format { 2496 RSCN_PORT_ADDR, 2497 RSCN_AREA_ADDR, 2498 RSCN_DOM_ADDR, 2499 RSCN_FAB_ADDR, 2500 }; 2501 2502 /* 2503 * Fibre channel port structure. 2504 */ 2505 typedef struct fc_port { 2506 struct list_head list; 2507 struct scsi_qla_host *vha; 2508 2509 unsigned int conf_compl_supported:1; 2510 unsigned int deleted:2; 2511 unsigned int free_pending:1; 2512 unsigned int local:1; 2513 unsigned int logout_on_delete:1; 2514 unsigned int logo_ack_needed:1; 2515 unsigned int keep_nport_handle:1; 2516 unsigned int send_els_logo:1; 2517 unsigned int login_pause:1; 2518 unsigned int login_succ:1; 2519 unsigned int query:1; 2520 unsigned int id_changed:1; 2521 unsigned int scan_needed:1; 2522 unsigned int n2n_flag:1; 2523 unsigned int explicit_logout:1; 2524 unsigned int prli_pend_timer:1; 2525 unsigned int do_prli_nvme:1; 2526 2527 uint8_t nvme_flag; 2528 2529 uint8_t node_name[WWN_SIZE]; 2530 uint8_t port_name[WWN_SIZE]; 2531 port_id_t d_id; 2532 uint16_t loop_id; 2533 uint16_t old_loop_id; 2534 2535 struct completion nvme_del_done; 2536 uint32_t nvme_prli_service_param; 2537 #define NVME_PRLI_SP_PI_CTRL BIT_9 2538 #define NVME_PRLI_SP_SLER BIT_8 2539 #define NVME_PRLI_SP_CONF BIT_7 2540 #define NVME_PRLI_SP_INITIATOR BIT_5 2541 #define NVME_PRLI_SP_TARGET BIT_4 2542 #define NVME_PRLI_SP_DISCOVERY BIT_3 2543 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2544 2545 uint32_t nvme_first_burst_size; 2546 #define NVME_FLAG_REGISTERED 4 2547 #define NVME_FLAG_DELETING 2 2548 #define NVME_FLAG_RESETTING 1 2549 2550 struct fc_port *conflict; 2551 unsigned char logout_completed; 2552 int generation; 2553 2554 struct se_session *se_sess; 2555 struct list_head sess_cmd_list; 2556 spinlock_t sess_cmd_lock; 2557 struct kref sess_kref; 2558 struct qla_tgt *tgt; 2559 unsigned long expires; 2560 struct list_head del_list_entry; 2561 struct work_struct free_work; 2562 struct work_struct reg_work; 2563 uint64_t jiffies_at_registration; 2564 unsigned long prli_expired; 2565 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2566 2567 uint16_t tgt_id; 2568 uint16_t old_tgt_id; 2569 uint16_t sec_since_registration; 2570 2571 uint8_t fcp_prio; 2572 2573 uint8_t fabric_port_name[WWN_SIZE]; 2574 uint16_t fp_speed; 2575 2576 fc_port_type_t port_type; 2577 2578 atomic_t state; 2579 uint32_t flags; 2580 2581 int login_retry; 2582 2583 struct fc_rport *rport, *drport; 2584 u32 supported_classes; 2585 2586 uint8_t fc4_type; 2587 uint8_t fc4_features; 2588 uint8_t scan_state; 2589 2590 unsigned long last_queue_full; 2591 unsigned long last_ramp_up; 2592 2593 uint16_t port_id; 2594 2595 struct nvme_fc_remote_port *nvme_remote_port; 2596 2597 unsigned long retry_delay_timestamp; 2598 struct qla_tgt_sess *tgt_session; 2599 struct ct_sns_desc ct_desc; 2600 enum discovery_state disc_state; 2601 atomic_t shadow_disc_state; 2602 enum discovery_state next_disc_state; 2603 enum login_state fw_login_state; 2604 unsigned long dm_login_expire; 2605 unsigned long plogi_nack_done_deadline; 2606 2607 u32 login_gen, last_login_gen; 2608 u32 rscn_gen, last_rscn_gen; 2609 u32 chip_reset; 2610 struct list_head gnl_entry; 2611 struct work_struct del_work; 2612 u8 iocb[IOCB_SIZE]; 2613 u8 current_login_state; 2614 u8 last_login_state; 2615 u16 n2n_link_reset_cnt; 2616 u16 n2n_chip_reset; 2617 2618 struct dentry *dfs_rport_dir; 2619 2620 u64 tgt_short_link_down_cnt; 2621 u64 tgt_link_down_time; 2622 u64 dev_loss_tmo; 2623 /* 2624 * EDIF parameters for encryption. 2625 */ 2626 struct { 2627 uint32_t enable:1; /* device is edif enabled/req'd */ 2628 uint32_t app_stop:2; 2629 uint32_t app_started:1; 2630 uint32_t aes_gmac:1; 2631 uint32_t app_sess_online:1; 2632 uint32_t tx_sa_set:1; 2633 uint32_t rx_sa_set:1; 2634 uint32_t tx_sa_pending:1; 2635 uint32_t rx_sa_pending:1; 2636 uint32_t tx_rekey_cnt; 2637 uint32_t rx_rekey_cnt; 2638 uint64_t tx_bytes; 2639 uint64_t rx_bytes; 2640 uint8_t auth_state; 2641 uint16_t authok:1; 2642 uint16_t rekey_cnt; 2643 struct list_head edif_indx_list; 2644 spinlock_t indx_list_lock; 2645 2646 struct list_head tx_sa_list; 2647 struct list_head rx_sa_list; 2648 spinlock_t sa_list_lock; 2649 } edif; 2650 } fc_port_t; 2651 2652 enum { 2653 FC4_PRIORITY_NVME = 1, 2654 FC4_PRIORITY_FCP = 2, 2655 }; 2656 2657 #define QLA_FCPORT_SCAN 1 2658 #define QLA_FCPORT_FOUND 2 2659 2660 struct event_arg { 2661 fc_port_t *fcport; 2662 srb_t *sp; 2663 port_id_t id; 2664 u16 data[2], rc; 2665 u8 port_name[WWN_SIZE]; 2666 u32 iop[2]; 2667 }; 2668 2669 #include "qla_mr.h" 2670 2671 /* 2672 * Fibre channel port/lun states. 2673 */ 2674 enum { 2675 FCS_UNKNOWN, 2676 FCS_UNCONFIGURED, 2677 FCS_DEVICE_DEAD, 2678 FCS_DEVICE_LOST, 2679 FCS_ONLINE, 2680 }; 2681 2682 extern const char *const port_state_str[5]; 2683 2684 static const char *const port_dstate_str[] = { 2685 [DSC_DELETED] = "DELETED", 2686 [DSC_GNN_ID] = "GNN_ID", 2687 [DSC_GNL] = "GNL", 2688 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2689 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2690 [DSC_GPDB] = "GPDB", 2691 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2692 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2693 [DSC_ADISC] = "ADISC", 2694 [DSC_DELETE_PEND] = "DELETE_PEND", 2695 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2696 }; 2697 2698 /* 2699 * FC port flags. 2700 */ 2701 #define FCF_FABRIC_DEVICE BIT_0 2702 #define FCF_LOGIN_NEEDED BIT_1 2703 #define FCF_FCP2_DEVICE BIT_2 2704 #define FCF_ASYNC_SENT BIT_3 2705 #define FCF_CONF_COMP_SUPPORTED BIT_4 2706 #define FCF_ASYNC_ACTIVE BIT_5 2707 #define FCF_FCSP_DEVICE BIT_6 2708 #define FCF_EDIF_DELETE BIT_7 2709 2710 /* No loop ID flag. */ 2711 #define FC_NO_LOOP_ID 0x1000 2712 2713 /* 2714 * FC-CT interface 2715 * 2716 * NOTE: All structures are big-endian in form. 2717 */ 2718 2719 #define CT_REJECT_RESPONSE 0x8001 2720 #define CT_ACCEPT_RESPONSE 0x8002 2721 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2722 #define CT_REASON_CANNOT_PERFORM 0x09 2723 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2724 #define CT_EXPL_ALREADY_REGISTERED 0x10 2725 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2726 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2727 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2728 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2729 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2730 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2731 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2732 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2733 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2734 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2735 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2736 2737 #define NS_N_PORT_TYPE 0x01 2738 #define NS_NL_PORT_TYPE 0x02 2739 #define NS_NX_PORT_TYPE 0x7F 2740 2741 #define GA_NXT_CMD 0x100 2742 #define GA_NXT_REQ_SIZE (16 + 4) 2743 #define GA_NXT_RSP_SIZE (16 + 620) 2744 2745 #define GPN_FT_CMD 0x172 2746 #define GPN_FT_REQ_SIZE (16 + 4) 2747 #define GNN_FT_CMD 0x173 2748 #define GNN_FT_REQ_SIZE (16 + 4) 2749 2750 #define GID_PT_CMD 0x1A1 2751 #define GID_PT_REQ_SIZE (16 + 4) 2752 2753 #define GPN_ID_CMD 0x112 2754 #define GPN_ID_REQ_SIZE (16 + 4) 2755 #define GPN_ID_RSP_SIZE (16 + 8) 2756 2757 #define GNN_ID_CMD 0x113 2758 #define GNN_ID_REQ_SIZE (16 + 4) 2759 #define GNN_ID_RSP_SIZE (16 + 8) 2760 2761 #define GFT_ID_CMD 0x117 2762 #define GFT_ID_REQ_SIZE (16 + 4) 2763 #define GFT_ID_RSP_SIZE (16 + 32) 2764 2765 #define GID_PN_CMD 0x121 2766 #define GID_PN_REQ_SIZE (16 + 8) 2767 #define GID_PN_RSP_SIZE (16 + 4) 2768 2769 #define RFT_ID_CMD 0x217 2770 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2771 #define RFT_ID_RSP_SIZE 16 2772 2773 #define RFF_ID_CMD 0x21F 2774 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2775 #define RFF_ID_RSP_SIZE 16 2776 2777 #define RNN_ID_CMD 0x213 2778 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2779 #define RNN_ID_RSP_SIZE 16 2780 2781 #define RSNN_NN_CMD 0x239 2782 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2783 #define RSNN_NN_RSP_SIZE 16 2784 2785 #define GFPN_ID_CMD 0x11C 2786 #define GFPN_ID_REQ_SIZE (16 + 4) 2787 #define GFPN_ID_RSP_SIZE (16 + 8) 2788 2789 #define GPSC_CMD 0x127 2790 #define GPSC_REQ_SIZE (16 + 8) 2791 #define GPSC_RSP_SIZE (16 + 2 + 2) 2792 2793 #define GFF_ID_CMD 0x011F 2794 #define GFF_ID_REQ_SIZE (16 + 4) 2795 #define GFF_ID_RSP_SIZE (16 + 128) 2796 2797 /* 2798 * FDMI HBA attribute types. 2799 */ 2800 #define FDMI1_HBA_ATTR_COUNT 10 2801 #define FDMI2_HBA_ATTR_COUNT 17 2802 2803 #define FDMI_HBA_NODE_NAME 0x1 2804 #define FDMI_HBA_MANUFACTURER 0x2 2805 #define FDMI_HBA_SERIAL_NUMBER 0x3 2806 #define FDMI_HBA_MODEL 0x4 2807 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2808 #define FDMI_HBA_HARDWARE_VERSION 0x6 2809 #define FDMI_HBA_DRIVER_VERSION 0x7 2810 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2811 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2812 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2813 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2814 2815 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2816 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2817 #define FDMI_HBA_NUM_PORTS 0xe 2818 #define FDMI_HBA_FABRIC_NAME 0xf 2819 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2820 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2821 2822 struct ct_fdmi_hba_attr { 2823 __be16 type; 2824 __be16 len; 2825 union { 2826 uint8_t node_name[WWN_SIZE]; 2827 uint8_t manufacturer[64]; 2828 uint8_t serial_num[32]; 2829 uint8_t model[16+1]; 2830 uint8_t model_desc[80]; 2831 uint8_t hw_version[32]; 2832 uint8_t driver_version[32]; 2833 uint8_t orom_version[16]; 2834 uint8_t fw_version[32]; 2835 uint8_t os_version[128]; 2836 __be32 max_ct_len; 2837 2838 uint8_t sym_name[256]; 2839 __be32 vendor_specific_info; 2840 __be32 num_ports; 2841 uint8_t fabric_name[WWN_SIZE]; 2842 uint8_t bios_name[32]; 2843 uint8_t vendor_identifier[8]; 2844 } a; 2845 }; 2846 2847 struct ct_fdmi1_hba_attributes { 2848 __be32 count; 2849 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2850 }; 2851 2852 struct ct_fdmi2_hba_attributes { 2853 __be32 count; 2854 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2855 }; 2856 2857 /* 2858 * FDMI Port attribute types. 2859 */ 2860 #define FDMI1_PORT_ATTR_COUNT 6 2861 #define FDMI2_PORT_ATTR_COUNT 16 2862 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2863 2864 #define FDMI_PORT_FC4_TYPES 0x1 2865 #define FDMI_PORT_SUPPORT_SPEED 0x2 2866 #define FDMI_PORT_CURRENT_SPEED 0x3 2867 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2868 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2869 #define FDMI_PORT_HOST_NAME 0x6 2870 2871 #define FDMI_PORT_NODE_NAME 0x7 2872 #define FDMI_PORT_NAME 0x8 2873 #define FDMI_PORT_SYM_NAME 0x9 2874 #define FDMI_PORT_TYPE 0xa 2875 #define FDMI_PORT_SUPP_COS 0xb 2876 #define FDMI_PORT_FABRIC_NAME 0xc 2877 #define FDMI_PORT_FC4_TYPE 0xd 2878 #define FDMI_PORT_STATE 0x101 2879 #define FDMI_PORT_COUNT 0x102 2880 #define FDMI_PORT_IDENTIFIER 0x103 2881 2882 #define FDMI_SMARTSAN_SERVICE 0xF100 2883 #define FDMI_SMARTSAN_GUID 0xF101 2884 #define FDMI_SMARTSAN_VERSION 0xF102 2885 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2886 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2887 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2888 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2889 2890 #define FDMI_PORT_SPEED_1GB 0x1 2891 #define FDMI_PORT_SPEED_2GB 0x2 2892 #define FDMI_PORT_SPEED_10GB 0x4 2893 #define FDMI_PORT_SPEED_4GB 0x8 2894 #define FDMI_PORT_SPEED_8GB 0x10 2895 #define FDMI_PORT_SPEED_16GB 0x20 2896 #define FDMI_PORT_SPEED_32GB 0x40 2897 #define FDMI_PORT_SPEED_20GB 0x80 2898 #define FDMI_PORT_SPEED_40GB 0x100 2899 #define FDMI_PORT_SPEED_128GB 0x200 2900 #define FDMI_PORT_SPEED_64GB 0x400 2901 #define FDMI_PORT_SPEED_256GB 0x800 2902 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2903 2904 #define FC_CLASS_2 0x04 2905 #define FC_CLASS_3 0x08 2906 #define FC_CLASS_2_3 0x0C 2907 2908 struct ct_fdmi_port_attr { 2909 __be16 type; 2910 __be16 len; 2911 union { 2912 uint8_t fc4_types[32]; 2913 __be32 sup_speed; 2914 __be32 cur_speed; 2915 __be32 max_frame_size; 2916 uint8_t os_dev_name[32]; 2917 uint8_t host_name[256]; 2918 2919 uint8_t node_name[WWN_SIZE]; 2920 uint8_t port_name[WWN_SIZE]; 2921 uint8_t port_sym_name[128]; 2922 __be32 port_type; 2923 __be32 port_supported_cos; 2924 uint8_t fabric_name[WWN_SIZE]; 2925 uint8_t port_fc4_type[32]; 2926 __be32 port_state; 2927 __be32 num_ports; 2928 __be32 port_id; 2929 2930 uint8_t smartsan_service[24]; 2931 uint8_t smartsan_guid[16]; 2932 uint8_t smartsan_version[24]; 2933 uint8_t smartsan_prod_name[16]; 2934 __be32 smartsan_port_info; 2935 __be32 smartsan_qos_support; 2936 __be32 smartsan_security_support; 2937 } a; 2938 }; 2939 2940 struct ct_fdmi1_port_attributes { 2941 __be32 count; 2942 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2943 }; 2944 2945 struct ct_fdmi2_port_attributes { 2946 __be32 count; 2947 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2948 }; 2949 2950 #define FDMI_ATTR_TYPELEN(obj) \ 2951 (sizeof((obj)->type) + sizeof((obj)->len)) 2952 2953 #define FDMI_ATTR_ALIGNMENT(len) \ 2954 (4 - ((len) & 3)) 2955 2956 /* FDMI register call options */ 2957 #define CALLOPT_FDMI1 0 2958 #define CALLOPT_FDMI2 1 2959 #define CALLOPT_FDMI2_SMARTSAN 2 2960 2961 /* FDMI definitions. */ 2962 #define GRHL_CMD 0x100 2963 #define GHAT_CMD 0x101 2964 #define GRPL_CMD 0x102 2965 #define GPAT_CMD 0x110 2966 2967 #define RHBA_CMD 0x200 2968 #define RHBA_RSP_SIZE 16 2969 2970 #define RHAT_CMD 0x201 2971 2972 #define RPRT_CMD 0x210 2973 #define RPRT_RSP_SIZE 24 2974 2975 #define RPA_CMD 0x211 2976 #define RPA_RSP_SIZE 16 2977 #define SMARTSAN_RPA_RSP_SIZE 24 2978 2979 #define DHBA_CMD 0x300 2980 #define DHBA_REQ_SIZE (16 + 8) 2981 #define DHBA_RSP_SIZE 16 2982 2983 #define DHAT_CMD 0x301 2984 #define DPRT_CMD 0x310 2985 #define DPA_CMD 0x311 2986 2987 /* CT command header -- request/response common fields */ 2988 struct ct_cmd_hdr { 2989 uint8_t revision; 2990 uint8_t in_id[3]; 2991 uint8_t gs_type; 2992 uint8_t gs_subtype; 2993 uint8_t options; 2994 uint8_t reserved; 2995 }; 2996 2997 /* CT command request */ 2998 struct ct_sns_req { 2999 struct ct_cmd_hdr header; 3000 __be16 command; 3001 __be16 max_rsp_size; 3002 uint8_t fragment_id; 3003 uint8_t reserved[3]; 3004 3005 union { 3006 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3007 struct { 3008 uint8_t reserved; 3009 be_id_t port_id; 3010 } port_id; 3011 3012 struct { 3013 uint8_t reserved; 3014 uint8_t domain; 3015 uint8_t area; 3016 uint8_t port_type; 3017 } gpn_ft; 3018 3019 struct { 3020 uint8_t port_type; 3021 uint8_t domain; 3022 uint8_t area; 3023 uint8_t reserved; 3024 } gid_pt; 3025 3026 struct { 3027 uint8_t reserved; 3028 be_id_t port_id; 3029 uint8_t fc4_types[32]; 3030 } rft_id; 3031 3032 struct { 3033 uint8_t reserved; 3034 be_id_t port_id; 3035 uint16_t reserved2; 3036 uint8_t fc4_feature; 3037 uint8_t fc4_type; 3038 } rff_id; 3039 3040 struct { 3041 uint8_t reserved; 3042 be_id_t port_id; 3043 uint8_t node_name[8]; 3044 } rnn_id; 3045 3046 struct { 3047 uint8_t node_name[8]; 3048 uint8_t name_len; 3049 uint8_t sym_node_name[255]; 3050 } rsnn_nn; 3051 3052 struct { 3053 uint8_t hba_identifier[8]; 3054 } ghat; 3055 3056 struct { 3057 uint8_t hba_identifier[8]; 3058 __be32 entry_count; 3059 uint8_t port_name[8]; 3060 struct ct_fdmi2_hba_attributes attrs; 3061 } rhba; 3062 3063 struct { 3064 uint8_t hba_identifier[8]; 3065 struct ct_fdmi1_hba_attributes attrs; 3066 } rhat; 3067 3068 struct { 3069 uint8_t port_name[8]; 3070 struct ct_fdmi2_port_attributes attrs; 3071 } rpa; 3072 3073 struct { 3074 uint8_t hba_identifier[8]; 3075 uint8_t port_name[8]; 3076 struct ct_fdmi2_port_attributes attrs; 3077 } rprt; 3078 3079 struct { 3080 uint8_t port_name[8]; 3081 } dhba; 3082 3083 struct { 3084 uint8_t port_name[8]; 3085 } dhat; 3086 3087 struct { 3088 uint8_t port_name[8]; 3089 } dprt; 3090 3091 struct { 3092 uint8_t port_name[8]; 3093 } dpa; 3094 3095 struct { 3096 uint8_t port_name[8]; 3097 } gpsc; 3098 3099 struct { 3100 uint8_t reserved; 3101 uint8_t port_id[3]; 3102 } gff_id; 3103 3104 struct { 3105 uint8_t port_name[8]; 3106 } gid_pn; 3107 } req; 3108 }; 3109 3110 /* CT command response header */ 3111 struct ct_rsp_hdr { 3112 struct ct_cmd_hdr header; 3113 __be16 response; 3114 uint16_t residual; 3115 uint8_t fragment_id; 3116 uint8_t reason_code; 3117 uint8_t explanation_code; 3118 uint8_t vendor_unique; 3119 }; 3120 3121 struct ct_sns_gid_pt_data { 3122 uint8_t control_byte; 3123 be_id_t port_id; 3124 }; 3125 3126 /* It's the same for both GPN_FT and GNN_FT */ 3127 struct ct_sns_gpnft_rsp { 3128 struct { 3129 struct ct_cmd_hdr header; 3130 uint16_t response; 3131 uint16_t residual; 3132 uint8_t fragment_id; 3133 uint8_t reason_code; 3134 uint8_t explanation_code; 3135 uint8_t vendor_unique; 3136 }; 3137 /* Assume the largest number of targets for the union */ 3138 struct ct_sns_gpn_ft_data { 3139 u8 control_byte; 3140 u8 port_id[3]; 3141 u32 reserved; 3142 u8 port_name[8]; 3143 } entries[1]; 3144 }; 3145 3146 /* CT command response */ 3147 struct ct_sns_rsp { 3148 struct ct_rsp_hdr header; 3149 3150 union { 3151 struct { 3152 uint8_t port_type; 3153 be_id_t port_id; 3154 uint8_t port_name[8]; 3155 uint8_t sym_port_name_len; 3156 uint8_t sym_port_name[255]; 3157 uint8_t node_name[8]; 3158 uint8_t sym_node_name_len; 3159 uint8_t sym_node_name[255]; 3160 uint8_t init_proc_assoc[8]; 3161 uint8_t node_ip_addr[16]; 3162 uint8_t class_of_service[4]; 3163 uint8_t fc4_types[32]; 3164 uint8_t ip_address[16]; 3165 uint8_t fabric_port_name[8]; 3166 uint8_t reserved; 3167 uint8_t hard_address[3]; 3168 } ga_nxt; 3169 3170 struct { 3171 /* Assume the largest number of targets for the union */ 3172 struct ct_sns_gid_pt_data 3173 entries[MAX_FIBRE_DEVICES_MAX]; 3174 } gid_pt; 3175 3176 struct { 3177 uint8_t port_name[8]; 3178 } gpn_id; 3179 3180 struct { 3181 uint8_t node_name[8]; 3182 } gnn_id; 3183 3184 struct { 3185 uint8_t fc4_types[32]; 3186 } gft_id; 3187 3188 struct { 3189 uint32_t entry_count; 3190 uint8_t port_name[8]; 3191 struct ct_fdmi1_hba_attributes attrs; 3192 } ghat; 3193 3194 struct { 3195 uint8_t port_name[8]; 3196 } gfpn_id; 3197 3198 struct { 3199 __be16 speeds; 3200 __be16 speed; 3201 } gpsc; 3202 3203 #define GFF_FCP_SCSI_OFFSET 7 3204 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3205 struct { 3206 uint8_t fc4_features[128]; 3207 } gff_id; 3208 struct { 3209 uint8_t reserved; 3210 uint8_t port_id[3]; 3211 } gid_pn; 3212 } rsp; 3213 }; 3214 3215 struct ct_sns_pkt { 3216 union { 3217 struct ct_sns_req req; 3218 struct ct_sns_rsp rsp; 3219 } p; 3220 }; 3221 3222 struct ct_sns_gpnft_pkt { 3223 union { 3224 struct ct_sns_req req; 3225 struct ct_sns_gpnft_rsp rsp; 3226 } p; 3227 }; 3228 3229 enum scan_flags_t { 3230 SF_SCANNING = BIT_0, 3231 SF_QUEUED = BIT_1, 3232 }; 3233 3234 enum fc4type_t { 3235 FS_FC4TYPE_FCP = BIT_0, 3236 FS_FC4TYPE_NVME = BIT_1, 3237 FS_FCP_IS_N2N = BIT_7, 3238 }; 3239 3240 struct fab_scan_rp { 3241 port_id_t id; 3242 enum fc4type_t fc4type; 3243 u8 port_name[8]; 3244 u8 node_name[8]; 3245 }; 3246 3247 struct fab_scan { 3248 struct fab_scan_rp *l; 3249 u32 size; 3250 u16 scan_retry; 3251 #define MAX_SCAN_RETRIES 5 3252 enum scan_flags_t scan_flags; 3253 struct delayed_work scan_work; 3254 }; 3255 3256 /* 3257 * SNS command structures -- for 2200 compatibility. 3258 */ 3259 #define RFT_ID_SNS_SCMD_LEN 22 3260 #define RFT_ID_SNS_CMD_SIZE 60 3261 #define RFT_ID_SNS_DATA_SIZE 16 3262 3263 #define RNN_ID_SNS_SCMD_LEN 10 3264 #define RNN_ID_SNS_CMD_SIZE 36 3265 #define RNN_ID_SNS_DATA_SIZE 16 3266 3267 #define GA_NXT_SNS_SCMD_LEN 6 3268 #define GA_NXT_SNS_CMD_SIZE 28 3269 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3270 3271 #define GID_PT_SNS_SCMD_LEN 6 3272 #define GID_PT_SNS_CMD_SIZE 28 3273 /* 3274 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3275 * adapters. 3276 */ 3277 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3278 3279 #define GPN_ID_SNS_SCMD_LEN 6 3280 #define GPN_ID_SNS_CMD_SIZE 28 3281 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3282 3283 #define GNN_ID_SNS_SCMD_LEN 6 3284 #define GNN_ID_SNS_CMD_SIZE 28 3285 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3286 3287 struct sns_cmd_pkt { 3288 union { 3289 struct { 3290 __le16 buffer_length; 3291 __le16 reserved_1; 3292 __le64 buffer_address __packed; 3293 __le16 subcommand_length; 3294 __le16 reserved_2; 3295 __le16 subcommand; 3296 __le16 size; 3297 uint32_t reserved_3; 3298 uint8_t param[36]; 3299 } cmd; 3300 3301 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3302 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3303 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3304 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3305 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3306 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3307 } p; 3308 }; 3309 3310 struct fw_blob { 3311 char *name; 3312 uint32_t segs[4]; 3313 const struct firmware *fw; 3314 }; 3315 3316 /* Return data from MBC_GET_ID_LIST call. */ 3317 struct gid_list_info { 3318 uint8_t al_pa; 3319 uint8_t area; 3320 uint8_t domain; 3321 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3322 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3323 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3324 }; 3325 3326 /* NPIV */ 3327 typedef struct vport_info { 3328 uint8_t port_name[WWN_SIZE]; 3329 uint8_t node_name[WWN_SIZE]; 3330 int vp_id; 3331 uint16_t loop_id; 3332 unsigned long host_no; 3333 uint8_t port_id[3]; 3334 int loop_state; 3335 } vport_info_t; 3336 3337 typedef struct vport_params { 3338 uint8_t port_name[WWN_SIZE]; 3339 uint8_t node_name[WWN_SIZE]; 3340 uint32_t options; 3341 #define VP_OPTS_RETRY_ENABLE BIT_0 3342 #define VP_OPTS_VP_DISABLE BIT_1 3343 } vport_params_t; 3344 3345 /* NPIV - return codes of VP create and modify */ 3346 #define VP_RET_CODE_OK 0 3347 #define VP_RET_CODE_FATAL 1 3348 #define VP_RET_CODE_WRONG_ID 2 3349 #define VP_RET_CODE_WWPN 3 3350 #define VP_RET_CODE_RESOURCES 4 3351 #define VP_RET_CODE_NO_MEM 5 3352 #define VP_RET_CODE_NOT_FOUND 6 3353 3354 struct qla_hw_data; 3355 struct rsp_que; 3356 /* 3357 * ISP operations 3358 */ 3359 struct isp_operations { 3360 3361 int (*pci_config) (struct scsi_qla_host *); 3362 int (*reset_chip)(struct scsi_qla_host *); 3363 int (*chip_diag) (struct scsi_qla_host *); 3364 void (*config_rings) (struct scsi_qla_host *); 3365 int (*reset_adapter)(struct scsi_qla_host *); 3366 int (*nvram_config) (struct scsi_qla_host *); 3367 void (*update_fw_options) (struct scsi_qla_host *); 3368 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3369 3370 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3371 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3372 3373 irq_handler_t intr_handler; 3374 void (*enable_intrs) (struct qla_hw_data *); 3375 void (*disable_intrs) (struct qla_hw_data *); 3376 3377 int (*abort_command) (srb_t *); 3378 int (*target_reset) (struct fc_port *, uint64_t, int); 3379 int (*lun_reset) (struct fc_port *, uint64_t, int); 3380 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3381 uint8_t, uint8_t, uint16_t *, uint8_t); 3382 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3383 uint8_t, uint8_t); 3384 3385 uint16_t (*calc_req_entries) (uint16_t); 3386 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3387 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3388 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3389 uint32_t); 3390 3391 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3392 uint32_t, uint32_t); 3393 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3394 uint32_t); 3395 3396 void (*fw_dump)(struct scsi_qla_host *vha); 3397 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3398 3399 /* Context: task, might sleep */ 3400 int (*beacon_on) (struct scsi_qla_host *); 3401 int (*beacon_off) (struct scsi_qla_host *); 3402 3403 void (*beacon_blink) (struct scsi_qla_host *); 3404 3405 void *(*read_optrom)(struct scsi_qla_host *, void *, 3406 uint32_t, uint32_t); 3407 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3408 uint32_t); 3409 3410 int (*get_flash_version) (struct scsi_qla_host *, void *); 3411 int (*start_scsi) (srb_t *); 3412 int (*start_scsi_mq) (srb_t *); 3413 3414 /* Context: task, might sleep */ 3415 int (*abort_isp) (struct scsi_qla_host *); 3416 3417 int (*iospace_config)(struct qla_hw_data *); 3418 int (*initialize_adapter)(struct scsi_qla_host *); 3419 }; 3420 3421 /* MSI-X Support *************************************************************/ 3422 3423 #define QLA_MSIX_CHIP_REV_24XX 3 3424 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3425 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3426 3427 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3428 #define QLA_MSIX_RSP_Q 0x01 3429 #define QLA_ATIO_VECTOR 0x02 3430 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3431 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3432 3433 #define QLA_MIDX_DEFAULT 0 3434 #define QLA_MIDX_RSP_Q 1 3435 #define QLA_PCI_MSIX_CONTROL 0xa2 3436 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3437 3438 struct scsi_qla_host; 3439 3440 3441 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3442 3443 struct qla_msix_entry { 3444 int have_irq; 3445 int in_use; 3446 uint32_t vector; 3447 uint16_t entry; 3448 char name[30]; 3449 void *handle; 3450 int cpuid; 3451 }; 3452 3453 #define WATCH_INTERVAL 1 /* number of seconds */ 3454 3455 /* Work events. */ 3456 enum qla_work_type { 3457 QLA_EVT_AEN, 3458 QLA_EVT_IDC_ACK, 3459 QLA_EVT_ASYNC_LOGIN, 3460 QLA_EVT_ASYNC_LOGOUT, 3461 QLA_EVT_ASYNC_ADISC, 3462 QLA_EVT_UEVENT, 3463 QLA_EVT_AENFX, 3464 QLA_EVT_GPNID, 3465 QLA_EVT_UNMAP, 3466 QLA_EVT_NEW_SESS, 3467 QLA_EVT_GPDB, 3468 QLA_EVT_PRLI, 3469 QLA_EVT_GPSC, 3470 QLA_EVT_GNL, 3471 QLA_EVT_NACK, 3472 QLA_EVT_RELOGIN, 3473 QLA_EVT_ASYNC_PRLO, 3474 QLA_EVT_ASYNC_PRLO_DONE, 3475 QLA_EVT_GPNFT, 3476 QLA_EVT_GPNFT_DONE, 3477 QLA_EVT_GNNFT_DONE, 3478 QLA_EVT_GNNID, 3479 QLA_EVT_GFPNID, 3480 QLA_EVT_SP_RETRY, 3481 QLA_EVT_IIDMA, 3482 QLA_EVT_ELS_PLOGI, 3483 QLA_EVT_SA_REPLACE, 3484 }; 3485 3486 3487 struct qla_work_evt { 3488 struct list_head list; 3489 enum qla_work_type type; 3490 u32 flags; 3491 #define QLA_EVT_FLAG_FREE 0x1 3492 3493 union { 3494 struct { 3495 enum fc_host_event_code code; 3496 u32 data; 3497 } aen; 3498 struct { 3499 #define QLA_IDC_ACK_REGS 7 3500 uint16_t mb[QLA_IDC_ACK_REGS]; 3501 } idc_ack; 3502 struct { 3503 struct fc_port *fcport; 3504 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3505 u16 data[2]; 3506 } logio; 3507 struct { 3508 u32 code; 3509 #define QLA_UEVENT_CODE_FW_DUMP 0 3510 } uevent; 3511 struct { 3512 uint32_t evtcode; 3513 uint32_t mbx[8]; 3514 uint32_t count; 3515 } aenfx; 3516 struct { 3517 srb_t *sp; 3518 } iosb; 3519 struct { 3520 port_id_t id; 3521 } gpnid; 3522 struct { 3523 port_id_t id; 3524 u8 port_name[8]; 3525 u8 node_name[8]; 3526 void *pla; 3527 u8 fc4_type; 3528 } new_sess; 3529 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3530 fc_port_t *fcport; 3531 u8 opt; 3532 } fcport; 3533 struct { 3534 fc_port_t *fcport; 3535 u8 iocb[IOCB_SIZE]; 3536 int type; 3537 } nack; 3538 struct { 3539 u8 fc4_type; 3540 srb_t *sp; 3541 } gpnft; 3542 struct { 3543 struct edif_sa_ctl *sa_ctl; 3544 fc_port_t *fcport; 3545 uint16_t nport_handle; 3546 } sa_update; 3547 } u; 3548 }; 3549 3550 struct qla_chip_state_84xx { 3551 struct list_head list; 3552 struct kref kref; 3553 3554 void *bus; 3555 spinlock_t access_lock; 3556 struct mutex fw_update_mutex; 3557 uint32_t fw_update; 3558 uint32_t op_fw_version; 3559 uint32_t op_fw_size; 3560 uint32_t op_fw_seq_size; 3561 uint32_t diag_fw_version; 3562 uint32_t gold_fw_version; 3563 }; 3564 3565 struct qla_dif_statistics { 3566 uint64_t dif_input_bytes; 3567 uint64_t dif_output_bytes; 3568 uint64_t dif_input_requests; 3569 uint64_t dif_output_requests; 3570 uint32_t dif_guard_err; 3571 uint32_t dif_ref_tag_err; 3572 uint32_t dif_app_tag_err; 3573 }; 3574 3575 struct qla_statistics { 3576 uint32_t total_isp_aborts; 3577 uint64_t input_bytes; 3578 uint64_t output_bytes; 3579 uint64_t input_requests; 3580 uint64_t output_requests; 3581 uint32_t control_requests; 3582 3583 uint64_t jiffies_at_last_reset; 3584 uint32_t stat_max_pend_cmds; 3585 uint32_t stat_max_qfull_cmds_alloc; 3586 uint32_t stat_max_qfull_cmds_dropped; 3587 3588 struct qla_dif_statistics qla_dif_stats; 3589 }; 3590 3591 struct bidi_statistics { 3592 unsigned long long io_count; 3593 unsigned long long transfer_bytes; 3594 }; 3595 3596 struct qla_tc_param { 3597 struct scsi_qla_host *vha; 3598 uint32_t blk_sz; 3599 uint32_t bufflen; 3600 struct scatterlist *sg; 3601 struct scatterlist *prot_sg; 3602 struct crc_context *ctx; 3603 uint8_t *ctx_dsd_alloced; 3604 }; 3605 3606 /* Multi queue support */ 3607 #define MBC_INITIALIZE_MULTIQ 0x1f 3608 #define QLA_QUE_PAGE 0X1000 3609 #define QLA_MQ_SIZE 32 3610 #define QLA_MAX_QUEUES 256 3611 #define ISP_QUE_REG(ha, id) \ 3612 ((ha->mqenable || IS_QLA83XX(ha) || \ 3613 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3614 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3615 ((void __iomem *)ha->iobase)) 3616 #define QLA_REQ_QUE_ID(tag) \ 3617 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3618 #define QLA_DEFAULT_QUE_QOS 5 3619 #define QLA_PRECONFIG_VPORTS 32 3620 #define QLA_MAX_VPORTS_QLA24XX 128 3621 #define QLA_MAX_VPORTS_QLA25XX 256 3622 3623 struct qla_tgt_counters { 3624 uint64_t qla_core_sbt_cmd; 3625 uint64_t core_qla_que_buf; 3626 uint64_t qla_core_ret_ctio; 3627 uint64_t core_qla_snd_status; 3628 uint64_t qla_core_ret_sta_ctio; 3629 uint64_t core_qla_free_cmd; 3630 uint64_t num_q_full_sent; 3631 uint64_t num_alloc_iocb_failed; 3632 uint64_t num_term_xchg_sent; 3633 }; 3634 3635 struct qla_counters { 3636 uint64_t input_bytes; 3637 uint64_t input_requests; 3638 uint64_t output_bytes; 3639 uint64_t output_requests; 3640 3641 }; 3642 3643 struct qla_qpair; 3644 3645 /* Response queue data structure */ 3646 struct rsp_que { 3647 dma_addr_t dma; 3648 response_t *ring; 3649 response_t *ring_ptr; 3650 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3651 __le32 __iomem *rsp_q_out; 3652 uint16_t ring_index; 3653 uint16_t out_ptr; 3654 uint16_t *in_ptr; /* queue shadow in index */ 3655 uint16_t length; 3656 uint16_t options; 3657 uint16_t rid; 3658 uint16_t id; 3659 uint16_t vp_idx; 3660 struct qla_hw_data *hw; 3661 struct qla_msix_entry *msix; 3662 struct req_que *req; 3663 srb_t *status_srb; /* status continuation entry */ 3664 struct qla_qpair *qpair; 3665 3666 dma_addr_t dma_fx00; 3667 response_t *ring_fx00; 3668 uint16_t length_fx00; 3669 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3670 }; 3671 3672 /* Request queue data structure */ 3673 struct req_que { 3674 dma_addr_t dma; 3675 request_t *ring; 3676 request_t *ring_ptr; 3677 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3678 __le32 __iomem *req_q_out; 3679 uint16_t ring_index; 3680 uint16_t in_ptr; 3681 uint16_t *out_ptr; /* queue shadow out index */ 3682 uint16_t cnt; 3683 uint16_t length; 3684 uint16_t options; 3685 uint16_t rid; 3686 uint16_t id; 3687 uint16_t qos; 3688 uint16_t vp_idx; 3689 struct rsp_que *rsp; 3690 srb_t **outstanding_cmds; 3691 uint32_t current_outstanding_cmd; 3692 uint16_t num_outstanding_cmds; 3693 int max_q_depth; 3694 3695 dma_addr_t dma_fx00; 3696 request_t *ring_fx00; 3697 uint16_t length_fx00; 3698 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3699 }; 3700 3701 struct qla_fw_resources { 3702 u16 iocbs_total; 3703 u16 iocbs_limit; 3704 u16 iocbs_qp_limit; 3705 u16 iocbs_used; 3706 }; 3707 3708 #define QLA_IOCB_PCT_LIMIT 95 3709 3710 /*Queue pair data structure */ 3711 struct qla_qpair { 3712 spinlock_t qp_lock; 3713 atomic_t ref_count; 3714 uint32_t lun_cnt; 3715 /* 3716 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3717 * legacy code. For other Qpair(s), it will point at qp_lock. 3718 */ 3719 spinlock_t *qp_lock_ptr; 3720 struct scsi_qla_host *vha; 3721 u32 chip_reset; 3722 3723 /* distill these fields down to 'online=0/1' 3724 * ha->flags.eeh_busy 3725 * ha->flags.pci_channel_io_perm_failure 3726 * base_vha->loop_state 3727 */ 3728 uint32_t online:1; 3729 /* move vha->flags.difdix_supported here */ 3730 uint32_t difdix_supported:1; 3731 uint32_t delete_in_progress:1; 3732 uint32_t fw_started:1; 3733 uint32_t enable_class_2:1; 3734 uint32_t enable_explicit_conf:1; 3735 uint32_t use_shadow_reg:1; 3736 uint32_t rcv_intr:1; 3737 3738 uint16_t id; /* qp number used with FW */ 3739 uint16_t vp_idx; /* vport ID */ 3740 mempool_t *srb_mempool; 3741 3742 struct pci_dev *pdev; 3743 void (*reqq_start_iocbs)(struct qla_qpair *); 3744 3745 /* to do: New driver: move queues to here instead of pointers */ 3746 struct req_que *req; 3747 struct rsp_que *rsp; 3748 struct atio_que *atio; 3749 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3750 struct qla_hw_data *hw; 3751 struct work_struct q_work; 3752 struct qla_counters counters; 3753 3754 struct list_head qp_list_elem; /* vha->qp_list */ 3755 struct list_head hints_list; 3756 3757 uint16_t retry_term_cnt; 3758 __le32 retry_term_exchg_addr; 3759 uint64_t retry_term_jiff; 3760 struct qla_tgt_counters tgt_counters; 3761 uint16_t cpuid; 3762 struct qla_fw_resources fwres ____cacheline_aligned; 3763 u32 cmd_cnt; 3764 u32 cmd_completion_cnt; 3765 u32 prev_completion_cnt; 3766 }; 3767 3768 /* Place holder for FW buffer parameters */ 3769 struct qlfc_fw { 3770 void *fw_buf; 3771 dma_addr_t fw_dma; 3772 uint32_t len; 3773 }; 3774 3775 struct rdp_req_payload { 3776 uint32_t els_request; 3777 uint32_t desc_list_len; 3778 3779 /* NPIV descriptor */ 3780 struct { 3781 uint32_t desc_tag; 3782 uint32_t desc_len; 3783 uint8_t reserved; 3784 uint8_t nport_id[3]; 3785 } npiv_desc; 3786 }; 3787 3788 struct rdp_rsp_payload { 3789 struct { 3790 __be32 cmd; 3791 __be32 len; 3792 } hdr; 3793 3794 /* LS Request Info descriptor */ 3795 struct { 3796 __be32 desc_tag; 3797 __be32 desc_len; 3798 __be32 req_payload_word_0; 3799 } ls_req_info_desc; 3800 3801 /* LS Request Info descriptor */ 3802 struct { 3803 __be32 desc_tag; 3804 __be32 desc_len; 3805 __be32 req_payload_word_0; 3806 } ls_req_info_desc2; 3807 3808 /* SFP diagnostic param descriptor */ 3809 struct { 3810 __be32 desc_tag; 3811 __be32 desc_len; 3812 __be16 temperature; 3813 __be16 vcc; 3814 __be16 tx_bias; 3815 __be16 tx_power; 3816 __be16 rx_power; 3817 __be16 sfp_flags; 3818 } sfp_diag_desc; 3819 3820 /* Port Speed Descriptor */ 3821 struct { 3822 __be32 desc_tag; 3823 __be32 desc_len; 3824 __be16 speed_capab; 3825 __be16 operating_speed; 3826 } port_speed_desc; 3827 3828 /* Link Error Status Descriptor */ 3829 struct { 3830 __be32 desc_tag; 3831 __be32 desc_len; 3832 __be32 link_fail_cnt; 3833 __be32 loss_sync_cnt; 3834 __be32 loss_sig_cnt; 3835 __be32 prim_seq_err_cnt; 3836 __be32 inval_xmit_word_cnt; 3837 __be32 inval_crc_cnt; 3838 uint8_t pn_port_phy_type; 3839 uint8_t reserved[3]; 3840 } ls_err_desc; 3841 3842 /* Port name description with diag param */ 3843 struct { 3844 __be32 desc_tag; 3845 __be32 desc_len; 3846 uint8_t WWNN[WWN_SIZE]; 3847 uint8_t WWPN[WWN_SIZE]; 3848 } port_name_diag_desc; 3849 3850 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3851 struct { 3852 __be32 desc_tag; 3853 __be32 desc_len; 3854 uint8_t WWNN[WWN_SIZE]; 3855 uint8_t WWPN[WWN_SIZE]; 3856 } port_name_direct_desc; 3857 3858 /* Buffer Credit descriptor */ 3859 struct { 3860 __be32 desc_tag; 3861 __be32 desc_len; 3862 __be32 fcport_b2b; 3863 __be32 attached_fcport_b2b; 3864 __be32 fcport_rtt; 3865 } buffer_credit_desc; 3866 3867 /* Optical Element Data Descriptor */ 3868 struct { 3869 __be32 desc_tag; 3870 __be32 desc_len; 3871 __be16 high_alarm; 3872 __be16 low_alarm; 3873 __be16 high_warn; 3874 __be16 low_warn; 3875 __be32 element_flags; 3876 } optical_elmt_desc[5]; 3877 3878 /* Optical Product Data Descriptor */ 3879 struct { 3880 __be32 desc_tag; 3881 __be32 desc_len; 3882 uint8_t vendor_name[16]; 3883 uint8_t part_number[16]; 3884 uint8_t serial_number[16]; 3885 uint8_t revision[4]; 3886 uint8_t date[8]; 3887 } optical_prod_desc; 3888 }; 3889 3890 #define RDP_DESC_LEN(obj) \ 3891 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3892 3893 #define RDP_PORT_SPEED_1GB BIT_15 3894 #define RDP_PORT_SPEED_2GB BIT_14 3895 #define RDP_PORT_SPEED_4GB BIT_13 3896 #define RDP_PORT_SPEED_10GB BIT_12 3897 #define RDP_PORT_SPEED_8GB BIT_11 3898 #define RDP_PORT_SPEED_16GB BIT_10 3899 #define RDP_PORT_SPEED_32GB BIT_9 3900 #define RDP_PORT_SPEED_64GB BIT_8 3901 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3902 3903 struct scsi_qlt_host { 3904 void *target_lport_ptr; 3905 struct mutex tgt_mutex; 3906 struct mutex tgt_host_action_mutex; 3907 struct qla_tgt *qla_tgt; 3908 }; 3909 3910 struct qlt_hw_data { 3911 /* Protected by hw lock */ 3912 uint32_t node_name_set:1; 3913 3914 dma_addr_t atio_dma; /* Physical address. */ 3915 struct atio *atio_ring; /* Base virtual address */ 3916 struct atio *atio_ring_ptr; /* Current address. */ 3917 uint16_t atio_ring_index; /* Current index. */ 3918 uint16_t atio_q_length; 3919 __le32 __iomem *atio_q_in; 3920 __le32 __iomem *atio_q_out; 3921 3922 const struct qla_tgt_func_tmpl *tgt_ops; 3923 struct qla_tgt_vp_map *tgt_vp_map; 3924 3925 int saved_set; 3926 __le16 saved_exchange_count; 3927 __le32 saved_firmware_options_1; 3928 __le32 saved_firmware_options_2; 3929 __le32 saved_firmware_options_3; 3930 uint8_t saved_firmware_options[2]; 3931 uint8_t saved_add_firmware_options[2]; 3932 3933 uint8_t tgt_node_name[WWN_SIZE]; 3934 3935 struct dentry *dfs_tgt_sess; 3936 struct dentry *dfs_tgt_port_database; 3937 struct dentry *dfs_naqp; 3938 3939 struct list_head q_full_list; 3940 uint32_t num_pend_cmds; 3941 uint32_t num_qfull_cmds_alloc; 3942 uint32_t num_qfull_cmds_dropped; 3943 spinlock_t q_full_lock; 3944 uint32_t leak_exchg_thresh_hold; 3945 spinlock_t sess_lock; 3946 int num_act_qpairs; 3947 #define DEFAULT_NAQP 2 3948 spinlock_t atio_lock ____cacheline_aligned; 3949 }; 3950 3951 #define MAX_QFULL_CMDS_ALLOC 8192 3952 #define Q_FULL_THRESH_HOLD_PERCENT 90 3953 #define Q_FULL_THRESH_HOLD(ha) \ 3954 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3955 3956 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3957 3958 struct qla_hw_data_stat { 3959 u32 num_fw_dump; 3960 u32 num_mpi_reset; 3961 }; 3962 3963 /* refer to pcie_do_recovery reference */ 3964 typedef enum { 3965 QLA_PCI_RESUME, 3966 QLA_PCI_ERR_DETECTED, 3967 QLA_PCI_MMIO_ENABLED, 3968 QLA_PCI_SLOT_RESET, 3969 } pci_error_state_t; 3970 /* 3971 * Qlogic host adapter specific data structure. 3972 */ 3973 struct qla_hw_data { 3974 struct pci_dev *pdev; 3975 /* SRB cache. */ 3976 #define SRB_MIN_REQ 128 3977 mempool_t *srb_mempool; 3978 3979 volatile struct { 3980 uint32_t mbox_int :1; 3981 uint32_t mbox_busy :1; 3982 uint32_t disable_risc_code_load :1; 3983 uint32_t enable_64bit_addressing :1; 3984 uint32_t enable_lip_reset :1; 3985 uint32_t enable_target_reset :1; 3986 uint32_t enable_lip_full_login :1; 3987 uint32_t enable_led_scheme :1; 3988 3989 uint32_t msi_enabled :1; 3990 uint32_t msix_enabled :1; 3991 uint32_t disable_serdes :1; 3992 uint32_t gpsc_supported :1; 3993 uint32_t npiv_supported :1; 3994 uint32_t pci_channel_io_perm_failure :1; 3995 uint32_t fce_enabled :1; 3996 uint32_t fac_supported :1; 3997 3998 uint32_t chip_reset_done :1; 3999 uint32_t running_gold_fw :1; 4000 uint32_t eeh_busy :1; 4001 uint32_t disable_msix_handshake :1; 4002 uint32_t fcp_prio_enabled :1; 4003 uint32_t isp82xx_fw_hung:1; 4004 uint32_t nic_core_hung:1; 4005 4006 uint32_t quiesce_owner:1; 4007 uint32_t nic_core_reset_hdlr_active:1; 4008 uint32_t nic_core_reset_owner:1; 4009 uint32_t isp82xx_no_md_cap:1; 4010 uint32_t host_shutting_down:1; 4011 uint32_t idc_compl_status:1; 4012 uint32_t mr_reset_hdlr_active:1; 4013 uint32_t mr_intr_valid:1; 4014 4015 uint32_t dport_enabled:1; 4016 uint32_t fawwpn_enabled:1; 4017 uint32_t exlogins_enabled:1; 4018 uint32_t exchoffld_enabled:1; 4019 4020 uint32_t lip_ae:1; 4021 uint32_t n2n_ae:1; 4022 uint32_t fw_started:1; 4023 uint32_t fw_init_done:1; 4024 4025 uint32_t lr_detected:1; 4026 4027 uint32_t rida_fmt2:1; 4028 uint32_t purge_mbox:1; 4029 uint32_t n2n_bigger:1; 4030 uint32_t secure_adapter:1; 4031 uint32_t secure_fw:1; 4032 /* Supported by Adapter */ 4033 uint32_t scm_supported_a:1; 4034 /* Supported by Firmware */ 4035 uint32_t scm_supported_f:1; 4036 /* Enabled in Driver */ 4037 uint32_t scm_enabled:1; 4038 uint32_t edif_hw:1; 4039 uint32_t edif_enabled:1; 4040 uint32_t n2n_fw_acc_sec:1; 4041 uint32_t plogi_template_valid:1; 4042 uint32_t port_isolated:1; 4043 } flags; 4044 4045 uint16_t max_exchg; 4046 uint16_t lr_distance; /* 32G & above */ 4047 #define LR_DISTANCE_5K 1 4048 #define LR_DISTANCE_10K 0 4049 4050 /* This spinlock is used to protect "io transactions", you must 4051 * acquire it before doing any IO to the card, eg with RD_REG*() and 4052 * WRT_REG*() for the duration of your entire commandtransaction. 4053 * 4054 * This spinlock is of lower priority than the io request lock. 4055 */ 4056 4057 spinlock_t hardware_lock ____cacheline_aligned; 4058 int bars; 4059 int mem_only; 4060 device_reg_t *iobase; /* Base I/O address */ 4061 resource_size_t pio_address; 4062 4063 #define MIN_IOBASE_LEN 0x100 4064 dma_addr_t bar0_hdl; 4065 4066 void __iomem *cregbase; 4067 dma_addr_t bar2_hdl; 4068 #define BAR0_LEN_FX00 (1024 * 1024) 4069 #define BAR2_LEN_FX00 (128 * 1024) 4070 4071 uint32_t rqstq_intr_code; 4072 uint32_t mbx_intr_code; 4073 uint32_t req_que_len; 4074 uint32_t rsp_que_len; 4075 uint32_t req_que_off; 4076 uint32_t rsp_que_off; 4077 4078 /* Multi queue data structs */ 4079 device_reg_t *mqiobase; 4080 device_reg_t *msixbase; 4081 uint16_t msix_count; 4082 uint8_t mqenable; 4083 struct req_que **req_q_map; 4084 struct rsp_que **rsp_q_map; 4085 struct qla_qpair **queue_pair_map; 4086 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4087 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4088 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4089 / sizeof(unsigned long)]; 4090 uint8_t max_req_queues; 4091 uint8_t max_rsp_queues; 4092 uint8_t max_qpairs; 4093 uint8_t num_qpairs; 4094 struct qla_qpair *base_qpair; 4095 struct qla_npiv_entry *npiv_info; 4096 uint16_t nvram_npiv_size; 4097 4098 uint16_t switch_cap; 4099 #define FLOGI_SEQ_DEL BIT_8 4100 #define FLOGI_MID_SUPPORT BIT_10 4101 #define FLOGI_VSAN_SUPPORT BIT_12 4102 #define FLOGI_SP_SUPPORT BIT_13 4103 4104 uint8_t port_no; /* Physical port of adapter */ 4105 uint8_t exch_starvation; 4106 4107 /* Timeout timers. */ 4108 uint8_t loop_down_abort_time; /* port down timer */ 4109 atomic_t loop_down_timer; /* loop down timer */ 4110 uint8_t link_down_timeout; /* link down timeout */ 4111 uint16_t max_loop_id; 4112 uint16_t max_fibre_devices; /* Maximum number of targets */ 4113 4114 uint16_t fb_rev; 4115 uint16_t min_external_loopid; /* First external loop Id */ 4116 4117 #define PORT_SPEED_UNKNOWN 0xFFFF 4118 #define PORT_SPEED_1GB 0x00 4119 #define PORT_SPEED_2GB 0x01 4120 #define PORT_SPEED_AUTO 0x02 4121 #define PORT_SPEED_4GB 0x03 4122 #define PORT_SPEED_8GB 0x04 4123 #define PORT_SPEED_16GB 0x05 4124 #define PORT_SPEED_32GB 0x06 4125 #define PORT_SPEED_64GB 0x07 4126 #define PORT_SPEED_10GB 0x13 4127 uint16_t link_data_rate; /* F/W operating speed */ 4128 uint16_t set_data_rate; /* Set by user */ 4129 4130 uint8_t current_topology; 4131 uint8_t prev_topology; 4132 #define ISP_CFG_NL 1 4133 #define ISP_CFG_N 2 4134 #define ISP_CFG_FL 4 4135 #define ISP_CFG_F 8 4136 4137 uint8_t operating_mode; /* F/W operating mode */ 4138 #define LOOP 0 4139 #define P2P 1 4140 #define LOOP_P2P 2 4141 #define P2P_LOOP 3 4142 uint8_t interrupts_on; 4143 uint32_t isp_abort_cnt; 4144 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4145 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4146 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4147 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4148 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4149 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4150 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4151 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4152 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4153 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4154 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4155 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4156 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4157 4158 uint32_t isp_type; 4159 #define DT_ISP2100 BIT_0 4160 #define DT_ISP2200 BIT_1 4161 #define DT_ISP2300 BIT_2 4162 #define DT_ISP2312 BIT_3 4163 #define DT_ISP2322 BIT_4 4164 #define DT_ISP6312 BIT_5 4165 #define DT_ISP6322 BIT_6 4166 #define DT_ISP2422 BIT_7 4167 #define DT_ISP2432 BIT_8 4168 #define DT_ISP5422 BIT_9 4169 #define DT_ISP5432 BIT_10 4170 #define DT_ISP2532 BIT_11 4171 #define DT_ISP8432 BIT_12 4172 #define DT_ISP8001 BIT_13 4173 #define DT_ISP8021 BIT_14 4174 #define DT_ISP2031 BIT_15 4175 #define DT_ISP8031 BIT_16 4176 #define DT_ISPFX00 BIT_17 4177 #define DT_ISP8044 BIT_18 4178 #define DT_ISP2071 BIT_19 4179 #define DT_ISP2271 BIT_20 4180 #define DT_ISP2261 BIT_21 4181 #define DT_ISP2061 BIT_22 4182 #define DT_ISP2081 BIT_23 4183 #define DT_ISP2089 BIT_24 4184 #define DT_ISP2281 BIT_25 4185 #define DT_ISP2289 BIT_26 4186 #define DT_ISP_LAST (DT_ISP2289 << 1) 4187 4188 uint32_t device_type; 4189 #define DT_T10_PI BIT_25 4190 #define DT_IIDMA BIT_26 4191 #define DT_FWI2 BIT_27 4192 #define DT_ZIO_SUPPORTED BIT_28 4193 #define DT_OEM_001 BIT_29 4194 #define DT_ISP2200A BIT_30 4195 #define DT_EXTENDED_IDS BIT_31 4196 4197 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4198 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4199 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4200 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4201 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4202 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4203 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4204 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4205 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4206 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4207 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4208 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4209 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4210 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4211 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4212 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4213 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4214 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4215 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4216 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4217 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4218 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4219 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4220 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4221 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4222 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4223 4224 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4225 IS_QLA6312(ha) || IS_QLA6322(ha)) 4226 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4227 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4228 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4229 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4230 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4231 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4232 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4233 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4234 IS_QLA84XX(ha)) 4235 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4236 IS_QLA8031(ha) || IS_QLA8044(ha)) 4237 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4238 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4239 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4240 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4241 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4242 IS_QLA28XX(ha)) 4243 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4244 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4245 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4246 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4247 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4248 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4249 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4250 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4251 4252 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4253 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4254 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4255 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4256 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4257 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4258 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4259 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 4260 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4261 #define IS_BIDI_CAPABLE(ha) \ 4262 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4263 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4264 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4265 ((ha)->fw_attributes_ext[0] & BIT_0)) 4266 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4267 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4268 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4269 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4270 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4271 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4272 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4273 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4274 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4275 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4276 4277 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4278 IS_QLA28XX(ha)) 4279 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4280 IS_QLA28XX(ha)) 4281 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4282 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4283 IS_QLA28XX(ha)) 4284 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4285 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4286 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4287 IS_QLA28XX(ha)) 4288 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4289 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4290 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4291 IS_QLA28XX(ha)) 4292 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4293 IS_QLA28XX(ha)) 4294 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4295 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4296 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4297 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4298 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4299 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4300 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4301 4302 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4303 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4304 (ha->zio_mode == QLA_ZIO_MODE_6)) 4305 4306 /* HBA serial number */ 4307 uint8_t serial0; 4308 uint8_t serial1; 4309 uint8_t serial2; 4310 4311 /* NVRAM configuration data */ 4312 #define MAX_NVRAM_SIZE 4096 4313 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4314 uint16_t nvram_size; 4315 uint16_t nvram_base; 4316 void *nvram; 4317 uint16_t vpd_size; 4318 uint16_t vpd_base; 4319 void *vpd; 4320 4321 uint16_t loop_reset_delay; 4322 uint8_t retry_count; 4323 uint8_t login_timeout; 4324 uint16_t r_a_tov; 4325 int port_down_retry_count; 4326 uint8_t mbx_count; 4327 uint8_t aen_mbx_count; 4328 atomic_t num_pend_mbx_stage1; 4329 atomic_t num_pend_mbx_stage2; 4330 atomic_t num_pend_mbx_stage3; 4331 uint16_t frame_payload_size; 4332 4333 uint32_t login_retry_count; 4334 /* SNS command interfaces. */ 4335 ms_iocb_entry_t *ms_iocb; 4336 dma_addr_t ms_iocb_dma; 4337 struct ct_sns_pkt *ct_sns; 4338 dma_addr_t ct_sns_dma; 4339 /* SNS command interfaces for 2200. */ 4340 struct sns_cmd_pkt *sns_cmd; 4341 dma_addr_t sns_cmd_dma; 4342 4343 #define SFP_DEV_SIZE 512 4344 #define SFP_BLOCK_SIZE 64 4345 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4346 4347 void *sfp_data; 4348 dma_addr_t sfp_data_dma; 4349 4350 struct qla_flt_header *flt; 4351 dma_addr_t flt_dma; 4352 4353 #define XGMAC_DATA_SIZE 4096 4354 void *xgmac_data; 4355 dma_addr_t xgmac_data_dma; 4356 4357 #define DCBX_TLV_DATA_SIZE 4096 4358 void *dcbx_tlv; 4359 dma_addr_t dcbx_tlv_dma; 4360 4361 struct task_struct *dpc_thread; 4362 uint8_t dpc_active; /* DPC routine is active */ 4363 4364 dma_addr_t gid_list_dma; 4365 struct gid_list_info *gid_list; 4366 int gid_list_info_size; 4367 4368 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4369 #define DMA_POOL_SIZE 256 4370 struct dma_pool *s_dma_pool; 4371 4372 dma_addr_t init_cb_dma; 4373 init_cb_t *init_cb; 4374 int init_cb_size; 4375 dma_addr_t ex_init_cb_dma; 4376 struct ex_init_cb_81xx *ex_init_cb; 4377 dma_addr_t sf_init_cb_dma; 4378 struct init_sf_cb *sf_init_cb; 4379 4380 void *scm_fpin_els_buff; 4381 uint64_t scm_fpin_els_buff_size; 4382 bool scm_fpin_valid; 4383 bool scm_fpin_payload_size; 4384 4385 void *async_pd; 4386 dma_addr_t async_pd_dma; 4387 4388 #define ENABLE_EXTENDED_LOGIN BIT_7 4389 4390 /* Extended Logins */ 4391 void *exlogin_buf; 4392 dma_addr_t exlogin_buf_dma; 4393 uint32_t exlogin_size; 4394 4395 #define ENABLE_EXCHANGE_OFFLD BIT_2 4396 4397 /* Exchange Offload */ 4398 void *exchoffld_buf; 4399 dma_addr_t exchoffld_buf_dma; 4400 int exchoffld_size; 4401 int exchoffld_count; 4402 4403 /* n2n */ 4404 struct fc_els_flogi plogi_els_payld; 4405 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4406 4407 void *swl; 4408 4409 /* These are used by mailbox operations. */ 4410 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4411 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4412 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4413 4414 mbx_cmd_t *mcp; 4415 struct mbx_cmd_32 *mcp32; 4416 4417 unsigned long mbx_cmd_flags; 4418 #define MBX_INTERRUPT 1 4419 #define MBX_INTR_WAIT 2 4420 #define MBX_UPDATE_FLASH_ACTIVE 3 4421 4422 struct mutex vport_lock; /* Virtual port synchronization */ 4423 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4424 struct mutex mq_lock; /* multi-queue synchronization */ 4425 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4426 struct completion mbx_intr_comp; /* Used for completion notification */ 4427 struct completion dcbx_comp; /* For set port config notification */ 4428 struct completion lb_portup_comp; /* Used to wait for link up during 4429 * loopback */ 4430 #define DCBX_COMP_TIMEOUT 20 4431 #define LB_PORTUP_COMP_TIMEOUT 10 4432 4433 int notify_dcbx_comp; 4434 int notify_lb_portup_comp; 4435 struct mutex selflogin_lock; 4436 4437 /* Basic firmware related information. */ 4438 uint16_t fw_major_version; 4439 uint16_t fw_minor_version; 4440 uint16_t fw_subminor_version; 4441 uint16_t fw_attributes; 4442 uint16_t fw_attributes_h; 4443 #define FW_ATTR_H_NVME_FBURST BIT_1 4444 #define FW_ATTR_H_NVME BIT_10 4445 #define FW_ATTR_H_NVME_UPDATED BIT_14 4446 4447 /* About firmware SCM support */ 4448 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4449 /* Brocade fabric attached */ 4450 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4451 /* Cisco fabric attached */ 4452 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4453 #define FW_ATTR_EXT0_NVME2 BIT_13 4454 #define FW_ATTR_EXT0_EDIF BIT_5 4455 uint16_t fw_attributes_ext[2]; 4456 uint32_t fw_memory_size; 4457 uint32_t fw_transfer_size; 4458 uint32_t fw_srisc_address; 4459 #define RISC_START_ADDRESS_2100 0x1000 4460 #define RISC_START_ADDRESS_2300 0x800 4461 #define RISC_START_ADDRESS_2400 0x100000 4462 4463 uint16_t orig_fw_tgt_xcb_count; 4464 uint16_t cur_fw_tgt_xcb_count; 4465 uint16_t orig_fw_xcb_count; 4466 uint16_t cur_fw_xcb_count; 4467 uint16_t orig_fw_iocb_count; 4468 uint16_t cur_fw_iocb_count; 4469 uint16_t fw_max_fcf_count; 4470 4471 uint32_t fw_shared_ram_start; 4472 uint32_t fw_shared_ram_end; 4473 uint32_t fw_ddr_ram_start; 4474 uint32_t fw_ddr_ram_end; 4475 4476 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4477 uint8_t fw_seriallink_options[4]; 4478 __le16 fw_seriallink_options24[4]; 4479 4480 uint8_t serdes_version[3]; 4481 uint8_t mpi_version[3]; 4482 uint32_t mpi_capabilities; 4483 uint8_t phy_version[3]; 4484 uint8_t pep_version[3]; 4485 4486 /* Firmware dump template */ 4487 struct fwdt { 4488 void *template; 4489 ulong length; 4490 ulong dump_size; 4491 } fwdt[2]; 4492 struct qla2xxx_fw_dump *fw_dump; 4493 uint32_t fw_dump_len; 4494 u32 fw_dump_alloc_len; 4495 bool fw_dumped; 4496 unsigned long fw_dump_cap_flags; 4497 #define RISC_PAUSE_CMPL 0 4498 #define DMA_SHUTDOWN_CMPL 1 4499 #define ISP_RESET_CMPL 2 4500 #define RISC_RDY_AFT_RESET 3 4501 #define RISC_SRAM_DUMP_CMPL 4 4502 #define RISC_EXT_MEM_DUMP_CMPL 5 4503 #define ISP_MBX_RDY 6 4504 #define ISP_SOFT_RESET_CMPL 7 4505 int fw_dump_reading; 4506 void *mpi_fw_dump; 4507 u32 mpi_fw_dump_len; 4508 unsigned int mpi_fw_dump_reading:1; 4509 unsigned int mpi_fw_dumped:1; 4510 int prev_minidump_failed; 4511 dma_addr_t eft_dma; 4512 void *eft; 4513 /* Current size of mctp dump is 0x086064 bytes */ 4514 #define MCTP_DUMP_SIZE 0x086064 4515 dma_addr_t mctp_dump_dma; 4516 void *mctp_dump; 4517 int mctp_dumped; 4518 int mctp_dump_reading; 4519 uint32_t chain_offset; 4520 struct dentry *dfs_dir; 4521 struct dentry *dfs_fce; 4522 struct dentry *dfs_tgt_counters; 4523 struct dentry *dfs_fw_resource_cnt; 4524 4525 dma_addr_t fce_dma; 4526 void *fce; 4527 uint32_t fce_bufs; 4528 uint16_t fce_mb[8]; 4529 uint64_t fce_wr, fce_rd; 4530 struct mutex fce_mutex; 4531 4532 uint32_t pci_attr; 4533 uint16_t chip_revision; 4534 4535 uint16_t product_id[4]; 4536 4537 uint8_t model_number[16+1]; 4538 char model_desc[80]; 4539 uint8_t adapter_id[16+1]; 4540 4541 /* Option ROM information. */ 4542 char *optrom_buffer; 4543 uint32_t optrom_size; 4544 int optrom_state; 4545 #define QLA_SWAITING 0 4546 #define QLA_SREADING 1 4547 #define QLA_SWRITING 2 4548 uint32_t optrom_region_start; 4549 uint32_t optrom_region_size; 4550 struct mutex optrom_mutex; 4551 4552 /* PCI expansion ROM image information. */ 4553 #define ROM_CODE_TYPE_BIOS 0 4554 #define ROM_CODE_TYPE_FCODE 1 4555 #define ROM_CODE_TYPE_EFI 3 4556 uint8_t bios_revision[2]; 4557 uint8_t efi_revision[2]; 4558 uint8_t fcode_revision[16]; 4559 uint32_t fw_revision[4]; 4560 4561 uint32_t gold_fw_version[4]; 4562 4563 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4564 uint32_t flash_conf_off; 4565 uint32_t flash_data_off; 4566 uint32_t nvram_conf_off; 4567 uint32_t nvram_data_off; 4568 4569 uint32_t fdt_wrt_disable; 4570 uint32_t fdt_wrt_enable; 4571 uint32_t fdt_erase_cmd; 4572 uint32_t fdt_block_size; 4573 uint32_t fdt_unprotect_sec_cmd; 4574 uint32_t fdt_protect_sec_cmd; 4575 uint32_t fdt_wrt_sts_reg_cmd; 4576 4577 struct { 4578 uint32_t flt_region_flt; 4579 uint32_t flt_region_fdt; 4580 uint32_t flt_region_boot; 4581 uint32_t flt_region_boot_sec; 4582 uint32_t flt_region_fw; 4583 uint32_t flt_region_fw_sec; 4584 uint32_t flt_region_vpd_nvram; 4585 uint32_t flt_region_vpd_nvram_sec; 4586 uint32_t flt_region_vpd; 4587 uint32_t flt_region_vpd_sec; 4588 uint32_t flt_region_nvram; 4589 uint32_t flt_region_nvram_sec; 4590 uint32_t flt_region_npiv_conf; 4591 uint32_t flt_region_gold_fw; 4592 uint32_t flt_region_fcp_prio; 4593 uint32_t flt_region_bootload; 4594 uint32_t flt_region_img_status_pri; 4595 uint32_t flt_region_img_status_sec; 4596 uint32_t flt_region_aux_img_status_pri; 4597 uint32_t flt_region_aux_img_status_sec; 4598 }; 4599 uint8_t active_image; 4600 4601 /* Needed for BEACON */ 4602 uint16_t beacon_blink_led; 4603 uint8_t beacon_color_state; 4604 #define QLA_LED_GRN_ON 0x01 4605 #define QLA_LED_YLW_ON 0x02 4606 #define QLA_LED_ABR_ON 0x04 4607 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4608 /* ISP2322: red, green, amber. */ 4609 uint16_t zio_mode; 4610 uint16_t zio_timer; 4611 4612 struct qla_msix_entry *msix_entries; 4613 4614 struct list_head vp_list; /* list of VP */ 4615 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4616 sizeof(unsigned long)]; 4617 uint16_t num_vhosts; /* number of vports created */ 4618 uint16_t num_vsans; /* number of vsan created */ 4619 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4620 int cur_vport_count; 4621 4622 struct qla_chip_state_84xx *cs84xx; 4623 struct isp_operations *isp_ops; 4624 struct workqueue_struct *wq; 4625 struct work_struct heartbeat_work; 4626 struct qlfc_fw fw_buf; 4627 unsigned long last_heartbeat_run_jiffies; 4628 4629 /* FCP_CMND priority support */ 4630 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4631 4632 struct dma_pool *dl_dma_pool; 4633 #define DSD_LIST_DMA_POOL_SIZE 512 4634 4635 struct dma_pool *fcp_cmnd_dma_pool; 4636 mempool_t *ctx_mempool; 4637 #define FCP_CMND_DMA_POOL_SIZE 512 4638 4639 void __iomem *nx_pcibase; /* Base I/O address */ 4640 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4641 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4642 4643 uint32_t crb_win; 4644 uint32_t curr_window; 4645 uint32_t ddr_mn_window; 4646 unsigned long mn_win_crb; 4647 unsigned long ms_win_crb; 4648 int qdr_sn_window; 4649 uint32_t fcoe_dev_init_timeout; 4650 uint32_t fcoe_reset_timeout; 4651 rwlock_t hw_lock; 4652 uint16_t portnum; /* port number */ 4653 int link_width; 4654 struct fw_blob *hablob; 4655 struct qla82xx_legacy_intr_set nx_legacy_intr; 4656 4657 uint16_t gbl_dsd_inuse; 4658 uint16_t gbl_dsd_avail; 4659 struct list_head gbl_dsd_list; 4660 #define NUM_DSD_CHAIN 4096 4661 4662 uint8_t fw_type; 4663 uint32_t file_prd_off; /* File firmware product offset */ 4664 4665 uint32_t md_template_size; 4666 void *md_tmplt_hdr; 4667 dma_addr_t md_tmplt_hdr_dma; 4668 void *md_dump; 4669 uint32_t md_dump_size; 4670 4671 void *loop_id_map; 4672 4673 /* QLA83XX IDC specific fields */ 4674 uint32_t idc_audit_ts; 4675 uint32_t idc_extend_tmo; 4676 4677 /* DPC low-priority workqueue */ 4678 struct workqueue_struct *dpc_lp_wq; 4679 struct work_struct idc_aen; 4680 /* DPC high-priority workqueue */ 4681 struct workqueue_struct *dpc_hp_wq; 4682 struct work_struct nic_core_reset; 4683 struct work_struct idc_state_handler; 4684 struct work_struct nic_core_unrecoverable; 4685 struct work_struct board_disable; 4686 4687 struct mr_data_fx00 mr; 4688 uint32_t chip_reset; 4689 4690 struct qlt_hw_data tgt; 4691 int allow_cna_fw_dump; 4692 uint32_t fw_ability_mask; 4693 uint16_t min_supported_speed; 4694 uint16_t max_supported_speed; 4695 4696 /* DMA pool for the DIF bundling buffers */ 4697 struct dma_pool *dif_bundl_pool; 4698 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4699 struct { 4700 struct { 4701 struct list_head head; 4702 uint count; 4703 } good; 4704 struct { 4705 struct list_head head; 4706 uint count; 4707 } unusable; 4708 } pool; 4709 4710 unsigned long long dif_bundle_crossed_pages; 4711 unsigned long long dif_bundle_reads; 4712 unsigned long long dif_bundle_writes; 4713 unsigned long long dif_bundle_kallocs; 4714 unsigned long long dif_bundle_dma_allocs; 4715 4716 atomic_t nvme_active_aen_cnt; 4717 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4718 4719 uint8_t fc4_type_priority; 4720 4721 atomic_t zio_threshold; 4722 uint16_t last_zio_threshold; 4723 4724 #define DEFAULT_ZIO_THRESHOLD 5 4725 4726 struct qla_hw_data_stat stat; 4727 pci_error_state_t pci_error_state; 4728 struct dma_pool *purex_dma_pool; 4729 struct btree_head32 host_map; 4730 4731 #define EDIF_NUM_SA_INDEX 512 4732 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4733 void *edif_rx_sa_id_map; 4734 void *edif_tx_sa_id_map; 4735 spinlock_t sadb_fp_lock; 4736 4737 struct list_head sadb_tx_index_list; 4738 struct list_head sadb_rx_index_list; 4739 spinlock_t sadb_lock; /* protects list */ 4740 struct els_reject elsrej; 4741 u8 edif_post_stop_cnt_down; 4742 }; 4743 4744 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4745 4746 struct active_regions { 4747 uint8_t global; 4748 struct { 4749 uint8_t board_config; 4750 uint8_t vpd_nvram; 4751 uint8_t npiv_config_0_1; 4752 uint8_t npiv_config_2_3; 4753 } aux; 4754 }; 4755 4756 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4757 #define FW_ABILITY_MAX_SPEED_16G 0x0 4758 #define FW_ABILITY_MAX_SPEED_32G 0x1 4759 #define FW_ABILITY_MAX_SPEED(ha) \ 4760 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4761 4762 #define QLA_GET_DATA_RATE 0 4763 #define QLA_SET_DATA_RATE_NOLR 1 4764 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4765 4766 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4767 /* 4768 * This item might be allocated with a size > sizeof(struct purex_item). 4769 * The "size" variable gives the size of the payload (which 4770 * is variable) starting at "iocb". 4771 */ 4772 struct purex_item { 4773 struct list_head list; 4774 struct scsi_qla_host *vha; 4775 void (*process_item)(struct scsi_qla_host *vha, 4776 struct purex_item *pkt); 4777 atomic_t in_use; 4778 uint16_t size; 4779 struct { 4780 uint8_t iocb[64]; 4781 } iocb; 4782 }; 4783 4784 #include "qla_edif.h" 4785 4786 #define SCM_FLAG_RDF_REJECT 0x00 4787 #define SCM_FLAG_RDF_COMPLETED 0x01 4788 4789 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4790 #define QLA_CONGESTION_ARB_WARNING 0x1 4791 #define QLA_CONGESTION_ARB_ALARM 0X2 4792 4793 /* 4794 * Qlogic scsi host structure 4795 */ 4796 typedef struct scsi_qla_host { 4797 struct list_head list; 4798 struct list_head vp_fcports; /* list of fcports */ 4799 struct list_head work_list; 4800 spinlock_t work_lock; 4801 struct work_struct iocb_work; 4802 4803 /* Commonly used flags and state information. */ 4804 struct Scsi_Host *host; 4805 unsigned long host_no; 4806 uint8_t host_str[16]; 4807 4808 volatile struct { 4809 uint32_t init_done :1; 4810 uint32_t online :1; 4811 uint32_t reset_active :1; 4812 4813 uint32_t management_server_logged_in :1; 4814 uint32_t process_response_queue :1; 4815 uint32_t difdix_supported:1; 4816 uint32_t delete_progress:1; 4817 4818 uint32_t fw_tgt_reported:1; 4819 uint32_t bbcr_enable:1; 4820 uint32_t qpairs_available:1; 4821 uint32_t qpairs_req_created:1; 4822 uint32_t qpairs_rsp_created:1; 4823 uint32_t nvme_enabled:1; 4824 uint32_t nvme_first_burst:1; 4825 uint32_t nvme2_enabled:1; 4826 } flags; 4827 4828 atomic_t loop_state; 4829 #define LOOP_TIMEOUT 1 4830 #define LOOP_DOWN 2 4831 #define LOOP_UP 3 4832 #define LOOP_UPDATE 4 4833 #define LOOP_READY 5 4834 #define LOOP_DEAD 6 4835 4836 unsigned long relogin_jif; 4837 unsigned long dpc_flags; 4838 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4839 #define RESET_ACTIVE 1 4840 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4841 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4842 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4843 #define LOOP_RESYNC_ACTIVE 5 4844 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4845 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4846 #define RELOGIN_NEEDED 8 4847 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4848 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4849 #define BEACON_BLINK_NEEDED 11 4850 #define REGISTER_FDMI_NEEDED 12 4851 #define FCPORT_UPDATE_NEEDED 13 4852 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4853 #define UNLOADING 15 4854 #define NPIV_CONFIG_NEEDED 16 4855 #define ISP_UNRECOVERABLE 17 4856 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4857 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4858 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4859 #define N2N_LINK_RESET 21 4860 #define PORT_UPDATE_NEEDED 22 4861 #define FX00_RESET_RECOVERY 23 4862 #define FX00_TARGET_SCAN 24 4863 #define FX00_CRITEMP_RECOVERY 25 4864 #define FX00_HOST_INFO_RESEND 26 4865 #define QPAIR_ONLINE_CHECK_NEEDED 27 4866 #define DO_EEH_RECOVERY 28 4867 #define DETECT_SFP_CHANGE 29 4868 #define N2N_LOGIN_NEEDED 30 4869 #define IOCB_WORK_ACTIVE 31 4870 #define SET_ZIO_THRESHOLD_NEEDED 32 4871 #define ISP_ABORT_TO_ROM 33 4872 #define VPORT_DELETE 34 4873 4874 #define PROCESS_PUREX_IOCB 63 4875 4876 unsigned long pci_flags; 4877 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4878 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4879 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4880 4881 uint32_t device_flags; 4882 #define SWITCH_FOUND BIT_0 4883 #define DFLG_NO_CABLE BIT_1 4884 #define DFLG_DEV_FAILED BIT_5 4885 4886 /* ISP configuration data. */ 4887 uint16_t loop_id; /* Host adapter loop id */ 4888 uint16_t self_login_loop_id; /* host adapter loop id 4889 * get it on self login 4890 */ 4891 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4892 * no need of allocating it for 4893 * each command 4894 */ 4895 4896 port_id_t d_id; /* Host adapter port id */ 4897 uint8_t marker_needed; 4898 uint16_t mgmt_svr_loop_id; 4899 4900 4901 4902 /* Timeout timers. */ 4903 uint8_t loop_down_abort_time; /* port down timer */ 4904 atomic_t loop_down_timer; /* loop down timer */ 4905 uint8_t link_down_timeout; /* link down timeout */ 4906 4907 uint32_t timer_active; 4908 struct timer_list timer; 4909 4910 uint8_t node_name[WWN_SIZE]; 4911 uint8_t port_name[WWN_SIZE]; 4912 uint8_t fabric_node_name[WWN_SIZE]; 4913 uint8_t fabric_port_name[WWN_SIZE]; 4914 4915 struct nvme_fc_local_port *nvme_local_port; 4916 struct completion nvme_del_done; 4917 4918 uint16_t fcoe_vlan_id; 4919 uint16_t fcoe_fcf_idx; 4920 uint8_t fcoe_vn_port_mac[6]; 4921 4922 /* list of commands waiting on workqueue */ 4923 struct list_head qla_cmd_list; 4924 struct list_head unknown_atio_list; 4925 spinlock_t cmd_list_lock; 4926 struct delayed_work unknown_atio_work; 4927 4928 /* Counter to detect races between ELS and RSCN events */ 4929 atomic_t generation_tick; 4930 /* Time when global fcport update has been scheduled */ 4931 int total_fcport_update_gen; 4932 /* List of pending LOGOs, protected by tgt_mutex */ 4933 struct list_head logo_list; 4934 /* List of pending PLOGI acks, protected by hw lock */ 4935 struct list_head plogi_ack_list; 4936 4937 struct list_head qp_list; 4938 4939 uint32_t vp_abort_cnt; 4940 4941 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4942 uint16_t vp_idx; /* vport ID */ 4943 struct qla_qpair *qpair; /* base qpair */ 4944 4945 unsigned long vp_flags; 4946 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4947 #define VP_CREATE_NEEDED 1 4948 #define VP_BIND_NEEDED 2 4949 #define VP_DELETE_NEEDED 3 4950 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4951 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4952 atomic_t vp_state; 4953 #define VP_OFFLINE 0 4954 #define VP_ACTIVE 1 4955 #define VP_FAILED 2 4956 // #define VP_DISABLE 3 4957 uint16_t vp_err_state; 4958 uint16_t vp_prev_err_state; 4959 #define VP_ERR_UNKWN 0 4960 #define VP_ERR_PORTDWN 1 4961 #define VP_ERR_FAB_UNSUPPORTED 2 4962 #define VP_ERR_FAB_NORESOURCES 3 4963 #define VP_ERR_FAB_LOGOUT 4 4964 #define VP_ERR_ADAP_NORESOURCES 5 4965 struct qla_hw_data *hw; 4966 struct scsi_qlt_host vha_tgt; 4967 struct req_que *req; 4968 int fw_heartbeat_counter; 4969 int seconds_since_last_heartbeat; 4970 struct fc_host_statistics fc_host_stat; 4971 struct qla_statistics qla_stats; 4972 struct bidi_statistics bidi_stats; 4973 atomic_t vref_count; 4974 struct qla8044_reset_template reset_tmplt; 4975 uint16_t bbcr; 4976 4977 uint16_t u_ql2xexchoffld; 4978 uint16_t u_ql2xiniexchg; 4979 uint16_t qlini_mode; 4980 uint16_t ql2xexchoffld; 4981 uint16_t ql2xiniexchg; 4982 4983 struct dentry *dfs_rport_root; 4984 4985 struct purex_list { 4986 struct list_head head; 4987 spinlock_t lock; 4988 } purex_list; 4989 struct purex_item default_item; 4990 4991 struct name_list_extended gnl; 4992 /* Count of active session/fcport */ 4993 int fcport_count; 4994 wait_queue_head_t fcport_waitQ; 4995 wait_queue_head_t vref_waitq; 4996 uint8_t min_supported_speed; 4997 uint8_t n2n_node_name[WWN_SIZE]; 4998 uint8_t n2n_port_name[WWN_SIZE]; 4999 uint16_t n2n_id; 5000 __le16 dport_data[4]; 5001 struct list_head gpnid_list; 5002 struct fab_scan scan; 5003 uint8_t scm_fabric_connection_flags; 5004 5005 unsigned int irq_offset; 5006 5007 u64 hw_err_cnt; 5008 u64 interface_err_cnt; 5009 u64 cmd_timeout_cnt; 5010 u64 reset_cmd_err_cnt; 5011 u64 link_down_time; 5012 u64 short_link_down_cnt; 5013 struct edif_dbell e_dbell; 5014 struct pur_core pur_cinfo; 5015 } scsi_qla_host_t; 5016 5017 struct qla27xx_image_status { 5018 uint8_t image_status_mask; 5019 __le16 generation; 5020 uint8_t ver_major; 5021 uint8_t ver_minor; 5022 uint8_t bitmap; /* 28xx only */ 5023 uint8_t reserved[2]; 5024 __le32 checksum; 5025 __le32 signature; 5026 } __packed; 5027 5028 /* 28xx aux image status bimap values */ 5029 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5030 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5031 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5032 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5033 5034 #define SET_VP_IDX 1 5035 #define SET_AL_PA 2 5036 #define RESET_VP_IDX 3 5037 #define RESET_AL_PA 4 5038 struct qla_tgt_vp_map { 5039 uint8_t idx; 5040 scsi_qla_host_t *vha; 5041 }; 5042 5043 struct qla2_sgx { 5044 dma_addr_t dma_addr; /* OUT */ 5045 uint32_t dma_len; /* OUT */ 5046 5047 uint32_t tot_bytes; /* IN */ 5048 struct scatterlist *cur_sg; /* IN */ 5049 5050 /* for book keeping, bzero on initial invocation */ 5051 uint32_t bytes_consumed; 5052 uint32_t num_bytes; 5053 uint32_t tot_partial; 5054 5055 /* for debugging */ 5056 uint32_t num_sg; 5057 srb_t *sp; 5058 }; 5059 5060 #define QLA_FW_STARTED(_ha) { \ 5061 int i; \ 5062 _ha->flags.fw_started = 1; \ 5063 _ha->base_qpair->fw_started = 1; \ 5064 for (i = 0; i < _ha->max_qpairs; i++) { \ 5065 if (_ha->queue_pair_map[i]) \ 5066 _ha->queue_pair_map[i]->fw_started = 1; \ 5067 } \ 5068 } 5069 5070 #define QLA_FW_STOPPED(_ha) { \ 5071 int i; \ 5072 _ha->flags.fw_started = 0; \ 5073 _ha->base_qpair->fw_started = 0; \ 5074 for (i = 0; i < _ha->max_qpairs; i++) { \ 5075 if (_ha->queue_pair_map[i]) \ 5076 _ha->queue_pair_map[i]->fw_started = 0; \ 5077 } \ 5078 } 5079 5080 5081 #define SFUB_CHECKSUM_SIZE 4 5082 5083 struct secure_flash_update_block { 5084 uint32_t block_info; 5085 uint32_t signature_lo; 5086 uint32_t signature_hi; 5087 uint32_t signature_upper[0x3e]; 5088 }; 5089 5090 struct secure_flash_update_block_pk { 5091 uint32_t block_info; 5092 uint32_t signature_lo; 5093 uint32_t signature_hi; 5094 uint32_t signature_upper[0x3e]; 5095 uint32_t public_key[0x41]; 5096 }; 5097 5098 /* 5099 * Macros to help code, maintain, etc. 5100 */ 5101 #define LOOP_TRANSITION(ha) \ 5102 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5103 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5104 atomic_read(&ha->loop_state) == LOOP_DOWN) 5105 5106 #define STATE_TRANSITION(ha) \ 5107 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5108 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5109 5110 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 5111 atomic_inc(&__vha->vref_count); \ 5112 mb(); \ 5113 if (__vha->flags.delete_progress) { \ 5114 atomic_dec(&__vha->vref_count); \ 5115 wake_up(&__vha->vref_waitq); \ 5116 __bail = 1; \ 5117 } else { \ 5118 __bail = 0; \ 5119 } \ 5120 } while (0) 5121 5122 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5123 atomic_dec(&__vha->vref_count); \ 5124 wake_up(&__vha->vref_waitq); \ 5125 } while (0) \ 5126 5127 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5128 atomic_inc(&__qpair->ref_count); \ 5129 mb(); \ 5130 if (__qpair->delete_in_progress) { \ 5131 atomic_dec(&__qpair->ref_count); \ 5132 __bail = 1; \ 5133 } else { \ 5134 __bail = 0; \ 5135 } \ 5136 } while (0) 5137 5138 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5139 atomic_dec(&__qpair->ref_count) 5140 5141 #define QLA_ENA_CONF(_ha) {\ 5142 int i;\ 5143 _ha->base_qpair->enable_explicit_conf = 1; \ 5144 for (i = 0; i < _ha->max_qpairs; i++) { \ 5145 if (_ha->queue_pair_map[i]) \ 5146 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5147 } \ 5148 } 5149 5150 #define QLA_DIS_CONF(_ha) {\ 5151 int i;\ 5152 _ha->base_qpair->enable_explicit_conf = 0; \ 5153 for (i = 0; i < _ha->max_qpairs; i++) { \ 5154 if (_ha->queue_pair_map[i]) \ 5155 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5156 } \ 5157 } 5158 5159 /* 5160 * qla2x00 local function return status codes 5161 */ 5162 #define MBS_MASK 0x3fff 5163 5164 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5165 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5166 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5167 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5168 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5169 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5170 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5171 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5172 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5173 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5174 5175 #define QLA_FUNCTION_TIMEOUT 0x100 5176 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5177 #define QLA_FUNCTION_FAILED 0x102 5178 #define QLA_MEMORY_ALLOC_FAILED 0x103 5179 #define QLA_LOCK_TIMEOUT 0x104 5180 #define QLA_ABORTED 0x105 5181 #define QLA_SUSPENDED 0x106 5182 #define QLA_BUSY 0x107 5183 #define QLA_ALREADY_REGISTERED 0x109 5184 #define QLA_OS_TIMER_EXPIRED 0x10a 5185 #define QLA_ERR_NO_QPAIR 0x10b 5186 #define QLA_ERR_NOT_FOUND 0x10c 5187 #define QLA_ERR_FROM_FW 0x10d 5188 5189 #define NVRAM_DELAY() udelay(10) 5190 5191 /* 5192 * Flash support definitions 5193 */ 5194 #define OPTROM_SIZE_2300 0x20000 5195 #define OPTROM_SIZE_2322 0x100000 5196 #define OPTROM_SIZE_24XX 0x100000 5197 #define OPTROM_SIZE_25XX 0x200000 5198 #define OPTROM_SIZE_81XX 0x400000 5199 #define OPTROM_SIZE_82XX 0x800000 5200 #define OPTROM_SIZE_83XX 0x1000000 5201 #define OPTROM_SIZE_28XX 0x2000000 5202 5203 #define OPTROM_BURST_SIZE 0x1000 5204 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5205 5206 #define QLA_DSDS_PER_IOCB 37 5207 5208 #define QLA_SG_ALL 1024 5209 5210 enum nexus_wait_type { 5211 WAIT_HOST = 0, 5212 WAIT_TARGET, 5213 WAIT_LUN, 5214 }; 5215 5216 #define INVALID_EDIF_SA_INDEX 0xffff 5217 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5218 5219 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5220 5221 /* edif hash element */ 5222 struct edif_list_entry { 5223 uint16_t handle; /* nport_handle */ 5224 uint32_t update_sa_index; 5225 uint32_t delete_sa_index; 5226 uint32_t count; /* counter for filtering sa_index */ 5227 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5228 uint32_t flags; /* used by sadb cleanup code */ 5229 fc_port_t *fcport; /* needed by rx delay timer function */ 5230 struct timer_list timer; /* rx delay timer */ 5231 struct list_head next; 5232 }; 5233 5234 #define EDIF_TX_INDX_BASE 512 5235 #define EDIF_RX_INDX_BASE 0 5236 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5237 5238 /* entry in the sa_index free pool */ 5239 5240 struct sa_index_pair { 5241 uint16_t sa_index; 5242 uint32_t spi; 5243 }; 5244 5245 /* edif sa_index data structure */ 5246 struct edif_sa_index_entry { 5247 struct sa_index_pair sa_pair[2]; 5248 fc_port_t *fcport; 5249 uint16_t handle; 5250 struct list_head next; 5251 }; 5252 5253 /* Refer to SNIA SFF 8247 */ 5254 struct sff_8247_a0 { 5255 u8 txid; /* transceiver id */ 5256 u8 ext_txid; 5257 u8 connector; 5258 /* compliance code */ 5259 u8 eth_infi_cc3; /* ethernet, inifiband */ 5260 u8 sonet_cc4[2]; 5261 u8 eth_cc6; 5262 /* link length */ 5263 #define FC_LL_VL BIT_7 /* very long */ 5264 #define FC_LL_S BIT_6 /* Short */ 5265 #define FC_LL_I BIT_5 /* Intermidiate*/ 5266 #define FC_LL_L BIT_4 /* Long */ 5267 #define FC_LL_M BIT_3 /* Medium */ 5268 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5269 #define FC_LL_LC BIT_1 /* LongWave laser */ 5270 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5271 u8 fc_ll_cc7; 5272 /* FC technology */ 5273 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5274 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5275 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5276 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5277 #define FC_TEC_ACT BIT_3 /* Active cable */ 5278 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5279 u8 fc_tec_cc8; 5280 /* Transmission Media */ 5281 #define FC_MED_TW BIT_7 /* Twin Ax */ 5282 #define FC_MED_TP BIT_6 /* Twited Pair */ 5283 #define FC_MED_MI BIT_5 /* Min Coax */ 5284 #define FC_MED_TV BIT_4 /* Video Coax */ 5285 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5286 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5287 #define FC_MED_SM BIT_0 /* Single Mode */ 5288 u8 fc_med_cc9; 5289 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5290 #define FC_SP_12 BIT_7 5291 #define FC_SP_8 BIT_6 5292 #define FC_SP_16 BIT_5 5293 #define FC_SP_4 BIT_4 5294 #define FC_SP_32 BIT_3 5295 #define FC_SP_2 BIT_2 5296 #define FC_SP_1 BIT_0 5297 u8 fc_sp_cc10; 5298 u8 encode; 5299 u8 bitrate; 5300 u8 rate_id; 5301 u8 length_km; /* offset 14/eh */ 5302 u8 length_100m; 5303 u8 length_50um_10m; 5304 u8 length_62um_10m; 5305 u8 length_om4_10m; 5306 u8 length_om3_10m; 5307 #define SFF_VEN_NAME_LEN 16 5308 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5309 u8 tx_compat; 5310 u8 vendor_oui[3]; 5311 #define SFF_PART_NAME_LEN 16 5312 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5313 u8 vendor_rev[4]; 5314 u8 wavelength[2]; 5315 u8 resv; 5316 u8 cc_base; 5317 u8 options[2]; /* offset 64 */ 5318 u8 br_max; 5319 u8 br_min; 5320 u8 vendor_sn[16]; 5321 u8 date_code[8]; 5322 u8 diag; 5323 u8 enh_options; 5324 u8 sff_revision; 5325 u8 cc_ext; 5326 u8 vendor_specific[32]; 5327 u8 resv2[128]; 5328 }; 5329 5330 /* BPM -- Buffer Plus Management support. */ 5331 #define IS_BPM_CAPABLE(ha) \ 5332 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5333 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5334 #define IS_BPM_RANGE_CAPABLE(ha) \ 5335 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5336 #define IS_BPM_ENABLED(vha) \ 5337 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5338 5339 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5340 5341 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5342 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5343 5344 #define SAVE_TOPO(_ha) { \ 5345 if (_ha->current_topology) \ 5346 _ha->prev_topology = _ha->current_topology; \ 5347 } 5348 5349 #define N2N_TOPO(ha) \ 5350 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5351 ha->current_topology == ISP_CFG_N || \ 5352 !ha->current_topology) 5353 5354 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5355 5356 #define NVME_TYPE(fcport) \ 5357 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5358 5359 #define FCP_TYPE(fcport) \ 5360 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5361 5362 #define NVME_ONLY_TARGET(fcport) \ 5363 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5364 5365 #define NVME_FCP_TARGET(fcport) \ 5366 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5367 5368 #define NVME_PRIORITY(ha, fcport) \ 5369 (NVME_FCP_TARGET(fcport) && \ 5370 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5371 5372 #define NVME_TARGET(ha, fcport) \ 5373 (fcport->do_prli_nvme || \ 5374 NVME_ONLY_TARGET(fcport)) \ 5375 5376 #define PRLI_PHASE(_cls) \ 5377 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5378 5379 enum ql_vnd_host_stat_action { 5380 QLA_STOP = 0, 5381 QLA_START, 5382 QLA_CLEAR, 5383 }; 5384 5385 struct ql_vnd_mng_host_stats_param { 5386 u32 stat_type; 5387 enum ql_vnd_host_stat_action action; 5388 } __packed; 5389 5390 struct ql_vnd_mng_host_stats_resp { 5391 u32 status; 5392 } __packed; 5393 5394 struct ql_vnd_stats_param { 5395 u32 stat_type; 5396 } __packed; 5397 5398 struct ql_vnd_tgt_stats_param { 5399 s32 tgt_id; 5400 u32 stat_type; 5401 } __packed; 5402 5403 enum ql_vnd_host_port_action { 5404 QLA_ENABLE = 0, 5405 QLA_DISABLE, 5406 }; 5407 5408 struct ql_vnd_mng_host_port_param { 5409 enum ql_vnd_host_port_action action; 5410 } __packed; 5411 5412 struct ql_vnd_mng_host_port_resp { 5413 u32 status; 5414 } __packed; 5415 5416 struct ql_vnd_stat_entry { 5417 u32 stat_type; /* Failure type */ 5418 u32 tgt_num; /* Target Num */ 5419 u64 cnt; /* Counter value */ 5420 } __packed; 5421 5422 struct ql_vnd_stats { 5423 u64 entry_count; /* Num of entries */ 5424 u64 rservd; 5425 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5426 } __packed; 5427 5428 struct ql_vnd_host_stats_resp { 5429 u32 status; 5430 struct ql_vnd_stats stats; 5431 } __packed; 5432 5433 struct ql_vnd_tgt_stats_resp { 5434 u32 status; 5435 struct ql_vnd_stats stats; 5436 } __packed; 5437 5438 #include "qla_target.h" 5439 #include "qla_gbl.h" 5440 #include "qla_dbg.h" 5441 #include "qla_inline.h" 5442 5443 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5444 _fcport->disc_state == DSC_DELETED) 5445 5446 #endif 5447