1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 /* 59 * Data bit definitions 60 */ 61 #define BIT_0 0x1 62 #define BIT_1 0x2 63 #define BIT_2 0x4 64 #define BIT_3 0x8 65 #define BIT_4 0x10 66 #define BIT_5 0x20 67 #define BIT_6 0x40 68 #define BIT_7 0x80 69 #define BIT_8 0x100 70 #define BIT_9 0x200 71 #define BIT_10 0x400 72 #define BIT_11 0x800 73 #define BIT_12 0x1000 74 #define BIT_13 0x2000 75 #define BIT_14 0x4000 76 #define BIT_15 0x8000 77 #define BIT_16 0x10000 78 #define BIT_17 0x20000 79 #define BIT_18 0x40000 80 #define BIT_19 0x80000 81 #define BIT_20 0x100000 82 #define BIT_21 0x200000 83 #define BIT_22 0x400000 84 #define BIT_23 0x800000 85 #define BIT_24 0x1000000 86 #define BIT_25 0x2000000 87 #define BIT_26 0x4000000 88 #define BIT_27 0x8000000 89 #define BIT_28 0x10000000 90 #define BIT_29 0x20000000 91 #define BIT_30 0x40000000 92 #define BIT_31 0x80000000 93 94 #define LSB(x) ((uint8_t)(x)) 95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 96 97 #define LSW(x) ((uint16_t)(x)) 98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 99 100 #define LSD(x) ((uint32_t)((uint64_t)(x))) 101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 102 103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 104 105 /* 106 * I/O register 107 */ 108 109 #define RD_REG_BYTE(addr) readb(addr) 110 #define RD_REG_WORD(addr) readw(addr) 111 #define RD_REG_DWORD(addr) readl(addr) 112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 115 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 116 #define WRT_REG_WORD(addr, data) writew(data,addr) 117 #define WRT_REG_DWORD(addr, data) writel(data,addr) 118 119 /* 120 * ISP83XX specific remote register addresses 121 */ 122 #define QLA83XX_LED_PORT0 0x00201320 123 #define QLA83XX_LED_PORT1 0x00201328 124 #define QLA83XX_IDC_DEV_STATE 0x22102384 125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 129 #define QLA83XX_IDC_CONTROL 0x22102390 130 #define QLA83XX_IDC_AUDIT 0x22102394 131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 132 #define QLA83XX_DRIVER_LOCKID 0x22102104 133 #define QLA83XX_DRIVER_LOCK 0x8111c028 134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 135 #define QLA83XX_FLASH_LOCKID 0x22102100 136 #define QLA83XX_FLASH_LOCK 0x8111c010 137 #define QLA83XX_FLASH_UNLOCK 0x8111c014 138 #define QLA83XX_DEV_PARTINFO1 0x221023e0 139 #define QLA83XX_DEV_PARTINFO2 0x221023e4 140 #define QLA83XX_FW_HEARTBEAT 0x221020b0 141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 143 144 /* 83XX: Macros defining 8200 AEN Reason codes */ 145 #define IDC_DEVICE_STATE_CHANGE BIT_0 146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 148 #define IDC_HEARTBEAT_FAILURE BIT_3 149 150 /* 83XX: Macros defining 8200 AEN Error-levels */ 151 #define ERR_LEVEL_NON_FATAL 0x1 152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 154 155 /* 83XX: Macros for IDC Version */ 156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 158 159 /* 83XX: Macros for scheduling dpc tasks */ 160 #define QLA83XX_NIC_CORE_RESET 0x1 161 #define QLA83XX_IDC_STATE_HANDLER 0x2 162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 163 164 /* 83XX: Macros for defining IDC-Control bits */ 165 #define QLA83XX_IDC_RESET_DISABLED BIT_0 166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 167 168 /* 83XX: Macros for different timeouts */ 169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 172 173 /* 83XX: Macros for defining class in DEV-Partition Info register */ 174 #define QLA83XX_CLASS_TYPE_NONE 0x0 175 #define QLA83XX_CLASS_TYPE_NIC 0x1 176 #define QLA83XX_CLASS_TYPE_FCOE 0x2 177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 178 179 /* 83XX: Macros for IDC Lock-Recovery stages */ 180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 181 * lock-recovery 182 */ 183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 184 185 /* 83XX: Macros for IDC Audit type */ 186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 187 * dev-state change to NEED-RESET 188 * or NEED-QUIESCENT 189 */ 190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 191 * reset-recovery completion is 192 * second 193 */ 194 /* ISP2031: Values for laser on/off */ 195 #define PORT_0_2031 0x00201340 196 #define PORT_1_2031 0x00201350 197 #define LASER_ON_2031 0x01800100 198 #define LASER_OFF_2031 0x01800180 199 200 /* 201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 202 * 133Mhz slot. 203 */ 204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 206 207 /* 208 * Fibre Channel device definitions. 209 */ 210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 211 #define MAX_FIBRE_DEVICES_2100 512 212 #define MAX_FIBRE_DEVICES_2400 2048 213 #define MAX_FIBRE_DEVICES_LOOP 128 214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 216 #define MAX_FIBRE_LUNS 0xFFFF 217 #define MAX_HOST_COUNT 16 218 219 /* 220 * Host adapter default definitions. 221 */ 222 #define MAX_BUSES 1 /* We only have one bus today */ 223 #define MIN_LUNS 8 224 #define MAX_LUNS MAX_FIBRE_LUNS 225 #define MAX_CMDS_PER_LUN 255 226 227 /* 228 * Fibre Channel device definitions. 229 */ 230 #define SNS_LAST_LOOP_ID_2100 0xfe 231 #define SNS_LAST_LOOP_ID_2300 0x7ff 232 233 #define LAST_LOCAL_LOOP_ID 0x7d 234 #define SNS_FL_PORT 0x7e 235 #define FABRIC_CONTROLLER 0x7f 236 #define SIMPLE_NAME_SERVER 0x80 237 #define SNS_FIRST_LOOP_ID 0x81 238 #define MANAGEMENT_SERVER 0xfe 239 #define BROADCAST 0xff 240 241 /* 242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 243 * valid range of an N-PORT id is 0 through 0x7ef. 244 */ 245 #define NPH_LAST_HANDLE 0x7ef 246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 247 #define NPH_SNS 0x7fc /* FFFFFC */ 248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 249 #define NPH_F_PORT 0x7fe /* FFFFFE */ 250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 251 252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 253 #include "qla_fw.h" 254 /* 255 * Timeout timer counts in seconds 256 */ 257 #define PORT_RETRY_TIME 1 258 #define LOOP_DOWN_TIMEOUT 60 259 #define LOOP_DOWN_TIME 255 /* 240 */ 260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 261 262 #define DEFAULT_OUTSTANDING_COMMANDS 4096 263 #define MIN_OUTSTANDING_COMMANDS 128 264 265 /* ISP request and response entry counts (37-65535) */ 266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 270 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 271 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 272 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 273 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 274 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 275 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 276 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */ 277 278 struct req_que; 279 struct qla_tgt_sess; 280 281 /* 282 * (sd.h is not exported, hence local inclusion) 283 * Data Integrity Field tuple. 284 */ 285 struct sd_dif_tuple { 286 __be16 guard_tag; /* Checksum */ 287 __be16 app_tag; /* Opaque storage */ 288 __be32 ref_tag; /* Target LBA or indirect LBA */ 289 }; 290 291 /* 292 * SCSI Request Block 293 */ 294 struct srb_cmd { 295 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 296 uint32_t request_sense_length; 297 uint32_t fw_sense_length; 298 uint8_t *request_sense_ptr; 299 void *ctx; 300 }; 301 302 /* 303 * SRB flag definitions 304 */ 305 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 306 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 307 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 308 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 309 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 310 311 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 312 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 313 314 struct els_logo_payload { 315 uint8_t opcode; 316 uint8_t rsvd[3]; 317 uint8_t s_id[3]; 318 uint8_t rsvd1[1]; 319 uint8_t wwpn[WWN_SIZE]; 320 }; 321 322 /* 323 * SRB extensions. 324 */ 325 struct srb_iocb { 326 union { 327 struct { 328 uint16_t flags; 329 #define SRB_LOGIN_RETRIED BIT_0 330 #define SRB_LOGIN_COND_PLOGI BIT_1 331 #define SRB_LOGIN_SKIP_PRLI BIT_2 332 uint16_t data[2]; 333 } logio; 334 struct { 335 #define ELS_DCMD_TIMEOUT 20 336 #define ELS_DCMD_LOGO 0x5 337 uint32_t flags; 338 uint32_t els_cmd; 339 struct completion comp; 340 struct els_logo_payload *els_logo_pyld; 341 dma_addr_t els_logo_pyld_dma; 342 } els_logo; 343 struct { 344 /* 345 * Values for flags field below are as 346 * defined in tsk_mgmt_entry struct 347 * for control_flags field in qla_fw.h. 348 */ 349 uint64_t lun; 350 uint32_t flags; 351 uint32_t data; 352 struct completion comp; 353 __le16 comp_status; 354 } tmf; 355 struct { 356 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 357 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 358 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 359 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 360 #define FXDISC_TIMEOUT 20 361 uint8_t flags; 362 uint32_t req_len; 363 uint32_t rsp_len; 364 void *req_addr; 365 void *rsp_addr; 366 dma_addr_t req_dma_handle; 367 dma_addr_t rsp_dma_handle; 368 __le32 adapter_id; 369 __le32 adapter_id_hi; 370 __le16 req_func_type; 371 __le32 req_data; 372 __le32 req_data_extra; 373 __le32 result; 374 __le32 seq_number; 375 __le16 fw_flags; 376 struct completion fxiocb_comp; 377 __le32 reserved_0; 378 uint8_t reserved_1; 379 } fxiocb; 380 struct { 381 uint32_t cmd_hndl; 382 __le16 comp_status; 383 struct completion comp; 384 } abt; 385 } u; 386 387 struct timer_list timer; 388 void (*timeout)(void *); 389 }; 390 391 /* Values for srb_ctx type */ 392 #define SRB_LOGIN_CMD 1 393 #define SRB_LOGOUT_CMD 2 394 #define SRB_ELS_CMD_RPT 3 395 #define SRB_ELS_CMD_HST 4 396 #define SRB_CT_CMD 5 397 #define SRB_ADISC_CMD 6 398 #define SRB_TM_CMD 7 399 #define SRB_SCSI_CMD 8 400 #define SRB_BIDI_CMD 9 401 #define SRB_FXIOCB_DCMD 10 402 #define SRB_FXIOCB_BCMD 11 403 #define SRB_ABT_CMD 12 404 #define SRB_ELS_DCMD 13 405 406 typedef struct srb { 407 atomic_t ref_count; 408 struct fc_port *fcport; 409 uint32_t handle; 410 uint16_t flags; 411 uint16_t type; 412 char *name; 413 int iocbs; 414 union { 415 struct srb_iocb iocb_cmd; 416 struct fc_bsg_job *bsg_job; 417 struct srb_cmd scmd; 418 } u; 419 void (*done)(void *, void *, int); 420 void (*free)(void *, void *); 421 } srb_t; 422 423 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 424 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 425 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 426 427 #define GET_CMD_SENSE_LEN(sp) \ 428 (sp->u.scmd.request_sense_length) 429 #define SET_CMD_SENSE_LEN(sp, len) \ 430 (sp->u.scmd.request_sense_length = len) 431 #define GET_CMD_SENSE_PTR(sp) \ 432 (sp->u.scmd.request_sense_ptr) 433 #define SET_CMD_SENSE_PTR(sp, ptr) \ 434 (sp->u.scmd.request_sense_ptr = ptr) 435 #define GET_FW_SENSE_LEN(sp) \ 436 (sp->u.scmd.fw_sense_length) 437 #define SET_FW_SENSE_LEN(sp, len) \ 438 (sp->u.scmd.fw_sense_length = len) 439 440 struct msg_echo_lb { 441 dma_addr_t send_dma; 442 dma_addr_t rcv_dma; 443 uint16_t req_sg_cnt; 444 uint16_t rsp_sg_cnt; 445 uint16_t options; 446 uint32_t transfer_size; 447 uint32_t iteration_count; 448 }; 449 450 /* 451 * ISP I/O Register Set structure definitions. 452 */ 453 struct device_reg_2xxx { 454 uint16_t flash_address; /* Flash BIOS address */ 455 uint16_t flash_data; /* Flash BIOS data */ 456 uint16_t unused_1[1]; /* Gap */ 457 uint16_t ctrl_status; /* Control/Status */ 458 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 459 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 460 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 461 462 uint16_t ictrl; /* Interrupt control */ 463 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 464 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 465 466 uint16_t istatus; /* Interrupt status */ 467 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 468 469 uint16_t semaphore; /* Semaphore */ 470 uint16_t nvram; /* NVRAM register. */ 471 #define NVR_DESELECT 0 472 #define NVR_BUSY BIT_15 473 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 474 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 475 #define NVR_DATA_IN BIT_3 476 #define NVR_DATA_OUT BIT_2 477 #define NVR_SELECT BIT_1 478 #define NVR_CLOCK BIT_0 479 480 #define NVR_WAIT_CNT 20000 481 482 union { 483 struct { 484 uint16_t mailbox0; 485 uint16_t mailbox1; 486 uint16_t mailbox2; 487 uint16_t mailbox3; 488 uint16_t mailbox4; 489 uint16_t mailbox5; 490 uint16_t mailbox6; 491 uint16_t mailbox7; 492 uint16_t unused_2[59]; /* Gap */ 493 } __attribute__((packed)) isp2100; 494 struct { 495 /* Request Queue */ 496 uint16_t req_q_in; /* In-Pointer */ 497 uint16_t req_q_out; /* Out-Pointer */ 498 /* Response Queue */ 499 uint16_t rsp_q_in; /* In-Pointer */ 500 uint16_t rsp_q_out; /* Out-Pointer */ 501 502 /* RISC to Host Status */ 503 uint32_t host_status; 504 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 505 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 506 507 /* Host to Host Semaphore */ 508 uint16_t host_semaphore; 509 uint16_t unused_3[17]; /* Gap */ 510 uint16_t mailbox0; 511 uint16_t mailbox1; 512 uint16_t mailbox2; 513 uint16_t mailbox3; 514 uint16_t mailbox4; 515 uint16_t mailbox5; 516 uint16_t mailbox6; 517 uint16_t mailbox7; 518 uint16_t mailbox8; 519 uint16_t mailbox9; 520 uint16_t mailbox10; 521 uint16_t mailbox11; 522 uint16_t mailbox12; 523 uint16_t mailbox13; 524 uint16_t mailbox14; 525 uint16_t mailbox15; 526 uint16_t mailbox16; 527 uint16_t mailbox17; 528 uint16_t mailbox18; 529 uint16_t mailbox19; 530 uint16_t mailbox20; 531 uint16_t mailbox21; 532 uint16_t mailbox22; 533 uint16_t mailbox23; 534 uint16_t mailbox24; 535 uint16_t mailbox25; 536 uint16_t mailbox26; 537 uint16_t mailbox27; 538 uint16_t mailbox28; 539 uint16_t mailbox29; 540 uint16_t mailbox30; 541 uint16_t mailbox31; 542 uint16_t fb_cmd; 543 uint16_t unused_4[10]; /* Gap */ 544 } __attribute__((packed)) isp2300; 545 } u; 546 547 uint16_t fpm_diag_config; 548 uint16_t unused_5[0x4]; /* Gap */ 549 uint16_t risc_hw; 550 uint16_t unused_5_1; /* Gap */ 551 uint16_t pcr; /* Processor Control Register. */ 552 uint16_t unused_6[0x5]; /* Gap */ 553 uint16_t mctr; /* Memory Configuration and Timing. */ 554 uint16_t unused_7[0x3]; /* Gap */ 555 uint16_t fb_cmd_2100; /* Unused on 23XX */ 556 uint16_t unused_8[0x3]; /* Gap */ 557 uint16_t hccr; /* Host command & control register. */ 558 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 559 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 560 /* HCCR commands */ 561 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 562 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 563 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 564 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 565 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 566 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 567 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 568 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 569 570 uint16_t unused_9[5]; /* Gap */ 571 uint16_t gpiod; /* GPIO Data register. */ 572 uint16_t gpioe; /* GPIO Enable register. */ 573 #define GPIO_LED_MASK 0x00C0 574 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 575 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 576 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 577 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 578 #define GPIO_LED_ALL_OFF 0x0000 579 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 580 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 581 582 union { 583 struct { 584 uint16_t unused_10[8]; /* Gap */ 585 uint16_t mailbox8; 586 uint16_t mailbox9; 587 uint16_t mailbox10; 588 uint16_t mailbox11; 589 uint16_t mailbox12; 590 uint16_t mailbox13; 591 uint16_t mailbox14; 592 uint16_t mailbox15; 593 uint16_t mailbox16; 594 uint16_t mailbox17; 595 uint16_t mailbox18; 596 uint16_t mailbox19; 597 uint16_t mailbox20; 598 uint16_t mailbox21; 599 uint16_t mailbox22; 600 uint16_t mailbox23; /* Also probe reg. */ 601 } __attribute__((packed)) isp2200; 602 } u_end; 603 }; 604 605 struct device_reg_25xxmq { 606 uint32_t req_q_in; 607 uint32_t req_q_out; 608 uint32_t rsp_q_in; 609 uint32_t rsp_q_out; 610 uint32_t atio_q_in; 611 uint32_t atio_q_out; 612 }; 613 614 615 struct device_reg_fx00 { 616 uint32_t mailbox0; /* 00 */ 617 uint32_t mailbox1; /* 04 */ 618 uint32_t mailbox2; /* 08 */ 619 uint32_t mailbox3; /* 0C */ 620 uint32_t mailbox4; /* 10 */ 621 uint32_t mailbox5; /* 14 */ 622 uint32_t mailbox6; /* 18 */ 623 uint32_t mailbox7; /* 1C */ 624 uint32_t mailbox8; /* 20 */ 625 uint32_t mailbox9; /* 24 */ 626 uint32_t mailbox10; /* 28 */ 627 uint32_t mailbox11; 628 uint32_t mailbox12; 629 uint32_t mailbox13; 630 uint32_t mailbox14; 631 uint32_t mailbox15; 632 uint32_t mailbox16; 633 uint32_t mailbox17; 634 uint32_t mailbox18; 635 uint32_t mailbox19; 636 uint32_t mailbox20; 637 uint32_t mailbox21; 638 uint32_t mailbox22; 639 uint32_t mailbox23; 640 uint32_t mailbox24; 641 uint32_t mailbox25; 642 uint32_t mailbox26; 643 uint32_t mailbox27; 644 uint32_t mailbox28; 645 uint32_t mailbox29; 646 uint32_t mailbox30; 647 uint32_t mailbox31; 648 uint32_t aenmailbox0; 649 uint32_t aenmailbox1; 650 uint32_t aenmailbox2; 651 uint32_t aenmailbox3; 652 uint32_t aenmailbox4; 653 uint32_t aenmailbox5; 654 uint32_t aenmailbox6; 655 uint32_t aenmailbox7; 656 /* Request Queue. */ 657 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 658 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 659 /* Response Queue. */ 660 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 661 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 662 /* Init values shadowed on FW Up Event */ 663 uint32_t initval0; /* B0 */ 664 uint32_t initval1; /* B4 */ 665 uint32_t initval2; /* B8 */ 666 uint32_t initval3; /* BC */ 667 uint32_t initval4; /* C0 */ 668 uint32_t initval5; /* C4 */ 669 uint32_t initval6; /* C8 */ 670 uint32_t initval7; /* CC */ 671 uint32_t fwheartbeat; /* D0 */ 672 uint32_t pseudoaen; /* D4 */ 673 }; 674 675 676 677 typedef union { 678 struct device_reg_2xxx isp; 679 struct device_reg_24xx isp24; 680 struct device_reg_25xxmq isp25mq; 681 struct device_reg_82xx isp82; 682 struct device_reg_fx00 ispfx00; 683 } __iomem device_reg_t; 684 685 #define ISP_REQ_Q_IN(ha, reg) \ 686 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 687 &(reg)->u.isp2100.mailbox4 : \ 688 &(reg)->u.isp2300.req_q_in) 689 #define ISP_REQ_Q_OUT(ha, reg) \ 690 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 691 &(reg)->u.isp2100.mailbox4 : \ 692 &(reg)->u.isp2300.req_q_out) 693 #define ISP_RSP_Q_IN(ha, reg) \ 694 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 695 &(reg)->u.isp2100.mailbox5 : \ 696 &(reg)->u.isp2300.rsp_q_in) 697 #define ISP_RSP_Q_OUT(ha, reg) \ 698 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 699 &(reg)->u.isp2100.mailbox5 : \ 700 &(reg)->u.isp2300.rsp_q_out) 701 702 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 703 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 704 705 #define MAILBOX_REG(ha, reg, num) \ 706 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 707 (num < 8 ? \ 708 &(reg)->u.isp2100.mailbox0 + (num) : \ 709 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 710 &(reg)->u.isp2300.mailbox0 + (num)) 711 #define RD_MAILBOX_REG(ha, reg, num) \ 712 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 713 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 714 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 715 716 #define FB_CMD_REG(ha, reg) \ 717 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 718 &(reg)->fb_cmd_2100 : \ 719 &(reg)->u.isp2300.fb_cmd) 720 #define RD_FB_CMD_REG(ha, reg) \ 721 RD_REG_WORD(FB_CMD_REG(ha, reg)) 722 #define WRT_FB_CMD_REG(ha, reg, data) \ 723 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 724 725 typedef struct { 726 uint32_t out_mb; /* outbound from driver */ 727 uint32_t in_mb; /* Incoming from RISC */ 728 uint16_t mb[MAILBOX_REGISTER_COUNT]; 729 long buf_size; 730 void *bufp; 731 uint32_t tov; 732 uint8_t flags; 733 #define MBX_DMA_IN BIT_0 734 #define MBX_DMA_OUT BIT_1 735 #define IOCTL_CMD BIT_2 736 } mbx_cmd_t; 737 738 struct mbx_cmd_32 { 739 uint32_t out_mb; /* outbound from driver */ 740 uint32_t in_mb; /* Incoming from RISC */ 741 uint32_t mb[MAILBOX_REGISTER_COUNT]; 742 long buf_size; 743 void *bufp; 744 uint32_t tov; 745 uint8_t flags; 746 #define MBX_DMA_IN BIT_0 747 #define MBX_DMA_OUT BIT_1 748 #define IOCTL_CMD BIT_2 749 }; 750 751 752 #define MBX_TOV_SECONDS 30 753 754 /* 755 * ISP product identification definitions in mailboxes after reset. 756 */ 757 #define PROD_ID_1 0x4953 758 #define PROD_ID_2 0x0000 759 #define PROD_ID_2a 0x5020 760 #define PROD_ID_3 0x2020 761 762 /* 763 * ISP mailbox Self-Test status codes 764 */ 765 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 766 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 767 #define MBS_BUSY 4 /* Busy. */ 768 769 /* 770 * ISP mailbox command complete status codes 771 */ 772 #define MBS_COMMAND_COMPLETE 0x4000 773 #define MBS_INVALID_COMMAND 0x4001 774 #define MBS_HOST_INTERFACE_ERROR 0x4002 775 #define MBS_TEST_FAILED 0x4003 776 #define MBS_COMMAND_ERROR 0x4005 777 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 778 #define MBS_PORT_ID_USED 0x4007 779 #define MBS_LOOP_ID_USED 0x4008 780 #define MBS_ALL_IDS_IN_USE 0x4009 781 #define MBS_NOT_LOGGED_IN 0x400A 782 #define MBS_LINK_DOWN_ERROR 0x400B 783 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 784 785 /* 786 * ISP mailbox asynchronous event status codes 787 */ 788 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 789 #define MBA_RESET 0x8001 /* Reset Detected. */ 790 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 791 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 792 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 793 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 794 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 795 /* occurred. */ 796 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 797 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 798 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 799 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 800 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 801 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 802 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 803 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 804 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 805 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 806 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 807 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 808 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 809 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 810 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 811 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 812 /* used. */ 813 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 814 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 815 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 816 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 817 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 818 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 819 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 820 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 821 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 822 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 823 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 824 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 825 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 826 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 827 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 828 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 829 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 830 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 831 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 832 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 833 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 834 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 835 Notification */ 836 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 837 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 838 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 839 /* 83XX FCoE specific */ 840 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 841 842 /* Interrupt type codes */ 843 #define INTR_ROM_MB_SUCCESS 0x1 844 #define INTR_ROM_MB_FAILED 0x2 845 #define INTR_MB_SUCCESS 0x10 846 #define INTR_MB_FAILED 0x11 847 #define INTR_ASYNC_EVENT 0x12 848 #define INTR_RSP_QUE_UPDATE 0x13 849 #define INTR_RSP_QUE_UPDATE_83XX 0x14 850 #define INTR_ATIO_QUE_UPDATE 0x1C 851 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 852 853 /* ISP mailbox loopback echo diagnostic error code */ 854 #define MBS_LB_RESET 0x17 855 /* 856 * Firmware options 1, 2, 3. 857 */ 858 #define FO1_AE_ON_LIPF8 BIT_0 859 #define FO1_AE_ALL_LIP_RESET BIT_1 860 #define FO1_CTIO_RETRY BIT_3 861 #define FO1_DISABLE_LIP_F7_SW BIT_4 862 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 863 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 864 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 865 #define FO1_SET_EMPHASIS_SWING BIT_8 866 #define FO1_AE_AUTO_BYPASS BIT_9 867 #define FO1_ENABLE_PURE_IOCB BIT_10 868 #define FO1_AE_PLOGI_RJT BIT_11 869 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 870 #define FO1_AE_QUEUE_FULL BIT_13 871 872 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 873 #define FO2_REV_LOOPBACK BIT_1 874 875 #define FO3_ENABLE_EMERG_IOCB BIT_0 876 #define FO3_AE_RND_ERROR BIT_1 877 878 /* 24XX additional firmware options */ 879 #define ADD_FO_COUNT 3 880 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 881 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 882 883 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 884 885 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 886 887 /* 888 * ISP mailbox commands 889 */ 890 #define MBC_LOAD_RAM 1 /* Load RAM. */ 891 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 892 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 893 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 894 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 895 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 896 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 897 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 898 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 899 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 900 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 901 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 902 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 903 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 904 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 905 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 906 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 907 #define MBC_RESET 0x18 /* Reset. */ 908 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 909 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 910 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 911 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 912 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 913 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 914 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 915 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 916 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 917 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 918 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 919 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 920 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 921 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 922 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 923 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 924 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 925 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 926 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 927 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 928 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 929 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 930 #define MBC_DATA_RATE 0x5d /* Data Rate */ 931 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 932 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 933 /* Initialization Procedure */ 934 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 935 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 936 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 937 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 938 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 939 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 940 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 941 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 942 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 943 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 944 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 945 /* commandd. */ 946 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 947 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 948 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 949 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 950 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 951 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 952 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 953 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 954 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 955 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 956 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 957 958 /* 959 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 960 * should be defined with MBC_MR_* 961 */ 962 #define MBC_MR_DRV_SHUTDOWN 0x6A 963 964 /* 965 * ISP24xx mailbox commands 966 */ 967 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 968 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 969 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 970 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 971 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 972 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 973 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 974 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 975 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 976 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 977 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 978 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 979 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 980 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 981 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 982 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 983 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 984 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 985 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 986 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 987 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 988 #define MBC_PORT_RESET 0x120 /* Port Reset */ 989 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 990 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 991 992 /* 993 * ISP81xx mailbox commands 994 */ 995 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 996 997 /* 998 * ISP8044 mailbox commands 999 */ 1000 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1001 #define HCS_WRITE_SERDES 0x3 1002 #define HCS_READ_SERDES 0x4 1003 1004 /* Firmware return data sizes */ 1005 #define FCAL_MAP_SIZE 128 1006 1007 /* Mailbox bit definitions for out_mb and in_mb */ 1008 #define MBX_31 BIT_31 1009 #define MBX_30 BIT_30 1010 #define MBX_29 BIT_29 1011 #define MBX_28 BIT_28 1012 #define MBX_27 BIT_27 1013 #define MBX_26 BIT_26 1014 #define MBX_25 BIT_25 1015 #define MBX_24 BIT_24 1016 #define MBX_23 BIT_23 1017 #define MBX_22 BIT_22 1018 #define MBX_21 BIT_21 1019 #define MBX_20 BIT_20 1020 #define MBX_19 BIT_19 1021 #define MBX_18 BIT_18 1022 #define MBX_17 BIT_17 1023 #define MBX_16 BIT_16 1024 #define MBX_15 BIT_15 1025 #define MBX_14 BIT_14 1026 #define MBX_13 BIT_13 1027 #define MBX_12 BIT_12 1028 #define MBX_11 BIT_11 1029 #define MBX_10 BIT_10 1030 #define MBX_9 BIT_9 1031 #define MBX_8 BIT_8 1032 #define MBX_7 BIT_7 1033 #define MBX_6 BIT_6 1034 #define MBX_5 BIT_5 1035 #define MBX_4 BIT_4 1036 #define MBX_3 BIT_3 1037 #define MBX_2 BIT_2 1038 #define MBX_1 BIT_1 1039 #define MBX_0 BIT_0 1040 1041 #define RNID_TYPE_SET_VERSION 0x9 1042 #define RNID_TYPE_ASIC_TEMP 0xC 1043 1044 /* 1045 * Firmware state codes from get firmware state mailbox command 1046 */ 1047 #define FSTATE_CONFIG_WAIT 0 1048 #define FSTATE_WAIT_AL_PA 1 1049 #define FSTATE_WAIT_LOGIN 2 1050 #define FSTATE_READY 3 1051 #define FSTATE_LOSS_OF_SYNC 4 1052 #define FSTATE_ERROR 5 1053 #define FSTATE_REINIT 6 1054 #define FSTATE_NON_PART 7 1055 1056 #define FSTATE_CONFIG_CORRECT 0 1057 #define FSTATE_P2P_RCV_LIP 1 1058 #define FSTATE_P2P_CHOOSE_LOOP 2 1059 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1060 #define FSTATE_FATAL_ERROR 4 1061 #define FSTATE_LOOP_BACK_CONN 5 1062 1063 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1064 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1065 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1066 #define QLA27XX_PRIMARY_IMAGE 1 1067 #define QLA27XX_SECONDARY_IMAGE 2 1068 1069 /* 1070 * Port Database structure definition 1071 * Little endian except where noted. 1072 */ 1073 #define PORT_DATABASE_SIZE 128 /* bytes */ 1074 typedef struct { 1075 uint8_t options; 1076 uint8_t control; 1077 uint8_t master_state; 1078 uint8_t slave_state; 1079 uint8_t reserved[2]; 1080 uint8_t hard_address; 1081 uint8_t reserved_1; 1082 uint8_t port_id[4]; 1083 uint8_t node_name[WWN_SIZE]; 1084 uint8_t port_name[WWN_SIZE]; 1085 uint16_t execution_throttle; 1086 uint16_t execution_count; 1087 uint8_t reset_count; 1088 uint8_t reserved_2; 1089 uint16_t resource_allocation; 1090 uint16_t current_allocation; 1091 uint16_t queue_head; 1092 uint16_t queue_tail; 1093 uint16_t transmit_execution_list_next; 1094 uint16_t transmit_execution_list_previous; 1095 uint16_t common_features; 1096 uint16_t total_concurrent_sequences; 1097 uint16_t RO_by_information_category; 1098 uint8_t recipient; 1099 uint8_t initiator; 1100 uint16_t receive_data_size; 1101 uint16_t concurrent_sequences; 1102 uint16_t open_sequences_per_exchange; 1103 uint16_t lun_abort_flags; 1104 uint16_t lun_stop_flags; 1105 uint16_t stop_queue_head; 1106 uint16_t stop_queue_tail; 1107 uint16_t port_retry_timer; 1108 uint16_t next_sequence_id; 1109 uint16_t frame_count; 1110 uint16_t PRLI_payload_length; 1111 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1112 /* Bits 15-0 of word 0 */ 1113 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1114 /* Bits 15-0 of word 3 */ 1115 uint16_t loop_id; 1116 uint16_t extended_lun_info_list_pointer; 1117 uint16_t extended_lun_stop_list_pointer; 1118 } port_database_t; 1119 1120 /* 1121 * Port database slave/master states 1122 */ 1123 #define PD_STATE_DISCOVERY 0 1124 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1125 #define PD_STATE_PORT_LOGIN 2 1126 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1127 #define PD_STATE_PROCESS_LOGIN 4 1128 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1129 #define PD_STATE_PORT_LOGGED_IN 6 1130 #define PD_STATE_PORT_UNAVAILABLE 7 1131 #define PD_STATE_PROCESS_LOGOUT 8 1132 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1133 #define PD_STATE_PORT_LOGOUT 10 1134 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1135 1136 1137 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1138 #define QLA_ZIO_DISABLED 0 1139 #define QLA_ZIO_DEFAULT_TIMER 2 1140 1141 /* 1142 * ISP Initialization Control Block. 1143 * Little endian except where noted. 1144 */ 1145 #define ICB_VERSION 1 1146 typedef struct { 1147 uint8_t version; 1148 uint8_t reserved_1; 1149 1150 /* 1151 * LSB BIT 0 = Enable Hard Loop Id 1152 * LSB BIT 1 = Enable Fairness 1153 * LSB BIT 2 = Enable Full-Duplex 1154 * LSB BIT 3 = Enable Fast Posting 1155 * LSB BIT 4 = Enable Target Mode 1156 * LSB BIT 5 = Disable Initiator Mode 1157 * LSB BIT 6 = Enable ADISC 1158 * LSB BIT 7 = Enable Target Inquiry Data 1159 * 1160 * MSB BIT 0 = Enable PDBC Notify 1161 * MSB BIT 1 = Non Participating LIP 1162 * MSB BIT 2 = Descending Loop ID Search 1163 * MSB BIT 3 = Acquire Loop ID in LIPA 1164 * MSB BIT 4 = Stop PortQ on Full Status 1165 * MSB BIT 5 = Full Login after LIP 1166 * MSB BIT 6 = Node Name Option 1167 * MSB BIT 7 = Ext IFWCB enable bit 1168 */ 1169 uint8_t firmware_options[2]; 1170 1171 uint16_t frame_payload_size; 1172 uint16_t max_iocb_allocation; 1173 uint16_t execution_throttle; 1174 uint8_t retry_count; 1175 uint8_t retry_delay; /* unused */ 1176 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1177 uint16_t hard_address; 1178 uint8_t inquiry_data; 1179 uint8_t login_timeout; 1180 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1181 1182 uint16_t request_q_outpointer; 1183 uint16_t response_q_inpointer; 1184 uint16_t request_q_length; 1185 uint16_t response_q_length; 1186 uint32_t request_q_address[2]; 1187 uint32_t response_q_address[2]; 1188 1189 uint16_t lun_enables; 1190 uint8_t command_resource_count; 1191 uint8_t immediate_notify_resource_count; 1192 uint16_t timeout; 1193 uint8_t reserved_2[2]; 1194 1195 /* 1196 * LSB BIT 0 = Timer Operation mode bit 0 1197 * LSB BIT 1 = Timer Operation mode bit 1 1198 * LSB BIT 2 = Timer Operation mode bit 2 1199 * LSB BIT 3 = Timer Operation mode bit 3 1200 * LSB BIT 4 = Init Config Mode bit 0 1201 * LSB BIT 5 = Init Config Mode bit 1 1202 * LSB BIT 6 = Init Config Mode bit 2 1203 * LSB BIT 7 = Enable Non part on LIHA failure 1204 * 1205 * MSB BIT 0 = Enable class 2 1206 * MSB BIT 1 = Enable ACK0 1207 * MSB BIT 2 = 1208 * MSB BIT 3 = 1209 * MSB BIT 4 = FC Tape Enable 1210 * MSB BIT 5 = Enable FC Confirm 1211 * MSB BIT 6 = Enable command queuing in target mode 1212 * MSB BIT 7 = No Logo On Link Down 1213 */ 1214 uint8_t add_firmware_options[2]; 1215 1216 uint8_t response_accumulation_timer; 1217 uint8_t interrupt_delay_timer; 1218 1219 /* 1220 * LSB BIT 0 = Enable Read xfr_rdy 1221 * LSB BIT 1 = Soft ID only 1222 * LSB BIT 2 = 1223 * LSB BIT 3 = 1224 * LSB BIT 4 = FCP RSP Payload [0] 1225 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1226 * LSB BIT 6 = Enable Out-of-Order frame handling 1227 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1228 * 1229 * MSB BIT 0 = Sbus enable - 2300 1230 * MSB BIT 1 = 1231 * MSB BIT 2 = 1232 * MSB BIT 3 = 1233 * MSB BIT 4 = LED mode 1234 * MSB BIT 5 = enable 50 ohm termination 1235 * MSB BIT 6 = Data Rate (2300 only) 1236 * MSB BIT 7 = Data Rate (2300 only) 1237 */ 1238 uint8_t special_options[2]; 1239 1240 uint8_t reserved_3[26]; 1241 } init_cb_t; 1242 1243 /* 1244 * Get Link Status mailbox command return buffer. 1245 */ 1246 #define GLSO_SEND_RPS BIT_0 1247 #define GLSO_USE_DID BIT_3 1248 1249 struct link_statistics { 1250 uint32_t link_fail_cnt; 1251 uint32_t loss_sync_cnt; 1252 uint32_t loss_sig_cnt; 1253 uint32_t prim_seq_err_cnt; 1254 uint32_t inval_xmit_word_cnt; 1255 uint32_t inval_crc_cnt; 1256 uint32_t lip_cnt; 1257 uint32_t link_up_cnt; 1258 uint32_t link_down_loop_init_tmo; 1259 uint32_t link_down_los; 1260 uint32_t link_down_loss_rcv_clk; 1261 uint32_t reserved0[5]; 1262 uint32_t port_cfg_chg; 1263 uint32_t reserved1[11]; 1264 uint32_t rsp_q_full; 1265 uint32_t atio_q_full; 1266 uint32_t drop_ae; 1267 uint32_t els_proto_err; 1268 uint32_t reserved2; 1269 uint32_t tx_frames; 1270 uint32_t rx_frames; 1271 uint32_t discarded_frames; 1272 uint32_t dropped_frames; 1273 uint32_t reserved3; 1274 uint32_t nos_rcvd; 1275 uint32_t reserved4[4]; 1276 uint32_t tx_prjt; 1277 uint32_t rcv_exfail; 1278 uint32_t rcv_abts; 1279 uint32_t seq_frm_miss; 1280 uint32_t corr_err; 1281 uint32_t mb_rqst; 1282 uint32_t nport_full; 1283 uint32_t eofa; 1284 uint32_t reserved5; 1285 uint32_t fpm_recv_word_cnt_lo; 1286 uint32_t fpm_recv_word_cnt_hi; 1287 uint32_t fpm_disc_word_cnt_lo; 1288 uint32_t fpm_disc_word_cnt_hi; 1289 uint32_t fpm_xmit_word_cnt_lo; 1290 uint32_t fpm_xmit_word_cnt_hi; 1291 uint32_t reserved6[70]; 1292 }; 1293 1294 /* 1295 * NVRAM Command values. 1296 */ 1297 #define NV_START_BIT BIT_2 1298 #define NV_WRITE_OP (BIT_26+BIT_24) 1299 #define NV_READ_OP (BIT_26+BIT_25) 1300 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1301 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1302 #define NV_DELAY_COUNT 10 1303 1304 /* 1305 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1306 */ 1307 typedef struct { 1308 /* 1309 * NVRAM header 1310 */ 1311 uint8_t id[4]; 1312 uint8_t nvram_version; 1313 uint8_t reserved_0; 1314 1315 /* 1316 * NVRAM RISC parameter block 1317 */ 1318 uint8_t parameter_block_version; 1319 uint8_t reserved_1; 1320 1321 /* 1322 * LSB BIT 0 = Enable Hard Loop Id 1323 * LSB BIT 1 = Enable Fairness 1324 * LSB BIT 2 = Enable Full-Duplex 1325 * LSB BIT 3 = Enable Fast Posting 1326 * LSB BIT 4 = Enable Target Mode 1327 * LSB BIT 5 = Disable Initiator Mode 1328 * LSB BIT 6 = Enable ADISC 1329 * LSB BIT 7 = Enable Target Inquiry Data 1330 * 1331 * MSB BIT 0 = Enable PDBC Notify 1332 * MSB BIT 1 = Non Participating LIP 1333 * MSB BIT 2 = Descending Loop ID Search 1334 * MSB BIT 3 = Acquire Loop ID in LIPA 1335 * MSB BIT 4 = Stop PortQ on Full Status 1336 * MSB BIT 5 = Full Login after LIP 1337 * MSB BIT 6 = Node Name Option 1338 * MSB BIT 7 = Ext IFWCB enable bit 1339 */ 1340 uint8_t firmware_options[2]; 1341 1342 uint16_t frame_payload_size; 1343 uint16_t max_iocb_allocation; 1344 uint16_t execution_throttle; 1345 uint8_t retry_count; 1346 uint8_t retry_delay; /* unused */ 1347 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1348 uint16_t hard_address; 1349 uint8_t inquiry_data; 1350 uint8_t login_timeout; 1351 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1352 1353 /* 1354 * LSB BIT 0 = Timer Operation mode bit 0 1355 * LSB BIT 1 = Timer Operation mode bit 1 1356 * LSB BIT 2 = Timer Operation mode bit 2 1357 * LSB BIT 3 = Timer Operation mode bit 3 1358 * LSB BIT 4 = Init Config Mode bit 0 1359 * LSB BIT 5 = Init Config Mode bit 1 1360 * LSB BIT 6 = Init Config Mode bit 2 1361 * LSB BIT 7 = Enable Non part on LIHA failure 1362 * 1363 * MSB BIT 0 = Enable class 2 1364 * MSB BIT 1 = Enable ACK0 1365 * MSB BIT 2 = 1366 * MSB BIT 3 = 1367 * MSB BIT 4 = FC Tape Enable 1368 * MSB BIT 5 = Enable FC Confirm 1369 * MSB BIT 6 = Enable command queuing in target mode 1370 * MSB BIT 7 = No Logo On Link Down 1371 */ 1372 uint8_t add_firmware_options[2]; 1373 1374 uint8_t response_accumulation_timer; 1375 uint8_t interrupt_delay_timer; 1376 1377 /* 1378 * LSB BIT 0 = Enable Read xfr_rdy 1379 * LSB BIT 1 = Soft ID only 1380 * LSB BIT 2 = 1381 * LSB BIT 3 = 1382 * LSB BIT 4 = FCP RSP Payload [0] 1383 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1384 * LSB BIT 6 = Enable Out-of-Order frame handling 1385 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1386 * 1387 * MSB BIT 0 = Sbus enable - 2300 1388 * MSB BIT 1 = 1389 * MSB BIT 2 = 1390 * MSB BIT 3 = 1391 * MSB BIT 4 = LED mode 1392 * MSB BIT 5 = enable 50 ohm termination 1393 * MSB BIT 6 = Data Rate (2300 only) 1394 * MSB BIT 7 = Data Rate (2300 only) 1395 */ 1396 uint8_t special_options[2]; 1397 1398 /* Reserved for expanded RISC parameter block */ 1399 uint8_t reserved_2[22]; 1400 1401 /* 1402 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1403 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1404 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1405 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1406 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1407 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1408 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1409 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1410 * 1411 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1412 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1413 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1414 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1415 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1416 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1417 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1418 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1419 * 1420 * LSB BIT 0 = Output Swing 1G bit 0 1421 * LSB BIT 1 = Output Swing 1G bit 1 1422 * LSB BIT 2 = Output Swing 1G bit 2 1423 * LSB BIT 3 = Output Emphasis 1G bit 0 1424 * LSB BIT 4 = Output Emphasis 1G bit 1 1425 * LSB BIT 5 = Output Swing 2G bit 0 1426 * LSB BIT 6 = Output Swing 2G bit 1 1427 * LSB BIT 7 = Output Swing 2G bit 2 1428 * 1429 * MSB BIT 0 = Output Emphasis 2G bit 0 1430 * MSB BIT 1 = Output Emphasis 2G bit 1 1431 * MSB BIT 2 = Output Enable 1432 * MSB BIT 3 = 1433 * MSB BIT 4 = 1434 * MSB BIT 5 = 1435 * MSB BIT 6 = 1436 * MSB BIT 7 = 1437 */ 1438 uint8_t seriallink_options[4]; 1439 1440 /* 1441 * NVRAM host parameter block 1442 * 1443 * LSB BIT 0 = Enable spinup delay 1444 * LSB BIT 1 = Disable BIOS 1445 * LSB BIT 2 = Enable Memory Map BIOS 1446 * LSB BIT 3 = Enable Selectable Boot 1447 * LSB BIT 4 = Disable RISC code load 1448 * LSB BIT 5 = Set cache line size 1 1449 * LSB BIT 6 = PCI Parity Disable 1450 * LSB BIT 7 = Enable extended logging 1451 * 1452 * MSB BIT 0 = Enable 64bit addressing 1453 * MSB BIT 1 = Enable lip reset 1454 * MSB BIT 2 = Enable lip full login 1455 * MSB BIT 3 = Enable target reset 1456 * MSB BIT 4 = Enable database storage 1457 * MSB BIT 5 = Enable cache flush read 1458 * MSB BIT 6 = Enable database load 1459 * MSB BIT 7 = Enable alternate WWN 1460 */ 1461 uint8_t host_p[2]; 1462 1463 uint8_t boot_node_name[WWN_SIZE]; 1464 uint8_t boot_lun_number; 1465 uint8_t reset_delay; 1466 uint8_t port_down_retry_count; 1467 uint8_t boot_id_number; 1468 uint16_t max_luns_per_target; 1469 uint8_t fcode_boot_port_name[WWN_SIZE]; 1470 uint8_t alternate_port_name[WWN_SIZE]; 1471 uint8_t alternate_node_name[WWN_SIZE]; 1472 1473 /* 1474 * BIT 0 = Selective Login 1475 * BIT 1 = Alt-Boot Enable 1476 * BIT 2 = 1477 * BIT 3 = Boot Order List 1478 * BIT 4 = 1479 * BIT 5 = Selective LUN 1480 * BIT 6 = 1481 * BIT 7 = unused 1482 */ 1483 uint8_t efi_parameters; 1484 1485 uint8_t link_down_timeout; 1486 1487 uint8_t adapter_id[16]; 1488 1489 uint8_t alt1_boot_node_name[WWN_SIZE]; 1490 uint16_t alt1_boot_lun_number; 1491 uint8_t alt2_boot_node_name[WWN_SIZE]; 1492 uint16_t alt2_boot_lun_number; 1493 uint8_t alt3_boot_node_name[WWN_SIZE]; 1494 uint16_t alt3_boot_lun_number; 1495 uint8_t alt4_boot_node_name[WWN_SIZE]; 1496 uint16_t alt4_boot_lun_number; 1497 uint8_t alt5_boot_node_name[WWN_SIZE]; 1498 uint16_t alt5_boot_lun_number; 1499 uint8_t alt6_boot_node_name[WWN_SIZE]; 1500 uint16_t alt6_boot_lun_number; 1501 uint8_t alt7_boot_node_name[WWN_SIZE]; 1502 uint16_t alt7_boot_lun_number; 1503 1504 uint8_t reserved_3[2]; 1505 1506 /* Offset 200-215 : Model Number */ 1507 uint8_t model_number[16]; 1508 1509 /* OEM related items */ 1510 uint8_t oem_specific[16]; 1511 1512 /* 1513 * NVRAM Adapter Features offset 232-239 1514 * 1515 * LSB BIT 0 = External GBIC 1516 * LSB BIT 1 = Risc RAM parity 1517 * LSB BIT 2 = Buffer Plus Module 1518 * LSB BIT 3 = Multi Chip Adapter 1519 * LSB BIT 4 = Internal connector 1520 * LSB BIT 5 = 1521 * LSB BIT 6 = 1522 * LSB BIT 7 = 1523 * 1524 * MSB BIT 0 = 1525 * MSB BIT 1 = 1526 * MSB BIT 2 = 1527 * MSB BIT 3 = 1528 * MSB BIT 4 = 1529 * MSB BIT 5 = 1530 * MSB BIT 6 = 1531 * MSB BIT 7 = 1532 */ 1533 uint8_t adapter_features[2]; 1534 1535 uint8_t reserved_4[16]; 1536 1537 /* Subsystem vendor ID for ISP2200 */ 1538 uint16_t subsystem_vendor_id_2200; 1539 1540 /* Subsystem device ID for ISP2200 */ 1541 uint16_t subsystem_device_id_2200; 1542 1543 uint8_t reserved_5; 1544 uint8_t checksum; 1545 } nvram_t; 1546 1547 /* 1548 * ISP queue - response queue entry definition. 1549 */ 1550 typedef struct { 1551 uint8_t entry_type; /* Entry type. */ 1552 uint8_t entry_count; /* Entry count. */ 1553 uint8_t sys_define; /* System defined. */ 1554 uint8_t entry_status; /* Entry Status. */ 1555 uint32_t handle; /* System defined handle */ 1556 uint8_t data[52]; 1557 uint32_t signature; 1558 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1559 } response_t; 1560 1561 /* 1562 * ISP queue - ATIO queue entry definition. 1563 */ 1564 struct atio { 1565 uint8_t entry_type; /* Entry type. */ 1566 uint8_t entry_count; /* Entry count. */ 1567 uint8_t data[58]; 1568 uint32_t signature; 1569 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1570 }; 1571 1572 typedef union { 1573 uint16_t extended; 1574 struct { 1575 uint8_t reserved; 1576 uint8_t standard; 1577 } id; 1578 } target_id_t; 1579 1580 #define SET_TARGET_ID(ha, to, from) \ 1581 do { \ 1582 if (HAS_EXTENDED_IDS(ha)) \ 1583 to.extended = cpu_to_le16(from); \ 1584 else \ 1585 to.id.standard = (uint8_t)from; \ 1586 } while (0) 1587 1588 /* 1589 * ISP queue - command entry structure definition. 1590 */ 1591 #define COMMAND_TYPE 0x11 /* Command entry */ 1592 typedef struct { 1593 uint8_t entry_type; /* Entry type. */ 1594 uint8_t entry_count; /* Entry count. */ 1595 uint8_t sys_define; /* System defined. */ 1596 uint8_t entry_status; /* Entry Status. */ 1597 uint32_t handle; /* System handle. */ 1598 target_id_t target; /* SCSI ID */ 1599 uint16_t lun; /* SCSI LUN */ 1600 uint16_t control_flags; /* Control flags. */ 1601 #define CF_WRITE BIT_6 1602 #define CF_READ BIT_5 1603 #define CF_SIMPLE_TAG BIT_3 1604 #define CF_ORDERED_TAG BIT_2 1605 #define CF_HEAD_TAG BIT_1 1606 uint16_t reserved_1; 1607 uint16_t timeout; /* Command timeout. */ 1608 uint16_t dseg_count; /* Data segment count. */ 1609 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1610 uint32_t byte_count; /* Total byte count. */ 1611 uint32_t dseg_0_address; /* Data segment 0 address. */ 1612 uint32_t dseg_0_length; /* Data segment 0 length. */ 1613 uint32_t dseg_1_address; /* Data segment 1 address. */ 1614 uint32_t dseg_1_length; /* Data segment 1 length. */ 1615 uint32_t dseg_2_address; /* Data segment 2 address. */ 1616 uint32_t dseg_2_length; /* Data segment 2 length. */ 1617 } cmd_entry_t; 1618 1619 /* 1620 * ISP queue - 64-Bit addressing, command entry structure definition. 1621 */ 1622 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1623 typedef struct { 1624 uint8_t entry_type; /* Entry type. */ 1625 uint8_t entry_count; /* Entry count. */ 1626 uint8_t sys_define; /* System defined. */ 1627 uint8_t entry_status; /* Entry Status. */ 1628 uint32_t handle; /* System handle. */ 1629 target_id_t target; /* SCSI ID */ 1630 uint16_t lun; /* SCSI LUN */ 1631 uint16_t control_flags; /* Control flags. */ 1632 uint16_t reserved_1; 1633 uint16_t timeout; /* Command timeout. */ 1634 uint16_t dseg_count; /* Data segment count. */ 1635 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1636 uint32_t byte_count; /* Total byte count. */ 1637 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1638 uint32_t dseg_0_length; /* Data segment 0 length. */ 1639 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1640 uint32_t dseg_1_length; /* Data segment 1 length. */ 1641 } cmd_a64_entry_t, request_t; 1642 1643 /* 1644 * ISP queue - continuation entry structure definition. 1645 */ 1646 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1647 typedef struct { 1648 uint8_t entry_type; /* Entry type. */ 1649 uint8_t entry_count; /* Entry count. */ 1650 uint8_t sys_define; /* System defined. */ 1651 uint8_t entry_status; /* Entry Status. */ 1652 uint32_t reserved; 1653 uint32_t dseg_0_address; /* Data segment 0 address. */ 1654 uint32_t dseg_0_length; /* Data segment 0 length. */ 1655 uint32_t dseg_1_address; /* Data segment 1 address. */ 1656 uint32_t dseg_1_length; /* Data segment 1 length. */ 1657 uint32_t dseg_2_address; /* Data segment 2 address. */ 1658 uint32_t dseg_2_length; /* Data segment 2 length. */ 1659 uint32_t dseg_3_address; /* Data segment 3 address. */ 1660 uint32_t dseg_3_length; /* Data segment 3 length. */ 1661 uint32_t dseg_4_address; /* Data segment 4 address. */ 1662 uint32_t dseg_4_length; /* Data segment 4 length. */ 1663 uint32_t dseg_5_address; /* Data segment 5 address. */ 1664 uint32_t dseg_5_length; /* Data segment 5 length. */ 1665 uint32_t dseg_6_address; /* Data segment 6 address. */ 1666 uint32_t dseg_6_length; /* Data segment 6 length. */ 1667 } cont_entry_t; 1668 1669 /* 1670 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1671 */ 1672 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1673 typedef struct { 1674 uint8_t entry_type; /* Entry type. */ 1675 uint8_t entry_count; /* Entry count. */ 1676 uint8_t sys_define; /* System defined. */ 1677 uint8_t entry_status; /* Entry Status. */ 1678 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1679 uint32_t dseg_0_length; /* Data segment 0 length. */ 1680 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1681 uint32_t dseg_1_length; /* Data segment 1 length. */ 1682 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1683 uint32_t dseg_2_length; /* Data segment 2 length. */ 1684 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1685 uint32_t dseg_3_length; /* Data segment 3 length. */ 1686 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1687 uint32_t dseg_4_length; /* Data segment 4 length. */ 1688 } cont_a64_entry_t; 1689 1690 #define PO_MODE_DIF_INSERT 0 1691 #define PO_MODE_DIF_REMOVE 1 1692 #define PO_MODE_DIF_PASS 2 1693 #define PO_MODE_DIF_REPLACE 3 1694 #define PO_MODE_DIF_TCP_CKSUM 6 1695 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1696 #define PO_DISABLE_GUARD_CHECK BIT_4 1697 #define PO_DISABLE_INCR_REF_TAG BIT_5 1698 #define PO_DIS_HEADER_MODE BIT_7 1699 #define PO_ENABLE_DIF_BUNDLING BIT_8 1700 #define PO_DIS_FRAME_MODE BIT_9 1701 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1702 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1703 1704 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1705 #define PO_DIS_REF_TAG_REPL BIT_13 1706 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1707 #define PO_DIS_REF_TAG_VALD BIT_15 1708 1709 /* 1710 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1711 */ 1712 struct crc_context { 1713 uint32_t handle; /* System handle. */ 1714 __le32 ref_tag; 1715 __le16 app_tag; 1716 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1717 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1718 __le16 guard_seed; /* Initial Guard Seed */ 1719 __le16 prot_opts; /* Requested Data Protection Mode */ 1720 __le16 blk_size; /* Data size in bytes */ 1721 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1722 * only) */ 1723 __le32 byte_count; /* Total byte count/ total data 1724 * transfer count */ 1725 union { 1726 struct { 1727 uint32_t reserved_1; 1728 uint16_t reserved_2; 1729 uint16_t reserved_3; 1730 uint32_t reserved_4; 1731 uint32_t data_address[2]; 1732 uint32_t data_length; 1733 uint32_t reserved_5[2]; 1734 uint32_t reserved_6; 1735 } nobundling; 1736 struct { 1737 __le32 dif_byte_count; /* Total DIF byte 1738 * count */ 1739 uint16_t reserved_1; 1740 __le16 dseg_count; /* Data segment count */ 1741 uint32_t reserved_2; 1742 uint32_t data_address[2]; 1743 uint32_t data_length; 1744 uint32_t dif_address[2]; 1745 uint32_t dif_length; /* Data segment 0 1746 * length */ 1747 } bundling; 1748 } u; 1749 1750 struct fcp_cmnd fcp_cmnd; 1751 dma_addr_t crc_ctx_dma; 1752 /* List of DMA context transfers */ 1753 struct list_head dsd_list; 1754 1755 /* This structure should not exceed 512 bytes */ 1756 }; 1757 1758 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1759 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1760 1761 /* 1762 * ISP queue - status entry structure definition. 1763 */ 1764 #define STATUS_TYPE 0x03 /* Status entry. */ 1765 typedef struct { 1766 uint8_t entry_type; /* Entry type. */ 1767 uint8_t entry_count; /* Entry count. */ 1768 uint8_t sys_define; /* System defined. */ 1769 uint8_t entry_status; /* Entry Status. */ 1770 uint32_t handle; /* System handle. */ 1771 uint16_t scsi_status; /* SCSI status. */ 1772 uint16_t comp_status; /* Completion status. */ 1773 uint16_t state_flags; /* State flags. */ 1774 uint16_t status_flags; /* Status flags. */ 1775 uint16_t rsp_info_len; /* Response Info Length. */ 1776 uint16_t req_sense_length; /* Request sense data length. */ 1777 uint32_t residual_length; /* Residual transfer length. */ 1778 uint8_t rsp_info[8]; /* FCP response information. */ 1779 uint8_t req_sense_data[32]; /* Request sense data. */ 1780 } sts_entry_t; 1781 1782 /* 1783 * Status entry entry status 1784 */ 1785 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1786 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1787 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1788 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1789 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1790 #define RF_BUSY BIT_1 /* Busy */ 1791 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1792 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1793 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1794 RF_INV_E_TYPE) 1795 1796 /* 1797 * Status entry SCSI status bit definitions. 1798 */ 1799 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1800 #define SS_RESIDUAL_UNDER BIT_11 1801 #define SS_RESIDUAL_OVER BIT_10 1802 #define SS_SENSE_LEN_VALID BIT_9 1803 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1804 1805 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1806 #define SS_BUSY_CONDITION BIT_3 1807 #define SS_CONDITION_MET BIT_2 1808 #define SS_CHECK_CONDITION BIT_1 1809 1810 /* 1811 * Status entry completion status 1812 */ 1813 #define CS_COMPLETE 0x0 /* No errors */ 1814 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1815 #define CS_DMA 0x2 /* A DMA direction error. */ 1816 #define CS_TRANSPORT 0x3 /* Transport error. */ 1817 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1818 #define CS_ABORTED 0x5 /* System aborted command. */ 1819 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1820 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1821 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1822 1823 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1824 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1825 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1826 /* (selection timeout) */ 1827 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1828 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1829 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1830 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1831 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1832 failure */ 1833 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1834 #define CS_UNKNOWN 0x81 /* Driver defined */ 1835 #define CS_RETRY 0x82 /* Driver defined */ 1836 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1837 1838 #define CS_BIDIR_RD_OVERRUN 0x700 1839 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1840 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1841 #define CS_BIDIR_RD_UNDERRUN 0x1500 1842 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1843 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1844 #define CS_BIDIR_DMA 0x200 1845 /* 1846 * Status entry status flags 1847 */ 1848 #define SF_ABTS_TERMINATED BIT_10 1849 #define SF_LOGOUT_SENT BIT_13 1850 1851 /* 1852 * ISP queue - status continuation entry structure definition. 1853 */ 1854 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1855 typedef struct { 1856 uint8_t entry_type; /* Entry type. */ 1857 uint8_t entry_count; /* Entry count. */ 1858 uint8_t sys_define; /* System defined. */ 1859 uint8_t entry_status; /* Entry Status. */ 1860 uint8_t data[60]; /* data */ 1861 } sts_cont_entry_t; 1862 1863 /* 1864 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1865 * structure definition. 1866 */ 1867 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1868 typedef struct { 1869 uint8_t entry_type; /* Entry type. */ 1870 uint8_t entry_count; /* Entry count. */ 1871 uint8_t handle_count; /* Handle count. */ 1872 uint8_t entry_status; /* Entry Status. */ 1873 uint32_t handle[15]; /* System handles. */ 1874 } sts21_entry_t; 1875 1876 /* 1877 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1878 * structure definition. 1879 */ 1880 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1881 typedef struct { 1882 uint8_t entry_type; /* Entry type. */ 1883 uint8_t entry_count; /* Entry count. */ 1884 uint8_t handle_count; /* Handle count. */ 1885 uint8_t entry_status; /* Entry Status. */ 1886 uint16_t handle[30]; /* System handles. */ 1887 } sts22_entry_t; 1888 1889 /* 1890 * ISP queue - marker entry structure definition. 1891 */ 1892 #define MARKER_TYPE 0x04 /* Marker entry. */ 1893 typedef struct { 1894 uint8_t entry_type; /* Entry type. */ 1895 uint8_t entry_count; /* Entry count. */ 1896 uint8_t handle_count; /* Handle count. */ 1897 uint8_t entry_status; /* Entry Status. */ 1898 uint32_t sys_define_2; /* System defined. */ 1899 target_id_t target; /* SCSI ID */ 1900 uint8_t modifier; /* Modifier (7-0). */ 1901 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1902 #define MK_SYNC_ID 1 /* Synchronize ID */ 1903 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1904 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1905 /* clear port changed, */ 1906 /* use sequence number. */ 1907 uint8_t reserved_1; 1908 uint16_t sequence_number; /* Sequence number of event */ 1909 uint16_t lun; /* SCSI LUN */ 1910 uint8_t reserved_2[48]; 1911 } mrk_entry_t; 1912 1913 /* 1914 * ISP queue - Management Server entry structure definition. 1915 */ 1916 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1917 typedef struct { 1918 uint8_t entry_type; /* Entry type. */ 1919 uint8_t entry_count; /* Entry count. */ 1920 uint8_t handle_count; /* Handle count. */ 1921 uint8_t entry_status; /* Entry Status. */ 1922 uint32_t handle1; /* System handle. */ 1923 target_id_t loop_id; 1924 uint16_t status; 1925 uint16_t control_flags; /* Control flags. */ 1926 uint16_t reserved2; 1927 uint16_t timeout; 1928 uint16_t cmd_dsd_count; 1929 uint16_t total_dsd_count; 1930 uint8_t type; 1931 uint8_t r_ctl; 1932 uint16_t rx_id; 1933 uint16_t reserved3; 1934 uint32_t handle2; 1935 uint32_t rsp_bytecount; 1936 uint32_t req_bytecount; 1937 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1938 uint32_t dseg_req_length; /* Data segment 0 length. */ 1939 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1940 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1941 } ms_iocb_entry_t; 1942 1943 1944 /* 1945 * ISP queue - Mailbox Command entry structure definition. 1946 */ 1947 #define MBX_IOCB_TYPE 0x39 1948 struct mbx_entry { 1949 uint8_t entry_type; 1950 uint8_t entry_count; 1951 uint8_t sys_define1; 1952 /* Use sys_define1 for source type */ 1953 #define SOURCE_SCSI 0x00 1954 #define SOURCE_IP 0x01 1955 #define SOURCE_VI 0x02 1956 #define SOURCE_SCTP 0x03 1957 #define SOURCE_MP 0x04 1958 #define SOURCE_MPIOCTL 0x05 1959 #define SOURCE_ASYNC_IOCB 0x07 1960 1961 uint8_t entry_status; 1962 1963 uint32_t handle; 1964 target_id_t loop_id; 1965 1966 uint16_t status; 1967 uint16_t state_flags; 1968 uint16_t status_flags; 1969 1970 uint32_t sys_define2[2]; 1971 1972 uint16_t mb0; 1973 uint16_t mb1; 1974 uint16_t mb2; 1975 uint16_t mb3; 1976 uint16_t mb6; 1977 uint16_t mb7; 1978 uint16_t mb9; 1979 uint16_t mb10; 1980 uint32_t reserved_2[2]; 1981 uint8_t node_name[WWN_SIZE]; 1982 uint8_t port_name[WWN_SIZE]; 1983 }; 1984 1985 /* 1986 * ISP request and response queue entry sizes 1987 */ 1988 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1989 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1990 1991 1992 /* 1993 * 24 bit port ID type definition. 1994 */ 1995 typedef union { 1996 uint32_t b24 : 24; 1997 1998 struct { 1999 #ifdef __BIG_ENDIAN 2000 uint8_t domain; 2001 uint8_t area; 2002 uint8_t al_pa; 2003 #elif defined(__LITTLE_ENDIAN) 2004 uint8_t al_pa; 2005 uint8_t area; 2006 uint8_t domain; 2007 #else 2008 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 2009 #endif 2010 uint8_t rsvd_1; 2011 } b; 2012 } port_id_t; 2013 #define INVALID_PORT_ID 0xFFFFFF 2014 2015 /* 2016 * Switch info gathering structure. 2017 */ 2018 typedef struct { 2019 port_id_t d_id; 2020 uint8_t node_name[WWN_SIZE]; 2021 uint8_t port_name[WWN_SIZE]; 2022 uint8_t fabric_port_name[WWN_SIZE]; 2023 uint16_t fp_speed; 2024 uint8_t fc4_type; 2025 } sw_info_t; 2026 2027 /* FCP-4 types */ 2028 #define FC4_TYPE_FCP_SCSI 0x08 2029 #define FC4_TYPE_OTHER 0x0 2030 #define FC4_TYPE_UNKNOWN 0xff 2031 2032 /* 2033 * Fibre channel port type. 2034 */ 2035 typedef enum { 2036 FCT_UNKNOWN, 2037 FCT_RSCN, 2038 FCT_SWITCH, 2039 FCT_BROADCAST, 2040 FCT_INITIATOR, 2041 FCT_TARGET 2042 } fc_port_type_t; 2043 2044 /* 2045 * Fibre channel port structure. 2046 */ 2047 typedef struct fc_port { 2048 struct list_head list; 2049 struct scsi_qla_host *vha; 2050 2051 uint8_t node_name[WWN_SIZE]; 2052 uint8_t port_name[WWN_SIZE]; 2053 port_id_t d_id; 2054 uint16_t loop_id; 2055 uint16_t old_loop_id; 2056 2057 uint16_t tgt_id; 2058 uint16_t old_tgt_id; 2059 2060 uint8_t fcp_prio; 2061 2062 uint8_t fabric_port_name[WWN_SIZE]; 2063 uint16_t fp_speed; 2064 2065 fc_port_type_t port_type; 2066 2067 atomic_t state; 2068 uint32_t flags; 2069 2070 int login_retry; 2071 2072 struct fc_rport *rport, *drport; 2073 u32 supported_classes; 2074 2075 uint8_t fc4_type; 2076 uint8_t scan_state; 2077 2078 unsigned long last_queue_full; 2079 unsigned long last_ramp_up; 2080 2081 uint16_t port_id; 2082 2083 unsigned long retry_delay_timestamp; 2084 struct qla_tgt_sess *tgt_session; 2085 } fc_port_t; 2086 2087 #include "qla_mr.h" 2088 2089 /* 2090 * Fibre channel port/lun states. 2091 */ 2092 #define FCS_UNCONFIGURED 1 2093 #define FCS_DEVICE_DEAD 2 2094 #define FCS_DEVICE_LOST 3 2095 #define FCS_ONLINE 4 2096 2097 static const char * const port_state_str[] = { 2098 "Unknown", 2099 "UNCONFIGURED", 2100 "DEAD", 2101 "LOST", 2102 "ONLINE" 2103 }; 2104 2105 /* 2106 * FC port flags. 2107 */ 2108 #define FCF_FABRIC_DEVICE BIT_0 2109 #define FCF_LOGIN_NEEDED BIT_1 2110 #define FCF_FCP2_DEVICE BIT_2 2111 #define FCF_ASYNC_SENT BIT_3 2112 #define FCF_CONF_COMP_SUPPORTED BIT_4 2113 2114 /* No loop ID flag. */ 2115 #define FC_NO_LOOP_ID 0x1000 2116 2117 /* 2118 * FC-CT interface 2119 * 2120 * NOTE: All structures are big-endian in form. 2121 */ 2122 2123 #define CT_REJECT_RESPONSE 0x8001 2124 #define CT_ACCEPT_RESPONSE 0x8002 2125 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2126 #define CT_REASON_CANNOT_PERFORM 0x09 2127 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2128 #define CT_EXPL_ALREADY_REGISTERED 0x10 2129 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2130 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2131 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2132 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2133 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2134 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2135 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2136 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2137 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2138 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2139 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2140 2141 #define NS_N_PORT_TYPE 0x01 2142 #define NS_NL_PORT_TYPE 0x02 2143 #define NS_NX_PORT_TYPE 0x7F 2144 2145 #define GA_NXT_CMD 0x100 2146 #define GA_NXT_REQ_SIZE (16 + 4) 2147 #define GA_NXT_RSP_SIZE (16 + 620) 2148 2149 #define GID_PT_CMD 0x1A1 2150 #define GID_PT_REQ_SIZE (16 + 4) 2151 2152 #define GPN_ID_CMD 0x112 2153 #define GPN_ID_REQ_SIZE (16 + 4) 2154 #define GPN_ID_RSP_SIZE (16 + 8) 2155 2156 #define GNN_ID_CMD 0x113 2157 #define GNN_ID_REQ_SIZE (16 + 4) 2158 #define GNN_ID_RSP_SIZE (16 + 8) 2159 2160 #define GFT_ID_CMD 0x117 2161 #define GFT_ID_REQ_SIZE (16 + 4) 2162 #define GFT_ID_RSP_SIZE (16 + 32) 2163 2164 #define RFT_ID_CMD 0x217 2165 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2166 #define RFT_ID_RSP_SIZE 16 2167 2168 #define RFF_ID_CMD 0x21F 2169 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2170 #define RFF_ID_RSP_SIZE 16 2171 2172 #define RNN_ID_CMD 0x213 2173 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2174 #define RNN_ID_RSP_SIZE 16 2175 2176 #define RSNN_NN_CMD 0x239 2177 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2178 #define RSNN_NN_RSP_SIZE 16 2179 2180 #define GFPN_ID_CMD 0x11C 2181 #define GFPN_ID_REQ_SIZE (16 + 4) 2182 #define GFPN_ID_RSP_SIZE (16 + 8) 2183 2184 #define GPSC_CMD 0x127 2185 #define GPSC_REQ_SIZE (16 + 8) 2186 #define GPSC_RSP_SIZE (16 + 2 + 2) 2187 2188 #define GFF_ID_CMD 0x011F 2189 #define GFF_ID_REQ_SIZE (16 + 4) 2190 #define GFF_ID_RSP_SIZE (16 + 128) 2191 2192 /* 2193 * HBA attribute types. 2194 */ 2195 #define FDMI_HBA_ATTR_COUNT 9 2196 #define FDMIV2_HBA_ATTR_COUNT 17 2197 #define FDMI_HBA_NODE_NAME 0x1 2198 #define FDMI_HBA_MANUFACTURER 0x2 2199 #define FDMI_HBA_SERIAL_NUMBER 0x3 2200 #define FDMI_HBA_MODEL 0x4 2201 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2202 #define FDMI_HBA_HARDWARE_VERSION 0x6 2203 #define FDMI_HBA_DRIVER_VERSION 0x7 2204 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2205 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2206 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2207 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2208 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2209 #define FDMI_HBA_VENDOR_ID 0xd 2210 #define FDMI_HBA_NUM_PORTS 0xe 2211 #define FDMI_HBA_FABRIC_NAME 0xf 2212 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2213 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2214 2215 struct ct_fdmi_hba_attr { 2216 uint16_t type; 2217 uint16_t len; 2218 union { 2219 uint8_t node_name[WWN_SIZE]; 2220 uint8_t manufacturer[64]; 2221 uint8_t serial_num[32]; 2222 uint8_t model[16+1]; 2223 uint8_t model_desc[80]; 2224 uint8_t hw_version[32]; 2225 uint8_t driver_version[32]; 2226 uint8_t orom_version[16]; 2227 uint8_t fw_version[32]; 2228 uint8_t os_version[128]; 2229 uint32_t max_ct_len; 2230 } a; 2231 }; 2232 2233 struct ct_fdmi_hba_attributes { 2234 uint32_t count; 2235 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2236 }; 2237 2238 struct ct_fdmiv2_hba_attr { 2239 uint16_t type; 2240 uint16_t len; 2241 union { 2242 uint8_t node_name[WWN_SIZE]; 2243 uint8_t manufacturer[64]; 2244 uint8_t serial_num[32]; 2245 uint8_t model[16+1]; 2246 uint8_t model_desc[80]; 2247 uint8_t hw_version[16]; 2248 uint8_t driver_version[32]; 2249 uint8_t orom_version[16]; 2250 uint8_t fw_version[32]; 2251 uint8_t os_version[128]; 2252 uint32_t max_ct_len; 2253 uint8_t sym_name[256]; 2254 uint32_t vendor_id; 2255 uint32_t num_ports; 2256 uint8_t fabric_name[WWN_SIZE]; 2257 uint8_t bios_name[32]; 2258 uint8_t vendor_indentifer[8]; 2259 } a; 2260 }; 2261 2262 struct ct_fdmiv2_hba_attributes { 2263 uint32_t count; 2264 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2265 }; 2266 2267 /* 2268 * Port attribute types. 2269 */ 2270 #define FDMI_PORT_ATTR_COUNT 6 2271 #define FDMIV2_PORT_ATTR_COUNT 16 2272 #define FDMI_PORT_FC4_TYPES 0x1 2273 #define FDMI_PORT_SUPPORT_SPEED 0x2 2274 #define FDMI_PORT_CURRENT_SPEED 0x3 2275 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2276 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2277 #define FDMI_PORT_HOST_NAME 0x6 2278 #define FDMI_PORT_NODE_NAME 0x7 2279 #define FDMI_PORT_NAME 0x8 2280 #define FDMI_PORT_SYM_NAME 0x9 2281 #define FDMI_PORT_TYPE 0xa 2282 #define FDMI_PORT_SUPP_COS 0xb 2283 #define FDMI_PORT_FABRIC_NAME 0xc 2284 #define FDMI_PORT_FC4_TYPE 0xd 2285 #define FDMI_PORT_STATE 0x101 2286 #define FDMI_PORT_COUNT 0x102 2287 #define FDMI_PORT_ID 0x103 2288 2289 #define FDMI_PORT_SPEED_1GB 0x1 2290 #define FDMI_PORT_SPEED_2GB 0x2 2291 #define FDMI_PORT_SPEED_10GB 0x4 2292 #define FDMI_PORT_SPEED_4GB 0x8 2293 #define FDMI_PORT_SPEED_8GB 0x10 2294 #define FDMI_PORT_SPEED_16GB 0x20 2295 #define FDMI_PORT_SPEED_32GB 0x40 2296 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2297 2298 #define FC_CLASS_2 0x04 2299 #define FC_CLASS_3 0x08 2300 #define FC_CLASS_2_3 0x0C 2301 2302 struct ct_fdmiv2_port_attr { 2303 uint16_t type; 2304 uint16_t len; 2305 union { 2306 uint8_t fc4_types[32]; 2307 uint32_t sup_speed; 2308 uint32_t cur_speed; 2309 uint32_t max_frame_size; 2310 uint8_t os_dev_name[32]; 2311 uint8_t host_name[256]; 2312 uint8_t node_name[WWN_SIZE]; 2313 uint8_t port_name[WWN_SIZE]; 2314 uint8_t port_sym_name[128]; 2315 uint32_t port_type; 2316 uint32_t port_supported_cos; 2317 uint8_t fabric_name[WWN_SIZE]; 2318 uint8_t port_fc4_type[32]; 2319 uint32_t port_state; 2320 uint32_t num_ports; 2321 uint32_t port_id; 2322 } a; 2323 }; 2324 2325 /* 2326 * Port Attribute Block. 2327 */ 2328 struct ct_fdmiv2_port_attributes { 2329 uint32_t count; 2330 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2331 }; 2332 2333 struct ct_fdmi_port_attr { 2334 uint16_t type; 2335 uint16_t len; 2336 union { 2337 uint8_t fc4_types[32]; 2338 uint32_t sup_speed; 2339 uint32_t cur_speed; 2340 uint32_t max_frame_size; 2341 uint8_t os_dev_name[32]; 2342 uint8_t host_name[256]; 2343 } a; 2344 }; 2345 2346 struct ct_fdmi_port_attributes { 2347 uint32_t count; 2348 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2349 }; 2350 2351 /* FDMI definitions. */ 2352 #define GRHL_CMD 0x100 2353 #define GHAT_CMD 0x101 2354 #define GRPL_CMD 0x102 2355 #define GPAT_CMD 0x110 2356 2357 #define RHBA_CMD 0x200 2358 #define RHBA_RSP_SIZE 16 2359 2360 #define RHAT_CMD 0x201 2361 #define RPRT_CMD 0x210 2362 2363 #define RPA_CMD 0x211 2364 #define RPA_RSP_SIZE 16 2365 2366 #define DHBA_CMD 0x300 2367 #define DHBA_REQ_SIZE (16 + 8) 2368 #define DHBA_RSP_SIZE 16 2369 2370 #define DHAT_CMD 0x301 2371 #define DPRT_CMD 0x310 2372 #define DPA_CMD 0x311 2373 2374 /* CT command header -- request/response common fields */ 2375 struct ct_cmd_hdr { 2376 uint8_t revision; 2377 uint8_t in_id[3]; 2378 uint8_t gs_type; 2379 uint8_t gs_subtype; 2380 uint8_t options; 2381 uint8_t reserved; 2382 }; 2383 2384 /* CT command request */ 2385 struct ct_sns_req { 2386 struct ct_cmd_hdr header; 2387 uint16_t command; 2388 uint16_t max_rsp_size; 2389 uint8_t fragment_id; 2390 uint8_t reserved[3]; 2391 2392 union { 2393 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2394 struct { 2395 uint8_t reserved; 2396 uint8_t port_id[3]; 2397 } port_id; 2398 2399 struct { 2400 uint8_t port_type; 2401 uint8_t domain; 2402 uint8_t area; 2403 uint8_t reserved; 2404 } gid_pt; 2405 2406 struct { 2407 uint8_t reserved; 2408 uint8_t port_id[3]; 2409 uint8_t fc4_types[32]; 2410 } rft_id; 2411 2412 struct { 2413 uint8_t reserved; 2414 uint8_t port_id[3]; 2415 uint16_t reserved2; 2416 uint8_t fc4_feature; 2417 uint8_t fc4_type; 2418 } rff_id; 2419 2420 struct { 2421 uint8_t reserved; 2422 uint8_t port_id[3]; 2423 uint8_t node_name[8]; 2424 } rnn_id; 2425 2426 struct { 2427 uint8_t node_name[8]; 2428 uint8_t name_len; 2429 uint8_t sym_node_name[255]; 2430 } rsnn_nn; 2431 2432 struct { 2433 uint8_t hba_indentifier[8]; 2434 } ghat; 2435 2436 struct { 2437 uint8_t hba_identifier[8]; 2438 uint32_t entry_count; 2439 uint8_t port_name[8]; 2440 struct ct_fdmi_hba_attributes attrs; 2441 } rhba; 2442 2443 struct { 2444 uint8_t hba_identifier[8]; 2445 uint32_t entry_count; 2446 uint8_t port_name[8]; 2447 struct ct_fdmiv2_hba_attributes attrs; 2448 } rhba2; 2449 2450 struct { 2451 uint8_t hba_identifier[8]; 2452 struct ct_fdmi_hba_attributes attrs; 2453 } rhat; 2454 2455 struct { 2456 uint8_t port_name[8]; 2457 struct ct_fdmi_port_attributes attrs; 2458 } rpa; 2459 2460 struct { 2461 uint8_t port_name[8]; 2462 struct ct_fdmiv2_port_attributes attrs; 2463 } rpa2; 2464 2465 struct { 2466 uint8_t port_name[8]; 2467 } dhba; 2468 2469 struct { 2470 uint8_t port_name[8]; 2471 } dhat; 2472 2473 struct { 2474 uint8_t port_name[8]; 2475 } dprt; 2476 2477 struct { 2478 uint8_t port_name[8]; 2479 } dpa; 2480 2481 struct { 2482 uint8_t port_name[8]; 2483 } gpsc; 2484 2485 struct { 2486 uint8_t reserved; 2487 uint8_t port_name[3]; 2488 } gff_id; 2489 } req; 2490 }; 2491 2492 /* CT command response header */ 2493 struct ct_rsp_hdr { 2494 struct ct_cmd_hdr header; 2495 uint16_t response; 2496 uint16_t residual; 2497 uint8_t fragment_id; 2498 uint8_t reason_code; 2499 uint8_t explanation_code; 2500 uint8_t vendor_unique; 2501 }; 2502 2503 struct ct_sns_gid_pt_data { 2504 uint8_t control_byte; 2505 uint8_t port_id[3]; 2506 }; 2507 2508 struct ct_sns_rsp { 2509 struct ct_rsp_hdr header; 2510 2511 union { 2512 struct { 2513 uint8_t port_type; 2514 uint8_t port_id[3]; 2515 uint8_t port_name[8]; 2516 uint8_t sym_port_name_len; 2517 uint8_t sym_port_name[255]; 2518 uint8_t node_name[8]; 2519 uint8_t sym_node_name_len; 2520 uint8_t sym_node_name[255]; 2521 uint8_t init_proc_assoc[8]; 2522 uint8_t node_ip_addr[16]; 2523 uint8_t class_of_service[4]; 2524 uint8_t fc4_types[32]; 2525 uint8_t ip_address[16]; 2526 uint8_t fabric_port_name[8]; 2527 uint8_t reserved; 2528 uint8_t hard_address[3]; 2529 } ga_nxt; 2530 2531 struct { 2532 /* Assume the largest number of targets for the union */ 2533 struct ct_sns_gid_pt_data 2534 entries[MAX_FIBRE_DEVICES_MAX]; 2535 } gid_pt; 2536 2537 struct { 2538 uint8_t port_name[8]; 2539 } gpn_id; 2540 2541 struct { 2542 uint8_t node_name[8]; 2543 } gnn_id; 2544 2545 struct { 2546 uint8_t fc4_types[32]; 2547 } gft_id; 2548 2549 struct { 2550 uint32_t entry_count; 2551 uint8_t port_name[8]; 2552 struct ct_fdmi_hba_attributes attrs; 2553 } ghat; 2554 2555 struct { 2556 uint8_t port_name[8]; 2557 } gfpn_id; 2558 2559 struct { 2560 uint16_t speeds; 2561 uint16_t speed; 2562 } gpsc; 2563 2564 #define GFF_FCP_SCSI_OFFSET 7 2565 struct { 2566 uint8_t fc4_features[128]; 2567 } gff_id; 2568 } rsp; 2569 }; 2570 2571 struct ct_sns_pkt { 2572 union { 2573 struct ct_sns_req req; 2574 struct ct_sns_rsp rsp; 2575 } p; 2576 }; 2577 2578 /* 2579 * SNS command structures -- for 2200 compatibility. 2580 */ 2581 #define RFT_ID_SNS_SCMD_LEN 22 2582 #define RFT_ID_SNS_CMD_SIZE 60 2583 #define RFT_ID_SNS_DATA_SIZE 16 2584 2585 #define RNN_ID_SNS_SCMD_LEN 10 2586 #define RNN_ID_SNS_CMD_SIZE 36 2587 #define RNN_ID_SNS_DATA_SIZE 16 2588 2589 #define GA_NXT_SNS_SCMD_LEN 6 2590 #define GA_NXT_SNS_CMD_SIZE 28 2591 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2592 2593 #define GID_PT_SNS_SCMD_LEN 6 2594 #define GID_PT_SNS_CMD_SIZE 28 2595 /* 2596 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2597 * adapters. 2598 */ 2599 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2600 2601 #define GPN_ID_SNS_SCMD_LEN 6 2602 #define GPN_ID_SNS_CMD_SIZE 28 2603 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2604 2605 #define GNN_ID_SNS_SCMD_LEN 6 2606 #define GNN_ID_SNS_CMD_SIZE 28 2607 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2608 2609 struct sns_cmd_pkt { 2610 union { 2611 struct { 2612 uint16_t buffer_length; 2613 uint16_t reserved_1; 2614 uint32_t buffer_address[2]; 2615 uint16_t subcommand_length; 2616 uint16_t reserved_2; 2617 uint16_t subcommand; 2618 uint16_t size; 2619 uint32_t reserved_3; 2620 uint8_t param[36]; 2621 } cmd; 2622 2623 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2624 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2625 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2626 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2627 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2628 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2629 } p; 2630 }; 2631 2632 struct fw_blob { 2633 char *name; 2634 uint32_t segs[4]; 2635 const struct firmware *fw; 2636 }; 2637 2638 /* Return data from MBC_GET_ID_LIST call. */ 2639 struct gid_list_info { 2640 uint8_t al_pa; 2641 uint8_t area; 2642 uint8_t domain; 2643 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2644 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2645 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2646 }; 2647 2648 /* NPIV */ 2649 typedef struct vport_info { 2650 uint8_t port_name[WWN_SIZE]; 2651 uint8_t node_name[WWN_SIZE]; 2652 int vp_id; 2653 uint16_t loop_id; 2654 unsigned long host_no; 2655 uint8_t port_id[3]; 2656 int loop_state; 2657 } vport_info_t; 2658 2659 typedef struct vport_params { 2660 uint8_t port_name[WWN_SIZE]; 2661 uint8_t node_name[WWN_SIZE]; 2662 uint32_t options; 2663 #define VP_OPTS_RETRY_ENABLE BIT_0 2664 #define VP_OPTS_VP_DISABLE BIT_1 2665 } vport_params_t; 2666 2667 /* NPIV - return codes of VP create and modify */ 2668 #define VP_RET_CODE_OK 0 2669 #define VP_RET_CODE_FATAL 1 2670 #define VP_RET_CODE_WRONG_ID 2 2671 #define VP_RET_CODE_WWPN 3 2672 #define VP_RET_CODE_RESOURCES 4 2673 #define VP_RET_CODE_NO_MEM 5 2674 #define VP_RET_CODE_NOT_FOUND 6 2675 2676 struct qla_hw_data; 2677 struct rsp_que; 2678 /* 2679 * ISP operations 2680 */ 2681 struct isp_operations { 2682 2683 int (*pci_config) (struct scsi_qla_host *); 2684 void (*reset_chip) (struct scsi_qla_host *); 2685 int (*chip_diag) (struct scsi_qla_host *); 2686 void (*config_rings) (struct scsi_qla_host *); 2687 void (*reset_adapter) (struct scsi_qla_host *); 2688 int (*nvram_config) (struct scsi_qla_host *); 2689 void (*update_fw_options) (struct scsi_qla_host *); 2690 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2691 2692 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2693 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 2694 2695 irq_handler_t intr_handler; 2696 void (*enable_intrs) (struct qla_hw_data *); 2697 void (*disable_intrs) (struct qla_hw_data *); 2698 2699 int (*abort_command) (srb_t *); 2700 int (*target_reset) (struct fc_port *, uint64_t, int); 2701 int (*lun_reset) (struct fc_port *, uint64_t, int); 2702 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2703 uint8_t, uint8_t, uint16_t *, uint8_t); 2704 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2705 uint8_t, uint8_t); 2706 2707 uint16_t (*calc_req_entries) (uint16_t); 2708 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2709 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2710 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2711 uint32_t); 2712 2713 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2714 uint32_t, uint32_t); 2715 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2716 uint32_t); 2717 2718 void (*fw_dump) (struct scsi_qla_host *, int); 2719 2720 int (*beacon_on) (struct scsi_qla_host *); 2721 int (*beacon_off) (struct scsi_qla_host *); 2722 void (*beacon_blink) (struct scsi_qla_host *); 2723 2724 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2725 uint32_t, uint32_t); 2726 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2727 uint32_t); 2728 2729 int (*get_flash_version) (struct scsi_qla_host *, void *); 2730 int (*start_scsi) (srb_t *); 2731 int (*abort_isp) (struct scsi_qla_host *); 2732 int (*iospace_config)(struct qla_hw_data*); 2733 int (*initialize_adapter)(struct scsi_qla_host *); 2734 }; 2735 2736 /* MSI-X Support *************************************************************/ 2737 2738 #define QLA_MSIX_CHIP_REV_24XX 3 2739 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2740 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2741 2742 #define QLA_MSIX_DEFAULT 0x00 2743 #define QLA_MSIX_RSP_Q 0x01 2744 2745 #define QLA_MIDX_DEFAULT 0 2746 #define QLA_MIDX_RSP_Q 1 2747 #define QLA_PCI_MSIX_CONTROL 0xa2 2748 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2749 2750 struct scsi_qla_host; 2751 2752 2753 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 2754 2755 struct qla_msix_entry { 2756 int have_irq; 2757 uint32_t vector; 2758 uint16_t entry; 2759 struct rsp_que *rsp; 2760 struct irq_affinity_notify irq_notify; 2761 int cpuid; 2762 }; 2763 2764 #define WATCH_INTERVAL 1 /* number of seconds */ 2765 2766 /* Work events. */ 2767 enum qla_work_type { 2768 QLA_EVT_AEN, 2769 QLA_EVT_IDC_ACK, 2770 QLA_EVT_ASYNC_LOGIN, 2771 QLA_EVT_ASYNC_LOGIN_DONE, 2772 QLA_EVT_ASYNC_LOGOUT, 2773 QLA_EVT_ASYNC_LOGOUT_DONE, 2774 QLA_EVT_ASYNC_ADISC, 2775 QLA_EVT_ASYNC_ADISC_DONE, 2776 QLA_EVT_UEVENT, 2777 QLA_EVT_AENFX, 2778 }; 2779 2780 2781 struct qla_work_evt { 2782 struct list_head list; 2783 enum qla_work_type type; 2784 u32 flags; 2785 #define QLA_EVT_FLAG_FREE 0x1 2786 2787 union { 2788 struct { 2789 enum fc_host_event_code code; 2790 u32 data; 2791 } aen; 2792 struct { 2793 #define QLA_IDC_ACK_REGS 7 2794 uint16_t mb[QLA_IDC_ACK_REGS]; 2795 } idc_ack; 2796 struct { 2797 struct fc_port *fcport; 2798 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2799 u16 data[2]; 2800 } logio; 2801 struct { 2802 u32 code; 2803 #define QLA_UEVENT_CODE_FW_DUMP 0 2804 } uevent; 2805 struct { 2806 uint32_t evtcode; 2807 uint32_t mbx[8]; 2808 uint32_t count; 2809 } aenfx; 2810 struct { 2811 srb_t *sp; 2812 } iosb; 2813 } u; 2814 }; 2815 2816 struct qla_chip_state_84xx { 2817 struct list_head list; 2818 struct kref kref; 2819 2820 void *bus; 2821 spinlock_t access_lock; 2822 struct mutex fw_update_mutex; 2823 uint32_t fw_update; 2824 uint32_t op_fw_version; 2825 uint32_t op_fw_size; 2826 uint32_t op_fw_seq_size; 2827 uint32_t diag_fw_version; 2828 uint32_t gold_fw_version; 2829 }; 2830 2831 struct qla_statistics { 2832 uint32_t total_isp_aborts; 2833 uint64_t input_bytes; 2834 uint64_t output_bytes; 2835 uint64_t input_requests; 2836 uint64_t output_requests; 2837 uint32_t control_requests; 2838 2839 uint64_t jiffies_at_last_reset; 2840 uint32_t stat_max_pend_cmds; 2841 uint32_t stat_max_qfull_cmds_alloc; 2842 uint32_t stat_max_qfull_cmds_dropped; 2843 }; 2844 2845 struct bidi_statistics { 2846 unsigned long long io_count; 2847 unsigned long long transfer_bytes; 2848 }; 2849 2850 /* Multi queue support */ 2851 #define MBC_INITIALIZE_MULTIQ 0x1f 2852 #define QLA_QUE_PAGE 0X1000 2853 #define QLA_MQ_SIZE 32 2854 #define QLA_MAX_QUEUES 256 2855 #define ISP_QUE_REG(ha, id) \ 2856 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 2857 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 2858 ((void __iomem *)ha->iobase)) 2859 #define QLA_REQ_QUE_ID(tag) \ 2860 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2861 #define QLA_DEFAULT_QUE_QOS 5 2862 #define QLA_PRECONFIG_VPORTS 32 2863 #define QLA_MAX_VPORTS_QLA24XX 128 2864 #define QLA_MAX_VPORTS_QLA25XX 256 2865 /* Response queue data structure */ 2866 struct rsp_que { 2867 dma_addr_t dma; 2868 response_t *ring; 2869 response_t *ring_ptr; 2870 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2871 uint32_t __iomem *rsp_q_out; 2872 uint16_t ring_index; 2873 uint16_t out_ptr; 2874 uint16_t *in_ptr; /* queue shadow in index */ 2875 uint16_t length; 2876 uint16_t options; 2877 uint16_t rid; 2878 uint16_t id; 2879 uint16_t vp_idx; 2880 struct qla_hw_data *hw; 2881 struct qla_msix_entry *msix; 2882 struct req_que *req; 2883 srb_t *status_srb; /* status continuation entry */ 2884 struct work_struct q_work; 2885 2886 dma_addr_t dma_fx00; 2887 response_t *ring_fx00; 2888 uint16_t length_fx00; 2889 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2890 }; 2891 2892 /* Request queue data structure */ 2893 struct req_que { 2894 dma_addr_t dma; 2895 request_t *ring; 2896 request_t *ring_ptr; 2897 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2898 uint32_t __iomem *req_q_out; 2899 uint16_t ring_index; 2900 uint16_t in_ptr; 2901 uint16_t *out_ptr; /* queue shadow out index */ 2902 uint16_t cnt; 2903 uint16_t length; 2904 uint16_t options; 2905 uint16_t rid; 2906 uint16_t id; 2907 uint16_t qos; 2908 uint16_t vp_idx; 2909 struct rsp_que *rsp; 2910 srb_t **outstanding_cmds; 2911 uint32_t current_outstanding_cmd; 2912 uint16_t num_outstanding_cmds; 2913 int max_q_depth; 2914 2915 dma_addr_t dma_fx00; 2916 request_t *ring_fx00; 2917 uint16_t length_fx00; 2918 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2919 }; 2920 2921 /* Place holder for FW buffer parameters */ 2922 struct qlfc_fw { 2923 void *fw_buf; 2924 dma_addr_t fw_dma; 2925 uint32_t len; 2926 }; 2927 2928 struct scsi_qlt_host { 2929 void *target_lport_ptr; 2930 struct mutex tgt_mutex; 2931 struct mutex tgt_host_action_mutex; 2932 struct qla_tgt *qla_tgt; 2933 }; 2934 2935 struct qlt_hw_data { 2936 /* Protected by hw lock */ 2937 uint32_t enable_class_2:1; 2938 uint32_t enable_explicit_conf:1; 2939 uint32_t ini_mode_force_reverse:1; 2940 uint32_t node_name_set:1; 2941 2942 dma_addr_t atio_dma; /* Physical address. */ 2943 struct atio *atio_ring; /* Base virtual address */ 2944 struct atio *atio_ring_ptr; /* Current address. */ 2945 uint16_t atio_ring_index; /* Current index. */ 2946 uint16_t atio_q_length; 2947 uint32_t __iomem *atio_q_in; 2948 uint32_t __iomem *atio_q_out; 2949 2950 struct qla_tgt_func_tmpl *tgt_ops; 2951 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2952 uint16_t current_handle; 2953 2954 struct qla_tgt_vp_map *tgt_vp_map; 2955 2956 int saved_set; 2957 uint16_t saved_exchange_count; 2958 uint32_t saved_firmware_options_1; 2959 uint32_t saved_firmware_options_2; 2960 uint32_t saved_firmware_options_3; 2961 uint8_t saved_firmware_options[2]; 2962 uint8_t saved_add_firmware_options[2]; 2963 2964 uint8_t tgt_node_name[WWN_SIZE]; 2965 2966 struct dentry *dfs_tgt_sess; 2967 struct list_head q_full_list; 2968 uint32_t num_pend_cmds; 2969 uint32_t num_qfull_cmds_alloc; 2970 uint32_t num_qfull_cmds_dropped; 2971 spinlock_t q_full_lock; 2972 uint32_t leak_exchg_thresh_hold; 2973 spinlock_t sess_lock; 2974 int rspq_vector_cpuid; 2975 spinlock_t atio_lock ____cacheline_aligned; 2976 }; 2977 2978 #define MAX_QFULL_CMDS_ALLOC 8192 2979 #define Q_FULL_THRESH_HOLD_PERCENT 90 2980 #define Q_FULL_THRESH_HOLD(ha) \ 2981 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 2982 2983 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 2984 2985 /* 2986 * Qlogic host adapter specific data structure. 2987 */ 2988 struct qla_hw_data { 2989 struct pci_dev *pdev; 2990 /* SRB cache. */ 2991 #define SRB_MIN_REQ 128 2992 mempool_t *srb_mempool; 2993 2994 volatile struct { 2995 uint32_t mbox_int :1; 2996 uint32_t mbox_busy :1; 2997 uint32_t disable_risc_code_load :1; 2998 uint32_t enable_64bit_addressing :1; 2999 uint32_t enable_lip_reset :1; 3000 uint32_t enable_target_reset :1; 3001 uint32_t enable_lip_full_login :1; 3002 uint32_t enable_led_scheme :1; 3003 3004 uint32_t msi_enabled :1; 3005 uint32_t msix_enabled :1; 3006 uint32_t disable_serdes :1; 3007 uint32_t gpsc_supported :1; 3008 uint32_t npiv_supported :1; 3009 uint32_t pci_channel_io_perm_failure :1; 3010 uint32_t fce_enabled :1; 3011 uint32_t fac_supported :1; 3012 3013 uint32_t chip_reset_done :1; 3014 uint32_t running_gold_fw :1; 3015 uint32_t eeh_busy :1; 3016 uint32_t cpu_affinity_enabled :1; 3017 uint32_t disable_msix_handshake :1; 3018 uint32_t fcp_prio_enabled :1; 3019 uint32_t isp82xx_fw_hung:1; 3020 uint32_t nic_core_hung:1; 3021 3022 uint32_t quiesce_owner:1; 3023 uint32_t nic_core_reset_hdlr_active:1; 3024 uint32_t nic_core_reset_owner:1; 3025 uint32_t isp82xx_no_md_cap:1; 3026 uint32_t host_shutting_down:1; 3027 uint32_t idc_compl_status:1; 3028 uint32_t mr_reset_hdlr_active:1; 3029 uint32_t mr_intr_valid:1; 3030 3031 uint32_t fawwpn_enabled:1; 3032 uint32_t exlogins_enabled:1; 3033 uint32_t exchoffld_enabled:1; 3034 /* 35 bits */ 3035 } flags; 3036 3037 /* This spinlock is used to protect "io transactions", you must 3038 * acquire it before doing any IO to the card, eg with RD_REG*() and 3039 * WRT_REG*() for the duration of your entire commandtransaction. 3040 * 3041 * This spinlock is of lower priority than the io request lock. 3042 */ 3043 3044 spinlock_t hardware_lock ____cacheline_aligned; 3045 int bars; 3046 int mem_only; 3047 device_reg_t *iobase; /* Base I/O address */ 3048 resource_size_t pio_address; 3049 3050 #define MIN_IOBASE_LEN 0x100 3051 dma_addr_t bar0_hdl; 3052 3053 void __iomem *cregbase; 3054 dma_addr_t bar2_hdl; 3055 #define BAR0_LEN_FX00 (1024 * 1024) 3056 #define BAR2_LEN_FX00 (128 * 1024) 3057 3058 uint32_t rqstq_intr_code; 3059 uint32_t mbx_intr_code; 3060 uint32_t req_que_len; 3061 uint32_t rsp_que_len; 3062 uint32_t req_que_off; 3063 uint32_t rsp_que_off; 3064 3065 /* Multi queue data structs */ 3066 device_reg_t *mqiobase; 3067 device_reg_t *msixbase; 3068 uint16_t msix_count; 3069 uint8_t mqenable; 3070 struct req_que **req_q_map; 3071 struct rsp_que **rsp_q_map; 3072 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3073 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3074 uint8_t max_req_queues; 3075 uint8_t max_rsp_queues; 3076 struct qla_npiv_entry *npiv_info; 3077 uint16_t nvram_npiv_size; 3078 3079 uint16_t switch_cap; 3080 #define FLOGI_SEQ_DEL BIT_8 3081 #define FLOGI_MID_SUPPORT BIT_10 3082 #define FLOGI_VSAN_SUPPORT BIT_12 3083 #define FLOGI_SP_SUPPORT BIT_13 3084 3085 uint8_t port_no; /* Physical port of adapter */ 3086 3087 /* Timeout timers. */ 3088 uint8_t loop_down_abort_time; /* port down timer */ 3089 atomic_t loop_down_timer; /* loop down timer */ 3090 uint8_t link_down_timeout; /* link down timeout */ 3091 uint16_t max_loop_id; 3092 uint16_t max_fibre_devices; /* Maximum number of targets */ 3093 3094 uint16_t fb_rev; 3095 uint16_t min_external_loopid; /* First external loop Id */ 3096 3097 #define PORT_SPEED_UNKNOWN 0xFFFF 3098 #define PORT_SPEED_1GB 0x00 3099 #define PORT_SPEED_2GB 0x01 3100 #define PORT_SPEED_4GB 0x03 3101 #define PORT_SPEED_8GB 0x04 3102 #define PORT_SPEED_16GB 0x05 3103 #define PORT_SPEED_32GB 0x06 3104 #define PORT_SPEED_10GB 0x13 3105 uint16_t link_data_rate; /* F/W operating speed */ 3106 3107 uint8_t current_topology; 3108 uint8_t prev_topology; 3109 #define ISP_CFG_NL 1 3110 #define ISP_CFG_N 2 3111 #define ISP_CFG_FL 4 3112 #define ISP_CFG_F 8 3113 3114 uint8_t operating_mode; /* F/W operating mode */ 3115 #define LOOP 0 3116 #define P2P 1 3117 #define LOOP_P2P 2 3118 #define P2P_LOOP 3 3119 uint8_t interrupts_on; 3120 uint32_t isp_abort_cnt; 3121 3122 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3123 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3124 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3125 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3126 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3127 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3128 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3129 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3130 3131 uint32_t device_type; 3132 #define DT_ISP2100 BIT_0 3133 #define DT_ISP2200 BIT_1 3134 #define DT_ISP2300 BIT_2 3135 #define DT_ISP2312 BIT_3 3136 #define DT_ISP2322 BIT_4 3137 #define DT_ISP6312 BIT_5 3138 #define DT_ISP6322 BIT_6 3139 #define DT_ISP2422 BIT_7 3140 #define DT_ISP2432 BIT_8 3141 #define DT_ISP5422 BIT_9 3142 #define DT_ISP5432 BIT_10 3143 #define DT_ISP2532 BIT_11 3144 #define DT_ISP8432 BIT_12 3145 #define DT_ISP8001 BIT_13 3146 #define DT_ISP8021 BIT_14 3147 #define DT_ISP2031 BIT_15 3148 #define DT_ISP8031 BIT_16 3149 #define DT_ISPFX00 BIT_17 3150 #define DT_ISP8044 BIT_18 3151 #define DT_ISP2071 BIT_19 3152 #define DT_ISP2271 BIT_20 3153 #define DT_ISP2261 BIT_21 3154 #define DT_ISP_LAST (DT_ISP2261 << 1) 3155 3156 #define DT_T10_PI BIT_25 3157 #define DT_IIDMA BIT_26 3158 #define DT_FWI2 BIT_27 3159 #define DT_ZIO_SUPPORTED BIT_28 3160 #define DT_OEM_001 BIT_29 3161 #define DT_ISP2200A BIT_30 3162 #define DT_EXTENDED_IDS BIT_31 3163 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 3164 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3165 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3166 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3167 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3168 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3169 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3170 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3171 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3172 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3173 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3174 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3175 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3176 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3177 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3178 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3179 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3180 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3181 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3182 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3183 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3184 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3185 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3186 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3187 3188 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3189 IS_QLA6312(ha) || IS_QLA6322(ha)) 3190 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3191 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3192 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3193 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3194 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3195 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3196 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3197 IS_QLA84XX(ha)) 3198 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3199 IS_QLA8031(ha) || IS_QLA8044(ha)) 3200 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3201 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3202 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3203 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3204 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3205 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3206 IS_QLA27XX(ha)) 3207 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3208 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3209 IS_QLA27XX(ha)) 3210 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3211 IS_QLA27XX(ha)) 3212 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3213 3214 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3215 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3216 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3217 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3218 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3219 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3220 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3221 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3222 IS_QLA27XX(ha)) 3223 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3224 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3225 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3226 ((ha)->fw_attributes_ext[0] & BIT_0)) 3227 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3228 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3229 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3230 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3231 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3232 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3233 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3234 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3235 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3236 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3237 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3238 3239 /* HBA serial number */ 3240 uint8_t serial0; 3241 uint8_t serial1; 3242 uint8_t serial2; 3243 3244 /* NVRAM configuration data */ 3245 #define MAX_NVRAM_SIZE 4096 3246 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3247 uint16_t nvram_size; 3248 uint16_t nvram_base; 3249 void *nvram; 3250 uint16_t vpd_size; 3251 uint16_t vpd_base; 3252 void *vpd; 3253 3254 uint16_t loop_reset_delay; 3255 uint8_t retry_count; 3256 uint8_t login_timeout; 3257 uint16_t r_a_tov; 3258 int port_down_retry_count; 3259 uint8_t mbx_count; 3260 uint8_t aen_mbx_count; 3261 3262 uint32_t login_retry_count; 3263 /* SNS command interfaces. */ 3264 ms_iocb_entry_t *ms_iocb; 3265 dma_addr_t ms_iocb_dma; 3266 struct ct_sns_pkt *ct_sns; 3267 dma_addr_t ct_sns_dma; 3268 /* SNS command interfaces for 2200. */ 3269 struct sns_cmd_pkt *sns_cmd; 3270 dma_addr_t sns_cmd_dma; 3271 3272 #define SFP_DEV_SIZE 256 3273 #define SFP_BLOCK_SIZE 64 3274 void *sfp_data; 3275 dma_addr_t sfp_data_dma; 3276 3277 #define XGMAC_DATA_SIZE 4096 3278 void *xgmac_data; 3279 dma_addr_t xgmac_data_dma; 3280 3281 #define DCBX_TLV_DATA_SIZE 4096 3282 void *dcbx_tlv; 3283 dma_addr_t dcbx_tlv_dma; 3284 3285 struct task_struct *dpc_thread; 3286 uint8_t dpc_active; /* DPC routine is active */ 3287 3288 dma_addr_t gid_list_dma; 3289 struct gid_list_info *gid_list; 3290 int gid_list_info_size; 3291 3292 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3293 #define DMA_POOL_SIZE 256 3294 struct dma_pool *s_dma_pool; 3295 3296 dma_addr_t init_cb_dma; 3297 init_cb_t *init_cb; 3298 int init_cb_size; 3299 dma_addr_t ex_init_cb_dma; 3300 struct ex_init_cb_81xx *ex_init_cb; 3301 3302 void *async_pd; 3303 dma_addr_t async_pd_dma; 3304 3305 #define ENABLE_EXTENDED_LOGIN BIT_7 3306 3307 /* Extended Logins */ 3308 void *exlogin_buf; 3309 dma_addr_t exlogin_buf_dma; 3310 int exlogin_size; 3311 3312 #define ENABLE_EXCHANGE_OFFLD BIT_2 3313 3314 /* Exchange Offload */ 3315 void *exchoffld_buf; 3316 dma_addr_t exchoffld_buf_dma; 3317 int exchoffld_size; 3318 int exchoffld_count; 3319 3320 void *swl; 3321 3322 /* These are used by mailbox operations. */ 3323 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3324 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3325 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3326 3327 mbx_cmd_t *mcp; 3328 struct mbx_cmd_32 *mcp32; 3329 3330 unsigned long mbx_cmd_flags; 3331 #define MBX_INTERRUPT 1 3332 #define MBX_INTR_WAIT 2 3333 #define MBX_UPDATE_FLASH_ACTIVE 3 3334 3335 struct mutex vport_lock; /* Virtual port synchronization */ 3336 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3337 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3338 struct completion mbx_intr_comp; /* Used for completion notification */ 3339 struct completion dcbx_comp; /* For set port config notification */ 3340 struct completion lb_portup_comp; /* Used to wait for link up during 3341 * loopback */ 3342 #define DCBX_COMP_TIMEOUT 20 3343 #define LB_PORTUP_COMP_TIMEOUT 10 3344 3345 int notify_dcbx_comp; 3346 int notify_lb_portup_comp; 3347 struct mutex selflogin_lock; 3348 3349 /* Basic firmware related information. */ 3350 uint16_t fw_major_version; 3351 uint16_t fw_minor_version; 3352 uint16_t fw_subminor_version; 3353 uint16_t fw_attributes; 3354 uint16_t fw_attributes_h; 3355 uint16_t fw_attributes_ext[2]; 3356 uint32_t fw_memory_size; 3357 uint32_t fw_transfer_size; 3358 uint32_t fw_srisc_address; 3359 #define RISC_START_ADDRESS_2100 0x1000 3360 #define RISC_START_ADDRESS_2300 0x800 3361 #define RISC_START_ADDRESS_2400 0x100000 3362 3363 uint16_t orig_fw_tgt_xcb_count; 3364 uint16_t cur_fw_tgt_xcb_count; 3365 uint16_t orig_fw_xcb_count; 3366 uint16_t cur_fw_xcb_count; 3367 uint16_t orig_fw_iocb_count; 3368 uint16_t cur_fw_iocb_count; 3369 uint16_t fw_max_fcf_count; 3370 3371 uint32_t fw_shared_ram_start; 3372 uint32_t fw_shared_ram_end; 3373 3374 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3375 uint8_t fw_seriallink_options[4]; 3376 uint16_t fw_seriallink_options24[4]; 3377 3378 uint8_t mpi_version[3]; 3379 uint32_t mpi_capabilities; 3380 uint8_t phy_version[3]; 3381 uint8_t pep_version[3]; 3382 3383 /* Firmware dump template */ 3384 void *fw_dump_template; 3385 uint32_t fw_dump_template_len; 3386 /* Firmware dump information. */ 3387 struct qla2xxx_fw_dump *fw_dump; 3388 uint32_t fw_dump_len; 3389 int fw_dumped; 3390 unsigned long fw_dump_cap_flags; 3391 #define RISC_PAUSE_CMPL 0 3392 #define DMA_SHUTDOWN_CMPL 1 3393 #define ISP_RESET_CMPL 2 3394 #define RISC_RDY_AFT_RESET 3 3395 #define RISC_SRAM_DUMP_CMPL 4 3396 #define RISC_EXT_MEM_DUMP_CMPL 5 3397 #define ISP_MBX_RDY 6 3398 #define ISP_SOFT_RESET_CMPL 7 3399 int fw_dump_reading; 3400 int prev_minidump_failed; 3401 dma_addr_t eft_dma; 3402 void *eft; 3403 /* Current size of mctp dump is 0x086064 bytes */ 3404 #define MCTP_DUMP_SIZE 0x086064 3405 dma_addr_t mctp_dump_dma; 3406 void *mctp_dump; 3407 int mctp_dumped; 3408 int mctp_dump_reading; 3409 uint32_t chain_offset; 3410 struct dentry *dfs_dir; 3411 struct dentry *dfs_fce; 3412 struct dentry *dfs_tgt_counters; 3413 struct dentry *dfs_fw_resource_cnt; 3414 3415 dma_addr_t fce_dma; 3416 void *fce; 3417 uint32_t fce_bufs; 3418 uint16_t fce_mb[8]; 3419 uint64_t fce_wr, fce_rd; 3420 struct mutex fce_mutex; 3421 3422 uint32_t pci_attr; 3423 uint16_t chip_revision; 3424 3425 uint16_t product_id[4]; 3426 3427 uint8_t model_number[16+1]; 3428 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3429 char model_desc[80]; 3430 uint8_t adapter_id[16+1]; 3431 3432 /* Option ROM information. */ 3433 char *optrom_buffer; 3434 uint32_t optrom_size; 3435 int optrom_state; 3436 #define QLA_SWAITING 0 3437 #define QLA_SREADING 1 3438 #define QLA_SWRITING 2 3439 uint32_t optrom_region_start; 3440 uint32_t optrom_region_size; 3441 struct mutex optrom_mutex; 3442 3443 /* PCI expansion ROM image information. */ 3444 #define ROM_CODE_TYPE_BIOS 0 3445 #define ROM_CODE_TYPE_FCODE 1 3446 #define ROM_CODE_TYPE_EFI 3 3447 uint8_t bios_revision[2]; 3448 uint8_t efi_revision[2]; 3449 uint8_t fcode_revision[16]; 3450 uint32_t fw_revision[4]; 3451 3452 uint32_t gold_fw_version[4]; 3453 3454 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3455 uint32_t flash_conf_off; 3456 uint32_t flash_data_off; 3457 uint32_t nvram_conf_off; 3458 uint32_t nvram_data_off; 3459 3460 uint32_t fdt_wrt_disable; 3461 uint32_t fdt_wrt_enable; 3462 uint32_t fdt_erase_cmd; 3463 uint32_t fdt_block_size; 3464 uint32_t fdt_unprotect_sec_cmd; 3465 uint32_t fdt_protect_sec_cmd; 3466 uint32_t fdt_wrt_sts_reg_cmd; 3467 3468 uint32_t flt_region_flt; 3469 uint32_t flt_region_fdt; 3470 uint32_t flt_region_boot; 3471 uint32_t flt_region_boot_sec; 3472 uint32_t flt_region_fw; 3473 uint32_t flt_region_fw_sec; 3474 uint32_t flt_region_vpd_nvram; 3475 uint32_t flt_region_vpd; 3476 uint32_t flt_region_vpd_sec; 3477 uint32_t flt_region_nvram; 3478 uint32_t flt_region_npiv_conf; 3479 uint32_t flt_region_gold_fw; 3480 uint32_t flt_region_fcp_prio; 3481 uint32_t flt_region_bootload; 3482 uint32_t flt_region_img_status_pri; 3483 uint32_t flt_region_img_status_sec; 3484 uint8_t active_image; 3485 3486 /* Needed for BEACON */ 3487 uint16_t beacon_blink_led; 3488 uint8_t beacon_color_state; 3489 #define QLA_LED_GRN_ON 0x01 3490 #define QLA_LED_YLW_ON 0x02 3491 #define QLA_LED_ABR_ON 0x04 3492 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3493 /* ISP2322: red, green, amber. */ 3494 uint16_t zio_mode; 3495 uint16_t zio_timer; 3496 3497 struct qla_msix_entry *msix_entries; 3498 3499 struct list_head vp_list; /* list of VP */ 3500 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3501 sizeof(unsigned long)]; 3502 uint16_t num_vhosts; /* number of vports created */ 3503 uint16_t num_vsans; /* number of vsan created */ 3504 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3505 int cur_vport_count; 3506 3507 struct qla_chip_state_84xx *cs84xx; 3508 struct qla_statistics qla_stats; 3509 struct isp_operations *isp_ops; 3510 struct workqueue_struct *wq; 3511 struct qlfc_fw fw_buf; 3512 3513 /* FCP_CMND priority support */ 3514 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3515 3516 struct dma_pool *dl_dma_pool; 3517 #define DSD_LIST_DMA_POOL_SIZE 512 3518 3519 struct dma_pool *fcp_cmnd_dma_pool; 3520 mempool_t *ctx_mempool; 3521 #define FCP_CMND_DMA_POOL_SIZE 512 3522 3523 void __iomem *nx_pcibase; /* Base I/O address */ 3524 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 3525 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 3526 3527 uint32_t crb_win; 3528 uint32_t curr_window; 3529 uint32_t ddr_mn_window; 3530 unsigned long mn_win_crb; 3531 unsigned long ms_win_crb; 3532 int qdr_sn_window; 3533 uint32_t fcoe_dev_init_timeout; 3534 uint32_t fcoe_reset_timeout; 3535 rwlock_t hw_lock; 3536 uint16_t portnum; /* port number */ 3537 int link_width; 3538 struct fw_blob *hablob; 3539 struct qla82xx_legacy_intr_set nx_legacy_intr; 3540 3541 uint16_t gbl_dsd_inuse; 3542 uint16_t gbl_dsd_avail; 3543 struct list_head gbl_dsd_list; 3544 #define NUM_DSD_CHAIN 4096 3545 3546 uint8_t fw_type; 3547 __le32 file_prd_off; /* File firmware product offset */ 3548 3549 uint32_t md_template_size; 3550 void *md_tmplt_hdr; 3551 dma_addr_t md_tmplt_hdr_dma; 3552 void *md_dump; 3553 uint32_t md_dump_size; 3554 3555 void *loop_id_map; 3556 3557 /* QLA83XX IDC specific fields */ 3558 uint32_t idc_audit_ts; 3559 uint32_t idc_extend_tmo; 3560 3561 /* DPC low-priority workqueue */ 3562 struct workqueue_struct *dpc_lp_wq; 3563 struct work_struct idc_aen; 3564 /* DPC high-priority workqueue */ 3565 struct workqueue_struct *dpc_hp_wq; 3566 struct work_struct nic_core_reset; 3567 struct work_struct idc_state_handler; 3568 struct work_struct nic_core_unrecoverable; 3569 struct work_struct board_disable; 3570 3571 struct mr_data_fx00 mr; 3572 uint32_t chip_reset; 3573 3574 struct qlt_hw_data tgt; 3575 int allow_cna_fw_dump; 3576 }; 3577 3578 struct qla_tgt_counters { 3579 uint64_t qla_core_sbt_cmd; 3580 uint64_t core_qla_que_buf; 3581 uint64_t qla_core_ret_ctio; 3582 uint64_t core_qla_snd_status; 3583 uint64_t qla_core_ret_sta_ctio; 3584 uint64_t core_qla_free_cmd; 3585 uint64_t num_q_full_sent; 3586 uint64_t num_alloc_iocb_failed; 3587 uint64_t num_term_xchg_sent; 3588 }; 3589 3590 /* 3591 * Qlogic scsi host structure 3592 */ 3593 typedef struct scsi_qla_host { 3594 struct list_head list; 3595 struct list_head vp_fcports; /* list of fcports */ 3596 struct list_head work_list; 3597 spinlock_t work_lock; 3598 3599 /* Commonly used flags and state information. */ 3600 struct Scsi_Host *host; 3601 unsigned long host_no; 3602 uint8_t host_str[16]; 3603 3604 volatile struct { 3605 uint32_t init_done :1; 3606 uint32_t online :1; 3607 uint32_t reset_active :1; 3608 3609 uint32_t management_server_logged_in :1; 3610 uint32_t process_response_queue :1; 3611 uint32_t difdix_supported:1; 3612 uint32_t delete_progress:1; 3613 3614 uint32_t fw_tgt_reported:1; 3615 uint32_t bbcr_enable:1; 3616 } flags; 3617 3618 atomic_t loop_state; 3619 #define LOOP_TIMEOUT 1 3620 #define LOOP_DOWN 2 3621 #define LOOP_UP 3 3622 #define LOOP_UPDATE 4 3623 #define LOOP_READY 5 3624 #define LOOP_DEAD 6 3625 3626 unsigned long dpc_flags; 3627 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3628 #define RESET_ACTIVE 1 3629 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3630 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3631 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3632 #define LOOP_RESYNC_ACTIVE 5 3633 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3634 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3635 #define RELOGIN_NEEDED 8 3636 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3637 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3638 #define BEACON_BLINK_NEEDED 11 3639 #define REGISTER_FDMI_NEEDED 12 3640 #define FCPORT_UPDATE_NEEDED 13 3641 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3642 #define UNLOADING 15 3643 #define NPIV_CONFIG_NEEDED 16 3644 #define ISP_UNRECOVERABLE 17 3645 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3646 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3647 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3648 #define SCR_PENDING 21 /* SCR in target mode */ 3649 #define PORT_UPDATE_NEEDED 22 3650 #define FX00_RESET_RECOVERY 23 3651 #define FX00_TARGET_SCAN 24 3652 #define FX00_CRITEMP_RECOVERY 25 3653 #define FX00_HOST_INFO_RESEND 26 3654 3655 unsigned long pci_flags; 3656 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 3657 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 3658 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 3659 3660 uint32_t device_flags; 3661 #define SWITCH_FOUND BIT_0 3662 #define DFLG_NO_CABLE BIT_1 3663 #define DFLG_DEV_FAILED BIT_5 3664 3665 /* ISP configuration data. */ 3666 uint16_t loop_id; /* Host adapter loop id */ 3667 uint16_t self_login_loop_id; /* host adapter loop id 3668 * get it on self login 3669 */ 3670 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3671 * no need of allocating it for 3672 * each command 3673 */ 3674 3675 port_id_t d_id; /* Host adapter port id */ 3676 uint8_t marker_needed; 3677 uint16_t mgmt_svr_loop_id; 3678 3679 3680 3681 /* Timeout timers. */ 3682 uint8_t loop_down_abort_time; /* port down timer */ 3683 atomic_t loop_down_timer; /* loop down timer */ 3684 uint8_t link_down_timeout; /* link down timeout */ 3685 3686 uint32_t timer_active; 3687 struct timer_list timer; 3688 3689 uint8_t node_name[WWN_SIZE]; 3690 uint8_t port_name[WWN_SIZE]; 3691 uint8_t fabric_node_name[WWN_SIZE]; 3692 3693 uint16_t fcoe_vlan_id; 3694 uint16_t fcoe_fcf_idx; 3695 uint8_t fcoe_vn_port_mac[6]; 3696 3697 /* list of commands waiting on workqueue */ 3698 struct list_head qla_cmd_list; 3699 struct list_head qla_sess_op_cmd_list; 3700 spinlock_t cmd_list_lock; 3701 3702 /* Counter to detect races between ELS and RSCN events */ 3703 atomic_t generation_tick; 3704 /* Time when global fcport update has been scheduled */ 3705 int total_fcport_update_gen; 3706 /* List of pending LOGOs, protected by tgt_mutex */ 3707 struct list_head logo_list; 3708 /* List of pending PLOGI acks, protected by hw lock */ 3709 struct list_head plogi_ack_list; 3710 3711 uint32_t vp_abort_cnt; 3712 3713 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3714 uint16_t vp_idx; /* vport ID */ 3715 3716 unsigned long vp_flags; 3717 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3718 #define VP_CREATE_NEEDED 1 3719 #define VP_BIND_NEEDED 2 3720 #define VP_DELETE_NEEDED 3 3721 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3722 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 3723 atomic_t vp_state; 3724 #define VP_OFFLINE 0 3725 #define VP_ACTIVE 1 3726 #define VP_FAILED 2 3727 // #define VP_DISABLE 3 3728 uint16_t vp_err_state; 3729 uint16_t vp_prev_err_state; 3730 #define VP_ERR_UNKWN 0 3731 #define VP_ERR_PORTDWN 1 3732 #define VP_ERR_FAB_UNSUPPORTED 2 3733 #define VP_ERR_FAB_NORESOURCES 3 3734 #define VP_ERR_FAB_LOGOUT 4 3735 #define VP_ERR_ADAP_NORESOURCES 5 3736 struct qla_hw_data *hw; 3737 struct scsi_qlt_host vha_tgt; 3738 struct req_que *req; 3739 int fw_heartbeat_counter; 3740 int seconds_since_last_heartbeat; 3741 struct fc_host_statistics fc_host_stat; 3742 struct qla_statistics qla_stats; 3743 struct bidi_statistics bidi_stats; 3744 3745 atomic_t vref_count; 3746 struct qla8044_reset_template reset_tmplt; 3747 struct qla_tgt_counters tgt_counters; 3748 uint16_t bbcr; 3749 } scsi_qla_host_t; 3750 3751 struct qla27xx_image_status { 3752 uint8_t image_status_mask; 3753 uint16_t generation_number; 3754 uint8_t reserved[3]; 3755 uint8_t ver_minor; 3756 uint8_t ver_major; 3757 uint32_t checksum; 3758 uint32_t signature; 3759 } __packed; 3760 3761 #define SET_VP_IDX 1 3762 #define SET_AL_PA 2 3763 #define RESET_VP_IDX 3 3764 #define RESET_AL_PA 4 3765 struct qla_tgt_vp_map { 3766 uint8_t idx; 3767 scsi_qla_host_t *vha; 3768 }; 3769 3770 /* 3771 * Macros to help code, maintain, etc. 3772 */ 3773 #define LOOP_TRANSITION(ha) \ 3774 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3775 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3776 atomic_read(&ha->loop_state) == LOOP_DOWN) 3777 3778 #define STATE_TRANSITION(ha) \ 3779 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3780 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3781 3782 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3783 atomic_inc(&__vha->vref_count); \ 3784 mb(); \ 3785 if (__vha->flags.delete_progress) { \ 3786 atomic_dec(&__vha->vref_count); \ 3787 __bail = 1; \ 3788 } else { \ 3789 __bail = 0; \ 3790 } \ 3791 } while (0) 3792 3793 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3794 atomic_dec(&__vha->vref_count); \ 3795 } while (0) 3796 3797 /* 3798 * qla2x00 local function return status codes 3799 */ 3800 #define MBS_MASK 0x3fff 3801 3802 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3803 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3804 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3805 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3806 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3807 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3808 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3809 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3810 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3811 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3812 3813 #define QLA_FUNCTION_TIMEOUT 0x100 3814 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3815 #define QLA_FUNCTION_FAILED 0x102 3816 #define QLA_MEMORY_ALLOC_FAILED 0x103 3817 #define QLA_LOCK_TIMEOUT 0x104 3818 #define QLA_ABORTED 0x105 3819 #define QLA_SUSPENDED 0x106 3820 #define QLA_BUSY 0x107 3821 #define QLA_ALREADY_REGISTERED 0x109 3822 3823 #define NVRAM_DELAY() udelay(10) 3824 3825 /* 3826 * Flash support definitions 3827 */ 3828 #define OPTROM_SIZE_2300 0x20000 3829 #define OPTROM_SIZE_2322 0x100000 3830 #define OPTROM_SIZE_24XX 0x100000 3831 #define OPTROM_SIZE_25XX 0x200000 3832 #define OPTROM_SIZE_81XX 0x400000 3833 #define OPTROM_SIZE_82XX 0x800000 3834 #define OPTROM_SIZE_83XX 0x1000000 3835 3836 #define OPTROM_BURST_SIZE 0x1000 3837 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3838 3839 #define QLA_DSDS_PER_IOCB 37 3840 3841 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3842 3843 #define QLA_SG_ALL 1024 3844 3845 enum nexus_wait_type { 3846 WAIT_HOST = 0, 3847 WAIT_TARGET, 3848 WAIT_LUN, 3849 }; 3850 3851 #include "qla_gbl.h" 3852 #include "qla_dbg.h" 3853 #include "qla_inline.h" 3854 #endif 3855