1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 PM8001_FAIL_DBG(pm8001_ha, 62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" 63 " = 0x%x\n", reg_val)); 64 return -1; 65 } 66 return 0; 67 } 68 69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 70 const void *destination, 71 u32 dw_count, u32 bus_base_number) 72 { 73 u32 index, value, offset; 74 u32 *destination1; 75 destination1 = (u32 *)destination; 76 77 for (index = 0; index < dw_count; index += 4, destination1++) { 78 offset = (soffset + index / 4); 79 if (offset < (64 * 1024)) { 80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 81 *destination1 = cpu_to_le32(value); 82 } 83 } 84 return; 85 } 86 87 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 88 struct device_attribute *attr, char *buf) 89 { 90 struct Scsi_Host *shost = class_to_shost(cdev); 91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 94 u32 accum_len , reg_val, index, *temp; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 99 pm8001_ha->forensic_info.data_buf.direct_data = buf; 100 if (pm8001_ha->chip_id == chip_8001) { 101 pm8001_ha->forensic_info.data_buf.direct_data += 102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 103 "Not supported for SPC controller"); 104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 105 (char *)buf; 106 } 107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 108 PM8001_IO_DBG(pm8001_ha, 109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n")); 110 direct_data = (u8 *)fatal_error_data; 111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 113 pm8001_ha->forensic_info.data_buf.read_len = 0; 114 115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 116 117 /* start to get data */ 118 /* Program the MEMBASE II Shifting Register with 0x00.*/ 119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 120 pm8001_ha->fatal_forensic_shift_offset); 121 pm8001_ha->forensic_last_offset = 0; 122 pm8001_ha->forensic_fatal_step = 0; 123 pm8001_ha->fatal_bar_loc = 0; 124 } 125 126 /* Read until accum_len is retrived */ 127 accum_len = pm8001_mr32(fatal_table_address, 128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n", 130 accum_len)); 131 if (accum_len == 0xFFFFFFFF) { 132 PM8001_IO_DBG(pm8001_ha, 133 pm8001_printk("Possible PCI issue 0x%x not expected\n", 134 accum_len)); 135 return -EIO; 136 } 137 if (accum_len == 0 || accum_len >= 0x100000) { 138 pm8001_ha->forensic_info.data_buf.direct_data += 139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 140 "%08x ", 0xFFFFFFFF); 141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 142 (char *)buf; 143 } 144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 145 if (pm8001_ha->forensic_fatal_step == 0) { 146 moreData: 147 if (pm8001_ha->forensic_info.data_buf.direct_data) { 148 /* Data is in bar, copy to host memory */ 149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc, 150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 151 pm8001_ha->forensic_info.data_buf.direct_len , 152 1); 153 } 154 pm8001_ha->fatal_bar_loc += 155 pm8001_ha->forensic_info.data_buf.direct_len; 156 pm8001_ha->forensic_info.data_buf.direct_offset += 157 pm8001_ha->forensic_info.data_buf.direct_len; 158 pm8001_ha->forensic_last_offset += 159 pm8001_ha->forensic_info.data_buf.direct_len; 160 pm8001_ha->forensic_info.data_buf.read_len = 161 pm8001_ha->forensic_info.data_buf.direct_len; 162 163 if (pm8001_ha->forensic_last_offset >= accum_len) { 164 pm8001_ha->forensic_info.data_buf.direct_data += 165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 166 "%08x ", 3); 167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) { 168 pm8001_ha->forensic_info.data_buf.direct_data += 169 sprintf(pm8001_ha-> 170 forensic_info.data_buf.direct_data, 171 "%08x ", *(temp + index)); 172 } 173 174 pm8001_ha->fatal_bar_loc = 0; 175 pm8001_ha->forensic_fatal_step = 1; 176 pm8001_ha->fatal_forensic_shift_offset = 0; 177 pm8001_ha->forensic_last_offset = 0; 178 return (char *)pm8001_ha-> 179 forensic_info.data_buf.direct_data - 180 (char *)buf; 181 } 182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 183 pm8001_ha->forensic_info.data_buf.direct_data += 184 sprintf(pm8001_ha-> 185 forensic_info.data_buf.direct_data, 186 "%08x ", 2); 187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) { 188 pm8001_ha->forensic_info.data_buf.direct_data += 189 sprintf(pm8001_ha-> 190 forensic_info.data_buf.direct_data, 191 "%08x ", *(temp + index)); 192 } 193 return (char *)pm8001_ha-> 194 forensic_info.data_buf.direct_data - 195 (char *)buf; 196 } 197 198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 199 pm8001_ha->forensic_info.data_buf.direct_data += 200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 201 "%08x ", 2); 202 for (index = 0; index < 256; index++) { 203 pm8001_ha->forensic_info.data_buf.direct_data += 204 sprintf(pm8001_ha-> 205 forensic_info.data_buf.direct_data, 206 "%08x ", *(temp + index)); 207 } 208 pm8001_ha->fatal_forensic_shift_offset += 0x100; 209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 210 pm8001_ha->fatal_forensic_shift_offset); 211 pm8001_ha->fatal_bar_loc = 0; 212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 213 (char *)buf; 214 } 215 if (pm8001_ha->forensic_fatal_step == 1) { 216 pm8001_ha->fatal_forensic_shift_offset = 0; 217 /* Read 64K of the debug data. */ 218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 219 pm8001_ha->fatal_forensic_shift_offset); 220 pm8001_mw32(fatal_table_address, 221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 222 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 223 224 /* Poll FDDHSHK until clear */ 225 start = jiffies + (2 * HZ); /* 2 sec */ 226 227 do { 228 reg_val = pm8001_mr32(fatal_table_address, 229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 230 } while ((reg_val) && time_before(jiffies, start)); 231 232 if (reg_val != 0) { 233 PM8001_FAIL_DBG(pm8001_ha, 234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" 235 " = 0x%x\n", reg_val)); 236 return -EIO; 237 } 238 239 /* Read the next 64K of the debug data. */ 240 pm8001_ha->forensic_fatal_step = 0; 241 if (pm8001_mr32(fatal_table_address, 242 MPI_FATAL_EDUMP_TABLE_STATUS) != 243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 244 pm8001_mw32(fatal_table_address, 245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0); 246 goto moreData; 247 } else { 248 pm8001_ha->forensic_info.data_buf.direct_data += 249 sprintf(pm8001_ha-> 250 forensic_info.data_buf.direct_data, 251 "%08x ", 4); 252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 253 pm8001_ha->forensic_info.data_buf.direct_len = 0; 254 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 255 pm8001_ha->forensic_info.data_buf.read_len = 0; 256 } 257 } 258 259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 260 (char *)buf; 261 } 262 263 /** 264 * read_main_config_table - read the configure table and save it. 265 * @pm8001_ha: our hba card information 266 */ 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 268 { 269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 270 271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 274 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 276 pm8001_mr32(address, MAIN_FW_REVISION); 277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 284 pm8001_mr32(address, MAIN_GST_OFFSET); 285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 286 pm8001_mr32(address, MAIN_IBQ_OFFSET); 287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 288 pm8001_mr32(address, MAIN_OBQ_OFFSET); 289 290 /* read Error Dump Offset and Length */ 291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 299 300 /* read GPIO LED settings from the configuration table */ 301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 303 304 /* read analog Setting offset from the configuration table */ 305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 307 308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 312 /* read port recover and reset timeout */ 313 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 314 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 315 } 316 317 /** 318 * read_general_status_table - read the general status table and save it. 319 * @pm8001_ha: our hba card information 320 */ 321 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 322 { 323 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 324 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 325 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 326 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 327 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 328 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 329 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 330 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 331 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 332 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 333 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 334 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 335 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 336 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 337 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 338 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 339 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 340 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 341 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 342 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 343 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 344 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 345 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 346 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 347 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 348 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 349 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 350 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 351 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 352 } 353 /** 354 * read_phy_attr_table - read the phy attribute table and save it. 355 * @pm8001_ha: our hba card information 356 */ 357 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 358 { 359 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 360 pm8001_ha->phy_attr_table.phystart1_16[0] = 361 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 362 pm8001_ha->phy_attr_table.phystart1_16[1] = 363 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 364 pm8001_ha->phy_attr_table.phystart1_16[2] = 365 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 366 pm8001_ha->phy_attr_table.phystart1_16[3] = 367 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 368 pm8001_ha->phy_attr_table.phystart1_16[4] = 369 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 370 pm8001_ha->phy_attr_table.phystart1_16[5] = 371 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 372 pm8001_ha->phy_attr_table.phystart1_16[6] = 373 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 374 pm8001_ha->phy_attr_table.phystart1_16[7] = 375 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 376 pm8001_ha->phy_attr_table.phystart1_16[8] = 377 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 378 pm8001_ha->phy_attr_table.phystart1_16[9] = 379 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 380 pm8001_ha->phy_attr_table.phystart1_16[10] = 381 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 382 pm8001_ha->phy_attr_table.phystart1_16[11] = 383 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 384 pm8001_ha->phy_attr_table.phystart1_16[12] = 385 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 386 pm8001_ha->phy_attr_table.phystart1_16[13] = 387 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 388 pm8001_ha->phy_attr_table.phystart1_16[14] = 389 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 390 pm8001_ha->phy_attr_table.phystart1_16[15] = 391 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 392 393 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 394 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 395 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 396 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 397 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 398 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 399 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 400 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 401 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 402 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 403 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 404 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 405 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 406 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 407 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 408 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 409 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 410 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 411 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 412 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 413 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 414 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 415 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 416 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 417 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 418 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 419 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 420 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 421 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 422 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 423 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 424 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 425 426 } 427 428 /** 429 * read_inbnd_queue_table - read the inbound queue table and save it. 430 * @pm8001_ha: our hba card information 431 */ 432 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 433 { 434 int i; 435 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 436 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 437 u32 offset = i * 0x20; 438 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 439 get_pci_bar_index(pm8001_mr32(address, 440 (offset + IB_PIPCI_BAR))); 441 pm8001_ha->inbnd_q_tbl[i].pi_offset = 442 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 443 } 444 } 445 446 /** 447 * read_outbnd_queue_table - read the outbound queue table and save it. 448 * @pm8001_ha: our hba card information 449 */ 450 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 451 { 452 int i; 453 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 454 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 455 u32 offset = i * 0x24; 456 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 457 get_pci_bar_index(pm8001_mr32(address, 458 (offset + OB_CIPCI_BAR))); 459 pm8001_ha->outbnd_q_tbl[i].ci_offset = 460 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 461 } 462 } 463 464 /** 465 * init_default_table_values - init the default table. 466 * @pm8001_ha: our hba card information 467 */ 468 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 469 { 470 int i; 471 u32 offsetib, offsetob; 472 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 473 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 474 475 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 476 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 477 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 478 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 479 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 480 PM8001_EVENT_LOG_SIZE; 481 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 482 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 483 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 484 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 485 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 487 PM8001_EVENT_LOG_SIZE; 488 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 489 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 490 491 /* Disable end to end CRC checking */ 492 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 493 494 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 495 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 496 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 497 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 498 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 499 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 500 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 501 pm8001_ha->inbnd_q_tbl[i].base_virt = 502 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 503 pm8001_ha->inbnd_q_tbl[i].total_length = 504 pm8001_ha->memoryMap.region[IB + i].total_len; 505 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 506 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 507 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 508 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 509 pm8001_ha->inbnd_q_tbl[i].ci_virt = 510 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 511 offsetib = i * 0x20; 512 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 513 get_pci_bar_index(pm8001_mr32(addressib, 514 (offsetib + 0x14))); 515 pm8001_ha->inbnd_q_tbl[i].pi_offset = 516 pm8001_mr32(addressib, (offsetib + 0x18)); 517 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 518 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 519 } 520 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 521 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 522 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 523 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 524 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 525 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 526 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 527 pm8001_ha->outbnd_q_tbl[i].base_virt = 528 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 529 pm8001_ha->outbnd_q_tbl[i].total_length = 530 pm8001_ha->memoryMap.region[OB + i].total_len; 531 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 532 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 533 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 534 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 535 /* interrupt vector based on oq */ 536 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 537 pm8001_ha->outbnd_q_tbl[i].pi_virt = 538 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 539 offsetob = i * 0x24; 540 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 541 get_pci_bar_index(pm8001_mr32(addressob, 542 offsetob + 0x14)); 543 pm8001_ha->outbnd_q_tbl[i].ci_offset = 544 pm8001_mr32(addressob, (offsetob + 0x18)); 545 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 546 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 547 } 548 } 549 550 /** 551 * update_main_config_table - update the main default table to the HBA. 552 * @pm8001_ha: our hba card information 553 */ 554 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 555 { 556 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 557 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 559 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 561 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 563 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 565 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 567 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 569 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 570 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 571 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 572 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 573 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 575 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 577 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 578 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 579 580 /* SPCv specific */ 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 582 /* Set GPIOLED to 0x2 for LED indicator */ 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 584 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 585 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 586 587 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 589 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 590 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 591 592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 594 PORT_RECOVERY_TIMEOUT; 595 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 597 } 598 599 /** 600 * update_inbnd_queue_table - update the inbound queue table to the HBA. 601 * @pm8001_ha: our hba card information 602 */ 603 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 604 int number) 605 { 606 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 607 u16 offset = number * 0x20; 608 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 609 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 610 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 611 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 612 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 613 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 614 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 615 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 616 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 617 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 618 } 619 620 /** 621 * update_outbnd_queue_table - update the outbound queue table to the HBA. 622 * @pm8001_ha: our hba card information 623 */ 624 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 625 int number) 626 { 627 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 628 u16 offset = number * 0x24; 629 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 630 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 631 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 632 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 633 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 634 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 635 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 636 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 637 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 638 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 639 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 640 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 641 } 642 643 /** 644 * mpi_init_check - check firmware initialization status. 645 * @pm8001_ha: our hba card information 646 */ 647 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 648 { 649 u32 max_wait_count; 650 u32 value; 651 u32 gst_len_mpistate; 652 653 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 654 table is updated */ 655 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 656 /* wait until Inbound DoorBell Clear Register toggled */ 657 if (IS_SPCV_12G(pm8001_ha->pdev)) { 658 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 659 } else { 660 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 661 } 662 do { 663 udelay(1); 664 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 665 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 666 } while ((value != 0) && (--max_wait_count)); 667 668 if (!max_wait_count) 669 return -1; 670 /* check the MPI-State for initialization upto 100ms*/ 671 max_wait_count = 100 * 1000;/* 100 msec */ 672 do { 673 udelay(1); 674 gst_len_mpistate = 675 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 676 GST_GSTLEN_MPIS_OFFSET); 677 } while ((GST_MPI_STATE_INIT != 678 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 679 if (!max_wait_count) 680 return -1; 681 682 /* check MPI Initialization error */ 683 gst_len_mpistate = gst_len_mpistate >> 16; 684 if (0x0000 != gst_len_mpistate) 685 return -1; 686 687 return 0; 688 } 689 690 /** 691 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 692 * @pm8001_ha: our hba card information 693 */ 694 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 695 { 696 u32 value; 697 u32 max_wait_count; 698 u32 max_wait_time; 699 int ret = 0; 700 701 /* reset / PCIe ready */ 702 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */ 703 do { 704 udelay(1); 705 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 706 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 707 708 /* check ila status */ 709 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */ 710 do { 711 udelay(1); 712 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 713 } while (((value & SCRATCH_PAD_ILA_READY) != 714 SCRATCH_PAD_ILA_READY) && (--max_wait_count)); 715 if (!max_wait_count) 716 ret = -1; 717 else { 718 PM8001_MSG_DBG(pm8001_ha, 719 pm8001_printk(" ila ready status in %d millisec\n", 720 (max_wait_time - max_wait_count))); 721 } 722 723 /* check RAAE status */ 724 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */ 725 do { 726 udelay(1); 727 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 728 } while (((value & SCRATCH_PAD_RAAE_READY) != 729 SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); 730 if (!max_wait_count) 731 ret = -1; 732 else { 733 PM8001_MSG_DBG(pm8001_ha, 734 pm8001_printk(" raae ready status in %d millisec\n", 735 (max_wait_time - max_wait_count))); 736 } 737 738 /* check iop0 status */ 739 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */ 740 do { 741 udelay(1); 742 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 743 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && 744 (--max_wait_count)); 745 if (!max_wait_count) 746 ret = -1; 747 else { 748 PM8001_MSG_DBG(pm8001_ha, 749 pm8001_printk(" iop0 ready status in %d millisec\n", 750 (max_wait_time - max_wait_count))); 751 } 752 753 /* check iop1 status only for 16 port controllers */ 754 if ((pm8001_ha->chip_id != chip_8008) && 755 (pm8001_ha->chip_id != chip_8009)) { 756 /* 200 milli sec */ 757 max_wait_time = max_wait_count = 200 * 1000; 758 do { 759 udelay(1); 760 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 761 } while (((value & SCRATCH_PAD_IOP1_READY) != 762 SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); 763 if (!max_wait_count) 764 ret = -1; 765 else { 766 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 767 "iop1 ready status in %d millisec\n", 768 (max_wait_time - max_wait_count))); 769 } 770 } 771 772 return ret; 773 } 774 775 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 776 { 777 void __iomem *base_addr; 778 u32 value; 779 u32 offset; 780 u32 pcibar; 781 u32 pcilogic; 782 783 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 784 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 785 786 PM8001_INIT_DBG(pm8001_ha, 787 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n", 788 offset, value)); 789 pcilogic = (value & 0xFC000000) >> 26; 790 pcibar = get_pci_bar_index(pcilogic); 791 PM8001_INIT_DBG(pm8001_ha, 792 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 793 pm8001_ha->main_cfg_tbl_addr = base_addr = 794 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 795 pm8001_ha->general_stat_tbl_addr = 796 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 797 0xFFFFFF); 798 pm8001_ha->inbnd_q_tbl_addr = 799 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 800 0xFFFFFF); 801 pm8001_ha->outbnd_q_tbl_addr = 802 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 803 0xFFFFFF); 804 pm8001_ha->ivt_tbl_addr = 805 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 806 0xFFFFFF); 807 pm8001_ha->pspa_q_tbl_addr = 808 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 809 0xFFFFFF); 810 pm8001_ha->fatal_tbl_addr = 811 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 812 0xFFFFFF); 813 814 PM8001_INIT_DBG(pm8001_ha, 815 pm8001_printk("GST OFFSET 0x%x\n", 816 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18))); 817 PM8001_INIT_DBG(pm8001_ha, 818 pm8001_printk("INBND OFFSET 0x%x\n", 819 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C))); 820 PM8001_INIT_DBG(pm8001_ha, 821 pm8001_printk("OBND OFFSET 0x%x\n", 822 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20))); 823 PM8001_INIT_DBG(pm8001_ha, 824 pm8001_printk("IVT OFFSET 0x%x\n", 825 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C))); 826 PM8001_INIT_DBG(pm8001_ha, 827 pm8001_printk("PSPA OFFSET 0x%x\n", 828 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90))); 829 PM8001_INIT_DBG(pm8001_ha, 830 pm8001_printk("addr - main cfg %p general status %p\n", 831 pm8001_ha->main_cfg_tbl_addr, 832 pm8001_ha->general_stat_tbl_addr)); 833 PM8001_INIT_DBG(pm8001_ha, 834 pm8001_printk("addr - inbnd %p obnd %p\n", 835 pm8001_ha->inbnd_q_tbl_addr, 836 pm8001_ha->outbnd_q_tbl_addr)); 837 PM8001_INIT_DBG(pm8001_ha, 838 pm8001_printk("addr - pspa %p ivt %p\n", 839 pm8001_ha->pspa_q_tbl_addr, 840 pm8001_ha->ivt_tbl_addr)); 841 } 842 843 /** 844 * pm80xx_set_thermal_config - support the thermal configuration 845 * @pm8001_ha: our hba card information. 846 */ 847 int 848 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 849 { 850 struct set_ctrl_cfg_req payload; 851 struct inbound_queue_table *circularQ; 852 int rc; 853 u32 tag; 854 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 855 u32 page_code; 856 857 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 858 rc = pm8001_tag_alloc(pm8001_ha, &tag); 859 if (rc) 860 return -1; 861 862 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 863 payload.tag = cpu_to_le32(tag); 864 865 if (IS_SPCV_12G(pm8001_ha->pdev)) 866 page_code = THERMAL_PAGE_CODE_7H; 867 else 868 page_code = THERMAL_PAGE_CODE_8H; 869 870 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 871 (THERMAL_ENABLE << 8) | page_code; 872 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 873 874 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 875 if (rc) 876 pm8001_tag_free(pm8001_ha, tag); 877 return rc; 878 879 } 880 881 /** 882 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 883 * Timer configuration page 884 * @pm8001_ha: our hba card information. 885 */ 886 static int 887 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 888 { 889 struct set_ctrl_cfg_req payload; 890 struct inbound_queue_table *circularQ; 891 SASProtocolTimerConfig_t SASConfigPage; 892 int rc; 893 u32 tag; 894 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 895 896 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 897 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 898 899 rc = pm8001_tag_alloc(pm8001_ha, &tag); 900 901 if (rc) 902 return -1; 903 904 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 905 payload.tag = cpu_to_le32(tag); 906 907 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 908 SASConfigPage.MST_MSI = 3 << 15; 909 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 910 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 911 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 912 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 913 914 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 915 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 916 917 918 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 919 SAS_OPNRJT_RTRY_INTVL; 920 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 921 | SAS_COPNRJT_RTRY_TMO; 922 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 923 | SAS_COPNRJT_RTRY_THR; 924 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 925 926 PM8001_INIT_DBG(pm8001_ha, 927 pm8001_printk("SASConfigPage.pageCode " 928 "0x%08x\n", SASConfigPage.pageCode)); 929 PM8001_INIT_DBG(pm8001_ha, 930 pm8001_printk("SASConfigPage.MST_MSI " 931 " 0x%08x\n", SASConfigPage.MST_MSI)); 932 PM8001_INIT_DBG(pm8001_ha, 933 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO " 934 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO)); 935 PM8001_INIT_DBG(pm8001_ha, 936 pm8001_printk("SASConfigPage.STP_FRM_TMO " 937 " 0x%08x\n", SASConfigPage.STP_FRM_TMO)); 938 PM8001_INIT_DBG(pm8001_ha, 939 pm8001_printk("SASConfigPage.STP_IDLE_TMO " 940 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO)); 941 PM8001_INIT_DBG(pm8001_ha, 942 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL " 943 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL)); 944 PM8001_INIT_DBG(pm8001_ha, 945 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO " 946 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 947 PM8001_INIT_DBG(pm8001_ha, 948 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR " 949 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 950 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP " 951 " 0x%08x\n", SASConfigPage.MAX_AIP)); 952 953 memcpy(&payload.cfg_pg, &SASConfigPage, 954 sizeof(SASProtocolTimerConfig_t)); 955 956 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 957 if (rc) 958 pm8001_tag_free(pm8001_ha, tag); 959 960 return rc; 961 } 962 963 /** 964 * pm80xx_get_encrypt_info - Check for encryption 965 * @pm8001_ha: our hba card information. 966 */ 967 static int 968 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 969 { 970 u32 scratch3_value; 971 int ret = -1; 972 973 /* Read encryption status from SCRATCH PAD 3 */ 974 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 975 976 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 977 SCRATCH_PAD3_ENC_READY) { 978 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 979 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 980 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 981 SCRATCH_PAD3_SMF_ENABLED) 982 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 983 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 984 SCRATCH_PAD3_SMA_ENABLED) 985 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 986 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 987 SCRATCH_PAD3_SMB_ENABLED) 988 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 989 pm8001_ha->encrypt_info.status = 0; 990 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 991 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X." 992 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 993 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 994 pm8001_ha->encrypt_info.sec_mode, 995 pm8001_ha->encrypt_info.status)); 996 ret = 0; 997 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 998 SCRATCH_PAD3_ENC_DISABLED) { 999 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1000 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1001 scratch3_value)); 1002 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1003 pm8001_ha->encrypt_info.cipher_mode = 0; 1004 pm8001_ha->encrypt_info.sec_mode = 0; 1005 ret = 0; 1006 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1007 SCRATCH_PAD3_ENC_DIS_ERR) { 1008 pm8001_ha->encrypt_info.status = 1009 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1010 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1011 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1012 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1013 SCRATCH_PAD3_SMF_ENABLED) 1014 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1015 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1016 SCRATCH_PAD3_SMA_ENABLED) 1017 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1018 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1019 SCRATCH_PAD3_SMB_ENABLED) 1020 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1021 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1022 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X." 1023 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1024 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1025 pm8001_ha->encrypt_info.sec_mode, 1026 pm8001_ha->encrypt_info.status)); 1027 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1028 SCRATCH_PAD3_ENC_ENA_ERR) { 1029 1030 pm8001_ha->encrypt_info.status = 1031 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1032 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1033 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1034 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1035 SCRATCH_PAD3_SMF_ENABLED) 1036 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1037 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1038 SCRATCH_PAD3_SMA_ENABLED) 1039 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1040 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1041 SCRATCH_PAD3_SMB_ENABLED) 1042 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1043 1044 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1045 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X." 1046 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1047 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1048 pm8001_ha->encrypt_info.sec_mode, 1049 pm8001_ha->encrypt_info.status)); 1050 } 1051 return ret; 1052 } 1053 1054 /** 1055 * pm80xx_encrypt_update - update flash with encryption informtion 1056 * @pm8001_ha: our hba card information. 1057 */ 1058 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1059 { 1060 struct kek_mgmt_req payload; 1061 struct inbound_queue_table *circularQ; 1062 int rc; 1063 u32 tag; 1064 u32 opc = OPC_INB_KEK_MANAGEMENT; 1065 1066 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1067 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1068 if (rc) 1069 return -1; 1070 1071 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1072 payload.tag = cpu_to_le32(tag); 1073 /* Currently only one key is used. New KEK index is 1. 1074 * Current KEK index is 1. Store KEK to NVRAM is 1. 1075 */ 1076 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1077 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1078 1079 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 1080 if (rc) 1081 pm8001_tag_free(pm8001_ha, tag); 1082 1083 return rc; 1084 } 1085 1086 /** 1087 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 1088 * @pm8001_ha: our hba card information 1089 */ 1090 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1091 { 1092 int ret; 1093 u8 i = 0; 1094 1095 /* check the firmware status */ 1096 if (-1 == check_fw_ready(pm8001_ha)) { 1097 PM8001_FAIL_DBG(pm8001_ha, 1098 pm8001_printk("Firmware is not ready!\n")); 1099 return -EBUSY; 1100 } 1101 1102 /* Initialize pci space address eg: mpi offset */ 1103 init_pci_device_addresses(pm8001_ha); 1104 init_default_table_values(pm8001_ha); 1105 read_main_config_table(pm8001_ha); 1106 read_general_status_table(pm8001_ha); 1107 read_inbnd_queue_table(pm8001_ha); 1108 read_outbnd_queue_table(pm8001_ha); 1109 read_phy_attr_table(pm8001_ha); 1110 1111 /* update main config table ,inbound table and outbound table */ 1112 update_main_config_table(pm8001_ha); 1113 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) 1114 update_inbnd_queue_table(pm8001_ha, i); 1115 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) 1116 update_outbnd_queue_table(pm8001_ha, i); 1117 1118 /* notify firmware update finished and check initialization status */ 1119 if (0 == mpi_init_check(pm8001_ha)) { 1120 PM8001_INIT_DBG(pm8001_ha, 1121 pm8001_printk("MPI initialize successful!\n")); 1122 } else 1123 return -EBUSY; 1124 1125 /* send SAS protocol timer configuration page to FW */ 1126 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1127 1128 /* Check for encryption */ 1129 if (pm8001_ha->chip->encrypt) { 1130 PM8001_INIT_DBG(pm8001_ha, 1131 pm8001_printk("Checking for encryption\n")); 1132 ret = pm80xx_get_encrypt_info(pm8001_ha); 1133 if (ret == -1) { 1134 PM8001_INIT_DBG(pm8001_ha, 1135 pm8001_printk("Encryption error !!\n")); 1136 if (pm8001_ha->encrypt_info.status == 0x81) { 1137 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1138 "Encryption enabled with error." 1139 "Saving encryption key to flash\n")); 1140 pm80xx_encrypt_update(pm8001_ha); 1141 } 1142 } 1143 } 1144 return 0; 1145 } 1146 1147 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1148 { 1149 u32 max_wait_count; 1150 u32 value; 1151 u32 gst_len_mpistate; 1152 init_pci_device_addresses(pm8001_ha); 1153 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1154 table is stop */ 1155 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1156 1157 /* wait until Inbound DoorBell Clear Register toggled */ 1158 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1159 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 1160 } else { 1161 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1162 } 1163 do { 1164 udelay(1); 1165 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1166 value &= SPCv_MSGU_CFG_TABLE_RESET; 1167 } while ((value != 0) && (--max_wait_count)); 1168 1169 if (!max_wait_count) { 1170 PM8001_FAIL_DBG(pm8001_ha, 1171 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value)); 1172 return -1; 1173 } 1174 1175 /* check the MPI-State for termination in progress */ 1176 /* wait until Inbound DoorBell Clear Register toggled */ 1177 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 1178 do { 1179 udelay(1); 1180 gst_len_mpistate = 1181 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1182 GST_GSTLEN_MPIS_OFFSET); 1183 if (GST_MPI_STATE_UNINIT == 1184 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1185 break; 1186 } while (--max_wait_count); 1187 if (!max_wait_count) { 1188 PM8001_FAIL_DBG(pm8001_ha, 1189 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 1190 gst_len_mpistate & GST_MPI_STATE_MASK)); 1191 return -1; 1192 } 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1199 * the FW register status to the originated status. 1200 * @pm8001_ha: our hba card information 1201 */ 1202 1203 static int 1204 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1205 { 1206 u32 regval; 1207 u32 bootloader_state; 1208 u32 ibutton0, ibutton1; 1209 1210 /* Check if MPI is in ready state to reset */ 1211 if (mpi_uninit_check(pm8001_ha) != 0) { 1212 PM8001_FAIL_DBG(pm8001_ha, 1213 pm8001_printk("MPI state is not ready\n")); 1214 return -1; 1215 } 1216 1217 /* checked for reset register normal state; 0x0 */ 1218 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1219 PM8001_INIT_DBG(pm8001_ha, 1220 pm8001_printk("reset register before write : 0x%x\n", regval)); 1221 1222 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1223 mdelay(500); 1224 1225 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1226 PM8001_INIT_DBG(pm8001_ha, 1227 pm8001_printk("reset register after write 0x%x\n", regval)); 1228 1229 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1230 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1231 PM8001_MSG_DBG(pm8001_ha, 1232 pm8001_printk(" soft reset successful [regval: 0x%x]\n", 1233 regval)); 1234 } else { 1235 PM8001_MSG_DBG(pm8001_ha, 1236 pm8001_printk(" soft reset failed [regval: 0x%x]\n", 1237 regval)); 1238 1239 /* check bootloader is successfully executed or in HDA mode */ 1240 bootloader_state = 1241 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1242 SCRATCH_PAD1_BOOTSTATE_MASK; 1243 1244 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1245 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1246 "Bootloader state - HDA mode SEEPROM\n")); 1247 } else if (bootloader_state == 1248 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1249 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1250 "Bootloader state - HDA mode Bootstrap Pin\n")); 1251 } else if (bootloader_state == 1252 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1253 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1254 "Bootloader state - HDA mode soft reset\n")); 1255 } else if (bootloader_state == 1256 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1257 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1258 "Bootloader state-HDA mode critical error\n")); 1259 } 1260 return -EBUSY; 1261 } 1262 1263 /* check the firmware status after reset */ 1264 if (-1 == check_fw_ready(pm8001_ha)) { 1265 PM8001_FAIL_DBG(pm8001_ha, 1266 pm8001_printk("Firmware is not ready!\n")); 1267 /* check iButton feature support for motherboard controller */ 1268 if (pm8001_ha->pdev->subsystem_vendor != 1269 PCI_VENDOR_ID_ADAPTEC2 && 1270 pm8001_ha->pdev->subsystem_vendor != 0) { 1271 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1272 MSGU_HOST_SCRATCH_PAD_6); 1273 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1274 MSGU_HOST_SCRATCH_PAD_7); 1275 if (!ibutton0 && !ibutton1) { 1276 PM8001_FAIL_DBG(pm8001_ha, 1277 pm8001_printk("iButton Feature is" 1278 " not Available!!!\n")); 1279 return -EBUSY; 1280 } 1281 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1282 PM8001_FAIL_DBG(pm8001_ha, 1283 pm8001_printk("CRC Check for iButton" 1284 " Feature Failed!!!\n")); 1285 return -EBUSY; 1286 } 1287 } 1288 } 1289 PM8001_INIT_DBG(pm8001_ha, 1290 pm8001_printk("SPCv soft reset Complete\n")); 1291 return 0; 1292 } 1293 1294 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1295 { 1296 u32 i; 1297 1298 PM8001_INIT_DBG(pm8001_ha, 1299 pm8001_printk("chip reset start\n")); 1300 1301 /* do SPCv chip reset. */ 1302 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1303 PM8001_INIT_DBG(pm8001_ha, 1304 pm8001_printk("SPC soft reset Complete\n")); 1305 1306 /* Check this ..whether delay is required or no */ 1307 /* delay 10 usec */ 1308 udelay(10); 1309 1310 /* wait for 20 msec until the firmware gets reloaded */ 1311 i = 20; 1312 do { 1313 mdelay(1); 1314 } while ((--i) != 0); 1315 1316 PM8001_INIT_DBG(pm8001_ha, 1317 pm8001_printk("chip reset finished\n")); 1318 } 1319 1320 /** 1321 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1322 * @pm8001_ha: our hba card information 1323 */ 1324 static void 1325 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1326 { 1327 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1328 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1329 } 1330 1331 /** 1332 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1333 * @pm8001_ha: our hba card information 1334 */ 1335 static void 1336 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1337 { 1338 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1339 } 1340 1341 /** 1342 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1343 * @pm8001_ha: our hba card information 1344 */ 1345 static void 1346 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1347 { 1348 #ifdef PM8001_USE_MSIX 1349 u32 mask; 1350 mask = (u32)(1 << vec); 1351 1352 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1353 return; 1354 #endif 1355 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1356 1357 } 1358 1359 /** 1360 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1361 * @pm8001_ha: our hba card information 1362 */ 1363 static void 1364 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1365 { 1366 #ifdef PM8001_USE_MSIX 1367 u32 mask; 1368 if (vec == 0xFF) 1369 mask = 0xFFFFFFFF; 1370 else 1371 mask = (u32)(1 << vec); 1372 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1373 return; 1374 #endif 1375 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1376 } 1377 1378 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1379 struct pm8001_device *pm8001_ha_dev) 1380 { 1381 int res; 1382 u32 ccb_tag; 1383 struct pm8001_ccb_info *ccb; 1384 struct sas_task *task = NULL; 1385 struct task_abort_req task_abort; 1386 struct inbound_queue_table *circularQ; 1387 u32 opc = OPC_INB_SATA_ABORT; 1388 int ret; 1389 1390 if (!pm8001_ha_dev) { 1391 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1392 return; 1393 } 1394 1395 task = sas_alloc_slow_task(GFP_ATOMIC); 1396 1397 if (!task) { 1398 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1399 "allocate task\n")); 1400 return; 1401 } 1402 1403 task->task_done = pm8001_task_done; 1404 1405 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1406 if (res) { 1407 sas_free_task(task); 1408 return; 1409 } 1410 1411 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1412 ccb->device = pm8001_ha_dev; 1413 ccb->ccb_tag = ccb_tag; 1414 ccb->task = task; 1415 1416 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1417 1418 memset(&task_abort, 0, sizeof(task_abort)); 1419 task_abort.abort_all = cpu_to_le32(1); 1420 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1421 task_abort.tag = cpu_to_le32(ccb_tag); 1422 1423 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 1424 if (ret) { 1425 sas_free_task(task); 1426 pm8001_tag_free(pm8001_ha, ccb_tag); 1427 } 1428 } 1429 1430 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1431 struct pm8001_device *pm8001_ha_dev) 1432 { 1433 struct sata_start_req sata_cmd; 1434 int res; 1435 u32 ccb_tag; 1436 struct pm8001_ccb_info *ccb; 1437 struct sas_task *task = NULL; 1438 struct host_to_dev_fis fis; 1439 struct domain_device *dev; 1440 struct inbound_queue_table *circularQ; 1441 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1442 1443 task = sas_alloc_slow_task(GFP_ATOMIC); 1444 1445 if (!task) { 1446 PM8001_FAIL_DBG(pm8001_ha, 1447 pm8001_printk("cannot allocate task !!!\n")); 1448 return; 1449 } 1450 task->task_done = pm8001_task_done; 1451 1452 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1453 if (res) { 1454 sas_free_task(task); 1455 PM8001_FAIL_DBG(pm8001_ha, 1456 pm8001_printk("cannot allocate tag !!!\n")); 1457 return; 1458 } 1459 1460 /* allocate domain device by ourselves as libsas 1461 * is not going to provide any 1462 */ 1463 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1464 if (!dev) { 1465 sas_free_task(task); 1466 pm8001_tag_free(pm8001_ha, ccb_tag); 1467 PM8001_FAIL_DBG(pm8001_ha, 1468 pm8001_printk("Domain device cannot be allocated\n")); 1469 return; 1470 } 1471 1472 task->dev = dev; 1473 task->dev->lldd_dev = pm8001_ha_dev; 1474 1475 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1476 ccb->device = pm8001_ha_dev; 1477 ccb->ccb_tag = ccb_tag; 1478 ccb->task = task; 1479 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1480 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1481 1482 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1483 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1484 1485 /* construct read log FIS */ 1486 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1487 fis.fis_type = 0x27; 1488 fis.flags = 0x80; 1489 fis.command = ATA_CMD_READ_LOG_EXT; 1490 fis.lbal = 0x10; 1491 fis.sector_count = 0x1; 1492 1493 sata_cmd.tag = cpu_to_le32(ccb_tag); 1494 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1495 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1496 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1497 1498 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 1499 if (res) { 1500 sas_free_task(task); 1501 pm8001_tag_free(pm8001_ha, ccb_tag); 1502 kfree(dev); 1503 } 1504 } 1505 1506 /** 1507 * mpi_ssp_completion- process the event that FW response to the SSP request. 1508 * @pm8001_ha: our hba card information 1509 * @piomb: the message contents of this outbound message. 1510 * 1511 * When FW has completed a ssp request for example a IO request, after it has 1512 * filled the SG data with the data, it will trigger this event represent 1513 * that he has finished the job,please check the coresponding buffer. 1514 * So we will tell the caller who maybe waiting the result to tell upper layer 1515 * that the task has been finished. 1516 */ 1517 static void 1518 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1519 { 1520 struct sas_task *t; 1521 struct pm8001_ccb_info *ccb; 1522 unsigned long flags; 1523 u32 status; 1524 u32 param; 1525 u32 tag; 1526 struct ssp_completion_resp *psspPayload; 1527 struct task_status_struct *ts; 1528 struct ssp_response_iu *iu; 1529 struct pm8001_device *pm8001_dev; 1530 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1531 status = le32_to_cpu(psspPayload->status); 1532 tag = le32_to_cpu(psspPayload->tag); 1533 ccb = &pm8001_ha->ccb_info[tag]; 1534 if ((status == IO_ABORTED) && ccb->open_retry) { 1535 /* Being completed by another */ 1536 ccb->open_retry = 0; 1537 return; 1538 } 1539 pm8001_dev = ccb->device; 1540 param = le32_to_cpu(psspPayload->param); 1541 t = ccb->task; 1542 1543 if (status && status != IO_UNDERFLOW) 1544 PM8001_FAIL_DBG(pm8001_ha, 1545 pm8001_printk("sas IO status 0x%x\n", status)); 1546 if (unlikely(!t || !t->lldd_task || !t->dev)) 1547 return; 1548 ts = &t->task_status; 1549 /* Print sas address of IO failed device */ 1550 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1551 (status != IO_UNDERFLOW)) 1552 PM8001_FAIL_DBG(pm8001_ha, 1553 pm8001_printk("SAS Address of IO Failure Drive" 1554 ":%016llx", SAS_ADDR(t->dev->sas_addr))); 1555 1556 switch (status) { 1557 case IO_SUCCESS: 1558 PM8001_IO_DBG(pm8001_ha, 1559 pm8001_printk("IO_SUCCESS ,param = 0x%x\n", 1560 param)); 1561 if (param == 0) { 1562 ts->resp = SAS_TASK_COMPLETE; 1563 ts->stat = SAM_STAT_GOOD; 1564 } else { 1565 ts->resp = SAS_TASK_COMPLETE; 1566 ts->stat = SAS_PROTO_RESPONSE; 1567 ts->residual = param; 1568 iu = &psspPayload->ssp_resp_iu; 1569 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1570 } 1571 if (pm8001_dev) 1572 pm8001_dev->running_req--; 1573 break; 1574 case IO_ABORTED: 1575 PM8001_IO_DBG(pm8001_ha, 1576 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1577 ts->resp = SAS_TASK_COMPLETE; 1578 ts->stat = SAS_ABORTED_TASK; 1579 break; 1580 case IO_UNDERFLOW: 1581 /* SSP Completion with error */ 1582 PM8001_IO_DBG(pm8001_ha, 1583 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n", 1584 param)); 1585 ts->resp = SAS_TASK_COMPLETE; 1586 ts->stat = SAS_DATA_UNDERRUN; 1587 ts->residual = param; 1588 if (pm8001_dev) 1589 pm8001_dev->running_req--; 1590 break; 1591 case IO_NO_DEVICE: 1592 PM8001_IO_DBG(pm8001_ha, 1593 pm8001_printk("IO_NO_DEVICE\n")); 1594 ts->resp = SAS_TASK_UNDELIVERED; 1595 ts->stat = SAS_PHY_DOWN; 1596 break; 1597 case IO_XFER_ERROR_BREAK: 1598 PM8001_IO_DBG(pm8001_ha, 1599 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1600 ts->resp = SAS_TASK_COMPLETE; 1601 ts->stat = SAS_OPEN_REJECT; 1602 /* Force the midlayer to retry */ 1603 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1604 break; 1605 case IO_XFER_ERROR_PHY_NOT_READY: 1606 PM8001_IO_DBG(pm8001_ha, 1607 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1608 ts->resp = SAS_TASK_COMPLETE; 1609 ts->stat = SAS_OPEN_REJECT; 1610 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1611 break; 1612 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1613 PM8001_IO_DBG(pm8001_ha, 1614 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n")); 1615 ts->resp = SAS_TASK_COMPLETE; 1616 ts->stat = SAS_OPEN_REJECT; 1617 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1618 break; 1619 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1620 PM8001_IO_DBG(pm8001_ha, 1621 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1622 ts->resp = SAS_TASK_COMPLETE; 1623 ts->stat = SAS_OPEN_REJECT; 1624 ts->open_rej_reason = SAS_OREJ_EPROTO; 1625 break; 1626 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1627 PM8001_IO_DBG(pm8001_ha, 1628 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1629 ts->resp = SAS_TASK_COMPLETE; 1630 ts->stat = SAS_OPEN_REJECT; 1631 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1632 break; 1633 case IO_OPEN_CNX_ERROR_BREAK: 1634 PM8001_IO_DBG(pm8001_ha, 1635 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1636 ts->resp = SAS_TASK_COMPLETE; 1637 ts->stat = SAS_OPEN_REJECT; 1638 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1639 break; 1640 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1641 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1642 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1643 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1644 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1645 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1646 PM8001_IO_DBG(pm8001_ha, 1647 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1648 ts->resp = SAS_TASK_COMPLETE; 1649 ts->stat = SAS_OPEN_REJECT; 1650 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1651 if (!t->uldd_task) 1652 pm8001_handle_event(pm8001_ha, 1653 pm8001_dev, 1654 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1655 break; 1656 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1657 PM8001_IO_DBG(pm8001_ha, 1658 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1659 ts->resp = SAS_TASK_COMPLETE; 1660 ts->stat = SAS_OPEN_REJECT; 1661 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1662 break; 1663 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1664 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1665 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1666 ts->resp = SAS_TASK_COMPLETE; 1667 ts->stat = SAS_OPEN_REJECT; 1668 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1669 break; 1670 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1671 PM8001_IO_DBG(pm8001_ha, 1672 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1673 ts->resp = SAS_TASK_UNDELIVERED; 1674 ts->stat = SAS_OPEN_REJECT; 1675 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1676 break; 1677 case IO_XFER_ERROR_NAK_RECEIVED: 1678 PM8001_IO_DBG(pm8001_ha, 1679 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1680 ts->resp = SAS_TASK_COMPLETE; 1681 ts->stat = SAS_OPEN_REJECT; 1682 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1683 break; 1684 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1685 PM8001_IO_DBG(pm8001_ha, 1686 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1687 ts->resp = SAS_TASK_COMPLETE; 1688 ts->stat = SAS_NAK_R_ERR; 1689 break; 1690 case IO_XFER_ERROR_DMA: 1691 PM8001_IO_DBG(pm8001_ha, 1692 pm8001_printk("IO_XFER_ERROR_DMA\n")); 1693 ts->resp = SAS_TASK_COMPLETE; 1694 ts->stat = SAS_OPEN_REJECT; 1695 break; 1696 case IO_XFER_OPEN_RETRY_TIMEOUT: 1697 PM8001_IO_DBG(pm8001_ha, 1698 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1699 ts->resp = SAS_TASK_COMPLETE; 1700 ts->stat = SAS_OPEN_REJECT; 1701 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1702 break; 1703 case IO_XFER_ERROR_OFFSET_MISMATCH: 1704 PM8001_IO_DBG(pm8001_ha, 1705 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1706 ts->resp = SAS_TASK_COMPLETE; 1707 ts->stat = SAS_OPEN_REJECT; 1708 break; 1709 case IO_PORT_IN_RESET: 1710 PM8001_IO_DBG(pm8001_ha, 1711 pm8001_printk("IO_PORT_IN_RESET\n")); 1712 ts->resp = SAS_TASK_COMPLETE; 1713 ts->stat = SAS_OPEN_REJECT; 1714 break; 1715 case IO_DS_NON_OPERATIONAL: 1716 PM8001_IO_DBG(pm8001_ha, 1717 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1718 ts->resp = SAS_TASK_COMPLETE; 1719 ts->stat = SAS_OPEN_REJECT; 1720 if (!t->uldd_task) 1721 pm8001_handle_event(pm8001_ha, 1722 pm8001_dev, 1723 IO_DS_NON_OPERATIONAL); 1724 break; 1725 case IO_DS_IN_RECOVERY: 1726 PM8001_IO_DBG(pm8001_ha, 1727 pm8001_printk("IO_DS_IN_RECOVERY\n")); 1728 ts->resp = SAS_TASK_COMPLETE; 1729 ts->stat = SAS_OPEN_REJECT; 1730 break; 1731 case IO_TM_TAG_NOT_FOUND: 1732 PM8001_IO_DBG(pm8001_ha, 1733 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1734 ts->resp = SAS_TASK_COMPLETE; 1735 ts->stat = SAS_OPEN_REJECT; 1736 break; 1737 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1738 PM8001_IO_DBG(pm8001_ha, 1739 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1740 ts->resp = SAS_TASK_COMPLETE; 1741 ts->stat = SAS_OPEN_REJECT; 1742 break; 1743 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1744 PM8001_IO_DBG(pm8001_ha, 1745 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1746 ts->resp = SAS_TASK_COMPLETE; 1747 ts->stat = SAS_OPEN_REJECT; 1748 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1749 break; 1750 default: 1751 PM8001_IO_DBG(pm8001_ha, 1752 pm8001_printk("Unknown status 0x%x\n", status)); 1753 /* not allowed case. Therefore, return failed status */ 1754 ts->resp = SAS_TASK_COMPLETE; 1755 ts->stat = SAS_OPEN_REJECT; 1756 break; 1757 } 1758 PM8001_IO_DBG(pm8001_ha, 1759 pm8001_printk("scsi_status = 0x%x\n ", 1760 psspPayload->ssp_resp_iu.status)); 1761 spin_lock_irqsave(&t->task_state_lock, flags); 1762 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1763 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1764 t->task_state_flags |= SAS_TASK_STATE_DONE; 1765 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1766 spin_unlock_irqrestore(&t->task_state_lock, flags); 1767 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1768 "task 0x%p done with io_status 0x%x resp 0x%x " 1769 "stat 0x%x but aborted by upper layer!\n", 1770 t, status, ts->resp, ts->stat)); 1771 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1772 } else { 1773 spin_unlock_irqrestore(&t->task_state_lock, flags); 1774 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1775 mb();/* in order to force CPU ordering */ 1776 t->task_done(t); 1777 } 1778 } 1779 1780 /*See the comments for mpi_ssp_completion */ 1781 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 1782 { 1783 struct sas_task *t; 1784 unsigned long flags; 1785 struct task_status_struct *ts; 1786 struct pm8001_ccb_info *ccb; 1787 struct pm8001_device *pm8001_dev; 1788 struct ssp_event_resp *psspPayload = 1789 (struct ssp_event_resp *)(piomb + 4); 1790 u32 event = le32_to_cpu(psspPayload->event); 1791 u32 tag = le32_to_cpu(psspPayload->tag); 1792 u32 port_id = le32_to_cpu(psspPayload->port_id); 1793 1794 ccb = &pm8001_ha->ccb_info[tag]; 1795 t = ccb->task; 1796 pm8001_dev = ccb->device; 1797 if (event) 1798 PM8001_FAIL_DBG(pm8001_ha, 1799 pm8001_printk("sas IO status 0x%x\n", event)); 1800 if (unlikely(!t || !t->lldd_task || !t->dev)) 1801 return; 1802 ts = &t->task_status; 1803 PM8001_IO_DBG(pm8001_ha, 1804 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 1805 port_id, tag, event)); 1806 switch (event) { 1807 case IO_OVERFLOW: 1808 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 1809 ts->resp = SAS_TASK_COMPLETE; 1810 ts->stat = SAS_DATA_OVERRUN; 1811 ts->residual = 0; 1812 if (pm8001_dev) 1813 pm8001_dev->running_req--; 1814 break; 1815 case IO_XFER_ERROR_BREAK: 1816 PM8001_IO_DBG(pm8001_ha, 1817 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1818 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 1819 return; 1820 case IO_XFER_ERROR_PHY_NOT_READY: 1821 PM8001_IO_DBG(pm8001_ha, 1822 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1823 ts->resp = SAS_TASK_COMPLETE; 1824 ts->stat = SAS_OPEN_REJECT; 1825 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1826 break; 1827 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1828 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1829 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1830 ts->resp = SAS_TASK_COMPLETE; 1831 ts->stat = SAS_OPEN_REJECT; 1832 ts->open_rej_reason = SAS_OREJ_EPROTO; 1833 break; 1834 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1835 PM8001_IO_DBG(pm8001_ha, 1836 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1837 ts->resp = SAS_TASK_COMPLETE; 1838 ts->stat = SAS_OPEN_REJECT; 1839 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1840 break; 1841 case IO_OPEN_CNX_ERROR_BREAK: 1842 PM8001_IO_DBG(pm8001_ha, 1843 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1844 ts->resp = SAS_TASK_COMPLETE; 1845 ts->stat = SAS_OPEN_REJECT; 1846 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1847 break; 1848 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1849 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1850 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1851 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1852 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1853 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1854 PM8001_IO_DBG(pm8001_ha, 1855 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1856 ts->resp = SAS_TASK_COMPLETE; 1857 ts->stat = SAS_OPEN_REJECT; 1858 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1859 if (!t->uldd_task) 1860 pm8001_handle_event(pm8001_ha, 1861 pm8001_dev, 1862 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1863 break; 1864 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1865 PM8001_IO_DBG(pm8001_ha, 1866 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1867 ts->resp = SAS_TASK_COMPLETE; 1868 ts->stat = SAS_OPEN_REJECT; 1869 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1870 break; 1871 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1872 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1873 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1874 ts->resp = SAS_TASK_COMPLETE; 1875 ts->stat = SAS_OPEN_REJECT; 1876 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1877 break; 1878 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1879 PM8001_IO_DBG(pm8001_ha, 1880 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1881 ts->resp = SAS_TASK_COMPLETE; 1882 ts->stat = SAS_OPEN_REJECT; 1883 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1884 break; 1885 case IO_XFER_ERROR_NAK_RECEIVED: 1886 PM8001_IO_DBG(pm8001_ha, 1887 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1888 ts->resp = SAS_TASK_COMPLETE; 1889 ts->stat = SAS_OPEN_REJECT; 1890 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1891 break; 1892 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1893 PM8001_IO_DBG(pm8001_ha, 1894 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1895 ts->resp = SAS_TASK_COMPLETE; 1896 ts->stat = SAS_NAK_R_ERR; 1897 break; 1898 case IO_XFER_OPEN_RETRY_TIMEOUT: 1899 PM8001_IO_DBG(pm8001_ha, 1900 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1901 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 1902 return; 1903 case IO_XFER_ERROR_UNEXPECTED_PHASE: 1904 PM8001_IO_DBG(pm8001_ha, 1905 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 1906 ts->resp = SAS_TASK_COMPLETE; 1907 ts->stat = SAS_DATA_OVERRUN; 1908 break; 1909 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 1910 PM8001_IO_DBG(pm8001_ha, 1911 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 1912 ts->resp = SAS_TASK_COMPLETE; 1913 ts->stat = SAS_DATA_OVERRUN; 1914 break; 1915 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 1916 PM8001_IO_DBG(pm8001_ha, 1917 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 1918 ts->resp = SAS_TASK_COMPLETE; 1919 ts->stat = SAS_DATA_OVERRUN; 1920 break; 1921 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 1922 PM8001_IO_DBG(pm8001_ha, 1923 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 1924 ts->resp = SAS_TASK_COMPLETE; 1925 ts->stat = SAS_DATA_OVERRUN; 1926 break; 1927 case IO_XFER_ERROR_OFFSET_MISMATCH: 1928 PM8001_IO_DBG(pm8001_ha, 1929 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1930 ts->resp = SAS_TASK_COMPLETE; 1931 ts->stat = SAS_DATA_OVERRUN; 1932 break; 1933 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 1934 PM8001_IO_DBG(pm8001_ha, 1935 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 1936 ts->resp = SAS_TASK_COMPLETE; 1937 ts->stat = SAS_DATA_OVERRUN; 1938 break; 1939 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 1940 PM8001_IO_DBG(pm8001_ha, 1941 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 1942 /* TBC: used default set values */ 1943 ts->resp = SAS_TASK_COMPLETE; 1944 ts->stat = SAS_DATA_OVERRUN; 1945 break; 1946 case IO_XFER_CMD_FRAME_ISSUED: 1947 PM8001_IO_DBG(pm8001_ha, 1948 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 1949 return; 1950 default: 1951 PM8001_IO_DBG(pm8001_ha, 1952 pm8001_printk("Unknown status 0x%x\n", event)); 1953 /* not allowed case. Therefore, return failed status */ 1954 ts->resp = SAS_TASK_COMPLETE; 1955 ts->stat = SAS_DATA_OVERRUN; 1956 break; 1957 } 1958 spin_lock_irqsave(&t->task_state_lock, flags); 1959 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1960 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1961 t->task_state_flags |= SAS_TASK_STATE_DONE; 1962 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1963 spin_unlock_irqrestore(&t->task_state_lock, flags); 1964 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1965 "task 0x%p done with event 0x%x resp 0x%x " 1966 "stat 0x%x but aborted by upper layer!\n", 1967 t, event, ts->resp, ts->stat)); 1968 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1969 } else { 1970 spin_unlock_irqrestore(&t->task_state_lock, flags); 1971 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1972 mb();/* in order to force CPU ordering */ 1973 t->task_done(t); 1974 } 1975 } 1976 1977 /*See the comments for mpi_ssp_completion */ 1978 static void 1979 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1980 { 1981 struct sas_task *t; 1982 struct pm8001_ccb_info *ccb; 1983 u32 param; 1984 u32 status; 1985 u32 tag; 1986 int i, j; 1987 u8 sata_addr_low[4]; 1988 u32 temp_sata_addr_low, temp_sata_addr_hi; 1989 u8 sata_addr_hi[4]; 1990 struct sata_completion_resp *psataPayload; 1991 struct task_status_struct *ts; 1992 struct ata_task_resp *resp ; 1993 u32 *sata_resp; 1994 struct pm8001_device *pm8001_dev; 1995 unsigned long flags; 1996 1997 psataPayload = (struct sata_completion_resp *)(piomb + 4); 1998 status = le32_to_cpu(psataPayload->status); 1999 tag = le32_to_cpu(psataPayload->tag); 2000 2001 if (!tag) { 2002 PM8001_FAIL_DBG(pm8001_ha, 2003 pm8001_printk("tag null\n")); 2004 return; 2005 } 2006 ccb = &pm8001_ha->ccb_info[tag]; 2007 param = le32_to_cpu(psataPayload->param); 2008 if (ccb) { 2009 t = ccb->task; 2010 pm8001_dev = ccb->device; 2011 } else { 2012 PM8001_FAIL_DBG(pm8001_ha, 2013 pm8001_printk("ccb null\n")); 2014 return; 2015 } 2016 2017 if (t) { 2018 if (t->dev && (t->dev->lldd_dev)) 2019 pm8001_dev = t->dev->lldd_dev; 2020 } else { 2021 PM8001_FAIL_DBG(pm8001_ha, 2022 pm8001_printk("task null\n")); 2023 return; 2024 } 2025 2026 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2027 && unlikely(!t || !t->lldd_task || !t->dev)) { 2028 PM8001_FAIL_DBG(pm8001_ha, 2029 pm8001_printk("task or dev null\n")); 2030 return; 2031 } 2032 2033 ts = &t->task_status; 2034 if (!ts) { 2035 PM8001_FAIL_DBG(pm8001_ha, 2036 pm8001_printk("ts null\n")); 2037 return; 2038 } 2039 /* Print sas address of IO failed device */ 2040 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2041 (status != IO_UNDERFLOW)) { 2042 if (!((t->dev->parent) && 2043 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) { 2044 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 2045 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2046 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 2047 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2048 memcpy(&temp_sata_addr_low, sata_addr_low, 2049 sizeof(sata_addr_low)); 2050 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2051 sizeof(sata_addr_hi)); 2052 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2053 |((temp_sata_addr_hi << 8) & 2054 0xff0000) | 2055 ((temp_sata_addr_hi >> 8) 2056 & 0xff00) | 2057 ((temp_sata_addr_hi << 24) & 2058 0xff000000)); 2059 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2060 & 0xff) | 2061 ((temp_sata_addr_low << 8) 2062 & 0xff0000) | 2063 ((temp_sata_addr_low >> 8) 2064 & 0xff00) | 2065 ((temp_sata_addr_low << 24) 2066 & 0xff000000)) + 2067 pm8001_dev->attached_phy + 2068 0x10); 2069 PM8001_FAIL_DBG(pm8001_ha, 2070 pm8001_printk("SAS Address of IO Failure Drive:" 2071 "%08x%08x", temp_sata_addr_hi, 2072 temp_sata_addr_low)); 2073 2074 } else { 2075 PM8001_FAIL_DBG(pm8001_ha, 2076 pm8001_printk("SAS Address of IO Failure Drive:" 2077 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2078 } 2079 } 2080 switch (status) { 2081 case IO_SUCCESS: 2082 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2083 if (param == 0) { 2084 ts->resp = SAS_TASK_COMPLETE; 2085 ts->stat = SAM_STAT_GOOD; 2086 /* check if response is for SEND READ LOG */ 2087 if (pm8001_dev && 2088 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2089 /* set new bit for abort_all */ 2090 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2091 /* clear bit for read log */ 2092 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2093 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2094 /* Free the tag */ 2095 pm8001_tag_free(pm8001_ha, tag); 2096 sas_free_task(t); 2097 return; 2098 } 2099 } else { 2100 u8 len; 2101 ts->resp = SAS_TASK_COMPLETE; 2102 ts->stat = SAS_PROTO_RESPONSE; 2103 ts->residual = param; 2104 PM8001_IO_DBG(pm8001_ha, 2105 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2106 param)); 2107 sata_resp = &psataPayload->sata_resp[0]; 2108 resp = (struct ata_task_resp *)ts->buf; 2109 if (t->ata_task.dma_xfer == 0 && 2110 t->data_dir == PCI_DMA_FROMDEVICE) { 2111 len = sizeof(struct pio_setup_fis); 2112 PM8001_IO_DBG(pm8001_ha, 2113 pm8001_printk("PIO read len = %d\n", len)); 2114 } else if (t->ata_task.use_ncq) { 2115 len = sizeof(struct set_dev_bits_fis); 2116 PM8001_IO_DBG(pm8001_ha, 2117 pm8001_printk("FPDMA len = %d\n", len)); 2118 } else { 2119 len = sizeof(struct dev_to_host_fis); 2120 PM8001_IO_DBG(pm8001_ha, 2121 pm8001_printk("other len = %d\n", len)); 2122 } 2123 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2124 resp->frame_len = len; 2125 memcpy(&resp->ending_fis[0], sata_resp, len); 2126 ts->buf_valid_size = sizeof(*resp); 2127 } else 2128 PM8001_IO_DBG(pm8001_ha, 2129 pm8001_printk("response to large\n")); 2130 } 2131 if (pm8001_dev) 2132 pm8001_dev->running_req--; 2133 break; 2134 case IO_ABORTED: 2135 PM8001_IO_DBG(pm8001_ha, 2136 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2137 ts->resp = SAS_TASK_COMPLETE; 2138 ts->stat = SAS_ABORTED_TASK; 2139 if (pm8001_dev) 2140 pm8001_dev->running_req--; 2141 break; 2142 /* following cases are to do cases */ 2143 case IO_UNDERFLOW: 2144 /* SATA Completion with error */ 2145 PM8001_IO_DBG(pm8001_ha, 2146 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2147 ts->resp = SAS_TASK_COMPLETE; 2148 ts->stat = SAS_DATA_UNDERRUN; 2149 ts->residual = param; 2150 if (pm8001_dev) 2151 pm8001_dev->running_req--; 2152 break; 2153 case IO_NO_DEVICE: 2154 PM8001_IO_DBG(pm8001_ha, 2155 pm8001_printk("IO_NO_DEVICE\n")); 2156 ts->resp = SAS_TASK_UNDELIVERED; 2157 ts->stat = SAS_PHY_DOWN; 2158 break; 2159 case IO_XFER_ERROR_BREAK: 2160 PM8001_IO_DBG(pm8001_ha, 2161 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2162 ts->resp = SAS_TASK_COMPLETE; 2163 ts->stat = SAS_INTERRUPTED; 2164 break; 2165 case IO_XFER_ERROR_PHY_NOT_READY: 2166 PM8001_IO_DBG(pm8001_ha, 2167 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2168 ts->resp = SAS_TASK_COMPLETE; 2169 ts->stat = SAS_OPEN_REJECT; 2170 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2171 break; 2172 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2173 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2174 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2175 ts->resp = SAS_TASK_COMPLETE; 2176 ts->stat = SAS_OPEN_REJECT; 2177 ts->open_rej_reason = SAS_OREJ_EPROTO; 2178 break; 2179 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2180 PM8001_IO_DBG(pm8001_ha, 2181 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2182 ts->resp = SAS_TASK_COMPLETE; 2183 ts->stat = SAS_OPEN_REJECT; 2184 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2185 break; 2186 case IO_OPEN_CNX_ERROR_BREAK: 2187 PM8001_IO_DBG(pm8001_ha, 2188 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2189 ts->resp = SAS_TASK_COMPLETE; 2190 ts->stat = SAS_OPEN_REJECT; 2191 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2192 break; 2193 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2194 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2195 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2196 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2197 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2198 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2199 PM8001_IO_DBG(pm8001_ha, 2200 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2201 ts->resp = SAS_TASK_COMPLETE; 2202 ts->stat = SAS_DEV_NO_RESPONSE; 2203 if (!t->uldd_task) { 2204 pm8001_handle_event(pm8001_ha, 2205 pm8001_dev, 2206 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2207 ts->resp = SAS_TASK_UNDELIVERED; 2208 ts->stat = SAS_QUEUE_FULL; 2209 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2210 return; 2211 } 2212 break; 2213 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2214 PM8001_IO_DBG(pm8001_ha, 2215 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2216 ts->resp = SAS_TASK_UNDELIVERED; 2217 ts->stat = SAS_OPEN_REJECT; 2218 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2219 if (!t->uldd_task) { 2220 pm8001_handle_event(pm8001_ha, 2221 pm8001_dev, 2222 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2223 ts->resp = SAS_TASK_UNDELIVERED; 2224 ts->stat = SAS_QUEUE_FULL; 2225 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2226 return; 2227 } 2228 break; 2229 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2230 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2231 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2232 ts->resp = SAS_TASK_COMPLETE; 2233 ts->stat = SAS_OPEN_REJECT; 2234 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2235 break; 2236 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2237 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2238 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); 2239 ts->resp = SAS_TASK_COMPLETE; 2240 ts->stat = SAS_DEV_NO_RESPONSE; 2241 if (!t->uldd_task) { 2242 pm8001_handle_event(pm8001_ha, 2243 pm8001_dev, 2244 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2245 ts->resp = SAS_TASK_UNDELIVERED; 2246 ts->stat = SAS_QUEUE_FULL; 2247 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2248 return; 2249 } 2250 break; 2251 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2252 PM8001_IO_DBG(pm8001_ha, 2253 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2254 ts->resp = SAS_TASK_COMPLETE; 2255 ts->stat = SAS_OPEN_REJECT; 2256 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2257 break; 2258 case IO_XFER_ERROR_NAK_RECEIVED: 2259 PM8001_IO_DBG(pm8001_ha, 2260 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2261 ts->resp = SAS_TASK_COMPLETE; 2262 ts->stat = SAS_NAK_R_ERR; 2263 break; 2264 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2265 PM8001_IO_DBG(pm8001_ha, 2266 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2267 ts->resp = SAS_TASK_COMPLETE; 2268 ts->stat = SAS_NAK_R_ERR; 2269 break; 2270 case IO_XFER_ERROR_DMA: 2271 PM8001_IO_DBG(pm8001_ha, 2272 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2273 ts->resp = SAS_TASK_COMPLETE; 2274 ts->stat = SAS_ABORTED_TASK; 2275 break; 2276 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2277 PM8001_IO_DBG(pm8001_ha, 2278 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2279 ts->resp = SAS_TASK_UNDELIVERED; 2280 ts->stat = SAS_DEV_NO_RESPONSE; 2281 break; 2282 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2283 PM8001_IO_DBG(pm8001_ha, 2284 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2285 ts->resp = SAS_TASK_COMPLETE; 2286 ts->stat = SAS_DATA_UNDERRUN; 2287 break; 2288 case IO_XFER_OPEN_RETRY_TIMEOUT: 2289 PM8001_IO_DBG(pm8001_ha, 2290 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2291 ts->resp = SAS_TASK_COMPLETE; 2292 ts->stat = SAS_OPEN_TO; 2293 break; 2294 case IO_PORT_IN_RESET: 2295 PM8001_IO_DBG(pm8001_ha, 2296 pm8001_printk("IO_PORT_IN_RESET\n")); 2297 ts->resp = SAS_TASK_COMPLETE; 2298 ts->stat = SAS_DEV_NO_RESPONSE; 2299 break; 2300 case IO_DS_NON_OPERATIONAL: 2301 PM8001_IO_DBG(pm8001_ha, 2302 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2303 ts->resp = SAS_TASK_COMPLETE; 2304 ts->stat = SAS_DEV_NO_RESPONSE; 2305 if (!t->uldd_task) { 2306 pm8001_handle_event(pm8001_ha, pm8001_dev, 2307 IO_DS_NON_OPERATIONAL); 2308 ts->resp = SAS_TASK_UNDELIVERED; 2309 ts->stat = SAS_QUEUE_FULL; 2310 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2311 return; 2312 } 2313 break; 2314 case IO_DS_IN_RECOVERY: 2315 PM8001_IO_DBG(pm8001_ha, 2316 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2317 ts->resp = SAS_TASK_COMPLETE; 2318 ts->stat = SAS_DEV_NO_RESPONSE; 2319 break; 2320 case IO_DS_IN_ERROR: 2321 PM8001_IO_DBG(pm8001_ha, 2322 pm8001_printk("IO_DS_IN_ERROR\n")); 2323 ts->resp = SAS_TASK_COMPLETE; 2324 ts->stat = SAS_DEV_NO_RESPONSE; 2325 if (!t->uldd_task) { 2326 pm8001_handle_event(pm8001_ha, pm8001_dev, 2327 IO_DS_IN_ERROR); 2328 ts->resp = SAS_TASK_UNDELIVERED; 2329 ts->stat = SAS_QUEUE_FULL; 2330 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2331 return; 2332 } 2333 break; 2334 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2335 PM8001_IO_DBG(pm8001_ha, 2336 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2337 ts->resp = SAS_TASK_COMPLETE; 2338 ts->stat = SAS_OPEN_REJECT; 2339 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2340 break; 2341 default: 2342 PM8001_IO_DBG(pm8001_ha, 2343 pm8001_printk("Unknown status 0x%x\n", status)); 2344 /* not allowed case. Therefore, return failed status */ 2345 ts->resp = SAS_TASK_COMPLETE; 2346 ts->stat = SAS_DEV_NO_RESPONSE; 2347 break; 2348 } 2349 spin_lock_irqsave(&t->task_state_lock, flags); 2350 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2351 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2352 t->task_state_flags |= SAS_TASK_STATE_DONE; 2353 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2354 spin_unlock_irqrestore(&t->task_state_lock, flags); 2355 PM8001_FAIL_DBG(pm8001_ha, 2356 pm8001_printk("task 0x%p done with io_status 0x%x" 2357 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2358 t, status, ts->resp, ts->stat)); 2359 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2360 } else { 2361 spin_unlock_irqrestore(&t->task_state_lock, flags); 2362 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2363 } 2364 } 2365 2366 /*See the comments for mpi_ssp_completion */ 2367 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2368 { 2369 struct sas_task *t; 2370 struct task_status_struct *ts; 2371 struct pm8001_ccb_info *ccb; 2372 struct pm8001_device *pm8001_dev; 2373 struct sata_event_resp *psataPayload = 2374 (struct sata_event_resp *)(piomb + 4); 2375 u32 event = le32_to_cpu(psataPayload->event); 2376 u32 tag = le32_to_cpu(psataPayload->tag); 2377 u32 port_id = le32_to_cpu(psataPayload->port_id); 2378 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2379 unsigned long flags; 2380 2381 ccb = &pm8001_ha->ccb_info[tag]; 2382 2383 if (ccb) { 2384 t = ccb->task; 2385 pm8001_dev = ccb->device; 2386 } else { 2387 PM8001_FAIL_DBG(pm8001_ha, 2388 pm8001_printk("No CCB !!!. returning\n")); 2389 return; 2390 } 2391 if (event) 2392 PM8001_FAIL_DBG(pm8001_ha, 2393 pm8001_printk("SATA EVENT 0x%x\n", event)); 2394 2395 /* Check if this is NCQ error */ 2396 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2397 /* find device using device id */ 2398 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2399 /* send read log extension */ 2400 if (pm8001_dev) 2401 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2402 return; 2403 } 2404 2405 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2406 PM8001_FAIL_DBG(pm8001_ha, 2407 pm8001_printk("task or dev null\n")); 2408 return; 2409 } 2410 2411 ts = &t->task_status; 2412 PM8001_IO_DBG(pm8001_ha, 2413 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 2414 port_id, tag, event)); 2415 switch (event) { 2416 case IO_OVERFLOW: 2417 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2418 ts->resp = SAS_TASK_COMPLETE; 2419 ts->stat = SAS_DATA_OVERRUN; 2420 ts->residual = 0; 2421 if (pm8001_dev) 2422 pm8001_dev->running_req--; 2423 break; 2424 case IO_XFER_ERROR_BREAK: 2425 PM8001_IO_DBG(pm8001_ha, 2426 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2427 ts->resp = SAS_TASK_COMPLETE; 2428 ts->stat = SAS_INTERRUPTED; 2429 break; 2430 case IO_XFER_ERROR_PHY_NOT_READY: 2431 PM8001_IO_DBG(pm8001_ha, 2432 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2433 ts->resp = SAS_TASK_COMPLETE; 2434 ts->stat = SAS_OPEN_REJECT; 2435 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2436 break; 2437 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2438 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2439 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2440 ts->resp = SAS_TASK_COMPLETE; 2441 ts->stat = SAS_OPEN_REJECT; 2442 ts->open_rej_reason = SAS_OREJ_EPROTO; 2443 break; 2444 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2445 PM8001_IO_DBG(pm8001_ha, 2446 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2447 ts->resp = SAS_TASK_COMPLETE; 2448 ts->stat = SAS_OPEN_REJECT; 2449 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2450 break; 2451 case IO_OPEN_CNX_ERROR_BREAK: 2452 PM8001_IO_DBG(pm8001_ha, 2453 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2454 ts->resp = SAS_TASK_COMPLETE; 2455 ts->stat = SAS_OPEN_REJECT; 2456 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2457 break; 2458 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2459 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2460 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2461 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2462 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2463 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2464 PM8001_FAIL_DBG(pm8001_ha, 2465 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2466 ts->resp = SAS_TASK_UNDELIVERED; 2467 ts->stat = SAS_DEV_NO_RESPONSE; 2468 if (!t->uldd_task) { 2469 pm8001_handle_event(pm8001_ha, 2470 pm8001_dev, 2471 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2472 ts->resp = SAS_TASK_COMPLETE; 2473 ts->stat = SAS_QUEUE_FULL; 2474 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2475 return; 2476 } 2477 break; 2478 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2479 PM8001_IO_DBG(pm8001_ha, 2480 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2481 ts->resp = SAS_TASK_UNDELIVERED; 2482 ts->stat = SAS_OPEN_REJECT; 2483 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2484 break; 2485 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2486 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2487 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2488 ts->resp = SAS_TASK_COMPLETE; 2489 ts->stat = SAS_OPEN_REJECT; 2490 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2491 break; 2492 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2493 PM8001_IO_DBG(pm8001_ha, 2494 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2495 ts->resp = SAS_TASK_COMPLETE; 2496 ts->stat = SAS_OPEN_REJECT; 2497 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2498 break; 2499 case IO_XFER_ERROR_NAK_RECEIVED: 2500 PM8001_IO_DBG(pm8001_ha, 2501 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2502 ts->resp = SAS_TASK_COMPLETE; 2503 ts->stat = SAS_NAK_R_ERR; 2504 break; 2505 case IO_XFER_ERROR_PEER_ABORTED: 2506 PM8001_IO_DBG(pm8001_ha, 2507 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2508 ts->resp = SAS_TASK_COMPLETE; 2509 ts->stat = SAS_NAK_R_ERR; 2510 break; 2511 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2512 PM8001_IO_DBG(pm8001_ha, 2513 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2514 ts->resp = SAS_TASK_COMPLETE; 2515 ts->stat = SAS_DATA_UNDERRUN; 2516 break; 2517 case IO_XFER_OPEN_RETRY_TIMEOUT: 2518 PM8001_IO_DBG(pm8001_ha, 2519 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2520 ts->resp = SAS_TASK_COMPLETE; 2521 ts->stat = SAS_OPEN_TO; 2522 break; 2523 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2524 PM8001_IO_DBG(pm8001_ha, 2525 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2526 ts->resp = SAS_TASK_COMPLETE; 2527 ts->stat = SAS_OPEN_TO; 2528 break; 2529 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2530 PM8001_IO_DBG(pm8001_ha, 2531 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2532 ts->resp = SAS_TASK_COMPLETE; 2533 ts->stat = SAS_OPEN_TO; 2534 break; 2535 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2536 PM8001_IO_DBG(pm8001_ha, 2537 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2538 ts->resp = SAS_TASK_COMPLETE; 2539 ts->stat = SAS_OPEN_TO; 2540 break; 2541 case IO_XFER_ERROR_OFFSET_MISMATCH: 2542 PM8001_IO_DBG(pm8001_ha, 2543 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2544 ts->resp = SAS_TASK_COMPLETE; 2545 ts->stat = SAS_OPEN_TO; 2546 break; 2547 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2548 PM8001_IO_DBG(pm8001_ha, 2549 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2550 ts->resp = SAS_TASK_COMPLETE; 2551 ts->stat = SAS_OPEN_TO; 2552 break; 2553 case IO_XFER_CMD_FRAME_ISSUED: 2554 PM8001_IO_DBG(pm8001_ha, 2555 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2556 break; 2557 case IO_XFER_PIO_SETUP_ERROR: 2558 PM8001_IO_DBG(pm8001_ha, 2559 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2560 ts->resp = SAS_TASK_COMPLETE; 2561 ts->stat = SAS_OPEN_TO; 2562 break; 2563 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2564 PM8001_FAIL_DBG(pm8001_ha, 2565 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 2566 /* TBC: used default set values */ 2567 ts->resp = SAS_TASK_COMPLETE; 2568 ts->stat = SAS_OPEN_TO; 2569 break; 2570 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2571 PM8001_FAIL_DBG(pm8001_ha, 2572 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n")); 2573 /* TBC: used default set values */ 2574 ts->resp = SAS_TASK_COMPLETE; 2575 ts->stat = SAS_OPEN_TO; 2576 break; 2577 default: 2578 PM8001_IO_DBG(pm8001_ha, 2579 pm8001_printk("Unknown status 0x%x\n", event)); 2580 /* not allowed case. Therefore, return failed status */ 2581 ts->resp = SAS_TASK_COMPLETE; 2582 ts->stat = SAS_OPEN_TO; 2583 break; 2584 } 2585 spin_lock_irqsave(&t->task_state_lock, flags); 2586 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2587 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2588 t->task_state_flags |= SAS_TASK_STATE_DONE; 2589 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2590 spin_unlock_irqrestore(&t->task_state_lock, flags); 2591 PM8001_FAIL_DBG(pm8001_ha, 2592 pm8001_printk("task 0x%p done with io_status 0x%x" 2593 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2594 t, event, ts->resp, ts->stat)); 2595 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2596 } else { 2597 spin_unlock_irqrestore(&t->task_state_lock, flags); 2598 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2599 } 2600 } 2601 2602 /*See the comments for mpi_ssp_completion */ 2603 static void 2604 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2605 { 2606 u32 param, i; 2607 struct sas_task *t; 2608 struct pm8001_ccb_info *ccb; 2609 unsigned long flags; 2610 u32 status; 2611 u32 tag; 2612 struct smp_completion_resp *psmpPayload; 2613 struct task_status_struct *ts; 2614 struct pm8001_device *pm8001_dev; 2615 char *pdma_respaddr = NULL; 2616 2617 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2618 status = le32_to_cpu(psmpPayload->status); 2619 tag = le32_to_cpu(psmpPayload->tag); 2620 2621 ccb = &pm8001_ha->ccb_info[tag]; 2622 param = le32_to_cpu(psmpPayload->param); 2623 t = ccb->task; 2624 ts = &t->task_status; 2625 pm8001_dev = ccb->device; 2626 if (status) 2627 PM8001_FAIL_DBG(pm8001_ha, 2628 pm8001_printk("smp IO status 0x%x\n", status)); 2629 if (unlikely(!t || !t->lldd_task || !t->dev)) 2630 return; 2631 2632 switch (status) { 2633 2634 case IO_SUCCESS: 2635 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2636 ts->resp = SAS_TASK_COMPLETE; 2637 ts->stat = SAM_STAT_GOOD; 2638 if (pm8001_dev) 2639 pm8001_dev->running_req--; 2640 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2641 PM8001_IO_DBG(pm8001_ha, 2642 pm8001_printk("DIRECT RESPONSE Length:%d\n", 2643 param)); 2644 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 2645 ((u64)sg_dma_address 2646 (&t->smp_task.smp_resp)))); 2647 for (i = 0; i < param; i++) { 2648 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 2649 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2650 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2651 i, *(pdma_respaddr+i), 2652 psmpPayload->_r_a[i])); 2653 } 2654 } 2655 break; 2656 case IO_ABORTED: 2657 PM8001_IO_DBG(pm8001_ha, 2658 pm8001_printk("IO_ABORTED IOMB\n")); 2659 ts->resp = SAS_TASK_COMPLETE; 2660 ts->stat = SAS_ABORTED_TASK; 2661 if (pm8001_dev) 2662 pm8001_dev->running_req--; 2663 break; 2664 case IO_OVERFLOW: 2665 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2666 ts->resp = SAS_TASK_COMPLETE; 2667 ts->stat = SAS_DATA_OVERRUN; 2668 ts->residual = 0; 2669 if (pm8001_dev) 2670 pm8001_dev->running_req--; 2671 break; 2672 case IO_NO_DEVICE: 2673 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2674 ts->resp = SAS_TASK_COMPLETE; 2675 ts->stat = SAS_PHY_DOWN; 2676 break; 2677 case IO_ERROR_HW_TIMEOUT: 2678 PM8001_IO_DBG(pm8001_ha, 2679 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2680 ts->resp = SAS_TASK_COMPLETE; 2681 ts->stat = SAM_STAT_BUSY; 2682 break; 2683 case IO_XFER_ERROR_BREAK: 2684 PM8001_IO_DBG(pm8001_ha, 2685 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2686 ts->resp = SAS_TASK_COMPLETE; 2687 ts->stat = SAM_STAT_BUSY; 2688 break; 2689 case IO_XFER_ERROR_PHY_NOT_READY: 2690 PM8001_IO_DBG(pm8001_ha, 2691 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2692 ts->resp = SAS_TASK_COMPLETE; 2693 ts->stat = SAM_STAT_BUSY; 2694 break; 2695 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2696 PM8001_IO_DBG(pm8001_ha, 2697 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2698 ts->resp = SAS_TASK_COMPLETE; 2699 ts->stat = SAS_OPEN_REJECT; 2700 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2701 break; 2702 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2703 PM8001_IO_DBG(pm8001_ha, 2704 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2705 ts->resp = SAS_TASK_COMPLETE; 2706 ts->stat = SAS_OPEN_REJECT; 2707 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2708 break; 2709 case IO_OPEN_CNX_ERROR_BREAK: 2710 PM8001_IO_DBG(pm8001_ha, 2711 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2712 ts->resp = SAS_TASK_COMPLETE; 2713 ts->stat = SAS_OPEN_REJECT; 2714 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2715 break; 2716 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2717 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2718 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2719 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2720 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2721 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2722 PM8001_IO_DBG(pm8001_ha, 2723 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2724 ts->resp = SAS_TASK_COMPLETE; 2725 ts->stat = SAS_OPEN_REJECT; 2726 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2727 pm8001_handle_event(pm8001_ha, 2728 pm8001_dev, 2729 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2730 break; 2731 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2732 PM8001_IO_DBG(pm8001_ha, 2733 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2734 ts->resp = SAS_TASK_COMPLETE; 2735 ts->stat = SAS_OPEN_REJECT; 2736 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2737 break; 2738 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2739 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\ 2740 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2741 ts->resp = SAS_TASK_COMPLETE; 2742 ts->stat = SAS_OPEN_REJECT; 2743 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2744 break; 2745 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2746 PM8001_IO_DBG(pm8001_ha, 2747 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2748 ts->resp = SAS_TASK_COMPLETE; 2749 ts->stat = SAS_OPEN_REJECT; 2750 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2751 break; 2752 case IO_XFER_ERROR_RX_FRAME: 2753 PM8001_IO_DBG(pm8001_ha, 2754 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 2755 ts->resp = SAS_TASK_COMPLETE; 2756 ts->stat = SAS_DEV_NO_RESPONSE; 2757 break; 2758 case IO_XFER_OPEN_RETRY_TIMEOUT: 2759 PM8001_IO_DBG(pm8001_ha, 2760 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2761 ts->resp = SAS_TASK_COMPLETE; 2762 ts->stat = SAS_OPEN_REJECT; 2763 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2764 break; 2765 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2766 PM8001_IO_DBG(pm8001_ha, 2767 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 2768 ts->resp = SAS_TASK_COMPLETE; 2769 ts->stat = SAS_QUEUE_FULL; 2770 break; 2771 case IO_PORT_IN_RESET: 2772 PM8001_IO_DBG(pm8001_ha, 2773 pm8001_printk("IO_PORT_IN_RESET\n")); 2774 ts->resp = SAS_TASK_COMPLETE; 2775 ts->stat = SAS_OPEN_REJECT; 2776 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2777 break; 2778 case IO_DS_NON_OPERATIONAL: 2779 PM8001_IO_DBG(pm8001_ha, 2780 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2781 ts->resp = SAS_TASK_COMPLETE; 2782 ts->stat = SAS_DEV_NO_RESPONSE; 2783 break; 2784 case IO_DS_IN_RECOVERY: 2785 PM8001_IO_DBG(pm8001_ha, 2786 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2787 ts->resp = SAS_TASK_COMPLETE; 2788 ts->stat = SAS_OPEN_REJECT; 2789 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2790 break; 2791 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2792 PM8001_IO_DBG(pm8001_ha, 2793 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2794 ts->resp = SAS_TASK_COMPLETE; 2795 ts->stat = SAS_OPEN_REJECT; 2796 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2797 break; 2798 default: 2799 PM8001_IO_DBG(pm8001_ha, 2800 pm8001_printk("Unknown status 0x%x\n", status)); 2801 ts->resp = SAS_TASK_COMPLETE; 2802 ts->stat = SAS_DEV_NO_RESPONSE; 2803 /* not allowed case. Therefore, return failed status */ 2804 break; 2805 } 2806 spin_lock_irqsave(&t->task_state_lock, flags); 2807 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2808 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2809 t->task_state_flags |= SAS_TASK_STATE_DONE; 2810 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2811 spin_unlock_irqrestore(&t->task_state_lock, flags); 2812 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 2813 "task 0x%p done with io_status 0x%x resp 0x%x" 2814 "stat 0x%x but aborted by upper layer!\n", 2815 t, status, ts->resp, ts->stat)); 2816 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2817 } else { 2818 spin_unlock_irqrestore(&t->task_state_lock, flags); 2819 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2820 mb();/* in order to force CPU ordering */ 2821 t->task_done(t); 2822 } 2823 } 2824 2825 /** 2826 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 2827 * @pm8001_ha: our hba card information 2828 * @Qnum: the outbound queue message number. 2829 * @SEA: source of event to ack 2830 * @port_id: port id. 2831 * @phyId: phy id. 2832 * @param0: parameter 0. 2833 * @param1: parameter 1. 2834 */ 2835 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 2836 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 2837 { 2838 struct hw_event_ack_req payload; 2839 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 2840 2841 struct inbound_queue_table *circularQ; 2842 2843 memset((u8 *)&payload, 0, sizeof(payload)); 2844 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 2845 payload.tag = cpu_to_le32(1); 2846 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 2847 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 2848 payload.param0 = cpu_to_le32(param0); 2849 payload.param1 = cpu_to_le32(param1); 2850 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 2851 } 2852 2853 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 2854 u32 phyId, u32 phy_op); 2855 2856 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 2857 void *piomb) 2858 { 2859 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 2860 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2861 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2862 u32 lr_status_evt_portid = 2863 le32_to_cpu(pPayload->lr_status_evt_portid); 2864 u8 deviceType = pPayload->sas_identify.dev_type; 2865 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2866 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2867 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2868 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2869 2870 if (deviceType == SAS_END_DEVICE) { 2871 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 2872 PHY_NOTIFY_ENABLE_SPINUP); 2873 } 2874 2875 port->wide_port_phymap |= (1U << phy_id); 2876 pm8001_get_lrate_mode(phy, link_rate); 2877 phy->sas_phy.oob_mode = SAS_OOB_MODE; 2878 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 2879 phy->phy_attached = 1; 2880 } 2881 2882 /** 2883 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 2884 * @pm8001_ha: our hba card information 2885 * @piomb: IO message buffer 2886 */ 2887 static void 2888 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2889 { 2890 struct hw_event_resp *pPayload = 2891 (struct hw_event_resp *)(piomb + 4); 2892 u32 lr_status_evt_portid = 2893 le32_to_cpu(pPayload->lr_status_evt_portid); 2894 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2895 2896 u8 link_rate = 2897 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2898 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2899 u8 phy_id = 2900 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2901 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2902 2903 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2904 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2905 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2906 unsigned long flags; 2907 u8 deviceType = pPayload->sas_identify.dev_type; 2908 port->port_state = portstate; 2909 port->wide_port_phymap |= (1U << phy_id); 2910 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 2911 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2912 "portid:%d; phyid:%d; linkrate:%d; " 2913 "portstate:%x; devicetype:%x\n", 2914 port_id, phy_id, link_rate, portstate, deviceType)); 2915 2916 switch (deviceType) { 2917 case SAS_PHY_UNUSED: 2918 PM8001_MSG_DBG(pm8001_ha, 2919 pm8001_printk("device type no device.\n")); 2920 break; 2921 case SAS_END_DEVICE: 2922 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 2923 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 2924 PHY_NOTIFY_ENABLE_SPINUP); 2925 port->port_attached = 1; 2926 pm8001_get_lrate_mode(phy, link_rate); 2927 break; 2928 case SAS_EDGE_EXPANDER_DEVICE: 2929 PM8001_MSG_DBG(pm8001_ha, 2930 pm8001_printk("expander device.\n")); 2931 port->port_attached = 1; 2932 pm8001_get_lrate_mode(phy, link_rate); 2933 break; 2934 case SAS_FANOUT_EXPANDER_DEVICE: 2935 PM8001_MSG_DBG(pm8001_ha, 2936 pm8001_printk("fanout expander device.\n")); 2937 port->port_attached = 1; 2938 pm8001_get_lrate_mode(phy, link_rate); 2939 break; 2940 default: 2941 PM8001_MSG_DBG(pm8001_ha, 2942 pm8001_printk("unknown device type(%x)\n", deviceType)); 2943 break; 2944 } 2945 phy->phy_type |= PORT_TYPE_SAS; 2946 phy->identify.device_type = deviceType; 2947 phy->phy_attached = 1; 2948 if (phy->identify.device_type == SAS_END_DEVICE) 2949 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 2950 else if (phy->identify.device_type != SAS_PHY_UNUSED) 2951 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 2952 phy->sas_phy.oob_mode = SAS_OOB_MODE; 2953 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2954 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2955 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 2956 sizeof(struct sas_identify_frame)-4); 2957 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 2958 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2959 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2960 if (pm8001_ha->flags == PM8001F_RUN_TIME) 2961 mdelay(200);/*delay a moment to wait disk to spinup*/ 2962 pm8001_bytes_dmaed(pm8001_ha, phy_id); 2963 } 2964 2965 /** 2966 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 2967 * @pm8001_ha: our hba card information 2968 * @piomb: IO message buffer 2969 */ 2970 static void 2971 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2972 { 2973 struct hw_event_resp *pPayload = 2974 (struct hw_event_resp *)(piomb + 4); 2975 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2976 u32 lr_status_evt_portid = 2977 le32_to_cpu(pPayload->lr_status_evt_portid); 2978 u8 link_rate = 2979 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2980 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2981 u8 phy_id = 2982 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2983 2984 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2985 2986 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2987 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2988 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2989 unsigned long flags; 2990 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2991 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 2992 port_id, phy_id, link_rate, portstate)); 2993 2994 port->port_state = portstate; 2995 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 2996 port->port_attached = 1; 2997 pm8001_get_lrate_mode(phy, link_rate); 2998 phy->phy_type |= PORT_TYPE_SATA; 2999 phy->phy_attached = 1; 3000 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3001 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3002 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3003 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3004 sizeof(struct dev_to_host_fis)); 3005 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3006 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3007 phy->identify.device_type = SAS_SATA_DEV; 3008 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3009 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3010 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3011 } 3012 3013 /** 3014 * hw_event_phy_down -we should notify the libsas the phy is down. 3015 * @pm8001_ha: our hba card information 3016 * @piomb: IO message buffer 3017 */ 3018 static void 3019 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3020 { 3021 struct hw_event_resp *pPayload = 3022 (struct hw_event_resp *)(piomb + 4); 3023 3024 u32 lr_status_evt_portid = 3025 le32_to_cpu(pPayload->lr_status_evt_portid); 3026 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3027 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3028 u8 phy_id = 3029 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3030 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3031 3032 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3033 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3034 port->port_state = portstate; 3035 phy->identify.device_type = 0; 3036 phy->phy_attached = 0; 3037 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3038 switch (portstate) { 3039 case PORT_VALID: 3040 break; 3041 case PORT_INVALID: 3042 PM8001_MSG_DBG(pm8001_ha, 3043 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3044 PM8001_MSG_DBG(pm8001_ha, 3045 pm8001_printk(" Last phy Down and port invalid\n")); 3046 if (phy->phy_type & PORT_TYPE_SATA) { 3047 phy->phy_type = 0; 3048 port->port_attached = 0; 3049 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3050 port_id, phy_id, 0, 0); 3051 } 3052 sas_phy_disconnected(&phy->sas_phy); 3053 break; 3054 case PORT_IN_RESET: 3055 PM8001_MSG_DBG(pm8001_ha, 3056 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3057 break; 3058 case PORT_NOT_ESTABLISHED: 3059 PM8001_MSG_DBG(pm8001_ha, 3060 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n")); 3061 port->port_attached = 0; 3062 break; 3063 case PORT_LOSTCOMM: 3064 PM8001_MSG_DBG(pm8001_ha, 3065 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n")); 3066 PM8001_MSG_DBG(pm8001_ha, 3067 pm8001_printk(" Last phy Down and port invalid\n")); 3068 if (phy->phy_type & PORT_TYPE_SATA) { 3069 port->port_attached = 0; 3070 phy->phy_type = 0; 3071 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3072 port_id, phy_id, 0, 0); 3073 } 3074 sas_phy_disconnected(&phy->sas_phy); 3075 break; 3076 default: 3077 port->port_attached = 0; 3078 PM8001_MSG_DBG(pm8001_ha, 3079 pm8001_printk(" Phy Down and(default) = 0x%x\n", 3080 portstate)); 3081 break; 3082 3083 } 3084 } 3085 3086 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3087 { 3088 struct phy_start_resp *pPayload = 3089 (struct phy_start_resp *)(piomb + 4); 3090 u32 status = 3091 le32_to_cpu(pPayload->status); 3092 u32 phy_id = 3093 le32_to_cpu(pPayload->phyid); 3094 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3095 3096 PM8001_INIT_DBG(pm8001_ha, 3097 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n", 3098 status, phy_id)); 3099 if (status == 0) { 3100 phy->phy_state = 1; 3101 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3102 complete(phy->enable_completion); 3103 } 3104 return 0; 3105 3106 } 3107 3108 /** 3109 * mpi_thermal_hw_event -The hw event has come. 3110 * @pm8001_ha: our hba card information 3111 * @piomb: IO message buffer 3112 */ 3113 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3114 { 3115 struct thermal_hw_event *pPayload = 3116 (struct thermal_hw_event *)(piomb + 4); 3117 3118 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3119 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3120 3121 if (thermal_event & 0x40) { 3122 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3123 "Thermal Event: Local high temperature violated!\n")); 3124 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3125 "Thermal Event: Measured local high temperature %d\n", 3126 ((rht_lht & 0xFF00) >> 8))); 3127 } 3128 if (thermal_event & 0x10) { 3129 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3130 "Thermal Event: Remote high temperature violated!\n")); 3131 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3132 "Thermal Event: Measured remote high temperature %d\n", 3133 ((rht_lht & 0xFF000000) >> 24))); 3134 } 3135 return 0; 3136 } 3137 3138 /** 3139 * mpi_hw_event -The hw event has come. 3140 * @pm8001_ha: our hba card information 3141 * @piomb: IO message buffer 3142 */ 3143 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3144 { 3145 unsigned long flags, i; 3146 struct hw_event_resp *pPayload = 3147 (struct hw_event_resp *)(piomb + 4); 3148 u32 lr_status_evt_portid = 3149 le32_to_cpu(pPayload->lr_status_evt_portid); 3150 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3151 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3152 u8 phy_id = 3153 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3154 u16 eventType = 3155 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3156 u8 status = 3157 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3158 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3159 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3160 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3161 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3162 PM8001_MSG_DBG(pm8001_ha, 3163 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n", 3164 port_id, phy_id, eventType, status)); 3165 3166 switch (eventType) { 3167 3168 case HW_EVENT_SAS_PHY_UP: 3169 PM8001_MSG_DBG(pm8001_ha, 3170 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3171 hw_event_sas_phy_up(pm8001_ha, piomb); 3172 break; 3173 case HW_EVENT_SATA_PHY_UP: 3174 PM8001_MSG_DBG(pm8001_ha, 3175 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3176 hw_event_sata_phy_up(pm8001_ha, piomb); 3177 break; 3178 case HW_EVENT_SATA_SPINUP_HOLD: 3179 PM8001_MSG_DBG(pm8001_ha, 3180 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3181 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3182 break; 3183 case HW_EVENT_PHY_DOWN: 3184 PM8001_MSG_DBG(pm8001_ha, 3185 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3186 if (phy->phy_type & PORT_TYPE_SATA) 3187 sas_ha->notify_phy_event(&phy->sas_phy, 3188 PHYE_LOSS_OF_SIGNAL); 3189 phy->phy_attached = 0; 3190 phy->phy_state = 0; 3191 hw_event_phy_down(pm8001_ha, piomb); 3192 break; 3193 case HW_EVENT_PORT_INVALID: 3194 PM8001_MSG_DBG(pm8001_ha, 3195 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3196 sas_phy_disconnected(sas_phy); 3197 phy->phy_attached = 0; 3198 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3199 break; 3200 /* the broadcast change primitive received, tell the LIBSAS this event 3201 to revalidate the sas domain*/ 3202 case HW_EVENT_BROADCAST_CHANGE: 3203 PM8001_MSG_DBG(pm8001_ha, 3204 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3205 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3206 port_id, phy_id, 1, 0); 3207 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3208 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3209 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3210 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3211 break; 3212 case HW_EVENT_PHY_ERROR: 3213 PM8001_MSG_DBG(pm8001_ha, 3214 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3215 sas_phy_disconnected(&phy->sas_phy); 3216 phy->phy_attached = 0; 3217 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3218 break; 3219 case HW_EVENT_BROADCAST_EXP: 3220 PM8001_MSG_DBG(pm8001_ha, 3221 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3222 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3223 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3224 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3225 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3226 break; 3227 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3228 PM8001_MSG_DBG(pm8001_ha, 3229 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3230 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3231 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3232 break; 3233 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3234 PM8001_MSG_DBG(pm8001_ha, 3235 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3236 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3237 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3238 port_id, phy_id, 0, 0); 3239 break; 3240 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3241 PM8001_MSG_DBG(pm8001_ha, 3242 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3243 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3244 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3245 port_id, phy_id, 0, 0); 3246 break; 3247 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3248 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3249 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3250 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3251 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3252 port_id, phy_id, 0, 0); 3253 break; 3254 case HW_EVENT_MALFUNCTION: 3255 PM8001_MSG_DBG(pm8001_ha, 3256 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3257 break; 3258 case HW_EVENT_BROADCAST_SES: 3259 PM8001_MSG_DBG(pm8001_ha, 3260 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3261 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3262 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3263 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3264 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3265 break; 3266 case HW_EVENT_INBOUND_CRC_ERROR: 3267 PM8001_MSG_DBG(pm8001_ha, 3268 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3269 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3270 HW_EVENT_INBOUND_CRC_ERROR, 3271 port_id, phy_id, 0, 0); 3272 break; 3273 case HW_EVENT_HARD_RESET_RECEIVED: 3274 PM8001_MSG_DBG(pm8001_ha, 3275 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3276 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3277 break; 3278 case HW_EVENT_ID_FRAME_TIMEOUT: 3279 PM8001_MSG_DBG(pm8001_ha, 3280 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3281 sas_phy_disconnected(sas_phy); 3282 phy->phy_attached = 0; 3283 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3284 break; 3285 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3286 PM8001_MSG_DBG(pm8001_ha, 3287 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3288 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3289 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3290 port_id, phy_id, 0, 0); 3291 sas_phy_disconnected(sas_phy); 3292 phy->phy_attached = 0; 3293 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3294 break; 3295 case HW_EVENT_PORT_RESET_TIMER_TMO: 3296 PM8001_MSG_DBG(pm8001_ha, 3297 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3298 sas_phy_disconnected(sas_phy); 3299 phy->phy_attached = 0; 3300 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3301 break; 3302 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3303 PM8001_MSG_DBG(pm8001_ha, 3304 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3305 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3306 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3307 port_id, phy_id, 0, 0); 3308 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3309 if (port->wide_port_phymap & (1 << i)) { 3310 phy = &pm8001_ha->phy[i]; 3311 sas_ha->notify_phy_event(&phy->sas_phy, 3312 PHYE_LOSS_OF_SIGNAL); 3313 port->wide_port_phymap &= ~(1 << i); 3314 } 3315 } 3316 break; 3317 case HW_EVENT_PORT_RECOVER: 3318 PM8001_MSG_DBG(pm8001_ha, 3319 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3320 hw_event_port_recover(pm8001_ha, piomb); 3321 break; 3322 case HW_EVENT_PORT_RESET_COMPLETE: 3323 PM8001_MSG_DBG(pm8001_ha, 3324 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3325 break; 3326 case EVENT_BROADCAST_ASYNCH_EVENT: 3327 PM8001_MSG_DBG(pm8001_ha, 3328 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3329 break; 3330 default: 3331 PM8001_MSG_DBG(pm8001_ha, 3332 pm8001_printk("Unknown event type 0x%x\n", eventType)); 3333 break; 3334 } 3335 return 0; 3336 } 3337 3338 /** 3339 * mpi_phy_stop_resp - SPCv specific 3340 * @pm8001_ha: our hba card information 3341 * @piomb: IO message buffer 3342 */ 3343 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3344 { 3345 struct phy_stop_resp *pPayload = 3346 (struct phy_stop_resp *)(piomb + 4); 3347 u32 status = 3348 le32_to_cpu(pPayload->status); 3349 u32 phyid = 3350 le32_to_cpu(pPayload->phyid); 3351 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3352 PM8001_MSG_DBG(pm8001_ha, 3353 pm8001_printk("phy:0x%x status:0x%x\n", 3354 phyid, status)); 3355 if (status == 0) 3356 phy->phy_state = 0; 3357 return 0; 3358 } 3359 3360 /** 3361 * mpi_set_controller_config_resp - SPCv specific 3362 * @pm8001_ha: our hba card information 3363 * @piomb: IO message buffer 3364 */ 3365 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3366 void *piomb) 3367 { 3368 struct set_ctrl_cfg_resp *pPayload = 3369 (struct set_ctrl_cfg_resp *)(piomb + 4); 3370 u32 status = le32_to_cpu(pPayload->status); 3371 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3372 3373 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3374 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3375 status, err_qlfr_pgcd)); 3376 3377 return 0; 3378 } 3379 3380 /** 3381 * mpi_get_controller_config_resp - SPCv specific 3382 * @pm8001_ha: our hba card information 3383 * @piomb: IO message buffer 3384 */ 3385 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3386 void *piomb) 3387 { 3388 PM8001_MSG_DBG(pm8001_ha, 3389 pm8001_printk(" pm80xx_addition_functionality\n")); 3390 3391 return 0; 3392 } 3393 3394 /** 3395 * mpi_get_phy_profile_resp - SPCv specific 3396 * @pm8001_ha: our hba card information 3397 * @piomb: IO message buffer 3398 */ 3399 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3400 void *piomb) 3401 { 3402 PM8001_MSG_DBG(pm8001_ha, 3403 pm8001_printk(" pm80xx_addition_functionality\n")); 3404 3405 return 0; 3406 } 3407 3408 /** 3409 * mpi_flash_op_ext_resp - SPCv specific 3410 * @pm8001_ha: our hba card information 3411 * @piomb: IO message buffer 3412 */ 3413 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3414 { 3415 PM8001_MSG_DBG(pm8001_ha, 3416 pm8001_printk(" pm80xx_addition_functionality\n")); 3417 3418 return 0; 3419 } 3420 3421 /** 3422 * mpi_set_phy_profile_resp - SPCv specific 3423 * @pm8001_ha: our hba card information 3424 * @piomb: IO message buffer 3425 */ 3426 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3427 void *piomb) 3428 { 3429 u8 page_code; 3430 struct set_phy_profile_resp *pPayload = 3431 (struct set_phy_profile_resp *)(piomb + 4); 3432 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3433 u32 status = le32_to_cpu(pPayload->status); 3434 3435 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3436 if (status) { 3437 /* status is FAILED */ 3438 PM8001_FAIL_DBG(pm8001_ha, 3439 pm8001_printk("PhyProfile command failed with status " 3440 "0x%08X \n", status)); 3441 return -1; 3442 } else { 3443 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3444 PM8001_FAIL_DBG(pm8001_ha, 3445 pm8001_printk("Invalid page code 0x%X\n", 3446 page_code)); 3447 return -1; 3448 } 3449 } 3450 return 0; 3451 } 3452 3453 /** 3454 * mpi_kek_management_resp - SPCv specific 3455 * @pm8001_ha: our hba card information 3456 * @piomb: IO message buffer 3457 */ 3458 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3459 void *piomb) 3460 { 3461 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3462 3463 u32 status = le32_to_cpu(pPayload->status); 3464 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3465 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3466 3467 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3468 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3469 status, kidx_new_curr_ksop, err_qlfr)); 3470 3471 return 0; 3472 } 3473 3474 /** 3475 * mpi_dek_management_resp - SPCv specific 3476 * @pm8001_ha: our hba card information 3477 * @piomb: IO message buffer 3478 */ 3479 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3480 void *piomb) 3481 { 3482 PM8001_MSG_DBG(pm8001_ha, 3483 pm8001_printk(" pm80xx_addition_functionality\n")); 3484 3485 return 0; 3486 } 3487 3488 /** 3489 * ssp_coalesced_comp_resp - SPCv specific 3490 * @pm8001_ha: our hba card information 3491 * @piomb: IO message buffer 3492 */ 3493 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3494 void *piomb) 3495 { 3496 PM8001_MSG_DBG(pm8001_ha, 3497 pm8001_printk(" pm80xx_addition_functionality\n")); 3498 3499 return 0; 3500 } 3501 3502 /** 3503 * process_one_iomb - process one outbound Queue memory block 3504 * @pm8001_ha: our hba card information 3505 * @piomb: IO message buffer 3506 */ 3507 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3508 { 3509 __le32 pHeader = *(__le32 *)piomb; 3510 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3511 3512 switch (opc) { 3513 case OPC_OUB_ECHO: 3514 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3515 break; 3516 case OPC_OUB_HW_EVENT: 3517 PM8001_MSG_DBG(pm8001_ha, 3518 pm8001_printk("OPC_OUB_HW_EVENT\n")); 3519 mpi_hw_event(pm8001_ha, piomb); 3520 break; 3521 case OPC_OUB_THERM_HW_EVENT: 3522 PM8001_MSG_DBG(pm8001_ha, 3523 pm8001_printk("OPC_OUB_THERMAL_EVENT\n")); 3524 mpi_thermal_hw_event(pm8001_ha, piomb); 3525 break; 3526 case OPC_OUB_SSP_COMP: 3527 PM8001_MSG_DBG(pm8001_ha, 3528 pm8001_printk("OPC_OUB_SSP_COMP\n")); 3529 mpi_ssp_completion(pm8001_ha, piomb); 3530 break; 3531 case OPC_OUB_SMP_COMP: 3532 PM8001_MSG_DBG(pm8001_ha, 3533 pm8001_printk("OPC_OUB_SMP_COMP\n")); 3534 mpi_smp_completion(pm8001_ha, piomb); 3535 break; 3536 case OPC_OUB_LOCAL_PHY_CNTRL: 3537 PM8001_MSG_DBG(pm8001_ha, 3538 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3539 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3540 break; 3541 case OPC_OUB_DEV_REGIST: 3542 PM8001_MSG_DBG(pm8001_ha, 3543 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 3544 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3545 break; 3546 case OPC_OUB_DEREG_DEV: 3547 PM8001_MSG_DBG(pm8001_ha, 3548 pm8001_printk("unregister the device\n")); 3549 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3550 break; 3551 case OPC_OUB_GET_DEV_HANDLE: 3552 PM8001_MSG_DBG(pm8001_ha, 3553 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 3554 break; 3555 case OPC_OUB_SATA_COMP: 3556 PM8001_MSG_DBG(pm8001_ha, 3557 pm8001_printk("OPC_OUB_SATA_COMP\n")); 3558 mpi_sata_completion(pm8001_ha, piomb); 3559 break; 3560 case OPC_OUB_SATA_EVENT: 3561 PM8001_MSG_DBG(pm8001_ha, 3562 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 3563 mpi_sata_event(pm8001_ha, piomb); 3564 break; 3565 case OPC_OUB_SSP_EVENT: 3566 PM8001_MSG_DBG(pm8001_ha, 3567 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3568 mpi_ssp_event(pm8001_ha, piomb); 3569 break; 3570 case OPC_OUB_DEV_HANDLE_ARRIV: 3571 PM8001_MSG_DBG(pm8001_ha, 3572 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3573 /*This is for target*/ 3574 break; 3575 case OPC_OUB_SSP_RECV_EVENT: 3576 PM8001_MSG_DBG(pm8001_ha, 3577 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3578 /*This is for target*/ 3579 break; 3580 case OPC_OUB_FW_FLASH_UPDATE: 3581 PM8001_MSG_DBG(pm8001_ha, 3582 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3583 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3584 break; 3585 case OPC_OUB_GPIO_RESPONSE: 3586 PM8001_MSG_DBG(pm8001_ha, 3587 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3588 break; 3589 case OPC_OUB_GPIO_EVENT: 3590 PM8001_MSG_DBG(pm8001_ha, 3591 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3592 break; 3593 case OPC_OUB_GENERAL_EVENT: 3594 PM8001_MSG_DBG(pm8001_ha, 3595 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3596 pm8001_mpi_general_event(pm8001_ha, piomb); 3597 break; 3598 case OPC_OUB_SSP_ABORT_RSP: 3599 PM8001_MSG_DBG(pm8001_ha, 3600 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3601 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3602 break; 3603 case OPC_OUB_SATA_ABORT_RSP: 3604 PM8001_MSG_DBG(pm8001_ha, 3605 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3606 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3607 break; 3608 case OPC_OUB_SAS_DIAG_MODE_START_END: 3609 PM8001_MSG_DBG(pm8001_ha, 3610 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3611 break; 3612 case OPC_OUB_SAS_DIAG_EXECUTE: 3613 PM8001_MSG_DBG(pm8001_ha, 3614 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3615 break; 3616 case OPC_OUB_GET_TIME_STAMP: 3617 PM8001_MSG_DBG(pm8001_ha, 3618 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3619 break; 3620 case OPC_OUB_SAS_HW_EVENT_ACK: 3621 PM8001_MSG_DBG(pm8001_ha, 3622 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3623 break; 3624 case OPC_OUB_PORT_CONTROL: 3625 PM8001_MSG_DBG(pm8001_ha, 3626 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3627 break; 3628 case OPC_OUB_SMP_ABORT_RSP: 3629 PM8001_MSG_DBG(pm8001_ha, 3630 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3631 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3632 break; 3633 case OPC_OUB_GET_NVMD_DATA: 3634 PM8001_MSG_DBG(pm8001_ha, 3635 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3636 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3637 break; 3638 case OPC_OUB_SET_NVMD_DATA: 3639 PM8001_MSG_DBG(pm8001_ha, 3640 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3641 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3642 break; 3643 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3644 PM8001_MSG_DBG(pm8001_ha, 3645 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3646 break; 3647 case OPC_OUB_SET_DEVICE_STATE: 3648 PM8001_MSG_DBG(pm8001_ha, 3649 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3650 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3651 break; 3652 case OPC_OUB_GET_DEVICE_STATE: 3653 PM8001_MSG_DBG(pm8001_ha, 3654 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3655 break; 3656 case OPC_OUB_SET_DEV_INFO: 3657 PM8001_MSG_DBG(pm8001_ha, 3658 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3659 break; 3660 /* spcv specifc commands */ 3661 case OPC_OUB_PHY_START_RESP: 3662 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3663 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc)); 3664 mpi_phy_start_resp(pm8001_ha, piomb); 3665 break; 3666 case OPC_OUB_PHY_STOP_RESP: 3667 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3668 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc)); 3669 mpi_phy_stop_resp(pm8001_ha, piomb); 3670 break; 3671 case OPC_OUB_SET_CONTROLLER_CONFIG: 3672 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3673 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3674 mpi_set_controller_config_resp(pm8001_ha, piomb); 3675 break; 3676 case OPC_OUB_GET_CONTROLLER_CONFIG: 3677 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3678 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3679 mpi_get_controller_config_resp(pm8001_ha, piomb); 3680 break; 3681 case OPC_OUB_GET_PHY_PROFILE: 3682 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3683 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc)); 3684 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3685 break; 3686 case OPC_OUB_FLASH_OP_EXT: 3687 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3688 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc)); 3689 mpi_flash_op_ext_resp(pm8001_ha, piomb); 3690 break; 3691 case OPC_OUB_SET_PHY_PROFILE: 3692 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3693 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc)); 3694 mpi_set_phy_profile_resp(pm8001_ha, piomb); 3695 break; 3696 case OPC_OUB_KEK_MANAGEMENT_RESP: 3697 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3698 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3699 mpi_kek_management_resp(pm8001_ha, piomb); 3700 break; 3701 case OPC_OUB_DEK_MANAGEMENT_RESP: 3702 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3703 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3704 mpi_dek_management_resp(pm8001_ha, piomb); 3705 break; 3706 case OPC_OUB_SSP_COALESCED_COMP_RESP: 3707 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3708 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc)); 3709 ssp_coalesced_comp_resp(pm8001_ha, piomb); 3710 break; 3711 default: 3712 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3713 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc)); 3714 break; 3715 } 3716 } 3717 3718 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 3719 { 3720 struct outbound_queue_table *circularQ; 3721 void *pMsg1 = NULL; 3722 u8 uninitialized_var(bc); 3723 u32 ret = MPI_IO_STATUS_FAIL; 3724 unsigned long flags; 3725 3726 spin_lock_irqsave(&pm8001_ha->lock, flags); 3727 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 3728 do { 3729 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3730 if (MPI_IO_STATUS_SUCCESS == ret) { 3731 /* process the outbound message */ 3732 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3733 /* free the message from the outbound circular buffer */ 3734 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 3735 circularQ, bc); 3736 } 3737 if (MPI_IO_STATUS_BUSY == ret) { 3738 /* Update the producer index from SPC */ 3739 circularQ->producer_index = 3740 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3741 if (le32_to_cpu(circularQ->producer_index) == 3742 circularQ->consumer_idx) 3743 /* OQ is empty */ 3744 break; 3745 } 3746 } while (1); 3747 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3748 return ret; 3749 } 3750 3751 /* PCI_DMA_... to our direction translation. */ 3752 static const u8 data_dir_flags[] = { 3753 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ 3754 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ 3755 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ 3756 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ 3757 }; 3758 3759 static void build_smp_cmd(u32 deviceID, __le32 hTag, 3760 struct smp_req *psmp_cmd, int mode, int length) 3761 { 3762 psmp_cmd->tag = hTag; 3763 psmp_cmd->device_id = cpu_to_le32(deviceID); 3764 if (mode == SMP_DIRECT) { 3765 length = length - 4; /* subtract crc */ 3766 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 3767 } else { 3768 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3769 } 3770 } 3771 3772 /** 3773 * pm8001_chip_smp_req - send a SMP task to FW 3774 * @pm8001_ha: our hba card information. 3775 * @ccb: the ccb information this request used. 3776 */ 3777 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3778 struct pm8001_ccb_info *ccb) 3779 { 3780 int elem, rc; 3781 struct sas_task *task = ccb->task; 3782 struct domain_device *dev = task->dev; 3783 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3784 struct scatterlist *sg_req, *sg_resp; 3785 u32 req_len, resp_len; 3786 struct smp_req smp_cmd; 3787 u32 opc; 3788 struct inbound_queue_table *circularQ; 3789 char *preq_dma_addr = NULL; 3790 __le64 tmp_addr; 3791 u32 i, length; 3792 3793 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3794 /* 3795 * DMA-map SMP request, response buffers 3796 */ 3797 sg_req = &task->smp_task.smp_req; 3798 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); 3799 if (!elem) 3800 return -ENOMEM; 3801 req_len = sg_dma_len(sg_req); 3802 3803 sg_resp = &task->smp_task.smp_resp; 3804 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); 3805 if (!elem) { 3806 rc = -ENOMEM; 3807 goto err_out; 3808 } 3809 resp_len = sg_dma_len(sg_resp); 3810 /* must be in dwords */ 3811 if ((req_len & 0x3) || (resp_len & 0x3)) { 3812 rc = -EINVAL; 3813 goto err_out_2; 3814 } 3815 3816 opc = OPC_INB_SMP_REQUEST; 3817 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3818 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3819 3820 length = sg_req->length; 3821 PM8001_IO_DBG(pm8001_ha, 3822 pm8001_printk("SMP Frame Length %d\n", sg_req->length)); 3823 if (!(length - 8)) 3824 pm8001_ha->smp_exp_mode = SMP_DIRECT; 3825 else 3826 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 3827 3828 3829 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3830 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 3831 3832 /* INDIRECT MODE command settings. Use DMA */ 3833 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 3834 PM8001_IO_DBG(pm8001_ha, 3835 pm8001_printk("SMP REQUEST INDIRECT MODE\n")); 3836 /* for SPCv indirect mode. Place the top 4 bytes of 3837 * SMP Request header here. */ 3838 for (i = 0; i < 4; i++) 3839 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 3840 /* exclude top 4 bytes for SMP req header */ 3841 smp_cmd.long_smp_req.long_req_addr = 3842 cpu_to_le64((u64)sg_dma_address 3843 (&task->smp_task.smp_req) + 4); 3844 /* exclude 4 bytes for SMP req header and CRC */ 3845 smp_cmd.long_smp_req.long_req_size = 3846 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 3847 smp_cmd.long_smp_req.long_resp_addr = 3848 cpu_to_le64((u64)sg_dma_address 3849 (&task->smp_task.smp_resp)); 3850 smp_cmd.long_smp_req.long_resp_size = 3851 cpu_to_le32((u32)sg_dma_len 3852 (&task->smp_task.smp_resp)-4); 3853 } else { /* DIRECT MODE */ 3854 smp_cmd.long_smp_req.long_req_addr = 3855 cpu_to_le64((u64)sg_dma_address 3856 (&task->smp_task.smp_req)); 3857 smp_cmd.long_smp_req.long_req_size = 3858 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3859 smp_cmd.long_smp_req.long_resp_addr = 3860 cpu_to_le64((u64)sg_dma_address 3861 (&task->smp_task.smp_resp)); 3862 smp_cmd.long_smp_req.long_resp_size = 3863 cpu_to_le32 3864 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3865 } 3866 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3867 PM8001_IO_DBG(pm8001_ha, 3868 pm8001_printk("SMP REQUEST DIRECT MODE\n")); 3869 for (i = 0; i < length; i++) 3870 if (i < 16) { 3871 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 3872 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3873 "Byte[%d]:%x (DMA data:%x)\n", 3874 i, smp_cmd.smp_req16[i], 3875 *(preq_dma_addr))); 3876 } else { 3877 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 3878 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3879 "Byte[%d]:%x (DMA data:%x)\n", 3880 i, smp_cmd.smp_req[i], 3881 *(preq_dma_addr))); 3882 } 3883 } 3884 3885 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 3886 &smp_cmd, pm8001_ha->smp_exp_mode, length); 3887 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 3888 (u32 *)&smp_cmd, 0); 3889 if (rc) 3890 goto err_out_2; 3891 return 0; 3892 3893 err_out_2: 3894 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 3895 PCI_DMA_FROMDEVICE); 3896 err_out: 3897 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 3898 PCI_DMA_TODEVICE); 3899 return rc; 3900 } 3901 3902 static int check_enc_sas_cmd(struct sas_task *task) 3903 { 3904 u8 cmd = task->ssp_task.cmd->cmnd[0]; 3905 3906 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 3907 return 1; 3908 else 3909 return 0; 3910 } 3911 3912 static int check_enc_sat_cmd(struct sas_task *task) 3913 { 3914 int ret = 0; 3915 switch (task->ata_task.fis.command) { 3916 case ATA_CMD_FPDMA_READ: 3917 case ATA_CMD_READ_EXT: 3918 case ATA_CMD_READ: 3919 case ATA_CMD_FPDMA_WRITE: 3920 case ATA_CMD_WRITE_EXT: 3921 case ATA_CMD_WRITE: 3922 case ATA_CMD_PIO_READ: 3923 case ATA_CMD_PIO_READ_EXT: 3924 case ATA_CMD_PIO_WRITE: 3925 case ATA_CMD_PIO_WRITE_EXT: 3926 ret = 1; 3927 break; 3928 default: 3929 ret = 0; 3930 break; 3931 } 3932 return ret; 3933 } 3934 3935 /** 3936 * pm80xx_chip_ssp_io_req - send a SSP task to FW 3937 * @pm8001_ha: our hba card information. 3938 * @ccb: the ccb information this request used. 3939 */ 3940 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 3941 struct pm8001_ccb_info *ccb) 3942 { 3943 struct sas_task *task = ccb->task; 3944 struct domain_device *dev = task->dev; 3945 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3946 struct ssp_ini_io_start_req ssp_cmd; 3947 u32 tag = ccb->ccb_tag; 3948 int ret; 3949 u64 phys_addr, start_addr, end_addr; 3950 u32 end_addr_high, end_addr_low; 3951 struct inbound_queue_table *circularQ; 3952 u32 q_index; 3953 u32 opc = OPC_INB_SSPINIIOSTART; 3954 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 3955 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 3956 /* data address domain added for spcv; set to 0 by host, 3957 * used internally by controller 3958 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 3959 */ 3960 ssp_cmd.dad_dir_m_tlr = 3961 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 3962 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3963 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 3964 ssp_cmd.tag = cpu_to_le32(tag); 3965 if (task->ssp_task.enable_first_burst) 3966 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 3967 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 3968 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 3969 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 3970 task->ssp_task.cmd->cmd_len); 3971 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 3972 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 3973 3974 /* Check if encryption is set */ 3975 if (pm8001_ha->chip->encrypt && 3976 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 3977 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3978 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 3979 task->ssp_task.cmd->cmnd[0])); 3980 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 3981 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 3982 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 3983 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 3984 3985 /* fill in PRD (scatter/gather) table, if any */ 3986 if (task->num_scatter > 1) { 3987 pm8001_chip_make_sg(task->scatter, 3988 ccb->n_elem, ccb->buf_prd); 3989 phys_addr = ccb->ccb_dma_handle + 3990 offsetof(struct pm8001_ccb_info, buf_prd[0]); 3991 ssp_cmd.enc_addr_low = 3992 cpu_to_le32(lower_32_bits(phys_addr)); 3993 ssp_cmd.enc_addr_high = 3994 cpu_to_le32(upper_32_bits(phys_addr)); 3995 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 3996 } else if (task->num_scatter == 1) { 3997 u64 dma_addr = sg_dma_address(task->scatter); 3998 ssp_cmd.enc_addr_low = 3999 cpu_to_le32(lower_32_bits(dma_addr)); 4000 ssp_cmd.enc_addr_high = 4001 cpu_to_le32(upper_32_bits(dma_addr)); 4002 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4003 ssp_cmd.enc_esgl = 0; 4004 /* Check 4G Boundary */ 4005 start_addr = cpu_to_le64(dma_addr); 4006 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4007 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4008 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4009 if (end_addr_high != ssp_cmd.enc_addr_high) { 4010 PM8001_FAIL_DBG(pm8001_ha, 4011 pm8001_printk("The sg list address " 4012 "start_addr=0x%016llx data_len=0x%x " 4013 "end_addr_high=0x%08x end_addr_low=" 4014 "0x%08x has crossed 4G boundary\n", 4015 start_addr, ssp_cmd.enc_len, 4016 end_addr_high, end_addr_low)); 4017 pm8001_chip_make_sg(task->scatter, 1, 4018 ccb->buf_prd); 4019 phys_addr = ccb->ccb_dma_handle + 4020 offsetof(struct pm8001_ccb_info, 4021 buf_prd[0]); 4022 ssp_cmd.enc_addr_low = 4023 cpu_to_le32(lower_32_bits(phys_addr)); 4024 ssp_cmd.enc_addr_high = 4025 cpu_to_le32(upper_32_bits(phys_addr)); 4026 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4027 } 4028 } else if (task->num_scatter == 0) { 4029 ssp_cmd.enc_addr_low = 0; 4030 ssp_cmd.enc_addr_high = 0; 4031 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4032 ssp_cmd.enc_esgl = 0; 4033 } 4034 /* XTS mode. All other fields are 0 */ 4035 ssp_cmd.key_cmode = 0x6 << 4; 4036 /* set tweak values. Should be the start lba */ 4037 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4038 (task->ssp_task.cmd->cmnd[3] << 16) | 4039 (task->ssp_task.cmd->cmnd[4] << 8) | 4040 (task->ssp_task.cmd->cmnd[5])); 4041 } else { 4042 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4043 "Sending Normal SAS command 0x%x inb q %x\n", 4044 task->ssp_task.cmd->cmnd[0], q_index)); 4045 /* fill in PRD (scatter/gather) table, if any */ 4046 if (task->num_scatter > 1) { 4047 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4048 ccb->buf_prd); 4049 phys_addr = ccb->ccb_dma_handle + 4050 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4051 ssp_cmd.addr_low = 4052 cpu_to_le32(lower_32_bits(phys_addr)); 4053 ssp_cmd.addr_high = 4054 cpu_to_le32(upper_32_bits(phys_addr)); 4055 ssp_cmd.esgl = cpu_to_le32(1<<31); 4056 } else if (task->num_scatter == 1) { 4057 u64 dma_addr = sg_dma_address(task->scatter); 4058 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4059 ssp_cmd.addr_high = 4060 cpu_to_le32(upper_32_bits(dma_addr)); 4061 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4062 ssp_cmd.esgl = 0; 4063 /* Check 4G Boundary */ 4064 start_addr = cpu_to_le64(dma_addr); 4065 end_addr = (start_addr + ssp_cmd.len) - 1; 4066 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4067 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4068 if (end_addr_high != ssp_cmd.addr_high) { 4069 PM8001_FAIL_DBG(pm8001_ha, 4070 pm8001_printk("The sg list address " 4071 "start_addr=0x%016llx data_len=0x%x " 4072 "end_addr_high=0x%08x end_addr_low=" 4073 "0x%08x has crossed 4G boundary\n", 4074 start_addr, ssp_cmd.len, 4075 end_addr_high, end_addr_low)); 4076 pm8001_chip_make_sg(task->scatter, 1, 4077 ccb->buf_prd); 4078 phys_addr = ccb->ccb_dma_handle + 4079 offsetof(struct pm8001_ccb_info, 4080 buf_prd[0]); 4081 ssp_cmd.addr_low = 4082 cpu_to_le32(lower_32_bits(phys_addr)); 4083 ssp_cmd.addr_high = 4084 cpu_to_le32(upper_32_bits(phys_addr)); 4085 ssp_cmd.esgl = cpu_to_le32(1<<31); 4086 } 4087 } else if (task->num_scatter == 0) { 4088 ssp_cmd.addr_low = 0; 4089 ssp_cmd.addr_high = 0; 4090 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4091 ssp_cmd.esgl = 0; 4092 } 4093 } 4094 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4095 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4096 &ssp_cmd, q_index); 4097 return ret; 4098 } 4099 4100 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4101 struct pm8001_ccb_info *ccb) 4102 { 4103 struct sas_task *task = ccb->task; 4104 struct domain_device *dev = task->dev; 4105 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4106 u32 tag = ccb->ccb_tag; 4107 int ret; 4108 u32 q_index; 4109 struct sata_start_req sata_cmd; 4110 u32 hdr_tag, ncg_tag = 0; 4111 u64 phys_addr, start_addr, end_addr; 4112 u32 end_addr_high, end_addr_low; 4113 u32 ATAP = 0x0; 4114 u32 dir; 4115 struct inbound_queue_table *circularQ; 4116 unsigned long flags; 4117 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4118 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4119 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 4120 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4121 4122 if (task->data_dir == PCI_DMA_NONE) { 4123 ATAP = 0x04; /* no data*/ 4124 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4125 } else if (likely(!task->ata_task.device_control_reg_update)) { 4126 if (task->ata_task.dma_xfer) { 4127 ATAP = 0x06; /* DMA */ 4128 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4129 } else { 4130 ATAP = 0x05; /* PIO*/ 4131 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4132 } 4133 if (task->ata_task.use_ncq && 4134 dev->sata_dev.class != ATA_DEV_ATAPI) { 4135 ATAP = 0x07; /* FPDMA */ 4136 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4137 } 4138 } 4139 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4140 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4141 ncg_tag = hdr_tag; 4142 } 4143 dir = data_dir_flags[task->data_dir] << 8; 4144 sata_cmd.tag = cpu_to_le32(tag); 4145 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4146 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4147 4148 sata_cmd.sata_fis = task->ata_task.fis; 4149 if (likely(!task->ata_task.device_control_reg_update)) 4150 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4151 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4152 4153 /* Check if encryption is set */ 4154 if (pm8001_ha->chip->encrypt && 4155 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4156 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4157 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4158 sata_cmd.sata_fis.command)); 4159 opc = OPC_INB_SATA_DIF_ENC_IO; 4160 4161 /* set encryption bit */ 4162 sata_cmd.ncqtag_atap_dir_m_dad = 4163 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4164 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4165 /* dad (bit 0-1) is 0 */ 4166 /* fill in PRD (scatter/gather) table, if any */ 4167 if (task->num_scatter > 1) { 4168 pm8001_chip_make_sg(task->scatter, 4169 ccb->n_elem, ccb->buf_prd); 4170 phys_addr = ccb->ccb_dma_handle + 4171 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4172 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4173 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4174 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4175 } else if (task->num_scatter == 1) { 4176 u64 dma_addr = sg_dma_address(task->scatter); 4177 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4178 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4179 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4180 sata_cmd.enc_esgl = 0; 4181 /* Check 4G Boundary */ 4182 start_addr = cpu_to_le64(dma_addr); 4183 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4184 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4185 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4186 if (end_addr_high != sata_cmd.enc_addr_high) { 4187 PM8001_FAIL_DBG(pm8001_ha, 4188 pm8001_printk("The sg list address " 4189 "start_addr=0x%016llx data_len=0x%x " 4190 "end_addr_high=0x%08x end_addr_low" 4191 "=0x%08x has crossed 4G boundary\n", 4192 start_addr, sata_cmd.enc_len, 4193 end_addr_high, end_addr_low)); 4194 pm8001_chip_make_sg(task->scatter, 1, 4195 ccb->buf_prd); 4196 phys_addr = ccb->ccb_dma_handle + 4197 offsetof(struct pm8001_ccb_info, 4198 buf_prd[0]); 4199 sata_cmd.enc_addr_low = 4200 lower_32_bits(phys_addr); 4201 sata_cmd.enc_addr_high = 4202 upper_32_bits(phys_addr); 4203 sata_cmd.enc_esgl = 4204 cpu_to_le32(1 << 31); 4205 } 4206 } else if (task->num_scatter == 0) { 4207 sata_cmd.enc_addr_low = 0; 4208 sata_cmd.enc_addr_high = 0; 4209 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4210 sata_cmd.enc_esgl = 0; 4211 } 4212 /* XTS mode. All other fields are 0 */ 4213 sata_cmd.key_index_mode = 0x6 << 4; 4214 /* set tweak values. Should be the start lba */ 4215 sata_cmd.twk_val0 = 4216 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4217 (sata_cmd.sata_fis.lbah << 16) | 4218 (sata_cmd.sata_fis.lbam << 8) | 4219 (sata_cmd.sata_fis.lbal)); 4220 sata_cmd.twk_val1 = 4221 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4222 (sata_cmd.sata_fis.lbam_exp)); 4223 } else { 4224 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4225 "Sending Normal SATA command 0x%x inb %x\n", 4226 sata_cmd.sata_fis.command, q_index)); 4227 /* dad (bit 0-1) is 0 */ 4228 sata_cmd.ncqtag_atap_dir_m_dad = 4229 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4230 ((ATAP & 0x3f) << 10) | dir); 4231 4232 /* fill in PRD (scatter/gather) table, if any */ 4233 if (task->num_scatter > 1) { 4234 pm8001_chip_make_sg(task->scatter, 4235 ccb->n_elem, ccb->buf_prd); 4236 phys_addr = ccb->ccb_dma_handle + 4237 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4238 sata_cmd.addr_low = lower_32_bits(phys_addr); 4239 sata_cmd.addr_high = upper_32_bits(phys_addr); 4240 sata_cmd.esgl = cpu_to_le32(1 << 31); 4241 } else if (task->num_scatter == 1) { 4242 u64 dma_addr = sg_dma_address(task->scatter); 4243 sata_cmd.addr_low = lower_32_bits(dma_addr); 4244 sata_cmd.addr_high = upper_32_bits(dma_addr); 4245 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4246 sata_cmd.esgl = 0; 4247 /* Check 4G Boundary */ 4248 start_addr = cpu_to_le64(dma_addr); 4249 end_addr = (start_addr + sata_cmd.len) - 1; 4250 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4251 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4252 if (end_addr_high != sata_cmd.addr_high) { 4253 PM8001_FAIL_DBG(pm8001_ha, 4254 pm8001_printk("The sg list address " 4255 "start_addr=0x%016llx data_len=0x%x" 4256 "end_addr_high=0x%08x end_addr_low=" 4257 "0x%08x has crossed 4G boundary\n", 4258 start_addr, sata_cmd.len, 4259 end_addr_high, end_addr_low)); 4260 pm8001_chip_make_sg(task->scatter, 1, 4261 ccb->buf_prd); 4262 phys_addr = ccb->ccb_dma_handle + 4263 offsetof(struct pm8001_ccb_info, 4264 buf_prd[0]); 4265 sata_cmd.addr_low = 4266 lower_32_bits(phys_addr); 4267 sata_cmd.addr_high = 4268 upper_32_bits(phys_addr); 4269 sata_cmd.esgl = cpu_to_le32(1 << 31); 4270 } 4271 } else if (task->num_scatter == 0) { 4272 sata_cmd.addr_low = 0; 4273 sata_cmd.addr_high = 0; 4274 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4275 sata_cmd.esgl = 0; 4276 } 4277 /* scsi cdb */ 4278 sata_cmd.atapi_scsi_cdb[0] = 4279 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4280 (task->ata_task.atapi_packet[1] << 8) | 4281 (task->ata_task.atapi_packet[2] << 16) | 4282 (task->ata_task.atapi_packet[3] << 24))); 4283 sata_cmd.atapi_scsi_cdb[1] = 4284 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4285 (task->ata_task.atapi_packet[5] << 8) | 4286 (task->ata_task.atapi_packet[6] << 16) | 4287 (task->ata_task.atapi_packet[7] << 24))); 4288 sata_cmd.atapi_scsi_cdb[2] = 4289 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4290 (task->ata_task.atapi_packet[9] << 8) | 4291 (task->ata_task.atapi_packet[10] << 16) | 4292 (task->ata_task.atapi_packet[11] << 24))); 4293 sata_cmd.atapi_scsi_cdb[3] = 4294 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4295 (task->ata_task.atapi_packet[13] << 8) | 4296 (task->ata_task.atapi_packet[14] << 16) | 4297 (task->ata_task.atapi_packet[15] << 24))); 4298 } 4299 4300 /* Check for read log for failed drive and return */ 4301 if (sata_cmd.sata_fis.command == 0x2f) { 4302 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4303 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4304 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4305 struct task_status_struct *ts; 4306 4307 pm8001_ha_dev->id &= 0xDFFFFFFF; 4308 ts = &task->task_status; 4309 4310 spin_lock_irqsave(&task->task_state_lock, flags); 4311 ts->resp = SAS_TASK_COMPLETE; 4312 ts->stat = SAM_STAT_GOOD; 4313 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4314 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4315 task->task_state_flags |= SAS_TASK_STATE_DONE; 4316 if (unlikely((task->task_state_flags & 4317 SAS_TASK_STATE_ABORTED))) { 4318 spin_unlock_irqrestore(&task->task_state_lock, 4319 flags); 4320 PM8001_FAIL_DBG(pm8001_ha, 4321 pm8001_printk("task 0x%p resp 0x%x " 4322 " stat 0x%x but aborted by upper layer " 4323 "\n", task, ts->resp, ts->stat)); 4324 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4325 return 0; 4326 } else { 4327 spin_unlock_irqrestore(&task->task_state_lock, 4328 flags); 4329 pm8001_ccb_task_free_done(pm8001_ha, task, 4330 ccb, tag); 4331 return 0; 4332 } 4333 } 4334 } 4335 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4336 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4337 &sata_cmd, q_index); 4338 return ret; 4339 } 4340 4341 /** 4342 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4343 * @pm8001_ha: our hba card information. 4344 * @num: the inbound queue number 4345 * @phy_id: the phy id which we wanted to start up. 4346 */ 4347 static int 4348 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4349 { 4350 struct phy_start_req payload; 4351 struct inbound_queue_table *circularQ; 4352 int ret; 4353 u32 tag = 0x01; 4354 u32 opcode = OPC_INB_PHYSTART; 4355 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4356 memset(&payload, 0, sizeof(payload)); 4357 payload.tag = cpu_to_le32(tag); 4358 4359 PM8001_INIT_DBG(pm8001_ha, 4360 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id)); 4361 /* 4362 ** [0:7] PHY Identifier 4363 ** [8:11] link rate 1.5G, 3G, 6G 4364 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode 4365 ** [14] 0b disable spin up hold; 1b enable spin up hold 4366 ** [15] ob no change in current PHY analig setup 1b enable using SPAST 4367 */ 4368 if (!IS_SPCV_12G(pm8001_ha->pdev)) 4369 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4370 LINKMODE_AUTO | LINKRATE_15 | 4371 LINKRATE_30 | LINKRATE_60 | phy_id); 4372 else 4373 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4374 LINKMODE_AUTO | LINKRATE_15 | 4375 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 | 4376 phy_id); 4377 4378 /* SSC Disable and SAS Analog ST configuration */ 4379 /** 4380 payload.ase_sh_lm_slr_phyid = 4381 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4382 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4383 phy_id); 4384 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4385 **/ 4386 4387 payload.sas_identify.dev_type = SAS_END_DEVICE; 4388 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4389 memcpy(payload.sas_identify.sas_addr, 4390 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4391 payload.sas_identify.phy_id = phy_id; 4392 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4393 return ret; 4394 } 4395 4396 /** 4397 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4398 * @pm8001_ha: our hba card information. 4399 * @num: the inbound queue number 4400 * @phy_id: the phy id which we wanted to start up. 4401 */ 4402 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4403 u8 phy_id) 4404 { 4405 struct phy_stop_req payload; 4406 struct inbound_queue_table *circularQ; 4407 int ret; 4408 u32 tag = 0x01; 4409 u32 opcode = OPC_INB_PHYSTOP; 4410 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4411 memset(&payload, 0, sizeof(payload)); 4412 payload.tag = cpu_to_le32(tag); 4413 payload.phy_id = cpu_to_le32(phy_id); 4414 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4415 return ret; 4416 } 4417 4418 /** 4419 * see comments on pm8001_mpi_reg_resp. 4420 */ 4421 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4422 struct pm8001_device *pm8001_dev, u32 flag) 4423 { 4424 struct reg_dev_req payload; 4425 u32 opc; 4426 u32 stp_sspsmp_sata = 0x4; 4427 struct inbound_queue_table *circularQ; 4428 u32 linkrate, phy_id; 4429 int rc, tag = 0xdeadbeef; 4430 struct pm8001_ccb_info *ccb; 4431 u8 retryFlag = 0x1; 4432 u16 firstBurstSize = 0; 4433 u16 ITNT = 2000; 4434 struct domain_device *dev = pm8001_dev->sas_device; 4435 struct domain_device *parent_dev = dev->parent; 4436 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4437 4438 memset(&payload, 0, sizeof(payload)); 4439 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4440 if (rc) 4441 return rc; 4442 ccb = &pm8001_ha->ccb_info[tag]; 4443 ccb->device = pm8001_dev; 4444 ccb->ccb_tag = tag; 4445 payload.tag = cpu_to_le32(tag); 4446 4447 if (flag == 1) { 4448 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4449 } else { 4450 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4451 stp_sspsmp_sata = 0x00; /* stp*/ 4452 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4453 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4454 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4455 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4456 } 4457 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4458 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4459 else 4460 phy_id = pm8001_dev->attached_phy; 4461 4462 opc = OPC_INB_REG_DEV; 4463 4464 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4465 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4466 4467 payload.phyid_portid = 4468 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4469 ((phy_id & 0xFF) << 8)); 4470 4471 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4472 ((linkrate & 0x0F) << 24) | 4473 ((stp_sspsmp_sata & 0x03) << 28)); 4474 payload.firstburstsize_ITNexustimeout = 4475 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4476 4477 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4478 SAS_ADDR_SIZE); 4479 4480 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4481 if (rc) 4482 pm8001_tag_free(pm8001_ha, tag); 4483 4484 return rc; 4485 } 4486 4487 /** 4488 * pm80xx_chip_phy_ctl_req - support the local phy operation 4489 * @pm8001_ha: our hba card information. 4490 * @num: the inbound queue number 4491 * @phy_id: the phy id which we wanted to operate 4492 * @phy_op: 4493 */ 4494 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4495 u32 phyId, u32 phy_op) 4496 { 4497 struct local_phy_ctl_req payload; 4498 struct inbound_queue_table *circularQ; 4499 int ret; 4500 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4501 memset(&payload, 0, sizeof(payload)); 4502 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4503 payload.tag = cpu_to_le32(1); 4504 payload.phyop_phyid = 4505 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4506 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4507 return ret; 4508 } 4509 4510 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) 4511 { 4512 u32 value; 4513 #ifdef PM8001_USE_MSIX 4514 return 1; 4515 #endif 4516 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4517 if (value) 4518 return 1; 4519 return 0; 4520 4521 } 4522 4523 /** 4524 * pm8001_chip_isr - PM8001 isr handler. 4525 * @pm8001_ha: our hba card information. 4526 * @irq: irq number. 4527 * @stat: stat. 4528 */ 4529 static irqreturn_t 4530 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4531 { 4532 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4533 process_oq(pm8001_ha, vec); 4534 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4535 return IRQ_HANDLED; 4536 } 4537 4538 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4539 u32 operation, u32 phyid, u32 length, u32 *buf) 4540 { 4541 u32 tag , i, j = 0; 4542 int rc; 4543 struct set_phy_profile_req payload; 4544 struct inbound_queue_table *circularQ; 4545 u32 opc = OPC_INB_SET_PHY_PROFILE; 4546 4547 memset(&payload, 0, sizeof(payload)); 4548 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4549 if (rc) 4550 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n")); 4551 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4552 payload.tag = cpu_to_le32(tag); 4553 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4554 PM8001_INIT_DBG(pm8001_ha, 4555 pm8001_printk(" phy profile command for phy %x ,length is %d\n", 4556 payload.ppc_phyid, length)); 4557 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4558 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4559 j++; 4560 } 4561 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4562 if (rc) 4563 pm8001_tag_free(pm8001_ha, tag); 4564 } 4565 4566 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4567 u32 length, u8 *buf) 4568 { 4569 u32 page_code, i; 4570 4571 page_code = SAS_PHY_ANALOG_SETTINGS_PAGE; 4572 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4573 mpi_set_phy_profile_req(pm8001_ha, 4574 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4575 length = length + PHY_DWORD_LENGTH; 4576 } 4577 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n")); 4578 } 4579 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4580 .name = "pmc80xx", 4581 .chip_init = pm80xx_chip_init, 4582 .chip_soft_rst = pm80xx_chip_soft_rst, 4583 .chip_rst = pm80xx_hw_chip_rst, 4584 .chip_iounmap = pm8001_chip_iounmap, 4585 .isr = pm80xx_chip_isr, 4586 .is_our_interupt = pm80xx_chip_is_our_interupt, 4587 .isr_process_oq = process_oq, 4588 .interrupt_enable = pm80xx_chip_interrupt_enable, 4589 .interrupt_disable = pm80xx_chip_interrupt_disable, 4590 .make_prd = pm8001_chip_make_sg, 4591 .smp_req = pm80xx_chip_smp_req, 4592 .ssp_io_req = pm80xx_chip_ssp_io_req, 4593 .sata_req = pm80xx_chip_sata_req, 4594 .phy_start_req = pm80xx_chip_phy_start_req, 4595 .phy_stop_req = pm80xx_chip_phy_stop_req, 4596 .reg_dev_req = pm80xx_chip_reg_dev_req, 4597 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4598 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4599 .task_abort = pm8001_chip_abort_task, 4600 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4601 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4602 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4603 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4604 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4605 }; 4606