1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 PM8001_FAIL_DBG(pm8001_ha, 62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" 63 " = 0x%x\n", reg_val)); 64 return -1; 65 } 66 return 0; 67 } 68 69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 70 const void *destination, 71 u32 dw_count, u32 bus_base_number) 72 { 73 u32 index, value, offset; 74 u32 *destination1; 75 destination1 = (u32 *)destination; 76 77 for (index = 0; index < dw_count; index += 4, destination1++) { 78 offset = (soffset + index / 4); 79 if (offset < (64 * 1024)) { 80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 81 *destination1 = cpu_to_le32(value); 82 } 83 } 84 return; 85 } 86 87 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 88 struct device_attribute *attr, char *buf) 89 { 90 struct Scsi_Host *shost = class_to_shost(cdev); 91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 94 u32 accum_len , reg_val, index, *temp; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 99 pm8001_ha->forensic_info.data_buf.direct_data = buf; 100 if (pm8001_ha->chip_id == chip_8001) { 101 pm8001_ha->forensic_info.data_buf.direct_data += 102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 103 "Not supported for SPC controller"); 104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 105 (char *)buf; 106 } 107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 108 PM8001_IO_DBG(pm8001_ha, 109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n")); 110 direct_data = (u8 *)fatal_error_data; 111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 113 pm8001_ha->forensic_info.data_buf.read_len = 0; 114 115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 116 117 /* start to get data */ 118 /* Program the MEMBASE II Shifting Register with 0x00.*/ 119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 120 pm8001_ha->fatal_forensic_shift_offset); 121 pm8001_ha->forensic_last_offset = 0; 122 pm8001_ha->forensic_fatal_step = 0; 123 pm8001_ha->fatal_bar_loc = 0; 124 } 125 126 /* Read until accum_len is retrived */ 127 accum_len = pm8001_mr32(fatal_table_address, 128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n", 130 accum_len)); 131 if (accum_len == 0xFFFFFFFF) { 132 PM8001_IO_DBG(pm8001_ha, 133 pm8001_printk("Possible PCI issue 0x%x not expected\n", 134 accum_len)); 135 return -EIO; 136 } 137 if (accum_len == 0 || accum_len >= 0x100000) { 138 pm8001_ha->forensic_info.data_buf.direct_data += 139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 140 "%08x ", 0xFFFFFFFF); 141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 142 (char *)buf; 143 } 144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 145 if (pm8001_ha->forensic_fatal_step == 0) { 146 moreData: 147 if (pm8001_ha->forensic_info.data_buf.direct_data) { 148 /* Data is in bar, copy to host memory */ 149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc, 150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 151 pm8001_ha->forensic_info.data_buf.direct_len , 152 1); 153 } 154 pm8001_ha->fatal_bar_loc += 155 pm8001_ha->forensic_info.data_buf.direct_len; 156 pm8001_ha->forensic_info.data_buf.direct_offset += 157 pm8001_ha->forensic_info.data_buf.direct_len; 158 pm8001_ha->forensic_last_offset += 159 pm8001_ha->forensic_info.data_buf.direct_len; 160 pm8001_ha->forensic_info.data_buf.read_len = 161 pm8001_ha->forensic_info.data_buf.direct_len; 162 163 if (pm8001_ha->forensic_last_offset >= accum_len) { 164 pm8001_ha->forensic_info.data_buf.direct_data += 165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 166 "%08x ", 3); 167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) { 168 pm8001_ha->forensic_info.data_buf.direct_data += 169 sprintf(pm8001_ha-> 170 forensic_info.data_buf.direct_data, 171 "%08x ", *(temp + index)); 172 } 173 174 pm8001_ha->fatal_bar_loc = 0; 175 pm8001_ha->forensic_fatal_step = 1; 176 pm8001_ha->fatal_forensic_shift_offset = 0; 177 pm8001_ha->forensic_last_offset = 0; 178 return (char *)pm8001_ha-> 179 forensic_info.data_buf.direct_data - 180 (char *)buf; 181 } 182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 183 pm8001_ha->forensic_info.data_buf.direct_data += 184 sprintf(pm8001_ha-> 185 forensic_info.data_buf.direct_data, 186 "%08x ", 2); 187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) { 188 pm8001_ha->forensic_info.data_buf.direct_data += 189 sprintf(pm8001_ha-> 190 forensic_info.data_buf.direct_data, 191 "%08x ", *(temp + index)); 192 } 193 return (char *)pm8001_ha-> 194 forensic_info.data_buf.direct_data - 195 (char *)buf; 196 } 197 198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 199 pm8001_ha->forensic_info.data_buf.direct_data += 200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 201 "%08x ", 2); 202 for (index = 0; index < 256; index++) { 203 pm8001_ha->forensic_info.data_buf.direct_data += 204 sprintf(pm8001_ha-> 205 forensic_info.data_buf.direct_data, 206 "%08x ", *(temp + index)); 207 } 208 pm8001_ha->fatal_forensic_shift_offset += 0x100; 209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 210 pm8001_ha->fatal_forensic_shift_offset); 211 pm8001_ha->fatal_bar_loc = 0; 212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 213 (char *)buf; 214 } 215 if (pm8001_ha->forensic_fatal_step == 1) { 216 pm8001_ha->fatal_forensic_shift_offset = 0; 217 /* Read 64K of the debug data. */ 218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 219 pm8001_ha->fatal_forensic_shift_offset); 220 pm8001_mw32(fatal_table_address, 221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 222 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 223 224 /* Poll FDDHSHK until clear */ 225 start = jiffies + (2 * HZ); /* 2 sec */ 226 227 do { 228 reg_val = pm8001_mr32(fatal_table_address, 229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 230 } while ((reg_val) && time_before(jiffies, start)); 231 232 if (reg_val != 0) { 233 PM8001_FAIL_DBG(pm8001_ha, 234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" 235 " = 0x%x\n", reg_val)); 236 return -EIO; 237 } 238 239 /* Read the next 64K of the debug data. */ 240 pm8001_ha->forensic_fatal_step = 0; 241 if (pm8001_mr32(fatal_table_address, 242 MPI_FATAL_EDUMP_TABLE_STATUS) != 243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 244 pm8001_mw32(fatal_table_address, 245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0); 246 goto moreData; 247 } else { 248 pm8001_ha->forensic_info.data_buf.direct_data += 249 sprintf(pm8001_ha-> 250 forensic_info.data_buf.direct_data, 251 "%08x ", 4); 252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 253 pm8001_ha->forensic_info.data_buf.direct_len = 0; 254 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 255 pm8001_ha->forensic_info.data_buf.read_len = 0; 256 } 257 } 258 259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 260 (char *)buf; 261 } 262 263 /** 264 * read_main_config_table - read the configure table and save it. 265 * @pm8001_ha: our hba card information 266 */ 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 268 { 269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 270 271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 274 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 276 pm8001_mr32(address, MAIN_FW_REVISION); 277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 284 pm8001_mr32(address, MAIN_GST_OFFSET); 285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 286 pm8001_mr32(address, MAIN_IBQ_OFFSET); 287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 288 pm8001_mr32(address, MAIN_OBQ_OFFSET); 289 290 /* read Error Dump Offset and Length */ 291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 299 300 /* read GPIO LED settings from the configuration table */ 301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 303 304 /* read analog Setting offset from the configuration table */ 305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 307 308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 312 /* read port recover and reset timeout */ 313 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 314 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 315 /* read ILA and inactive firmware version */ 316 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 317 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 318 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 319 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 320 } 321 322 /** 323 * read_general_status_table - read the general status table and save it. 324 * @pm8001_ha: our hba card information 325 */ 326 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 327 { 328 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 329 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 330 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 331 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 332 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 333 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 334 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 335 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 336 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 337 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 338 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 339 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 340 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 341 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 342 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 343 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 344 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 345 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 346 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 347 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 348 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 349 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 350 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 351 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 352 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 353 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 354 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 355 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 356 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 357 } 358 /** 359 * read_phy_attr_table - read the phy attribute table and save it. 360 * @pm8001_ha: our hba card information 361 */ 362 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 363 { 364 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 365 pm8001_ha->phy_attr_table.phystart1_16[0] = 366 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 367 pm8001_ha->phy_attr_table.phystart1_16[1] = 368 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 369 pm8001_ha->phy_attr_table.phystart1_16[2] = 370 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 371 pm8001_ha->phy_attr_table.phystart1_16[3] = 372 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 373 pm8001_ha->phy_attr_table.phystart1_16[4] = 374 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 375 pm8001_ha->phy_attr_table.phystart1_16[5] = 376 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 377 pm8001_ha->phy_attr_table.phystart1_16[6] = 378 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 379 pm8001_ha->phy_attr_table.phystart1_16[7] = 380 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 381 pm8001_ha->phy_attr_table.phystart1_16[8] = 382 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 383 pm8001_ha->phy_attr_table.phystart1_16[9] = 384 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 385 pm8001_ha->phy_attr_table.phystart1_16[10] = 386 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 387 pm8001_ha->phy_attr_table.phystart1_16[11] = 388 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 389 pm8001_ha->phy_attr_table.phystart1_16[12] = 390 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 391 pm8001_ha->phy_attr_table.phystart1_16[13] = 392 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 393 pm8001_ha->phy_attr_table.phystart1_16[14] = 394 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 395 pm8001_ha->phy_attr_table.phystart1_16[15] = 396 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 397 398 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 399 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 400 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 401 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 402 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 403 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 404 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 405 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 406 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 407 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 408 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 409 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 410 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 411 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 412 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 413 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 414 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 415 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 416 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 417 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 418 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 419 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 420 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 421 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 422 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 423 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 424 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 425 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 426 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 427 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 428 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 429 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 430 431 } 432 433 /** 434 * read_inbnd_queue_table - read the inbound queue table and save it. 435 * @pm8001_ha: our hba card information 436 */ 437 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 438 { 439 int i; 440 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 441 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 442 u32 offset = i * 0x20; 443 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 444 get_pci_bar_index(pm8001_mr32(address, 445 (offset + IB_PIPCI_BAR))); 446 pm8001_ha->inbnd_q_tbl[i].pi_offset = 447 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 448 } 449 } 450 451 /** 452 * read_outbnd_queue_table - read the outbound queue table and save it. 453 * @pm8001_ha: our hba card information 454 */ 455 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 456 { 457 int i; 458 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 459 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 460 u32 offset = i * 0x24; 461 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 462 get_pci_bar_index(pm8001_mr32(address, 463 (offset + OB_CIPCI_BAR))); 464 pm8001_ha->outbnd_q_tbl[i].ci_offset = 465 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 466 } 467 } 468 469 /** 470 * init_default_table_values - init the default table. 471 * @pm8001_ha: our hba card information 472 */ 473 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 474 { 475 int i; 476 u32 offsetib, offsetob; 477 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 478 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 479 480 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 481 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 482 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 483 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 484 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 485 PM8001_EVENT_LOG_SIZE; 486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 487 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 488 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 489 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 490 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 491 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 492 PM8001_EVENT_LOG_SIZE; 493 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 494 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 495 496 /* Disable end to end CRC checking */ 497 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 498 499 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 500 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 501 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 502 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 503 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 504 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 505 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 506 pm8001_ha->inbnd_q_tbl[i].base_virt = 507 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 508 pm8001_ha->inbnd_q_tbl[i].total_length = 509 pm8001_ha->memoryMap.region[IB + i].total_len; 510 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 511 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 512 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 513 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 514 pm8001_ha->inbnd_q_tbl[i].ci_virt = 515 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 516 offsetib = i * 0x20; 517 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 518 get_pci_bar_index(pm8001_mr32(addressib, 519 (offsetib + 0x14))); 520 pm8001_ha->inbnd_q_tbl[i].pi_offset = 521 pm8001_mr32(addressib, (offsetib + 0x18)); 522 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 523 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 524 } 525 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 526 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 527 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 528 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 529 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 530 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 531 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 532 pm8001_ha->outbnd_q_tbl[i].base_virt = 533 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 534 pm8001_ha->outbnd_q_tbl[i].total_length = 535 pm8001_ha->memoryMap.region[OB + i].total_len; 536 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 537 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 538 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 539 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 540 /* interrupt vector based on oq */ 541 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 542 pm8001_ha->outbnd_q_tbl[i].pi_virt = 543 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 544 offsetob = i * 0x24; 545 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 546 get_pci_bar_index(pm8001_mr32(addressob, 547 offsetob + 0x14)); 548 pm8001_ha->outbnd_q_tbl[i].ci_offset = 549 pm8001_mr32(addressob, (offsetob + 0x18)); 550 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 551 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 552 } 553 } 554 555 /** 556 * update_main_config_table - update the main default table to the HBA. 557 * @pm8001_ha: our hba card information 558 */ 559 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 560 { 561 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 562 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 564 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 565 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 566 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 568 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 570 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 571 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 572 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 574 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 576 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 577 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 578 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 580 /* Update Fatal error interrupt vector */ 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 582 ((pm8001_ha->number_of_intr - 1) << 8); 583 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 585 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 586 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 587 588 /* SPCv specific */ 589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 590 /* Set GPIOLED to 0x2 for LED indicator */ 591 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 592 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 594 595 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 597 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 598 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 599 600 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 601 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 602 PORT_RECOVERY_TIMEOUT; 603 if (pm8001_ha->chip_id == chip_8006) { 604 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 605 0x0000ffff; 606 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 607 0x140000; 608 } 609 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 610 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 611 } 612 613 /** 614 * update_inbnd_queue_table - update the inbound queue table to the HBA. 615 * @pm8001_ha: our hba card information 616 */ 617 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 618 int number) 619 { 620 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 621 u16 offset = number * 0x20; 622 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 623 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 624 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 625 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 626 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 627 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 628 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 629 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 630 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 631 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 632 } 633 634 /** 635 * update_outbnd_queue_table - update the outbound queue table to the HBA. 636 * @pm8001_ha: our hba card information 637 */ 638 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 639 int number) 640 { 641 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 642 u16 offset = number * 0x24; 643 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 644 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 645 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 646 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 647 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 648 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 649 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 650 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 651 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 652 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 653 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 654 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 655 } 656 657 /** 658 * mpi_init_check - check firmware initialization status. 659 * @pm8001_ha: our hba card information 660 */ 661 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 662 { 663 u32 max_wait_count; 664 u32 value; 665 u32 gst_len_mpistate; 666 667 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 668 table is updated */ 669 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 670 /* wait until Inbound DoorBell Clear Register toggled */ 671 if (IS_SPCV_12G(pm8001_ha->pdev)) { 672 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 673 } else { 674 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 675 } 676 do { 677 udelay(1); 678 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 679 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 680 } while ((value != 0) && (--max_wait_count)); 681 682 if (!max_wait_count) 683 return -1; 684 /* check the MPI-State for initialization upto 100ms*/ 685 max_wait_count = 100 * 1000;/* 100 msec */ 686 do { 687 udelay(1); 688 gst_len_mpistate = 689 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 690 GST_GSTLEN_MPIS_OFFSET); 691 } while ((GST_MPI_STATE_INIT != 692 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 693 if (!max_wait_count) 694 return -1; 695 696 /* check MPI Initialization error */ 697 gst_len_mpistate = gst_len_mpistate >> 16; 698 if (0x0000 != gst_len_mpistate) 699 return -1; 700 701 return 0; 702 } 703 704 /** 705 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 706 * @pm8001_ha: our hba card information 707 */ 708 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 709 { 710 u32 value; 711 u32 max_wait_count; 712 u32 max_wait_time; 713 int ret = 0; 714 715 /* reset / PCIe ready */ 716 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */ 717 do { 718 udelay(1); 719 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 720 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 721 722 /* check ila status */ 723 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */ 724 do { 725 udelay(1); 726 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 727 } while (((value & SCRATCH_PAD_ILA_READY) != 728 SCRATCH_PAD_ILA_READY) && (--max_wait_count)); 729 if (!max_wait_count) 730 ret = -1; 731 else { 732 PM8001_MSG_DBG(pm8001_ha, 733 pm8001_printk(" ila ready status in %d millisec\n", 734 (max_wait_time - max_wait_count))); 735 } 736 737 /* check RAAE status */ 738 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */ 739 do { 740 udelay(1); 741 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 742 } while (((value & SCRATCH_PAD_RAAE_READY) != 743 SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); 744 if (!max_wait_count) 745 ret = -1; 746 else { 747 PM8001_MSG_DBG(pm8001_ha, 748 pm8001_printk(" raae ready status in %d millisec\n", 749 (max_wait_time - max_wait_count))); 750 } 751 752 /* check iop0 status */ 753 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */ 754 do { 755 udelay(1); 756 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 757 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && 758 (--max_wait_count)); 759 if (!max_wait_count) 760 ret = -1; 761 else { 762 PM8001_MSG_DBG(pm8001_ha, 763 pm8001_printk(" iop0 ready status in %d millisec\n", 764 (max_wait_time - max_wait_count))); 765 } 766 767 /* check iop1 status only for 16 port controllers */ 768 if ((pm8001_ha->chip_id != chip_8008) && 769 (pm8001_ha->chip_id != chip_8009)) { 770 /* 200 milli sec */ 771 max_wait_time = max_wait_count = 200 * 1000; 772 do { 773 udelay(1); 774 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 775 } while (((value & SCRATCH_PAD_IOP1_READY) != 776 SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); 777 if (!max_wait_count) 778 ret = -1; 779 else { 780 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 781 "iop1 ready status in %d millisec\n", 782 (max_wait_time - max_wait_count))); 783 } 784 } 785 786 return ret; 787 } 788 789 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 790 { 791 void __iomem *base_addr; 792 u32 value; 793 u32 offset; 794 u32 pcibar; 795 u32 pcilogic; 796 797 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 798 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 799 800 PM8001_INIT_DBG(pm8001_ha, 801 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n", 802 offset, value)); 803 pcilogic = (value & 0xFC000000) >> 26; 804 pcibar = get_pci_bar_index(pcilogic); 805 PM8001_INIT_DBG(pm8001_ha, 806 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 807 pm8001_ha->main_cfg_tbl_addr = base_addr = 808 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 809 pm8001_ha->general_stat_tbl_addr = 810 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 811 0xFFFFFF); 812 pm8001_ha->inbnd_q_tbl_addr = 813 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 814 0xFFFFFF); 815 pm8001_ha->outbnd_q_tbl_addr = 816 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 817 0xFFFFFF); 818 pm8001_ha->ivt_tbl_addr = 819 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 820 0xFFFFFF); 821 pm8001_ha->pspa_q_tbl_addr = 822 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 823 0xFFFFFF); 824 pm8001_ha->fatal_tbl_addr = 825 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 826 0xFFFFFF); 827 828 PM8001_INIT_DBG(pm8001_ha, 829 pm8001_printk("GST OFFSET 0x%x\n", 830 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18))); 831 PM8001_INIT_DBG(pm8001_ha, 832 pm8001_printk("INBND OFFSET 0x%x\n", 833 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C))); 834 PM8001_INIT_DBG(pm8001_ha, 835 pm8001_printk("OBND OFFSET 0x%x\n", 836 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20))); 837 PM8001_INIT_DBG(pm8001_ha, 838 pm8001_printk("IVT OFFSET 0x%x\n", 839 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C))); 840 PM8001_INIT_DBG(pm8001_ha, 841 pm8001_printk("PSPA OFFSET 0x%x\n", 842 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90))); 843 PM8001_INIT_DBG(pm8001_ha, 844 pm8001_printk("addr - main cfg %p general status %p\n", 845 pm8001_ha->main_cfg_tbl_addr, 846 pm8001_ha->general_stat_tbl_addr)); 847 PM8001_INIT_DBG(pm8001_ha, 848 pm8001_printk("addr - inbnd %p obnd %p\n", 849 pm8001_ha->inbnd_q_tbl_addr, 850 pm8001_ha->outbnd_q_tbl_addr)); 851 PM8001_INIT_DBG(pm8001_ha, 852 pm8001_printk("addr - pspa %p ivt %p\n", 853 pm8001_ha->pspa_q_tbl_addr, 854 pm8001_ha->ivt_tbl_addr)); 855 } 856 857 /** 858 * pm80xx_set_thermal_config - support the thermal configuration 859 * @pm8001_ha: our hba card information. 860 */ 861 int 862 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 863 { 864 struct set_ctrl_cfg_req payload; 865 struct inbound_queue_table *circularQ; 866 int rc; 867 u32 tag; 868 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 869 u32 page_code; 870 871 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 872 rc = pm8001_tag_alloc(pm8001_ha, &tag); 873 if (rc) 874 return -1; 875 876 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 877 payload.tag = cpu_to_le32(tag); 878 879 if (IS_SPCV_12G(pm8001_ha->pdev)) 880 page_code = THERMAL_PAGE_CODE_7H; 881 else 882 page_code = THERMAL_PAGE_CODE_8H; 883 884 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 885 (THERMAL_ENABLE << 8) | page_code; 886 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 887 888 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 889 if (rc) 890 pm8001_tag_free(pm8001_ha, tag); 891 return rc; 892 893 } 894 895 /** 896 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 897 * Timer configuration page 898 * @pm8001_ha: our hba card information. 899 */ 900 static int 901 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 902 { 903 struct set_ctrl_cfg_req payload; 904 struct inbound_queue_table *circularQ; 905 SASProtocolTimerConfig_t SASConfigPage; 906 int rc; 907 u32 tag; 908 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 909 910 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 911 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 912 913 rc = pm8001_tag_alloc(pm8001_ha, &tag); 914 915 if (rc) 916 return -1; 917 918 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 919 payload.tag = cpu_to_le32(tag); 920 921 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 922 SASConfigPage.MST_MSI = 3 << 15; 923 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 924 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 925 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 926 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 927 928 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 929 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 930 931 932 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 933 SAS_OPNRJT_RTRY_INTVL; 934 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 935 | SAS_COPNRJT_RTRY_TMO; 936 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 937 | SAS_COPNRJT_RTRY_THR; 938 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 939 940 PM8001_INIT_DBG(pm8001_ha, 941 pm8001_printk("SASConfigPage.pageCode " 942 "0x%08x\n", SASConfigPage.pageCode)); 943 PM8001_INIT_DBG(pm8001_ha, 944 pm8001_printk("SASConfigPage.MST_MSI " 945 " 0x%08x\n", SASConfigPage.MST_MSI)); 946 PM8001_INIT_DBG(pm8001_ha, 947 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO " 948 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO)); 949 PM8001_INIT_DBG(pm8001_ha, 950 pm8001_printk("SASConfigPage.STP_FRM_TMO " 951 " 0x%08x\n", SASConfigPage.STP_FRM_TMO)); 952 PM8001_INIT_DBG(pm8001_ha, 953 pm8001_printk("SASConfigPage.STP_IDLE_TMO " 954 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO)); 955 PM8001_INIT_DBG(pm8001_ha, 956 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL " 957 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL)); 958 PM8001_INIT_DBG(pm8001_ha, 959 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO " 960 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 961 PM8001_INIT_DBG(pm8001_ha, 962 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR " 963 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 964 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP " 965 " 0x%08x\n", SASConfigPage.MAX_AIP)); 966 967 memcpy(&payload.cfg_pg, &SASConfigPage, 968 sizeof(SASProtocolTimerConfig_t)); 969 970 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 971 if (rc) 972 pm8001_tag_free(pm8001_ha, tag); 973 974 return rc; 975 } 976 977 /** 978 * pm80xx_get_encrypt_info - Check for encryption 979 * @pm8001_ha: our hba card information. 980 */ 981 static int 982 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 983 { 984 u32 scratch3_value; 985 int ret = -1; 986 987 /* Read encryption status from SCRATCH PAD 3 */ 988 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 989 990 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 991 SCRATCH_PAD3_ENC_READY) { 992 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 993 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 994 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 995 SCRATCH_PAD3_SMF_ENABLED) 996 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 997 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 998 SCRATCH_PAD3_SMA_ENABLED) 999 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1000 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1001 SCRATCH_PAD3_SMB_ENABLED) 1002 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1003 pm8001_ha->encrypt_info.status = 0; 1004 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1005 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X." 1006 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1007 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1008 pm8001_ha->encrypt_info.sec_mode, 1009 pm8001_ha->encrypt_info.status)); 1010 ret = 0; 1011 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1012 SCRATCH_PAD3_ENC_DISABLED) { 1013 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1014 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1015 scratch3_value)); 1016 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1017 pm8001_ha->encrypt_info.cipher_mode = 0; 1018 pm8001_ha->encrypt_info.sec_mode = 0; 1019 ret = 0; 1020 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1021 SCRATCH_PAD3_ENC_DIS_ERR) { 1022 pm8001_ha->encrypt_info.status = 1023 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1024 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1025 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1026 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1027 SCRATCH_PAD3_SMF_ENABLED) 1028 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1029 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1030 SCRATCH_PAD3_SMA_ENABLED) 1031 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1032 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1033 SCRATCH_PAD3_SMB_ENABLED) 1034 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1035 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1036 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X." 1037 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1038 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1039 pm8001_ha->encrypt_info.sec_mode, 1040 pm8001_ha->encrypt_info.status)); 1041 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1042 SCRATCH_PAD3_ENC_ENA_ERR) { 1043 1044 pm8001_ha->encrypt_info.status = 1045 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1046 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1047 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1048 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1049 SCRATCH_PAD3_SMF_ENABLED) 1050 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1051 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1052 SCRATCH_PAD3_SMA_ENABLED) 1053 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1054 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1055 SCRATCH_PAD3_SMB_ENABLED) 1056 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1057 1058 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1059 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X." 1060 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1061 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1062 pm8001_ha->encrypt_info.sec_mode, 1063 pm8001_ha->encrypt_info.status)); 1064 } 1065 return ret; 1066 } 1067 1068 /** 1069 * pm80xx_encrypt_update - update flash with encryption informtion 1070 * @pm8001_ha: our hba card information. 1071 */ 1072 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1073 { 1074 struct kek_mgmt_req payload; 1075 struct inbound_queue_table *circularQ; 1076 int rc; 1077 u32 tag; 1078 u32 opc = OPC_INB_KEK_MANAGEMENT; 1079 1080 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1081 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1082 if (rc) 1083 return -1; 1084 1085 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1086 payload.tag = cpu_to_le32(tag); 1087 /* Currently only one key is used. New KEK index is 1. 1088 * Current KEK index is 1. Store KEK to NVRAM is 1. 1089 */ 1090 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1091 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1092 1093 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 1094 if (rc) 1095 pm8001_tag_free(pm8001_ha, tag); 1096 1097 return rc; 1098 } 1099 1100 /** 1101 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 1102 * @pm8001_ha: our hba card information 1103 */ 1104 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1105 { 1106 int ret; 1107 u8 i = 0; 1108 1109 /* check the firmware status */ 1110 if (-1 == check_fw_ready(pm8001_ha)) { 1111 PM8001_FAIL_DBG(pm8001_ha, 1112 pm8001_printk("Firmware is not ready!\n")); 1113 return -EBUSY; 1114 } 1115 1116 /* Initialize the controller fatal error flag */ 1117 pm8001_ha->controller_fatal_error = false; 1118 1119 /* Initialize pci space address eg: mpi offset */ 1120 init_pci_device_addresses(pm8001_ha); 1121 init_default_table_values(pm8001_ha); 1122 read_main_config_table(pm8001_ha); 1123 read_general_status_table(pm8001_ha); 1124 read_inbnd_queue_table(pm8001_ha); 1125 read_outbnd_queue_table(pm8001_ha); 1126 read_phy_attr_table(pm8001_ha); 1127 1128 /* update main config table ,inbound table and outbound table */ 1129 update_main_config_table(pm8001_ha); 1130 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) 1131 update_inbnd_queue_table(pm8001_ha, i); 1132 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) 1133 update_outbnd_queue_table(pm8001_ha, i); 1134 1135 /* notify firmware update finished and check initialization status */ 1136 if (0 == mpi_init_check(pm8001_ha)) { 1137 PM8001_INIT_DBG(pm8001_ha, 1138 pm8001_printk("MPI initialize successful!\n")); 1139 } else 1140 return -EBUSY; 1141 1142 /* send SAS protocol timer configuration page to FW */ 1143 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1144 1145 /* Check for encryption */ 1146 if (pm8001_ha->chip->encrypt) { 1147 PM8001_INIT_DBG(pm8001_ha, 1148 pm8001_printk("Checking for encryption\n")); 1149 ret = pm80xx_get_encrypt_info(pm8001_ha); 1150 if (ret == -1) { 1151 PM8001_INIT_DBG(pm8001_ha, 1152 pm8001_printk("Encryption error !!\n")); 1153 if (pm8001_ha->encrypt_info.status == 0x81) { 1154 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1155 "Encryption enabled with error." 1156 "Saving encryption key to flash\n")); 1157 pm80xx_encrypt_update(pm8001_ha); 1158 } 1159 } 1160 } 1161 return 0; 1162 } 1163 1164 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1165 { 1166 u32 max_wait_count; 1167 u32 value; 1168 u32 gst_len_mpistate; 1169 init_pci_device_addresses(pm8001_ha); 1170 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1171 table is stop */ 1172 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1173 1174 /* wait until Inbound DoorBell Clear Register toggled */ 1175 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1176 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 1177 } else { 1178 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1179 } 1180 do { 1181 udelay(1); 1182 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1183 value &= SPCv_MSGU_CFG_TABLE_RESET; 1184 } while ((value != 0) && (--max_wait_count)); 1185 1186 if (!max_wait_count) { 1187 PM8001_FAIL_DBG(pm8001_ha, 1188 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value)); 1189 return -1; 1190 } 1191 1192 /* check the MPI-State for termination in progress */ 1193 /* wait until Inbound DoorBell Clear Register toggled */ 1194 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 1195 do { 1196 udelay(1); 1197 gst_len_mpistate = 1198 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1199 GST_GSTLEN_MPIS_OFFSET); 1200 if (GST_MPI_STATE_UNINIT == 1201 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1202 break; 1203 } while (--max_wait_count); 1204 if (!max_wait_count) { 1205 PM8001_FAIL_DBG(pm8001_ha, 1206 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 1207 gst_len_mpistate & GST_MPI_STATE_MASK)); 1208 return -1; 1209 } 1210 1211 return 0; 1212 } 1213 1214 /** 1215 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1216 * the FW register status to the originated status. 1217 * @pm8001_ha: our hba card information 1218 */ 1219 1220 static int 1221 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1222 { 1223 u32 regval; 1224 u32 bootloader_state; 1225 u32 ibutton0, ibutton1; 1226 1227 /* Process MPI table uninitialization only if FW is ready */ 1228 if (!pm8001_ha->controller_fatal_error) { 1229 /* Check if MPI is in ready state to reset */ 1230 if (mpi_uninit_check(pm8001_ha) != 0) { 1231 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1232 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1233 "MPI state is not ready scratch1 :0x%x\n", 1234 regval)); 1235 return -1; 1236 } 1237 } 1238 /* checked for reset register normal state; 0x0 */ 1239 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1240 PM8001_INIT_DBG(pm8001_ha, 1241 pm8001_printk("reset register before write : 0x%x\n", regval)); 1242 1243 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1244 mdelay(500); 1245 1246 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1247 PM8001_INIT_DBG(pm8001_ha, 1248 pm8001_printk("reset register after write 0x%x\n", regval)); 1249 1250 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1251 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1252 PM8001_MSG_DBG(pm8001_ha, 1253 pm8001_printk(" soft reset successful [regval: 0x%x]\n", 1254 regval)); 1255 } else { 1256 PM8001_MSG_DBG(pm8001_ha, 1257 pm8001_printk(" soft reset failed [regval: 0x%x]\n", 1258 regval)); 1259 1260 /* check bootloader is successfully executed or in HDA mode */ 1261 bootloader_state = 1262 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1263 SCRATCH_PAD1_BOOTSTATE_MASK; 1264 1265 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1266 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1267 "Bootloader state - HDA mode SEEPROM\n")); 1268 } else if (bootloader_state == 1269 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1270 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1271 "Bootloader state - HDA mode Bootstrap Pin\n")); 1272 } else if (bootloader_state == 1273 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1274 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1275 "Bootloader state - HDA mode soft reset\n")); 1276 } else if (bootloader_state == 1277 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1278 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1279 "Bootloader state-HDA mode critical error\n")); 1280 } 1281 return -EBUSY; 1282 } 1283 1284 /* check the firmware status after reset */ 1285 if (-1 == check_fw_ready(pm8001_ha)) { 1286 PM8001_FAIL_DBG(pm8001_ha, 1287 pm8001_printk("Firmware is not ready!\n")); 1288 /* check iButton feature support for motherboard controller */ 1289 if (pm8001_ha->pdev->subsystem_vendor != 1290 PCI_VENDOR_ID_ADAPTEC2 && 1291 pm8001_ha->pdev->subsystem_vendor != 1292 PCI_VENDOR_ID_ATTO && 1293 pm8001_ha->pdev->subsystem_vendor != 0) { 1294 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1295 MSGU_HOST_SCRATCH_PAD_6); 1296 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1297 MSGU_HOST_SCRATCH_PAD_7); 1298 if (!ibutton0 && !ibutton1) { 1299 PM8001_FAIL_DBG(pm8001_ha, 1300 pm8001_printk("iButton Feature is" 1301 " not Available!!!\n")); 1302 return -EBUSY; 1303 } 1304 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1305 PM8001_FAIL_DBG(pm8001_ha, 1306 pm8001_printk("CRC Check for iButton" 1307 " Feature Failed!!!\n")); 1308 return -EBUSY; 1309 } 1310 } 1311 } 1312 PM8001_INIT_DBG(pm8001_ha, 1313 pm8001_printk("SPCv soft reset Complete\n")); 1314 return 0; 1315 } 1316 1317 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1318 { 1319 u32 i; 1320 1321 PM8001_INIT_DBG(pm8001_ha, 1322 pm8001_printk("chip reset start\n")); 1323 1324 /* do SPCv chip reset. */ 1325 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1326 PM8001_INIT_DBG(pm8001_ha, 1327 pm8001_printk("SPC soft reset Complete\n")); 1328 1329 /* Check this ..whether delay is required or no */ 1330 /* delay 10 usec */ 1331 udelay(10); 1332 1333 /* wait for 20 msec until the firmware gets reloaded */ 1334 i = 20; 1335 do { 1336 mdelay(1); 1337 } while ((--i) != 0); 1338 1339 PM8001_INIT_DBG(pm8001_ha, 1340 pm8001_printk("chip reset finished\n")); 1341 } 1342 1343 /** 1344 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1345 * @pm8001_ha: our hba card information 1346 */ 1347 static void 1348 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1349 { 1350 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1351 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1352 } 1353 1354 /** 1355 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1356 * @pm8001_ha: our hba card information 1357 */ 1358 static void 1359 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1360 { 1361 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1362 } 1363 1364 /** 1365 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1366 * @pm8001_ha: our hba card information 1367 */ 1368 static void 1369 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1370 { 1371 #ifdef PM8001_USE_MSIX 1372 u32 mask; 1373 mask = (u32)(1 << vec); 1374 1375 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1376 return; 1377 #endif 1378 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1379 1380 } 1381 1382 /** 1383 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1384 * @pm8001_ha: our hba card information 1385 */ 1386 static void 1387 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1388 { 1389 #ifdef PM8001_USE_MSIX 1390 u32 mask; 1391 if (vec == 0xFF) 1392 mask = 0xFFFFFFFF; 1393 else 1394 mask = (u32)(1 << vec); 1395 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1396 return; 1397 #endif 1398 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1399 } 1400 1401 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1402 struct pm8001_device *pm8001_ha_dev) 1403 { 1404 int res; 1405 u32 ccb_tag; 1406 struct pm8001_ccb_info *ccb; 1407 struct sas_task *task = NULL; 1408 struct task_abort_req task_abort; 1409 struct inbound_queue_table *circularQ; 1410 u32 opc = OPC_INB_SATA_ABORT; 1411 int ret; 1412 1413 if (!pm8001_ha_dev) { 1414 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1415 return; 1416 } 1417 1418 task = sas_alloc_slow_task(GFP_ATOMIC); 1419 1420 if (!task) { 1421 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1422 "allocate task\n")); 1423 return; 1424 } 1425 1426 task->task_done = pm8001_task_done; 1427 1428 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1429 if (res) { 1430 sas_free_task(task); 1431 return; 1432 } 1433 1434 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1435 ccb->device = pm8001_ha_dev; 1436 ccb->ccb_tag = ccb_tag; 1437 ccb->task = task; 1438 1439 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1440 1441 memset(&task_abort, 0, sizeof(task_abort)); 1442 task_abort.abort_all = cpu_to_le32(1); 1443 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1444 task_abort.tag = cpu_to_le32(ccb_tag); 1445 1446 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 1447 if (ret) { 1448 sas_free_task(task); 1449 pm8001_tag_free(pm8001_ha, ccb_tag); 1450 } 1451 } 1452 1453 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1454 struct pm8001_device *pm8001_ha_dev) 1455 { 1456 struct sata_start_req sata_cmd; 1457 int res; 1458 u32 ccb_tag; 1459 struct pm8001_ccb_info *ccb; 1460 struct sas_task *task = NULL; 1461 struct host_to_dev_fis fis; 1462 struct domain_device *dev; 1463 struct inbound_queue_table *circularQ; 1464 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1465 1466 task = sas_alloc_slow_task(GFP_ATOMIC); 1467 1468 if (!task) { 1469 PM8001_FAIL_DBG(pm8001_ha, 1470 pm8001_printk("cannot allocate task !!!\n")); 1471 return; 1472 } 1473 task->task_done = pm8001_task_done; 1474 1475 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1476 if (res) { 1477 sas_free_task(task); 1478 PM8001_FAIL_DBG(pm8001_ha, 1479 pm8001_printk("cannot allocate tag !!!\n")); 1480 return; 1481 } 1482 1483 /* allocate domain device by ourselves as libsas 1484 * is not going to provide any 1485 */ 1486 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1487 if (!dev) { 1488 sas_free_task(task); 1489 pm8001_tag_free(pm8001_ha, ccb_tag); 1490 PM8001_FAIL_DBG(pm8001_ha, 1491 pm8001_printk("Domain device cannot be allocated\n")); 1492 return; 1493 } 1494 1495 task->dev = dev; 1496 task->dev->lldd_dev = pm8001_ha_dev; 1497 1498 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1499 ccb->device = pm8001_ha_dev; 1500 ccb->ccb_tag = ccb_tag; 1501 ccb->task = task; 1502 ccb->n_elem = 0; 1503 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1504 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1505 1506 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1507 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1508 1509 /* construct read log FIS */ 1510 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1511 fis.fis_type = 0x27; 1512 fis.flags = 0x80; 1513 fis.command = ATA_CMD_READ_LOG_EXT; 1514 fis.lbal = 0x10; 1515 fis.sector_count = 0x1; 1516 1517 sata_cmd.tag = cpu_to_le32(ccb_tag); 1518 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1519 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1520 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1521 1522 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 1523 if (res) { 1524 sas_free_task(task); 1525 pm8001_tag_free(pm8001_ha, ccb_tag); 1526 kfree(dev); 1527 } 1528 } 1529 1530 /** 1531 * mpi_ssp_completion- process the event that FW response to the SSP request. 1532 * @pm8001_ha: our hba card information 1533 * @piomb: the message contents of this outbound message. 1534 * 1535 * When FW has completed a ssp request for example a IO request, after it has 1536 * filled the SG data with the data, it will trigger this event represent 1537 * that he has finished the job,please check the coresponding buffer. 1538 * So we will tell the caller who maybe waiting the result to tell upper layer 1539 * that the task has been finished. 1540 */ 1541 static void 1542 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1543 { 1544 struct sas_task *t; 1545 struct pm8001_ccb_info *ccb; 1546 unsigned long flags; 1547 u32 status; 1548 u32 param; 1549 u32 tag; 1550 struct ssp_completion_resp *psspPayload; 1551 struct task_status_struct *ts; 1552 struct ssp_response_iu *iu; 1553 struct pm8001_device *pm8001_dev; 1554 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1555 status = le32_to_cpu(psspPayload->status); 1556 tag = le32_to_cpu(psspPayload->tag); 1557 ccb = &pm8001_ha->ccb_info[tag]; 1558 if ((status == IO_ABORTED) && ccb->open_retry) { 1559 /* Being completed by another */ 1560 ccb->open_retry = 0; 1561 return; 1562 } 1563 pm8001_dev = ccb->device; 1564 param = le32_to_cpu(psspPayload->param); 1565 t = ccb->task; 1566 1567 if (status && status != IO_UNDERFLOW) 1568 PM8001_FAIL_DBG(pm8001_ha, 1569 pm8001_printk("sas IO status 0x%x\n", status)); 1570 if (unlikely(!t || !t->lldd_task || !t->dev)) 1571 return; 1572 ts = &t->task_status; 1573 /* Print sas address of IO failed device */ 1574 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1575 (status != IO_UNDERFLOW)) 1576 PM8001_FAIL_DBG(pm8001_ha, 1577 pm8001_printk("SAS Address of IO Failure Drive" 1578 ":%016llx", SAS_ADDR(t->dev->sas_addr))); 1579 1580 switch (status) { 1581 case IO_SUCCESS: 1582 PM8001_IO_DBG(pm8001_ha, 1583 pm8001_printk("IO_SUCCESS ,param = 0x%x\n", 1584 param)); 1585 if (param == 0) { 1586 ts->resp = SAS_TASK_COMPLETE; 1587 ts->stat = SAM_STAT_GOOD; 1588 } else { 1589 ts->resp = SAS_TASK_COMPLETE; 1590 ts->stat = SAS_PROTO_RESPONSE; 1591 ts->residual = param; 1592 iu = &psspPayload->ssp_resp_iu; 1593 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1594 } 1595 if (pm8001_dev) 1596 pm8001_dev->running_req--; 1597 break; 1598 case IO_ABORTED: 1599 PM8001_IO_DBG(pm8001_ha, 1600 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1601 ts->resp = SAS_TASK_COMPLETE; 1602 ts->stat = SAS_ABORTED_TASK; 1603 break; 1604 case IO_UNDERFLOW: 1605 /* SSP Completion with error */ 1606 PM8001_IO_DBG(pm8001_ha, 1607 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n", 1608 param)); 1609 ts->resp = SAS_TASK_COMPLETE; 1610 ts->stat = SAS_DATA_UNDERRUN; 1611 ts->residual = param; 1612 if (pm8001_dev) 1613 pm8001_dev->running_req--; 1614 break; 1615 case IO_NO_DEVICE: 1616 PM8001_IO_DBG(pm8001_ha, 1617 pm8001_printk("IO_NO_DEVICE\n")); 1618 ts->resp = SAS_TASK_UNDELIVERED; 1619 ts->stat = SAS_PHY_DOWN; 1620 break; 1621 case IO_XFER_ERROR_BREAK: 1622 PM8001_IO_DBG(pm8001_ha, 1623 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1624 ts->resp = SAS_TASK_COMPLETE; 1625 ts->stat = SAS_OPEN_REJECT; 1626 /* Force the midlayer to retry */ 1627 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1628 break; 1629 case IO_XFER_ERROR_PHY_NOT_READY: 1630 PM8001_IO_DBG(pm8001_ha, 1631 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1632 ts->resp = SAS_TASK_COMPLETE; 1633 ts->stat = SAS_OPEN_REJECT; 1634 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1635 break; 1636 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1637 PM8001_IO_DBG(pm8001_ha, 1638 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n")); 1639 ts->resp = SAS_TASK_COMPLETE; 1640 ts->stat = SAS_OPEN_REJECT; 1641 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1642 break; 1643 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1644 PM8001_IO_DBG(pm8001_ha, 1645 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1646 ts->resp = SAS_TASK_COMPLETE; 1647 ts->stat = SAS_OPEN_REJECT; 1648 ts->open_rej_reason = SAS_OREJ_EPROTO; 1649 break; 1650 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1651 PM8001_IO_DBG(pm8001_ha, 1652 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1653 ts->resp = SAS_TASK_COMPLETE; 1654 ts->stat = SAS_OPEN_REJECT; 1655 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1656 break; 1657 case IO_OPEN_CNX_ERROR_BREAK: 1658 PM8001_IO_DBG(pm8001_ha, 1659 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1660 ts->resp = SAS_TASK_COMPLETE; 1661 ts->stat = SAS_OPEN_REJECT; 1662 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1663 break; 1664 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1665 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1666 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1667 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1668 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1669 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1670 PM8001_IO_DBG(pm8001_ha, 1671 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1672 ts->resp = SAS_TASK_COMPLETE; 1673 ts->stat = SAS_OPEN_REJECT; 1674 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1675 if (!t->uldd_task) 1676 pm8001_handle_event(pm8001_ha, 1677 pm8001_dev, 1678 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1679 break; 1680 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1681 PM8001_IO_DBG(pm8001_ha, 1682 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1683 ts->resp = SAS_TASK_COMPLETE; 1684 ts->stat = SAS_OPEN_REJECT; 1685 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1686 break; 1687 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1688 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1689 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1690 ts->resp = SAS_TASK_COMPLETE; 1691 ts->stat = SAS_OPEN_REJECT; 1692 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1693 break; 1694 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1695 PM8001_IO_DBG(pm8001_ha, 1696 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1697 ts->resp = SAS_TASK_UNDELIVERED; 1698 ts->stat = SAS_OPEN_REJECT; 1699 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1700 break; 1701 case IO_XFER_ERROR_NAK_RECEIVED: 1702 PM8001_IO_DBG(pm8001_ha, 1703 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1704 ts->resp = SAS_TASK_COMPLETE; 1705 ts->stat = SAS_OPEN_REJECT; 1706 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1707 break; 1708 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1709 PM8001_IO_DBG(pm8001_ha, 1710 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1711 ts->resp = SAS_TASK_COMPLETE; 1712 ts->stat = SAS_NAK_R_ERR; 1713 break; 1714 case IO_XFER_ERROR_DMA: 1715 PM8001_IO_DBG(pm8001_ha, 1716 pm8001_printk("IO_XFER_ERROR_DMA\n")); 1717 ts->resp = SAS_TASK_COMPLETE; 1718 ts->stat = SAS_OPEN_REJECT; 1719 break; 1720 case IO_XFER_OPEN_RETRY_TIMEOUT: 1721 PM8001_IO_DBG(pm8001_ha, 1722 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1723 ts->resp = SAS_TASK_COMPLETE; 1724 ts->stat = SAS_OPEN_REJECT; 1725 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1726 break; 1727 case IO_XFER_ERROR_OFFSET_MISMATCH: 1728 PM8001_IO_DBG(pm8001_ha, 1729 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1730 ts->resp = SAS_TASK_COMPLETE; 1731 ts->stat = SAS_OPEN_REJECT; 1732 break; 1733 case IO_PORT_IN_RESET: 1734 PM8001_IO_DBG(pm8001_ha, 1735 pm8001_printk("IO_PORT_IN_RESET\n")); 1736 ts->resp = SAS_TASK_COMPLETE; 1737 ts->stat = SAS_OPEN_REJECT; 1738 break; 1739 case IO_DS_NON_OPERATIONAL: 1740 PM8001_IO_DBG(pm8001_ha, 1741 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1742 ts->resp = SAS_TASK_COMPLETE; 1743 ts->stat = SAS_OPEN_REJECT; 1744 if (!t->uldd_task) 1745 pm8001_handle_event(pm8001_ha, 1746 pm8001_dev, 1747 IO_DS_NON_OPERATIONAL); 1748 break; 1749 case IO_DS_IN_RECOVERY: 1750 PM8001_IO_DBG(pm8001_ha, 1751 pm8001_printk("IO_DS_IN_RECOVERY\n")); 1752 ts->resp = SAS_TASK_COMPLETE; 1753 ts->stat = SAS_OPEN_REJECT; 1754 break; 1755 case IO_TM_TAG_NOT_FOUND: 1756 PM8001_IO_DBG(pm8001_ha, 1757 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1758 ts->resp = SAS_TASK_COMPLETE; 1759 ts->stat = SAS_OPEN_REJECT; 1760 break; 1761 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1762 PM8001_IO_DBG(pm8001_ha, 1763 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1764 ts->resp = SAS_TASK_COMPLETE; 1765 ts->stat = SAS_OPEN_REJECT; 1766 break; 1767 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1768 PM8001_IO_DBG(pm8001_ha, 1769 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1770 ts->resp = SAS_TASK_COMPLETE; 1771 ts->stat = SAS_OPEN_REJECT; 1772 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1773 break; 1774 default: 1775 PM8001_IO_DBG(pm8001_ha, 1776 pm8001_printk("Unknown status 0x%x\n", status)); 1777 /* not allowed case. Therefore, return failed status */ 1778 ts->resp = SAS_TASK_COMPLETE; 1779 ts->stat = SAS_OPEN_REJECT; 1780 break; 1781 } 1782 PM8001_IO_DBG(pm8001_ha, 1783 pm8001_printk("scsi_status = 0x%x\n ", 1784 psspPayload->ssp_resp_iu.status)); 1785 spin_lock_irqsave(&t->task_state_lock, flags); 1786 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1787 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1788 t->task_state_flags |= SAS_TASK_STATE_DONE; 1789 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1790 spin_unlock_irqrestore(&t->task_state_lock, flags); 1791 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1792 "task 0x%p done with io_status 0x%x resp 0x%x " 1793 "stat 0x%x but aborted by upper layer!\n", 1794 t, status, ts->resp, ts->stat)); 1795 if (t->slow_task) 1796 complete(&t->slow_task->completion); 1797 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1798 } else { 1799 spin_unlock_irqrestore(&t->task_state_lock, flags); 1800 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1801 mb();/* in order to force CPU ordering */ 1802 t->task_done(t); 1803 } 1804 } 1805 1806 /*See the comments for mpi_ssp_completion */ 1807 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 1808 { 1809 struct sas_task *t; 1810 unsigned long flags; 1811 struct task_status_struct *ts; 1812 struct pm8001_ccb_info *ccb; 1813 struct pm8001_device *pm8001_dev; 1814 struct ssp_event_resp *psspPayload = 1815 (struct ssp_event_resp *)(piomb + 4); 1816 u32 event = le32_to_cpu(psspPayload->event); 1817 u32 tag = le32_to_cpu(psspPayload->tag); 1818 u32 port_id = le32_to_cpu(psspPayload->port_id); 1819 1820 ccb = &pm8001_ha->ccb_info[tag]; 1821 t = ccb->task; 1822 pm8001_dev = ccb->device; 1823 if (event) 1824 PM8001_FAIL_DBG(pm8001_ha, 1825 pm8001_printk("sas IO status 0x%x\n", event)); 1826 if (unlikely(!t || !t->lldd_task || !t->dev)) 1827 return; 1828 ts = &t->task_status; 1829 PM8001_IO_DBG(pm8001_ha, 1830 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 1831 port_id, tag, event)); 1832 switch (event) { 1833 case IO_OVERFLOW: 1834 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 1835 ts->resp = SAS_TASK_COMPLETE; 1836 ts->stat = SAS_DATA_OVERRUN; 1837 ts->residual = 0; 1838 if (pm8001_dev) 1839 pm8001_dev->running_req--; 1840 break; 1841 case IO_XFER_ERROR_BREAK: 1842 PM8001_IO_DBG(pm8001_ha, 1843 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1844 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 1845 return; 1846 case IO_XFER_ERROR_PHY_NOT_READY: 1847 PM8001_IO_DBG(pm8001_ha, 1848 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1849 ts->resp = SAS_TASK_COMPLETE; 1850 ts->stat = SAS_OPEN_REJECT; 1851 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1852 break; 1853 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1854 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1855 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1856 ts->resp = SAS_TASK_COMPLETE; 1857 ts->stat = SAS_OPEN_REJECT; 1858 ts->open_rej_reason = SAS_OREJ_EPROTO; 1859 break; 1860 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1861 PM8001_IO_DBG(pm8001_ha, 1862 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1863 ts->resp = SAS_TASK_COMPLETE; 1864 ts->stat = SAS_OPEN_REJECT; 1865 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1866 break; 1867 case IO_OPEN_CNX_ERROR_BREAK: 1868 PM8001_IO_DBG(pm8001_ha, 1869 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1870 ts->resp = SAS_TASK_COMPLETE; 1871 ts->stat = SAS_OPEN_REJECT; 1872 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1873 break; 1874 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1875 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1876 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1877 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1878 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1879 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1880 PM8001_IO_DBG(pm8001_ha, 1881 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1882 ts->resp = SAS_TASK_COMPLETE; 1883 ts->stat = SAS_OPEN_REJECT; 1884 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1885 if (!t->uldd_task) 1886 pm8001_handle_event(pm8001_ha, 1887 pm8001_dev, 1888 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1889 break; 1890 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1891 PM8001_IO_DBG(pm8001_ha, 1892 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1893 ts->resp = SAS_TASK_COMPLETE; 1894 ts->stat = SAS_OPEN_REJECT; 1895 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1896 break; 1897 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1898 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1899 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1900 ts->resp = SAS_TASK_COMPLETE; 1901 ts->stat = SAS_OPEN_REJECT; 1902 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1903 break; 1904 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1905 PM8001_IO_DBG(pm8001_ha, 1906 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1907 ts->resp = SAS_TASK_COMPLETE; 1908 ts->stat = SAS_OPEN_REJECT; 1909 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1910 break; 1911 case IO_XFER_ERROR_NAK_RECEIVED: 1912 PM8001_IO_DBG(pm8001_ha, 1913 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1914 ts->resp = SAS_TASK_COMPLETE; 1915 ts->stat = SAS_OPEN_REJECT; 1916 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1917 break; 1918 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1919 PM8001_IO_DBG(pm8001_ha, 1920 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1921 ts->resp = SAS_TASK_COMPLETE; 1922 ts->stat = SAS_NAK_R_ERR; 1923 break; 1924 case IO_XFER_OPEN_RETRY_TIMEOUT: 1925 PM8001_IO_DBG(pm8001_ha, 1926 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1927 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 1928 return; 1929 case IO_XFER_ERROR_UNEXPECTED_PHASE: 1930 PM8001_IO_DBG(pm8001_ha, 1931 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 1932 ts->resp = SAS_TASK_COMPLETE; 1933 ts->stat = SAS_DATA_OVERRUN; 1934 break; 1935 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 1936 PM8001_IO_DBG(pm8001_ha, 1937 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 1938 ts->resp = SAS_TASK_COMPLETE; 1939 ts->stat = SAS_DATA_OVERRUN; 1940 break; 1941 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 1942 PM8001_IO_DBG(pm8001_ha, 1943 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 1944 ts->resp = SAS_TASK_COMPLETE; 1945 ts->stat = SAS_DATA_OVERRUN; 1946 break; 1947 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 1948 PM8001_IO_DBG(pm8001_ha, 1949 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 1950 ts->resp = SAS_TASK_COMPLETE; 1951 ts->stat = SAS_DATA_OVERRUN; 1952 break; 1953 case IO_XFER_ERROR_OFFSET_MISMATCH: 1954 PM8001_IO_DBG(pm8001_ha, 1955 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1956 ts->resp = SAS_TASK_COMPLETE; 1957 ts->stat = SAS_DATA_OVERRUN; 1958 break; 1959 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 1960 PM8001_IO_DBG(pm8001_ha, 1961 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 1962 ts->resp = SAS_TASK_COMPLETE; 1963 ts->stat = SAS_DATA_OVERRUN; 1964 break; 1965 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 1966 PM8001_IO_DBG(pm8001_ha, 1967 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 1968 /* TBC: used default set values */ 1969 ts->resp = SAS_TASK_COMPLETE; 1970 ts->stat = SAS_DATA_OVERRUN; 1971 break; 1972 case IO_XFER_CMD_FRAME_ISSUED: 1973 PM8001_IO_DBG(pm8001_ha, 1974 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 1975 return; 1976 default: 1977 PM8001_IO_DBG(pm8001_ha, 1978 pm8001_printk("Unknown status 0x%x\n", event)); 1979 /* not allowed case. Therefore, return failed status */ 1980 ts->resp = SAS_TASK_COMPLETE; 1981 ts->stat = SAS_DATA_OVERRUN; 1982 break; 1983 } 1984 spin_lock_irqsave(&t->task_state_lock, flags); 1985 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1986 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1987 t->task_state_flags |= SAS_TASK_STATE_DONE; 1988 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1989 spin_unlock_irqrestore(&t->task_state_lock, flags); 1990 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1991 "task 0x%p done with event 0x%x resp 0x%x " 1992 "stat 0x%x but aborted by upper layer!\n", 1993 t, event, ts->resp, ts->stat)); 1994 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1995 } else { 1996 spin_unlock_irqrestore(&t->task_state_lock, flags); 1997 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1998 mb();/* in order to force CPU ordering */ 1999 t->task_done(t); 2000 } 2001 } 2002 2003 /*See the comments for mpi_ssp_completion */ 2004 static void 2005 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2006 { 2007 struct sas_task *t; 2008 struct pm8001_ccb_info *ccb; 2009 u32 param; 2010 u32 status; 2011 u32 tag; 2012 int i, j; 2013 u8 sata_addr_low[4]; 2014 u32 temp_sata_addr_low, temp_sata_addr_hi; 2015 u8 sata_addr_hi[4]; 2016 struct sata_completion_resp *psataPayload; 2017 struct task_status_struct *ts; 2018 struct ata_task_resp *resp ; 2019 u32 *sata_resp; 2020 struct pm8001_device *pm8001_dev; 2021 unsigned long flags; 2022 2023 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2024 status = le32_to_cpu(psataPayload->status); 2025 tag = le32_to_cpu(psataPayload->tag); 2026 2027 if (!tag) { 2028 PM8001_FAIL_DBG(pm8001_ha, 2029 pm8001_printk("tag null\n")); 2030 return; 2031 } 2032 ccb = &pm8001_ha->ccb_info[tag]; 2033 param = le32_to_cpu(psataPayload->param); 2034 if (ccb) { 2035 t = ccb->task; 2036 pm8001_dev = ccb->device; 2037 } else { 2038 PM8001_FAIL_DBG(pm8001_ha, 2039 pm8001_printk("ccb null\n")); 2040 return; 2041 } 2042 2043 if (t) { 2044 if (t->dev && (t->dev->lldd_dev)) 2045 pm8001_dev = t->dev->lldd_dev; 2046 } else { 2047 PM8001_FAIL_DBG(pm8001_ha, 2048 pm8001_printk("task null\n")); 2049 return; 2050 } 2051 2052 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2053 && unlikely(!t || !t->lldd_task || !t->dev)) { 2054 PM8001_FAIL_DBG(pm8001_ha, 2055 pm8001_printk("task or dev null\n")); 2056 return; 2057 } 2058 2059 ts = &t->task_status; 2060 if (!ts) { 2061 PM8001_FAIL_DBG(pm8001_ha, 2062 pm8001_printk("ts null\n")); 2063 return; 2064 } 2065 /* Print sas address of IO failed device */ 2066 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2067 (status != IO_UNDERFLOW)) { 2068 if (!((t->dev->parent) && 2069 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) { 2070 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 2071 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2072 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 2073 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2074 memcpy(&temp_sata_addr_low, sata_addr_low, 2075 sizeof(sata_addr_low)); 2076 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2077 sizeof(sata_addr_hi)); 2078 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2079 |((temp_sata_addr_hi << 8) & 2080 0xff0000) | 2081 ((temp_sata_addr_hi >> 8) 2082 & 0xff00) | 2083 ((temp_sata_addr_hi << 24) & 2084 0xff000000)); 2085 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2086 & 0xff) | 2087 ((temp_sata_addr_low << 8) 2088 & 0xff0000) | 2089 ((temp_sata_addr_low >> 8) 2090 & 0xff00) | 2091 ((temp_sata_addr_low << 24) 2092 & 0xff000000)) + 2093 pm8001_dev->attached_phy + 2094 0x10); 2095 PM8001_FAIL_DBG(pm8001_ha, 2096 pm8001_printk("SAS Address of IO Failure Drive:" 2097 "%08x%08x", temp_sata_addr_hi, 2098 temp_sata_addr_low)); 2099 2100 } else { 2101 PM8001_FAIL_DBG(pm8001_ha, 2102 pm8001_printk("SAS Address of IO Failure Drive:" 2103 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2104 } 2105 } 2106 switch (status) { 2107 case IO_SUCCESS: 2108 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2109 if (param == 0) { 2110 ts->resp = SAS_TASK_COMPLETE; 2111 ts->stat = SAM_STAT_GOOD; 2112 /* check if response is for SEND READ LOG */ 2113 if (pm8001_dev && 2114 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2115 /* set new bit for abort_all */ 2116 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2117 /* clear bit for read log */ 2118 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2119 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2120 /* Free the tag */ 2121 pm8001_tag_free(pm8001_ha, tag); 2122 sas_free_task(t); 2123 return; 2124 } 2125 } else { 2126 u8 len; 2127 ts->resp = SAS_TASK_COMPLETE; 2128 ts->stat = SAS_PROTO_RESPONSE; 2129 ts->residual = param; 2130 PM8001_IO_DBG(pm8001_ha, 2131 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2132 param)); 2133 sata_resp = &psataPayload->sata_resp[0]; 2134 resp = (struct ata_task_resp *)ts->buf; 2135 if (t->ata_task.dma_xfer == 0 && 2136 t->data_dir == DMA_FROM_DEVICE) { 2137 len = sizeof(struct pio_setup_fis); 2138 PM8001_IO_DBG(pm8001_ha, 2139 pm8001_printk("PIO read len = %d\n", len)); 2140 } else if (t->ata_task.use_ncq) { 2141 len = sizeof(struct set_dev_bits_fis); 2142 PM8001_IO_DBG(pm8001_ha, 2143 pm8001_printk("FPDMA len = %d\n", len)); 2144 } else { 2145 len = sizeof(struct dev_to_host_fis); 2146 PM8001_IO_DBG(pm8001_ha, 2147 pm8001_printk("other len = %d\n", len)); 2148 } 2149 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2150 resp->frame_len = len; 2151 memcpy(&resp->ending_fis[0], sata_resp, len); 2152 ts->buf_valid_size = sizeof(*resp); 2153 } else 2154 PM8001_IO_DBG(pm8001_ha, 2155 pm8001_printk("response to large\n")); 2156 } 2157 if (pm8001_dev) 2158 pm8001_dev->running_req--; 2159 break; 2160 case IO_ABORTED: 2161 PM8001_IO_DBG(pm8001_ha, 2162 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2163 ts->resp = SAS_TASK_COMPLETE; 2164 ts->stat = SAS_ABORTED_TASK; 2165 if (pm8001_dev) 2166 pm8001_dev->running_req--; 2167 break; 2168 /* following cases are to do cases */ 2169 case IO_UNDERFLOW: 2170 /* SATA Completion with error */ 2171 PM8001_IO_DBG(pm8001_ha, 2172 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2173 ts->resp = SAS_TASK_COMPLETE; 2174 ts->stat = SAS_DATA_UNDERRUN; 2175 ts->residual = param; 2176 if (pm8001_dev) 2177 pm8001_dev->running_req--; 2178 break; 2179 case IO_NO_DEVICE: 2180 PM8001_IO_DBG(pm8001_ha, 2181 pm8001_printk("IO_NO_DEVICE\n")); 2182 ts->resp = SAS_TASK_UNDELIVERED; 2183 ts->stat = SAS_PHY_DOWN; 2184 break; 2185 case IO_XFER_ERROR_BREAK: 2186 PM8001_IO_DBG(pm8001_ha, 2187 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2188 ts->resp = SAS_TASK_COMPLETE; 2189 ts->stat = SAS_INTERRUPTED; 2190 break; 2191 case IO_XFER_ERROR_PHY_NOT_READY: 2192 PM8001_IO_DBG(pm8001_ha, 2193 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2194 ts->resp = SAS_TASK_COMPLETE; 2195 ts->stat = SAS_OPEN_REJECT; 2196 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2197 break; 2198 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2199 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2200 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2201 ts->resp = SAS_TASK_COMPLETE; 2202 ts->stat = SAS_OPEN_REJECT; 2203 ts->open_rej_reason = SAS_OREJ_EPROTO; 2204 break; 2205 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2206 PM8001_IO_DBG(pm8001_ha, 2207 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2208 ts->resp = SAS_TASK_COMPLETE; 2209 ts->stat = SAS_OPEN_REJECT; 2210 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2211 break; 2212 case IO_OPEN_CNX_ERROR_BREAK: 2213 PM8001_IO_DBG(pm8001_ha, 2214 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2215 ts->resp = SAS_TASK_COMPLETE; 2216 ts->stat = SAS_OPEN_REJECT; 2217 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2218 break; 2219 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2220 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2221 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2222 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2223 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2224 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2225 PM8001_IO_DBG(pm8001_ha, 2226 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2227 ts->resp = SAS_TASK_COMPLETE; 2228 ts->stat = SAS_DEV_NO_RESPONSE; 2229 if (!t->uldd_task) { 2230 pm8001_handle_event(pm8001_ha, 2231 pm8001_dev, 2232 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2233 ts->resp = SAS_TASK_UNDELIVERED; 2234 ts->stat = SAS_QUEUE_FULL; 2235 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2236 return; 2237 } 2238 break; 2239 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2240 PM8001_IO_DBG(pm8001_ha, 2241 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2242 ts->resp = SAS_TASK_UNDELIVERED; 2243 ts->stat = SAS_OPEN_REJECT; 2244 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2245 if (!t->uldd_task) { 2246 pm8001_handle_event(pm8001_ha, 2247 pm8001_dev, 2248 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2249 ts->resp = SAS_TASK_UNDELIVERED; 2250 ts->stat = SAS_QUEUE_FULL; 2251 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2252 return; 2253 } 2254 break; 2255 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2256 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2257 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2258 ts->resp = SAS_TASK_COMPLETE; 2259 ts->stat = SAS_OPEN_REJECT; 2260 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2261 break; 2262 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2263 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2264 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); 2265 ts->resp = SAS_TASK_COMPLETE; 2266 ts->stat = SAS_DEV_NO_RESPONSE; 2267 if (!t->uldd_task) { 2268 pm8001_handle_event(pm8001_ha, 2269 pm8001_dev, 2270 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2271 ts->resp = SAS_TASK_UNDELIVERED; 2272 ts->stat = SAS_QUEUE_FULL; 2273 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2274 return; 2275 } 2276 break; 2277 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2278 PM8001_IO_DBG(pm8001_ha, 2279 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2280 ts->resp = SAS_TASK_COMPLETE; 2281 ts->stat = SAS_OPEN_REJECT; 2282 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2283 break; 2284 case IO_XFER_ERROR_NAK_RECEIVED: 2285 PM8001_IO_DBG(pm8001_ha, 2286 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2287 ts->resp = SAS_TASK_COMPLETE; 2288 ts->stat = SAS_NAK_R_ERR; 2289 break; 2290 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2291 PM8001_IO_DBG(pm8001_ha, 2292 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2293 ts->resp = SAS_TASK_COMPLETE; 2294 ts->stat = SAS_NAK_R_ERR; 2295 break; 2296 case IO_XFER_ERROR_DMA: 2297 PM8001_IO_DBG(pm8001_ha, 2298 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2299 ts->resp = SAS_TASK_COMPLETE; 2300 ts->stat = SAS_ABORTED_TASK; 2301 break; 2302 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2303 PM8001_IO_DBG(pm8001_ha, 2304 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2305 ts->resp = SAS_TASK_UNDELIVERED; 2306 ts->stat = SAS_DEV_NO_RESPONSE; 2307 break; 2308 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2309 PM8001_IO_DBG(pm8001_ha, 2310 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2311 ts->resp = SAS_TASK_COMPLETE; 2312 ts->stat = SAS_DATA_UNDERRUN; 2313 break; 2314 case IO_XFER_OPEN_RETRY_TIMEOUT: 2315 PM8001_IO_DBG(pm8001_ha, 2316 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2317 ts->resp = SAS_TASK_COMPLETE; 2318 ts->stat = SAS_OPEN_TO; 2319 break; 2320 case IO_PORT_IN_RESET: 2321 PM8001_IO_DBG(pm8001_ha, 2322 pm8001_printk("IO_PORT_IN_RESET\n")); 2323 ts->resp = SAS_TASK_COMPLETE; 2324 ts->stat = SAS_DEV_NO_RESPONSE; 2325 break; 2326 case IO_DS_NON_OPERATIONAL: 2327 PM8001_IO_DBG(pm8001_ha, 2328 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2329 ts->resp = SAS_TASK_COMPLETE; 2330 ts->stat = SAS_DEV_NO_RESPONSE; 2331 if (!t->uldd_task) { 2332 pm8001_handle_event(pm8001_ha, pm8001_dev, 2333 IO_DS_NON_OPERATIONAL); 2334 ts->resp = SAS_TASK_UNDELIVERED; 2335 ts->stat = SAS_QUEUE_FULL; 2336 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2337 return; 2338 } 2339 break; 2340 case IO_DS_IN_RECOVERY: 2341 PM8001_IO_DBG(pm8001_ha, 2342 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2343 ts->resp = SAS_TASK_COMPLETE; 2344 ts->stat = SAS_DEV_NO_RESPONSE; 2345 break; 2346 case IO_DS_IN_ERROR: 2347 PM8001_IO_DBG(pm8001_ha, 2348 pm8001_printk("IO_DS_IN_ERROR\n")); 2349 ts->resp = SAS_TASK_COMPLETE; 2350 ts->stat = SAS_DEV_NO_RESPONSE; 2351 if (!t->uldd_task) { 2352 pm8001_handle_event(pm8001_ha, pm8001_dev, 2353 IO_DS_IN_ERROR); 2354 ts->resp = SAS_TASK_UNDELIVERED; 2355 ts->stat = SAS_QUEUE_FULL; 2356 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2357 return; 2358 } 2359 break; 2360 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2361 PM8001_IO_DBG(pm8001_ha, 2362 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2363 ts->resp = SAS_TASK_COMPLETE; 2364 ts->stat = SAS_OPEN_REJECT; 2365 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2366 break; 2367 default: 2368 PM8001_IO_DBG(pm8001_ha, 2369 pm8001_printk("Unknown status 0x%x\n", status)); 2370 /* not allowed case. Therefore, return failed status */ 2371 ts->resp = SAS_TASK_COMPLETE; 2372 ts->stat = SAS_DEV_NO_RESPONSE; 2373 break; 2374 } 2375 spin_lock_irqsave(&t->task_state_lock, flags); 2376 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2377 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2378 t->task_state_flags |= SAS_TASK_STATE_DONE; 2379 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2380 spin_unlock_irqrestore(&t->task_state_lock, flags); 2381 PM8001_FAIL_DBG(pm8001_ha, 2382 pm8001_printk("task 0x%p done with io_status 0x%x" 2383 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2384 t, status, ts->resp, ts->stat)); 2385 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2386 } else { 2387 spin_unlock_irqrestore(&t->task_state_lock, flags); 2388 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2389 } 2390 } 2391 2392 /*See the comments for mpi_ssp_completion */ 2393 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2394 { 2395 struct sas_task *t; 2396 struct task_status_struct *ts; 2397 struct pm8001_ccb_info *ccb; 2398 struct pm8001_device *pm8001_dev; 2399 struct sata_event_resp *psataPayload = 2400 (struct sata_event_resp *)(piomb + 4); 2401 u32 event = le32_to_cpu(psataPayload->event); 2402 u32 tag = le32_to_cpu(psataPayload->tag); 2403 u32 port_id = le32_to_cpu(psataPayload->port_id); 2404 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2405 unsigned long flags; 2406 2407 ccb = &pm8001_ha->ccb_info[tag]; 2408 2409 if (ccb) { 2410 t = ccb->task; 2411 pm8001_dev = ccb->device; 2412 } else { 2413 PM8001_FAIL_DBG(pm8001_ha, 2414 pm8001_printk("No CCB !!!. returning\n")); 2415 return; 2416 } 2417 if (event) 2418 PM8001_FAIL_DBG(pm8001_ha, 2419 pm8001_printk("SATA EVENT 0x%x\n", event)); 2420 2421 /* Check if this is NCQ error */ 2422 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2423 /* find device using device id */ 2424 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2425 /* send read log extension */ 2426 if (pm8001_dev) 2427 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2428 return; 2429 } 2430 2431 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2432 PM8001_FAIL_DBG(pm8001_ha, 2433 pm8001_printk("task or dev null\n")); 2434 return; 2435 } 2436 2437 ts = &t->task_status; 2438 PM8001_IO_DBG(pm8001_ha, 2439 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 2440 port_id, tag, event)); 2441 switch (event) { 2442 case IO_OVERFLOW: 2443 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2444 ts->resp = SAS_TASK_COMPLETE; 2445 ts->stat = SAS_DATA_OVERRUN; 2446 ts->residual = 0; 2447 if (pm8001_dev) 2448 pm8001_dev->running_req--; 2449 break; 2450 case IO_XFER_ERROR_BREAK: 2451 PM8001_IO_DBG(pm8001_ha, 2452 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2453 ts->resp = SAS_TASK_COMPLETE; 2454 ts->stat = SAS_INTERRUPTED; 2455 break; 2456 case IO_XFER_ERROR_PHY_NOT_READY: 2457 PM8001_IO_DBG(pm8001_ha, 2458 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2459 ts->resp = SAS_TASK_COMPLETE; 2460 ts->stat = SAS_OPEN_REJECT; 2461 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2462 break; 2463 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2464 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2465 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2466 ts->resp = SAS_TASK_COMPLETE; 2467 ts->stat = SAS_OPEN_REJECT; 2468 ts->open_rej_reason = SAS_OREJ_EPROTO; 2469 break; 2470 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2471 PM8001_IO_DBG(pm8001_ha, 2472 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2473 ts->resp = SAS_TASK_COMPLETE; 2474 ts->stat = SAS_OPEN_REJECT; 2475 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2476 break; 2477 case IO_OPEN_CNX_ERROR_BREAK: 2478 PM8001_IO_DBG(pm8001_ha, 2479 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2480 ts->resp = SAS_TASK_COMPLETE; 2481 ts->stat = SAS_OPEN_REJECT; 2482 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2483 break; 2484 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2485 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2486 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2487 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2488 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2489 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2490 PM8001_FAIL_DBG(pm8001_ha, 2491 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2492 ts->resp = SAS_TASK_UNDELIVERED; 2493 ts->stat = SAS_DEV_NO_RESPONSE; 2494 if (!t->uldd_task) { 2495 pm8001_handle_event(pm8001_ha, 2496 pm8001_dev, 2497 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2498 ts->resp = SAS_TASK_COMPLETE; 2499 ts->stat = SAS_QUEUE_FULL; 2500 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2501 return; 2502 } 2503 break; 2504 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2505 PM8001_IO_DBG(pm8001_ha, 2506 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2507 ts->resp = SAS_TASK_UNDELIVERED; 2508 ts->stat = SAS_OPEN_REJECT; 2509 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2510 break; 2511 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2512 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2513 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2514 ts->resp = SAS_TASK_COMPLETE; 2515 ts->stat = SAS_OPEN_REJECT; 2516 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2517 break; 2518 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2519 PM8001_IO_DBG(pm8001_ha, 2520 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2521 ts->resp = SAS_TASK_COMPLETE; 2522 ts->stat = SAS_OPEN_REJECT; 2523 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2524 break; 2525 case IO_XFER_ERROR_NAK_RECEIVED: 2526 PM8001_IO_DBG(pm8001_ha, 2527 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2528 ts->resp = SAS_TASK_COMPLETE; 2529 ts->stat = SAS_NAK_R_ERR; 2530 break; 2531 case IO_XFER_ERROR_PEER_ABORTED: 2532 PM8001_IO_DBG(pm8001_ha, 2533 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2534 ts->resp = SAS_TASK_COMPLETE; 2535 ts->stat = SAS_NAK_R_ERR; 2536 break; 2537 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2538 PM8001_IO_DBG(pm8001_ha, 2539 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2540 ts->resp = SAS_TASK_COMPLETE; 2541 ts->stat = SAS_DATA_UNDERRUN; 2542 break; 2543 case IO_XFER_OPEN_RETRY_TIMEOUT: 2544 PM8001_IO_DBG(pm8001_ha, 2545 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2546 ts->resp = SAS_TASK_COMPLETE; 2547 ts->stat = SAS_OPEN_TO; 2548 break; 2549 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2550 PM8001_IO_DBG(pm8001_ha, 2551 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2552 ts->resp = SAS_TASK_COMPLETE; 2553 ts->stat = SAS_OPEN_TO; 2554 break; 2555 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2556 PM8001_IO_DBG(pm8001_ha, 2557 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2558 ts->resp = SAS_TASK_COMPLETE; 2559 ts->stat = SAS_OPEN_TO; 2560 break; 2561 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2562 PM8001_IO_DBG(pm8001_ha, 2563 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2564 ts->resp = SAS_TASK_COMPLETE; 2565 ts->stat = SAS_OPEN_TO; 2566 break; 2567 case IO_XFER_ERROR_OFFSET_MISMATCH: 2568 PM8001_IO_DBG(pm8001_ha, 2569 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2570 ts->resp = SAS_TASK_COMPLETE; 2571 ts->stat = SAS_OPEN_TO; 2572 break; 2573 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2574 PM8001_IO_DBG(pm8001_ha, 2575 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2576 ts->resp = SAS_TASK_COMPLETE; 2577 ts->stat = SAS_OPEN_TO; 2578 break; 2579 case IO_XFER_CMD_FRAME_ISSUED: 2580 PM8001_IO_DBG(pm8001_ha, 2581 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2582 break; 2583 case IO_XFER_PIO_SETUP_ERROR: 2584 PM8001_IO_DBG(pm8001_ha, 2585 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2586 ts->resp = SAS_TASK_COMPLETE; 2587 ts->stat = SAS_OPEN_TO; 2588 break; 2589 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2590 PM8001_FAIL_DBG(pm8001_ha, 2591 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 2592 /* TBC: used default set values */ 2593 ts->resp = SAS_TASK_COMPLETE; 2594 ts->stat = SAS_OPEN_TO; 2595 break; 2596 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2597 PM8001_FAIL_DBG(pm8001_ha, 2598 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n")); 2599 /* TBC: used default set values */ 2600 ts->resp = SAS_TASK_COMPLETE; 2601 ts->stat = SAS_OPEN_TO; 2602 break; 2603 default: 2604 PM8001_IO_DBG(pm8001_ha, 2605 pm8001_printk("Unknown status 0x%x\n", event)); 2606 /* not allowed case. Therefore, return failed status */ 2607 ts->resp = SAS_TASK_COMPLETE; 2608 ts->stat = SAS_OPEN_TO; 2609 break; 2610 } 2611 spin_lock_irqsave(&t->task_state_lock, flags); 2612 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2613 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2614 t->task_state_flags |= SAS_TASK_STATE_DONE; 2615 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2616 spin_unlock_irqrestore(&t->task_state_lock, flags); 2617 PM8001_FAIL_DBG(pm8001_ha, 2618 pm8001_printk("task 0x%p done with io_status 0x%x" 2619 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2620 t, event, ts->resp, ts->stat)); 2621 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2622 } else { 2623 spin_unlock_irqrestore(&t->task_state_lock, flags); 2624 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2625 } 2626 } 2627 2628 /*See the comments for mpi_ssp_completion */ 2629 static void 2630 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2631 { 2632 u32 param, i; 2633 struct sas_task *t; 2634 struct pm8001_ccb_info *ccb; 2635 unsigned long flags; 2636 u32 status; 2637 u32 tag; 2638 struct smp_completion_resp *psmpPayload; 2639 struct task_status_struct *ts; 2640 struct pm8001_device *pm8001_dev; 2641 char *pdma_respaddr = NULL; 2642 2643 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2644 status = le32_to_cpu(psmpPayload->status); 2645 tag = le32_to_cpu(psmpPayload->tag); 2646 2647 ccb = &pm8001_ha->ccb_info[tag]; 2648 param = le32_to_cpu(psmpPayload->param); 2649 t = ccb->task; 2650 ts = &t->task_status; 2651 pm8001_dev = ccb->device; 2652 if (status) 2653 PM8001_FAIL_DBG(pm8001_ha, 2654 pm8001_printk("smp IO status 0x%x\n", status)); 2655 if (unlikely(!t || !t->lldd_task || !t->dev)) 2656 return; 2657 2658 switch (status) { 2659 2660 case IO_SUCCESS: 2661 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2662 ts->resp = SAS_TASK_COMPLETE; 2663 ts->stat = SAM_STAT_GOOD; 2664 if (pm8001_dev) 2665 pm8001_dev->running_req--; 2666 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2667 PM8001_IO_DBG(pm8001_ha, 2668 pm8001_printk("DIRECT RESPONSE Length:%d\n", 2669 param)); 2670 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 2671 ((u64)sg_dma_address 2672 (&t->smp_task.smp_resp)))); 2673 for (i = 0; i < param; i++) { 2674 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 2675 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2676 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2677 i, *(pdma_respaddr+i), 2678 psmpPayload->_r_a[i])); 2679 } 2680 } 2681 break; 2682 case IO_ABORTED: 2683 PM8001_IO_DBG(pm8001_ha, 2684 pm8001_printk("IO_ABORTED IOMB\n")); 2685 ts->resp = SAS_TASK_COMPLETE; 2686 ts->stat = SAS_ABORTED_TASK; 2687 if (pm8001_dev) 2688 pm8001_dev->running_req--; 2689 break; 2690 case IO_OVERFLOW: 2691 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2692 ts->resp = SAS_TASK_COMPLETE; 2693 ts->stat = SAS_DATA_OVERRUN; 2694 ts->residual = 0; 2695 if (pm8001_dev) 2696 pm8001_dev->running_req--; 2697 break; 2698 case IO_NO_DEVICE: 2699 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2700 ts->resp = SAS_TASK_COMPLETE; 2701 ts->stat = SAS_PHY_DOWN; 2702 break; 2703 case IO_ERROR_HW_TIMEOUT: 2704 PM8001_IO_DBG(pm8001_ha, 2705 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2706 ts->resp = SAS_TASK_COMPLETE; 2707 ts->stat = SAM_STAT_BUSY; 2708 break; 2709 case IO_XFER_ERROR_BREAK: 2710 PM8001_IO_DBG(pm8001_ha, 2711 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2712 ts->resp = SAS_TASK_COMPLETE; 2713 ts->stat = SAM_STAT_BUSY; 2714 break; 2715 case IO_XFER_ERROR_PHY_NOT_READY: 2716 PM8001_IO_DBG(pm8001_ha, 2717 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2718 ts->resp = SAS_TASK_COMPLETE; 2719 ts->stat = SAM_STAT_BUSY; 2720 break; 2721 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2722 PM8001_IO_DBG(pm8001_ha, 2723 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2724 ts->resp = SAS_TASK_COMPLETE; 2725 ts->stat = SAS_OPEN_REJECT; 2726 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2727 break; 2728 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2729 PM8001_IO_DBG(pm8001_ha, 2730 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2731 ts->resp = SAS_TASK_COMPLETE; 2732 ts->stat = SAS_OPEN_REJECT; 2733 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2734 break; 2735 case IO_OPEN_CNX_ERROR_BREAK: 2736 PM8001_IO_DBG(pm8001_ha, 2737 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2738 ts->resp = SAS_TASK_COMPLETE; 2739 ts->stat = SAS_OPEN_REJECT; 2740 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2741 break; 2742 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2743 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2744 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2745 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2746 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2747 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2748 PM8001_IO_DBG(pm8001_ha, 2749 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2750 ts->resp = SAS_TASK_COMPLETE; 2751 ts->stat = SAS_OPEN_REJECT; 2752 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2753 pm8001_handle_event(pm8001_ha, 2754 pm8001_dev, 2755 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2756 break; 2757 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2758 PM8001_IO_DBG(pm8001_ha, 2759 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2760 ts->resp = SAS_TASK_COMPLETE; 2761 ts->stat = SAS_OPEN_REJECT; 2762 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2763 break; 2764 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2765 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\ 2766 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2767 ts->resp = SAS_TASK_COMPLETE; 2768 ts->stat = SAS_OPEN_REJECT; 2769 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2770 break; 2771 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2772 PM8001_IO_DBG(pm8001_ha, 2773 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2774 ts->resp = SAS_TASK_COMPLETE; 2775 ts->stat = SAS_OPEN_REJECT; 2776 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2777 break; 2778 case IO_XFER_ERROR_RX_FRAME: 2779 PM8001_IO_DBG(pm8001_ha, 2780 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 2781 ts->resp = SAS_TASK_COMPLETE; 2782 ts->stat = SAS_DEV_NO_RESPONSE; 2783 break; 2784 case IO_XFER_OPEN_RETRY_TIMEOUT: 2785 PM8001_IO_DBG(pm8001_ha, 2786 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2787 ts->resp = SAS_TASK_COMPLETE; 2788 ts->stat = SAS_OPEN_REJECT; 2789 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2790 break; 2791 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2792 PM8001_IO_DBG(pm8001_ha, 2793 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 2794 ts->resp = SAS_TASK_COMPLETE; 2795 ts->stat = SAS_QUEUE_FULL; 2796 break; 2797 case IO_PORT_IN_RESET: 2798 PM8001_IO_DBG(pm8001_ha, 2799 pm8001_printk("IO_PORT_IN_RESET\n")); 2800 ts->resp = SAS_TASK_COMPLETE; 2801 ts->stat = SAS_OPEN_REJECT; 2802 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2803 break; 2804 case IO_DS_NON_OPERATIONAL: 2805 PM8001_IO_DBG(pm8001_ha, 2806 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2807 ts->resp = SAS_TASK_COMPLETE; 2808 ts->stat = SAS_DEV_NO_RESPONSE; 2809 break; 2810 case IO_DS_IN_RECOVERY: 2811 PM8001_IO_DBG(pm8001_ha, 2812 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2813 ts->resp = SAS_TASK_COMPLETE; 2814 ts->stat = SAS_OPEN_REJECT; 2815 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2816 break; 2817 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2818 PM8001_IO_DBG(pm8001_ha, 2819 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2820 ts->resp = SAS_TASK_COMPLETE; 2821 ts->stat = SAS_OPEN_REJECT; 2822 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2823 break; 2824 default: 2825 PM8001_IO_DBG(pm8001_ha, 2826 pm8001_printk("Unknown status 0x%x\n", status)); 2827 ts->resp = SAS_TASK_COMPLETE; 2828 ts->stat = SAS_DEV_NO_RESPONSE; 2829 /* not allowed case. Therefore, return failed status */ 2830 break; 2831 } 2832 spin_lock_irqsave(&t->task_state_lock, flags); 2833 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2834 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2835 t->task_state_flags |= SAS_TASK_STATE_DONE; 2836 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2837 spin_unlock_irqrestore(&t->task_state_lock, flags); 2838 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 2839 "task 0x%p done with io_status 0x%x resp 0x%x" 2840 "stat 0x%x but aborted by upper layer!\n", 2841 t, status, ts->resp, ts->stat)); 2842 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2843 } else { 2844 spin_unlock_irqrestore(&t->task_state_lock, flags); 2845 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2846 mb();/* in order to force CPU ordering */ 2847 t->task_done(t); 2848 } 2849 } 2850 2851 /** 2852 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 2853 * @pm8001_ha: our hba card information 2854 * @Qnum: the outbound queue message number. 2855 * @SEA: source of event to ack 2856 * @port_id: port id. 2857 * @phyId: phy id. 2858 * @param0: parameter 0. 2859 * @param1: parameter 1. 2860 */ 2861 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 2862 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 2863 { 2864 struct hw_event_ack_req payload; 2865 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 2866 2867 struct inbound_queue_table *circularQ; 2868 2869 memset((u8 *)&payload, 0, sizeof(payload)); 2870 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 2871 payload.tag = cpu_to_le32(1); 2872 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 2873 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 2874 payload.param0 = cpu_to_le32(param0); 2875 payload.param1 = cpu_to_le32(param1); 2876 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 2877 } 2878 2879 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 2880 u32 phyId, u32 phy_op); 2881 2882 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 2883 void *piomb) 2884 { 2885 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 2886 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2887 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2888 u32 lr_status_evt_portid = 2889 le32_to_cpu(pPayload->lr_status_evt_portid); 2890 u8 deviceType = pPayload->sas_identify.dev_type; 2891 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2892 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2893 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2894 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2895 2896 if (deviceType == SAS_END_DEVICE) { 2897 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 2898 PHY_NOTIFY_ENABLE_SPINUP); 2899 } 2900 2901 port->wide_port_phymap |= (1U << phy_id); 2902 pm8001_get_lrate_mode(phy, link_rate); 2903 phy->sas_phy.oob_mode = SAS_OOB_MODE; 2904 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 2905 phy->phy_attached = 1; 2906 } 2907 2908 /** 2909 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 2910 * @pm8001_ha: our hba card information 2911 * @piomb: IO message buffer 2912 */ 2913 static void 2914 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2915 { 2916 struct hw_event_resp *pPayload = 2917 (struct hw_event_resp *)(piomb + 4); 2918 u32 lr_status_evt_portid = 2919 le32_to_cpu(pPayload->lr_status_evt_portid); 2920 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2921 2922 u8 link_rate = 2923 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2924 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2925 u8 phy_id = 2926 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2927 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2928 2929 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2930 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2931 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2932 unsigned long flags; 2933 u8 deviceType = pPayload->sas_identify.dev_type; 2934 port->port_state = portstate; 2935 port->wide_port_phymap |= (1U << phy_id); 2936 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 2937 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2938 "portid:%d; phyid:%d; linkrate:%d; " 2939 "portstate:%x; devicetype:%x\n", 2940 port_id, phy_id, link_rate, portstate, deviceType)); 2941 2942 switch (deviceType) { 2943 case SAS_PHY_UNUSED: 2944 PM8001_MSG_DBG(pm8001_ha, 2945 pm8001_printk("device type no device.\n")); 2946 break; 2947 case SAS_END_DEVICE: 2948 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 2949 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 2950 PHY_NOTIFY_ENABLE_SPINUP); 2951 port->port_attached = 1; 2952 pm8001_get_lrate_mode(phy, link_rate); 2953 break; 2954 case SAS_EDGE_EXPANDER_DEVICE: 2955 PM8001_MSG_DBG(pm8001_ha, 2956 pm8001_printk("expander device.\n")); 2957 port->port_attached = 1; 2958 pm8001_get_lrate_mode(phy, link_rate); 2959 break; 2960 case SAS_FANOUT_EXPANDER_DEVICE: 2961 PM8001_MSG_DBG(pm8001_ha, 2962 pm8001_printk("fanout expander device.\n")); 2963 port->port_attached = 1; 2964 pm8001_get_lrate_mode(phy, link_rate); 2965 break; 2966 default: 2967 PM8001_MSG_DBG(pm8001_ha, 2968 pm8001_printk("unknown device type(%x)\n", deviceType)); 2969 break; 2970 } 2971 phy->phy_type |= PORT_TYPE_SAS; 2972 phy->identify.device_type = deviceType; 2973 phy->phy_attached = 1; 2974 if (phy->identify.device_type == SAS_END_DEVICE) 2975 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 2976 else if (phy->identify.device_type != SAS_PHY_UNUSED) 2977 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 2978 phy->sas_phy.oob_mode = SAS_OOB_MODE; 2979 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2980 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2981 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 2982 sizeof(struct sas_identify_frame)-4); 2983 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 2984 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2985 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2986 if (pm8001_ha->flags == PM8001F_RUN_TIME) 2987 mdelay(200);/*delay a moment to wait disk to spinup*/ 2988 pm8001_bytes_dmaed(pm8001_ha, phy_id); 2989 } 2990 2991 /** 2992 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 2993 * @pm8001_ha: our hba card information 2994 * @piomb: IO message buffer 2995 */ 2996 static void 2997 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2998 { 2999 struct hw_event_resp *pPayload = 3000 (struct hw_event_resp *)(piomb + 4); 3001 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3002 u32 lr_status_evt_portid = 3003 le32_to_cpu(pPayload->lr_status_evt_portid); 3004 u8 link_rate = 3005 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3006 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3007 u8 phy_id = 3008 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3009 3010 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3011 3012 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3013 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3014 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3015 unsigned long flags; 3016 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3017 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3018 port_id, phy_id, link_rate, portstate)); 3019 3020 port->port_state = portstate; 3021 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3022 port->port_attached = 1; 3023 pm8001_get_lrate_mode(phy, link_rate); 3024 phy->phy_type |= PORT_TYPE_SATA; 3025 phy->phy_attached = 1; 3026 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3027 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3028 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3029 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3030 sizeof(struct dev_to_host_fis)); 3031 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3032 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3033 phy->identify.device_type = SAS_SATA_DEV; 3034 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3035 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3036 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3037 } 3038 3039 /** 3040 * hw_event_phy_down -we should notify the libsas the phy is down. 3041 * @pm8001_ha: our hba card information 3042 * @piomb: IO message buffer 3043 */ 3044 static void 3045 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3046 { 3047 struct hw_event_resp *pPayload = 3048 (struct hw_event_resp *)(piomb + 4); 3049 3050 u32 lr_status_evt_portid = 3051 le32_to_cpu(pPayload->lr_status_evt_portid); 3052 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3053 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3054 u8 phy_id = 3055 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3056 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3057 3058 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3059 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3060 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3061 port->port_state = portstate; 3062 phy->identify.device_type = 0; 3063 phy->phy_attached = 0; 3064 switch (portstate) { 3065 case PORT_VALID: 3066 break; 3067 case PORT_INVALID: 3068 PM8001_MSG_DBG(pm8001_ha, 3069 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3070 PM8001_MSG_DBG(pm8001_ha, 3071 pm8001_printk(" Last phy Down and port invalid\n")); 3072 if (port_sata) { 3073 phy->phy_type = 0; 3074 port->port_attached = 0; 3075 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3076 port_id, phy_id, 0, 0); 3077 } 3078 sas_phy_disconnected(&phy->sas_phy); 3079 break; 3080 case PORT_IN_RESET: 3081 PM8001_MSG_DBG(pm8001_ha, 3082 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3083 break; 3084 case PORT_NOT_ESTABLISHED: 3085 PM8001_MSG_DBG(pm8001_ha, 3086 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n")); 3087 port->port_attached = 0; 3088 break; 3089 case PORT_LOSTCOMM: 3090 PM8001_MSG_DBG(pm8001_ha, 3091 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n")); 3092 PM8001_MSG_DBG(pm8001_ha, 3093 pm8001_printk(" Last phy Down and port invalid\n")); 3094 if (port_sata) { 3095 port->port_attached = 0; 3096 phy->phy_type = 0; 3097 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3098 port_id, phy_id, 0, 0); 3099 } 3100 sas_phy_disconnected(&phy->sas_phy); 3101 break; 3102 default: 3103 port->port_attached = 0; 3104 PM8001_MSG_DBG(pm8001_ha, 3105 pm8001_printk(" Phy Down and(default) = 0x%x\n", 3106 portstate)); 3107 break; 3108 3109 } 3110 if (port_sata && (portstate != PORT_IN_RESET)) { 3111 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3112 3113 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3114 } 3115 } 3116 3117 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3118 { 3119 struct phy_start_resp *pPayload = 3120 (struct phy_start_resp *)(piomb + 4); 3121 u32 status = 3122 le32_to_cpu(pPayload->status); 3123 u32 phy_id = 3124 le32_to_cpu(pPayload->phyid); 3125 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3126 3127 PM8001_INIT_DBG(pm8001_ha, 3128 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n", 3129 status, phy_id)); 3130 if (status == 0) { 3131 phy->phy_state = PHY_LINK_DOWN; 3132 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3133 phy->enable_completion != NULL) 3134 complete(phy->enable_completion); 3135 } 3136 return 0; 3137 3138 } 3139 3140 /** 3141 * mpi_thermal_hw_event -The hw event has come. 3142 * @pm8001_ha: our hba card information 3143 * @piomb: IO message buffer 3144 */ 3145 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3146 { 3147 struct thermal_hw_event *pPayload = 3148 (struct thermal_hw_event *)(piomb + 4); 3149 3150 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3151 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3152 3153 if (thermal_event & 0x40) { 3154 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3155 "Thermal Event: Local high temperature violated!\n")); 3156 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3157 "Thermal Event: Measured local high temperature %d\n", 3158 ((rht_lht & 0xFF00) >> 8))); 3159 } 3160 if (thermal_event & 0x10) { 3161 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3162 "Thermal Event: Remote high temperature violated!\n")); 3163 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3164 "Thermal Event: Measured remote high temperature %d\n", 3165 ((rht_lht & 0xFF000000) >> 24))); 3166 } 3167 return 0; 3168 } 3169 3170 /** 3171 * mpi_hw_event -The hw event has come. 3172 * @pm8001_ha: our hba card information 3173 * @piomb: IO message buffer 3174 */ 3175 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3176 { 3177 unsigned long flags, i; 3178 struct hw_event_resp *pPayload = 3179 (struct hw_event_resp *)(piomb + 4); 3180 u32 lr_status_evt_portid = 3181 le32_to_cpu(pPayload->lr_status_evt_portid); 3182 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3183 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3184 u8 phy_id = 3185 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3186 u16 eventType = 3187 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3188 u8 status = 3189 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3190 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3191 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3192 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3193 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3194 PM8001_MSG_DBG(pm8001_ha, 3195 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n", 3196 port_id, phy_id, eventType, status)); 3197 3198 switch (eventType) { 3199 3200 case HW_EVENT_SAS_PHY_UP: 3201 PM8001_MSG_DBG(pm8001_ha, 3202 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3203 hw_event_sas_phy_up(pm8001_ha, piomb); 3204 break; 3205 case HW_EVENT_SATA_PHY_UP: 3206 PM8001_MSG_DBG(pm8001_ha, 3207 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3208 hw_event_sata_phy_up(pm8001_ha, piomb); 3209 break; 3210 case HW_EVENT_SATA_SPINUP_HOLD: 3211 PM8001_MSG_DBG(pm8001_ha, 3212 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3213 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3214 break; 3215 case HW_EVENT_PHY_DOWN: 3216 PM8001_MSG_DBG(pm8001_ha, 3217 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3218 hw_event_phy_down(pm8001_ha, piomb); 3219 if (pm8001_ha->reset_in_progress) { 3220 PM8001_MSG_DBG(pm8001_ha, 3221 pm8001_printk("Reset in progress\n")); 3222 return 0; 3223 } 3224 phy->phy_attached = 0; 3225 phy->phy_state = PHY_LINK_DISABLE; 3226 break; 3227 case HW_EVENT_PORT_INVALID: 3228 PM8001_MSG_DBG(pm8001_ha, 3229 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3230 sas_phy_disconnected(sas_phy); 3231 phy->phy_attached = 0; 3232 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3233 break; 3234 /* the broadcast change primitive received, tell the LIBSAS this event 3235 to revalidate the sas domain*/ 3236 case HW_EVENT_BROADCAST_CHANGE: 3237 PM8001_MSG_DBG(pm8001_ha, 3238 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3239 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3240 port_id, phy_id, 1, 0); 3241 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3242 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3243 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3244 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3245 break; 3246 case HW_EVENT_PHY_ERROR: 3247 PM8001_MSG_DBG(pm8001_ha, 3248 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3249 sas_phy_disconnected(&phy->sas_phy); 3250 phy->phy_attached = 0; 3251 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3252 break; 3253 case HW_EVENT_BROADCAST_EXP: 3254 PM8001_MSG_DBG(pm8001_ha, 3255 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3256 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3257 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3258 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3259 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3260 break; 3261 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3262 PM8001_MSG_DBG(pm8001_ha, 3263 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3264 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3265 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3266 break; 3267 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3268 PM8001_MSG_DBG(pm8001_ha, 3269 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3270 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3271 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3272 port_id, phy_id, 0, 0); 3273 break; 3274 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3275 PM8001_MSG_DBG(pm8001_ha, 3276 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3277 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3278 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3279 port_id, phy_id, 0, 0); 3280 break; 3281 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3282 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3283 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3284 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3285 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3286 port_id, phy_id, 0, 0); 3287 break; 3288 case HW_EVENT_MALFUNCTION: 3289 PM8001_MSG_DBG(pm8001_ha, 3290 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3291 break; 3292 case HW_EVENT_BROADCAST_SES: 3293 PM8001_MSG_DBG(pm8001_ha, 3294 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3295 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3296 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3297 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3298 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3299 break; 3300 case HW_EVENT_INBOUND_CRC_ERROR: 3301 PM8001_MSG_DBG(pm8001_ha, 3302 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3303 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3304 HW_EVENT_INBOUND_CRC_ERROR, 3305 port_id, phy_id, 0, 0); 3306 break; 3307 case HW_EVENT_HARD_RESET_RECEIVED: 3308 PM8001_MSG_DBG(pm8001_ha, 3309 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3310 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3311 break; 3312 case HW_EVENT_ID_FRAME_TIMEOUT: 3313 PM8001_MSG_DBG(pm8001_ha, 3314 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3315 sas_phy_disconnected(sas_phy); 3316 phy->phy_attached = 0; 3317 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3318 break; 3319 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3320 PM8001_MSG_DBG(pm8001_ha, 3321 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3322 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3323 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3324 port_id, phy_id, 0, 0); 3325 sas_phy_disconnected(sas_phy); 3326 phy->phy_attached = 0; 3327 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3328 break; 3329 case HW_EVENT_PORT_RESET_TIMER_TMO: 3330 PM8001_MSG_DBG(pm8001_ha, 3331 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3332 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3333 port_id, phy_id, 0, 0); 3334 sas_phy_disconnected(sas_phy); 3335 phy->phy_attached = 0; 3336 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3337 if (pm8001_ha->phy[phy_id].reset_completion) { 3338 pm8001_ha->phy[phy_id].port_reset_status = 3339 PORT_RESET_TMO; 3340 complete(pm8001_ha->phy[phy_id].reset_completion); 3341 pm8001_ha->phy[phy_id].reset_completion = NULL; 3342 } 3343 break; 3344 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3345 PM8001_MSG_DBG(pm8001_ha, 3346 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3347 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3348 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3349 port_id, phy_id, 0, 0); 3350 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3351 if (port->wide_port_phymap & (1 << i)) { 3352 phy = &pm8001_ha->phy[i]; 3353 sas_ha->notify_phy_event(&phy->sas_phy, 3354 PHYE_LOSS_OF_SIGNAL); 3355 port->wide_port_phymap &= ~(1 << i); 3356 } 3357 } 3358 break; 3359 case HW_EVENT_PORT_RECOVER: 3360 PM8001_MSG_DBG(pm8001_ha, 3361 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3362 hw_event_port_recover(pm8001_ha, piomb); 3363 break; 3364 case HW_EVENT_PORT_RESET_COMPLETE: 3365 PM8001_MSG_DBG(pm8001_ha, 3366 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3367 if (pm8001_ha->phy[phy_id].reset_completion) { 3368 pm8001_ha->phy[phy_id].port_reset_status = 3369 PORT_RESET_SUCCESS; 3370 complete(pm8001_ha->phy[phy_id].reset_completion); 3371 pm8001_ha->phy[phy_id].reset_completion = NULL; 3372 } 3373 break; 3374 case EVENT_BROADCAST_ASYNCH_EVENT: 3375 PM8001_MSG_DBG(pm8001_ha, 3376 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3377 break; 3378 default: 3379 PM8001_MSG_DBG(pm8001_ha, 3380 pm8001_printk("Unknown event type 0x%x\n", eventType)); 3381 break; 3382 } 3383 return 0; 3384 } 3385 3386 /** 3387 * mpi_phy_stop_resp - SPCv specific 3388 * @pm8001_ha: our hba card information 3389 * @piomb: IO message buffer 3390 */ 3391 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3392 { 3393 struct phy_stop_resp *pPayload = 3394 (struct phy_stop_resp *)(piomb + 4); 3395 u32 status = 3396 le32_to_cpu(pPayload->status); 3397 u32 phyid = 3398 le32_to_cpu(pPayload->phyid) & 0xFF; 3399 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3400 PM8001_MSG_DBG(pm8001_ha, 3401 pm8001_printk("phy:0x%x status:0x%x\n", 3402 phyid, status)); 3403 if (status == PHY_STOP_SUCCESS || 3404 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3405 phy->phy_state = PHY_LINK_DISABLE; 3406 return 0; 3407 } 3408 3409 /** 3410 * mpi_set_controller_config_resp - SPCv specific 3411 * @pm8001_ha: our hba card information 3412 * @piomb: IO message buffer 3413 */ 3414 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3415 void *piomb) 3416 { 3417 struct set_ctrl_cfg_resp *pPayload = 3418 (struct set_ctrl_cfg_resp *)(piomb + 4); 3419 u32 status = le32_to_cpu(pPayload->status); 3420 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3421 3422 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3423 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3424 status, err_qlfr_pgcd)); 3425 3426 return 0; 3427 } 3428 3429 /** 3430 * mpi_get_controller_config_resp - SPCv specific 3431 * @pm8001_ha: our hba card information 3432 * @piomb: IO message buffer 3433 */ 3434 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3435 void *piomb) 3436 { 3437 PM8001_MSG_DBG(pm8001_ha, 3438 pm8001_printk(" pm80xx_addition_functionality\n")); 3439 3440 return 0; 3441 } 3442 3443 /** 3444 * mpi_get_phy_profile_resp - SPCv specific 3445 * @pm8001_ha: our hba card information 3446 * @piomb: IO message buffer 3447 */ 3448 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3449 void *piomb) 3450 { 3451 PM8001_MSG_DBG(pm8001_ha, 3452 pm8001_printk(" pm80xx_addition_functionality\n")); 3453 3454 return 0; 3455 } 3456 3457 /** 3458 * mpi_flash_op_ext_resp - SPCv specific 3459 * @pm8001_ha: our hba card information 3460 * @piomb: IO message buffer 3461 */ 3462 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3463 { 3464 PM8001_MSG_DBG(pm8001_ha, 3465 pm8001_printk(" pm80xx_addition_functionality\n")); 3466 3467 return 0; 3468 } 3469 3470 /** 3471 * mpi_set_phy_profile_resp - SPCv specific 3472 * @pm8001_ha: our hba card information 3473 * @piomb: IO message buffer 3474 */ 3475 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3476 void *piomb) 3477 { 3478 u8 page_code; 3479 struct set_phy_profile_resp *pPayload = 3480 (struct set_phy_profile_resp *)(piomb + 4); 3481 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3482 u32 status = le32_to_cpu(pPayload->status); 3483 3484 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3485 if (status) { 3486 /* status is FAILED */ 3487 PM8001_FAIL_DBG(pm8001_ha, 3488 pm8001_printk("PhyProfile command failed with status " 3489 "0x%08X \n", status)); 3490 return -1; 3491 } else { 3492 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3493 PM8001_FAIL_DBG(pm8001_ha, 3494 pm8001_printk("Invalid page code 0x%X\n", 3495 page_code)); 3496 return -1; 3497 } 3498 } 3499 return 0; 3500 } 3501 3502 /** 3503 * mpi_kek_management_resp - SPCv specific 3504 * @pm8001_ha: our hba card information 3505 * @piomb: IO message buffer 3506 */ 3507 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3508 void *piomb) 3509 { 3510 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3511 3512 u32 status = le32_to_cpu(pPayload->status); 3513 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3514 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3515 3516 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3517 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3518 status, kidx_new_curr_ksop, err_qlfr)); 3519 3520 return 0; 3521 } 3522 3523 /** 3524 * mpi_dek_management_resp - SPCv specific 3525 * @pm8001_ha: our hba card information 3526 * @piomb: IO message buffer 3527 */ 3528 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3529 void *piomb) 3530 { 3531 PM8001_MSG_DBG(pm8001_ha, 3532 pm8001_printk(" pm80xx_addition_functionality\n")); 3533 3534 return 0; 3535 } 3536 3537 /** 3538 * ssp_coalesced_comp_resp - SPCv specific 3539 * @pm8001_ha: our hba card information 3540 * @piomb: IO message buffer 3541 */ 3542 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3543 void *piomb) 3544 { 3545 PM8001_MSG_DBG(pm8001_ha, 3546 pm8001_printk(" pm80xx_addition_functionality\n")); 3547 3548 return 0; 3549 } 3550 3551 /** 3552 * process_one_iomb - process one outbound Queue memory block 3553 * @pm8001_ha: our hba card information 3554 * @piomb: IO message buffer 3555 */ 3556 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3557 { 3558 __le32 pHeader = *(__le32 *)piomb; 3559 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3560 3561 switch (opc) { 3562 case OPC_OUB_ECHO: 3563 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3564 break; 3565 case OPC_OUB_HW_EVENT: 3566 PM8001_MSG_DBG(pm8001_ha, 3567 pm8001_printk("OPC_OUB_HW_EVENT\n")); 3568 mpi_hw_event(pm8001_ha, piomb); 3569 break; 3570 case OPC_OUB_THERM_HW_EVENT: 3571 PM8001_MSG_DBG(pm8001_ha, 3572 pm8001_printk("OPC_OUB_THERMAL_EVENT\n")); 3573 mpi_thermal_hw_event(pm8001_ha, piomb); 3574 break; 3575 case OPC_OUB_SSP_COMP: 3576 PM8001_MSG_DBG(pm8001_ha, 3577 pm8001_printk("OPC_OUB_SSP_COMP\n")); 3578 mpi_ssp_completion(pm8001_ha, piomb); 3579 break; 3580 case OPC_OUB_SMP_COMP: 3581 PM8001_MSG_DBG(pm8001_ha, 3582 pm8001_printk("OPC_OUB_SMP_COMP\n")); 3583 mpi_smp_completion(pm8001_ha, piomb); 3584 break; 3585 case OPC_OUB_LOCAL_PHY_CNTRL: 3586 PM8001_MSG_DBG(pm8001_ha, 3587 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3588 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3589 break; 3590 case OPC_OUB_DEV_REGIST: 3591 PM8001_MSG_DBG(pm8001_ha, 3592 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 3593 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3594 break; 3595 case OPC_OUB_DEREG_DEV: 3596 PM8001_MSG_DBG(pm8001_ha, 3597 pm8001_printk("unregister the device\n")); 3598 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3599 break; 3600 case OPC_OUB_GET_DEV_HANDLE: 3601 PM8001_MSG_DBG(pm8001_ha, 3602 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 3603 break; 3604 case OPC_OUB_SATA_COMP: 3605 PM8001_MSG_DBG(pm8001_ha, 3606 pm8001_printk("OPC_OUB_SATA_COMP\n")); 3607 mpi_sata_completion(pm8001_ha, piomb); 3608 break; 3609 case OPC_OUB_SATA_EVENT: 3610 PM8001_MSG_DBG(pm8001_ha, 3611 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 3612 mpi_sata_event(pm8001_ha, piomb); 3613 break; 3614 case OPC_OUB_SSP_EVENT: 3615 PM8001_MSG_DBG(pm8001_ha, 3616 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3617 mpi_ssp_event(pm8001_ha, piomb); 3618 break; 3619 case OPC_OUB_DEV_HANDLE_ARRIV: 3620 PM8001_MSG_DBG(pm8001_ha, 3621 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3622 /*This is for target*/ 3623 break; 3624 case OPC_OUB_SSP_RECV_EVENT: 3625 PM8001_MSG_DBG(pm8001_ha, 3626 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3627 /*This is for target*/ 3628 break; 3629 case OPC_OUB_FW_FLASH_UPDATE: 3630 PM8001_MSG_DBG(pm8001_ha, 3631 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3632 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3633 break; 3634 case OPC_OUB_GPIO_RESPONSE: 3635 PM8001_MSG_DBG(pm8001_ha, 3636 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3637 break; 3638 case OPC_OUB_GPIO_EVENT: 3639 PM8001_MSG_DBG(pm8001_ha, 3640 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3641 break; 3642 case OPC_OUB_GENERAL_EVENT: 3643 PM8001_MSG_DBG(pm8001_ha, 3644 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3645 pm8001_mpi_general_event(pm8001_ha, piomb); 3646 break; 3647 case OPC_OUB_SSP_ABORT_RSP: 3648 PM8001_MSG_DBG(pm8001_ha, 3649 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3650 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3651 break; 3652 case OPC_OUB_SATA_ABORT_RSP: 3653 PM8001_MSG_DBG(pm8001_ha, 3654 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3655 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3656 break; 3657 case OPC_OUB_SAS_DIAG_MODE_START_END: 3658 PM8001_MSG_DBG(pm8001_ha, 3659 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3660 break; 3661 case OPC_OUB_SAS_DIAG_EXECUTE: 3662 PM8001_MSG_DBG(pm8001_ha, 3663 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3664 break; 3665 case OPC_OUB_GET_TIME_STAMP: 3666 PM8001_MSG_DBG(pm8001_ha, 3667 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3668 break; 3669 case OPC_OUB_SAS_HW_EVENT_ACK: 3670 PM8001_MSG_DBG(pm8001_ha, 3671 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3672 break; 3673 case OPC_OUB_PORT_CONTROL: 3674 PM8001_MSG_DBG(pm8001_ha, 3675 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3676 break; 3677 case OPC_OUB_SMP_ABORT_RSP: 3678 PM8001_MSG_DBG(pm8001_ha, 3679 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3680 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3681 break; 3682 case OPC_OUB_GET_NVMD_DATA: 3683 PM8001_MSG_DBG(pm8001_ha, 3684 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3685 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3686 break; 3687 case OPC_OUB_SET_NVMD_DATA: 3688 PM8001_MSG_DBG(pm8001_ha, 3689 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3690 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3691 break; 3692 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3693 PM8001_MSG_DBG(pm8001_ha, 3694 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3695 break; 3696 case OPC_OUB_SET_DEVICE_STATE: 3697 PM8001_MSG_DBG(pm8001_ha, 3698 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3699 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3700 break; 3701 case OPC_OUB_GET_DEVICE_STATE: 3702 PM8001_MSG_DBG(pm8001_ha, 3703 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3704 break; 3705 case OPC_OUB_SET_DEV_INFO: 3706 PM8001_MSG_DBG(pm8001_ha, 3707 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3708 break; 3709 /* spcv specifc commands */ 3710 case OPC_OUB_PHY_START_RESP: 3711 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3712 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc)); 3713 mpi_phy_start_resp(pm8001_ha, piomb); 3714 break; 3715 case OPC_OUB_PHY_STOP_RESP: 3716 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3717 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc)); 3718 mpi_phy_stop_resp(pm8001_ha, piomb); 3719 break; 3720 case OPC_OUB_SET_CONTROLLER_CONFIG: 3721 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3722 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3723 mpi_set_controller_config_resp(pm8001_ha, piomb); 3724 break; 3725 case OPC_OUB_GET_CONTROLLER_CONFIG: 3726 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3727 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3728 mpi_get_controller_config_resp(pm8001_ha, piomb); 3729 break; 3730 case OPC_OUB_GET_PHY_PROFILE: 3731 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3732 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc)); 3733 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3734 break; 3735 case OPC_OUB_FLASH_OP_EXT: 3736 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3737 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc)); 3738 mpi_flash_op_ext_resp(pm8001_ha, piomb); 3739 break; 3740 case OPC_OUB_SET_PHY_PROFILE: 3741 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3742 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc)); 3743 mpi_set_phy_profile_resp(pm8001_ha, piomb); 3744 break; 3745 case OPC_OUB_KEK_MANAGEMENT_RESP: 3746 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3747 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3748 mpi_kek_management_resp(pm8001_ha, piomb); 3749 break; 3750 case OPC_OUB_DEK_MANAGEMENT_RESP: 3751 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3752 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3753 mpi_dek_management_resp(pm8001_ha, piomb); 3754 break; 3755 case OPC_OUB_SSP_COALESCED_COMP_RESP: 3756 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3757 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc)); 3758 ssp_coalesced_comp_resp(pm8001_ha, piomb); 3759 break; 3760 default: 3761 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3762 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc)); 3763 break; 3764 } 3765 } 3766 3767 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 3768 { 3769 PM8001_FAIL_DBG(pm8001_ha, 3770 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n", 3771 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 3772 PM8001_FAIL_DBG(pm8001_ha, 3773 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n", 3774 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1))); 3775 PM8001_FAIL_DBG(pm8001_ha, 3776 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n", 3777 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2))); 3778 PM8001_FAIL_DBG(pm8001_ha, 3779 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n", 3780 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 3781 PM8001_FAIL_DBG(pm8001_ha, 3782 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 3783 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0))); 3784 PM8001_FAIL_DBG(pm8001_ha, 3785 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 3786 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1))); 3787 PM8001_FAIL_DBG(pm8001_ha, 3788 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 3789 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2))); 3790 PM8001_FAIL_DBG(pm8001_ha, 3791 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 3792 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3))); 3793 PM8001_FAIL_DBG(pm8001_ha, 3794 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 3795 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4))); 3796 PM8001_FAIL_DBG(pm8001_ha, 3797 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 3798 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5))); 3799 PM8001_FAIL_DBG(pm8001_ha, 3800 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 3801 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6))); 3802 PM8001_FAIL_DBG(pm8001_ha, 3803 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 3804 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7))); 3805 } 3806 3807 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 3808 { 3809 struct outbound_queue_table *circularQ; 3810 void *pMsg1 = NULL; 3811 u8 uninitialized_var(bc); 3812 u32 ret = MPI_IO_STATUS_FAIL; 3813 unsigned long flags; 3814 u32 regval; 3815 3816 if (vec == (pm8001_ha->number_of_intr - 1)) { 3817 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 3818 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 3819 SCRATCH_PAD_MIPSALL_READY) { 3820 pm8001_ha->controller_fatal_error = true; 3821 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 3822 "Firmware Fatal error! Regval:0x%x\n", regval)); 3823 print_scratchpad_registers(pm8001_ha); 3824 return ret; 3825 } 3826 } 3827 spin_lock_irqsave(&pm8001_ha->lock, flags); 3828 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 3829 do { 3830 /* spurious interrupt during setup if kexec-ing and 3831 * driver doing a doorbell access w/ the pre-kexec oq 3832 * interrupt setup. 3833 */ 3834 if (!circularQ->pi_virt) 3835 break; 3836 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3837 if (MPI_IO_STATUS_SUCCESS == ret) { 3838 /* process the outbound message */ 3839 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3840 /* free the message from the outbound circular buffer */ 3841 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 3842 circularQ, bc); 3843 } 3844 if (MPI_IO_STATUS_BUSY == ret) { 3845 /* Update the producer index from SPC */ 3846 circularQ->producer_index = 3847 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3848 if (le32_to_cpu(circularQ->producer_index) == 3849 circularQ->consumer_idx) 3850 /* OQ is empty */ 3851 break; 3852 } 3853 } while (1); 3854 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3855 return ret; 3856 } 3857 3858 /* DMA_... to our direction translation. */ 3859 static const u8 data_dir_flags[] = { 3860 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 3861 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 3862 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 3863 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 3864 }; 3865 3866 static void build_smp_cmd(u32 deviceID, __le32 hTag, 3867 struct smp_req *psmp_cmd, int mode, int length) 3868 { 3869 psmp_cmd->tag = hTag; 3870 psmp_cmd->device_id = cpu_to_le32(deviceID); 3871 if (mode == SMP_DIRECT) { 3872 length = length - 4; /* subtract crc */ 3873 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 3874 } else { 3875 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3876 } 3877 } 3878 3879 /** 3880 * pm8001_chip_smp_req - send a SMP task to FW 3881 * @pm8001_ha: our hba card information. 3882 * @ccb: the ccb information this request used. 3883 */ 3884 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3885 struct pm8001_ccb_info *ccb) 3886 { 3887 int elem, rc; 3888 struct sas_task *task = ccb->task; 3889 struct domain_device *dev = task->dev; 3890 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3891 struct scatterlist *sg_req, *sg_resp; 3892 u32 req_len, resp_len; 3893 struct smp_req smp_cmd; 3894 u32 opc; 3895 struct inbound_queue_table *circularQ; 3896 char *preq_dma_addr = NULL; 3897 __le64 tmp_addr; 3898 u32 i, length; 3899 3900 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3901 /* 3902 * DMA-map SMP request, response buffers 3903 */ 3904 sg_req = &task->smp_task.smp_req; 3905 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 3906 if (!elem) 3907 return -ENOMEM; 3908 req_len = sg_dma_len(sg_req); 3909 3910 sg_resp = &task->smp_task.smp_resp; 3911 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 3912 if (!elem) { 3913 rc = -ENOMEM; 3914 goto err_out; 3915 } 3916 resp_len = sg_dma_len(sg_resp); 3917 /* must be in dwords */ 3918 if ((req_len & 0x3) || (resp_len & 0x3)) { 3919 rc = -EINVAL; 3920 goto err_out_2; 3921 } 3922 3923 opc = OPC_INB_SMP_REQUEST; 3924 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3925 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3926 3927 length = sg_req->length; 3928 PM8001_IO_DBG(pm8001_ha, 3929 pm8001_printk("SMP Frame Length %d\n", sg_req->length)); 3930 if (!(length - 8)) 3931 pm8001_ha->smp_exp_mode = SMP_DIRECT; 3932 else 3933 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 3934 3935 3936 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3937 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 3938 3939 /* INDIRECT MODE command settings. Use DMA */ 3940 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 3941 PM8001_IO_DBG(pm8001_ha, 3942 pm8001_printk("SMP REQUEST INDIRECT MODE\n")); 3943 /* for SPCv indirect mode. Place the top 4 bytes of 3944 * SMP Request header here. */ 3945 for (i = 0; i < 4; i++) 3946 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 3947 /* exclude top 4 bytes for SMP req header */ 3948 smp_cmd.long_smp_req.long_req_addr = 3949 cpu_to_le64((u64)sg_dma_address 3950 (&task->smp_task.smp_req) + 4); 3951 /* exclude 4 bytes for SMP req header and CRC */ 3952 smp_cmd.long_smp_req.long_req_size = 3953 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 3954 smp_cmd.long_smp_req.long_resp_addr = 3955 cpu_to_le64((u64)sg_dma_address 3956 (&task->smp_task.smp_resp)); 3957 smp_cmd.long_smp_req.long_resp_size = 3958 cpu_to_le32((u32)sg_dma_len 3959 (&task->smp_task.smp_resp)-4); 3960 } else { /* DIRECT MODE */ 3961 smp_cmd.long_smp_req.long_req_addr = 3962 cpu_to_le64((u64)sg_dma_address 3963 (&task->smp_task.smp_req)); 3964 smp_cmd.long_smp_req.long_req_size = 3965 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3966 smp_cmd.long_smp_req.long_resp_addr = 3967 cpu_to_le64((u64)sg_dma_address 3968 (&task->smp_task.smp_resp)); 3969 smp_cmd.long_smp_req.long_resp_size = 3970 cpu_to_le32 3971 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3972 } 3973 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3974 PM8001_IO_DBG(pm8001_ha, 3975 pm8001_printk("SMP REQUEST DIRECT MODE\n")); 3976 for (i = 0; i < length; i++) 3977 if (i < 16) { 3978 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 3979 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3980 "Byte[%d]:%x (DMA data:%x)\n", 3981 i, smp_cmd.smp_req16[i], 3982 *(preq_dma_addr))); 3983 } else { 3984 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 3985 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3986 "Byte[%d]:%x (DMA data:%x)\n", 3987 i, smp_cmd.smp_req[i], 3988 *(preq_dma_addr))); 3989 } 3990 } 3991 3992 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 3993 &smp_cmd, pm8001_ha->smp_exp_mode, length); 3994 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 3995 (u32 *)&smp_cmd, 0); 3996 if (rc) 3997 goto err_out_2; 3998 return 0; 3999 4000 err_out_2: 4001 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4002 DMA_FROM_DEVICE); 4003 err_out: 4004 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4005 DMA_TO_DEVICE); 4006 return rc; 4007 } 4008 4009 static int check_enc_sas_cmd(struct sas_task *task) 4010 { 4011 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4012 4013 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4014 return 1; 4015 else 4016 return 0; 4017 } 4018 4019 static int check_enc_sat_cmd(struct sas_task *task) 4020 { 4021 int ret = 0; 4022 switch (task->ata_task.fis.command) { 4023 case ATA_CMD_FPDMA_READ: 4024 case ATA_CMD_READ_EXT: 4025 case ATA_CMD_READ: 4026 case ATA_CMD_FPDMA_WRITE: 4027 case ATA_CMD_WRITE_EXT: 4028 case ATA_CMD_WRITE: 4029 case ATA_CMD_PIO_READ: 4030 case ATA_CMD_PIO_READ_EXT: 4031 case ATA_CMD_PIO_WRITE: 4032 case ATA_CMD_PIO_WRITE_EXT: 4033 ret = 1; 4034 break; 4035 default: 4036 ret = 0; 4037 break; 4038 } 4039 return ret; 4040 } 4041 4042 /** 4043 * pm80xx_chip_ssp_io_req - send a SSP task to FW 4044 * @pm8001_ha: our hba card information. 4045 * @ccb: the ccb information this request used. 4046 */ 4047 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4048 struct pm8001_ccb_info *ccb) 4049 { 4050 struct sas_task *task = ccb->task; 4051 struct domain_device *dev = task->dev; 4052 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4053 struct ssp_ini_io_start_req ssp_cmd; 4054 u32 tag = ccb->ccb_tag; 4055 int ret; 4056 u64 phys_addr, start_addr, end_addr; 4057 u32 end_addr_high, end_addr_low; 4058 struct inbound_queue_table *circularQ; 4059 u32 q_index; 4060 u32 opc = OPC_INB_SSPINIIOSTART; 4061 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4062 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4063 /* data address domain added for spcv; set to 0 by host, 4064 * used internally by controller 4065 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4066 */ 4067 ssp_cmd.dad_dir_m_tlr = 4068 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4069 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4070 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4071 ssp_cmd.tag = cpu_to_le32(tag); 4072 if (task->ssp_task.enable_first_burst) 4073 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4074 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4075 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4076 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4077 task->ssp_task.cmd->cmd_len); 4078 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 4079 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4080 4081 /* Check if encryption is set */ 4082 if (pm8001_ha->chip->encrypt && 4083 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4084 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4085 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4086 task->ssp_task.cmd->cmnd[0])); 4087 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4088 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4089 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4090 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4091 4092 /* fill in PRD (scatter/gather) table, if any */ 4093 if (task->num_scatter > 1) { 4094 pm8001_chip_make_sg(task->scatter, 4095 ccb->n_elem, ccb->buf_prd); 4096 phys_addr = ccb->ccb_dma_handle + 4097 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4098 ssp_cmd.enc_addr_low = 4099 cpu_to_le32(lower_32_bits(phys_addr)); 4100 ssp_cmd.enc_addr_high = 4101 cpu_to_le32(upper_32_bits(phys_addr)); 4102 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4103 } else if (task->num_scatter == 1) { 4104 u64 dma_addr = sg_dma_address(task->scatter); 4105 ssp_cmd.enc_addr_low = 4106 cpu_to_le32(lower_32_bits(dma_addr)); 4107 ssp_cmd.enc_addr_high = 4108 cpu_to_le32(upper_32_bits(dma_addr)); 4109 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4110 ssp_cmd.enc_esgl = 0; 4111 /* Check 4G Boundary */ 4112 start_addr = cpu_to_le64(dma_addr); 4113 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4114 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4115 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4116 if (end_addr_high != ssp_cmd.enc_addr_high) { 4117 PM8001_FAIL_DBG(pm8001_ha, 4118 pm8001_printk("The sg list address " 4119 "start_addr=0x%016llx data_len=0x%x " 4120 "end_addr_high=0x%08x end_addr_low=" 4121 "0x%08x has crossed 4G boundary\n", 4122 start_addr, ssp_cmd.enc_len, 4123 end_addr_high, end_addr_low)); 4124 pm8001_chip_make_sg(task->scatter, 1, 4125 ccb->buf_prd); 4126 phys_addr = ccb->ccb_dma_handle + 4127 offsetof(struct pm8001_ccb_info, 4128 buf_prd[0]); 4129 ssp_cmd.enc_addr_low = 4130 cpu_to_le32(lower_32_bits(phys_addr)); 4131 ssp_cmd.enc_addr_high = 4132 cpu_to_le32(upper_32_bits(phys_addr)); 4133 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4134 } 4135 } else if (task->num_scatter == 0) { 4136 ssp_cmd.enc_addr_low = 0; 4137 ssp_cmd.enc_addr_high = 0; 4138 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4139 ssp_cmd.enc_esgl = 0; 4140 } 4141 /* XTS mode. All other fields are 0 */ 4142 ssp_cmd.key_cmode = 0x6 << 4; 4143 /* set tweak values. Should be the start lba */ 4144 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4145 (task->ssp_task.cmd->cmnd[3] << 16) | 4146 (task->ssp_task.cmd->cmnd[4] << 8) | 4147 (task->ssp_task.cmd->cmnd[5])); 4148 } else { 4149 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4150 "Sending Normal SAS command 0x%x inb q %x\n", 4151 task->ssp_task.cmd->cmnd[0], q_index)); 4152 /* fill in PRD (scatter/gather) table, if any */ 4153 if (task->num_scatter > 1) { 4154 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4155 ccb->buf_prd); 4156 phys_addr = ccb->ccb_dma_handle + 4157 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4158 ssp_cmd.addr_low = 4159 cpu_to_le32(lower_32_bits(phys_addr)); 4160 ssp_cmd.addr_high = 4161 cpu_to_le32(upper_32_bits(phys_addr)); 4162 ssp_cmd.esgl = cpu_to_le32(1<<31); 4163 } else if (task->num_scatter == 1) { 4164 u64 dma_addr = sg_dma_address(task->scatter); 4165 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4166 ssp_cmd.addr_high = 4167 cpu_to_le32(upper_32_bits(dma_addr)); 4168 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4169 ssp_cmd.esgl = 0; 4170 /* Check 4G Boundary */ 4171 start_addr = cpu_to_le64(dma_addr); 4172 end_addr = (start_addr + ssp_cmd.len) - 1; 4173 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4174 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4175 if (end_addr_high != ssp_cmd.addr_high) { 4176 PM8001_FAIL_DBG(pm8001_ha, 4177 pm8001_printk("The sg list address " 4178 "start_addr=0x%016llx data_len=0x%x " 4179 "end_addr_high=0x%08x end_addr_low=" 4180 "0x%08x has crossed 4G boundary\n", 4181 start_addr, ssp_cmd.len, 4182 end_addr_high, end_addr_low)); 4183 pm8001_chip_make_sg(task->scatter, 1, 4184 ccb->buf_prd); 4185 phys_addr = ccb->ccb_dma_handle + 4186 offsetof(struct pm8001_ccb_info, 4187 buf_prd[0]); 4188 ssp_cmd.addr_low = 4189 cpu_to_le32(lower_32_bits(phys_addr)); 4190 ssp_cmd.addr_high = 4191 cpu_to_le32(upper_32_bits(phys_addr)); 4192 ssp_cmd.esgl = cpu_to_le32(1<<31); 4193 } 4194 } else if (task->num_scatter == 0) { 4195 ssp_cmd.addr_low = 0; 4196 ssp_cmd.addr_high = 0; 4197 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4198 ssp_cmd.esgl = 0; 4199 } 4200 } 4201 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4202 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4203 &ssp_cmd, q_index); 4204 return ret; 4205 } 4206 4207 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4208 struct pm8001_ccb_info *ccb) 4209 { 4210 struct sas_task *task = ccb->task; 4211 struct domain_device *dev = task->dev; 4212 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4213 u32 tag = ccb->ccb_tag; 4214 int ret; 4215 u32 q_index; 4216 struct sata_start_req sata_cmd; 4217 u32 hdr_tag, ncg_tag = 0; 4218 u64 phys_addr, start_addr, end_addr; 4219 u32 end_addr_high, end_addr_low; 4220 u32 ATAP = 0x0; 4221 u32 dir; 4222 struct inbound_queue_table *circularQ; 4223 unsigned long flags; 4224 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4225 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4226 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 4227 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4228 4229 if (task->data_dir == DMA_NONE) { 4230 ATAP = 0x04; /* no data*/ 4231 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4232 } else if (likely(!task->ata_task.device_control_reg_update)) { 4233 if (task->ata_task.dma_xfer) { 4234 ATAP = 0x06; /* DMA */ 4235 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4236 } else { 4237 ATAP = 0x05; /* PIO*/ 4238 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4239 } 4240 if (task->ata_task.use_ncq && 4241 dev->sata_dev.class != ATA_DEV_ATAPI) { 4242 ATAP = 0x07; /* FPDMA */ 4243 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4244 } 4245 } 4246 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4247 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4248 ncg_tag = hdr_tag; 4249 } 4250 dir = data_dir_flags[task->data_dir] << 8; 4251 sata_cmd.tag = cpu_to_le32(tag); 4252 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4253 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4254 4255 sata_cmd.sata_fis = task->ata_task.fis; 4256 if (likely(!task->ata_task.device_control_reg_update)) 4257 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4258 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4259 4260 /* Check if encryption is set */ 4261 if (pm8001_ha->chip->encrypt && 4262 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4263 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4264 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4265 sata_cmd.sata_fis.command)); 4266 opc = OPC_INB_SATA_DIF_ENC_IO; 4267 4268 /* set encryption bit */ 4269 sata_cmd.ncqtag_atap_dir_m_dad = 4270 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4271 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4272 /* dad (bit 0-1) is 0 */ 4273 /* fill in PRD (scatter/gather) table, if any */ 4274 if (task->num_scatter > 1) { 4275 pm8001_chip_make_sg(task->scatter, 4276 ccb->n_elem, ccb->buf_prd); 4277 phys_addr = ccb->ccb_dma_handle + 4278 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4279 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4280 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4281 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4282 } else if (task->num_scatter == 1) { 4283 u64 dma_addr = sg_dma_address(task->scatter); 4284 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4285 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4286 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4287 sata_cmd.enc_esgl = 0; 4288 /* Check 4G Boundary */ 4289 start_addr = cpu_to_le64(dma_addr); 4290 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4291 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4292 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4293 if (end_addr_high != sata_cmd.enc_addr_high) { 4294 PM8001_FAIL_DBG(pm8001_ha, 4295 pm8001_printk("The sg list address " 4296 "start_addr=0x%016llx data_len=0x%x " 4297 "end_addr_high=0x%08x end_addr_low" 4298 "=0x%08x has crossed 4G boundary\n", 4299 start_addr, sata_cmd.enc_len, 4300 end_addr_high, end_addr_low)); 4301 pm8001_chip_make_sg(task->scatter, 1, 4302 ccb->buf_prd); 4303 phys_addr = ccb->ccb_dma_handle + 4304 offsetof(struct pm8001_ccb_info, 4305 buf_prd[0]); 4306 sata_cmd.enc_addr_low = 4307 lower_32_bits(phys_addr); 4308 sata_cmd.enc_addr_high = 4309 upper_32_bits(phys_addr); 4310 sata_cmd.enc_esgl = 4311 cpu_to_le32(1 << 31); 4312 } 4313 } else if (task->num_scatter == 0) { 4314 sata_cmd.enc_addr_low = 0; 4315 sata_cmd.enc_addr_high = 0; 4316 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4317 sata_cmd.enc_esgl = 0; 4318 } 4319 /* XTS mode. All other fields are 0 */ 4320 sata_cmd.key_index_mode = 0x6 << 4; 4321 /* set tweak values. Should be the start lba */ 4322 sata_cmd.twk_val0 = 4323 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4324 (sata_cmd.sata_fis.lbah << 16) | 4325 (sata_cmd.sata_fis.lbam << 8) | 4326 (sata_cmd.sata_fis.lbal)); 4327 sata_cmd.twk_val1 = 4328 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4329 (sata_cmd.sata_fis.lbam_exp)); 4330 } else { 4331 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4332 "Sending Normal SATA command 0x%x inb %x\n", 4333 sata_cmd.sata_fis.command, q_index)); 4334 /* dad (bit 0-1) is 0 */ 4335 sata_cmd.ncqtag_atap_dir_m_dad = 4336 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4337 ((ATAP & 0x3f) << 10) | dir); 4338 4339 /* fill in PRD (scatter/gather) table, if any */ 4340 if (task->num_scatter > 1) { 4341 pm8001_chip_make_sg(task->scatter, 4342 ccb->n_elem, ccb->buf_prd); 4343 phys_addr = ccb->ccb_dma_handle + 4344 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4345 sata_cmd.addr_low = lower_32_bits(phys_addr); 4346 sata_cmd.addr_high = upper_32_bits(phys_addr); 4347 sata_cmd.esgl = cpu_to_le32(1 << 31); 4348 } else if (task->num_scatter == 1) { 4349 u64 dma_addr = sg_dma_address(task->scatter); 4350 sata_cmd.addr_low = lower_32_bits(dma_addr); 4351 sata_cmd.addr_high = upper_32_bits(dma_addr); 4352 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4353 sata_cmd.esgl = 0; 4354 /* Check 4G Boundary */ 4355 start_addr = cpu_to_le64(dma_addr); 4356 end_addr = (start_addr + sata_cmd.len) - 1; 4357 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4358 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4359 if (end_addr_high != sata_cmd.addr_high) { 4360 PM8001_FAIL_DBG(pm8001_ha, 4361 pm8001_printk("The sg list address " 4362 "start_addr=0x%016llx data_len=0x%x" 4363 "end_addr_high=0x%08x end_addr_low=" 4364 "0x%08x has crossed 4G boundary\n", 4365 start_addr, sata_cmd.len, 4366 end_addr_high, end_addr_low)); 4367 pm8001_chip_make_sg(task->scatter, 1, 4368 ccb->buf_prd); 4369 phys_addr = ccb->ccb_dma_handle + 4370 offsetof(struct pm8001_ccb_info, 4371 buf_prd[0]); 4372 sata_cmd.addr_low = 4373 lower_32_bits(phys_addr); 4374 sata_cmd.addr_high = 4375 upper_32_bits(phys_addr); 4376 sata_cmd.esgl = cpu_to_le32(1 << 31); 4377 } 4378 } else if (task->num_scatter == 0) { 4379 sata_cmd.addr_low = 0; 4380 sata_cmd.addr_high = 0; 4381 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4382 sata_cmd.esgl = 0; 4383 } 4384 /* scsi cdb */ 4385 sata_cmd.atapi_scsi_cdb[0] = 4386 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4387 (task->ata_task.atapi_packet[1] << 8) | 4388 (task->ata_task.atapi_packet[2] << 16) | 4389 (task->ata_task.atapi_packet[3] << 24))); 4390 sata_cmd.atapi_scsi_cdb[1] = 4391 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4392 (task->ata_task.atapi_packet[5] << 8) | 4393 (task->ata_task.atapi_packet[6] << 16) | 4394 (task->ata_task.atapi_packet[7] << 24))); 4395 sata_cmd.atapi_scsi_cdb[2] = 4396 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4397 (task->ata_task.atapi_packet[9] << 8) | 4398 (task->ata_task.atapi_packet[10] << 16) | 4399 (task->ata_task.atapi_packet[11] << 24))); 4400 sata_cmd.atapi_scsi_cdb[3] = 4401 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4402 (task->ata_task.atapi_packet[13] << 8) | 4403 (task->ata_task.atapi_packet[14] << 16) | 4404 (task->ata_task.atapi_packet[15] << 24))); 4405 } 4406 4407 /* Check for read log for failed drive and return */ 4408 if (sata_cmd.sata_fis.command == 0x2f) { 4409 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4410 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4411 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4412 struct task_status_struct *ts; 4413 4414 pm8001_ha_dev->id &= 0xDFFFFFFF; 4415 ts = &task->task_status; 4416 4417 spin_lock_irqsave(&task->task_state_lock, flags); 4418 ts->resp = SAS_TASK_COMPLETE; 4419 ts->stat = SAM_STAT_GOOD; 4420 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4421 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4422 task->task_state_flags |= SAS_TASK_STATE_DONE; 4423 if (unlikely((task->task_state_flags & 4424 SAS_TASK_STATE_ABORTED))) { 4425 spin_unlock_irqrestore(&task->task_state_lock, 4426 flags); 4427 PM8001_FAIL_DBG(pm8001_ha, 4428 pm8001_printk("task 0x%p resp 0x%x " 4429 " stat 0x%x but aborted by upper layer " 4430 "\n", task, ts->resp, ts->stat)); 4431 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4432 return 0; 4433 } else { 4434 spin_unlock_irqrestore(&task->task_state_lock, 4435 flags); 4436 pm8001_ccb_task_free_done(pm8001_ha, task, 4437 ccb, tag); 4438 return 0; 4439 } 4440 } 4441 } 4442 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4443 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4444 &sata_cmd, q_index); 4445 return ret; 4446 } 4447 4448 /** 4449 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4450 * @pm8001_ha: our hba card information. 4451 * @num: the inbound queue number 4452 * @phy_id: the phy id which we wanted to start up. 4453 */ 4454 static int 4455 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4456 { 4457 struct phy_start_req payload; 4458 struct inbound_queue_table *circularQ; 4459 int ret; 4460 u32 tag = 0x01; 4461 u32 opcode = OPC_INB_PHYSTART; 4462 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4463 memset(&payload, 0, sizeof(payload)); 4464 payload.tag = cpu_to_le32(tag); 4465 4466 PM8001_INIT_DBG(pm8001_ha, 4467 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id)); 4468 /* 4469 ** [0:7] PHY Identifier 4470 ** [8:11] link rate 1.5G, 3G, 6G 4471 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode 4472 ** [14] 0b disable spin up hold; 1b enable spin up hold 4473 ** [15] ob no change in current PHY analig setup 1b enable using SPAST 4474 */ 4475 if (!IS_SPCV_12G(pm8001_ha->pdev)) 4476 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4477 LINKMODE_AUTO | LINKRATE_15 | 4478 LINKRATE_30 | LINKRATE_60 | phy_id); 4479 else 4480 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4481 LINKMODE_AUTO | LINKRATE_15 | 4482 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 | 4483 phy_id); 4484 4485 /* SSC Disable and SAS Analog ST configuration */ 4486 /** 4487 payload.ase_sh_lm_slr_phyid = 4488 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4489 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4490 phy_id); 4491 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4492 **/ 4493 4494 payload.sas_identify.dev_type = SAS_END_DEVICE; 4495 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4496 memcpy(payload.sas_identify.sas_addr, 4497 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE); 4498 payload.sas_identify.phy_id = phy_id; 4499 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4500 return ret; 4501 } 4502 4503 /** 4504 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4505 * @pm8001_ha: our hba card information. 4506 * @num: the inbound queue number 4507 * @phy_id: the phy id which we wanted to start up. 4508 */ 4509 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4510 u8 phy_id) 4511 { 4512 struct phy_stop_req payload; 4513 struct inbound_queue_table *circularQ; 4514 int ret; 4515 u32 tag = 0x01; 4516 u32 opcode = OPC_INB_PHYSTOP; 4517 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4518 memset(&payload, 0, sizeof(payload)); 4519 payload.tag = cpu_to_le32(tag); 4520 payload.phy_id = cpu_to_le32(phy_id); 4521 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4522 return ret; 4523 } 4524 4525 /** 4526 * see comments on pm8001_mpi_reg_resp. 4527 */ 4528 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4529 struct pm8001_device *pm8001_dev, u32 flag) 4530 { 4531 struct reg_dev_req payload; 4532 u32 opc; 4533 u32 stp_sspsmp_sata = 0x4; 4534 struct inbound_queue_table *circularQ; 4535 u32 linkrate, phy_id; 4536 int rc, tag = 0xdeadbeef; 4537 struct pm8001_ccb_info *ccb; 4538 u8 retryFlag = 0x1; 4539 u16 firstBurstSize = 0; 4540 u16 ITNT = 2000; 4541 struct domain_device *dev = pm8001_dev->sas_device; 4542 struct domain_device *parent_dev = dev->parent; 4543 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4544 4545 memset(&payload, 0, sizeof(payload)); 4546 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4547 if (rc) 4548 return rc; 4549 ccb = &pm8001_ha->ccb_info[tag]; 4550 ccb->device = pm8001_dev; 4551 ccb->ccb_tag = tag; 4552 payload.tag = cpu_to_le32(tag); 4553 4554 if (flag == 1) { 4555 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4556 } else { 4557 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4558 stp_sspsmp_sata = 0x00; /* stp*/ 4559 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4560 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4561 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4562 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4563 } 4564 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4565 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4566 else 4567 phy_id = pm8001_dev->attached_phy; 4568 4569 opc = OPC_INB_REG_DEV; 4570 4571 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4572 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4573 4574 payload.phyid_portid = 4575 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4576 ((phy_id & 0xFF) << 8)); 4577 4578 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4579 ((linkrate & 0x0F) << 24) | 4580 ((stp_sspsmp_sata & 0x03) << 28)); 4581 payload.firstburstsize_ITNexustimeout = 4582 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4583 4584 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4585 SAS_ADDR_SIZE); 4586 4587 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4588 if (rc) 4589 pm8001_tag_free(pm8001_ha, tag); 4590 4591 return rc; 4592 } 4593 4594 /** 4595 * pm80xx_chip_phy_ctl_req - support the local phy operation 4596 * @pm8001_ha: our hba card information. 4597 * @num: the inbound queue number 4598 * @phy_id: the phy id which we wanted to operate 4599 * @phy_op: 4600 */ 4601 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4602 u32 phyId, u32 phy_op) 4603 { 4604 u32 tag; 4605 int rc; 4606 struct local_phy_ctl_req payload; 4607 struct inbound_queue_table *circularQ; 4608 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4609 memset(&payload, 0, sizeof(payload)); 4610 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4611 if (rc) 4612 return rc; 4613 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4614 payload.tag = cpu_to_le32(tag); 4615 payload.phyop_phyid = 4616 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4617 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4618 } 4619 4620 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4621 { 4622 #ifdef PM8001_USE_MSIX 4623 return 1; 4624 #else 4625 u32 value; 4626 4627 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4628 if (value) 4629 return 1; 4630 return 0; 4631 #endif 4632 } 4633 4634 /** 4635 * pm8001_chip_isr - PM8001 isr handler. 4636 * @pm8001_ha: our hba card information. 4637 * @irq: irq number. 4638 * @stat: stat. 4639 */ 4640 static irqreturn_t 4641 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4642 { 4643 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4644 process_oq(pm8001_ha, vec); 4645 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4646 return IRQ_HANDLED; 4647 } 4648 4649 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4650 u32 operation, u32 phyid, u32 length, u32 *buf) 4651 { 4652 u32 tag , i, j = 0; 4653 int rc; 4654 struct set_phy_profile_req payload; 4655 struct inbound_queue_table *circularQ; 4656 u32 opc = OPC_INB_SET_PHY_PROFILE; 4657 4658 memset(&payload, 0, sizeof(payload)); 4659 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4660 if (rc) 4661 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n")); 4662 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4663 payload.tag = cpu_to_le32(tag); 4664 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4665 PM8001_INIT_DBG(pm8001_ha, 4666 pm8001_printk(" phy profile command for phy %x ,length is %d\n", 4667 payload.ppc_phyid, length)); 4668 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4669 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4670 j++; 4671 } 4672 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4673 if (rc) 4674 pm8001_tag_free(pm8001_ha, tag); 4675 } 4676 4677 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4678 u32 length, u8 *buf) 4679 { 4680 u32 i; 4681 4682 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4683 mpi_set_phy_profile_req(pm8001_ha, 4684 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4685 length = length + PHY_DWORD_LENGTH; 4686 } 4687 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n")); 4688 } 4689 4690 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4691 u32 phy, u32 length, u32 *buf) 4692 { 4693 u32 tag, opc; 4694 int rc, i; 4695 struct set_phy_profile_req payload; 4696 struct inbound_queue_table *circularQ; 4697 4698 memset(&payload, 0, sizeof(payload)); 4699 4700 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4701 if (rc) 4702 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag")); 4703 4704 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4705 opc = OPC_INB_SET_PHY_PROFILE; 4706 4707 payload.tag = cpu_to_le32(tag); 4708 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4709 | (phy & 0xFF)); 4710 4711 for (i = 0; i < length; i++) 4712 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4713 4714 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4715 if (rc) 4716 pm8001_tag_free(pm8001_ha, tag); 4717 4718 PM8001_INIT_DBG(pm8001_ha, 4719 pm8001_printk("PHY %d settings applied", phy)); 4720 } 4721 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4722 .name = "pmc80xx", 4723 .chip_init = pm80xx_chip_init, 4724 .chip_soft_rst = pm80xx_chip_soft_rst, 4725 .chip_rst = pm80xx_hw_chip_rst, 4726 .chip_iounmap = pm8001_chip_iounmap, 4727 .isr = pm80xx_chip_isr, 4728 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4729 .isr_process_oq = process_oq, 4730 .interrupt_enable = pm80xx_chip_interrupt_enable, 4731 .interrupt_disable = pm80xx_chip_interrupt_disable, 4732 .make_prd = pm8001_chip_make_sg, 4733 .smp_req = pm80xx_chip_smp_req, 4734 .ssp_io_req = pm80xx_chip_ssp_io_req, 4735 .sata_req = pm80xx_chip_sata_req, 4736 .phy_start_req = pm80xx_chip_phy_start_req, 4737 .phy_stop_req = pm80xx_chip_phy_stop_req, 4738 .reg_dev_req = pm80xx_chip_reg_dev_req, 4739 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4740 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4741 .task_abort = pm8001_chip_abort_task, 4742 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4743 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4744 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4745 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4746 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4747 }; 4748