1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 #include "pm80xx_tracepoints.h" 46 47 #define SMP_DIRECT 1 48 #define SMP_INDIRECT 2 49 50 51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 52 { 53 u32 reg_val; 54 unsigned long start; 55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 56 /* confirm the setting is written */ 57 start = jiffies + HZ; /* 1 sec */ 58 do { 59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 60 } while ((reg_val != shift_value) && time_before(jiffies, start)); 61 if (reg_val != shift_value) { 62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 63 reg_val); 64 return -1; 65 } 66 return 0; 67 } 68 69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 70 __le32 *destination, 71 u32 dw_count, u32 bus_base_number) 72 { 73 u32 index, value, offset; 74 75 for (index = 0; index < dw_count; index += 4, destination++) { 76 offset = (soffset + index); 77 if (offset < (64 * 1024)) { 78 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 79 *destination = cpu_to_le32(value); 80 } 81 } 82 return; 83 } 84 85 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 86 struct device_attribute *attr, char *buf) 87 { 88 struct Scsi_Host *shost = class_to_shost(cdev); 89 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 90 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 91 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 92 u32 accum_len, reg_val, index, *temp; 93 u32 status = 1; 94 unsigned long start; 95 u8 *direct_data; 96 char *fatal_error_data = buf; 97 u32 length_to_read; 98 u32 offset; 99 100 pm8001_ha->forensic_info.data_buf.direct_data = buf; 101 if (pm8001_ha->chip_id == chip_8001) { 102 pm8001_ha->forensic_info.data_buf.direct_data += 103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 104 "Not supported for SPC controller"); 105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 106 (char *)buf; 107 } 108 /* initialize variables for very first call from host application */ 109 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 110 pm8001_dbg(pm8001_ha, IO, 111 "forensic_info TYPE_NON_FATAL..............\n"); 112 direct_data = (u8 *)fatal_error_data; 113 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 114 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 115 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 116 pm8001_ha->forensic_info.data_buf.read_len = 0; 117 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 118 119 /* Write signature to fatal dump table */ 120 pm8001_mw32(fatal_table_address, 121 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 122 123 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 124 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 126 pm8001_ha->forensic_info.data_buf.read_len); 127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 128 pm8001_ha->forensic_info.data_buf.direct_len); 129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 130 pm8001_ha->forensic_info.data_buf.direct_offset); 131 } 132 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 133 /* start to get data */ 134 /* Program the MEMBASE II Shifting Register with 0x00.*/ 135 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 136 pm8001_ha->fatal_forensic_shift_offset); 137 pm8001_ha->forensic_last_offset = 0; 138 pm8001_ha->forensic_fatal_step = 0; 139 pm8001_ha->fatal_bar_loc = 0; 140 } 141 142 /* Read until accum_len is retrieved */ 143 accum_len = pm8001_mr32(fatal_table_address, 144 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 145 /* Determine length of data between previously stored transfer length 146 * and current accumulated transfer length 147 */ 148 length_to_read = 149 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 150 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 151 accum_len); 152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 153 length_to_read); 154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 155 pm8001_ha->forensic_last_offset); 156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 157 pm8001_ha->forensic_info.data_buf.read_len); 158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 159 pm8001_ha->forensic_info.data_buf.direct_len); 160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 161 pm8001_ha->forensic_info.data_buf.direct_offset); 162 163 /* If accumulated length failed to read correctly fail the attempt.*/ 164 if (accum_len == 0xFFFFFFFF) { 165 pm8001_dbg(pm8001_ha, IO, 166 "Possible PCI issue 0x%x not expected\n", 167 accum_len); 168 return status; 169 } 170 /* If accumulated length is zero fail the attempt */ 171 if (accum_len == 0) { 172 pm8001_ha->forensic_info.data_buf.direct_data += 173 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 174 "%08x ", 0xFFFFFFFF); 175 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 176 (char *)buf; 177 } 178 /* Accumulated length is good so start capturing the first data */ 179 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 180 if (pm8001_ha->forensic_fatal_step == 0) { 181 moreData: 182 /* If data to read is less than SYSFS_OFFSET then reduce the 183 * length of dataLen 184 */ 185 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 186 > length_to_read) { 187 pm8001_ha->forensic_info.data_buf.direct_len = 188 length_to_read - 189 pm8001_ha->forensic_last_offset; 190 } else { 191 pm8001_ha->forensic_info.data_buf.direct_len = 192 SYSFS_OFFSET; 193 } 194 if (pm8001_ha->forensic_info.data_buf.direct_data) { 195 /* Data is in bar, copy to host memory */ 196 pm80xx_pci_mem_copy(pm8001_ha, 197 pm8001_ha->fatal_bar_loc, 198 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 199 pm8001_ha->forensic_info.data_buf.direct_len, 1); 200 } 201 pm8001_ha->fatal_bar_loc += 202 pm8001_ha->forensic_info.data_buf.direct_len; 203 pm8001_ha->forensic_info.data_buf.direct_offset += 204 pm8001_ha->forensic_info.data_buf.direct_len; 205 pm8001_ha->forensic_last_offset += 206 pm8001_ha->forensic_info.data_buf.direct_len; 207 pm8001_ha->forensic_info.data_buf.read_len = 208 pm8001_ha->forensic_info.data_buf.direct_len; 209 210 if (pm8001_ha->forensic_last_offset >= length_to_read) { 211 pm8001_ha->forensic_info.data_buf.direct_data += 212 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 213 "%08x ", 3); 214 for (index = 0; index < 215 (pm8001_ha->forensic_info.data_buf.direct_len 216 / 4); index++) { 217 pm8001_ha->forensic_info.data_buf.direct_data += 218 sprintf( 219 pm8001_ha->forensic_info.data_buf.direct_data, 220 "%08x ", *(temp + index)); 221 } 222 223 pm8001_ha->fatal_bar_loc = 0; 224 pm8001_ha->forensic_fatal_step = 1; 225 pm8001_ha->fatal_forensic_shift_offset = 0; 226 pm8001_ha->forensic_last_offset = 0; 227 status = 0; 228 offset = (int) 229 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 230 - (char *)buf); 231 pm8001_dbg(pm8001_ha, IO, 232 "get_fatal_spcv:return1 0x%x\n", offset); 233 return (char *)pm8001_ha-> 234 forensic_info.data_buf.direct_data - 235 (char *)buf; 236 } 237 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 238 pm8001_ha->forensic_info.data_buf.direct_data += 239 sprintf(pm8001_ha-> 240 forensic_info.data_buf.direct_data, 241 "%08x ", 2); 242 for (index = 0; index < 243 (pm8001_ha->forensic_info.data_buf.direct_len 244 / 4); index++) { 245 pm8001_ha->forensic_info.data_buf.direct_data 246 += sprintf(pm8001_ha-> 247 forensic_info.data_buf.direct_data, 248 "%08x ", *(temp + index)); 249 } 250 status = 0; 251 offset = (int) 252 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 253 - (char *)buf); 254 pm8001_dbg(pm8001_ha, IO, 255 "get_fatal_spcv:return2 0x%x\n", offset); 256 return (char *)pm8001_ha-> 257 forensic_info.data_buf.direct_data - 258 (char *)buf; 259 } 260 261 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 262 pm8001_ha->forensic_info.data_buf.direct_data += 263 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 264 "%08x ", 2); 265 for (index = 0; index < 266 (pm8001_ha->forensic_info.data_buf.direct_len 267 / 4) ; index++) { 268 pm8001_ha->forensic_info.data_buf.direct_data += 269 sprintf(pm8001_ha-> 270 forensic_info.data_buf.direct_data, 271 "%08x ", *(temp + index)); 272 } 273 pm8001_ha->fatal_forensic_shift_offset += 0x100; 274 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 275 pm8001_ha->fatal_forensic_shift_offset); 276 pm8001_ha->fatal_bar_loc = 0; 277 status = 0; 278 offset = (int) 279 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 280 - (char *)buf); 281 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 282 offset); 283 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 284 (char *)buf; 285 } 286 if (pm8001_ha->forensic_fatal_step == 1) { 287 /* store previous accumulated length before triggering next 288 * accumulated length update 289 */ 290 pm8001_ha->forensic_preserved_accumulated_transfer = 291 pm8001_mr32(fatal_table_address, 292 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 293 294 /* continue capturing the fatal log until Dump status is 0x3 */ 295 if (pm8001_mr32(fatal_table_address, 296 MPI_FATAL_EDUMP_TABLE_STATUS) < 297 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 298 299 /* reset fddstat bit by writing to zero*/ 300 pm8001_mw32(fatal_table_address, 301 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 302 303 /* set dump control value to '1' so that new data will 304 * be transferred to shared memory 305 */ 306 pm8001_mw32(fatal_table_address, 307 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 308 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 309 310 /*Poll FDDHSHK until clear */ 311 start = jiffies + (2 * HZ); /* 2 sec */ 312 313 do { 314 reg_val = pm8001_mr32(fatal_table_address, 315 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 316 } while ((reg_val) && time_before(jiffies, start)); 317 318 if (reg_val != 0) { 319 pm8001_dbg(pm8001_ha, FAIL, 320 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 321 reg_val); 322 /* Fail the dump if a timeout occurs */ 323 pm8001_ha->forensic_info.data_buf.direct_data += 324 sprintf( 325 pm8001_ha->forensic_info.data_buf.direct_data, 326 "%08x ", 0xFFFFFFFF); 327 return((char *) 328 pm8001_ha->forensic_info.data_buf.direct_data 329 - (char *)buf); 330 } 331 /* Poll status register until set to 2 or 332 * 3 for up to 2 seconds 333 */ 334 start = jiffies + (2 * HZ); /* 2 sec */ 335 336 do { 337 reg_val = pm8001_mr32(fatal_table_address, 338 MPI_FATAL_EDUMP_TABLE_STATUS); 339 } while (((reg_val != 2) && (reg_val != 3)) && 340 time_before(jiffies, start)); 341 342 if (reg_val < 2) { 343 pm8001_dbg(pm8001_ha, FAIL, 344 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 345 reg_val); 346 /* Fail the dump if a timeout occurs */ 347 pm8001_ha->forensic_info.data_buf.direct_data += 348 sprintf( 349 pm8001_ha->forensic_info.data_buf.direct_data, 350 "%08x ", 0xFFFFFFFF); 351 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 352 (char *)buf); 353 } 354 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 355 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 356 pm8001_cw32(pm8001_ha, 0, 357 MEMBASE_II_SHIFT_REGISTER, 358 pm8001_ha->fatal_forensic_shift_offset); 359 } 360 /* Read the next block of the debug data.*/ 361 length_to_read = pm8001_mr32(fatal_table_address, 362 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 363 pm8001_ha->forensic_preserved_accumulated_transfer; 364 if (length_to_read != 0x0) { 365 pm8001_ha->forensic_fatal_step = 0; 366 goto moreData; 367 } else { 368 pm8001_ha->forensic_info.data_buf.direct_data += 369 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 370 "%08x ", 4); 371 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 372 pm8001_ha->forensic_info.data_buf.direct_len = 0; 373 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 374 pm8001_ha->forensic_info.data_buf.read_len = 0; 375 } 376 } 377 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 378 - (char *)buf); 379 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 380 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 381 (char *)buf); 382 } 383 384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 385 * location by the firmware. 386 */ 387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 388 struct device_attribute *attr, char *buf) 389 { 390 struct Scsi_Host *shost = class_to_shost(cdev); 391 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 392 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 393 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 394 u32 accum_len = 0; 395 u32 total_len = 0; 396 u32 reg_val = 0; 397 u32 *temp = NULL; 398 u32 index = 0; 399 u32 output_length; 400 unsigned long start = 0; 401 char *buf_copy = buf; 402 403 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 404 if (++pm8001_ha->non_fatal_count == 1) { 405 if (pm8001_ha->chip_id == chip_8001) { 406 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 407 PAGE_SIZE, "Not supported for SPC controller"); 408 return 0; 409 } 410 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 411 /* 412 * Step 1: Write the host buffer parameters in the MPI Fatal and 413 * Non-Fatal Error Dump Capture Table.This is the buffer 414 * where debug data will be DMAed to. 415 */ 416 pm8001_mw32(nonfatal_table_address, 417 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 418 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 419 420 pm8001_mw32(nonfatal_table_address, 421 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 422 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 423 424 pm8001_mw32(nonfatal_table_address, 425 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 426 427 /* Optionally, set the DUMPCTRL bit to 1 if the host 428 * keeps sending active I/Os while capturing the non-fatal 429 * debug data. Otherwise, leave this bit set to zero 430 */ 431 pm8001_mw32(nonfatal_table_address, 432 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 433 434 /* 435 * Step 2: Clear Accumulative Length of Debug Data Transferred 436 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 437 * Capture Table to zero. 438 */ 439 pm8001_mw32(nonfatal_table_address, 440 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 441 442 /* initiallize previous accumulated length to 0 */ 443 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 444 pm8001_ha->non_fatal_read_length = 0; 445 } 446 447 total_len = pm8001_mr32(nonfatal_table_address, 448 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 449 /* 450 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 451 * field and then request that the SPCv controller transfer the debug 452 * data by setting bit 7 of the Inbound Doorbell Set Register. 453 */ 454 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 455 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 456 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 457 458 /* 459 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 460 * 2 seconds) until register bit 7 is cleared. 461 * This step only indicates the request is accepted by the controller. 462 */ 463 start = jiffies + (2 * HZ); /* 2 sec */ 464 do { 465 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 466 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 467 } while ((reg_val != 0) && time_before(jiffies, start)); 468 469 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 470 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 471 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 472 */ 473 start = jiffies + (2 * HZ); /* 2 sec */ 474 do { 475 reg_val = pm8001_mr32(nonfatal_table_address, 476 MPI_FATAL_EDUMP_TABLE_STATUS); 477 } while ((!reg_val) && time_before(jiffies, start)); 478 479 if ((reg_val == 0x00) || 480 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 481 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 482 pm8001_ha->non_fatal_read_length = 0; 483 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 484 pm8001_ha->non_fatal_count = 0; 485 return (buf_copy - buf); 486 } else if (reg_val == 487 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 488 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 489 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 490 (pm8001_ha->non_fatal_read_length >= total_len)) { 491 pm8001_ha->non_fatal_read_length = 0; 492 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 493 pm8001_ha->non_fatal_count = 0; 494 } 495 accum_len = pm8001_mr32(nonfatal_table_address, 496 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 497 output_length = accum_len - 498 pm8001_ha->forensic_preserved_accumulated_transfer; 499 500 for (index = 0; index < output_length/4; index++) 501 buf_copy += snprintf(buf_copy, PAGE_SIZE, 502 "%08x ", *(temp+index)); 503 504 pm8001_ha->non_fatal_read_length += output_length; 505 506 /* store current accumulated length to use in next iteration as 507 * the previous accumulated length 508 */ 509 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 510 return (buf_copy - buf); 511 } 512 513 /** 514 * read_main_config_table - read the configure table and save it. 515 * @pm8001_ha: our hba card information 516 */ 517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 518 { 519 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 520 521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 522 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 524 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 526 pm8001_mr32(address, MAIN_FW_REVISION); 527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 528 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 530 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 532 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 534 pm8001_mr32(address, MAIN_GST_OFFSET); 535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 536 pm8001_mr32(address, MAIN_IBQ_OFFSET); 537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 538 pm8001_mr32(address, MAIN_OBQ_OFFSET); 539 540 /* read Error Dump Offset and Length */ 541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 542 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 544 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 546 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 548 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 549 550 /* read GPIO LED settings from the configuration table */ 551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 552 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 553 554 /* read analog Setting offset from the configuration table */ 555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 556 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 557 558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 559 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 561 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 562 /* read port recover and reset timeout */ 563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 564 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 565 /* read ILA and inactive firmware version */ 566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 567 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 569 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 570 571 pm8001_dbg(pm8001_ha, INIT, 572 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 576 577 pm8001_dbg(pm8001_ha, INIT, 578 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 584 585 pm8001_dbg(pm8001_ha, INIT, 586 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 589 } 590 591 /** 592 * read_general_status_table - read the general status table and save it. 593 * @pm8001_ha: our hba card information 594 */ 595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 596 { 597 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 599 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 601 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 603 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 605 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 607 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 609 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 611 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 613 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 615 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 617 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 619 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 621 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 623 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 625 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 626 } 627 /** 628 * read_phy_attr_table - read the phy attribute table and save it. 629 * @pm8001_ha: our hba card information 630 */ 631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 632 { 633 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 634 pm8001_ha->phy_attr_table.phystart1_16[0] = 635 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 636 pm8001_ha->phy_attr_table.phystart1_16[1] = 637 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 638 pm8001_ha->phy_attr_table.phystart1_16[2] = 639 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 640 pm8001_ha->phy_attr_table.phystart1_16[3] = 641 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 642 pm8001_ha->phy_attr_table.phystart1_16[4] = 643 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 644 pm8001_ha->phy_attr_table.phystart1_16[5] = 645 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 646 pm8001_ha->phy_attr_table.phystart1_16[6] = 647 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 648 pm8001_ha->phy_attr_table.phystart1_16[7] = 649 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 650 pm8001_ha->phy_attr_table.phystart1_16[8] = 651 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 652 pm8001_ha->phy_attr_table.phystart1_16[9] = 653 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 654 pm8001_ha->phy_attr_table.phystart1_16[10] = 655 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 656 pm8001_ha->phy_attr_table.phystart1_16[11] = 657 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 658 pm8001_ha->phy_attr_table.phystart1_16[12] = 659 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 660 pm8001_ha->phy_attr_table.phystart1_16[13] = 661 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 662 pm8001_ha->phy_attr_table.phystart1_16[14] = 663 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 664 pm8001_ha->phy_attr_table.phystart1_16[15] = 665 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 666 667 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 668 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 670 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 672 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 674 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 676 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 678 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 680 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 682 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 684 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 686 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 688 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 690 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 692 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 694 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 696 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 698 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 699 700 } 701 702 /** 703 * read_inbnd_queue_table - read the inbound queue table and save it. 704 * @pm8001_ha: our hba card information 705 */ 706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 707 { 708 int i; 709 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 710 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 711 u32 offset = i * 0x20; 712 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 713 get_pci_bar_index(pm8001_mr32(address, 714 (offset + IB_PIPCI_BAR))); 715 pm8001_ha->inbnd_q_tbl[i].pi_offset = 716 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 717 } 718 } 719 720 /** 721 * read_outbnd_queue_table - read the outbound queue table and save it. 722 * @pm8001_ha: our hba card information 723 */ 724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 725 { 726 int i; 727 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 728 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 729 u32 offset = i * 0x24; 730 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 731 get_pci_bar_index(pm8001_mr32(address, 732 (offset + OB_CIPCI_BAR))); 733 pm8001_ha->outbnd_q_tbl[i].ci_offset = 734 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 735 } 736 } 737 738 /** 739 * init_default_table_values - init the default table. 740 * @pm8001_ha: our hba card information 741 */ 742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 743 { 744 int i; 745 u32 offsetib, offsetob; 746 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 747 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 748 u32 ib_offset = pm8001_ha->ib_offset; 749 u32 ob_offset = pm8001_ha->ob_offset; 750 u32 ci_offset = pm8001_ha->ci_offset; 751 u32 pi_offset = pm8001_ha->pi_offset; 752 753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 754 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 756 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 758 PM8001_EVENT_LOG_SIZE; 759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 761 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 763 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 765 PM8001_EVENT_LOG_SIZE; 766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 767 pcs_event_log_severity; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Enable higher IQs and OQs, 32 to 63, bit 16 */ 771 if (pm8001_ha->max_q_num > 32) 772 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 773 1 << 16; 774 /* Disable end to end CRC checking */ 775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 776 777 for (i = 0; i < pm8001_ha->max_q_num; i++) { 778 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 779 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 780 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 781 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 782 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 783 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 784 pm8001_ha->inbnd_q_tbl[i].base_virt = 785 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 786 pm8001_ha->inbnd_q_tbl[i].total_length = 787 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 788 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 789 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 790 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 791 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 792 pm8001_ha->inbnd_q_tbl[i].ci_virt = 793 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 794 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 795 offsetib = i * 0x20; 796 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 797 get_pci_bar_index(pm8001_mr32(addressib, 798 (offsetib + 0x14))); 799 pm8001_ha->inbnd_q_tbl[i].pi_offset = 800 pm8001_mr32(addressib, (offsetib + 0x18)); 801 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 802 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 803 804 pm8001_dbg(pm8001_ha, DEV, 805 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 806 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 807 pm8001_ha->inbnd_q_tbl[i].pi_offset); 808 } 809 for (i = 0; i < pm8001_ha->max_q_num; i++) { 810 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 811 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 812 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 813 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 814 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 815 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 816 pm8001_ha->outbnd_q_tbl[i].base_virt = 817 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 818 pm8001_ha->outbnd_q_tbl[i].total_length = 819 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 820 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 821 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 822 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 823 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 824 /* interrupt vector based on oq */ 825 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 826 pm8001_ha->outbnd_q_tbl[i].pi_virt = 827 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 828 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 829 offsetob = i * 0x24; 830 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 831 get_pci_bar_index(pm8001_mr32(addressob, 832 offsetob + 0x14)); 833 pm8001_ha->outbnd_q_tbl[i].ci_offset = 834 pm8001_mr32(addressob, (offsetob + 0x18)); 835 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 836 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 837 838 pm8001_dbg(pm8001_ha, DEV, 839 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 840 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 841 pm8001_ha->outbnd_q_tbl[i].ci_offset); 842 } 843 } 844 845 /** 846 * update_main_config_table - update the main default table to the HBA. 847 * @pm8001_ha: our hba card information 848 */ 849 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 850 { 851 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 852 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 854 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 856 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 858 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 860 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 866 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 868 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 870 /* Update Fatal error interrupt vector */ 871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 872 ((pm8001_ha->max_q_num - 1) << 8); 873 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 875 pm8001_dbg(pm8001_ha, DEV, 876 "Updated Fatal error interrupt vector 0x%x\n", 877 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 878 879 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 880 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 881 882 /* SPCv specific */ 883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 884 /* Set GPIOLED to 0x2 for LED indicator */ 885 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 886 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 888 pm8001_dbg(pm8001_ha, DEV, 889 "Programming DW 0x21 in main cfg table with 0x%x\n", 890 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 891 892 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 894 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 896 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 898 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 899 PORT_RECOVERY_TIMEOUT; 900 if (pm8001_ha->chip_id == chip_8006) { 901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 902 0x0000ffff; 903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 904 CHIP_8006_PORT_RECOVERY_TIMEOUT; 905 } 906 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 907 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 908 } 909 910 /** 911 * update_inbnd_queue_table - update the inbound queue table to the HBA. 912 * @pm8001_ha: our hba card information 913 * @number: entry in the queue 914 */ 915 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 916 int number) 917 { 918 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 919 u16 offset = number * 0x20; 920 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 922 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 924 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 925 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 926 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 927 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 928 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 929 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 930 931 pm8001_dbg(pm8001_ha, DEV, 932 "IQ %d: Element pri size 0x%x\n", 933 number, 934 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 935 936 pm8001_dbg(pm8001_ha, DEV, 937 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 938 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 939 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 940 941 pm8001_dbg(pm8001_ha, DEV, 942 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 943 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 944 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 945 } 946 947 /** 948 * update_outbnd_queue_table - update the outbound queue table to the HBA. 949 * @pm8001_ha: our hba card information 950 * @number: entry in the queue 951 */ 952 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 953 int number) 954 { 955 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 956 u16 offset = number * 0x24; 957 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 959 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 961 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 963 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 964 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 965 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 966 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 967 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 968 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 969 970 pm8001_dbg(pm8001_ha, DEV, 971 "OQ %d: Element pri size 0x%x\n", 972 number, 973 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 974 975 pm8001_dbg(pm8001_ha, DEV, 976 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 977 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 978 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 979 980 pm8001_dbg(pm8001_ha, DEV, 981 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 982 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 983 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 984 } 985 986 /** 987 * mpi_init_check - check firmware initialization status. 988 * @pm8001_ha: our hba card information 989 */ 990 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 991 { 992 u32 max_wait_count; 993 u32 value; 994 u32 gst_len_mpistate; 995 996 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 997 table is updated */ 998 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 999 /* wait until Inbound DoorBell Clear Register toggled */ 1000 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1001 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1002 } else { 1003 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1004 } 1005 do { 1006 msleep(FW_READY_INTERVAL); 1007 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1008 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1009 } while ((value != 0) && (--max_wait_count)); 1010 1011 if (!max_wait_count) { 1012 /* additional check */ 1013 pm8001_dbg(pm8001_ha, FAIL, 1014 "Inb doorbell clear not toggled[value:%x]\n", 1015 value); 1016 return -EBUSY; 1017 } 1018 /* check the MPI-State for initialization up to 100ms*/ 1019 max_wait_count = 5;/* 100 msec */ 1020 do { 1021 msleep(FW_READY_INTERVAL); 1022 gst_len_mpistate = 1023 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1024 GST_GSTLEN_MPIS_OFFSET); 1025 } while ((GST_MPI_STATE_INIT != 1026 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1027 if (!max_wait_count) 1028 return -EBUSY; 1029 1030 /* check MPI Initialization error */ 1031 gst_len_mpistate = gst_len_mpistate >> 16; 1032 if (0x0000 != gst_len_mpistate) 1033 return -EBUSY; 1034 1035 /* 1036 * As per controller datasheet, after successful MPI 1037 * initialization minimum 500ms delay is required before 1038 * issuing commands. 1039 */ 1040 msleep(500); 1041 1042 return 0; 1043 } 1044 1045 /** 1046 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1047 * This function sleeps hence it must not be used in atomic context. 1048 * @pm8001_ha: our hba card information 1049 */ 1050 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1051 { 1052 u32 value; 1053 u32 max_wait_count; 1054 u32 max_wait_time; 1055 u32 expected_mask; 1056 int ret = 0; 1057 1058 /* reset / PCIe ready */ 1059 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1060 do { 1061 msleep(FW_READY_INTERVAL); 1062 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1063 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1064 1065 /* check ila, RAAE and iops status */ 1066 if ((pm8001_ha->chip_id != chip_8008) && 1067 (pm8001_ha->chip_id != chip_8009)) { 1068 max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 1069 expected_mask = SCRATCH_PAD_ILA_READY | 1070 SCRATCH_PAD_RAAE_READY | 1071 SCRATCH_PAD_IOP0_READY | 1072 SCRATCH_PAD_IOP1_READY; 1073 } else { 1074 max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 1075 expected_mask = SCRATCH_PAD_ILA_READY | 1076 SCRATCH_PAD_RAAE_READY | 1077 SCRATCH_PAD_IOP0_READY; 1078 } 1079 do { 1080 msleep(FW_READY_INTERVAL); 1081 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1082 } while (((value & expected_mask) != 1083 expected_mask) && (--max_wait_count)); 1084 if (!max_wait_count) { 1085 pm8001_dbg(pm8001_ha, INIT, 1086 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 1087 max_wait_time * FW_READY_INTERVAL, value); 1088 ret = -1; 1089 } else { 1090 pm8001_dbg(pm8001_ha, MSG, 1091 "All FW components ready by %d ms\n", 1092 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1093 } 1094 return ret; 1095 } 1096 1097 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1098 { 1099 void __iomem *base_addr; 1100 u32 value; 1101 u32 offset; 1102 u32 pcibar; 1103 u32 pcilogic; 1104 1105 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1106 1107 /* 1108 * lower 26 bits of SCRATCHPAD0 register describes offset within the 1109 * PCIe BAR where the MPI configuration table is present 1110 */ 1111 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1112 1113 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1114 offset, value); 1115 /* 1116 * Upper 6 bits describe the offset within PCI config space where BAR 1117 * is located. 1118 */ 1119 pcilogic = (value & 0xFC000000) >> 26; 1120 pcibar = get_pci_bar_index(pcilogic); 1121 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1122 1123 /* 1124 * Make sure the offset falls inside the ioremapped PCI BAR 1125 */ 1126 if (offset > pm8001_ha->io_mem[pcibar].memsize) { 1127 pm8001_dbg(pm8001_ha, FAIL, 1128 "Main cfg tbl offset outside %u > %u\n", 1129 offset, pm8001_ha->io_mem[pcibar].memsize); 1130 return -EBUSY; 1131 } 1132 pm8001_ha->main_cfg_tbl_addr = base_addr = 1133 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1134 1135 /* 1136 * Validate main configuration table address: first DWord should read 1137 * "PMCS" 1138 */ 1139 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 1140 if (memcmp(&value, "PMCS", 4) != 0) { 1141 pm8001_dbg(pm8001_ha, FAIL, 1142 "BAD main config signature 0x%x\n", 1143 value); 1144 return -EBUSY; 1145 } 1146 pm8001_dbg(pm8001_ha, INIT, 1147 "VALID main config signature 0x%x\n", value); 1148 pm8001_ha->general_stat_tbl_addr = 1149 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1150 0xFFFFFF); 1151 pm8001_ha->inbnd_q_tbl_addr = 1152 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1153 0xFFFFFF); 1154 pm8001_ha->outbnd_q_tbl_addr = 1155 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1156 0xFFFFFF); 1157 pm8001_ha->ivt_tbl_addr = 1158 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1159 0xFFFFFF); 1160 pm8001_ha->pspa_q_tbl_addr = 1161 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1162 0xFFFFFF); 1163 pm8001_ha->fatal_tbl_addr = 1164 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1165 0xFFFFFF); 1166 1167 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1168 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1169 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1170 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1171 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1172 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1173 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1174 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1175 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1176 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1177 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1178 pm8001_ha->main_cfg_tbl_addr, 1179 pm8001_ha->general_stat_tbl_addr); 1180 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1181 pm8001_ha->inbnd_q_tbl_addr, 1182 pm8001_ha->outbnd_q_tbl_addr); 1183 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1184 pm8001_ha->pspa_q_tbl_addr, 1185 pm8001_ha->ivt_tbl_addr); 1186 return 0; 1187 } 1188 1189 /** 1190 * pm80xx_set_thermal_config - support the thermal configuration 1191 * @pm8001_ha: our hba card information. 1192 */ 1193 int 1194 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1195 { 1196 struct set_ctrl_cfg_req payload; 1197 int rc; 1198 u32 tag; 1199 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1200 u32 page_code; 1201 1202 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1203 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1204 if (rc) 1205 return rc; 1206 1207 payload.tag = cpu_to_le32(tag); 1208 1209 if (IS_SPCV_12G(pm8001_ha->pdev)) 1210 page_code = THERMAL_PAGE_CODE_7H; 1211 else 1212 page_code = THERMAL_PAGE_CODE_8H; 1213 1214 payload.cfg_pg[0] = 1215 cpu_to_le32((THERMAL_LOG_ENABLE << 9) | 1216 (THERMAL_ENABLE << 8) | page_code); 1217 payload.cfg_pg[1] = 1218 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8)); 1219 1220 pm8001_dbg(pm8001_ha, DEV, 1221 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1222 payload.cfg_pg[0], payload.cfg_pg[1]); 1223 1224 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1225 sizeof(payload), 0); 1226 if (rc) 1227 pm8001_tag_free(pm8001_ha, tag); 1228 return rc; 1229 1230 } 1231 1232 /** 1233 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1234 * Timer configuration page 1235 * @pm8001_ha: our hba card information. 1236 */ 1237 static int 1238 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1239 { 1240 struct set_ctrl_cfg_req payload; 1241 SASProtocolTimerConfig_t SASConfigPage; 1242 int rc; 1243 u32 tag; 1244 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1245 1246 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1247 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1248 1249 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1250 if (rc) 1251 return rc; 1252 1253 payload.tag = cpu_to_le32(tag); 1254 1255 SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE); 1256 SASConfigPage.MST_MSI = cpu_to_le32(3 << 15); 1257 SASConfigPage.STP_SSP_MCT_TMO = 1258 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO); 1259 SASConfigPage.STP_FRM_TMO = 1260 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) | 1261 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER); 1262 SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME); 1263 1264 SASConfigPage.OPNRJT_RTRY_INTVL = 1265 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL); 1266 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = 1267 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO); 1268 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = 1269 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR); 1270 SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP); 1271 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1273 le32_to_cpu(SASConfigPage.pageCode)); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1275 le32_to_cpu(SASConfigPage.MST_MSI)); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1277 le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO)); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1279 le32_to_cpu(SASConfigPage.STP_FRM_TMO)); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1281 le32_to_cpu(SASConfigPage.STP_IDLE_TMO)); 1282 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1283 le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL)); 1284 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1285 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 1286 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1287 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 1288 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1289 le32_to_cpu(SASConfigPage.MAX_AIP)); 1290 1291 memcpy(&payload.cfg_pg, &SASConfigPage, 1292 sizeof(SASProtocolTimerConfig_t)); 1293 1294 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1295 sizeof(payload), 0); 1296 if (rc) 1297 pm8001_tag_free(pm8001_ha, tag); 1298 1299 return rc; 1300 } 1301 1302 /** 1303 * pm80xx_get_encrypt_info - Check for encryption 1304 * @pm8001_ha: our hba card information. 1305 */ 1306 static int 1307 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1308 { 1309 u32 scratch3_value; 1310 int ret = -1; 1311 1312 /* Read encryption status from SCRATCH PAD 3 */ 1313 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1314 1315 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1316 SCRATCH_PAD3_ENC_READY) { 1317 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1318 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1319 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1320 SCRATCH_PAD3_SMF_ENABLED) 1321 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1322 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1323 SCRATCH_PAD3_SMA_ENABLED) 1324 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1325 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1326 SCRATCH_PAD3_SMB_ENABLED) 1327 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1328 pm8001_ha->encrypt_info.status = 0; 1329 pm8001_dbg(pm8001_ha, INIT, 1330 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1331 scratch3_value, 1332 pm8001_ha->encrypt_info.cipher_mode, 1333 pm8001_ha->encrypt_info.sec_mode, 1334 pm8001_ha->encrypt_info.status); 1335 ret = 0; 1336 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1337 SCRATCH_PAD3_ENC_DISABLED) { 1338 pm8001_dbg(pm8001_ha, INIT, 1339 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1340 scratch3_value); 1341 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1342 pm8001_ha->encrypt_info.cipher_mode = 0; 1343 pm8001_ha->encrypt_info.sec_mode = 0; 1344 ret = 0; 1345 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1346 SCRATCH_PAD3_ENC_DIS_ERR) { 1347 pm8001_ha->encrypt_info.status = 1348 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1349 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1350 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1351 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1352 SCRATCH_PAD3_SMF_ENABLED) 1353 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1354 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1355 SCRATCH_PAD3_SMA_ENABLED) 1356 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1357 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1358 SCRATCH_PAD3_SMB_ENABLED) 1359 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1360 pm8001_dbg(pm8001_ha, INIT, 1361 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1362 scratch3_value, 1363 pm8001_ha->encrypt_info.cipher_mode, 1364 pm8001_ha->encrypt_info.sec_mode, 1365 pm8001_ha->encrypt_info.status); 1366 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1367 SCRATCH_PAD3_ENC_ENA_ERR) { 1368 1369 pm8001_ha->encrypt_info.status = 1370 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1371 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1372 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1373 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1374 SCRATCH_PAD3_SMF_ENABLED) 1375 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1376 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1377 SCRATCH_PAD3_SMA_ENABLED) 1378 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1379 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1380 SCRATCH_PAD3_SMB_ENABLED) 1381 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1382 1383 pm8001_dbg(pm8001_ha, INIT, 1384 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1385 scratch3_value, 1386 pm8001_ha->encrypt_info.cipher_mode, 1387 pm8001_ha->encrypt_info.sec_mode, 1388 pm8001_ha->encrypt_info.status); 1389 } 1390 return ret; 1391 } 1392 1393 /** 1394 * pm80xx_encrypt_update - update flash with encryption information 1395 * @pm8001_ha: our hba card information. 1396 */ 1397 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1398 { 1399 struct kek_mgmt_req payload; 1400 int rc; 1401 u32 tag; 1402 u32 opc = OPC_INB_KEK_MANAGEMENT; 1403 1404 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1405 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1406 if (rc) 1407 return rc; 1408 1409 payload.tag = cpu_to_le32(tag); 1410 /* Currently only one key is used. New KEK index is 1. 1411 * Current KEK index is 1. Store KEK to NVRAM is 1. 1412 */ 1413 payload.new_curidx_ksop = 1414 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) | 1415 KEK_MGMT_SUBOP_KEYCARDUPDATE)); 1416 1417 pm8001_dbg(pm8001_ha, DEV, 1418 "Saving Encryption info to flash. payload 0x%x\n", 1419 le32_to_cpu(payload.new_curidx_ksop)); 1420 1421 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1422 sizeof(payload), 0); 1423 if (rc) 1424 pm8001_tag_free(pm8001_ha, tag); 1425 1426 return rc; 1427 } 1428 1429 /** 1430 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip. 1431 * @pm8001_ha: our hba card information 1432 */ 1433 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1434 { 1435 int ret; 1436 u8 i = 0; 1437 1438 /* check the firmware status */ 1439 if (-1 == check_fw_ready(pm8001_ha)) { 1440 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1441 return -EBUSY; 1442 } 1443 1444 /* Initialize the controller fatal error flag */ 1445 pm8001_ha->controller_fatal_error = false; 1446 1447 /* Initialize pci space address eg: mpi offset */ 1448 ret = init_pci_device_addresses(pm8001_ha); 1449 if (ret) { 1450 pm8001_dbg(pm8001_ha, FAIL, 1451 "Failed to init pci addresses"); 1452 return ret; 1453 } 1454 init_default_table_values(pm8001_ha); 1455 read_main_config_table(pm8001_ha); 1456 read_general_status_table(pm8001_ha); 1457 read_inbnd_queue_table(pm8001_ha); 1458 read_outbnd_queue_table(pm8001_ha); 1459 read_phy_attr_table(pm8001_ha); 1460 1461 /* update main config table ,inbound table and outbound table */ 1462 update_main_config_table(pm8001_ha); 1463 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1464 update_inbnd_queue_table(pm8001_ha, i); 1465 update_outbnd_queue_table(pm8001_ha, i); 1466 } 1467 /* notify firmware update finished and check initialization status */ 1468 if (0 == mpi_init_check(pm8001_ha)) { 1469 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1470 } else 1471 return -EBUSY; 1472 1473 return 0; 1474 } 1475 1476 static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha) 1477 { 1478 /* send SAS protocol timer configuration page to FW */ 1479 pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1480 1481 /* Check for encryption */ 1482 if (pm8001_ha->chip->encrypt) { 1483 int ret; 1484 1485 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1486 ret = pm80xx_get_encrypt_info(pm8001_ha); 1487 if (ret == -1) { 1488 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1489 if (pm8001_ha->encrypt_info.status == 0x81) { 1490 pm8001_dbg(pm8001_ha, INIT, 1491 "Encryption enabled with error.Saving encryption key to flash\n"); 1492 pm80xx_encrypt_update(pm8001_ha); 1493 } 1494 } 1495 } 1496 } 1497 1498 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1499 { 1500 u32 max_wait_count; 1501 u32 value; 1502 u32 gst_len_mpistate; 1503 int ret; 1504 1505 ret = init_pci_device_addresses(pm8001_ha); 1506 if (ret) { 1507 pm8001_dbg(pm8001_ha, FAIL, 1508 "Failed to init pci addresses"); 1509 return ret; 1510 } 1511 1512 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1513 table is stop */ 1514 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1515 1516 /* wait until Inbound DoorBell Clear Register toggled */ 1517 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1518 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1519 } else { 1520 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1521 } 1522 do { 1523 msleep(FW_READY_INTERVAL); 1524 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1525 value &= SPCv_MSGU_CFG_TABLE_RESET; 1526 } while ((value != 0) && (--max_wait_count)); 1527 1528 if (!max_wait_count) { 1529 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1530 return -1; 1531 } 1532 1533 /* check the MPI-State for termination in progress */ 1534 /* wait until Inbound DoorBell Clear Register toggled */ 1535 max_wait_count = 100; /* 2 sec for spcv/ve */ 1536 do { 1537 msleep(FW_READY_INTERVAL); 1538 gst_len_mpistate = 1539 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1540 GST_GSTLEN_MPIS_OFFSET); 1541 if (GST_MPI_STATE_UNINIT == 1542 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1543 break; 1544 } while (--max_wait_count); 1545 if (!max_wait_count) { 1546 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1547 gst_len_mpistate & GST_MPI_STATE_MASK); 1548 return -1; 1549 } 1550 1551 return 0; 1552 } 1553 1554 /** 1555 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors 1556 * @pm8001_ha: our hba card information 1557 * 1558 * Fatal errors are recoverable only after a host reboot. 1559 */ 1560 int 1561 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1562 { 1563 int ret = 0; 1564 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 1565 MSGU_SCRATCH_PAD_RSVD_0); 1566 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 1567 MSGU_SCRATCH_PAD_RSVD_1); 1568 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1569 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1570 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1571 1572 if (pm8001_ha->chip_id != chip_8006 && 1573 pm8001_ha->chip_id != chip_8074 && 1574 pm8001_ha->chip_id != chip_8076) { 1575 return 0; 1576 } 1577 1578 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1579 pm8001_dbg(pm8001_ha, FAIL, 1580 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1581 scratch_pad1, scratch_pad2, scratch_pad3, 1582 scratch_pad_rsvd0, scratch_pad_rsvd1); 1583 ret = 1; 1584 } 1585 1586 return ret; 1587 } 1588 1589 /** 1590 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all 1591 * FW register status are reset to the originated status. 1592 * @pm8001_ha: our hba card information 1593 */ 1594 1595 static int 1596 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1597 { 1598 u32 regval; 1599 u32 bootloader_state; 1600 u32 ibutton0, ibutton1; 1601 1602 /* Process MPI table uninitialization only if FW is ready */ 1603 if (!pm8001_ha->controller_fatal_error) { 1604 /* Check if MPI is in ready state to reset */ 1605 if (mpi_uninit_check(pm8001_ha) != 0) { 1606 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1607 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1608 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1609 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1610 pm8001_dbg(pm8001_ha, FAIL, 1611 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1612 r0, r1, r2, r3); 1613 /* if things aren't ready but the bootloader is ok then 1614 * try the reset anyway. 1615 */ 1616 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1617 return -1; 1618 } 1619 } 1620 /* checked for reset register normal state; 0x0 */ 1621 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1622 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1623 regval); 1624 1625 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1626 msleep(500); 1627 1628 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1629 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1630 regval); 1631 1632 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1633 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1634 pm8001_dbg(pm8001_ha, MSG, 1635 " soft reset successful [regval: 0x%x]\n", 1636 regval); 1637 } else { 1638 pm8001_dbg(pm8001_ha, MSG, 1639 " soft reset failed [regval: 0x%x]\n", 1640 regval); 1641 1642 /* check bootloader is successfully executed or in HDA mode */ 1643 bootloader_state = 1644 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1645 SCRATCH_PAD1_BOOTSTATE_MASK; 1646 1647 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1648 pm8001_dbg(pm8001_ha, MSG, 1649 "Bootloader state - HDA mode SEEPROM\n"); 1650 } else if (bootloader_state == 1651 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1652 pm8001_dbg(pm8001_ha, MSG, 1653 "Bootloader state - HDA mode Bootstrap Pin\n"); 1654 } else if (bootloader_state == 1655 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1656 pm8001_dbg(pm8001_ha, MSG, 1657 "Bootloader state - HDA mode soft reset\n"); 1658 } else if (bootloader_state == 1659 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1660 pm8001_dbg(pm8001_ha, MSG, 1661 "Bootloader state-HDA mode critical error\n"); 1662 } 1663 return -EBUSY; 1664 } 1665 1666 /* check the firmware status after reset */ 1667 if (-1 == check_fw_ready(pm8001_ha)) { 1668 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1669 /* check iButton feature support for motherboard controller */ 1670 if (pm8001_ha->pdev->subsystem_vendor != 1671 PCI_VENDOR_ID_ADAPTEC2 && 1672 pm8001_ha->pdev->subsystem_vendor != 1673 PCI_VENDOR_ID_ATTO && 1674 pm8001_ha->pdev->subsystem_vendor != 0) { 1675 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1676 MSGU_SCRATCH_PAD_RSVD_0); 1677 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1678 MSGU_SCRATCH_PAD_RSVD_1); 1679 if (!ibutton0 && !ibutton1) { 1680 pm8001_dbg(pm8001_ha, FAIL, 1681 "iButton Feature is not Available!!!\n"); 1682 return -EBUSY; 1683 } 1684 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1685 pm8001_dbg(pm8001_ha, FAIL, 1686 "CRC Check for iButton Feature Failed!!!\n"); 1687 return -EBUSY; 1688 } 1689 } 1690 } 1691 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1692 return 0; 1693 } 1694 1695 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1696 { 1697 u32 i; 1698 1699 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1700 1701 /* do SPCv chip reset. */ 1702 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1703 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1704 1705 /* Check this ..whether delay is required or no */ 1706 /* delay 10 usec */ 1707 udelay(10); 1708 1709 /* wait for 20 msec until the firmware gets reloaded */ 1710 i = 20; 1711 do { 1712 mdelay(1); 1713 } while ((--i) != 0); 1714 1715 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1716 } 1717 1718 /** 1719 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt 1720 * @pm8001_ha: our hba card information 1721 * @vec: interrupt number to enable 1722 */ 1723 static void 1724 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1725 { 1726 if (!pm8001_ha->use_msix) { 1727 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1728 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1729 return; 1730 } 1731 1732 if (vec < 32) 1733 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); 1734 else 1735 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32)); 1736 } 1737 1738 /** 1739 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt 1740 * @pm8001_ha: our hba card information 1741 * @vec: interrupt number to disable 1742 */ 1743 static void 1744 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1745 { 1746 if (!pm8001_ha->use_msix) { 1747 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1748 return; 1749 } 1750 1751 if (vec == 0xFF) { 1752 /* disable all vectors 0-31, 32-63 */ 1753 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); 1754 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); 1755 } else if (vec < 32) { 1756 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); 1757 } else { 1758 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32)); 1759 } 1760 } 1761 1762 /** 1763 * mpi_ssp_completion - process the event that FW response to the SSP request. 1764 * @pm8001_ha: our hba card information 1765 * @piomb: the message contents of this outbound message. 1766 * 1767 * When FW has completed a ssp request for example a IO request, after it has 1768 * filled the SG data with the data, it will trigger this event representing 1769 * that he has finished the job; please check the corresponding buffer. 1770 * So we will tell the caller who maybe waiting the result to tell upper layer 1771 * that the task has been finished. 1772 */ 1773 static void 1774 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1775 { 1776 struct sas_task *t; 1777 struct pm8001_ccb_info *ccb; 1778 unsigned long flags; 1779 u32 status; 1780 u32 param; 1781 u32 tag; 1782 struct ssp_completion_resp *psspPayload; 1783 struct task_status_struct *ts; 1784 struct ssp_response_iu *iu; 1785 struct pm8001_device *pm8001_dev; 1786 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1787 status = le32_to_cpu(psspPayload->status); 1788 tag = le32_to_cpu(psspPayload->tag); 1789 ccb = &pm8001_ha->ccb_info[tag]; 1790 if ((status == IO_ABORTED) && ccb->open_retry) { 1791 /* Being completed by another */ 1792 ccb->open_retry = 0; 1793 return; 1794 } 1795 pm8001_dev = ccb->device; 1796 param = le32_to_cpu(psspPayload->param); 1797 t = ccb->task; 1798 1799 if (status && status != IO_UNDERFLOW) 1800 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1801 if (unlikely(!t || !t->lldd_task || !t->dev)) 1802 return; 1803 ts = &t->task_status; 1804 1805 pm8001_dbg(pm8001_ha, DEV, 1806 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1807 1808 /* Print sas address of IO failed device */ 1809 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1810 (status != IO_UNDERFLOW)) 1811 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1812 SAS_ADDR(t->dev->sas_addr)); 1813 1814 switch (status) { 1815 case IO_SUCCESS: 1816 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1817 param); 1818 if (param == 0) { 1819 ts->resp = SAS_TASK_COMPLETE; 1820 ts->stat = SAS_SAM_STAT_GOOD; 1821 } else { 1822 ts->resp = SAS_TASK_COMPLETE; 1823 ts->stat = SAS_PROTO_RESPONSE; 1824 ts->residual = param; 1825 iu = &psspPayload->ssp_resp_iu; 1826 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1827 } 1828 if (pm8001_dev) 1829 atomic_dec(&pm8001_dev->running_req); 1830 break; 1831 case IO_ABORTED: 1832 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1833 ts->resp = SAS_TASK_COMPLETE; 1834 ts->stat = SAS_ABORTED_TASK; 1835 if (pm8001_dev) 1836 atomic_dec(&pm8001_dev->running_req); 1837 break; 1838 case IO_UNDERFLOW: 1839 /* SSP Completion with error */ 1840 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1841 param); 1842 ts->resp = SAS_TASK_COMPLETE; 1843 ts->stat = SAS_DATA_UNDERRUN; 1844 ts->residual = param; 1845 if (pm8001_dev) 1846 atomic_dec(&pm8001_dev->running_req); 1847 break; 1848 case IO_NO_DEVICE: 1849 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1850 ts->resp = SAS_TASK_UNDELIVERED; 1851 ts->stat = SAS_PHY_DOWN; 1852 if (pm8001_dev) 1853 atomic_dec(&pm8001_dev->running_req); 1854 break; 1855 case IO_XFER_ERROR_BREAK: 1856 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1857 ts->resp = SAS_TASK_COMPLETE; 1858 ts->stat = SAS_OPEN_REJECT; 1859 /* Force the midlayer to retry */ 1860 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1861 if (pm8001_dev) 1862 atomic_dec(&pm8001_dev->running_req); 1863 break; 1864 case IO_XFER_ERROR_PHY_NOT_READY: 1865 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1866 ts->resp = SAS_TASK_COMPLETE; 1867 ts->stat = SAS_OPEN_REJECT; 1868 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1869 if (pm8001_dev) 1870 atomic_dec(&pm8001_dev->running_req); 1871 break; 1872 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1873 pm8001_dbg(pm8001_ha, IO, 1874 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 1875 ts->resp = SAS_TASK_COMPLETE; 1876 ts->stat = SAS_OPEN_REJECT; 1877 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1878 if (pm8001_dev) 1879 atomic_dec(&pm8001_dev->running_req); 1880 break; 1881 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1882 pm8001_dbg(pm8001_ha, IO, 1883 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1884 ts->resp = SAS_TASK_COMPLETE; 1885 ts->stat = SAS_OPEN_REJECT; 1886 ts->open_rej_reason = SAS_OREJ_EPROTO; 1887 if (pm8001_dev) 1888 atomic_dec(&pm8001_dev->running_req); 1889 break; 1890 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1891 pm8001_dbg(pm8001_ha, IO, 1892 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1893 ts->resp = SAS_TASK_COMPLETE; 1894 ts->stat = SAS_OPEN_REJECT; 1895 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1896 if (pm8001_dev) 1897 atomic_dec(&pm8001_dev->running_req); 1898 break; 1899 case IO_OPEN_CNX_ERROR_BREAK: 1900 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1901 ts->resp = SAS_TASK_COMPLETE; 1902 ts->stat = SAS_OPEN_REJECT; 1903 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1904 if (pm8001_dev) 1905 atomic_dec(&pm8001_dev->running_req); 1906 break; 1907 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1908 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1909 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1910 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1911 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1912 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1913 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1914 ts->resp = SAS_TASK_COMPLETE; 1915 ts->stat = SAS_OPEN_REJECT; 1916 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1917 if (!t->uldd_task) 1918 pm8001_handle_event(pm8001_ha, 1919 pm8001_dev, 1920 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1921 break; 1922 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1923 pm8001_dbg(pm8001_ha, IO, 1924 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 1925 ts->resp = SAS_TASK_COMPLETE; 1926 ts->stat = SAS_OPEN_REJECT; 1927 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1928 if (pm8001_dev) 1929 atomic_dec(&pm8001_dev->running_req); 1930 break; 1931 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1932 pm8001_dbg(pm8001_ha, IO, 1933 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 1934 ts->resp = SAS_TASK_COMPLETE; 1935 ts->stat = SAS_OPEN_REJECT; 1936 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1937 if (pm8001_dev) 1938 atomic_dec(&pm8001_dev->running_req); 1939 break; 1940 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1941 pm8001_dbg(pm8001_ha, IO, 1942 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 1943 ts->resp = SAS_TASK_UNDELIVERED; 1944 ts->stat = SAS_OPEN_REJECT; 1945 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1946 if (pm8001_dev) 1947 atomic_dec(&pm8001_dev->running_req); 1948 break; 1949 case IO_XFER_ERROR_NAK_RECEIVED: 1950 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 1951 ts->resp = SAS_TASK_COMPLETE; 1952 ts->stat = SAS_OPEN_REJECT; 1953 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1954 if (pm8001_dev) 1955 atomic_dec(&pm8001_dev->running_req); 1956 break; 1957 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1958 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 1959 ts->resp = SAS_TASK_COMPLETE; 1960 ts->stat = SAS_NAK_R_ERR; 1961 if (pm8001_dev) 1962 atomic_dec(&pm8001_dev->running_req); 1963 break; 1964 case IO_XFER_ERROR_DMA: 1965 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 1966 ts->resp = SAS_TASK_COMPLETE; 1967 ts->stat = SAS_OPEN_REJECT; 1968 if (pm8001_dev) 1969 atomic_dec(&pm8001_dev->running_req); 1970 break; 1971 case IO_XFER_OPEN_RETRY_TIMEOUT: 1972 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1973 ts->resp = SAS_TASK_COMPLETE; 1974 ts->stat = SAS_OPEN_REJECT; 1975 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1976 if (pm8001_dev) 1977 atomic_dec(&pm8001_dev->running_req); 1978 break; 1979 case IO_XFER_ERROR_OFFSET_MISMATCH: 1980 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 1981 ts->resp = SAS_TASK_COMPLETE; 1982 ts->stat = SAS_OPEN_REJECT; 1983 if (pm8001_dev) 1984 atomic_dec(&pm8001_dev->running_req); 1985 break; 1986 case IO_PORT_IN_RESET: 1987 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 1988 ts->resp = SAS_TASK_COMPLETE; 1989 ts->stat = SAS_OPEN_REJECT; 1990 if (pm8001_dev) 1991 atomic_dec(&pm8001_dev->running_req); 1992 break; 1993 case IO_DS_NON_OPERATIONAL: 1994 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 1995 ts->resp = SAS_TASK_COMPLETE; 1996 ts->stat = SAS_OPEN_REJECT; 1997 if (!t->uldd_task) 1998 pm8001_handle_event(pm8001_ha, 1999 pm8001_dev, 2000 IO_DS_NON_OPERATIONAL); 2001 break; 2002 case IO_DS_IN_RECOVERY: 2003 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2004 ts->resp = SAS_TASK_COMPLETE; 2005 ts->stat = SAS_OPEN_REJECT; 2006 if (pm8001_dev) 2007 atomic_dec(&pm8001_dev->running_req); 2008 break; 2009 case IO_TM_TAG_NOT_FOUND: 2010 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2011 ts->resp = SAS_TASK_COMPLETE; 2012 ts->stat = SAS_OPEN_REJECT; 2013 if (pm8001_dev) 2014 atomic_dec(&pm8001_dev->running_req); 2015 break; 2016 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2017 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2018 ts->resp = SAS_TASK_COMPLETE; 2019 ts->stat = SAS_OPEN_REJECT; 2020 if (pm8001_dev) 2021 atomic_dec(&pm8001_dev->running_req); 2022 break; 2023 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2024 pm8001_dbg(pm8001_ha, IO, 2025 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2026 ts->resp = SAS_TASK_COMPLETE; 2027 ts->stat = SAS_OPEN_REJECT; 2028 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2029 if (pm8001_dev) 2030 atomic_dec(&pm8001_dev->running_req); 2031 break; 2032 default: 2033 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2034 /* not allowed case. Therefore, return failed status */ 2035 ts->resp = SAS_TASK_COMPLETE; 2036 ts->stat = SAS_OPEN_REJECT; 2037 if (pm8001_dev) 2038 atomic_dec(&pm8001_dev->running_req); 2039 break; 2040 } 2041 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n", 2042 psspPayload->ssp_resp_iu.status); 2043 spin_lock_irqsave(&t->task_state_lock, flags); 2044 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2045 t->task_state_flags |= SAS_TASK_STATE_DONE; 2046 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2047 spin_unlock_irqrestore(&t->task_state_lock, flags); 2048 pm8001_dbg(pm8001_ha, FAIL, 2049 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2050 t, status, ts->resp, ts->stat); 2051 pm8001_ccb_task_free(pm8001_ha, ccb); 2052 if (t->slow_task) 2053 complete(&t->slow_task->completion); 2054 } else { 2055 spin_unlock_irqrestore(&t->task_state_lock, flags); 2056 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2057 } 2058 } 2059 2060 /*See the comments for mpi_ssp_completion */ 2061 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2062 { 2063 struct sas_task *t; 2064 unsigned long flags; 2065 struct task_status_struct *ts; 2066 struct pm8001_ccb_info *ccb; 2067 struct pm8001_device *pm8001_dev; 2068 struct ssp_event_resp *psspPayload = 2069 (struct ssp_event_resp *)(piomb + 4); 2070 u32 event = le32_to_cpu(psspPayload->event); 2071 u32 tag = le32_to_cpu(psspPayload->tag); 2072 u32 port_id = le32_to_cpu(psspPayload->port_id); 2073 2074 ccb = &pm8001_ha->ccb_info[tag]; 2075 t = ccb->task; 2076 pm8001_dev = ccb->device; 2077 if (event) 2078 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2079 if (unlikely(!t || !t->lldd_task || !t->dev)) 2080 return; 2081 ts = &t->task_status; 2082 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2083 port_id, tag, event); 2084 switch (event) { 2085 case IO_OVERFLOW: 2086 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2087 ts->resp = SAS_TASK_COMPLETE; 2088 ts->stat = SAS_DATA_OVERRUN; 2089 ts->residual = 0; 2090 if (pm8001_dev) 2091 atomic_dec(&pm8001_dev->running_req); 2092 break; 2093 case IO_XFER_ERROR_BREAK: 2094 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2095 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2096 return; 2097 case IO_XFER_ERROR_PHY_NOT_READY: 2098 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2099 ts->resp = SAS_TASK_COMPLETE; 2100 ts->stat = SAS_OPEN_REJECT; 2101 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2102 break; 2103 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2104 pm8001_dbg(pm8001_ha, IO, 2105 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_OPEN_REJECT; 2108 ts->open_rej_reason = SAS_OREJ_EPROTO; 2109 break; 2110 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2111 pm8001_dbg(pm8001_ha, IO, 2112 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2113 ts->resp = SAS_TASK_COMPLETE; 2114 ts->stat = SAS_OPEN_REJECT; 2115 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2116 break; 2117 case IO_OPEN_CNX_ERROR_BREAK: 2118 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2119 ts->resp = SAS_TASK_COMPLETE; 2120 ts->stat = SAS_OPEN_REJECT; 2121 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2122 break; 2123 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2124 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2125 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2126 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2127 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2128 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2129 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2130 ts->resp = SAS_TASK_COMPLETE; 2131 ts->stat = SAS_OPEN_REJECT; 2132 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2133 if (!t->uldd_task) 2134 pm8001_handle_event(pm8001_ha, 2135 pm8001_dev, 2136 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2137 break; 2138 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2139 pm8001_dbg(pm8001_ha, IO, 2140 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2141 ts->resp = SAS_TASK_COMPLETE; 2142 ts->stat = SAS_OPEN_REJECT; 2143 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2144 break; 2145 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2146 pm8001_dbg(pm8001_ha, IO, 2147 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2148 ts->resp = SAS_TASK_COMPLETE; 2149 ts->stat = SAS_OPEN_REJECT; 2150 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2151 break; 2152 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2153 pm8001_dbg(pm8001_ha, IO, 2154 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2155 ts->resp = SAS_TASK_COMPLETE; 2156 ts->stat = SAS_OPEN_REJECT; 2157 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2158 break; 2159 case IO_XFER_ERROR_NAK_RECEIVED: 2160 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2161 ts->resp = SAS_TASK_COMPLETE; 2162 ts->stat = SAS_OPEN_REJECT; 2163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2164 break; 2165 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2166 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2167 ts->resp = SAS_TASK_COMPLETE; 2168 ts->stat = SAS_NAK_R_ERR; 2169 break; 2170 case IO_XFER_OPEN_RETRY_TIMEOUT: 2171 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2172 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2173 return; 2174 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2175 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2176 ts->resp = SAS_TASK_COMPLETE; 2177 ts->stat = SAS_DATA_OVERRUN; 2178 break; 2179 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2180 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2181 ts->resp = SAS_TASK_COMPLETE; 2182 ts->stat = SAS_DATA_OVERRUN; 2183 break; 2184 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2185 pm8001_dbg(pm8001_ha, IO, 2186 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2187 ts->resp = SAS_TASK_COMPLETE; 2188 ts->stat = SAS_DATA_OVERRUN; 2189 break; 2190 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2191 pm8001_dbg(pm8001_ha, IO, 2192 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2193 ts->resp = SAS_TASK_COMPLETE; 2194 ts->stat = SAS_DATA_OVERRUN; 2195 break; 2196 case IO_XFER_ERROR_OFFSET_MISMATCH: 2197 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2198 ts->resp = SAS_TASK_COMPLETE; 2199 ts->stat = SAS_DATA_OVERRUN; 2200 break; 2201 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2202 pm8001_dbg(pm8001_ha, IO, 2203 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2204 ts->resp = SAS_TASK_COMPLETE; 2205 ts->stat = SAS_DATA_OVERRUN; 2206 break; 2207 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2208 pm8001_dbg(pm8001_ha, IOERR, 2209 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2210 /* TBC: used default set values */ 2211 ts->resp = SAS_TASK_COMPLETE; 2212 ts->stat = SAS_DATA_OVERRUN; 2213 break; 2214 case IO_XFER_CMD_FRAME_ISSUED: 2215 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2216 return; 2217 default: 2218 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2219 /* not allowed case. Therefore, return failed status */ 2220 ts->resp = SAS_TASK_COMPLETE; 2221 ts->stat = SAS_DATA_OVERRUN; 2222 break; 2223 } 2224 spin_lock_irqsave(&t->task_state_lock, flags); 2225 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2226 t->task_state_flags |= SAS_TASK_STATE_DONE; 2227 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2228 spin_unlock_irqrestore(&t->task_state_lock, flags); 2229 pm8001_dbg(pm8001_ha, FAIL, 2230 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2231 t, event, ts->resp, ts->stat); 2232 pm8001_ccb_task_free(pm8001_ha, ccb); 2233 } else { 2234 spin_unlock_irqrestore(&t->task_state_lock, flags); 2235 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2236 } 2237 } 2238 2239 /*See the comments for mpi_ssp_completion */ 2240 static void 2241 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, 2242 struct outbound_queue_table *circularQ, void *piomb) 2243 { 2244 struct sas_task *t; 2245 struct pm8001_ccb_info *ccb; 2246 u32 param; 2247 u32 status; 2248 u32 tag; 2249 int i, j; 2250 u8 sata_addr_low[4]; 2251 u32 temp_sata_addr_low, temp_sata_addr_hi; 2252 u8 sata_addr_hi[4]; 2253 struct sata_completion_resp *psataPayload; 2254 struct task_status_struct *ts; 2255 struct ata_task_resp *resp ; 2256 u32 *sata_resp; 2257 struct pm8001_device *pm8001_dev; 2258 unsigned long flags; 2259 2260 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2261 status = le32_to_cpu(psataPayload->status); 2262 param = le32_to_cpu(psataPayload->param); 2263 tag = le32_to_cpu(psataPayload->tag); 2264 2265 ccb = &pm8001_ha->ccb_info[tag]; 2266 t = ccb->task; 2267 pm8001_dev = ccb->device; 2268 2269 if (t) { 2270 if (t->dev && (t->dev->lldd_dev)) 2271 pm8001_dev = t->dev->lldd_dev; 2272 } else { 2273 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2274 ccb->ccb_tag); 2275 pm8001_ccb_free(pm8001_ha, ccb); 2276 return; 2277 } 2278 2279 2280 if (pm8001_dev && unlikely(!t->lldd_task || !t->dev)) 2281 return; 2282 2283 ts = &t->task_status; 2284 2285 if (status != IO_SUCCESS) { 2286 pm8001_dbg(pm8001_ha, FAIL, 2287 "IO failed device_id %u status 0x%x tag %d\n", 2288 pm8001_dev->device_id, status, tag); 2289 } 2290 2291 /* Print sas address of IO failed device */ 2292 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2293 (status != IO_UNDERFLOW)) { 2294 if (!((t->dev->parent) && 2295 (dev_is_expander(t->dev->parent->dev_type)))) { 2296 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) 2297 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2298 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) 2299 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2300 memcpy(&temp_sata_addr_low, sata_addr_low, 2301 sizeof(sata_addr_low)); 2302 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2303 sizeof(sata_addr_hi)); 2304 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2305 |((temp_sata_addr_hi << 8) & 2306 0xff0000) | 2307 ((temp_sata_addr_hi >> 8) 2308 & 0xff00) | 2309 ((temp_sata_addr_hi << 24) & 2310 0xff000000)); 2311 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2312 & 0xff) | 2313 ((temp_sata_addr_low << 8) 2314 & 0xff0000) | 2315 ((temp_sata_addr_low >> 8) 2316 & 0xff00) | 2317 ((temp_sata_addr_low << 24) 2318 & 0xff000000)) + 2319 pm8001_dev->attached_phy + 2320 0x10); 2321 pm8001_dbg(pm8001_ha, FAIL, 2322 "SAS Address of IO Failure Drive:%08x%08x\n", 2323 temp_sata_addr_hi, 2324 temp_sata_addr_low); 2325 2326 } else { 2327 pm8001_dbg(pm8001_ha, FAIL, 2328 "SAS Address of IO Failure Drive:%016llx\n", 2329 SAS_ADDR(t->dev->sas_addr)); 2330 } 2331 } 2332 switch (status) { 2333 case IO_SUCCESS: 2334 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2335 if (param == 0) { 2336 ts->resp = SAS_TASK_COMPLETE; 2337 ts->stat = SAS_SAM_STAT_GOOD; 2338 } else { 2339 u8 len; 2340 ts->resp = SAS_TASK_COMPLETE; 2341 ts->stat = SAS_PROTO_RESPONSE; 2342 ts->residual = param; 2343 pm8001_dbg(pm8001_ha, IO, 2344 "SAS_PROTO_RESPONSE len = %d\n", 2345 param); 2346 sata_resp = &psataPayload->sata_resp[0]; 2347 resp = (struct ata_task_resp *)ts->buf; 2348 if (t->ata_task.dma_xfer == 0 && 2349 t->data_dir == DMA_FROM_DEVICE) { 2350 len = sizeof(struct pio_setup_fis); 2351 pm8001_dbg(pm8001_ha, IO, 2352 "PIO read len = %d\n", len); 2353 } else if (t->ata_task.use_ncq && 2354 t->data_dir != DMA_NONE) { 2355 len = sizeof(struct set_dev_bits_fis); 2356 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2357 len); 2358 } else { 2359 len = sizeof(struct dev_to_host_fis); 2360 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2361 len); 2362 } 2363 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2364 resp->frame_len = len; 2365 memcpy(&resp->ending_fis[0], sata_resp, len); 2366 ts->buf_valid_size = sizeof(*resp); 2367 } else 2368 pm8001_dbg(pm8001_ha, IO, 2369 "response too large\n"); 2370 } 2371 if (pm8001_dev) 2372 atomic_dec(&pm8001_dev->running_req); 2373 break; 2374 case IO_ABORTED: 2375 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2376 ts->resp = SAS_TASK_COMPLETE; 2377 ts->stat = SAS_ABORTED_TASK; 2378 if (pm8001_dev) 2379 atomic_dec(&pm8001_dev->running_req); 2380 break; 2381 /* following cases are to do cases */ 2382 case IO_UNDERFLOW: 2383 /* SATA Completion with error */ 2384 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2385 ts->resp = SAS_TASK_COMPLETE; 2386 ts->stat = SAS_DATA_UNDERRUN; 2387 ts->residual = param; 2388 if (pm8001_dev) 2389 atomic_dec(&pm8001_dev->running_req); 2390 break; 2391 case IO_NO_DEVICE: 2392 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2393 ts->resp = SAS_TASK_UNDELIVERED; 2394 ts->stat = SAS_PHY_DOWN; 2395 if (pm8001_dev) 2396 atomic_dec(&pm8001_dev->running_req); 2397 break; 2398 case IO_XFER_ERROR_BREAK: 2399 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2400 ts->resp = SAS_TASK_COMPLETE; 2401 ts->stat = SAS_INTERRUPTED; 2402 if (pm8001_dev) 2403 atomic_dec(&pm8001_dev->running_req); 2404 break; 2405 case IO_XFER_ERROR_PHY_NOT_READY: 2406 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2407 ts->resp = SAS_TASK_COMPLETE; 2408 ts->stat = SAS_OPEN_REJECT; 2409 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2410 if (pm8001_dev) 2411 atomic_dec(&pm8001_dev->running_req); 2412 break; 2413 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2414 pm8001_dbg(pm8001_ha, IO, 2415 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2416 ts->resp = SAS_TASK_COMPLETE; 2417 ts->stat = SAS_OPEN_REJECT; 2418 ts->open_rej_reason = SAS_OREJ_EPROTO; 2419 if (pm8001_dev) 2420 atomic_dec(&pm8001_dev->running_req); 2421 break; 2422 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2423 pm8001_dbg(pm8001_ha, IO, 2424 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2425 ts->resp = SAS_TASK_COMPLETE; 2426 ts->stat = SAS_OPEN_REJECT; 2427 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2428 if (pm8001_dev) 2429 atomic_dec(&pm8001_dev->running_req); 2430 break; 2431 case IO_OPEN_CNX_ERROR_BREAK: 2432 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2433 ts->resp = SAS_TASK_COMPLETE; 2434 ts->stat = SAS_OPEN_REJECT; 2435 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2436 if (pm8001_dev) 2437 atomic_dec(&pm8001_dev->running_req); 2438 break; 2439 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2440 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2441 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2442 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2443 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2444 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2445 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2446 ts->resp = SAS_TASK_COMPLETE; 2447 ts->stat = SAS_DEV_NO_RESPONSE; 2448 if (!t->uldd_task) { 2449 pm8001_handle_event(pm8001_ha, 2450 pm8001_dev, 2451 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2452 ts->resp = SAS_TASK_UNDELIVERED; 2453 ts->stat = SAS_QUEUE_FULL; 2454 spin_unlock_irqrestore(&circularQ->oq_lock, 2455 circularQ->lock_flags); 2456 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2457 spin_lock_irqsave(&circularQ->oq_lock, 2458 circularQ->lock_flags); 2459 return; 2460 } 2461 break; 2462 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2463 pm8001_dbg(pm8001_ha, IO, 2464 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2465 ts->resp = SAS_TASK_UNDELIVERED; 2466 ts->stat = SAS_OPEN_REJECT; 2467 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2468 if (!t->uldd_task) { 2469 pm8001_handle_event(pm8001_ha, 2470 pm8001_dev, 2471 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2472 ts->resp = SAS_TASK_UNDELIVERED; 2473 ts->stat = SAS_QUEUE_FULL; 2474 spin_unlock_irqrestore(&circularQ->oq_lock, 2475 circularQ->lock_flags); 2476 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2477 spin_lock_irqsave(&circularQ->oq_lock, 2478 circularQ->lock_flags); 2479 return; 2480 } 2481 break; 2482 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2483 pm8001_dbg(pm8001_ha, IO, 2484 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2485 ts->resp = SAS_TASK_COMPLETE; 2486 ts->stat = SAS_OPEN_REJECT; 2487 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2488 if (pm8001_dev) 2489 atomic_dec(&pm8001_dev->running_req); 2490 break; 2491 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2492 pm8001_dbg(pm8001_ha, IO, 2493 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2494 ts->resp = SAS_TASK_COMPLETE; 2495 ts->stat = SAS_DEV_NO_RESPONSE; 2496 if (!t->uldd_task) { 2497 pm8001_handle_event(pm8001_ha, 2498 pm8001_dev, 2499 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2500 ts->resp = SAS_TASK_UNDELIVERED; 2501 ts->stat = SAS_QUEUE_FULL; 2502 spin_unlock_irqrestore(&circularQ->oq_lock, 2503 circularQ->lock_flags); 2504 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2505 spin_lock_irqsave(&circularQ->oq_lock, 2506 circularQ->lock_flags); 2507 return; 2508 } 2509 break; 2510 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2511 pm8001_dbg(pm8001_ha, IO, 2512 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2513 ts->resp = SAS_TASK_COMPLETE; 2514 ts->stat = SAS_OPEN_REJECT; 2515 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2516 if (pm8001_dev) 2517 atomic_dec(&pm8001_dev->running_req); 2518 break; 2519 case IO_XFER_ERROR_NAK_RECEIVED: 2520 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2521 ts->resp = SAS_TASK_COMPLETE; 2522 ts->stat = SAS_NAK_R_ERR; 2523 if (pm8001_dev) 2524 atomic_dec(&pm8001_dev->running_req); 2525 break; 2526 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2527 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2528 ts->resp = SAS_TASK_COMPLETE; 2529 ts->stat = SAS_NAK_R_ERR; 2530 if (pm8001_dev) 2531 atomic_dec(&pm8001_dev->running_req); 2532 break; 2533 case IO_XFER_ERROR_DMA: 2534 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2535 ts->resp = SAS_TASK_COMPLETE; 2536 ts->stat = SAS_ABORTED_TASK; 2537 if (pm8001_dev) 2538 atomic_dec(&pm8001_dev->running_req); 2539 break; 2540 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2541 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2542 ts->resp = SAS_TASK_UNDELIVERED; 2543 ts->stat = SAS_DEV_NO_RESPONSE; 2544 if (pm8001_dev) 2545 atomic_dec(&pm8001_dev->running_req); 2546 break; 2547 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2548 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2549 ts->resp = SAS_TASK_COMPLETE; 2550 ts->stat = SAS_DATA_UNDERRUN; 2551 if (pm8001_dev) 2552 atomic_dec(&pm8001_dev->running_req); 2553 break; 2554 case IO_XFER_OPEN_RETRY_TIMEOUT: 2555 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2556 ts->resp = SAS_TASK_COMPLETE; 2557 ts->stat = SAS_OPEN_TO; 2558 if (pm8001_dev) 2559 atomic_dec(&pm8001_dev->running_req); 2560 break; 2561 case IO_PORT_IN_RESET: 2562 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2563 ts->resp = SAS_TASK_COMPLETE; 2564 ts->stat = SAS_DEV_NO_RESPONSE; 2565 if (pm8001_dev) 2566 atomic_dec(&pm8001_dev->running_req); 2567 break; 2568 case IO_DS_NON_OPERATIONAL: 2569 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2570 ts->resp = SAS_TASK_COMPLETE; 2571 ts->stat = SAS_DEV_NO_RESPONSE; 2572 if (!t->uldd_task) { 2573 pm8001_handle_event(pm8001_ha, pm8001_dev, 2574 IO_DS_NON_OPERATIONAL); 2575 ts->resp = SAS_TASK_UNDELIVERED; 2576 ts->stat = SAS_QUEUE_FULL; 2577 spin_unlock_irqrestore(&circularQ->oq_lock, 2578 circularQ->lock_flags); 2579 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2580 spin_lock_irqsave(&circularQ->oq_lock, 2581 circularQ->lock_flags); 2582 return; 2583 } 2584 break; 2585 case IO_DS_IN_RECOVERY: 2586 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2587 ts->resp = SAS_TASK_COMPLETE; 2588 ts->stat = SAS_DEV_NO_RESPONSE; 2589 if (pm8001_dev) 2590 atomic_dec(&pm8001_dev->running_req); 2591 break; 2592 case IO_DS_IN_ERROR: 2593 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2594 ts->resp = SAS_TASK_COMPLETE; 2595 ts->stat = SAS_DEV_NO_RESPONSE; 2596 if (!t->uldd_task) { 2597 pm8001_handle_event(pm8001_ha, pm8001_dev, 2598 IO_DS_IN_ERROR); 2599 ts->resp = SAS_TASK_UNDELIVERED; 2600 ts->stat = SAS_QUEUE_FULL; 2601 spin_unlock_irqrestore(&circularQ->oq_lock, 2602 circularQ->lock_flags); 2603 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2604 spin_lock_irqsave(&circularQ->oq_lock, 2605 circularQ->lock_flags); 2606 return; 2607 } 2608 break; 2609 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2610 pm8001_dbg(pm8001_ha, IO, 2611 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2612 ts->resp = SAS_TASK_COMPLETE; 2613 ts->stat = SAS_OPEN_REJECT; 2614 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2615 if (pm8001_dev) 2616 atomic_dec(&pm8001_dev->running_req); 2617 break; 2618 default: 2619 pm8001_dbg(pm8001_ha, DEVIO, 2620 "Unknown status device_id %u status 0x%x tag %d\n", 2621 pm8001_dev->device_id, status, tag); 2622 /* not allowed case. Therefore, return failed status */ 2623 ts->resp = SAS_TASK_COMPLETE; 2624 ts->stat = SAS_DEV_NO_RESPONSE; 2625 if (pm8001_dev) 2626 atomic_dec(&pm8001_dev->running_req); 2627 break; 2628 } 2629 spin_lock_irqsave(&t->task_state_lock, flags); 2630 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2631 t->task_state_flags |= SAS_TASK_STATE_DONE; 2632 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2633 spin_unlock_irqrestore(&t->task_state_lock, flags); 2634 pm8001_dbg(pm8001_ha, FAIL, 2635 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2636 t, status, ts->resp, ts->stat); 2637 pm8001_ccb_task_free(pm8001_ha, ccb); 2638 if (t->slow_task) 2639 complete(&t->slow_task->completion); 2640 } else { 2641 spin_unlock_irqrestore(&t->task_state_lock, flags); 2642 spin_unlock_irqrestore(&circularQ->oq_lock, 2643 circularQ->lock_flags); 2644 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2645 spin_lock_irqsave(&circularQ->oq_lock, 2646 circularQ->lock_flags); 2647 } 2648 } 2649 2650 /*See the comments for mpi_ssp_completion */ 2651 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, 2652 struct outbound_queue_table *circularQ, void *piomb) 2653 { 2654 struct sas_task *t; 2655 struct task_status_struct *ts; 2656 struct pm8001_ccb_info *ccb; 2657 struct pm8001_device *pm8001_dev; 2658 struct sata_event_resp *psataPayload = 2659 (struct sata_event_resp *)(piomb + 4); 2660 u32 event = le32_to_cpu(psataPayload->event); 2661 u32 tag = le32_to_cpu(psataPayload->tag); 2662 u32 port_id = le32_to_cpu(psataPayload->port_id); 2663 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2664 2665 if (event) 2666 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2667 2668 /* Check if this is NCQ error */ 2669 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2670 /* find device using device id */ 2671 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2672 /* send read log extension by aborting the link - libata does what we want */ 2673 if (pm8001_dev) 2674 pm8001_handle_event(pm8001_ha, 2675 pm8001_dev, 2676 IO_XFER_ERROR_ABORTED_NCQ_MODE); 2677 return; 2678 } 2679 2680 ccb = &pm8001_ha->ccb_info[tag]; 2681 t = ccb->task; 2682 pm8001_dev = ccb->device; 2683 if (unlikely(!t)) { 2684 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2685 ccb->ccb_tag); 2686 pm8001_ccb_free(pm8001_ha, ccb); 2687 return; 2688 } 2689 2690 if (unlikely(!t->lldd_task || !t->dev)) 2691 return; 2692 2693 ts = &t->task_status; 2694 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2695 port_id, tag, event); 2696 switch (event) { 2697 case IO_OVERFLOW: 2698 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2699 ts->resp = SAS_TASK_COMPLETE; 2700 ts->stat = SAS_DATA_OVERRUN; 2701 ts->residual = 0; 2702 break; 2703 case IO_XFER_ERROR_BREAK: 2704 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2705 ts->resp = SAS_TASK_COMPLETE; 2706 ts->stat = SAS_INTERRUPTED; 2707 break; 2708 case IO_XFER_ERROR_PHY_NOT_READY: 2709 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2710 ts->resp = SAS_TASK_COMPLETE; 2711 ts->stat = SAS_OPEN_REJECT; 2712 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2713 break; 2714 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2715 pm8001_dbg(pm8001_ha, IO, 2716 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2717 ts->resp = SAS_TASK_COMPLETE; 2718 ts->stat = SAS_OPEN_REJECT; 2719 ts->open_rej_reason = SAS_OREJ_EPROTO; 2720 break; 2721 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2722 pm8001_dbg(pm8001_ha, IO, 2723 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2724 ts->resp = SAS_TASK_COMPLETE; 2725 ts->stat = SAS_OPEN_REJECT; 2726 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2727 break; 2728 case IO_OPEN_CNX_ERROR_BREAK: 2729 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2730 ts->resp = SAS_TASK_COMPLETE; 2731 ts->stat = SAS_OPEN_REJECT; 2732 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2733 break; 2734 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2735 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2736 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2737 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2738 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2739 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2740 pm8001_dbg(pm8001_ha, FAIL, 2741 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2742 ts->resp = SAS_TASK_UNDELIVERED; 2743 ts->stat = SAS_DEV_NO_RESPONSE; 2744 if (!t->uldd_task) { 2745 pm8001_handle_event(pm8001_ha, 2746 pm8001_dev, 2747 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2748 ts->resp = SAS_TASK_COMPLETE; 2749 ts->stat = SAS_QUEUE_FULL; 2750 return; 2751 } 2752 break; 2753 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2754 pm8001_dbg(pm8001_ha, IO, 2755 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2756 ts->resp = SAS_TASK_UNDELIVERED; 2757 ts->stat = SAS_OPEN_REJECT; 2758 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2759 break; 2760 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2761 pm8001_dbg(pm8001_ha, IO, 2762 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2763 ts->resp = SAS_TASK_COMPLETE; 2764 ts->stat = SAS_OPEN_REJECT; 2765 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2766 break; 2767 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2768 pm8001_dbg(pm8001_ha, IO, 2769 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2770 ts->resp = SAS_TASK_COMPLETE; 2771 ts->stat = SAS_OPEN_REJECT; 2772 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2773 break; 2774 case IO_XFER_ERROR_NAK_RECEIVED: 2775 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2776 ts->resp = SAS_TASK_COMPLETE; 2777 ts->stat = SAS_NAK_R_ERR; 2778 break; 2779 case IO_XFER_ERROR_PEER_ABORTED: 2780 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2781 ts->resp = SAS_TASK_COMPLETE; 2782 ts->stat = SAS_NAK_R_ERR; 2783 break; 2784 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2785 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2786 ts->resp = SAS_TASK_COMPLETE; 2787 ts->stat = SAS_DATA_UNDERRUN; 2788 break; 2789 case IO_XFER_OPEN_RETRY_TIMEOUT: 2790 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2791 ts->resp = SAS_TASK_COMPLETE; 2792 ts->stat = SAS_OPEN_TO; 2793 break; 2794 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2795 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2796 ts->resp = SAS_TASK_COMPLETE; 2797 ts->stat = SAS_OPEN_TO; 2798 break; 2799 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2800 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2801 ts->resp = SAS_TASK_COMPLETE; 2802 ts->stat = SAS_OPEN_TO; 2803 break; 2804 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2805 pm8001_dbg(pm8001_ha, IO, 2806 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2807 ts->resp = SAS_TASK_COMPLETE; 2808 ts->stat = SAS_OPEN_TO; 2809 break; 2810 case IO_XFER_ERROR_OFFSET_MISMATCH: 2811 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2812 ts->resp = SAS_TASK_COMPLETE; 2813 ts->stat = SAS_OPEN_TO; 2814 break; 2815 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2816 pm8001_dbg(pm8001_ha, IO, 2817 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2818 ts->resp = SAS_TASK_COMPLETE; 2819 ts->stat = SAS_OPEN_TO; 2820 break; 2821 case IO_XFER_CMD_FRAME_ISSUED: 2822 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2823 break; 2824 case IO_XFER_PIO_SETUP_ERROR: 2825 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2826 ts->resp = SAS_TASK_COMPLETE; 2827 ts->stat = SAS_OPEN_TO; 2828 break; 2829 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2830 pm8001_dbg(pm8001_ha, FAIL, 2831 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2832 /* TBC: used default set values */ 2833 ts->resp = SAS_TASK_COMPLETE; 2834 ts->stat = SAS_OPEN_TO; 2835 break; 2836 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2837 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2838 /* TBC: used default set values */ 2839 ts->resp = SAS_TASK_COMPLETE; 2840 ts->stat = SAS_OPEN_TO; 2841 break; 2842 default: 2843 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2844 /* not allowed case. Therefore, return failed status */ 2845 ts->resp = SAS_TASK_COMPLETE; 2846 ts->stat = SAS_OPEN_TO; 2847 break; 2848 } 2849 } 2850 2851 /*See the comments for mpi_ssp_completion */ 2852 static void 2853 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2854 { 2855 u32 param, i; 2856 struct sas_task *t; 2857 struct pm8001_ccb_info *ccb; 2858 unsigned long flags; 2859 u32 status; 2860 u32 tag; 2861 struct smp_completion_resp *psmpPayload; 2862 struct task_status_struct *ts; 2863 struct pm8001_device *pm8001_dev; 2864 2865 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2866 status = le32_to_cpu(psmpPayload->status); 2867 tag = le32_to_cpu(psmpPayload->tag); 2868 2869 ccb = &pm8001_ha->ccb_info[tag]; 2870 param = le32_to_cpu(psmpPayload->param); 2871 t = ccb->task; 2872 ts = &t->task_status; 2873 pm8001_dev = ccb->device; 2874 if (status) 2875 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2876 if (unlikely(!t || !t->lldd_task || !t->dev)) 2877 return; 2878 2879 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 2880 2881 switch (status) { 2882 2883 case IO_SUCCESS: 2884 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2885 ts->resp = SAS_TASK_COMPLETE; 2886 ts->stat = SAS_SAM_STAT_GOOD; 2887 if (pm8001_dev) 2888 atomic_dec(&pm8001_dev->running_req); 2889 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2890 struct scatterlist *sg_resp = &t->smp_task.smp_resp; 2891 u8 *payload; 2892 void *to; 2893 2894 pm8001_dbg(pm8001_ha, IO, 2895 "DIRECT RESPONSE Length:%d\n", 2896 param); 2897 to = kmap_atomic(sg_page(sg_resp)); 2898 payload = to + sg_resp->offset; 2899 for (i = 0; i < param; i++) { 2900 *(payload + i) = psmpPayload->_r_a[i]; 2901 pm8001_dbg(pm8001_ha, IO, 2902 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2903 i, *(payload + i), 2904 psmpPayload->_r_a[i]); 2905 } 2906 kunmap_atomic(to); 2907 } 2908 break; 2909 case IO_ABORTED: 2910 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 2911 ts->resp = SAS_TASK_COMPLETE; 2912 ts->stat = SAS_ABORTED_TASK; 2913 if (pm8001_dev) 2914 atomic_dec(&pm8001_dev->running_req); 2915 break; 2916 case IO_OVERFLOW: 2917 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2918 ts->resp = SAS_TASK_COMPLETE; 2919 ts->stat = SAS_DATA_OVERRUN; 2920 ts->residual = 0; 2921 if (pm8001_dev) 2922 atomic_dec(&pm8001_dev->running_req); 2923 break; 2924 case IO_NO_DEVICE: 2925 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2926 ts->resp = SAS_TASK_COMPLETE; 2927 ts->stat = SAS_PHY_DOWN; 2928 break; 2929 case IO_ERROR_HW_TIMEOUT: 2930 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 2931 ts->resp = SAS_TASK_COMPLETE; 2932 ts->stat = SAS_SAM_STAT_BUSY; 2933 break; 2934 case IO_XFER_ERROR_BREAK: 2935 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2936 ts->resp = SAS_TASK_COMPLETE; 2937 ts->stat = SAS_SAM_STAT_BUSY; 2938 break; 2939 case IO_XFER_ERROR_PHY_NOT_READY: 2940 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2941 ts->resp = SAS_TASK_COMPLETE; 2942 ts->stat = SAS_SAM_STAT_BUSY; 2943 break; 2944 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2945 pm8001_dbg(pm8001_ha, IO, 2946 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2947 ts->resp = SAS_TASK_COMPLETE; 2948 ts->stat = SAS_OPEN_REJECT; 2949 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2950 break; 2951 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2952 pm8001_dbg(pm8001_ha, IO, 2953 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2954 ts->resp = SAS_TASK_COMPLETE; 2955 ts->stat = SAS_OPEN_REJECT; 2956 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2957 break; 2958 case IO_OPEN_CNX_ERROR_BREAK: 2959 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2960 ts->resp = SAS_TASK_COMPLETE; 2961 ts->stat = SAS_OPEN_REJECT; 2962 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2963 break; 2964 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2965 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2966 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2967 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2968 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2969 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2970 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2971 ts->resp = SAS_TASK_COMPLETE; 2972 ts->stat = SAS_OPEN_REJECT; 2973 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2974 pm8001_handle_event(pm8001_ha, 2975 pm8001_dev, 2976 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2977 break; 2978 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2979 pm8001_dbg(pm8001_ha, IO, 2980 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2981 ts->resp = SAS_TASK_COMPLETE; 2982 ts->stat = SAS_OPEN_REJECT; 2983 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2984 break; 2985 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2986 pm8001_dbg(pm8001_ha, IO, 2987 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2988 ts->resp = SAS_TASK_COMPLETE; 2989 ts->stat = SAS_OPEN_REJECT; 2990 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2991 break; 2992 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2993 pm8001_dbg(pm8001_ha, IO, 2994 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2995 ts->resp = SAS_TASK_COMPLETE; 2996 ts->stat = SAS_OPEN_REJECT; 2997 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2998 break; 2999 case IO_XFER_ERROR_RX_FRAME: 3000 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3001 ts->resp = SAS_TASK_COMPLETE; 3002 ts->stat = SAS_DEV_NO_RESPONSE; 3003 break; 3004 case IO_XFER_OPEN_RETRY_TIMEOUT: 3005 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3006 ts->resp = SAS_TASK_COMPLETE; 3007 ts->stat = SAS_OPEN_REJECT; 3008 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3009 break; 3010 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3011 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3012 ts->resp = SAS_TASK_COMPLETE; 3013 ts->stat = SAS_QUEUE_FULL; 3014 break; 3015 case IO_PORT_IN_RESET: 3016 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3017 ts->resp = SAS_TASK_COMPLETE; 3018 ts->stat = SAS_OPEN_REJECT; 3019 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3020 break; 3021 case IO_DS_NON_OPERATIONAL: 3022 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3023 ts->resp = SAS_TASK_COMPLETE; 3024 ts->stat = SAS_DEV_NO_RESPONSE; 3025 break; 3026 case IO_DS_IN_RECOVERY: 3027 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3028 ts->resp = SAS_TASK_COMPLETE; 3029 ts->stat = SAS_OPEN_REJECT; 3030 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3031 break; 3032 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3033 pm8001_dbg(pm8001_ha, IO, 3034 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3035 ts->resp = SAS_TASK_COMPLETE; 3036 ts->stat = SAS_OPEN_REJECT; 3037 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3038 break; 3039 default: 3040 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3041 ts->resp = SAS_TASK_COMPLETE; 3042 ts->stat = SAS_DEV_NO_RESPONSE; 3043 /* not allowed case. Therefore, return failed status */ 3044 break; 3045 } 3046 spin_lock_irqsave(&t->task_state_lock, flags); 3047 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3048 t->task_state_flags |= SAS_TASK_STATE_DONE; 3049 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3050 spin_unlock_irqrestore(&t->task_state_lock, flags); 3051 pm8001_dbg(pm8001_ha, FAIL, 3052 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3053 t, status, ts->resp, ts->stat); 3054 pm8001_ccb_task_free(pm8001_ha, ccb); 3055 } else { 3056 spin_unlock_irqrestore(&t->task_state_lock, flags); 3057 pm8001_ccb_task_free(pm8001_ha, ccb); 3058 mb();/* in order to force CPU ordering */ 3059 t->task_done(t); 3060 } 3061 } 3062 3063 /** 3064 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW. 3065 * @pm8001_ha: our hba card information 3066 * @Qnum: the outbound queue message number. 3067 * @SEA: source of event to ack 3068 * @port_id: port id. 3069 * @phyId: phy id. 3070 * @param0: parameter 0. 3071 * @param1: parameter 1. 3072 */ 3073 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3074 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3075 { 3076 struct hw_event_ack_req payload; 3077 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3078 3079 memset((u8 *)&payload, 0, sizeof(payload)); 3080 payload.tag = cpu_to_le32(1); 3081 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3082 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3083 payload.param0 = cpu_to_le32(param0); 3084 payload.param1 = cpu_to_le32(param1); 3085 3086 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, 3087 sizeof(payload), 0); 3088 } 3089 3090 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3091 u32 phyId, u32 phy_op); 3092 3093 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3094 void *piomb) 3095 { 3096 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3097 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3098 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3099 u32 lr_status_evt_portid = 3100 le32_to_cpu(pPayload->lr_status_evt_portid); 3101 u8 deviceType = pPayload->sas_identify.dev_type; 3102 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3103 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3104 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3105 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3106 3107 if (deviceType == SAS_END_DEVICE) { 3108 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3109 PHY_NOTIFY_ENABLE_SPINUP); 3110 } 3111 3112 port->wide_port_phymap |= (1U << phy_id); 3113 pm8001_get_lrate_mode(phy, link_rate); 3114 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3115 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3116 phy->phy_attached = 1; 3117 } 3118 3119 /** 3120 * hw_event_sas_phy_up - FW tells me a SAS phy up event. 3121 * @pm8001_ha: our hba card information 3122 * @piomb: IO message buffer 3123 */ 3124 static void 3125 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3126 { 3127 struct hw_event_resp *pPayload = 3128 (struct hw_event_resp *)(piomb + 4); 3129 u32 lr_status_evt_portid = 3130 le32_to_cpu(pPayload->lr_status_evt_portid); 3131 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3132 3133 u8 link_rate = 3134 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3135 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3136 u8 phy_id = 3137 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3138 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3139 3140 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3141 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3142 unsigned long flags; 3143 u8 deviceType = pPayload->sas_identify.dev_type; 3144 phy->port = port; 3145 port->port_id = port_id; 3146 port->port_state = portstate; 3147 port->wide_port_phymap |= (1U << phy_id); 3148 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3149 pm8001_dbg(pm8001_ha, MSG, 3150 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3151 port_id, phy_id, link_rate, portstate, deviceType); 3152 3153 switch (deviceType) { 3154 case SAS_PHY_UNUSED: 3155 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3156 break; 3157 case SAS_END_DEVICE: 3158 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3159 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3160 PHY_NOTIFY_ENABLE_SPINUP); 3161 port->port_attached = 1; 3162 pm8001_get_lrate_mode(phy, link_rate); 3163 break; 3164 case SAS_EDGE_EXPANDER_DEVICE: 3165 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3166 port->port_attached = 1; 3167 pm8001_get_lrate_mode(phy, link_rate); 3168 break; 3169 case SAS_FANOUT_EXPANDER_DEVICE: 3170 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3171 port->port_attached = 1; 3172 pm8001_get_lrate_mode(phy, link_rate); 3173 break; 3174 default: 3175 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3176 deviceType); 3177 break; 3178 } 3179 phy->phy_type |= PORT_TYPE_SAS; 3180 phy->identify.device_type = deviceType; 3181 phy->phy_attached = 1; 3182 if (phy->identify.device_type == SAS_END_DEVICE) 3183 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3184 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3185 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3186 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3187 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3188 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3189 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3190 sizeof(struct sas_identify_frame)-4); 3191 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3192 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3193 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3194 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3195 mdelay(200); /* delay a moment to wait for disk to spin up */ 3196 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3197 } 3198 3199 /** 3200 * hw_event_sata_phy_up - FW tells me a SATA phy up event. 3201 * @pm8001_ha: our hba card information 3202 * @piomb: IO message buffer 3203 */ 3204 static void 3205 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3206 { 3207 struct hw_event_resp *pPayload = 3208 (struct hw_event_resp *)(piomb + 4); 3209 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3210 u32 lr_status_evt_portid = 3211 le32_to_cpu(pPayload->lr_status_evt_portid); 3212 u8 link_rate = 3213 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3214 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3215 u8 phy_id = 3216 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3217 3218 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3219 3220 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3221 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3222 unsigned long flags; 3223 pm8001_dbg(pm8001_ha, EVENT, 3224 "HW_EVENT_SATA_PHY_UP phyid:%#x port_id:%#x link_rate:%d portstate:%#x\n", 3225 phy_id, port_id, link_rate, portstate); 3226 3227 phy->port = port; 3228 port->port_id = port_id; 3229 port->port_state = portstate; 3230 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3231 port->port_attached = 1; 3232 pm8001_get_lrate_mode(phy, link_rate); 3233 phy->phy_type |= PORT_TYPE_SATA; 3234 phy->phy_attached = 1; 3235 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3236 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3237 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3238 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3239 sizeof(struct dev_to_host_fis)); 3240 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3241 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3242 phy->identify.device_type = SAS_SATA_DEV; 3243 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3244 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3245 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3246 } 3247 3248 /** 3249 * hw_event_phy_down - we should notify the libsas the phy is down. 3250 * @pm8001_ha: our hba card information 3251 * @piomb: IO message buffer 3252 */ 3253 static void 3254 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3255 { 3256 struct hw_event_resp *pPayload = 3257 (struct hw_event_resp *)(piomb + 4); 3258 3259 u32 lr_status_evt_portid = 3260 le32_to_cpu(pPayload->lr_status_evt_portid); 3261 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3262 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3263 u8 phy_id = 3264 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3265 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3266 3267 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3268 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3269 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3270 port->port_state = portstate; 3271 phy->identify.device_type = 0; 3272 phy->phy_attached = 0; 3273 switch (portstate) { 3274 case PORT_VALID: 3275 pm8001_dbg(pm8001_ha, EVENT, 3276 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_VALID\n", 3277 phy_id, port_id); 3278 break; 3279 case PORT_INVALID: 3280 pm8001_dbg(pm8001_ha, EVENT, 3281 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_INVALID\n", 3282 phy_id, port_id); 3283 pm8001_dbg(pm8001_ha, MSG, 3284 " Last phy Down and port invalid\n"); 3285 if (port_sata) { 3286 phy->phy_type = 0; 3287 port->port_attached = 0; 3288 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3289 port_id, phy_id, 0, 0); 3290 } 3291 sas_phy_disconnected(&phy->sas_phy); 3292 break; 3293 case PORT_IN_RESET: 3294 pm8001_dbg(pm8001_ha, EVENT, 3295 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_IN_RESET\n", 3296 phy_id, port_id); 3297 break; 3298 case PORT_NOT_ESTABLISHED: 3299 pm8001_dbg(pm8001_ha, EVENT, 3300 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_NOT_ESTABLISHED\n", 3301 phy_id, port_id); 3302 port->port_attached = 0; 3303 break; 3304 case PORT_LOSTCOMM: 3305 pm8001_dbg(pm8001_ha, EVENT, 3306 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_LOSTCOMM\n", 3307 phy_id, port_id); 3308 pm8001_dbg(pm8001_ha, MSG, " Last phy Down and port invalid\n"); 3309 if (port_sata) { 3310 port->port_attached = 0; 3311 phy->phy_type = 0; 3312 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3313 port_id, phy_id, 0, 0); 3314 } 3315 sas_phy_disconnected(&phy->sas_phy); 3316 break; 3317 default: 3318 port->port_attached = 0; 3319 pm8001_dbg(pm8001_ha, EVENT, 3320 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate:%#x\n", 3321 phy_id, port_id, portstate); 3322 break; 3323 3324 } 3325 if (port_sata && (portstate != PORT_IN_RESET)) 3326 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3327 GFP_ATOMIC); 3328 } 3329 3330 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3331 { 3332 struct phy_start_resp *pPayload = 3333 (struct phy_start_resp *)(piomb + 4); 3334 u32 status = 3335 le32_to_cpu(pPayload->status); 3336 u32 phy_id = 3337 le32_to_cpu(pPayload->phyid) & 0xFF; 3338 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3339 3340 pm8001_dbg(pm8001_ha, INIT, 3341 "phy start resp status:0x%x, phyid:0x%x\n", 3342 status, phy_id); 3343 if (status == 0) 3344 phy->phy_state = PHY_LINK_DOWN; 3345 3346 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3347 phy->enable_completion != NULL) { 3348 complete(phy->enable_completion); 3349 phy->enable_completion = NULL; 3350 } 3351 return 0; 3352 3353 } 3354 3355 /** 3356 * mpi_thermal_hw_event - a thermal hw event has come. 3357 * @pm8001_ha: our hba card information 3358 * @piomb: IO message buffer 3359 */ 3360 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3361 { 3362 struct thermal_hw_event *pPayload = 3363 (struct thermal_hw_event *)(piomb + 4); 3364 3365 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3366 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3367 3368 if (thermal_event & 0x40) { 3369 pm8001_dbg(pm8001_ha, IO, 3370 "Thermal Event: Local high temperature violated!\n"); 3371 pm8001_dbg(pm8001_ha, IO, 3372 "Thermal Event: Measured local high temperature %d\n", 3373 ((rht_lht & 0xFF00) >> 8)); 3374 } 3375 if (thermal_event & 0x10) { 3376 pm8001_dbg(pm8001_ha, IO, 3377 "Thermal Event: Remote high temperature violated!\n"); 3378 pm8001_dbg(pm8001_ha, IO, 3379 "Thermal Event: Measured remote high temperature %d\n", 3380 ((rht_lht & 0xFF000000) >> 24)); 3381 } 3382 return 0; 3383 } 3384 3385 /** 3386 * mpi_hw_event - The hw event has come. 3387 * @pm8001_ha: our hba card information 3388 * @piomb: IO message buffer 3389 */ 3390 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3391 { 3392 unsigned long flags, i; 3393 struct hw_event_resp *pPayload = 3394 (struct hw_event_resp *)(piomb + 4); 3395 u32 lr_status_evt_portid = 3396 le32_to_cpu(pPayload->lr_status_evt_portid); 3397 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3398 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3399 u8 phy_id = 3400 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3401 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3402 u16 eventType = 3403 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3404 u8 status = 3405 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3406 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3407 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3408 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3409 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3410 pm8001_dbg(pm8001_ha, DEV, 3411 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3412 port_id, phy_id, eventType, status); 3413 3414 switch (eventType) { 3415 3416 case HW_EVENT_SAS_PHY_UP: 3417 pm8001_dbg(pm8001_ha, EVENT, 3418 "HW_EVENT_SAS_PHY_UP phyid:%#x port_id:%#x\n", 3419 phy_id, port_id); 3420 hw_event_sas_phy_up(pm8001_ha, piomb); 3421 break; 3422 case HW_EVENT_SATA_PHY_UP: 3423 hw_event_sata_phy_up(pm8001_ha, piomb); 3424 break; 3425 case HW_EVENT_SATA_SPINUP_HOLD: 3426 pm8001_dbg(pm8001_ha, EVENT, 3427 "HW_EVENT_SATA_SPINUP_HOLD phyid:%#x port_id:%#x\n", 3428 phy_id, port_id); 3429 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3430 GFP_ATOMIC); 3431 break; 3432 case HW_EVENT_PHY_DOWN: 3433 hw_event_phy_down(pm8001_ha, piomb); 3434 phy->phy_state = PHY_LINK_DISABLE; 3435 break; 3436 case HW_EVENT_PORT_INVALID: 3437 pm8001_dbg(pm8001_ha, EVENT, 3438 "HW_EVENT_PORT_INVALID phyid:%#x port_id:%#x\n", 3439 phy_id, port_id); 3440 sas_phy_disconnected(sas_phy); 3441 phy->phy_attached = 0; 3442 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3443 GFP_ATOMIC); 3444 break; 3445 /* the broadcast change primitive received, tell the LIBSAS this event 3446 to revalidate the sas domain*/ 3447 case HW_EVENT_BROADCAST_CHANGE: 3448 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3449 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3450 port_id, phy_id, 1, 0); 3451 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3452 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3453 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3454 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3455 GFP_ATOMIC); 3456 break; 3457 case HW_EVENT_PHY_ERROR: 3458 pm8001_dbg(pm8001_ha, EVENT, 3459 "HW_EVENT_PHY_ERROR phyid:%#x port_id:%#x\n", 3460 phy_id, port_id); 3461 sas_phy_disconnected(&phy->sas_phy); 3462 phy->phy_attached = 0; 3463 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3464 break; 3465 case HW_EVENT_BROADCAST_EXP: 3466 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3467 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3468 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3469 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3470 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3471 GFP_ATOMIC); 3472 break; 3473 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3474 pm8001_dbg(pm8001_ha, EVENT, 3475 "HW_EVENT_LINK_ERR_INVALID_DWORD phyid:%#x port_id:%#x\n", 3476 phy_id, port_id); 3477 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3478 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3479 break; 3480 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3481 pm8001_dbg(pm8001_ha, EVENT, 3482 "HW_EVENT_LINK_ERR_DISPARITY_ERROR phyid:%#x port_id:%#x\n", 3483 phy_id, port_id); 3484 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3485 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3486 port_id, phy_id, 0, 0); 3487 break; 3488 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3489 pm8001_dbg(pm8001_ha, EVENT, 3490 "HW_EVENT_LINK_ERR_CODE_VIOLATION phyid:%#x port_id:%#x\n", 3491 phy_id, port_id); 3492 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3493 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3494 port_id, phy_id, 0, 0); 3495 break; 3496 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3497 pm8001_dbg(pm8001_ha, EVENT, 3498 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH phyid:%#x port_id:%#x\n", 3499 phy_id, port_id); 3500 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3501 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3502 port_id, phy_id, 0, 0); 3503 break; 3504 case HW_EVENT_MALFUNCTION: 3505 pm8001_dbg(pm8001_ha, EVENT, 3506 "HW_EVENT_MALFUNCTION phyid:%#x\n", phy_id); 3507 break; 3508 case HW_EVENT_BROADCAST_SES: 3509 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3510 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3511 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3512 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3513 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3514 GFP_ATOMIC); 3515 break; 3516 case HW_EVENT_INBOUND_CRC_ERROR: 3517 pm8001_dbg(pm8001_ha, EVENT, 3518 "HW_EVENT_INBOUND_CRC_ERROR phyid:%#x port_id:%#x\n", 3519 phy_id, port_id); 3520 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3521 HW_EVENT_INBOUND_CRC_ERROR, 3522 port_id, phy_id, 0, 0); 3523 break; 3524 case HW_EVENT_HARD_RESET_RECEIVED: 3525 pm8001_dbg(pm8001_ha, EVENT, 3526 "HW_EVENT_HARD_RESET_RECEIVED phyid:%#x\n", phy_id); 3527 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3528 break; 3529 case HW_EVENT_ID_FRAME_TIMEOUT: 3530 pm8001_dbg(pm8001_ha, EVENT, 3531 "HW_EVENT_ID_FRAME_TIMEOUT phyid:%#x\n", phy_id); 3532 sas_phy_disconnected(sas_phy); 3533 phy->phy_attached = 0; 3534 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3535 GFP_ATOMIC); 3536 break; 3537 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3538 pm8001_dbg(pm8001_ha, EVENT, 3539 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED phyid:%#x port_id:%#x\n", 3540 phy_id, port_id); 3541 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3542 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3543 port_id, phy_id, 0, 0); 3544 sas_phy_disconnected(sas_phy); 3545 phy->phy_attached = 0; 3546 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3547 GFP_ATOMIC); 3548 break; 3549 case HW_EVENT_PORT_RESET_TIMER_TMO: 3550 pm8001_dbg(pm8001_ha, EVENT, 3551 "HW_EVENT_PORT_RESET_TIMER_TMO phyid:%#x port_id:%#x portstate:%#x\n", 3552 phy_id, port_id, portstate); 3553 if (!pm8001_ha->phy[phy_id].reset_completion) { 3554 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3555 port_id, phy_id, 0, 0); 3556 } 3557 sas_phy_disconnected(sas_phy); 3558 phy->phy_attached = 0; 3559 port->port_state = portstate; 3560 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3561 GFP_ATOMIC); 3562 if (pm8001_ha->phy[phy_id].reset_completion) { 3563 pm8001_ha->phy[phy_id].port_reset_status = 3564 PORT_RESET_TMO; 3565 complete(pm8001_ha->phy[phy_id].reset_completion); 3566 pm8001_ha->phy[phy_id].reset_completion = NULL; 3567 } 3568 break; 3569 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3570 pm8001_dbg(pm8001_ha, EVENT, 3571 "HW_EVENT_PORT_RECOVERY_TIMER_TMO phyid:%#x port_id:%#x\n", 3572 phy_id, port_id); 3573 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3574 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3575 port_id, phy_id, 0, 0); 3576 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3577 if (port->wide_port_phymap & (1 << i)) { 3578 phy = &pm8001_ha->phy[i]; 3579 sas_notify_phy_event(&phy->sas_phy, 3580 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 3581 port->wide_port_phymap &= ~(1 << i); 3582 } 3583 } 3584 break; 3585 case HW_EVENT_PORT_RECOVER: 3586 pm8001_dbg(pm8001_ha, EVENT, 3587 "HW_EVENT_PORT_RECOVER phyid:%#x port_id:%#x\n", 3588 phy_id, port_id); 3589 hw_event_port_recover(pm8001_ha, piomb); 3590 break; 3591 case HW_EVENT_PORT_RESET_COMPLETE: 3592 pm8001_dbg(pm8001_ha, EVENT, 3593 "HW_EVENT_PORT_RESET_COMPLETE phyid:%#x port_id:%#x portstate:%#x\n", 3594 phy_id, port_id, portstate); 3595 if (pm8001_ha->phy[phy_id].reset_completion) { 3596 pm8001_ha->phy[phy_id].port_reset_status = 3597 PORT_RESET_SUCCESS; 3598 complete(pm8001_ha->phy[phy_id].reset_completion); 3599 pm8001_ha->phy[phy_id].reset_completion = NULL; 3600 } 3601 phy->phy_attached = 1; 3602 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3603 port->port_state = portstate; 3604 break; 3605 case EVENT_BROADCAST_ASYNCH_EVENT: 3606 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3607 break; 3608 default: 3609 pm8001_dbg(pm8001_ha, DEVIO, 3610 "Unknown event portid:%d phyid:%d event:0x%x status:0x%x\n", 3611 port_id, phy_id, eventType, status); 3612 break; 3613 } 3614 return 0; 3615 } 3616 3617 /** 3618 * mpi_phy_stop_resp - SPCv specific 3619 * @pm8001_ha: our hba card information 3620 * @piomb: IO message buffer 3621 */ 3622 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3623 { 3624 struct phy_stop_resp *pPayload = 3625 (struct phy_stop_resp *)(piomb + 4); 3626 u32 status = 3627 le32_to_cpu(pPayload->status); 3628 u32 phyid = 3629 le32_to_cpu(pPayload->phyid) & 0xFF; 3630 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3631 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 3632 phyid, status); 3633 if (status == PHY_STOP_SUCCESS || 3634 status == PHY_STOP_ERR_DEVICE_ATTACHED) { 3635 phy->phy_state = PHY_LINK_DISABLE; 3636 phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED; 3637 phy->sas_phy.linkrate = SAS_PHY_DISABLED; 3638 } 3639 3640 return 0; 3641 } 3642 3643 /** 3644 * mpi_set_controller_config_resp - SPCv specific 3645 * @pm8001_ha: our hba card information 3646 * @piomb: IO message buffer 3647 */ 3648 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3649 void *piomb) 3650 { 3651 struct set_ctrl_cfg_resp *pPayload = 3652 (struct set_ctrl_cfg_resp *)(piomb + 4); 3653 u32 status = le32_to_cpu(pPayload->status); 3654 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3655 u32 tag = le32_to_cpu(pPayload->tag); 3656 3657 pm8001_dbg(pm8001_ha, MSG, 3658 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3659 status, err_qlfr_pgcd); 3660 pm8001_tag_free(pm8001_ha, tag); 3661 3662 return 0; 3663 } 3664 3665 /** 3666 * mpi_get_controller_config_resp - SPCv specific 3667 * @pm8001_ha: our hba card information 3668 * @piomb: IO message buffer 3669 */ 3670 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3671 void *piomb) 3672 { 3673 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3674 3675 return 0; 3676 } 3677 3678 /** 3679 * mpi_get_phy_profile_resp - SPCv specific 3680 * @pm8001_ha: our hba card information 3681 * @piomb: IO message buffer 3682 */ 3683 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3684 void *piomb) 3685 { 3686 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3687 3688 return 0; 3689 } 3690 3691 /** 3692 * mpi_flash_op_ext_resp - SPCv specific 3693 * @pm8001_ha: our hba card information 3694 * @piomb: IO message buffer 3695 */ 3696 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3697 { 3698 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3699 3700 return 0; 3701 } 3702 3703 /** 3704 * mpi_set_phy_profile_resp - SPCv specific 3705 * @pm8001_ha: our hba card information 3706 * @piomb: IO message buffer 3707 */ 3708 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3709 void *piomb) 3710 { 3711 u32 tag; 3712 u8 page_code; 3713 int rc = 0; 3714 struct set_phy_profile_resp *pPayload = 3715 (struct set_phy_profile_resp *)(piomb + 4); 3716 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3717 u32 status = le32_to_cpu(pPayload->status); 3718 3719 tag = le32_to_cpu(pPayload->tag); 3720 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3721 if (status) { 3722 /* status is FAILED */ 3723 pm8001_dbg(pm8001_ha, FAIL, 3724 "PhyProfile command failed with status 0x%08X\n", 3725 status); 3726 rc = -1; 3727 } else { 3728 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3729 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3730 page_code); 3731 rc = -1; 3732 } 3733 } 3734 pm8001_tag_free(pm8001_ha, tag); 3735 return rc; 3736 } 3737 3738 /** 3739 * mpi_kek_management_resp - SPCv specific 3740 * @pm8001_ha: our hba card information 3741 * @piomb: IO message buffer 3742 */ 3743 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3744 void *piomb) 3745 { 3746 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3747 3748 u32 status = le32_to_cpu(pPayload->status); 3749 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3750 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3751 3752 pm8001_dbg(pm8001_ha, MSG, 3753 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3754 status, kidx_new_curr_ksop, err_qlfr); 3755 3756 return 0; 3757 } 3758 3759 /** 3760 * mpi_dek_management_resp - SPCv specific 3761 * @pm8001_ha: our hba card information 3762 * @piomb: IO message buffer 3763 */ 3764 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3765 void *piomb) 3766 { 3767 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3768 3769 return 0; 3770 } 3771 3772 /** 3773 * ssp_coalesced_comp_resp - SPCv specific 3774 * @pm8001_ha: our hba card information 3775 * @piomb: IO message buffer 3776 */ 3777 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3778 void *piomb) 3779 { 3780 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3781 3782 return 0; 3783 } 3784 3785 /** 3786 * process_one_iomb - process one outbound Queue memory block 3787 * @pm8001_ha: our hba card information 3788 * @circularQ: outbound circular queue 3789 * @piomb: IO message buffer 3790 */ 3791 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, 3792 struct outbound_queue_table *circularQ, void *piomb) 3793 { 3794 __le32 pHeader = *(__le32 *)piomb; 3795 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3796 3797 switch (opc) { 3798 case OPC_OUB_ECHO: 3799 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3800 break; 3801 case OPC_OUB_HW_EVENT: 3802 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3803 mpi_hw_event(pm8001_ha, piomb); 3804 break; 3805 case OPC_OUB_THERM_HW_EVENT: 3806 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3807 mpi_thermal_hw_event(pm8001_ha, piomb); 3808 break; 3809 case OPC_OUB_SSP_COMP: 3810 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3811 mpi_ssp_completion(pm8001_ha, piomb); 3812 break; 3813 case OPC_OUB_SMP_COMP: 3814 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3815 mpi_smp_completion(pm8001_ha, piomb); 3816 break; 3817 case OPC_OUB_LOCAL_PHY_CNTRL: 3818 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3819 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3820 break; 3821 case OPC_OUB_DEV_REGIST: 3822 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3823 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3824 break; 3825 case OPC_OUB_DEREG_DEV: 3826 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3827 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3828 break; 3829 case OPC_OUB_GET_DEV_HANDLE: 3830 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3831 break; 3832 case OPC_OUB_SATA_COMP: 3833 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3834 mpi_sata_completion(pm8001_ha, circularQ, piomb); 3835 break; 3836 case OPC_OUB_SATA_EVENT: 3837 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3838 mpi_sata_event(pm8001_ha, circularQ, piomb); 3839 break; 3840 case OPC_OUB_SSP_EVENT: 3841 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3842 mpi_ssp_event(pm8001_ha, piomb); 3843 break; 3844 case OPC_OUB_DEV_HANDLE_ARRIV: 3845 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3846 /*This is for target*/ 3847 break; 3848 case OPC_OUB_SSP_RECV_EVENT: 3849 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3850 /*This is for target*/ 3851 break; 3852 case OPC_OUB_FW_FLASH_UPDATE: 3853 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3854 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3855 break; 3856 case OPC_OUB_GPIO_RESPONSE: 3857 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3858 break; 3859 case OPC_OUB_GPIO_EVENT: 3860 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3861 break; 3862 case OPC_OUB_GENERAL_EVENT: 3863 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3864 pm8001_mpi_general_event(pm8001_ha, piomb); 3865 break; 3866 case OPC_OUB_SSP_ABORT_RSP: 3867 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3868 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3869 break; 3870 case OPC_OUB_SATA_ABORT_RSP: 3871 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3872 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3873 break; 3874 case OPC_OUB_SAS_DIAG_MODE_START_END: 3875 pm8001_dbg(pm8001_ha, MSG, 3876 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3877 break; 3878 case OPC_OUB_SAS_DIAG_EXECUTE: 3879 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3880 break; 3881 case OPC_OUB_GET_TIME_STAMP: 3882 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3883 break; 3884 case OPC_OUB_SAS_HW_EVENT_ACK: 3885 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3886 break; 3887 case OPC_OUB_PORT_CONTROL: 3888 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3889 break; 3890 case OPC_OUB_SMP_ABORT_RSP: 3891 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3892 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3893 break; 3894 case OPC_OUB_GET_NVMD_DATA: 3895 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3896 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3897 break; 3898 case OPC_OUB_SET_NVMD_DATA: 3899 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3900 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3901 break; 3902 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3903 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3904 break; 3905 case OPC_OUB_SET_DEVICE_STATE: 3906 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3907 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3908 break; 3909 case OPC_OUB_GET_DEVICE_STATE: 3910 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 3911 break; 3912 case OPC_OUB_SET_DEV_INFO: 3913 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 3914 break; 3915 /* spcv specific commands */ 3916 case OPC_OUB_PHY_START_RESP: 3917 pm8001_dbg(pm8001_ha, MSG, 3918 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 3919 mpi_phy_start_resp(pm8001_ha, piomb); 3920 break; 3921 case OPC_OUB_PHY_STOP_RESP: 3922 pm8001_dbg(pm8001_ha, MSG, 3923 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 3924 mpi_phy_stop_resp(pm8001_ha, piomb); 3925 break; 3926 case OPC_OUB_SET_CONTROLLER_CONFIG: 3927 pm8001_dbg(pm8001_ha, MSG, 3928 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 3929 mpi_set_controller_config_resp(pm8001_ha, piomb); 3930 break; 3931 case OPC_OUB_GET_CONTROLLER_CONFIG: 3932 pm8001_dbg(pm8001_ha, MSG, 3933 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 3934 mpi_get_controller_config_resp(pm8001_ha, piomb); 3935 break; 3936 case OPC_OUB_GET_PHY_PROFILE: 3937 pm8001_dbg(pm8001_ha, MSG, 3938 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 3939 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3940 break; 3941 case OPC_OUB_FLASH_OP_EXT: 3942 pm8001_dbg(pm8001_ha, MSG, 3943 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 3944 mpi_flash_op_ext_resp(pm8001_ha, piomb); 3945 break; 3946 case OPC_OUB_SET_PHY_PROFILE: 3947 pm8001_dbg(pm8001_ha, MSG, 3948 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 3949 mpi_set_phy_profile_resp(pm8001_ha, piomb); 3950 break; 3951 case OPC_OUB_KEK_MANAGEMENT_RESP: 3952 pm8001_dbg(pm8001_ha, MSG, 3953 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 3954 mpi_kek_management_resp(pm8001_ha, piomb); 3955 break; 3956 case OPC_OUB_DEK_MANAGEMENT_RESP: 3957 pm8001_dbg(pm8001_ha, MSG, 3958 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 3959 mpi_dek_management_resp(pm8001_ha, piomb); 3960 break; 3961 case OPC_OUB_SSP_COALESCED_COMP_RESP: 3962 pm8001_dbg(pm8001_ha, MSG, 3963 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 3964 ssp_coalesced_comp_resp(pm8001_ha, piomb); 3965 break; 3966 default: 3967 pm8001_dbg(pm8001_ha, DEVIO, 3968 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 3969 break; 3970 } 3971 } 3972 3973 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 3974 { 3975 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 3976 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 3977 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 3978 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 3979 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 3980 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 3981 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 3982 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 3983 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 3984 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 3985 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 3986 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 3987 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 3988 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 3989 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 3990 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 3991 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 3992 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 3993 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 3994 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 3995 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 3996 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0)); 3997 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 3998 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1)); 3999 } 4000 4001 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4002 { 4003 struct outbound_queue_table *circularQ; 4004 void *pMsg1 = NULL; 4005 u8 bc; 4006 u32 ret = MPI_IO_STATUS_FAIL; 4007 u32 regval; 4008 4009 /* 4010 * Fatal errors are programmed to be signalled in irq vector 4011 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl. 4012 * fatal_err_interrupt 4013 */ 4014 if (vec == (pm8001_ha->max_q_num - 1)) { 4015 u32 mipsall_ready; 4016 4017 if (pm8001_ha->chip_id == chip_8008 || 4018 pm8001_ha->chip_id == chip_8009) 4019 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT; 4020 else 4021 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT; 4022 4023 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4024 if ((regval & mipsall_ready) != mipsall_ready) { 4025 pm8001_ha->controller_fatal_error = true; 4026 pm8001_dbg(pm8001_ha, FAIL, 4027 "Firmware Fatal error! Regval:0x%x\n", 4028 regval); 4029 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR); 4030 print_scratchpad_registers(pm8001_ha); 4031 return ret; 4032 } else { 4033 /*read scratchpad rsvd 0 register*/ 4034 regval = pm8001_cr32(pm8001_ha, 0, 4035 MSGU_SCRATCH_PAD_RSVD_0); 4036 switch (regval) { 4037 case NON_FATAL_SPBC_LBUS_ECC_ERR: 4038 case NON_FATAL_BDMA_ERR: 4039 case NON_FATAL_THERM_OVERTEMP_ERR: 4040 /*Clear the register*/ 4041 pm8001_cw32(pm8001_ha, 0, 4042 MSGU_SCRATCH_PAD_RSVD_0, 4043 0x00000000); 4044 break; 4045 default: 4046 break; 4047 } 4048 } 4049 } 4050 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4051 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags); 4052 do { 4053 /* spurious interrupt during setup if kexec-ing and 4054 * driver doing a doorbell access w/ the pre-kexec oq 4055 * interrupt setup. 4056 */ 4057 if (!circularQ->pi_virt) 4058 break; 4059 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4060 if (MPI_IO_STATUS_SUCCESS == ret) { 4061 /* process the outbound message */ 4062 process_one_iomb(pm8001_ha, circularQ, 4063 (void *)(pMsg1 - 4)); 4064 /* free the message from the outbound circular buffer */ 4065 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4066 circularQ, bc); 4067 } 4068 if (MPI_IO_STATUS_BUSY == ret) { 4069 /* Update the producer index from SPC */ 4070 circularQ->producer_index = 4071 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4072 if (le32_to_cpu(circularQ->producer_index) == 4073 circularQ->consumer_idx) 4074 /* OQ is empty */ 4075 break; 4076 } 4077 } while (1); 4078 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags); 4079 return ret; 4080 } 4081 4082 /* DMA_... to our direction translation. */ 4083 static const u8 data_dir_flags[] = { 4084 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4085 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4086 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4087 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4088 }; 4089 4090 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4091 struct smp_req *psmp_cmd, int mode, int length) 4092 { 4093 psmp_cmd->tag = hTag; 4094 psmp_cmd->device_id = cpu_to_le32(deviceID); 4095 if (mode == SMP_DIRECT) { 4096 length = length - 4; /* subtract crc */ 4097 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4098 } else { 4099 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4100 } 4101 } 4102 4103 /** 4104 * pm80xx_chip_smp_req - send an SMP task to FW 4105 * @pm8001_ha: our hba card information. 4106 * @ccb: the ccb information this request used. 4107 */ 4108 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4109 struct pm8001_ccb_info *ccb) 4110 { 4111 int elem, rc; 4112 struct sas_task *task = ccb->task; 4113 struct domain_device *dev = task->dev; 4114 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4115 struct scatterlist *sg_req, *sg_resp, *smp_req; 4116 u32 req_len, resp_len; 4117 struct smp_req smp_cmd; 4118 u32 opc; 4119 u32 i, length; 4120 u8 *payload; 4121 u8 *to; 4122 4123 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4124 /* 4125 * DMA-map SMP request, response buffers 4126 */ 4127 sg_req = &task->smp_task.smp_req; 4128 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4129 if (!elem) 4130 return -ENOMEM; 4131 req_len = sg_dma_len(sg_req); 4132 4133 sg_resp = &task->smp_task.smp_resp; 4134 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4135 if (!elem) { 4136 rc = -ENOMEM; 4137 goto err_out; 4138 } 4139 resp_len = sg_dma_len(sg_resp); 4140 /* must be in dwords */ 4141 if ((req_len & 0x3) || (resp_len & 0x3)) { 4142 rc = -EINVAL; 4143 goto err_out_2; 4144 } 4145 4146 opc = OPC_INB_SMP_REQUEST; 4147 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4148 4149 length = sg_req->length; 4150 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4151 if (!(length - 8)) 4152 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4153 else 4154 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4155 4156 4157 smp_req = &task->smp_task.smp_req; 4158 to = kmap_atomic(sg_page(smp_req)); 4159 payload = to + smp_req->offset; 4160 4161 /* INDIRECT MODE command settings. Use DMA */ 4162 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4163 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4164 /* for SPCv indirect mode. Place the top 4 bytes of 4165 * SMP Request header here. */ 4166 for (i = 0; i < 4; i++) 4167 smp_cmd.smp_req16[i] = *(payload + i); 4168 /* exclude top 4 bytes for SMP req header */ 4169 smp_cmd.long_smp_req.long_req_addr = 4170 cpu_to_le64((u64)sg_dma_address 4171 (&task->smp_task.smp_req) + 4); 4172 /* exclude 4 bytes for SMP req header and CRC */ 4173 smp_cmd.long_smp_req.long_req_size = 4174 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4175 smp_cmd.long_smp_req.long_resp_addr = 4176 cpu_to_le64((u64)sg_dma_address 4177 (&task->smp_task.smp_resp)); 4178 smp_cmd.long_smp_req.long_resp_size = 4179 cpu_to_le32((u32)sg_dma_len 4180 (&task->smp_task.smp_resp)-4); 4181 } else { /* DIRECT MODE */ 4182 smp_cmd.long_smp_req.long_req_addr = 4183 cpu_to_le64((u64)sg_dma_address 4184 (&task->smp_task.smp_req)); 4185 smp_cmd.long_smp_req.long_req_size = 4186 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4187 smp_cmd.long_smp_req.long_resp_addr = 4188 cpu_to_le64((u64)sg_dma_address 4189 (&task->smp_task.smp_resp)); 4190 smp_cmd.long_smp_req.long_resp_size = 4191 cpu_to_le32 4192 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4193 } 4194 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4195 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4196 for (i = 0; i < length; i++) 4197 if (i < 16) { 4198 smp_cmd.smp_req16[i] = *(payload + i); 4199 pm8001_dbg(pm8001_ha, IO, 4200 "Byte[%d]:%x (DMA data:%x)\n", 4201 i, smp_cmd.smp_req16[i], 4202 *(payload)); 4203 } else { 4204 smp_cmd.smp_req[i] = *(payload + i); 4205 pm8001_dbg(pm8001_ha, IO, 4206 "Byte[%d]:%x (DMA data:%x)\n", 4207 i, smp_cmd.smp_req[i], 4208 *(payload)); 4209 } 4210 } 4211 kunmap_atomic(to); 4212 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4213 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4214 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd, 4215 sizeof(smp_cmd), 0); 4216 if (rc) 4217 goto err_out_2; 4218 return 0; 4219 4220 err_out_2: 4221 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4222 DMA_FROM_DEVICE); 4223 err_out: 4224 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4225 DMA_TO_DEVICE); 4226 return rc; 4227 } 4228 4229 static int check_enc_sas_cmd(struct sas_task *task) 4230 { 4231 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4232 4233 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4234 return 1; 4235 else 4236 return 0; 4237 } 4238 4239 static int check_enc_sat_cmd(struct sas_task *task) 4240 { 4241 int ret = 0; 4242 switch (task->ata_task.fis.command) { 4243 case ATA_CMD_FPDMA_READ: 4244 case ATA_CMD_READ_EXT: 4245 case ATA_CMD_READ: 4246 case ATA_CMD_FPDMA_WRITE: 4247 case ATA_CMD_WRITE_EXT: 4248 case ATA_CMD_WRITE: 4249 case ATA_CMD_PIO_READ: 4250 case ATA_CMD_PIO_READ_EXT: 4251 case ATA_CMD_PIO_WRITE: 4252 case ATA_CMD_PIO_WRITE_EXT: 4253 ret = 1; 4254 break; 4255 default: 4256 ret = 0; 4257 break; 4258 } 4259 return ret; 4260 } 4261 4262 static u32 pm80xx_chip_get_q_index(struct sas_task *task) 4263 { 4264 struct request *rq = sas_task_find_rq(task); 4265 4266 if (!rq) 4267 return 0; 4268 4269 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(rq)); 4270 } 4271 4272 /** 4273 * pm80xx_chip_ssp_io_req - send an SSP task to FW 4274 * @pm8001_ha: our hba card information. 4275 * @ccb: the ccb information this request used. 4276 */ 4277 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4278 struct pm8001_ccb_info *ccb) 4279 { 4280 struct sas_task *task = ccb->task; 4281 struct domain_device *dev = task->dev; 4282 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4283 struct ssp_ini_io_start_req ssp_cmd; 4284 u32 tag = ccb->ccb_tag; 4285 u64 phys_addr, end_addr; 4286 u32 end_addr_high, end_addr_low; 4287 u32 q_index; 4288 u32 opc = OPC_INB_SSPINIIOSTART; 4289 4290 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4291 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4292 4293 /* data address domain added for spcv; set to 0 by host, 4294 * used internally by controller 4295 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4296 */ 4297 ssp_cmd.dad_dir_m_tlr = 4298 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4299 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4300 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4301 ssp_cmd.tag = cpu_to_le32(tag); 4302 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4303 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4304 task->ssp_task.cmd->cmd_len); 4305 q_index = pm80xx_chip_get_q_index(task); 4306 4307 /* Check if encryption is set */ 4308 if (pm8001_ha->chip->encrypt && 4309 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4310 pm8001_dbg(pm8001_ha, IO, 4311 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4312 task->ssp_task.cmd->cmnd[0]); 4313 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4314 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4315 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4316 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4317 4318 /* fill in PRD (scatter/gather) table, if any */ 4319 if (task->num_scatter > 1) { 4320 pm8001_chip_make_sg(task->scatter, 4321 ccb->n_elem, ccb->buf_prd); 4322 phys_addr = ccb->ccb_dma_handle; 4323 ssp_cmd.enc_addr_low = 4324 cpu_to_le32(lower_32_bits(phys_addr)); 4325 ssp_cmd.enc_addr_high = 4326 cpu_to_le32(upper_32_bits(phys_addr)); 4327 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4328 } else if (task->num_scatter == 1) { 4329 u64 dma_addr = sg_dma_address(task->scatter); 4330 4331 ssp_cmd.enc_addr_low = 4332 cpu_to_le32(lower_32_bits(dma_addr)); 4333 ssp_cmd.enc_addr_high = 4334 cpu_to_le32(upper_32_bits(dma_addr)); 4335 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4336 ssp_cmd.enc_esgl = 0; 4337 4338 /* Check 4G Boundary */ 4339 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1; 4340 end_addr_low = lower_32_bits(end_addr); 4341 end_addr_high = upper_32_bits(end_addr); 4342 4343 if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) { 4344 pm8001_dbg(pm8001_ha, FAIL, 4345 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4346 dma_addr, 4347 le32_to_cpu(ssp_cmd.enc_len), 4348 end_addr_high, end_addr_low); 4349 pm8001_chip_make_sg(task->scatter, 1, 4350 ccb->buf_prd); 4351 phys_addr = ccb->ccb_dma_handle; 4352 ssp_cmd.enc_addr_low = 4353 cpu_to_le32(lower_32_bits(phys_addr)); 4354 ssp_cmd.enc_addr_high = 4355 cpu_to_le32(upper_32_bits(phys_addr)); 4356 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31); 4357 } 4358 } else if (task->num_scatter == 0) { 4359 ssp_cmd.enc_addr_low = 0; 4360 ssp_cmd.enc_addr_high = 0; 4361 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4362 ssp_cmd.enc_esgl = 0; 4363 } 4364 4365 /* XTS mode. All other fields are 0 */ 4366 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4); 4367 4368 /* set tweak values. Should be the start lba */ 4369 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4370 (task->ssp_task.cmd->cmnd[3] << 16) | 4371 (task->ssp_task.cmd->cmnd[4] << 8) | 4372 (task->ssp_task.cmd->cmnd[5])); 4373 } else { 4374 pm8001_dbg(pm8001_ha, IO, 4375 "Sending Normal SAS command 0x%x inb q %x\n", 4376 task->ssp_task.cmd->cmnd[0], q_index); 4377 /* fill in PRD (scatter/gather) table, if any */ 4378 if (task->num_scatter > 1) { 4379 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4380 ccb->buf_prd); 4381 phys_addr = ccb->ccb_dma_handle; 4382 ssp_cmd.addr_low = 4383 cpu_to_le32(lower_32_bits(phys_addr)); 4384 ssp_cmd.addr_high = 4385 cpu_to_le32(upper_32_bits(phys_addr)); 4386 ssp_cmd.esgl = cpu_to_le32(1<<31); 4387 } else if (task->num_scatter == 1) { 4388 u64 dma_addr = sg_dma_address(task->scatter); 4389 4390 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4391 ssp_cmd.addr_high = 4392 cpu_to_le32(upper_32_bits(dma_addr)); 4393 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4394 ssp_cmd.esgl = 0; 4395 4396 /* Check 4G Boundary */ 4397 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1; 4398 end_addr_low = lower_32_bits(end_addr); 4399 end_addr_high = upper_32_bits(end_addr); 4400 if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) { 4401 pm8001_dbg(pm8001_ha, FAIL, 4402 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4403 dma_addr, 4404 le32_to_cpu(ssp_cmd.len), 4405 end_addr_high, end_addr_low); 4406 pm8001_chip_make_sg(task->scatter, 1, 4407 ccb->buf_prd); 4408 phys_addr = ccb->ccb_dma_handle; 4409 ssp_cmd.addr_low = 4410 cpu_to_le32(lower_32_bits(phys_addr)); 4411 ssp_cmd.addr_high = 4412 cpu_to_le32(upper_32_bits(phys_addr)); 4413 ssp_cmd.esgl = cpu_to_le32(1<<31); 4414 } 4415 } else if (task->num_scatter == 0) { 4416 ssp_cmd.addr_low = 0; 4417 ssp_cmd.addr_high = 0; 4418 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4419 ssp_cmd.esgl = 0; 4420 } 4421 } 4422 4423 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd, 4424 sizeof(ssp_cmd), q_index); 4425 } 4426 4427 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4428 struct pm8001_ccb_info *ccb) 4429 { 4430 struct sas_task *task = ccb->task; 4431 struct domain_device *dev = task->dev; 4432 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4433 struct ata_queued_cmd *qc = task->uldd_task; 4434 u32 tag = ccb->ccb_tag, q_index; 4435 struct sata_start_req sata_cmd; 4436 u32 hdr_tag, ncg_tag = 0; 4437 u64 phys_addr, end_addr; 4438 u32 end_addr_high, end_addr_low; 4439 u32 ATAP = 0x0; 4440 u32 dir, retfis = 0; 4441 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4442 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4443 4444 q_index = pm80xx_chip_get_q_index(task); 4445 4446 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { 4447 ATAP = 0x04; /* no data*/ 4448 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4449 } else if (likely(!task->ata_task.device_control_reg_update)) { 4450 if (task->ata_task.use_ncq && 4451 dev->sata_dev.class != ATA_DEV_ATAPI) { 4452 ATAP = 0x07; /* FPDMA */ 4453 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4454 } else if (task->ata_task.dma_xfer) { 4455 ATAP = 0x06; /* DMA */ 4456 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4457 } else { 4458 ATAP = 0x05; /* PIO*/ 4459 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4460 } 4461 } 4462 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4463 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4464 ncg_tag = hdr_tag; 4465 } 4466 dir = data_dir_flags[task->data_dir] << 8; 4467 sata_cmd.tag = cpu_to_le32(tag); 4468 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4469 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4470 if (task->ata_task.return_fis_on_success) 4471 retfis = 1; 4472 sata_cmd.sata_fis = task->ata_task.fis; 4473 if (likely(!task->ata_task.device_control_reg_update)) 4474 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4475 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4476 4477 /* Check if encryption is set */ 4478 if (pm8001_ha->chip->encrypt && 4479 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4480 pm8001_dbg(pm8001_ha, IO, 4481 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4482 sata_cmd.sata_fis.command); 4483 opc = OPC_INB_SATA_DIF_ENC_IO; 4484 /* set encryption bit; dad (bits 0-1) is 0 */ 4485 sata_cmd.retfis_ncqtag_atap_dir_m_dad = 4486 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4487 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4488 /* fill in PRD (scatter/gather) table, if any */ 4489 if (task->num_scatter > 1) { 4490 pm8001_chip_make_sg(task->scatter, 4491 ccb->n_elem, ccb->buf_prd); 4492 phys_addr = ccb->ccb_dma_handle; 4493 sata_cmd.enc_addr_low = 4494 cpu_to_le32(lower_32_bits(phys_addr)); 4495 sata_cmd.enc_addr_high = 4496 cpu_to_le32(upper_32_bits(phys_addr)); 4497 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4498 } else if (task->num_scatter == 1) { 4499 u64 dma_addr = sg_dma_address(task->scatter); 4500 4501 sata_cmd.enc_addr_low = 4502 cpu_to_le32(lower_32_bits(dma_addr)); 4503 sata_cmd.enc_addr_high = 4504 cpu_to_le32(upper_32_bits(dma_addr)); 4505 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4506 sata_cmd.enc_esgl = 0; 4507 4508 /* Check 4G Boundary */ 4509 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1; 4510 end_addr_low = lower_32_bits(end_addr); 4511 end_addr_high = upper_32_bits(end_addr); 4512 if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) { 4513 pm8001_dbg(pm8001_ha, FAIL, 4514 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4515 dma_addr, 4516 le32_to_cpu(sata_cmd.enc_len), 4517 end_addr_high, end_addr_low); 4518 pm8001_chip_make_sg(task->scatter, 1, 4519 ccb->buf_prd); 4520 phys_addr = ccb->ccb_dma_handle; 4521 sata_cmd.enc_addr_low = 4522 cpu_to_le32(lower_32_bits(phys_addr)); 4523 sata_cmd.enc_addr_high = 4524 cpu_to_le32(upper_32_bits(phys_addr)); 4525 sata_cmd.enc_esgl = 4526 cpu_to_le32(1 << 31); 4527 } 4528 } else if (task->num_scatter == 0) { 4529 sata_cmd.enc_addr_low = 0; 4530 sata_cmd.enc_addr_high = 0; 4531 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4532 sata_cmd.enc_esgl = 0; 4533 } 4534 /* XTS mode. All other fields are 0 */ 4535 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4); 4536 4537 /* set tweak values. Should be the start lba */ 4538 sata_cmd.twk_val0 = 4539 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4540 (sata_cmd.sata_fis.lbah << 16) | 4541 (sata_cmd.sata_fis.lbam << 8) | 4542 (sata_cmd.sata_fis.lbal)); 4543 sata_cmd.twk_val1 = 4544 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4545 (sata_cmd.sata_fis.lbam_exp)); 4546 } else { 4547 pm8001_dbg(pm8001_ha, IO, 4548 "Sending Normal SATA command 0x%x inb %x\n", 4549 sata_cmd.sata_fis.command, q_index); 4550 /* dad (bits 0-1) is 0 */ 4551 sata_cmd.retfis_ncqtag_atap_dir_m_dad = 4552 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4553 ((ATAP & 0x3f) << 10) | dir); 4554 /* fill in PRD (scatter/gather) table, if any */ 4555 if (task->num_scatter > 1) { 4556 pm8001_chip_make_sg(task->scatter, 4557 ccb->n_elem, ccb->buf_prd); 4558 phys_addr = ccb->ccb_dma_handle; 4559 sata_cmd.addr_low = lower_32_bits(phys_addr); 4560 sata_cmd.addr_high = upper_32_bits(phys_addr); 4561 sata_cmd.esgl = cpu_to_le32(1U << 31); 4562 } else if (task->num_scatter == 1) { 4563 u64 dma_addr = sg_dma_address(task->scatter); 4564 4565 sata_cmd.addr_low = lower_32_bits(dma_addr); 4566 sata_cmd.addr_high = upper_32_bits(dma_addr); 4567 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4568 sata_cmd.esgl = 0; 4569 4570 /* Check 4G Boundary */ 4571 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1; 4572 end_addr_low = lower_32_bits(end_addr); 4573 end_addr_high = upper_32_bits(end_addr); 4574 if (end_addr_high != sata_cmd.addr_high) { 4575 pm8001_dbg(pm8001_ha, FAIL, 4576 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4577 dma_addr, 4578 le32_to_cpu(sata_cmd.len), 4579 end_addr_high, end_addr_low); 4580 pm8001_chip_make_sg(task->scatter, 1, 4581 ccb->buf_prd); 4582 phys_addr = ccb->ccb_dma_handle; 4583 sata_cmd.addr_low = lower_32_bits(phys_addr); 4584 sata_cmd.addr_high = upper_32_bits(phys_addr); 4585 sata_cmd.esgl = cpu_to_le32(1U << 31); 4586 } 4587 } else if (task->num_scatter == 0) { 4588 sata_cmd.addr_low = 0; 4589 sata_cmd.addr_high = 0; 4590 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4591 sata_cmd.esgl = 0; 4592 } 4593 4594 /* scsi cdb */ 4595 sata_cmd.atapi_scsi_cdb[0] = 4596 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4597 (task->ata_task.atapi_packet[1] << 8) | 4598 (task->ata_task.atapi_packet[2] << 16) | 4599 (task->ata_task.atapi_packet[3] << 24))); 4600 sata_cmd.atapi_scsi_cdb[1] = 4601 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4602 (task->ata_task.atapi_packet[5] << 8) | 4603 (task->ata_task.atapi_packet[6] << 16) | 4604 (task->ata_task.atapi_packet[7] << 24))); 4605 sata_cmd.atapi_scsi_cdb[2] = 4606 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4607 (task->ata_task.atapi_packet[9] << 8) | 4608 (task->ata_task.atapi_packet[10] << 16) | 4609 (task->ata_task.atapi_packet[11] << 24))); 4610 sata_cmd.atapi_scsi_cdb[3] = 4611 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4612 (task->ata_task.atapi_packet[13] << 8) | 4613 (task->ata_task.atapi_packet[14] << 16) | 4614 (task->ata_task.atapi_packet[15] << 24))); 4615 } 4616 4617 trace_pm80xx_request_issue(pm8001_ha->id, 4618 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS, 4619 ccb->ccb_tag, opc, 4620 qc ? qc->tf.command : 0, // ata opcode 4621 ccb->device ? atomic_read(&ccb->device->running_req) : 0); 4622 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd, 4623 sizeof(sata_cmd), q_index); 4624 } 4625 4626 /** 4627 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4628 * @pm8001_ha: our hba card information. 4629 * @phy_id: the phy id which we wanted to start up. 4630 */ 4631 static int 4632 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4633 { 4634 struct phy_start_req payload; 4635 u32 tag = 0x01; 4636 u32 opcode = OPC_INB_PHYSTART; 4637 4638 memset(&payload, 0, sizeof(payload)); 4639 payload.tag = cpu_to_le32(tag); 4640 4641 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4642 4643 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4644 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4645 /* SSC Disable and SAS Analog ST configuration */ 4646 /* 4647 payload.ase_sh_lm_slr_phyid = 4648 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4649 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4650 phy_id); 4651 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4652 */ 4653 4654 payload.sas_identify.dev_type = SAS_END_DEVICE; 4655 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4656 memcpy(payload.sas_identify.sas_addr, 4657 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE); 4658 payload.sas_identify.phy_id = phy_id; 4659 4660 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4661 sizeof(payload), 0); 4662 } 4663 4664 /** 4665 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4666 * @pm8001_ha: our hba card information. 4667 * @phy_id: the phy id which we wanted to start up. 4668 */ 4669 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4670 u8 phy_id) 4671 { 4672 struct phy_stop_req payload; 4673 u32 tag = 0x01; 4674 u32 opcode = OPC_INB_PHYSTOP; 4675 4676 memset(&payload, 0, sizeof(payload)); 4677 payload.tag = cpu_to_le32(tag); 4678 payload.phy_id = cpu_to_le32(phy_id); 4679 4680 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4681 sizeof(payload), 0); 4682 } 4683 4684 /* 4685 * see comments on pm8001_mpi_reg_resp. 4686 */ 4687 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4688 struct pm8001_device *pm8001_dev, u32 flag) 4689 { 4690 struct reg_dev_req payload; 4691 u32 opc; 4692 u32 stp_sspsmp_sata = 0x4; 4693 u32 linkrate, phy_id; 4694 int rc; 4695 struct pm8001_ccb_info *ccb; 4696 u8 retryFlag = 0x1; 4697 u16 firstBurstSize = 0; 4698 u16 ITNT = 2000; 4699 struct domain_device *dev = pm8001_dev->sas_device; 4700 struct domain_device *parent_dev = dev->parent; 4701 struct pm8001_port *port = dev->port->lldd_port; 4702 4703 memset(&payload, 0, sizeof(payload)); 4704 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4705 if (!ccb) 4706 return -SAS_QUEUE_FULL; 4707 4708 payload.tag = cpu_to_le32(ccb->ccb_tag); 4709 4710 if (flag == 1) { 4711 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4712 } else { 4713 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4714 stp_sspsmp_sata = 0x00; /* stp*/ 4715 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4716 dev_is_expander(pm8001_dev->dev_type)) 4717 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4718 } 4719 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4720 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4721 else 4722 phy_id = pm8001_dev->attached_phy; 4723 4724 opc = OPC_INB_REG_DEV; 4725 4726 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4727 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4728 4729 payload.phyid_portid = 4730 cpu_to_le32(((port->port_id) & 0xFF) | 4731 ((phy_id & 0xFF) << 8)); 4732 4733 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4734 ((linkrate & 0x0F) << 24) | 4735 ((stp_sspsmp_sata & 0x03) << 28)); 4736 payload.firstburstsize_ITNexustimeout = 4737 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4738 4739 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4740 SAS_ADDR_SIZE); 4741 4742 pm8001_dbg(pm8001_ha, INIT, 4743 "register device req phy_id 0x%x port_id 0x%x\n", phy_id, 4744 (port->port_id & 0xFF)); 4745 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4746 sizeof(payload), 0); 4747 if (rc) 4748 pm8001_ccb_free(pm8001_ha, ccb); 4749 4750 return rc; 4751 } 4752 4753 /** 4754 * pm80xx_chip_phy_ctl_req - support the local phy operation 4755 * @pm8001_ha: our hba card information. 4756 * @phyId: the phy id which we wanted to operate 4757 * @phy_op: phy operation to request 4758 */ 4759 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4760 u32 phyId, u32 phy_op) 4761 { 4762 u32 tag; 4763 int rc; 4764 struct local_phy_ctl_req payload; 4765 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4766 4767 memset(&payload, 0, sizeof(payload)); 4768 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4769 if (rc) 4770 return rc; 4771 4772 payload.tag = cpu_to_le32(tag); 4773 payload.phyop_phyid = 4774 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4775 4776 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4777 sizeof(payload), 0); 4778 if (rc) 4779 pm8001_tag_free(pm8001_ha, tag); 4780 4781 return rc; 4782 } 4783 4784 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4785 { 4786 u32 value; 4787 4788 if (pm8001_ha->use_msix) 4789 return 1; 4790 4791 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4792 if (value) 4793 return 1; 4794 return 0; 4795 } 4796 4797 /** 4798 * pm80xx_chip_isr - PM8001 isr handler. 4799 * @pm8001_ha: our hba card information. 4800 * @vec: irq number. 4801 */ 4802 static irqreturn_t 4803 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4804 { 4805 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4806 pm8001_dbg(pm8001_ha, DEVIO, 4807 "irq vec %d, ODMR:0x%x\n", 4808 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4809 process_oq(pm8001_ha, vec); 4810 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4811 return IRQ_HANDLED; 4812 } 4813 4814 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4815 u32 operation, u32 phyid, 4816 u32 length, u32 *buf) 4817 { 4818 u32 tag, i, j = 0; 4819 int rc; 4820 struct set_phy_profile_req payload; 4821 u32 opc = OPC_INB_SET_PHY_PROFILE; 4822 4823 memset(&payload, 0, sizeof(payload)); 4824 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4825 if (rc) { 4826 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4827 return; 4828 } 4829 4830 payload.tag = cpu_to_le32(tag); 4831 payload.ppc_phyid = 4832 cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF)); 4833 pm8001_dbg(pm8001_ha, DISC, 4834 " phy profile command for phy %x ,length is %d\n", 4835 le32_to_cpu(payload.ppc_phyid), length); 4836 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4837 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4838 j++; 4839 } 4840 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4841 sizeof(payload), 0); 4842 if (rc) 4843 pm8001_tag_free(pm8001_ha, tag); 4844 } 4845 4846 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4847 u32 length, u8 *buf) 4848 { 4849 u32 i; 4850 4851 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4852 mpi_set_phy_profile_req(pm8001_ha, 4853 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4854 length = length + PHY_DWORD_LENGTH; 4855 } 4856 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 4857 } 4858 4859 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4860 u32 phy, u32 length, u32 *buf) 4861 { 4862 u32 tag, opc; 4863 int rc, i; 4864 struct set_phy_profile_req payload; 4865 4866 memset(&payload, 0, sizeof(payload)); 4867 4868 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4869 if (rc) { 4870 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 4871 return; 4872 } 4873 4874 opc = OPC_INB_SET_PHY_PROFILE; 4875 4876 payload.tag = cpu_to_le32(tag); 4877 payload.ppc_phyid = 4878 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4879 | (phy & 0xFF)); 4880 4881 for (i = 0; i < length; i++) 4882 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4883 4884 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4885 sizeof(payload), 0); 4886 if (rc) 4887 pm8001_tag_free(pm8001_ha, tag); 4888 4889 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 4890 } 4891 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4892 .name = "pmc80xx", 4893 .chip_init = pm80xx_chip_init, 4894 .chip_post_init = pm80xx_chip_post_init, 4895 .chip_soft_rst = pm80xx_chip_soft_rst, 4896 .chip_rst = pm80xx_hw_chip_rst, 4897 .chip_iounmap = pm8001_chip_iounmap, 4898 .isr = pm80xx_chip_isr, 4899 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4900 .isr_process_oq = process_oq, 4901 .interrupt_enable = pm80xx_chip_interrupt_enable, 4902 .interrupt_disable = pm80xx_chip_interrupt_disable, 4903 .make_prd = pm8001_chip_make_sg, 4904 .smp_req = pm80xx_chip_smp_req, 4905 .ssp_io_req = pm80xx_chip_ssp_io_req, 4906 .sata_req = pm80xx_chip_sata_req, 4907 .phy_start_req = pm80xx_chip_phy_start_req, 4908 .phy_stop_req = pm80xx_chip_phy_stop_req, 4909 .reg_dev_req = pm80xx_chip_reg_dev_req, 4910 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4911 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4912 .task_abort = pm8001_chip_abort_task, 4913 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4914 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4915 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4916 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4917 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4918 .fatal_errors = pm80xx_fatal_errors, 4919 .hw_event_ack_req = pm80xx_hw_event_ack_req, 4920 }; 4921