1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 #include "pm80xx_tracepoints.h" 46 47 #define SMP_DIRECT 1 48 #define SMP_INDIRECT 2 49 50 51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 52 { 53 u32 reg_val; 54 unsigned long start; 55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 56 /* confirm the setting is written */ 57 start = jiffies + HZ; /* 1 sec */ 58 do { 59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 60 } while ((reg_val != shift_value) && time_before(jiffies, start)); 61 if (reg_val != shift_value) { 62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 63 reg_val); 64 return -1; 65 } 66 return 0; 67 } 68 69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 70 __le32 *destination, 71 u32 dw_count, u32 bus_base_number) 72 { 73 u32 index, value, offset; 74 75 for (index = 0; index < dw_count; index += 4, destination++) { 76 offset = (soffset + index); 77 if (offset < (64 * 1024)) { 78 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 79 *destination = cpu_to_le32(value); 80 } 81 } 82 return; 83 } 84 85 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 86 struct device_attribute *attr, char *buf) 87 { 88 struct Scsi_Host *shost = class_to_shost(cdev); 89 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 90 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 91 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 92 u32 accum_len, reg_val, index, *temp; 93 u32 status = 1; 94 unsigned long start; 95 u8 *direct_data; 96 char *fatal_error_data = buf; 97 u32 length_to_read; 98 u32 offset; 99 100 pm8001_ha->forensic_info.data_buf.direct_data = buf; 101 if (pm8001_ha->chip_id == chip_8001) { 102 pm8001_ha->forensic_info.data_buf.direct_data += 103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 104 "Not supported for SPC controller"); 105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 106 (char *)buf; 107 } 108 /* initialize variables for very first call from host application */ 109 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 110 pm8001_dbg(pm8001_ha, IO, 111 "forensic_info TYPE_NON_FATAL..............\n"); 112 direct_data = (u8 *)fatal_error_data; 113 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 114 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 115 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 116 pm8001_ha->forensic_info.data_buf.read_len = 0; 117 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 118 119 /* Write signature to fatal dump table */ 120 pm8001_mw32(fatal_table_address, 121 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 122 123 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 124 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 126 pm8001_ha->forensic_info.data_buf.read_len); 127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 128 pm8001_ha->forensic_info.data_buf.direct_len); 129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 130 pm8001_ha->forensic_info.data_buf.direct_offset); 131 } 132 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 133 /* start to get data */ 134 /* Program the MEMBASE II Shifting Register with 0x00.*/ 135 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 136 pm8001_ha->fatal_forensic_shift_offset); 137 pm8001_ha->forensic_last_offset = 0; 138 pm8001_ha->forensic_fatal_step = 0; 139 pm8001_ha->fatal_bar_loc = 0; 140 } 141 142 /* Read until accum_len is retrieved */ 143 accum_len = pm8001_mr32(fatal_table_address, 144 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 145 /* Determine length of data between previously stored transfer length 146 * and current accumulated transfer length 147 */ 148 length_to_read = 149 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 150 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 151 accum_len); 152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 153 length_to_read); 154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 155 pm8001_ha->forensic_last_offset); 156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 157 pm8001_ha->forensic_info.data_buf.read_len); 158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 159 pm8001_ha->forensic_info.data_buf.direct_len); 160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 161 pm8001_ha->forensic_info.data_buf.direct_offset); 162 163 /* If accumulated length failed to read correctly fail the attempt.*/ 164 if (accum_len == 0xFFFFFFFF) { 165 pm8001_dbg(pm8001_ha, IO, 166 "Possible PCI issue 0x%x not expected\n", 167 accum_len); 168 return status; 169 } 170 /* If accumulated length is zero fail the attempt */ 171 if (accum_len == 0) { 172 pm8001_ha->forensic_info.data_buf.direct_data += 173 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 174 "%08x ", 0xFFFFFFFF); 175 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 176 (char *)buf; 177 } 178 /* Accumulated length is good so start capturing the first data */ 179 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 180 if (pm8001_ha->forensic_fatal_step == 0) { 181 moreData: 182 /* If data to read is less than SYSFS_OFFSET then reduce the 183 * length of dataLen 184 */ 185 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 186 > length_to_read) { 187 pm8001_ha->forensic_info.data_buf.direct_len = 188 length_to_read - 189 pm8001_ha->forensic_last_offset; 190 } else { 191 pm8001_ha->forensic_info.data_buf.direct_len = 192 SYSFS_OFFSET; 193 } 194 if (pm8001_ha->forensic_info.data_buf.direct_data) { 195 /* Data is in bar, copy to host memory */ 196 pm80xx_pci_mem_copy(pm8001_ha, 197 pm8001_ha->fatal_bar_loc, 198 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 199 pm8001_ha->forensic_info.data_buf.direct_len, 1); 200 } 201 pm8001_ha->fatal_bar_loc += 202 pm8001_ha->forensic_info.data_buf.direct_len; 203 pm8001_ha->forensic_info.data_buf.direct_offset += 204 pm8001_ha->forensic_info.data_buf.direct_len; 205 pm8001_ha->forensic_last_offset += 206 pm8001_ha->forensic_info.data_buf.direct_len; 207 pm8001_ha->forensic_info.data_buf.read_len = 208 pm8001_ha->forensic_info.data_buf.direct_len; 209 210 if (pm8001_ha->forensic_last_offset >= length_to_read) { 211 pm8001_ha->forensic_info.data_buf.direct_data += 212 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 213 "%08x ", 3); 214 for (index = 0; index < 215 (pm8001_ha->forensic_info.data_buf.direct_len 216 / 4); index++) { 217 pm8001_ha->forensic_info.data_buf.direct_data += 218 sprintf( 219 pm8001_ha->forensic_info.data_buf.direct_data, 220 "%08x ", *(temp + index)); 221 } 222 223 pm8001_ha->fatal_bar_loc = 0; 224 pm8001_ha->forensic_fatal_step = 1; 225 pm8001_ha->fatal_forensic_shift_offset = 0; 226 pm8001_ha->forensic_last_offset = 0; 227 status = 0; 228 offset = (int) 229 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 230 - (char *)buf); 231 pm8001_dbg(pm8001_ha, IO, 232 "get_fatal_spcv:return1 0x%x\n", offset); 233 return (char *)pm8001_ha-> 234 forensic_info.data_buf.direct_data - 235 (char *)buf; 236 } 237 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 238 pm8001_ha->forensic_info.data_buf.direct_data += 239 sprintf(pm8001_ha-> 240 forensic_info.data_buf.direct_data, 241 "%08x ", 2); 242 for (index = 0; index < 243 (pm8001_ha->forensic_info.data_buf.direct_len 244 / 4); index++) { 245 pm8001_ha->forensic_info.data_buf.direct_data 246 += sprintf(pm8001_ha-> 247 forensic_info.data_buf.direct_data, 248 "%08x ", *(temp + index)); 249 } 250 status = 0; 251 offset = (int) 252 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 253 - (char *)buf); 254 pm8001_dbg(pm8001_ha, IO, 255 "get_fatal_spcv:return2 0x%x\n", offset); 256 return (char *)pm8001_ha-> 257 forensic_info.data_buf.direct_data - 258 (char *)buf; 259 } 260 261 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 262 pm8001_ha->forensic_info.data_buf.direct_data += 263 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 264 "%08x ", 2); 265 for (index = 0; index < 266 (pm8001_ha->forensic_info.data_buf.direct_len 267 / 4) ; index++) { 268 pm8001_ha->forensic_info.data_buf.direct_data += 269 sprintf(pm8001_ha-> 270 forensic_info.data_buf.direct_data, 271 "%08x ", *(temp + index)); 272 } 273 pm8001_ha->fatal_forensic_shift_offset += 0x100; 274 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 275 pm8001_ha->fatal_forensic_shift_offset); 276 pm8001_ha->fatal_bar_loc = 0; 277 status = 0; 278 offset = (int) 279 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 280 - (char *)buf); 281 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 282 offset); 283 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 284 (char *)buf; 285 } 286 if (pm8001_ha->forensic_fatal_step == 1) { 287 /* store previous accumulated length before triggering next 288 * accumulated length update 289 */ 290 pm8001_ha->forensic_preserved_accumulated_transfer = 291 pm8001_mr32(fatal_table_address, 292 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 293 294 /* continue capturing the fatal log until Dump status is 0x3 */ 295 if (pm8001_mr32(fatal_table_address, 296 MPI_FATAL_EDUMP_TABLE_STATUS) < 297 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 298 299 /* reset fddstat bit by writing to zero*/ 300 pm8001_mw32(fatal_table_address, 301 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 302 303 /* set dump control value to '1' so that new data will 304 * be transferred to shared memory 305 */ 306 pm8001_mw32(fatal_table_address, 307 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 308 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 309 310 /*Poll FDDHSHK until clear */ 311 start = jiffies + (2 * HZ); /* 2 sec */ 312 313 do { 314 reg_val = pm8001_mr32(fatal_table_address, 315 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 316 } while ((reg_val) && time_before(jiffies, start)); 317 318 if (reg_val != 0) { 319 pm8001_dbg(pm8001_ha, FAIL, 320 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 321 reg_val); 322 /* Fail the dump if a timeout occurs */ 323 pm8001_ha->forensic_info.data_buf.direct_data += 324 sprintf( 325 pm8001_ha->forensic_info.data_buf.direct_data, 326 "%08x ", 0xFFFFFFFF); 327 return((char *) 328 pm8001_ha->forensic_info.data_buf.direct_data 329 - (char *)buf); 330 } 331 /* Poll status register until set to 2 or 332 * 3 for up to 2 seconds 333 */ 334 start = jiffies + (2 * HZ); /* 2 sec */ 335 336 do { 337 reg_val = pm8001_mr32(fatal_table_address, 338 MPI_FATAL_EDUMP_TABLE_STATUS); 339 } while (((reg_val != 2) && (reg_val != 3)) && 340 time_before(jiffies, start)); 341 342 if (reg_val < 2) { 343 pm8001_dbg(pm8001_ha, FAIL, 344 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 345 reg_val); 346 /* Fail the dump if a timeout occurs */ 347 pm8001_ha->forensic_info.data_buf.direct_data += 348 sprintf( 349 pm8001_ha->forensic_info.data_buf.direct_data, 350 "%08x ", 0xFFFFFFFF); 351 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 352 (char *)buf); 353 } 354 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 355 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 356 pm8001_cw32(pm8001_ha, 0, 357 MEMBASE_II_SHIFT_REGISTER, 358 pm8001_ha->fatal_forensic_shift_offset); 359 } 360 /* Read the next block of the debug data.*/ 361 length_to_read = pm8001_mr32(fatal_table_address, 362 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 363 pm8001_ha->forensic_preserved_accumulated_transfer; 364 if (length_to_read != 0x0) { 365 pm8001_ha->forensic_fatal_step = 0; 366 goto moreData; 367 } else { 368 pm8001_ha->forensic_info.data_buf.direct_data += 369 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 370 "%08x ", 4); 371 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 372 pm8001_ha->forensic_info.data_buf.direct_len = 0; 373 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 374 pm8001_ha->forensic_info.data_buf.read_len = 0; 375 } 376 } 377 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 378 - (char *)buf); 379 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 380 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 381 (char *)buf); 382 } 383 384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 385 * location by the firmware. 386 */ 387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 388 struct device_attribute *attr, char *buf) 389 { 390 struct Scsi_Host *shost = class_to_shost(cdev); 391 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 392 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 393 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 394 u32 accum_len = 0; 395 u32 total_len = 0; 396 u32 reg_val = 0; 397 u32 *temp = NULL; 398 u32 index = 0; 399 u32 output_length; 400 unsigned long start = 0; 401 char *buf_copy = buf; 402 403 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 404 if (++pm8001_ha->non_fatal_count == 1) { 405 if (pm8001_ha->chip_id == chip_8001) { 406 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 407 PAGE_SIZE, "Not supported for SPC controller"); 408 return 0; 409 } 410 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 411 /* 412 * Step 1: Write the host buffer parameters in the MPI Fatal and 413 * Non-Fatal Error Dump Capture Table.This is the buffer 414 * where debug data will be DMAed to. 415 */ 416 pm8001_mw32(nonfatal_table_address, 417 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 418 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 419 420 pm8001_mw32(nonfatal_table_address, 421 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 422 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 423 424 pm8001_mw32(nonfatal_table_address, 425 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 426 427 /* Optionally, set the DUMPCTRL bit to 1 if the host 428 * keeps sending active I/Os while capturing the non-fatal 429 * debug data. Otherwise, leave this bit set to zero 430 */ 431 pm8001_mw32(nonfatal_table_address, 432 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 433 434 /* 435 * Step 2: Clear Accumulative Length of Debug Data Transferred 436 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 437 * Capture Table to zero. 438 */ 439 pm8001_mw32(nonfatal_table_address, 440 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 441 442 /* initiallize previous accumulated length to 0 */ 443 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 444 pm8001_ha->non_fatal_read_length = 0; 445 } 446 447 total_len = pm8001_mr32(nonfatal_table_address, 448 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 449 /* 450 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 451 * field and then request that the SPCv controller transfer the debug 452 * data by setting bit 7 of the Inbound Doorbell Set Register. 453 */ 454 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 455 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 456 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 457 458 /* 459 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 460 * 2 seconds) until register bit 7 is cleared. 461 * This step only indicates the request is accepted by the controller. 462 */ 463 start = jiffies + (2 * HZ); /* 2 sec */ 464 do { 465 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 466 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 467 } while ((reg_val != 0) && time_before(jiffies, start)); 468 469 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 470 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 471 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 472 */ 473 start = jiffies + (2 * HZ); /* 2 sec */ 474 do { 475 reg_val = pm8001_mr32(nonfatal_table_address, 476 MPI_FATAL_EDUMP_TABLE_STATUS); 477 } while ((!reg_val) && time_before(jiffies, start)); 478 479 if ((reg_val == 0x00) || 480 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 481 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 482 pm8001_ha->non_fatal_read_length = 0; 483 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 484 pm8001_ha->non_fatal_count = 0; 485 return (buf_copy - buf); 486 } else if (reg_val == 487 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 488 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 489 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 490 (pm8001_ha->non_fatal_read_length >= total_len)) { 491 pm8001_ha->non_fatal_read_length = 0; 492 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 493 pm8001_ha->non_fatal_count = 0; 494 } 495 accum_len = pm8001_mr32(nonfatal_table_address, 496 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 497 output_length = accum_len - 498 pm8001_ha->forensic_preserved_accumulated_transfer; 499 500 for (index = 0; index < output_length/4; index++) 501 buf_copy += snprintf(buf_copy, PAGE_SIZE, 502 "%08x ", *(temp+index)); 503 504 pm8001_ha->non_fatal_read_length += output_length; 505 506 /* store current accumulated length to use in next iteration as 507 * the previous accumulated length 508 */ 509 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 510 return (buf_copy - buf); 511 } 512 513 /** 514 * read_main_config_table - read the configure table and save it. 515 * @pm8001_ha: our hba card information 516 */ 517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 518 { 519 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 520 521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 522 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 524 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 526 pm8001_mr32(address, MAIN_FW_REVISION); 527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 528 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 530 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 532 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 534 pm8001_mr32(address, MAIN_GST_OFFSET); 535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 536 pm8001_mr32(address, MAIN_IBQ_OFFSET); 537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 538 pm8001_mr32(address, MAIN_OBQ_OFFSET); 539 540 /* read Error Dump Offset and Length */ 541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 542 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 544 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 546 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 548 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 549 550 /* read GPIO LED settings from the configuration table */ 551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 552 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 553 554 /* read analog Setting offset from the configuration table */ 555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 556 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 557 558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 559 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 561 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 562 /* read port recover and reset timeout */ 563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 564 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 565 /* read ILA and inactive firmware version */ 566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 567 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 569 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 570 571 pm8001_dbg(pm8001_ha, INIT, 572 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 576 577 pm8001_dbg(pm8001_ha, INIT, 578 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 584 585 pm8001_dbg(pm8001_ha, INIT, 586 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 589 } 590 591 /** 592 * read_general_status_table - read the general status table and save it. 593 * @pm8001_ha: our hba card information 594 */ 595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 596 { 597 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 599 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 601 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 603 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 605 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 607 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 609 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 611 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 613 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 615 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 617 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 619 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 621 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 623 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 625 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 626 } 627 /** 628 * read_phy_attr_table - read the phy attribute table and save it. 629 * @pm8001_ha: our hba card information 630 */ 631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 632 { 633 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 634 pm8001_ha->phy_attr_table.phystart1_16[0] = 635 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 636 pm8001_ha->phy_attr_table.phystart1_16[1] = 637 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 638 pm8001_ha->phy_attr_table.phystart1_16[2] = 639 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 640 pm8001_ha->phy_attr_table.phystart1_16[3] = 641 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 642 pm8001_ha->phy_attr_table.phystart1_16[4] = 643 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 644 pm8001_ha->phy_attr_table.phystart1_16[5] = 645 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 646 pm8001_ha->phy_attr_table.phystart1_16[6] = 647 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 648 pm8001_ha->phy_attr_table.phystart1_16[7] = 649 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 650 pm8001_ha->phy_attr_table.phystart1_16[8] = 651 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 652 pm8001_ha->phy_attr_table.phystart1_16[9] = 653 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 654 pm8001_ha->phy_attr_table.phystart1_16[10] = 655 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 656 pm8001_ha->phy_attr_table.phystart1_16[11] = 657 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 658 pm8001_ha->phy_attr_table.phystart1_16[12] = 659 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 660 pm8001_ha->phy_attr_table.phystart1_16[13] = 661 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 662 pm8001_ha->phy_attr_table.phystart1_16[14] = 663 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 664 pm8001_ha->phy_attr_table.phystart1_16[15] = 665 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 666 667 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 668 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 670 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 672 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 674 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 676 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 678 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 680 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 682 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 684 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 686 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 688 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 690 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 692 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 694 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 696 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 698 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 699 700 } 701 702 /** 703 * read_inbnd_queue_table - read the inbound queue table and save it. 704 * @pm8001_ha: our hba card information 705 */ 706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 707 { 708 int i; 709 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 710 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 711 u32 offset = i * 0x20; 712 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 713 get_pci_bar_index(pm8001_mr32(address, 714 (offset + IB_PIPCI_BAR))); 715 pm8001_ha->inbnd_q_tbl[i].pi_offset = 716 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 717 } 718 } 719 720 /** 721 * read_outbnd_queue_table - read the outbound queue table and save it. 722 * @pm8001_ha: our hba card information 723 */ 724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 725 { 726 int i; 727 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 728 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 729 u32 offset = i * 0x24; 730 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 731 get_pci_bar_index(pm8001_mr32(address, 732 (offset + OB_CIPCI_BAR))); 733 pm8001_ha->outbnd_q_tbl[i].ci_offset = 734 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 735 } 736 } 737 738 /** 739 * init_default_table_values - init the default table. 740 * @pm8001_ha: our hba card information 741 */ 742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 743 { 744 int i; 745 u32 offsetib, offsetob; 746 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 747 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 748 u32 ib_offset = pm8001_ha->ib_offset; 749 u32 ob_offset = pm8001_ha->ob_offset; 750 u32 ci_offset = pm8001_ha->ci_offset; 751 u32 pi_offset = pm8001_ha->pi_offset; 752 753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 754 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 756 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 758 PM8001_EVENT_LOG_SIZE; 759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 761 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 763 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 765 PM8001_EVENT_LOG_SIZE; 766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 767 pcs_event_log_severity; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Enable higher IQs and OQs, 32 to 63, bit 16 */ 771 if (pm8001_ha->max_q_num > 32) 772 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 773 1 << 16; 774 /* Disable end to end CRC checking */ 775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 776 777 for (i = 0; i < pm8001_ha->max_q_num; i++) { 778 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 779 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 780 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 781 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 782 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 783 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 784 pm8001_ha->inbnd_q_tbl[i].base_virt = 785 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 786 pm8001_ha->inbnd_q_tbl[i].total_length = 787 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 788 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 789 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 790 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 791 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 792 pm8001_ha->inbnd_q_tbl[i].ci_virt = 793 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 794 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 795 offsetib = i * 0x20; 796 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 797 get_pci_bar_index(pm8001_mr32(addressib, 798 (offsetib + 0x14))); 799 pm8001_ha->inbnd_q_tbl[i].pi_offset = 800 pm8001_mr32(addressib, (offsetib + 0x18)); 801 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 802 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 803 804 pm8001_dbg(pm8001_ha, DEV, 805 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 806 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 807 pm8001_ha->inbnd_q_tbl[i].pi_offset); 808 } 809 for (i = 0; i < pm8001_ha->max_q_num; i++) { 810 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 811 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 812 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 813 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 814 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 815 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 816 pm8001_ha->outbnd_q_tbl[i].base_virt = 817 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 818 pm8001_ha->outbnd_q_tbl[i].total_length = 819 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 820 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 821 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 822 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 823 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 824 /* interrupt vector based on oq */ 825 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 826 pm8001_ha->outbnd_q_tbl[i].pi_virt = 827 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 828 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 829 offsetob = i * 0x24; 830 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 831 get_pci_bar_index(pm8001_mr32(addressob, 832 offsetob + 0x14)); 833 pm8001_ha->outbnd_q_tbl[i].ci_offset = 834 pm8001_mr32(addressob, (offsetob + 0x18)); 835 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 836 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 837 838 pm8001_dbg(pm8001_ha, DEV, 839 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 840 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 841 pm8001_ha->outbnd_q_tbl[i].ci_offset); 842 } 843 } 844 845 /** 846 * update_main_config_table - update the main default table to the HBA. 847 * @pm8001_ha: our hba card information 848 */ 849 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 850 { 851 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 852 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 854 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 856 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 858 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 860 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 866 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 868 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 870 /* Update Fatal error interrupt vector */ 871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 872 ((pm8001_ha->max_q_num - 1) << 8); 873 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 875 pm8001_dbg(pm8001_ha, DEV, 876 "Updated Fatal error interrupt vector 0x%x\n", 877 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 878 879 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 880 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 881 882 /* SPCv specific */ 883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 884 /* Set GPIOLED to 0x2 for LED indicator */ 885 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 886 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 888 pm8001_dbg(pm8001_ha, DEV, 889 "Programming DW 0x21 in main cfg table with 0x%x\n", 890 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 891 892 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 894 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 896 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 898 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 899 PORT_RECOVERY_TIMEOUT; 900 if (pm8001_ha->chip_id == chip_8006) { 901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 902 0x0000ffff; 903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 904 CHIP_8006_PORT_RECOVERY_TIMEOUT; 905 } 906 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 907 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 908 } 909 910 /** 911 * update_inbnd_queue_table - update the inbound queue table to the HBA. 912 * @pm8001_ha: our hba card information 913 * @number: entry in the queue 914 */ 915 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 916 int number) 917 { 918 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 919 u16 offset = number * 0x20; 920 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 922 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 924 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 925 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 926 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 927 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 928 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 929 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 930 931 pm8001_dbg(pm8001_ha, DEV, 932 "IQ %d: Element pri size 0x%x\n", 933 number, 934 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 935 936 pm8001_dbg(pm8001_ha, DEV, 937 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 938 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 939 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 940 941 pm8001_dbg(pm8001_ha, DEV, 942 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 943 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 944 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 945 } 946 947 /** 948 * update_outbnd_queue_table - update the outbound queue table to the HBA. 949 * @pm8001_ha: our hba card information 950 * @number: entry in the queue 951 */ 952 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 953 int number) 954 { 955 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 956 u16 offset = number * 0x24; 957 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 959 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 961 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 963 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 964 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 965 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 966 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 967 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 968 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 969 970 pm8001_dbg(pm8001_ha, DEV, 971 "OQ %d: Element pri size 0x%x\n", 972 number, 973 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 974 975 pm8001_dbg(pm8001_ha, DEV, 976 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 977 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 978 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 979 980 pm8001_dbg(pm8001_ha, DEV, 981 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 982 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 983 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 984 } 985 986 /** 987 * mpi_init_check - check firmware initialization status. 988 * @pm8001_ha: our hba card information 989 */ 990 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 991 { 992 u32 max_wait_count; 993 u32 value; 994 u32 gst_len_mpistate; 995 996 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 997 table is updated */ 998 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 999 /* wait until Inbound DoorBell Clear Register toggled */ 1000 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1001 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1002 } else { 1003 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1004 } 1005 do { 1006 msleep(FW_READY_INTERVAL); 1007 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1008 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1009 } while ((value != 0) && (--max_wait_count)); 1010 1011 if (!max_wait_count) { 1012 /* additional check */ 1013 pm8001_dbg(pm8001_ha, FAIL, 1014 "Inb doorbell clear not toggled[value:%x]\n", 1015 value); 1016 return -EBUSY; 1017 } 1018 /* check the MPI-State for initialization up to 100ms*/ 1019 max_wait_count = 5;/* 100 msec */ 1020 do { 1021 msleep(FW_READY_INTERVAL); 1022 gst_len_mpistate = 1023 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1024 GST_GSTLEN_MPIS_OFFSET); 1025 } while ((GST_MPI_STATE_INIT != 1026 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1027 if (!max_wait_count) 1028 return -EBUSY; 1029 1030 /* check MPI Initialization error */ 1031 gst_len_mpistate = gst_len_mpistate >> 16; 1032 if (0x0000 != gst_len_mpistate) 1033 return -EBUSY; 1034 1035 /* 1036 * As per controller datasheet, after successful MPI 1037 * initialization minimum 500ms delay is required before 1038 * issuing commands. 1039 */ 1040 msleep(500); 1041 1042 return 0; 1043 } 1044 1045 /** 1046 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1047 * This function sleeps hence it must not be used in atomic context. 1048 * @pm8001_ha: our hba card information 1049 */ 1050 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1051 { 1052 u32 value; 1053 u32 max_wait_count; 1054 u32 max_wait_time; 1055 u32 expected_mask; 1056 int ret = 0; 1057 1058 /* reset / PCIe ready */ 1059 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1060 do { 1061 msleep(FW_READY_INTERVAL); 1062 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1063 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1064 1065 /* check ila, RAAE and iops status */ 1066 if ((pm8001_ha->chip_id != chip_8008) && 1067 (pm8001_ha->chip_id != chip_8009)) { 1068 max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 1069 expected_mask = SCRATCH_PAD_ILA_READY | 1070 SCRATCH_PAD_RAAE_READY | 1071 SCRATCH_PAD_IOP0_READY | 1072 SCRATCH_PAD_IOP1_READY; 1073 } else { 1074 max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 1075 expected_mask = SCRATCH_PAD_ILA_READY | 1076 SCRATCH_PAD_RAAE_READY | 1077 SCRATCH_PAD_IOP0_READY; 1078 } 1079 do { 1080 msleep(FW_READY_INTERVAL); 1081 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1082 } while (((value & expected_mask) != 1083 expected_mask) && (--max_wait_count)); 1084 if (!max_wait_count) { 1085 pm8001_dbg(pm8001_ha, INIT, 1086 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 1087 max_wait_time * FW_READY_INTERVAL, value); 1088 ret = -1; 1089 } else { 1090 pm8001_dbg(pm8001_ha, MSG, 1091 "All FW components ready by %d ms\n", 1092 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1093 } 1094 return ret; 1095 } 1096 1097 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1098 { 1099 void __iomem *base_addr; 1100 u32 value; 1101 u32 offset; 1102 u32 pcibar; 1103 u32 pcilogic; 1104 1105 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1106 1107 /* 1108 * lower 26 bits of SCRATCHPAD0 register describes offset within the 1109 * PCIe BAR where the MPI configuration table is present 1110 */ 1111 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1112 1113 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1114 offset, value); 1115 /* 1116 * Upper 6 bits describe the offset within PCI config space where BAR 1117 * is located. 1118 */ 1119 pcilogic = (value & 0xFC000000) >> 26; 1120 pcibar = get_pci_bar_index(pcilogic); 1121 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1122 1123 /* 1124 * Make sure the offset falls inside the ioremapped PCI BAR 1125 */ 1126 if (offset > pm8001_ha->io_mem[pcibar].memsize) { 1127 pm8001_dbg(pm8001_ha, FAIL, 1128 "Main cfg tbl offset outside %u > %u\n", 1129 offset, pm8001_ha->io_mem[pcibar].memsize); 1130 return -EBUSY; 1131 } 1132 pm8001_ha->main_cfg_tbl_addr = base_addr = 1133 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1134 1135 /* 1136 * Validate main configuration table address: first DWord should read 1137 * "PMCS" 1138 */ 1139 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 1140 if (memcmp(&value, "PMCS", 4) != 0) { 1141 pm8001_dbg(pm8001_ha, FAIL, 1142 "BAD main config signature 0x%x\n", 1143 value); 1144 return -EBUSY; 1145 } 1146 pm8001_dbg(pm8001_ha, INIT, 1147 "VALID main config signature 0x%x\n", value); 1148 pm8001_ha->general_stat_tbl_addr = 1149 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1150 0xFFFFFF); 1151 pm8001_ha->inbnd_q_tbl_addr = 1152 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1153 0xFFFFFF); 1154 pm8001_ha->outbnd_q_tbl_addr = 1155 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1156 0xFFFFFF); 1157 pm8001_ha->ivt_tbl_addr = 1158 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1159 0xFFFFFF); 1160 pm8001_ha->pspa_q_tbl_addr = 1161 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1162 0xFFFFFF); 1163 pm8001_ha->fatal_tbl_addr = 1164 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1165 0xFFFFFF); 1166 1167 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1168 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1169 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1170 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1171 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1172 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1173 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1174 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1175 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1176 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1177 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1178 pm8001_ha->main_cfg_tbl_addr, 1179 pm8001_ha->general_stat_tbl_addr); 1180 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1181 pm8001_ha->inbnd_q_tbl_addr, 1182 pm8001_ha->outbnd_q_tbl_addr); 1183 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1184 pm8001_ha->pspa_q_tbl_addr, 1185 pm8001_ha->ivt_tbl_addr); 1186 return 0; 1187 } 1188 1189 /** 1190 * pm80xx_set_thermal_config - support the thermal configuration 1191 * @pm8001_ha: our hba card information. 1192 */ 1193 int 1194 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1195 { 1196 struct set_ctrl_cfg_req payload; 1197 int rc; 1198 u32 tag; 1199 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1200 u32 page_code; 1201 1202 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1203 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1204 if (rc) 1205 return rc; 1206 1207 payload.tag = cpu_to_le32(tag); 1208 1209 if (IS_SPCV_12G(pm8001_ha->pdev)) 1210 page_code = THERMAL_PAGE_CODE_7H; 1211 else 1212 page_code = THERMAL_PAGE_CODE_8H; 1213 1214 payload.cfg_pg[0] = 1215 cpu_to_le32((THERMAL_LOG_ENABLE << 9) | 1216 (THERMAL_ENABLE << 8) | page_code); 1217 payload.cfg_pg[1] = 1218 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8)); 1219 1220 pm8001_dbg(pm8001_ha, DEV, 1221 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1222 payload.cfg_pg[0], payload.cfg_pg[1]); 1223 1224 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1225 sizeof(payload), 0); 1226 if (rc) 1227 pm8001_tag_free(pm8001_ha, tag); 1228 return rc; 1229 1230 } 1231 1232 /** 1233 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1234 * Timer configuration page 1235 * @pm8001_ha: our hba card information. 1236 */ 1237 static int 1238 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1239 { 1240 struct set_ctrl_cfg_req payload; 1241 SASProtocolTimerConfig_t SASConfigPage; 1242 int rc; 1243 u32 tag; 1244 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1245 1246 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1247 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1248 1249 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1250 if (rc) 1251 return rc; 1252 1253 payload.tag = cpu_to_le32(tag); 1254 1255 SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE); 1256 SASConfigPage.MST_MSI = cpu_to_le32(3 << 15); 1257 SASConfigPage.STP_SSP_MCT_TMO = 1258 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO); 1259 SASConfigPage.STP_FRM_TMO = 1260 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) | 1261 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER); 1262 SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME); 1263 1264 SASConfigPage.OPNRJT_RTRY_INTVL = 1265 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL); 1266 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = 1267 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO); 1268 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = 1269 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR); 1270 SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP); 1271 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1273 le32_to_cpu(SASConfigPage.pageCode)); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1275 le32_to_cpu(SASConfigPage.MST_MSI)); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1277 le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO)); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1279 le32_to_cpu(SASConfigPage.STP_FRM_TMO)); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1281 le32_to_cpu(SASConfigPage.STP_IDLE_TMO)); 1282 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1283 le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL)); 1284 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1285 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 1286 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1287 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 1288 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1289 le32_to_cpu(SASConfigPage.MAX_AIP)); 1290 1291 memcpy(&payload.cfg_pg, &SASConfigPage, 1292 sizeof(SASProtocolTimerConfig_t)); 1293 1294 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1295 sizeof(payload), 0); 1296 if (rc) 1297 pm8001_tag_free(pm8001_ha, tag); 1298 1299 return rc; 1300 } 1301 1302 /** 1303 * pm80xx_get_encrypt_info - Check for encryption 1304 * @pm8001_ha: our hba card information. 1305 */ 1306 static int 1307 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1308 { 1309 u32 scratch3_value; 1310 int ret = -1; 1311 1312 /* Read encryption status from SCRATCH PAD 3 */ 1313 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1314 1315 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1316 SCRATCH_PAD3_ENC_READY) { 1317 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1318 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1319 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1320 SCRATCH_PAD3_SMF_ENABLED) 1321 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1322 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1323 SCRATCH_PAD3_SMA_ENABLED) 1324 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1325 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1326 SCRATCH_PAD3_SMB_ENABLED) 1327 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1328 pm8001_ha->encrypt_info.status = 0; 1329 pm8001_dbg(pm8001_ha, INIT, 1330 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1331 scratch3_value, 1332 pm8001_ha->encrypt_info.cipher_mode, 1333 pm8001_ha->encrypt_info.sec_mode, 1334 pm8001_ha->encrypt_info.status); 1335 ret = 0; 1336 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1337 SCRATCH_PAD3_ENC_DISABLED) { 1338 pm8001_dbg(pm8001_ha, INIT, 1339 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1340 scratch3_value); 1341 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1342 pm8001_ha->encrypt_info.cipher_mode = 0; 1343 pm8001_ha->encrypt_info.sec_mode = 0; 1344 ret = 0; 1345 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1346 SCRATCH_PAD3_ENC_DIS_ERR) { 1347 pm8001_ha->encrypt_info.status = 1348 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1349 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1350 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1351 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1352 SCRATCH_PAD3_SMF_ENABLED) 1353 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1354 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1355 SCRATCH_PAD3_SMA_ENABLED) 1356 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1357 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1358 SCRATCH_PAD3_SMB_ENABLED) 1359 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1360 pm8001_dbg(pm8001_ha, INIT, 1361 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1362 scratch3_value, 1363 pm8001_ha->encrypt_info.cipher_mode, 1364 pm8001_ha->encrypt_info.sec_mode, 1365 pm8001_ha->encrypt_info.status); 1366 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1367 SCRATCH_PAD3_ENC_ENA_ERR) { 1368 1369 pm8001_ha->encrypt_info.status = 1370 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1371 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1372 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1373 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1374 SCRATCH_PAD3_SMF_ENABLED) 1375 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1376 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1377 SCRATCH_PAD3_SMA_ENABLED) 1378 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1379 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1380 SCRATCH_PAD3_SMB_ENABLED) 1381 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1382 1383 pm8001_dbg(pm8001_ha, INIT, 1384 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1385 scratch3_value, 1386 pm8001_ha->encrypt_info.cipher_mode, 1387 pm8001_ha->encrypt_info.sec_mode, 1388 pm8001_ha->encrypt_info.status); 1389 } 1390 return ret; 1391 } 1392 1393 /** 1394 * pm80xx_encrypt_update - update flash with encryption information 1395 * @pm8001_ha: our hba card information. 1396 */ 1397 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1398 { 1399 struct kek_mgmt_req payload; 1400 int rc; 1401 u32 tag; 1402 u32 opc = OPC_INB_KEK_MANAGEMENT; 1403 1404 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1405 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1406 if (rc) 1407 return rc; 1408 1409 payload.tag = cpu_to_le32(tag); 1410 /* Currently only one key is used. New KEK index is 1. 1411 * Current KEK index is 1. Store KEK to NVRAM is 1. 1412 */ 1413 payload.new_curidx_ksop = 1414 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) | 1415 KEK_MGMT_SUBOP_KEYCARDUPDATE)); 1416 1417 pm8001_dbg(pm8001_ha, DEV, 1418 "Saving Encryption info to flash. payload 0x%x\n", 1419 le32_to_cpu(payload.new_curidx_ksop)); 1420 1421 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 1422 sizeof(payload), 0); 1423 if (rc) 1424 pm8001_tag_free(pm8001_ha, tag); 1425 1426 return rc; 1427 } 1428 1429 /** 1430 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip. 1431 * @pm8001_ha: our hba card information 1432 */ 1433 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1434 { 1435 int ret; 1436 u8 i = 0; 1437 1438 /* check the firmware status */ 1439 if (-1 == check_fw_ready(pm8001_ha)) { 1440 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1441 return -EBUSY; 1442 } 1443 1444 /* Initialize the controller fatal error flag */ 1445 pm8001_ha->controller_fatal_error = false; 1446 1447 /* Initialize pci space address eg: mpi offset */ 1448 ret = init_pci_device_addresses(pm8001_ha); 1449 if (ret) { 1450 pm8001_dbg(pm8001_ha, FAIL, 1451 "Failed to init pci addresses"); 1452 return ret; 1453 } 1454 init_default_table_values(pm8001_ha); 1455 read_main_config_table(pm8001_ha); 1456 read_general_status_table(pm8001_ha); 1457 read_inbnd_queue_table(pm8001_ha); 1458 read_outbnd_queue_table(pm8001_ha); 1459 read_phy_attr_table(pm8001_ha); 1460 1461 /* update main config table ,inbound table and outbound table */ 1462 update_main_config_table(pm8001_ha); 1463 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1464 update_inbnd_queue_table(pm8001_ha, i); 1465 update_outbnd_queue_table(pm8001_ha, i); 1466 } 1467 /* notify firmware update finished and check initialization status */ 1468 if (0 == mpi_init_check(pm8001_ha)) { 1469 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1470 } else 1471 return -EBUSY; 1472 1473 return 0; 1474 } 1475 1476 static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha) 1477 { 1478 /* send SAS protocol timer configuration page to FW */ 1479 pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1480 1481 /* Check for encryption */ 1482 if (pm8001_ha->chip->encrypt) { 1483 int ret; 1484 1485 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1486 ret = pm80xx_get_encrypt_info(pm8001_ha); 1487 if (ret == -1) { 1488 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1489 if (pm8001_ha->encrypt_info.status == 0x81) { 1490 pm8001_dbg(pm8001_ha, INIT, 1491 "Encryption enabled with error.Saving encryption key to flash\n"); 1492 pm80xx_encrypt_update(pm8001_ha); 1493 } 1494 } 1495 } 1496 } 1497 1498 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1499 { 1500 u32 max_wait_count; 1501 u32 value; 1502 u32 gst_len_mpistate; 1503 int ret; 1504 1505 ret = init_pci_device_addresses(pm8001_ha); 1506 if (ret) { 1507 pm8001_dbg(pm8001_ha, FAIL, 1508 "Failed to init pci addresses"); 1509 return ret; 1510 } 1511 1512 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1513 table is stop */ 1514 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1515 1516 /* wait until Inbound DoorBell Clear Register toggled */ 1517 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1518 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1519 } else { 1520 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1521 } 1522 do { 1523 msleep(FW_READY_INTERVAL); 1524 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1525 value &= SPCv_MSGU_CFG_TABLE_RESET; 1526 } while ((value != 0) && (--max_wait_count)); 1527 1528 if (!max_wait_count) { 1529 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1530 return -1; 1531 } 1532 1533 /* check the MPI-State for termination in progress */ 1534 /* wait until Inbound DoorBell Clear Register toggled */ 1535 max_wait_count = 100; /* 2 sec for spcv/ve */ 1536 do { 1537 msleep(FW_READY_INTERVAL); 1538 gst_len_mpistate = 1539 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1540 GST_GSTLEN_MPIS_OFFSET); 1541 if (GST_MPI_STATE_UNINIT == 1542 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1543 break; 1544 } while (--max_wait_count); 1545 if (!max_wait_count) { 1546 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1547 gst_len_mpistate & GST_MPI_STATE_MASK); 1548 return -1; 1549 } 1550 1551 return 0; 1552 } 1553 1554 /** 1555 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors 1556 * @pm8001_ha: our hba card information 1557 * 1558 * Fatal errors are recoverable only after a host reboot. 1559 */ 1560 int 1561 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1562 { 1563 int ret = 0; 1564 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 1565 MSGU_SCRATCH_PAD_RSVD_0); 1566 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 1567 MSGU_SCRATCH_PAD_RSVD_1); 1568 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1569 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1570 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1571 1572 if (pm8001_ha->chip_id != chip_8006 && 1573 pm8001_ha->chip_id != chip_8074 && 1574 pm8001_ha->chip_id != chip_8076) { 1575 return 0; 1576 } 1577 1578 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1579 pm8001_dbg(pm8001_ha, FAIL, 1580 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1581 scratch_pad1, scratch_pad2, scratch_pad3, 1582 scratch_pad_rsvd0, scratch_pad_rsvd1); 1583 ret = 1; 1584 } 1585 1586 return ret; 1587 } 1588 1589 /** 1590 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all 1591 * FW register status are reset to the originated status. 1592 * @pm8001_ha: our hba card information 1593 */ 1594 1595 static int 1596 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1597 { 1598 u32 regval; 1599 u32 bootloader_state; 1600 u32 ibutton0, ibutton1; 1601 1602 /* Process MPI table uninitialization only if FW is ready */ 1603 if (!pm8001_ha->controller_fatal_error) { 1604 /* Check if MPI is in ready state to reset */ 1605 if (mpi_uninit_check(pm8001_ha) != 0) { 1606 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1607 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1608 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1609 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1610 pm8001_dbg(pm8001_ha, FAIL, 1611 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1612 r0, r1, r2, r3); 1613 /* if things aren't ready but the bootloader is ok then 1614 * try the reset anyway. 1615 */ 1616 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1617 return -1; 1618 } 1619 } 1620 /* checked for reset register normal state; 0x0 */ 1621 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1622 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1623 regval); 1624 1625 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1626 msleep(500); 1627 1628 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1629 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1630 regval); 1631 1632 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1633 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1634 pm8001_dbg(pm8001_ha, MSG, 1635 " soft reset successful [regval: 0x%x]\n", 1636 regval); 1637 } else { 1638 pm8001_dbg(pm8001_ha, MSG, 1639 " soft reset failed [regval: 0x%x]\n", 1640 regval); 1641 1642 /* check bootloader is successfully executed or in HDA mode */ 1643 bootloader_state = 1644 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1645 SCRATCH_PAD1_BOOTSTATE_MASK; 1646 1647 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1648 pm8001_dbg(pm8001_ha, MSG, 1649 "Bootloader state - HDA mode SEEPROM\n"); 1650 } else if (bootloader_state == 1651 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1652 pm8001_dbg(pm8001_ha, MSG, 1653 "Bootloader state - HDA mode Bootstrap Pin\n"); 1654 } else if (bootloader_state == 1655 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1656 pm8001_dbg(pm8001_ha, MSG, 1657 "Bootloader state - HDA mode soft reset\n"); 1658 } else if (bootloader_state == 1659 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1660 pm8001_dbg(pm8001_ha, MSG, 1661 "Bootloader state-HDA mode critical error\n"); 1662 } 1663 return -EBUSY; 1664 } 1665 1666 /* check the firmware status after reset */ 1667 if (-1 == check_fw_ready(pm8001_ha)) { 1668 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1669 /* check iButton feature support for motherboard controller */ 1670 if (pm8001_ha->pdev->subsystem_vendor != 1671 PCI_VENDOR_ID_ADAPTEC2 && 1672 pm8001_ha->pdev->subsystem_vendor != 1673 PCI_VENDOR_ID_ATTO && 1674 pm8001_ha->pdev->subsystem_vendor != 0) { 1675 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1676 MSGU_SCRATCH_PAD_RSVD_0); 1677 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1678 MSGU_SCRATCH_PAD_RSVD_1); 1679 if (!ibutton0 && !ibutton1) { 1680 pm8001_dbg(pm8001_ha, FAIL, 1681 "iButton Feature is not Available!!!\n"); 1682 return -EBUSY; 1683 } 1684 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1685 pm8001_dbg(pm8001_ha, FAIL, 1686 "CRC Check for iButton Feature Failed!!!\n"); 1687 return -EBUSY; 1688 } 1689 } 1690 } 1691 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1692 return 0; 1693 } 1694 1695 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1696 { 1697 u32 i; 1698 1699 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1700 1701 /* do SPCv chip reset. */ 1702 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1703 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1704 1705 /* Check this ..whether delay is required or no */ 1706 /* delay 10 usec */ 1707 udelay(10); 1708 1709 /* wait for 20 msec until the firmware gets reloaded */ 1710 i = 20; 1711 do { 1712 mdelay(1); 1713 } while ((--i) != 0); 1714 1715 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1716 } 1717 1718 /** 1719 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt 1720 * @pm8001_ha: our hba card information 1721 * @vec: interrupt number to enable 1722 */ 1723 static void 1724 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1725 { 1726 if (!pm8001_ha->use_msix) { 1727 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1728 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1729 return; 1730 } 1731 1732 if (vec < 32) 1733 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); 1734 else 1735 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32)); 1736 } 1737 1738 /** 1739 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt 1740 * @pm8001_ha: our hba card information 1741 * @vec: interrupt number to disable 1742 */ 1743 static void 1744 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1745 { 1746 if (!pm8001_ha->use_msix) { 1747 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1748 return; 1749 } 1750 1751 if (vec == 0xFF) { 1752 /* disable all vectors 0-31, 32-63 */ 1753 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); 1754 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); 1755 } else if (vec < 32) { 1756 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); 1757 } else { 1758 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32)); 1759 } 1760 } 1761 1762 /** 1763 * mpi_ssp_completion - process the event that FW response to the SSP request. 1764 * @pm8001_ha: our hba card information 1765 * @piomb: the message contents of this outbound message. 1766 * 1767 * When FW has completed a ssp request for example a IO request, after it has 1768 * filled the SG data with the data, it will trigger this event representing 1769 * that he has finished the job; please check the corresponding buffer. 1770 * So we will tell the caller who maybe waiting the result to tell upper layer 1771 * that the task has been finished. 1772 */ 1773 static void 1774 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1775 { 1776 struct sas_task *t; 1777 struct pm8001_ccb_info *ccb; 1778 unsigned long flags; 1779 u32 status; 1780 u32 param; 1781 u32 tag; 1782 struct ssp_completion_resp *psspPayload; 1783 struct task_status_struct *ts; 1784 struct ssp_response_iu *iu; 1785 struct pm8001_device *pm8001_dev; 1786 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1787 status = le32_to_cpu(psspPayload->status); 1788 tag = le32_to_cpu(psspPayload->tag); 1789 ccb = &pm8001_ha->ccb_info[tag]; 1790 if ((status == IO_ABORTED) && ccb->open_retry) { 1791 /* Being completed by another */ 1792 ccb->open_retry = 0; 1793 return; 1794 } 1795 pm8001_dev = ccb->device; 1796 param = le32_to_cpu(psspPayload->param); 1797 t = ccb->task; 1798 1799 if (status && status != IO_UNDERFLOW) 1800 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1801 if (unlikely(!t || !t->lldd_task || !t->dev)) 1802 return; 1803 ts = &t->task_status; 1804 1805 pm8001_dbg(pm8001_ha, DEV, 1806 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1807 1808 /* Print sas address of IO failed device */ 1809 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1810 (status != IO_UNDERFLOW)) 1811 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1812 SAS_ADDR(t->dev->sas_addr)); 1813 1814 switch (status) { 1815 case IO_SUCCESS: 1816 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1817 param); 1818 if (param == 0) { 1819 ts->resp = SAS_TASK_COMPLETE; 1820 ts->stat = SAS_SAM_STAT_GOOD; 1821 } else { 1822 ts->resp = SAS_TASK_COMPLETE; 1823 ts->stat = SAS_PROTO_RESPONSE; 1824 ts->residual = param; 1825 iu = &psspPayload->ssp_resp_iu; 1826 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1827 } 1828 if (pm8001_dev) 1829 atomic_dec(&pm8001_dev->running_req); 1830 break; 1831 case IO_ABORTED: 1832 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1833 ts->resp = SAS_TASK_COMPLETE; 1834 ts->stat = SAS_ABORTED_TASK; 1835 if (pm8001_dev) 1836 atomic_dec(&pm8001_dev->running_req); 1837 break; 1838 case IO_UNDERFLOW: 1839 /* SSP Completion with error */ 1840 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1841 param); 1842 ts->resp = SAS_TASK_COMPLETE; 1843 ts->stat = SAS_DATA_UNDERRUN; 1844 ts->residual = param; 1845 if (pm8001_dev) 1846 atomic_dec(&pm8001_dev->running_req); 1847 break; 1848 case IO_NO_DEVICE: 1849 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1850 ts->resp = SAS_TASK_UNDELIVERED; 1851 ts->stat = SAS_PHY_DOWN; 1852 if (pm8001_dev) 1853 atomic_dec(&pm8001_dev->running_req); 1854 break; 1855 case IO_XFER_ERROR_BREAK: 1856 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1857 ts->resp = SAS_TASK_COMPLETE; 1858 ts->stat = SAS_OPEN_REJECT; 1859 /* Force the midlayer to retry */ 1860 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1861 if (pm8001_dev) 1862 atomic_dec(&pm8001_dev->running_req); 1863 break; 1864 case IO_XFER_ERROR_PHY_NOT_READY: 1865 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1866 ts->resp = SAS_TASK_COMPLETE; 1867 ts->stat = SAS_OPEN_REJECT; 1868 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1869 if (pm8001_dev) 1870 atomic_dec(&pm8001_dev->running_req); 1871 break; 1872 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1873 pm8001_dbg(pm8001_ha, IO, 1874 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 1875 ts->resp = SAS_TASK_COMPLETE; 1876 ts->stat = SAS_OPEN_REJECT; 1877 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1878 if (pm8001_dev) 1879 atomic_dec(&pm8001_dev->running_req); 1880 break; 1881 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1882 pm8001_dbg(pm8001_ha, IO, 1883 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1884 ts->resp = SAS_TASK_COMPLETE; 1885 ts->stat = SAS_OPEN_REJECT; 1886 ts->open_rej_reason = SAS_OREJ_EPROTO; 1887 if (pm8001_dev) 1888 atomic_dec(&pm8001_dev->running_req); 1889 break; 1890 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1891 pm8001_dbg(pm8001_ha, IO, 1892 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1893 ts->resp = SAS_TASK_COMPLETE; 1894 ts->stat = SAS_OPEN_REJECT; 1895 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1896 if (pm8001_dev) 1897 atomic_dec(&pm8001_dev->running_req); 1898 break; 1899 case IO_OPEN_CNX_ERROR_BREAK: 1900 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1901 ts->resp = SAS_TASK_COMPLETE; 1902 ts->stat = SAS_OPEN_REJECT; 1903 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1904 if (pm8001_dev) 1905 atomic_dec(&pm8001_dev->running_req); 1906 break; 1907 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1908 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1909 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1910 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1911 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1912 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1913 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1914 ts->resp = SAS_TASK_COMPLETE; 1915 ts->stat = SAS_OPEN_REJECT; 1916 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1917 if (!t->uldd_task) 1918 pm8001_handle_event(pm8001_ha, 1919 pm8001_dev, 1920 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1921 break; 1922 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1923 pm8001_dbg(pm8001_ha, IO, 1924 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 1925 ts->resp = SAS_TASK_COMPLETE; 1926 ts->stat = SAS_OPEN_REJECT; 1927 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1928 if (pm8001_dev) 1929 atomic_dec(&pm8001_dev->running_req); 1930 break; 1931 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1932 pm8001_dbg(pm8001_ha, IO, 1933 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 1934 ts->resp = SAS_TASK_COMPLETE; 1935 ts->stat = SAS_OPEN_REJECT; 1936 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1937 if (pm8001_dev) 1938 atomic_dec(&pm8001_dev->running_req); 1939 break; 1940 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1941 pm8001_dbg(pm8001_ha, IO, 1942 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 1943 ts->resp = SAS_TASK_UNDELIVERED; 1944 ts->stat = SAS_OPEN_REJECT; 1945 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1946 if (pm8001_dev) 1947 atomic_dec(&pm8001_dev->running_req); 1948 break; 1949 case IO_XFER_ERROR_NAK_RECEIVED: 1950 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 1951 ts->resp = SAS_TASK_COMPLETE; 1952 ts->stat = SAS_OPEN_REJECT; 1953 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1954 if (pm8001_dev) 1955 atomic_dec(&pm8001_dev->running_req); 1956 break; 1957 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1958 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 1959 ts->resp = SAS_TASK_COMPLETE; 1960 ts->stat = SAS_NAK_R_ERR; 1961 if (pm8001_dev) 1962 atomic_dec(&pm8001_dev->running_req); 1963 break; 1964 case IO_XFER_ERROR_DMA: 1965 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 1966 ts->resp = SAS_TASK_COMPLETE; 1967 ts->stat = SAS_OPEN_REJECT; 1968 if (pm8001_dev) 1969 atomic_dec(&pm8001_dev->running_req); 1970 break; 1971 case IO_XFER_OPEN_RETRY_TIMEOUT: 1972 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1973 ts->resp = SAS_TASK_COMPLETE; 1974 ts->stat = SAS_OPEN_REJECT; 1975 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1976 if (pm8001_dev) 1977 atomic_dec(&pm8001_dev->running_req); 1978 break; 1979 case IO_XFER_ERROR_OFFSET_MISMATCH: 1980 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 1981 ts->resp = SAS_TASK_COMPLETE; 1982 ts->stat = SAS_OPEN_REJECT; 1983 if (pm8001_dev) 1984 atomic_dec(&pm8001_dev->running_req); 1985 break; 1986 case IO_PORT_IN_RESET: 1987 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 1988 ts->resp = SAS_TASK_COMPLETE; 1989 ts->stat = SAS_OPEN_REJECT; 1990 if (pm8001_dev) 1991 atomic_dec(&pm8001_dev->running_req); 1992 break; 1993 case IO_DS_NON_OPERATIONAL: 1994 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 1995 ts->resp = SAS_TASK_COMPLETE; 1996 ts->stat = SAS_OPEN_REJECT; 1997 if (!t->uldd_task) 1998 pm8001_handle_event(pm8001_ha, 1999 pm8001_dev, 2000 IO_DS_NON_OPERATIONAL); 2001 break; 2002 case IO_DS_IN_RECOVERY: 2003 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2004 ts->resp = SAS_TASK_COMPLETE; 2005 ts->stat = SAS_OPEN_REJECT; 2006 if (pm8001_dev) 2007 atomic_dec(&pm8001_dev->running_req); 2008 break; 2009 case IO_TM_TAG_NOT_FOUND: 2010 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2011 ts->resp = SAS_TASK_COMPLETE; 2012 ts->stat = SAS_OPEN_REJECT; 2013 if (pm8001_dev) 2014 atomic_dec(&pm8001_dev->running_req); 2015 break; 2016 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2017 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2018 ts->resp = SAS_TASK_COMPLETE; 2019 ts->stat = SAS_OPEN_REJECT; 2020 if (pm8001_dev) 2021 atomic_dec(&pm8001_dev->running_req); 2022 break; 2023 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2024 pm8001_dbg(pm8001_ha, IO, 2025 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2026 ts->resp = SAS_TASK_COMPLETE; 2027 ts->stat = SAS_OPEN_REJECT; 2028 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2029 if (pm8001_dev) 2030 atomic_dec(&pm8001_dev->running_req); 2031 break; 2032 default: 2033 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2034 /* not allowed case. Therefore, return failed status */ 2035 ts->resp = SAS_TASK_COMPLETE; 2036 ts->stat = SAS_OPEN_REJECT; 2037 if (pm8001_dev) 2038 atomic_dec(&pm8001_dev->running_req); 2039 break; 2040 } 2041 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n", 2042 psspPayload->ssp_resp_iu.status); 2043 spin_lock_irqsave(&t->task_state_lock, flags); 2044 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2045 t->task_state_flags |= SAS_TASK_STATE_DONE; 2046 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2047 spin_unlock_irqrestore(&t->task_state_lock, flags); 2048 pm8001_dbg(pm8001_ha, FAIL, 2049 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2050 t, status, ts->resp, ts->stat); 2051 pm8001_ccb_task_free(pm8001_ha, ccb); 2052 if (t->slow_task) 2053 complete(&t->slow_task->completion); 2054 } else { 2055 spin_unlock_irqrestore(&t->task_state_lock, flags); 2056 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2057 } 2058 } 2059 2060 /*See the comments for mpi_ssp_completion */ 2061 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2062 { 2063 struct sas_task *t; 2064 unsigned long flags; 2065 struct task_status_struct *ts; 2066 struct pm8001_ccb_info *ccb; 2067 struct pm8001_device *pm8001_dev; 2068 struct ssp_event_resp *psspPayload = 2069 (struct ssp_event_resp *)(piomb + 4); 2070 u32 event = le32_to_cpu(psspPayload->event); 2071 u32 tag = le32_to_cpu(psspPayload->tag); 2072 u32 port_id = le32_to_cpu(psspPayload->port_id); 2073 2074 ccb = &pm8001_ha->ccb_info[tag]; 2075 t = ccb->task; 2076 pm8001_dev = ccb->device; 2077 if (event) 2078 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2079 if (unlikely(!t || !t->lldd_task || !t->dev)) 2080 return; 2081 ts = &t->task_status; 2082 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2083 port_id, tag, event); 2084 switch (event) { 2085 case IO_OVERFLOW: 2086 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2087 ts->resp = SAS_TASK_COMPLETE; 2088 ts->stat = SAS_DATA_OVERRUN; 2089 ts->residual = 0; 2090 if (pm8001_dev) 2091 atomic_dec(&pm8001_dev->running_req); 2092 break; 2093 case IO_XFER_ERROR_BREAK: 2094 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2095 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2096 return; 2097 case IO_XFER_ERROR_PHY_NOT_READY: 2098 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2099 ts->resp = SAS_TASK_COMPLETE; 2100 ts->stat = SAS_OPEN_REJECT; 2101 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2102 break; 2103 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2104 pm8001_dbg(pm8001_ha, IO, 2105 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_OPEN_REJECT; 2108 ts->open_rej_reason = SAS_OREJ_EPROTO; 2109 break; 2110 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2111 pm8001_dbg(pm8001_ha, IO, 2112 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2113 ts->resp = SAS_TASK_COMPLETE; 2114 ts->stat = SAS_OPEN_REJECT; 2115 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2116 break; 2117 case IO_OPEN_CNX_ERROR_BREAK: 2118 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2119 ts->resp = SAS_TASK_COMPLETE; 2120 ts->stat = SAS_OPEN_REJECT; 2121 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2122 break; 2123 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2124 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2125 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2126 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2127 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2128 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2129 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2130 ts->resp = SAS_TASK_COMPLETE; 2131 ts->stat = SAS_OPEN_REJECT; 2132 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2133 if (!t->uldd_task) 2134 pm8001_handle_event(pm8001_ha, 2135 pm8001_dev, 2136 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2137 break; 2138 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2139 pm8001_dbg(pm8001_ha, IO, 2140 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2141 ts->resp = SAS_TASK_COMPLETE; 2142 ts->stat = SAS_OPEN_REJECT; 2143 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2144 break; 2145 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2146 pm8001_dbg(pm8001_ha, IO, 2147 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2148 ts->resp = SAS_TASK_COMPLETE; 2149 ts->stat = SAS_OPEN_REJECT; 2150 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2151 break; 2152 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2153 pm8001_dbg(pm8001_ha, IO, 2154 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2155 ts->resp = SAS_TASK_COMPLETE; 2156 ts->stat = SAS_OPEN_REJECT; 2157 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2158 break; 2159 case IO_XFER_ERROR_NAK_RECEIVED: 2160 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2161 ts->resp = SAS_TASK_COMPLETE; 2162 ts->stat = SAS_OPEN_REJECT; 2163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2164 break; 2165 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2166 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2167 ts->resp = SAS_TASK_COMPLETE; 2168 ts->stat = SAS_NAK_R_ERR; 2169 break; 2170 case IO_XFER_OPEN_RETRY_TIMEOUT: 2171 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2172 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2173 return; 2174 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2175 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2176 ts->resp = SAS_TASK_COMPLETE; 2177 ts->stat = SAS_DATA_OVERRUN; 2178 break; 2179 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2180 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2181 ts->resp = SAS_TASK_COMPLETE; 2182 ts->stat = SAS_DATA_OVERRUN; 2183 break; 2184 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2185 pm8001_dbg(pm8001_ha, IO, 2186 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2187 ts->resp = SAS_TASK_COMPLETE; 2188 ts->stat = SAS_DATA_OVERRUN; 2189 break; 2190 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2191 pm8001_dbg(pm8001_ha, IO, 2192 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2193 ts->resp = SAS_TASK_COMPLETE; 2194 ts->stat = SAS_DATA_OVERRUN; 2195 break; 2196 case IO_XFER_ERROR_OFFSET_MISMATCH: 2197 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2198 ts->resp = SAS_TASK_COMPLETE; 2199 ts->stat = SAS_DATA_OVERRUN; 2200 break; 2201 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2202 pm8001_dbg(pm8001_ha, IO, 2203 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2204 ts->resp = SAS_TASK_COMPLETE; 2205 ts->stat = SAS_DATA_OVERRUN; 2206 break; 2207 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2208 pm8001_dbg(pm8001_ha, IOERR, 2209 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2210 /* TBC: used default set values */ 2211 ts->resp = SAS_TASK_COMPLETE; 2212 ts->stat = SAS_DATA_OVERRUN; 2213 break; 2214 case IO_XFER_CMD_FRAME_ISSUED: 2215 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2216 return; 2217 default: 2218 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2219 /* not allowed case. Therefore, return failed status */ 2220 ts->resp = SAS_TASK_COMPLETE; 2221 ts->stat = SAS_DATA_OVERRUN; 2222 break; 2223 } 2224 spin_lock_irqsave(&t->task_state_lock, flags); 2225 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2226 t->task_state_flags |= SAS_TASK_STATE_DONE; 2227 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2228 spin_unlock_irqrestore(&t->task_state_lock, flags); 2229 pm8001_dbg(pm8001_ha, FAIL, 2230 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2231 t, event, ts->resp, ts->stat); 2232 pm8001_ccb_task_free(pm8001_ha, ccb); 2233 } else { 2234 spin_unlock_irqrestore(&t->task_state_lock, flags); 2235 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2236 } 2237 } 2238 2239 /*See the comments for mpi_ssp_completion */ 2240 static void 2241 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, 2242 struct outbound_queue_table *circularQ, void *piomb) 2243 { 2244 struct sas_task *t; 2245 struct pm8001_ccb_info *ccb; 2246 u32 param; 2247 u32 status; 2248 u32 tag; 2249 int i, j, ata_tag = -1; 2250 u8 sata_addr_low[4]; 2251 u32 temp_sata_addr_low, temp_sata_addr_hi; 2252 u8 sata_addr_hi[4]; 2253 struct sata_completion_resp *psataPayload; 2254 struct task_status_struct *ts; 2255 struct ata_task_resp *resp ; 2256 u32 *sata_resp; 2257 struct pm8001_device *pm8001_dev; 2258 unsigned long flags; 2259 struct ata_queued_cmd *qc; 2260 2261 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2262 status = le32_to_cpu(psataPayload->status); 2263 param = le32_to_cpu(psataPayload->param); 2264 tag = le32_to_cpu(psataPayload->tag); 2265 2266 ccb = &pm8001_ha->ccb_info[tag]; 2267 t = ccb->task; 2268 pm8001_dev = ccb->device; 2269 2270 if (t) { 2271 if (t->dev && (t->dev->lldd_dev)) { 2272 pm8001_dev = t->dev->lldd_dev; 2273 qc = t->uldd_task; 2274 ata_tag = qc ? qc->tag : -1; 2275 } 2276 } else { 2277 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2278 ccb->ccb_tag); 2279 pm8001_ccb_free(pm8001_ha, ccb); 2280 return; 2281 } 2282 2283 if (pm8001_dev && unlikely(!t->lldd_task || !t->dev)) 2284 return; 2285 2286 ts = &t->task_status; 2287 if (status != IO_SUCCESS) { 2288 pm8001_dbg(pm8001_ha, FAIL, 2289 "IO failed status %#x pm80xx tag %#x ata tag %d\n", 2290 status, tag, ata_tag); 2291 } 2292 2293 /* Print sas address of IO failed device */ 2294 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2295 (status != IO_UNDERFLOW)) { 2296 if (!((t->dev->parent) && 2297 (dev_is_expander(t->dev->parent->dev_type)))) { 2298 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) 2299 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2300 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) 2301 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2302 memcpy(&temp_sata_addr_low, sata_addr_low, 2303 sizeof(sata_addr_low)); 2304 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2305 sizeof(sata_addr_hi)); 2306 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2307 |((temp_sata_addr_hi << 8) & 2308 0xff0000) | 2309 ((temp_sata_addr_hi >> 8) 2310 & 0xff00) | 2311 ((temp_sata_addr_hi << 24) & 2312 0xff000000)); 2313 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2314 & 0xff) | 2315 ((temp_sata_addr_low << 8) 2316 & 0xff0000) | 2317 ((temp_sata_addr_low >> 8) 2318 & 0xff00) | 2319 ((temp_sata_addr_low << 24) 2320 & 0xff000000)) + 2321 pm8001_dev->attached_phy + 2322 0x10); 2323 pm8001_dbg(pm8001_ha, FAIL, 2324 "SAS Address of IO Failure Drive:%08x%08x\n", 2325 temp_sata_addr_hi, 2326 temp_sata_addr_low); 2327 2328 } else { 2329 pm8001_dbg(pm8001_ha, FAIL, 2330 "SAS Address of IO Failure Drive:%016llx\n", 2331 SAS_ADDR(t->dev->sas_addr)); 2332 } 2333 } 2334 switch (status) { 2335 case IO_SUCCESS: 2336 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2337 if (param == 0) { 2338 ts->resp = SAS_TASK_COMPLETE; 2339 ts->stat = SAS_SAM_STAT_GOOD; 2340 } else { 2341 u8 len; 2342 ts->resp = SAS_TASK_COMPLETE; 2343 ts->stat = SAS_PROTO_RESPONSE; 2344 ts->residual = param; 2345 pm8001_dbg(pm8001_ha, IO, 2346 "SAS_PROTO_RESPONSE len = %d\n", 2347 param); 2348 sata_resp = &psataPayload->sata_resp[0]; 2349 resp = (struct ata_task_resp *)ts->buf; 2350 if (t->ata_task.dma_xfer == 0 && 2351 t->data_dir == DMA_FROM_DEVICE) { 2352 len = sizeof(struct pio_setup_fis); 2353 pm8001_dbg(pm8001_ha, IO, 2354 "PIO read len = %d\n", len); 2355 } else if (t->ata_task.use_ncq && 2356 t->data_dir != DMA_NONE) { 2357 len = sizeof(struct set_dev_bits_fis); 2358 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2359 len); 2360 } else { 2361 len = sizeof(struct dev_to_host_fis); 2362 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2363 len); 2364 } 2365 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2366 resp->frame_len = len; 2367 memcpy(&resp->ending_fis[0], sata_resp, len); 2368 ts->buf_valid_size = sizeof(*resp); 2369 } else 2370 pm8001_dbg(pm8001_ha, IO, 2371 "response too large\n"); 2372 } 2373 if (pm8001_dev) 2374 atomic_dec(&pm8001_dev->running_req); 2375 break; 2376 case IO_ABORTED: 2377 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2378 ts->resp = SAS_TASK_COMPLETE; 2379 ts->stat = SAS_ABORTED_TASK; 2380 if (pm8001_dev) 2381 atomic_dec(&pm8001_dev->running_req); 2382 break; 2383 /* following cases are to do cases */ 2384 case IO_UNDERFLOW: 2385 /* SATA Completion with error */ 2386 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2387 ts->resp = SAS_TASK_COMPLETE; 2388 ts->stat = SAS_DATA_UNDERRUN; 2389 ts->residual = param; 2390 if (pm8001_dev) 2391 atomic_dec(&pm8001_dev->running_req); 2392 break; 2393 case IO_NO_DEVICE: 2394 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2395 ts->resp = SAS_TASK_UNDELIVERED; 2396 ts->stat = SAS_PHY_DOWN; 2397 if (pm8001_dev) 2398 atomic_dec(&pm8001_dev->running_req); 2399 break; 2400 case IO_XFER_ERROR_BREAK: 2401 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2402 ts->resp = SAS_TASK_COMPLETE; 2403 ts->stat = SAS_INTERRUPTED; 2404 if (pm8001_dev) 2405 atomic_dec(&pm8001_dev->running_req); 2406 break; 2407 case IO_XFER_ERROR_PHY_NOT_READY: 2408 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2409 ts->resp = SAS_TASK_COMPLETE; 2410 ts->stat = SAS_OPEN_REJECT; 2411 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2412 if (pm8001_dev) 2413 atomic_dec(&pm8001_dev->running_req); 2414 break; 2415 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2416 pm8001_dbg(pm8001_ha, IO, 2417 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2418 ts->resp = SAS_TASK_COMPLETE; 2419 ts->stat = SAS_OPEN_REJECT; 2420 ts->open_rej_reason = SAS_OREJ_EPROTO; 2421 if (pm8001_dev) 2422 atomic_dec(&pm8001_dev->running_req); 2423 break; 2424 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2425 pm8001_dbg(pm8001_ha, IO, 2426 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2427 ts->resp = SAS_TASK_COMPLETE; 2428 ts->stat = SAS_OPEN_REJECT; 2429 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2430 if (pm8001_dev) 2431 atomic_dec(&pm8001_dev->running_req); 2432 break; 2433 case IO_OPEN_CNX_ERROR_BREAK: 2434 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2435 ts->resp = SAS_TASK_COMPLETE; 2436 ts->stat = SAS_OPEN_REJECT; 2437 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2438 if (pm8001_dev) 2439 atomic_dec(&pm8001_dev->running_req); 2440 break; 2441 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2442 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2443 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2444 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2445 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2446 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2447 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2448 ts->resp = SAS_TASK_COMPLETE; 2449 ts->stat = SAS_DEV_NO_RESPONSE; 2450 if (!t->uldd_task) { 2451 pm8001_handle_event(pm8001_ha, 2452 pm8001_dev, 2453 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2454 ts->resp = SAS_TASK_UNDELIVERED; 2455 ts->stat = SAS_QUEUE_FULL; 2456 spin_unlock_irqrestore(&circularQ->oq_lock, 2457 circularQ->lock_flags); 2458 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2459 spin_lock_irqsave(&circularQ->oq_lock, 2460 circularQ->lock_flags); 2461 return; 2462 } 2463 break; 2464 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2465 pm8001_dbg(pm8001_ha, IO, 2466 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2467 ts->resp = SAS_TASK_UNDELIVERED; 2468 ts->stat = SAS_OPEN_REJECT; 2469 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2470 if (!t->uldd_task) { 2471 pm8001_handle_event(pm8001_ha, 2472 pm8001_dev, 2473 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2474 ts->resp = SAS_TASK_UNDELIVERED; 2475 ts->stat = SAS_QUEUE_FULL; 2476 spin_unlock_irqrestore(&circularQ->oq_lock, 2477 circularQ->lock_flags); 2478 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2479 spin_lock_irqsave(&circularQ->oq_lock, 2480 circularQ->lock_flags); 2481 return; 2482 } 2483 break; 2484 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2485 pm8001_dbg(pm8001_ha, IO, 2486 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2487 ts->resp = SAS_TASK_COMPLETE; 2488 ts->stat = SAS_OPEN_REJECT; 2489 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2490 if (pm8001_dev) 2491 atomic_dec(&pm8001_dev->running_req); 2492 break; 2493 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2494 pm8001_dbg(pm8001_ha, IO, 2495 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2496 ts->resp = SAS_TASK_COMPLETE; 2497 ts->stat = SAS_DEV_NO_RESPONSE; 2498 if (!t->uldd_task) { 2499 pm8001_handle_event(pm8001_ha, 2500 pm8001_dev, 2501 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2502 ts->resp = SAS_TASK_UNDELIVERED; 2503 ts->stat = SAS_QUEUE_FULL; 2504 spin_unlock_irqrestore(&circularQ->oq_lock, 2505 circularQ->lock_flags); 2506 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2507 spin_lock_irqsave(&circularQ->oq_lock, 2508 circularQ->lock_flags); 2509 return; 2510 } 2511 break; 2512 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2513 pm8001_dbg(pm8001_ha, IO, 2514 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2515 ts->resp = SAS_TASK_COMPLETE; 2516 ts->stat = SAS_OPEN_REJECT; 2517 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2518 if (pm8001_dev) 2519 atomic_dec(&pm8001_dev->running_req); 2520 break; 2521 case IO_XFER_ERROR_NAK_RECEIVED: 2522 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2523 ts->resp = SAS_TASK_COMPLETE; 2524 ts->stat = SAS_NAK_R_ERR; 2525 if (pm8001_dev) 2526 atomic_dec(&pm8001_dev->running_req); 2527 break; 2528 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2529 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2530 ts->resp = SAS_TASK_COMPLETE; 2531 ts->stat = SAS_NAK_R_ERR; 2532 if (pm8001_dev) 2533 atomic_dec(&pm8001_dev->running_req); 2534 break; 2535 case IO_XFER_ERROR_DMA: 2536 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2537 ts->resp = SAS_TASK_COMPLETE; 2538 ts->stat = SAS_ABORTED_TASK; 2539 if (pm8001_dev) 2540 atomic_dec(&pm8001_dev->running_req); 2541 break; 2542 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2543 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2544 ts->resp = SAS_TASK_UNDELIVERED; 2545 ts->stat = SAS_DEV_NO_RESPONSE; 2546 if (pm8001_dev) 2547 atomic_dec(&pm8001_dev->running_req); 2548 break; 2549 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2550 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2551 ts->resp = SAS_TASK_COMPLETE; 2552 ts->stat = SAS_DATA_UNDERRUN; 2553 if (pm8001_dev) 2554 atomic_dec(&pm8001_dev->running_req); 2555 break; 2556 case IO_XFER_OPEN_RETRY_TIMEOUT: 2557 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2558 ts->resp = SAS_TASK_COMPLETE; 2559 ts->stat = SAS_OPEN_TO; 2560 if (pm8001_dev) 2561 atomic_dec(&pm8001_dev->running_req); 2562 break; 2563 case IO_PORT_IN_RESET: 2564 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2565 ts->resp = SAS_TASK_COMPLETE; 2566 ts->stat = SAS_DEV_NO_RESPONSE; 2567 if (pm8001_dev) 2568 atomic_dec(&pm8001_dev->running_req); 2569 break; 2570 case IO_DS_NON_OPERATIONAL: 2571 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2572 ts->resp = SAS_TASK_COMPLETE; 2573 ts->stat = SAS_DEV_NO_RESPONSE; 2574 if (!t->uldd_task) { 2575 pm8001_handle_event(pm8001_ha, pm8001_dev, 2576 IO_DS_NON_OPERATIONAL); 2577 ts->resp = SAS_TASK_UNDELIVERED; 2578 ts->stat = SAS_QUEUE_FULL; 2579 spin_unlock_irqrestore(&circularQ->oq_lock, 2580 circularQ->lock_flags); 2581 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2582 spin_lock_irqsave(&circularQ->oq_lock, 2583 circularQ->lock_flags); 2584 return; 2585 } 2586 break; 2587 case IO_DS_IN_RECOVERY: 2588 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2589 ts->resp = SAS_TASK_COMPLETE; 2590 ts->stat = SAS_DEV_NO_RESPONSE; 2591 if (pm8001_dev) 2592 atomic_dec(&pm8001_dev->running_req); 2593 break; 2594 case IO_DS_IN_ERROR: 2595 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2596 ts->resp = SAS_TASK_COMPLETE; 2597 ts->stat = SAS_DEV_NO_RESPONSE; 2598 if (!t->uldd_task) { 2599 pm8001_handle_event(pm8001_ha, pm8001_dev, 2600 IO_DS_IN_ERROR); 2601 ts->resp = SAS_TASK_UNDELIVERED; 2602 ts->stat = SAS_QUEUE_FULL; 2603 spin_unlock_irqrestore(&circularQ->oq_lock, 2604 circularQ->lock_flags); 2605 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2606 spin_lock_irqsave(&circularQ->oq_lock, 2607 circularQ->lock_flags); 2608 return; 2609 } 2610 break; 2611 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2612 pm8001_dbg(pm8001_ha, IO, 2613 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2614 ts->resp = SAS_TASK_COMPLETE; 2615 ts->stat = SAS_OPEN_REJECT; 2616 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2617 if (pm8001_dev) 2618 atomic_dec(&pm8001_dev->running_req); 2619 break; 2620 default: 2621 pm8001_dbg(pm8001_ha, DEVIO, 2622 "Unknown status device_id %u status 0x%x tag %d\n", 2623 pm8001_dev->device_id, status, tag); 2624 /* not allowed case. Therefore, return failed status */ 2625 ts->resp = SAS_TASK_COMPLETE; 2626 ts->stat = SAS_DEV_NO_RESPONSE; 2627 if (pm8001_dev) 2628 atomic_dec(&pm8001_dev->running_req); 2629 break; 2630 } 2631 spin_lock_irqsave(&t->task_state_lock, flags); 2632 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2633 t->task_state_flags |= SAS_TASK_STATE_DONE; 2634 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2635 spin_unlock_irqrestore(&t->task_state_lock, flags); 2636 pm8001_dbg(pm8001_ha, FAIL, 2637 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2638 t, status, ts->resp, ts->stat); 2639 pm8001_ccb_task_free(pm8001_ha, ccb); 2640 if (t->slow_task) 2641 complete(&t->slow_task->completion); 2642 } else { 2643 spin_unlock_irqrestore(&t->task_state_lock, flags); 2644 spin_unlock_irqrestore(&circularQ->oq_lock, 2645 circularQ->lock_flags); 2646 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2647 spin_lock_irqsave(&circularQ->oq_lock, 2648 circularQ->lock_flags); 2649 } 2650 } 2651 2652 /*See the comments for mpi_ssp_completion */ 2653 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, 2654 struct outbound_queue_table *circularQ, void *piomb) 2655 { 2656 struct sas_task *t; 2657 struct task_status_struct *ts; 2658 struct pm8001_ccb_info *ccb; 2659 struct pm8001_device *pm8001_dev; 2660 struct sata_event_resp *psataPayload = 2661 (struct sata_event_resp *)(piomb + 4); 2662 u32 event = le32_to_cpu(psataPayload->event); 2663 u32 tag = le32_to_cpu(psataPayload->tag); 2664 u32 port_id = le32_to_cpu(psataPayload->port_id); 2665 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2666 2667 if (event) 2668 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2669 2670 /* Check if this is NCQ error */ 2671 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2672 /* tag value is invalid with this event */ 2673 pm8001_dbg(pm8001_ha, FAIL, "NCQ ERROR for device %#x tag %#x\n", 2674 dev_id, tag); 2675 2676 /* find device using device id */ 2677 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2678 /* send read log extension by aborting the link - libata does what we want */ 2679 if (pm8001_dev) { 2680 pm80xx_show_pending_commands(pm8001_ha, pm8001_dev); 2681 pm8001_handle_event(pm8001_ha, 2682 pm8001_dev, 2683 IO_XFER_ERROR_ABORTED_NCQ_MODE); 2684 } 2685 return; 2686 } 2687 2688 ccb = &pm8001_ha->ccb_info[tag]; 2689 t = ccb->task; 2690 pm8001_dev = ccb->device; 2691 if (unlikely(!t)) { 2692 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2693 ccb->ccb_tag); 2694 pm8001_ccb_free(pm8001_ha, ccb); 2695 return; 2696 } 2697 2698 if (unlikely(!t->lldd_task || !t->dev)) 2699 return; 2700 2701 ts = &t->task_status; 2702 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2703 port_id, tag, event); 2704 switch (event) { 2705 case IO_OVERFLOW: 2706 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2707 ts->resp = SAS_TASK_COMPLETE; 2708 ts->stat = SAS_DATA_OVERRUN; 2709 ts->residual = 0; 2710 break; 2711 case IO_XFER_ERROR_BREAK: 2712 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2713 ts->resp = SAS_TASK_COMPLETE; 2714 ts->stat = SAS_INTERRUPTED; 2715 break; 2716 case IO_XFER_ERROR_PHY_NOT_READY: 2717 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2718 ts->resp = SAS_TASK_COMPLETE; 2719 ts->stat = SAS_OPEN_REJECT; 2720 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2721 break; 2722 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2723 pm8001_dbg(pm8001_ha, IO, 2724 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2725 ts->resp = SAS_TASK_COMPLETE; 2726 ts->stat = SAS_OPEN_REJECT; 2727 ts->open_rej_reason = SAS_OREJ_EPROTO; 2728 break; 2729 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2730 pm8001_dbg(pm8001_ha, IO, 2731 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2732 ts->resp = SAS_TASK_COMPLETE; 2733 ts->stat = SAS_OPEN_REJECT; 2734 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2735 break; 2736 case IO_OPEN_CNX_ERROR_BREAK: 2737 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2738 ts->resp = SAS_TASK_COMPLETE; 2739 ts->stat = SAS_OPEN_REJECT; 2740 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2741 break; 2742 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2743 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2744 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2745 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2746 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2747 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2748 pm8001_dbg(pm8001_ha, FAIL, 2749 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2750 ts->resp = SAS_TASK_UNDELIVERED; 2751 ts->stat = SAS_DEV_NO_RESPONSE; 2752 if (!t->uldd_task) { 2753 pm8001_handle_event(pm8001_ha, 2754 pm8001_dev, 2755 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2756 ts->resp = SAS_TASK_COMPLETE; 2757 ts->stat = SAS_QUEUE_FULL; 2758 return; 2759 } 2760 break; 2761 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2762 pm8001_dbg(pm8001_ha, IO, 2763 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2764 ts->resp = SAS_TASK_UNDELIVERED; 2765 ts->stat = SAS_OPEN_REJECT; 2766 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2767 break; 2768 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2769 pm8001_dbg(pm8001_ha, IO, 2770 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2771 ts->resp = SAS_TASK_COMPLETE; 2772 ts->stat = SAS_OPEN_REJECT; 2773 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2774 break; 2775 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2776 pm8001_dbg(pm8001_ha, IO, 2777 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2778 ts->resp = SAS_TASK_COMPLETE; 2779 ts->stat = SAS_OPEN_REJECT; 2780 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2781 break; 2782 case IO_XFER_ERROR_NAK_RECEIVED: 2783 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2784 ts->resp = SAS_TASK_COMPLETE; 2785 ts->stat = SAS_NAK_R_ERR; 2786 break; 2787 case IO_XFER_ERROR_PEER_ABORTED: 2788 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2789 ts->resp = SAS_TASK_COMPLETE; 2790 ts->stat = SAS_NAK_R_ERR; 2791 break; 2792 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2793 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2794 ts->resp = SAS_TASK_COMPLETE; 2795 ts->stat = SAS_DATA_UNDERRUN; 2796 break; 2797 case IO_XFER_OPEN_RETRY_TIMEOUT: 2798 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2799 ts->resp = SAS_TASK_COMPLETE; 2800 ts->stat = SAS_OPEN_TO; 2801 break; 2802 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2803 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2804 ts->resp = SAS_TASK_COMPLETE; 2805 ts->stat = SAS_OPEN_TO; 2806 break; 2807 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2808 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2809 ts->resp = SAS_TASK_COMPLETE; 2810 ts->stat = SAS_OPEN_TO; 2811 break; 2812 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2813 pm8001_dbg(pm8001_ha, IO, 2814 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2815 ts->resp = SAS_TASK_COMPLETE; 2816 ts->stat = SAS_OPEN_TO; 2817 break; 2818 case IO_XFER_ERROR_OFFSET_MISMATCH: 2819 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2820 ts->resp = SAS_TASK_COMPLETE; 2821 ts->stat = SAS_OPEN_TO; 2822 break; 2823 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2824 pm8001_dbg(pm8001_ha, IO, 2825 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2826 ts->resp = SAS_TASK_COMPLETE; 2827 ts->stat = SAS_OPEN_TO; 2828 break; 2829 case IO_XFER_CMD_FRAME_ISSUED: 2830 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2831 break; 2832 case IO_XFER_PIO_SETUP_ERROR: 2833 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2834 ts->resp = SAS_TASK_COMPLETE; 2835 ts->stat = SAS_OPEN_TO; 2836 break; 2837 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2838 pm8001_dbg(pm8001_ha, FAIL, 2839 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2840 /* TBC: used default set values */ 2841 ts->resp = SAS_TASK_COMPLETE; 2842 ts->stat = SAS_OPEN_TO; 2843 break; 2844 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2845 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2846 /* TBC: used default set values */ 2847 ts->resp = SAS_TASK_COMPLETE; 2848 ts->stat = SAS_OPEN_TO; 2849 break; 2850 default: 2851 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2852 /* not allowed case. Therefore, return failed status */ 2853 ts->resp = SAS_TASK_COMPLETE; 2854 ts->stat = SAS_OPEN_TO; 2855 break; 2856 } 2857 } 2858 2859 /*See the comments for mpi_ssp_completion */ 2860 static void 2861 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2862 { 2863 u32 param, i; 2864 struct sas_task *t; 2865 struct pm8001_ccb_info *ccb; 2866 unsigned long flags; 2867 u32 status; 2868 u32 tag; 2869 struct smp_completion_resp *psmpPayload; 2870 struct task_status_struct *ts; 2871 struct pm8001_device *pm8001_dev; 2872 2873 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2874 status = le32_to_cpu(psmpPayload->status); 2875 tag = le32_to_cpu(psmpPayload->tag); 2876 2877 ccb = &pm8001_ha->ccb_info[tag]; 2878 param = le32_to_cpu(psmpPayload->param); 2879 t = ccb->task; 2880 ts = &t->task_status; 2881 pm8001_dev = ccb->device; 2882 if (status) 2883 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2884 if (unlikely(!t || !t->lldd_task || !t->dev)) 2885 return; 2886 2887 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 2888 2889 switch (status) { 2890 2891 case IO_SUCCESS: 2892 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2893 ts->resp = SAS_TASK_COMPLETE; 2894 ts->stat = SAS_SAM_STAT_GOOD; 2895 if (pm8001_dev) 2896 atomic_dec(&pm8001_dev->running_req); 2897 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2898 struct scatterlist *sg_resp = &t->smp_task.smp_resp; 2899 u8 *payload; 2900 void *to; 2901 2902 pm8001_dbg(pm8001_ha, IO, 2903 "DIRECT RESPONSE Length:%d\n", 2904 param); 2905 to = kmap_atomic(sg_page(sg_resp)); 2906 payload = to + sg_resp->offset; 2907 for (i = 0; i < param; i++) { 2908 *(payload + i) = psmpPayload->_r_a[i]; 2909 pm8001_dbg(pm8001_ha, IO, 2910 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2911 i, *(payload + i), 2912 psmpPayload->_r_a[i]); 2913 } 2914 kunmap_atomic(to); 2915 } 2916 break; 2917 case IO_ABORTED: 2918 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 2919 ts->resp = SAS_TASK_COMPLETE; 2920 ts->stat = SAS_ABORTED_TASK; 2921 if (pm8001_dev) 2922 atomic_dec(&pm8001_dev->running_req); 2923 break; 2924 case IO_OVERFLOW: 2925 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2926 ts->resp = SAS_TASK_COMPLETE; 2927 ts->stat = SAS_DATA_OVERRUN; 2928 ts->residual = 0; 2929 if (pm8001_dev) 2930 atomic_dec(&pm8001_dev->running_req); 2931 break; 2932 case IO_NO_DEVICE: 2933 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2934 ts->resp = SAS_TASK_COMPLETE; 2935 ts->stat = SAS_PHY_DOWN; 2936 break; 2937 case IO_ERROR_HW_TIMEOUT: 2938 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 2939 ts->resp = SAS_TASK_COMPLETE; 2940 ts->stat = SAS_SAM_STAT_BUSY; 2941 break; 2942 case IO_XFER_ERROR_BREAK: 2943 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2944 ts->resp = SAS_TASK_COMPLETE; 2945 ts->stat = SAS_SAM_STAT_BUSY; 2946 break; 2947 case IO_XFER_ERROR_PHY_NOT_READY: 2948 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2949 ts->resp = SAS_TASK_COMPLETE; 2950 ts->stat = SAS_SAM_STAT_BUSY; 2951 break; 2952 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2953 pm8001_dbg(pm8001_ha, IO, 2954 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2955 ts->resp = SAS_TASK_COMPLETE; 2956 ts->stat = SAS_OPEN_REJECT; 2957 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2958 break; 2959 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2960 pm8001_dbg(pm8001_ha, IO, 2961 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2962 ts->resp = SAS_TASK_COMPLETE; 2963 ts->stat = SAS_OPEN_REJECT; 2964 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2965 break; 2966 case IO_OPEN_CNX_ERROR_BREAK: 2967 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2968 ts->resp = SAS_TASK_COMPLETE; 2969 ts->stat = SAS_OPEN_REJECT; 2970 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2971 break; 2972 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2973 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2974 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2975 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2976 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2977 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2978 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2979 ts->resp = SAS_TASK_COMPLETE; 2980 ts->stat = SAS_OPEN_REJECT; 2981 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2982 pm8001_handle_event(pm8001_ha, 2983 pm8001_dev, 2984 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2985 break; 2986 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2987 pm8001_dbg(pm8001_ha, IO, 2988 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2989 ts->resp = SAS_TASK_COMPLETE; 2990 ts->stat = SAS_OPEN_REJECT; 2991 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2992 break; 2993 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2994 pm8001_dbg(pm8001_ha, IO, 2995 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2996 ts->resp = SAS_TASK_COMPLETE; 2997 ts->stat = SAS_OPEN_REJECT; 2998 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2999 break; 3000 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3001 pm8001_dbg(pm8001_ha, IO, 3002 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3003 ts->resp = SAS_TASK_COMPLETE; 3004 ts->stat = SAS_OPEN_REJECT; 3005 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3006 break; 3007 case IO_XFER_ERROR_RX_FRAME: 3008 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3009 ts->resp = SAS_TASK_COMPLETE; 3010 ts->stat = SAS_DEV_NO_RESPONSE; 3011 break; 3012 case IO_XFER_OPEN_RETRY_TIMEOUT: 3013 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3014 ts->resp = SAS_TASK_COMPLETE; 3015 ts->stat = SAS_OPEN_REJECT; 3016 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3017 break; 3018 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3019 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3020 ts->resp = SAS_TASK_COMPLETE; 3021 ts->stat = SAS_QUEUE_FULL; 3022 break; 3023 case IO_PORT_IN_RESET: 3024 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3025 ts->resp = SAS_TASK_COMPLETE; 3026 ts->stat = SAS_OPEN_REJECT; 3027 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3028 break; 3029 case IO_DS_NON_OPERATIONAL: 3030 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3031 ts->resp = SAS_TASK_COMPLETE; 3032 ts->stat = SAS_DEV_NO_RESPONSE; 3033 break; 3034 case IO_DS_IN_RECOVERY: 3035 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3036 ts->resp = SAS_TASK_COMPLETE; 3037 ts->stat = SAS_OPEN_REJECT; 3038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3039 break; 3040 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3041 pm8001_dbg(pm8001_ha, IO, 3042 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3043 ts->resp = SAS_TASK_COMPLETE; 3044 ts->stat = SAS_OPEN_REJECT; 3045 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3046 break; 3047 default: 3048 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3049 ts->resp = SAS_TASK_COMPLETE; 3050 ts->stat = SAS_DEV_NO_RESPONSE; 3051 /* not allowed case. Therefore, return failed status */ 3052 break; 3053 } 3054 spin_lock_irqsave(&t->task_state_lock, flags); 3055 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3056 t->task_state_flags |= SAS_TASK_STATE_DONE; 3057 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3058 spin_unlock_irqrestore(&t->task_state_lock, flags); 3059 pm8001_dbg(pm8001_ha, FAIL, 3060 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3061 t, status, ts->resp, ts->stat); 3062 pm8001_ccb_task_free(pm8001_ha, ccb); 3063 } else { 3064 spin_unlock_irqrestore(&t->task_state_lock, flags); 3065 pm8001_ccb_task_free(pm8001_ha, ccb); 3066 mb();/* in order to force CPU ordering */ 3067 t->task_done(t); 3068 } 3069 } 3070 3071 /** 3072 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW. 3073 * @pm8001_ha: our hba card information 3074 * @Qnum: the outbound queue message number. 3075 * @SEA: source of event to ack 3076 * @port_id: port id. 3077 * @phyId: phy id. 3078 * @param0: parameter 0. 3079 * @param1: parameter 1. 3080 */ 3081 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3082 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3083 { 3084 struct hw_event_ack_req payload; 3085 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3086 3087 memset((u8 *)&payload, 0, sizeof(payload)); 3088 payload.tag = cpu_to_le32(1); 3089 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3090 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3091 payload.param0 = cpu_to_le32(param0); 3092 payload.param1 = cpu_to_le32(param1); 3093 3094 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, 3095 sizeof(payload), 0); 3096 } 3097 3098 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3099 u32 phyId, u32 phy_op); 3100 3101 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3102 void *piomb) 3103 { 3104 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3105 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3106 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3107 u32 lr_status_evt_portid = 3108 le32_to_cpu(pPayload->lr_status_evt_portid); 3109 u8 deviceType = pPayload->sas_identify.dev_type; 3110 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3111 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3112 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3113 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3114 3115 if (deviceType == SAS_END_DEVICE) { 3116 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3117 PHY_NOTIFY_ENABLE_SPINUP); 3118 } 3119 3120 port->wide_port_phymap |= (1U << phy_id); 3121 pm8001_get_lrate_mode(phy, link_rate); 3122 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3123 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3124 phy->phy_attached = 1; 3125 } 3126 3127 /** 3128 * hw_event_sas_phy_up - FW tells me a SAS phy up event. 3129 * @pm8001_ha: our hba card information 3130 * @piomb: IO message buffer 3131 */ 3132 static void 3133 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3134 { 3135 struct hw_event_resp *pPayload = 3136 (struct hw_event_resp *)(piomb + 4); 3137 u32 lr_status_evt_portid = 3138 le32_to_cpu(pPayload->lr_status_evt_portid); 3139 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3140 3141 u8 link_rate = 3142 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3143 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3144 u8 phy_id = 3145 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3146 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3147 3148 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3149 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3150 unsigned long flags; 3151 u8 deviceType = pPayload->sas_identify.dev_type; 3152 phy->port = port; 3153 port->port_id = port_id; 3154 port->port_state = portstate; 3155 port->wide_port_phymap |= (1U << phy_id); 3156 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3157 pm8001_dbg(pm8001_ha, MSG, 3158 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3159 port_id, phy_id, link_rate, portstate, deviceType); 3160 3161 switch (deviceType) { 3162 case SAS_PHY_UNUSED: 3163 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3164 break; 3165 case SAS_END_DEVICE: 3166 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3167 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3168 PHY_NOTIFY_ENABLE_SPINUP); 3169 port->port_attached = 1; 3170 pm8001_get_lrate_mode(phy, link_rate); 3171 break; 3172 case SAS_EDGE_EXPANDER_DEVICE: 3173 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3174 port->port_attached = 1; 3175 pm8001_get_lrate_mode(phy, link_rate); 3176 break; 3177 case SAS_FANOUT_EXPANDER_DEVICE: 3178 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3179 port->port_attached = 1; 3180 pm8001_get_lrate_mode(phy, link_rate); 3181 break; 3182 default: 3183 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3184 deviceType); 3185 break; 3186 } 3187 phy->phy_type |= PORT_TYPE_SAS; 3188 phy->identify.device_type = deviceType; 3189 phy->phy_attached = 1; 3190 if (phy->identify.device_type == SAS_END_DEVICE) 3191 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3192 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3193 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3194 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3195 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3196 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3197 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3198 sizeof(struct sas_identify_frame)-4); 3199 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3200 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3201 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3202 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3203 mdelay(200); /* delay a moment to wait for disk to spin up */ 3204 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3205 } 3206 3207 /** 3208 * hw_event_sata_phy_up - FW tells me a SATA phy up event. 3209 * @pm8001_ha: our hba card information 3210 * @piomb: IO message buffer 3211 */ 3212 static void 3213 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3214 { 3215 struct hw_event_resp *pPayload = 3216 (struct hw_event_resp *)(piomb + 4); 3217 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3218 u32 lr_status_evt_portid = 3219 le32_to_cpu(pPayload->lr_status_evt_portid); 3220 u8 link_rate = 3221 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3222 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3223 u8 phy_id = 3224 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3225 3226 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3227 3228 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3229 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3230 unsigned long flags; 3231 pm8001_dbg(pm8001_ha, EVENT, 3232 "HW_EVENT_SATA_PHY_UP phyid:%#x port_id:%#x link_rate:%d portstate:%#x\n", 3233 phy_id, port_id, link_rate, portstate); 3234 3235 phy->port = port; 3236 port->port_id = port_id; 3237 port->port_state = portstate; 3238 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3239 port->port_attached = 1; 3240 pm8001_get_lrate_mode(phy, link_rate); 3241 phy->phy_type |= PORT_TYPE_SATA; 3242 phy->phy_attached = 1; 3243 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3244 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3245 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3246 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3247 sizeof(struct dev_to_host_fis)); 3248 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3249 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3250 phy->identify.device_type = SAS_SATA_DEV; 3251 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3252 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3253 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3254 } 3255 3256 /** 3257 * hw_event_phy_down - we should notify the libsas the phy is down. 3258 * @pm8001_ha: our hba card information 3259 * @piomb: IO message buffer 3260 */ 3261 static void 3262 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3263 { 3264 struct hw_event_resp *pPayload = 3265 (struct hw_event_resp *)(piomb + 4); 3266 3267 u32 lr_status_evt_portid = 3268 le32_to_cpu(pPayload->lr_status_evt_portid); 3269 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3270 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3271 u8 phy_id = 3272 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3273 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3274 3275 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3276 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3277 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3278 port->port_state = portstate; 3279 phy->identify.device_type = 0; 3280 phy->phy_attached = 0; 3281 switch (portstate) { 3282 case PORT_VALID: 3283 pm8001_dbg(pm8001_ha, EVENT, 3284 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_VALID\n", 3285 phy_id, port_id); 3286 break; 3287 case PORT_INVALID: 3288 pm8001_dbg(pm8001_ha, EVENT, 3289 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_INVALID\n", 3290 phy_id, port_id); 3291 pm8001_dbg(pm8001_ha, MSG, 3292 " Last phy Down and port invalid\n"); 3293 if (port_sata) { 3294 phy->phy_type = 0; 3295 port->port_attached = 0; 3296 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3297 port_id, phy_id, 0, 0); 3298 } 3299 sas_phy_disconnected(&phy->sas_phy); 3300 break; 3301 case PORT_IN_RESET: 3302 pm8001_dbg(pm8001_ha, EVENT, 3303 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_IN_RESET\n", 3304 phy_id, port_id); 3305 break; 3306 case PORT_NOT_ESTABLISHED: 3307 pm8001_dbg(pm8001_ha, EVENT, 3308 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_NOT_ESTABLISHED\n", 3309 phy_id, port_id); 3310 port->port_attached = 0; 3311 break; 3312 case PORT_LOSTCOMM: 3313 pm8001_dbg(pm8001_ha, EVENT, 3314 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_LOSTCOMM\n", 3315 phy_id, port_id); 3316 pm8001_dbg(pm8001_ha, MSG, " Last phy Down and port invalid\n"); 3317 if (port_sata) { 3318 port->port_attached = 0; 3319 phy->phy_type = 0; 3320 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3321 port_id, phy_id, 0, 0); 3322 } 3323 sas_phy_disconnected(&phy->sas_phy); 3324 break; 3325 default: 3326 port->port_attached = 0; 3327 pm8001_dbg(pm8001_ha, EVENT, 3328 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate:%#x\n", 3329 phy_id, port_id, portstate); 3330 break; 3331 3332 } 3333 if (port_sata && (portstate != PORT_IN_RESET)) 3334 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3335 GFP_ATOMIC); 3336 } 3337 3338 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3339 { 3340 struct phy_start_resp *pPayload = 3341 (struct phy_start_resp *)(piomb + 4); 3342 u32 status = 3343 le32_to_cpu(pPayload->status); 3344 u32 phy_id = 3345 le32_to_cpu(pPayload->phyid) & 0xFF; 3346 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3347 u32 tag = le32_to_cpu(pPayload->tag); 3348 3349 pm8001_dbg(pm8001_ha, INIT, 3350 "phy start resp status:0x%x, phyid:0x%x, tag 0x%x\n", 3351 status, phy_id, tag); 3352 if (status == 0) 3353 phy->phy_state = PHY_LINK_DOWN; 3354 3355 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3356 phy->enable_completion != NULL) { 3357 complete(phy->enable_completion); 3358 phy->enable_completion = NULL; 3359 } 3360 3361 pm8001_tag_free(pm8001_ha, tag); 3362 return 0; 3363 3364 } 3365 3366 /** 3367 * mpi_thermal_hw_event - a thermal hw event has come. 3368 * @pm8001_ha: our hba card information 3369 * @piomb: IO message buffer 3370 */ 3371 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3372 { 3373 struct thermal_hw_event *pPayload = 3374 (struct thermal_hw_event *)(piomb + 4); 3375 3376 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3377 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3378 3379 if (thermal_event & 0x40) { 3380 pm8001_dbg(pm8001_ha, IO, 3381 "Thermal Event: Local high temperature violated!\n"); 3382 pm8001_dbg(pm8001_ha, IO, 3383 "Thermal Event: Measured local high temperature %d\n", 3384 ((rht_lht & 0xFF00) >> 8)); 3385 } 3386 if (thermal_event & 0x10) { 3387 pm8001_dbg(pm8001_ha, IO, 3388 "Thermal Event: Remote high temperature violated!\n"); 3389 pm8001_dbg(pm8001_ha, IO, 3390 "Thermal Event: Measured remote high temperature %d\n", 3391 ((rht_lht & 0xFF000000) >> 24)); 3392 } 3393 return 0; 3394 } 3395 3396 /** 3397 * mpi_hw_event - The hw event has come. 3398 * @pm8001_ha: our hba card information 3399 * @piomb: IO message buffer 3400 */ 3401 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3402 { 3403 unsigned long flags, i; 3404 struct hw_event_resp *pPayload = 3405 (struct hw_event_resp *)(piomb + 4); 3406 u32 lr_status_evt_portid = 3407 le32_to_cpu(pPayload->lr_status_evt_portid); 3408 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3409 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3410 u8 phy_id = 3411 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3412 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3413 u16 eventType = 3414 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3415 u8 status = 3416 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3417 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3418 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3419 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3420 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3421 pm8001_dbg(pm8001_ha, DEV, 3422 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3423 port_id, phy_id, eventType, status); 3424 3425 switch (eventType) { 3426 3427 case HW_EVENT_SAS_PHY_UP: 3428 pm8001_dbg(pm8001_ha, EVENT, 3429 "HW_EVENT_SAS_PHY_UP phyid:%#x port_id:%#x\n", 3430 phy_id, port_id); 3431 hw_event_sas_phy_up(pm8001_ha, piomb); 3432 break; 3433 case HW_EVENT_SATA_PHY_UP: 3434 hw_event_sata_phy_up(pm8001_ha, piomb); 3435 break; 3436 case HW_EVENT_SATA_SPINUP_HOLD: 3437 pm8001_dbg(pm8001_ha, EVENT, 3438 "HW_EVENT_SATA_SPINUP_HOLD phyid:%#x port_id:%#x\n", 3439 phy_id, port_id); 3440 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3441 GFP_ATOMIC); 3442 break; 3443 case HW_EVENT_PHY_DOWN: 3444 hw_event_phy_down(pm8001_ha, piomb); 3445 phy->phy_state = PHY_LINK_DISABLE; 3446 break; 3447 case HW_EVENT_PORT_INVALID: 3448 pm8001_dbg(pm8001_ha, EVENT, 3449 "HW_EVENT_PORT_INVALID phyid:%#x port_id:%#x\n", 3450 phy_id, port_id); 3451 sas_phy_disconnected(sas_phy); 3452 phy->phy_attached = 0; 3453 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3454 GFP_ATOMIC); 3455 break; 3456 /* the broadcast change primitive received, tell the LIBSAS this event 3457 to revalidate the sas domain*/ 3458 case HW_EVENT_BROADCAST_CHANGE: 3459 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3460 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3461 port_id, phy_id, 1, 0); 3462 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3463 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3464 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3465 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3466 GFP_ATOMIC); 3467 break; 3468 case HW_EVENT_PHY_ERROR: 3469 pm8001_dbg(pm8001_ha, EVENT, 3470 "HW_EVENT_PHY_ERROR phyid:%#x port_id:%#x\n", 3471 phy_id, port_id); 3472 sas_phy_disconnected(&phy->sas_phy); 3473 phy->phy_attached = 0; 3474 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3475 break; 3476 case HW_EVENT_BROADCAST_EXP: 3477 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3478 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3479 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3480 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3481 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3482 GFP_ATOMIC); 3483 break; 3484 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3485 pm8001_dbg(pm8001_ha, EVENT, 3486 "HW_EVENT_LINK_ERR_INVALID_DWORD phyid:%#x port_id:%#x\n", 3487 phy_id, port_id); 3488 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3489 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3490 break; 3491 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3492 pm8001_dbg(pm8001_ha, EVENT, 3493 "HW_EVENT_LINK_ERR_DISPARITY_ERROR phyid:%#x port_id:%#x\n", 3494 phy_id, port_id); 3495 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3496 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3497 port_id, phy_id, 0, 0); 3498 break; 3499 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3500 pm8001_dbg(pm8001_ha, EVENT, 3501 "HW_EVENT_LINK_ERR_CODE_VIOLATION phyid:%#x port_id:%#x\n", 3502 phy_id, port_id); 3503 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3504 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3505 port_id, phy_id, 0, 0); 3506 break; 3507 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3508 pm8001_dbg(pm8001_ha, EVENT, 3509 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH phyid:%#x port_id:%#x\n", 3510 phy_id, port_id); 3511 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3512 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3513 port_id, phy_id, 0, 0); 3514 break; 3515 case HW_EVENT_MALFUNCTION: 3516 pm8001_dbg(pm8001_ha, EVENT, 3517 "HW_EVENT_MALFUNCTION phyid:%#x\n", phy_id); 3518 break; 3519 case HW_EVENT_BROADCAST_SES: 3520 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3521 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3522 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3523 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3524 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3525 GFP_ATOMIC); 3526 break; 3527 case HW_EVENT_INBOUND_CRC_ERROR: 3528 pm8001_dbg(pm8001_ha, EVENT, 3529 "HW_EVENT_INBOUND_CRC_ERROR phyid:%#x port_id:%#x\n", 3530 phy_id, port_id); 3531 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3532 HW_EVENT_INBOUND_CRC_ERROR, 3533 port_id, phy_id, 0, 0); 3534 break; 3535 case HW_EVENT_HARD_RESET_RECEIVED: 3536 pm8001_dbg(pm8001_ha, EVENT, 3537 "HW_EVENT_HARD_RESET_RECEIVED phyid:%#x\n", phy_id); 3538 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3539 break; 3540 case HW_EVENT_ID_FRAME_TIMEOUT: 3541 pm8001_dbg(pm8001_ha, EVENT, 3542 "HW_EVENT_ID_FRAME_TIMEOUT phyid:%#x\n", phy_id); 3543 sas_phy_disconnected(sas_phy); 3544 phy->phy_attached = 0; 3545 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3546 GFP_ATOMIC); 3547 break; 3548 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3549 pm8001_dbg(pm8001_ha, EVENT, 3550 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED phyid:%#x port_id:%#x\n", 3551 phy_id, port_id); 3552 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3553 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3554 port_id, phy_id, 0, 0); 3555 sas_phy_disconnected(sas_phy); 3556 phy->phy_attached = 0; 3557 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3558 GFP_ATOMIC); 3559 break; 3560 case HW_EVENT_PORT_RESET_TIMER_TMO: 3561 pm8001_dbg(pm8001_ha, EVENT, 3562 "HW_EVENT_PORT_RESET_TIMER_TMO phyid:%#x port_id:%#x portstate:%#x\n", 3563 phy_id, port_id, portstate); 3564 if (!pm8001_ha->phy[phy_id].reset_completion) { 3565 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3566 port_id, phy_id, 0, 0); 3567 } 3568 sas_phy_disconnected(sas_phy); 3569 phy->phy_attached = 0; 3570 port->port_state = portstate; 3571 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3572 GFP_ATOMIC); 3573 if (pm8001_ha->phy[phy_id].reset_completion) { 3574 pm8001_ha->phy[phy_id].port_reset_status = 3575 PORT_RESET_TMO; 3576 complete(pm8001_ha->phy[phy_id].reset_completion); 3577 pm8001_ha->phy[phy_id].reset_completion = NULL; 3578 } 3579 break; 3580 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3581 pm8001_dbg(pm8001_ha, EVENT, 3582 "HW_EVENT_PORT_RECOVERY_TIMER_TMO phyid:%#x port_id:%#x\n", 3583 phy_id, port_id); 3584 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3585 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3586 port_id, phy_id, 0, 0); 3587 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3588 if (port->wide_port_phymap & (1 << i)) { 3589 phy = &pm8001_ha->phy[i]; 3590 sas_notify_phy_event(&phy->sas_phy, 3591 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 3592 port->wide_port_phymap &= ~(1 << i); 3593 } 3594 } 3595 break; 3596 case HW_EVENT_PORT_RECOVER: 3597 pm8001_dbg(pm8001_ha, EVENT, 3598 "HW_EVENT_PORT_RECOVER phyid:%#x port_id:%#x\n", 3599 phy_id, port_id); 3600 hw_event_port_recover(pm8001_ha, piomb); 3601 break; 3602 case HW_EVENT_PORT_RESET_COMPLETE: 3603 pm8001_dbg(pm8001_ha, EVENT, 3604 "HW_EVENT_PORT_RESET_COMPLETE phyid:%#x port_id:%#x portstate:%#x\n", 3605 phy_id, port_id, portstate); 3606 if (pm8001_ha->phy[phy_id].reset_completion) { 3607 pm8001_ha->phy[phy_id].port_reset_status = 3608 PORT_RESET_SUCCESS; 3609 complete(pm8001_ha->phy[phy_id].reset_completion); 3610 pm8001_ha->phy[phy_id].reset_completion = NULL; 3611 } 3612 phy->phy_attached = 1; 3613 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3614 port->port_state = portstate; 3615 break; 3616 case EVENT_BROADCAST_ASYNCH_EVENT: 3617 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3618 break; 3619 default: 3620 pm8001_dbg(pm8001_ha, DEVIO, 3621 "Unknown event portid:%d phyid:%d event:0x%x status:0x%x\n", 3622 port_id, phy_id, eventType, status); 3623 break; 3624 } 3625 return 0; 3626 } 3627 3628 /** 3629 * mpi_phy_stop_resp - SPCv specific 3630 * @pm8001_ha: our hba card information 3631 * @piomb: IO message buffer 3632 */ 3633 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3634 { 3635 struct phy_stop_resp *pPayload = 3636 (struct phy_stop_resp *)(piomb + 4); 3637 u32 status = 3638 le32_to_cpu(pPayload->status); 3639 u32 phyid = 3640 le32_to_cpu(pPayload->phyid) & 0xFF; 3641 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3642 u32 tag = le32_to_cpu(pPayload->tag); 3643 3644 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x tag 0x%x\n", phyid, 3645 status, tag); 3646 if (status == PHY_STOP_SUCCESS || 3647 status == PHY_STOP_ERR_DEVICE_ATTACHED) { 3648 phy->phy_state = PHY_LINK_DISABLE; 3649 phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED; 3650 phy->sas_phy.linkrate = SAS_PHY_DISABLED; 3651 } 3652 3653 pm8001_tag_free(pm8001_ha, tag); 3654 return 0; 3655 } 3656 3657 /** 3658 * mpi_set_controller_config_resp - SPCv specific 3659 * @pm8001_ha: our hba card information 3660 * @piomb: IO message buffer 3661 */ 3662 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3663 void *piomb) 3664 { 3665 struct set_ctrl_cfg_resp *pPayload = 3666 (struct set_ctrl_cfg_resp *)(piomb + 4); 3667 u32 status = le32_to_cpu(pPayload->status); 3668 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3669 u32 tag = le32_to_cpu(pPayload->tag); 3670 3671 pm8001_dbg(pm8001_ha, MSG, 3672 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x tag 0x%x\n", 3673 status, err_qlfr_pgcd, tag); 3674 pm8001_tag_free(pm8001_ha, tag); 3675 return 0; 3676 } 3677 3678 /** 3679 * mpi_get_controller_config_resp - SPCv specific 3680 * @pm8001_ha: our hba card information 3681 * @piomb: IO message buffer 3682 */ 3683 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3684 void *piomb) 3685 { 3686 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3687 3688 return 0; 3689 } 3690 3691 /** 3692 * mpi_get_phy_profile_resp - SPCv specific 3693 * @pm8001_ha: our hba card information 3694 * @piomb: IO message buffer 3695 */ 3696 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3697 void *piomb) 3698 { 3699 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3700 3701 return 0; 3702 } 3703 3704 /** 3705 * mpi_flash_op_ext_resp - SPCv specific 3706 * @pm8001_ha: our hba card information 3707 * @piomb: IO message buffer 3708 */ 3709 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3710 { 3711 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3712 3713 return 0; 3714 } 3715 3716 /** 3717 * mpi_set_phy_profile_resp - SPCv specific 3718 * @pm8001_ha: our hba card information 3719 * @piomb: IO message buffer 3720 */ 3721 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3722 void *piomb) 3723 { 3724 u32 tag; 3725 u8 page_code; 3726 int rc = 0; 3727 struct set_phy_profile_resp *pPayload = 3728 (struct set_phy_profile_resp *)(piomb + 4); 3729 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3730 u32 status = le32_to_cpu(pPayload->status); 3731 3732 tag = le32_to_cpu(pPayload->tag); 3733 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3734 if (status) { 3735 /* status is FAILED */ 3736 pm8001_dbg(pm8001_ha, FAIL, 3737 "PhyProfile command failed with status 0x%08X\n", 3738 status); 3739 rc = -1; 3740 } else { 3741 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3742 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3743 page_code); 3744 rc = -1; 3745 } 3746 } 3747 pm8001_tag_free(pm8001_ha, tag); 3748 return rc; 3749 } 3750 3751 /** 3752 * mpi_kek_management_resp - SPCv specific 3753 * @pm8001_ha: our hba card information 3754 * @piomb: IO message buffer 3755 */ 3756 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3757 void *piomb) 3758 { 3759 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3760 3761 u32 status = le32_to_cpu(pPayload->status); 3762 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3763 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3764 3765 pm8001_dbg(pm8001_ha, MSG, 3766 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3767 status, kidx_new_curr_ksop, err_qlfr); 3768 3769 return 0; 3770 } 3771 3772 /** 3773 * mpi_dek_management_resp - SPCv specific 3774 * @pm8001_ha: our hba card information 3775 * @piomb: IO message buffer 3776 */ 3777 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3778 void *piomb) 3779 { 3780 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3781 3782 return 0; 3783 } 3784 3785 /** 3786 * ssp_coalesced_comp_resp - SPCv specific 3787 * @pm8001_ha: our hba card information 3788 * @piomb: IO message buffer 3789 */ 3790 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3791 void *piomb) 3792 { 3793 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3794 3795 return 0; 3796 } 3797 3798 /** 3799 * process_one_iomb - process one outbound Queue memory block 3800 * @pm8001_ha: our hba card information 3801 * @circularQ: outbound circular queue 3802 * @piomb: IO message buffer 3803 */ 3804 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, 3805 struct outbound_queue_table *circularQ, void *piomb) 3806 { 3807 __le32 pHeader = *(__le32 *)piomb; 3808 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3809 3810 switch (opc) { 3811 case OPC_OUB_ECHO: 3812 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3813 break; 3814 case OPC_OUB_HW_EVENT: 3815 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3816 mpi_hw_event(pm8001_ha, piomb); 3817 break; 3818 case OPC_OUB_THERM_HW_EVENT: 3819 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3820 mpi_thermal_hw_event(pm8001_ha, piomb); 3821 break; 3822 case OPC_OUB_SSP_COMP: 3823 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3824 mpi_ssp_completion(pm8001_ha, piomb); 3825 break; 3826 case OPC_OUB_SMP_COMP: 3827 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3828 mpi_smp_completion(pm8001_ha, piomb); 3829 break; 3830 case OPC_OUB_LOCAL_PHY_CNTRL: 3831 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3832 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3833 break; 3834 case OPC_OUB_DEV_REGIST: 3835 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3836 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3837 break; 3838 case OPC_OUB_DEREG_DEV: 3839 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3840 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3841 break; 3842 case OPC_OUB_GET_DEV_HANDLE: 3843 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3844 break; 3845 case OPC_OUB_SATA_COMP: 3846 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3847 mpi_sata_completion(pm8001_ha, circularQ, piomb); 3848 break; 3849 case OPC_OUB_SATA_EVENT: 3850 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3851 mpi_sata_event(pm8001_ha, circularQ, piomb); 3852 break; 3853 case OPC_OUB_SSP_EVENT: 3854 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3855 mpi_ssp_event(pm8001_ha, piomb); 3856 break; 3857 case OPC_OUB_DEV_HANDLE_ARRIV: 3858 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3859 /*This is for target*/ 3860 break; 3861 case OPC_OUB_SSP_RECV_EVENT: 3862 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3863 /*This is for target*/ 3864 break; 3865 case OPC_OUB_FW_FLASH_UPDATE: 3866 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3867 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3868 break; 3869 case OPC_OUB_GPIO_RESPONSE: 3870 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3871 break; 3872 case OPC_OUB_GPIO_EVENT: 3873 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3874 break; 3875 case OPC_OUB_GENERAL_EVENT: 3876 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3877 pm8001_mpi_general_event(pm8001_ha, piomb); 3878 break; 3879 case OPC_OUB_SSP_ABORT_RSP: 3880 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3881 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3882 break; 3883 case OPC_OUB_SATA_ABORT_RSP: 3884 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3885 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3886 break; 3887 case OPC_OUB_SAS_DIAG_MODE_START_END: 3888 pm8001_dbg(pm8001_ha, MSG, 3889 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3890 break; 3891 case OPC_OUB_SAS_DIAG_EXECUTE: 3892 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3893 break; 3894 case OPC_OUB_GET_TIME_STAMP: 3895 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3896 break; 3897 case OPC_OUB_SAS_HW_EVENT_ACK: 3898 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3899 break; 3900 case OPC_OUB_PORT_CONTROL: 3901 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3902 break; 3903 case OPC_OUB_SMP_ABORT_RSP: 3904 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3905 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3906 break; 3907 case OPC_OUB_GET_NVMD_DATA: 3908 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3909 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3910 break; 3911 case OPC_OUB_SET_NVMD_DATA: 3912 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3913 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3914 break; 3915 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3916 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3917 break; 3918 case OPC_OUB_SET_DEVICE_STATE: 3919 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3920 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3921 break; 3922 case OPC_OUB_GET_DEVICE_STATE: 3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 3924 break; 3925 case OPC_OUB_SET_DEV_INFO: 3926 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 3927 break; 3928 /* spcv specific commands */ 3929 case OPC_OUB_PHY_START_RESP: 3930 pm8001_dbg(pm8001_ha, MSG, 3931 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 3932 mpi_phy_start_resp(pm8001_ha, piomb); 3933 break; 3934 case OPC_OUB_PHY_STOP_RESP: 3935 pm8001_dbg(pm8001_ha, MSG, 3936 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 3937 mpi_phy_stop_resp(pm8001_ha, piomb); 3938 break; 3939 case OPC_OUB_SET_CONTROLLER_CONFIG: 3940 pm8001_dbg(pm8001_ha, MSG, 3941 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 3942 mpi_set_controller_config_resp(pm8001_ha, piomb); 3943 break; 3944 case OPC_OUB_GET_CONTROLLER_CONFIG: 3945 pm8001_dbg(pm8001_ha, MSG, 3946 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 3947 mpi_get_controller_config_resp(pm8001_ha, piomb); 3948 break; 3949 case OPC_OUB_GET_PHY_PROFILE: 3950 pm8001_dbg(pm8001_ha, MSG, 3951 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 3952 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3953 break; 3954 case OPC_OUB_FLASH_OP_EXT: 3955 pm8001_dbg(pm8001_ha, MSG, 3956 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 3957 mpi_flash_op_ext_resp(pm8001_ha, piomb); 3958 break; 3959 case OPC_OUB_SET_PHY_PROFILE: 3960 pm8001_dbg(pm8001_ha, MSG, 3961 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 3962 mpi_set_phy_profile_resp(pm8001_ha, piomb); 3963 break; 3964 case OPC_OUB_KEK_MANAGEMENT_RESP: 3965 pm8001_dbg(pm8001_ha, MSG, 3966 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 3967 mpi_kek_management_resp(pm8001_ha, piomb); 3968 break; 3969 case OPC_OUB_DEK_MANAGEMENT_RESP: 3970 pm8001_dbg(pm8001_ha, MSG, 3971 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 3972 mpi_dek_management_resp(pm8001_ha, piomb); 3973 break; 3974 case OPC_OUB_SSP_COALESCED_COMP_RESP: 3975 pm8001_dbg(pm8001_ha, MSG, 3976 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 3977 ssp_coalesced_comp_resp(pm8001_ha, piomb); 3978 break; 3979 default: 3980 pm8001_dbg(pm8001_ha, DEVIO, 3981 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 3982 break; 3983 } 3984 } 3985 3986 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 3987 { 3988 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 3989 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 3990 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 3991 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 3992 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 3993 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 3994 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 3995 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 3996 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 3997 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 3998 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 3999 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 4000 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4001 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 4002 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4003 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 4004 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4005 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 4006 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4007 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 4008 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4009 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0)); 4010 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4011 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1)); 4012 } 4013 4014 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4015 { 4016 struct outbound_queue_table *circularQ; 4017 void *pMsg1 = NULL; 4018 u8 bc; 4019 u32 ret = MPI_IO_STATUS_FAIL; 4020 u32 regval; 4021 4022 /* 4023 * Fatal errors are programmed to be signalled in irq vector 4024 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl. 4025 * fatal_err_interrupt 4026 */ 4027 if (vec == (pm8001_ha->max_q_num - 1)) { 4028 u32 mipsall_ready; 4029 4030 if (pm8001_ha->chip_id == chip_8008 || 4031 pm8001_ha->chip_id == chip_8009) 4032 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT; 4033 else 4034 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT; 4035 4036 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4037 if ((regval & mipsall_ready) != mipsall_ready) { 4038 pm8001_ha->controller_fatal_error = true; 4039 pm8001_dbg(pm8001_ha, FAIL, 4040 "Firmware Fatal error! Regval:0x%x\n", 4041 regval); 4042 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR); 4043 print_scratchpad_registers(pm8001_ha); 4044 return ret; 4045 } else { 4046 /*read scratchpad rsvd 0 register*/ 4047 regval = pm8001_cr32(pm8001_ha, 0, 4048 MSGU_SCRATCH_PAD_RSVD_0); 4049 switch (regval) { 4050 case NON_FATAL_SPBC_LBUS_ECC_ERR: 4051 case NON_FATAL_BDMA_ERR: 4052 case NON_FATAL_THERM_OVERTEMP_ERR: 4053 /*Clear the register*/ 4054 pm8001_cw32(pm8001_ha, 0, 4055 MSGU_SCRATCH_PAD_RSVD_0, 4056 0x00000000); 4057 break; 4058 default: 4059 break; 4060 } 4061 } 4062 } 4063 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4064 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags); 4065 do { 4066 /* spurious interrupt during setup if kexec-ing and 4067 * driver doing a doorbell access w/ the pre-kexec oq 4068 * interrupt setup. 4069 */ 4070 if (!circularQ->pi_virt) 4071 break; 4072 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4073 if (MPI_IO_STATUS_SUCCESS == ret) { 4074 /* process the outbound message */ 4075 process_one_iomb(pm8001_ha, circularQ, 4076 (void *)(pMsg1 - 4)); 4077 /* free the message from the outbound circular buffer */ 4078 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4079 circularQ, bc); 4080 } 4081 if (MPI_IO_STATUS_BUSY == ret) { 4082 /* Update the producer index from SPC */ 4083 circularQ->producer_index = 4084 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4085 if (le32_to_cpu(circularQ->producer_index) == 4086 circularQ->consumer_idx) 4087 /* OQ is empty */ 4088 break; 4089 } 4090 } while (1); 4091 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags); 4092 return ret; 4093 } 4094 4095 /* DMA_... to our direction translation. */ 4096 static const u8 data_dir_flags[] = { 4097 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4098 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4099 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4100 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4101 }; 4102 4103 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4104 struct smp_req *psmp_cmd, int mode, int length) 4105 { 4106 psmp_cmd->tag = hTag; 4107 psmp_cmd->device_id = cpu_to_le32(deviceID); 4108 if (mode == SMP_DIRECT) { 4109 length = length - 4; /* subtract crc */ 4110 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4111 } else { 4112 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4113 } 4114 } 4115 4116 /** 4117 * pm80xx_chip_smp_req - send an SMP task to FW 4118 * @pm8001_ha: our hba card information. 4119 * @ccb: the ccb information this request used. 4120 */ 4121 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4122 struct pm8001_ccb_info *ccb) 4123 { 4124 int elem, rc; 4125 struct sas_task *task = ccb->task; 4126 struct domain_device *dev = task->dev; 4127 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4128 struct scatterlist *sg_req, *sg_resp, *smp_req; 4129 u32 req_len, resp_len; 4130 struct smp_req smp_cmd; 4131 u32 opc; 4132 u32 i, length; 4133 u8 *payload; 4134 u8 *to; 4135 4136 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4137 /* 4138 * DMA-map SMP request, response buffers 4139 */ 4140 sg_req = &task->smp_task.smp_req; 4141 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4142 if (!elem) 4143 return -ENOMEM; 4144 req_len = sg_dma_len(sg_req); 4145 4146 sg_resp = &task->smp_task.smp_resp; 4147 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4148 if (!elem) { 4149 rc = -ENOMEM; 4150 goto err_out; 4151 } 4152 resp_len = sg_dma_len(sg_resp); 4153 /* must be in dwords */ 4154 if ((req_len & 0x3) || (resp_len & 0x3)) { 4155 rc = -EINVAL; 4156 goto err_out_2; 4157 } 4158 4159 opc = OPC_INB_SMP_REQUEST; 4160 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4161 4162 length = sg_req->length; 4163 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4164 if (!(length - 8)) 4165 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4166 else 4167 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4168 4169 4170 smp_req = &task->smp_task.smp_req; 4171 to = kmap_atomic(sg_page(smp_req)); 4172 payload = to + smp_req->offset; 4173 4174 /* INDIRECT MODE command settings. Use DMA */ 4175 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4176 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4177 /* for SPCv indirect mode. Place the top 4 bytes of 4178 * SMP Request header here. */ 4179 for (i = 0; i < 4; i++) 4180 smp_cmd.smp_req16[i] = *(payload + i); 4181 /* exclude top 4 bytes for SMP req header */ 4182 smp_cmd.long_smp_req.long_req_addr = 4183 cpu_to_le64((u64)sg_dma_address 4184 (&task->smp_task.smp_req) + 4); 4185 /* exclude 4 bytes for SMP req header and CRC */ 4186 smp_cmd.long_smp_req.long_req_size = 4187 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4188 smp_cmd.long_smp_req.long_resp_addr = 4189 cpu_to_le64((u64)sg_dma_address 4190 (&task->smp_task.smp_resp)); 4191 smp_cmd.long_smp_req.long_resp_size = 4192 cpu_to_le32((u32)sg_dma_len 4193 (&task->smp_task.smp_resp)-4); 4194 } else { /* DIRECT MODE */ 4195 smp_cmd.long_smp_req.long_req_addr = 4196 cpu_to_le64((u64)sg_dma_address 4197 (&task->smp_task.smp_req)); 4198 smp_cmd.long_smp_req.long_req_size = 4199 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4200 smp_cmd.long_smp_req.long_resp_addr = 4201 cpu_to_le64((u64)sg_dma_address 4202 (&task->smp_task.smp_resp)); 4203 smp_cmd.long_smp_req.long_resp_size = 4204 cpu_to_le32 4205 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4206 } 4207 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4208 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4209 for (i = 0; i < length; i++) 4210 if (i < 16) { 4211 smp_cmd.smp_req16[i] = *(payload + i); 4212 pm8001_dbg(pm8001_ha, IO, 4213 "Byte[%d]:%x (DMA data:%x)\n", 4214 i, smp_cmd.smp_req16[i], 4215 *(payload)); 4216 } else { 4217 smp_cmd.smp_req[i] = *(payload + i); 4218 pm8001_dbg(pm8001_ha, IO, 4219 "Byte[%d]:%x (DMA data:%x)\n", 4220 i, smp_cmd.smp_req[i], 4221 *(payload)); 4222 } 4223 } 4224 kunmap_atomic(to); 4225 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4226 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4227 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd, 4228 sizeof(smp_cmd), 0); 4229 if (rc) 4230 goto err_out_2; 4231 return 0; 4232 4233 err_out_2: 4234 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4235 DMA_FROM_DEVICE); 4236 err_out: 4237 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4238 DMA_TO_DEVICE); 4239 return rc; 4240 } 4241 4242 static int check_enc_sas_cmd(struct sas_task *task) 4243 { 4244 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4245 4246 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4247 return 1; 4248 else 4249 return 0; 4250 } 4251 4252 static int check_enc_sat_cmd(struct sas_task *task) 4253 { 4254 int ret = 0; 4255 switch (task->ata_task.fis.command) { 4256 case ATA_CMD_FPDMA_READ: 4257 case ATA_CMD_READ_EXT: 4258 case ATA_CMD_READ: 4259 case ATA_CMD_FPDMA_WRITE: 4260 case ATA_CMD_WRITE_EXT: 4261 case ATA_CMD_WRITE: 4262 case ATA_CMD_PIO_READ: 4263 case ATA_CMD_PIO_READ_EXT: 4264 case ATA_CMD_PIO_WRITE: 4265 case ATA_CMD_PIO_WRITE_EXT: 4266 ret = 1; 4267 break; 4268 default: 4269 ret = 0; 4270 break; 4271 } 4272 return ret; 4273 } 4274 4275 static u32 pm80xx_chip_get_q_index(struct sas_task *task) 4276 { 4277 struct request *rq = sas_task_find_rq(task); 4278 4279 if (!rq) 4280 return 0; 4281 4282 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(rq)); 4283 } 4284 4285 /** 4286 * pm80xx_chip_ssp_io_req - send an SSP task to FW 4287 * @pm8001_ha: our hba card information. 4288 * @ccb: the ccb information this request used. 4289 */ 4290 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4291 struct pm8001_ccb_info *ccb) 4292 { 4293 struct sas_task *task = ccb->task; 4294 struct domain_device *dev = task->dev; 4295 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4296 struct ssp_ini_io_start_req ssp_cmd; 4297 u32 tag = ccb->ccb_tag; 4298 u64 phys_addr, end_addr; 4299 u32 end_addr_high, end_addr_low; 4300 u32 q_index; 4301 u32 opc = OPC_INB_SSPINIIOSTART; 4302 4303 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4304 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4305 4306 /* data address domain added for spcv; set to 0 by host, 4307 * used internally by controller 4308 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4309 */ 4310 ssp_cmd.dad_dir_m_tlr = 4311 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4312 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4313 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4314 ssp_cmd.tag = cpu_to_le32(tag); 4315 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4316 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4317 task->ssp_task.cmd->cmd_len); 4318 q_index = pm80xx_chip_get_q_index(task); 4319 4320 /* Check if encryption is set */ 4321 if (pm8001_ha->chip->encrypt && 4322 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4323 pm8001_dbg(pm8001_ha, IO, 4324 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4325 task->ssp_task.cmd->cmnd[0]); 4326 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4327 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4328 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4329 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4330 4331 /* fill in PRD (scatter/gather) table, if any */ 4332 if (task->num_scatter > 1) { 4333 pm8001_chip_make_sg(task->scatter, 4334 ccb->n_elem, ccb->buf_prd); 4335 phys_addr = ccb->ccb_dma_handle; 4336 ssp_cmd.enc_addr_low = 4337 cpu_to_le32(lower_32_bits(phys_addr)); 4338 ssp_cmd.enc_addr_high = 4339 cpu_to_le32(upper_32_bits(phys_addr)); 4340 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4341 } else if (task->num_scatter == 1) { 4342 u64 dma_addr = sg_dma_address(task->scatter); 4343 4344 ssp_cmd.enc_addr_low = 4345 cpu_to_le32(lower_32_bits(dma_addr)); 4346 ssp_cmd.enc_addr_high = 4347 cpu_to_le32(upper_32_bits(dma_addr)); 4348 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4349 ssp_cmd.enc_esgl = 0; 4350 4351 /* Check 4G Boundary */ 4352 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1; 4353 end_addr_low = lower_32_bits(end_addr); 4354 end_addr_high = upper_32_bits(end_addr); 4355 4356 if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) { 4357 pm8001_dbg(pm8001_ha, FAIL, 4358 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4359 dma_addr, 4360 le32_to_cpu(ssp_cmd.enc_len), 4361 end_addr_high, end_addr_low); 4362 pm8001_chip_make_sg(task->scatter, 1, 4363 ccb->buf_prd); 4364 phys_addr = ccb->ccb_dma_handle; 4365 ssp_cmd.enc_addr_low = 4366 cpu_to_le32(lower_32_bits(phys_addr)); 4367 ssp_cmd.enc_addr_high = 4368 cpu_to_le32(upper_32_bits(phys_addr)); 4369 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31); 4370 } 4371 } else if (task->num_scatter == 0) { 4372 ssp_cmd.enc_addr_low = 0; 4373 ssp_cmd.enc_addr_high = 0; 4374 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4375 ssp_cmd.enc_esgl = 0; 4376 } 4377 4378 /* XTS mode. All other fields are 0 */ 4379 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4); 4380 4381 /* set tweak values. Should be the start lba */ 4382 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4383 (task->ssp_task.cmd->cmnd[3] << 16) | 4384 (task->ssp_task.cmd->cmnd[4] << 8) | 4385 (task->ssp_task.cmd->cmnd[5])); 4386 } else { 4387 pm8001_dbg(pm8001_ha, IO, 4388 "Sending Normal SAS command 0x%x inb q %x\n", 4389 task->ssp_task.cmd->cmnd[0], q_index); 4390 /* fill in PRD (scatter/gather) table, if any */ 4391 if (task->num_scatter > 1) { 4392 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4393 ccb->buf_prd); 4394 phys_addr = ccb->ccb_dma_handle; 4395 ssp_cmd.addr_low = 4396 cpu_to_le32(lower_32_bits(phys_addr)); 4397 ssp_cmd.addr_high = 4398 cpu_to_le32(upper_32_bits(phys_addr)); 4399 ssp_cmd.esgl = cpu_to_le32(1<<31); 4400 } else if (task->num_scatter == 1) { 4401 u64 dma_addr = sg_dma_address(task->scatter); 4402 4403 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4404 ssp_cmd.addr_high = 4405 cpu_to_le32(upper_32_bits(dma_addr)); 4406 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4407 ssp_cmd.esgl = 0; 4408 4409 /* Check 4G Boundary */ 4410 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1; 4411 end_addr_low = lower_32_bits(end_addr); 4412 end_addr_high = upper_32_bits(end_addr); 4413 if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) { 4414 pm8001_dbg(pm8001_ha, FAIL, 4415 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4416 dma_addr, 4417 le32_to_cpu(ssp_cmd.len), 4418 end_addr_high, end_addr_low); 4419 pm8001_chip_make_sg(task->scatter, 1, 4420 ccb->buf_prd); 4421 phys_addr = ccb->ccb_dma_handle; 4422 ssp_cmd.addr_low = 4423 cpu_to_le32(lower_32_bits(phys_addr)); 4424 ssp_cmd.addr_high = 4425 cpu_to_le32(upper_32_bits(phys_addr)); 4426 ssp_cmd.esgl = cpu_to_le32(1<<31); 4427 } 4428 } else if (task->num_scatter == 0) { 4429 ssp_cmd.addr_low = 0; 4430 ssp_cmd.addr_high = 0; 4431 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4432 ssp_cmd.esgl = 0; 4433 } 4434 } 4435 4436 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd, 4437 sizeof(ssp_cmd), q_index); 4438 } 4439 4440 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4441 struct pm8001_ccb_info *ccb) 4442 { 4443 struct sas_task *task = ccb->task; 4444 struct domain_device *dev = task->dev; 4445 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4446 struct ata_queued_cmd *qc = task->uldd_task; 4447 u32 tag = ccb->ccb_tag, q_index; 4448 struct sata_start_req sata_cmd; 4449 u32 hdr_tag, ncg_tag = 0; 4450 u64 phys_addr, end_addr; 4451 u32 end_addr_high, end_addr_low; 4452 u32 ATAP = 0x0; 4453 u32 dir, retfis = 0; 4454 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4455 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4456 4457 q_index = pm80xx_chip_get_q_index(task); 4458 4459 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { 4460 ATAP = 0x04; /* no data*/ 4461 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4462 } else if (likely(!task->ata_task.device_control_reg_update)) { 4463 if (task->ata_task.use_ncq && 4464 dev->sata_dev.class != ATA_DEV_ATAPI) { 4465 ATAP = 0x07; /* FPDMA */ 4466 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4467 } else if (task->ata_task.dma_xfer) { 4468 ATAP = 0x06; /* DMA */ 4469 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4470 } else { 4471 ATAP = 0x05; /* PIO*/ 4472 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4473 } 4474 } 4475 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4476 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4477 ncg_tag = hdr_tag; 4478 } 4479 dir = data_dir_flags[task->data_dir] << 8; 4480 sata_cmd.tag = cpu_to_le32(tag); 4481 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4482 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4483 if (task->ata_task.return_fis_on_success) 4484 retfis = 1; 4485 sata_cmd.sata_fis = task->ata_task.fis; 4486 if (likely(!task->ata_task.device_control_reg_update)) 4487 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4488 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4489 4490 /* Check if encryption is set */ 4491 if (pm8001_ha->chip->encrypt && 4492 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4493 pm8001_dbg(pm8001_ha, IO, 4494 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4495 sata_cmd.sata_fis.command); 4496 opc = OPC_INB_SATA_DIF_ENC_IO; 4497 /* set encryption bit; dad (bits 0-1) is 0 */ 4498 sata_cmd.retfis_ncqtag_atap_dir_m_dad = 4499 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4500 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4501 /* fill in PRD (scatter/gather) table, if any */ 4502 if (task->num_scatter > 1) { 4503 pm8001_chip_make_sg(task->scatter, 4504 ccb->n_elem, ccb->buf_prd); 4505 phys_addr = ccb->ccb_dma_handle; 4506 sata_cmd.enc_addr_low = 4507 cpu_to_le32(lower_32_bits(phys_addr)); 4508 sata_cmd.enc_addr_high = 4509 cpu_to_le32(upper_32_bits(phys_addr)); 4510 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4511 } else if (task->num_scatter == 1) { 4512 u64 dma_addr = sg_dma_address(task->scatter); 4513 4514 sata_cmd.enc_addr_low = 4515 cpu_to_le32(lower_32_bits(dma_addr)); 4516 sata_cmd.enc_addr_high = 4517 cpu_to_le32(upper_32_bits(dma_addr)); 4518 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4519 sata_cmd.enc_esgl = 0; 4520 4521 /* Check 4G Boundary */ 4522 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1; 4523 end_addr_low = lower_32_bits(end_addr); 4524 end_addr_high = upper_32_bits(end_addr); 4525 if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) { 4526 pm8001_dbg(pm8001_ha, FAIL, 4527 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4528 dma_addr, 4529 le32_to_cpu(sata_cmd.enc_len), 4530 end_addr_high, end_addr_low); 4531 pm8001_chip_make_sg(task->scatter, 1, 4532 ccb->buf_prd); 4533 phys_addr = ccb->ccb_dma_handle; 4534 sata_cmd.enc_addr_low = 4535 cpu_to_le32(lower_32_bits(phys_addr)); 4536 sata_cmd.enc_addr_high = 4537 cpu_to_le32(upper_32_bits(phys_addr)); 4538 sata_cmd.enc_esgl = 4539 cpu_to_le32(1 << 31); 4540 } 4541 } else if (task->num_scatter == 0) { 4542 sata_cmd.enc_addr_low = 0; 4543 sata_cmd.enc_addr_high = 0; 4544 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4545 sata_cmd.enc_esgl = 0; 4546 } 4547 /* XTS mode. All other fields are 0 */ 4548 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4); 4549 4550 /* set tweak values. Should be the start lba */ 4551 sata_cmd.twk_val0 = 4552 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4553 (sata_cmd.sata_fis.lbah << 16) | 4554 (sata_cmd.sata_fis.lbam << 8) | 4555 (sata_cmd.sata_fis.lbal)); 4556 sata_cmd.twk_val1 = 4557 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4558 (sata_cmd.sata_fis.lbam_exp)); 4559 } else { 4560 pm8001_dbg(pm8001_ha, IO, 4561 "Sending Normal SATA command 0x%x inb %x\n", 4562 sata_cmd.sata_fis.command, q_index); 4563 /* dad (bits 0-1) is 0 */ 4564 sata_cmd.retfis_ncqtag_atap_dir_m_dad = 4565 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4566 ((ATAP & 0x3f) << 10) | dir); 4567 /* fill in PRD (scatter/gather) table, if any */ 4568 if (task->num_scatter > 1) { 4569 pm8001_chip_make_sg(task->scatter, 4570 ccb->n_elem, ccb->buf_prd); 4571 phys_addr = ccb->ccb_dma_handle; 4572 sata_cmd.addr_low = lower_32_bits(phys_addr); 4573 sata_cmd.addr_high = upper_32_bits(phys_addr); 4574 sata_cmd.esgl = cpu_to_le32(1U << 31); 4575 } else if (task->num_scatter == 1) { 4576 u64 dma_addr = sg_dma_address(task->scatter); 4577 4578 sata_cmd.addr_low = lower_32_bits(dma_addr); 4579 sata_cmd.addr_high = upper_32_bits(dma_addr); 4580 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4581 sata_cmd.esgl = 0; 4582 4583 /* Check 4G Boundary */ 4584 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1; 4585 end_addr_low = lower_32_bits(end_addr); 4586 end_addr_high = upper_32_bits(end_addr); 4587 if (end_addr_high != sata_cmd.addr_high) { 4588 pm8001_dbg(pm8001_ha, FAIL, 4589 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4590 dma_addr, 4591 le32_to_cpu(sata_cmd.len), 4592 end_addr_high, end_addr_low); 4593 pm8001_chip_make_sg(task->scatter, 1, 4594 ccb->buf_prd); 4595 phys_addr = ccb->ccb_dma_handle; 4596 sata_cmd.addr_low = lower_32_bits(phys_addr); 4597 sata_cmd.addr_high = upper_32_bits(phys_addr); 4598 sata_cmd.esgl = cpu_to_le32(1U << 31); 4599 } 4600 } else if (task->num_scatter == 0) { 4601 sata_cmd.addr_low = 0; 4602 sata_cmd.addr_high = 0; 4603 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4604 sata_cmd.esgl = 0; 4605 } 4606 4607 /* scsi cdb */ 4608 sata_cmd.atapi_scsi_cdb[0] = 4609 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4610 (task->ata_task.atapi_packet[1] << 8) | 4611 (task->ata_task.atapi_packet[2] << 16) | 4612 (task->ata_task.atapi_packet[3] << 24))); 4613 sata_cmd.atapi_scsi_cdb[1] = 4614 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4615 (task->ata_task.atapi_packet[5] << 8) | 4616 (task->ata_task.atapi_packet[6] << 16) | 4617 (task->ata_task.atapi_packet[7] << 24))); 4618 sata_cmd.atapi_scsi_cdb[2] = 4619 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4620 (task->ata_task.atapi_packet[9] << 8) | 4621 (task->ata_task.atapi_packet[10] << 16) | 4622 (task->ata_task.atapi_packet[11] << 24))); 4623 sata_cmd.atapi_scsi_cdb[3] = 4624 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4625 (task->ata_task.atapi_packet[13] << 8) | 4626 (task->ata_task.atapi_packet[14] << 16) | 4627 (task->ata_task.atapi_packet[15] << 24))); 4628 } 4629 4630 trace_pm80xx_request_issue(pm8001_ha->id, 4631 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS, 4632 ccb->ccb_tag, opc, 4633 qc ? qc->tf.command : 0, // ata opcode 4634 ccb->device ? atomic_read(&ccb->device->running_req) : 0); 4635 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd, 4636 sizeof(sata_cmd), q_index); 4637 } 4638 4639 /** 4640 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4641 * @pm8001_ha: our hba card information. 4642 * @phy_id: the phy id which we wanted to start up. 4643 */ 4644 static int 4645 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4646 { 4647 struct phy_start_req payload; 4648 int ret; 4649 u32 tag; 4650 u32 opcode = OPC_INB_PHYSTART; 4651 4652 ret = pm8001_tag_alloc(pm8001_ha, &tag); 4653 if (ret) { 4654 pm8001_dbg(pm8001_ha, FAIL, "Tag allocation failed\n"); 4655 return ret; 4656 } 4657 4658 memset(&payload, 0, sizeof(payload)); 4659 payload.tag = cpu_to_le32(tag); 4660 4661 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4662 4663 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4664 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4665 /* SSC Disable and SAS Analog ST configuration */ 4666 /* 4667 payload.ase_sh_lm_slr_phyid = 4668 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4669 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4670 phy_id); 4671 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4672 */ 4673 4674 payload.sas_identify.dev_type = SAS_END_DEVICE; 4675 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4676 memcpy(payload.sas_identify.sas_addr, 4677 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE); 4678 payload.sas_identify.phy_id = phy_id; 4679 4680 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4681 sizeof(payload), 0); 4682 } 4683 4684 /** 4685 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4686 * @pm8001_ha: our hba card information. 4687 * @phy_id: the phy id which we wanted to start up. 4688 */ 4689 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4690 u8 phy_id) 4691 { 4692 struct phy_stop_req payload; 4693 int ret; 4694 u32 tag; 4695 u32 opcode = OPC_INB_PHYSTOP; 4696 4697 ret = pm8001_tag_alloc(pm8001_ha, &tag); 4698 if (ret) { 4699 pm8001_dbg(pm8001_ha, FAIL, "Tag allocation failed\n"); 4700 return ret; 4701 } 4702 4703 memset(&payload, 0, sizeof(payload)); 4704 payload.tag = cpu_to_le32(tag); 4705 payload.phy_id = cpu_to_le32(phy_id); 4706 4707 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4708 sizeof(payload), 0); 4709 } 4710 4711 /* 4712 * see comments on pm8001_mpi_reg_resp. 4713 */ 4714 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4715 struct pm8001_device *pm8001_dev, u32 flag) 4716 { 4717 struct reg_dev_req payload; 4718 u32 opc; 4719 u32 stp_sspsmp_sata = 0x4; 4720 u32 linkrate, phy_id; 4721 int rc; 4722 struct pm8001_ccb_info *ccb; 4723 u8 retryFlag = 0x1; 4724 u16 firstBurstSize = 0; 4725 u16 ITNT = 2000; 4726 struct domain_device *dev = pm8001_dev->sas_device; 4727 struct domain_device *parent_dev = dev->parent; 4728 struct pm8001_port *port = dev->port->lldd_port; 4729 4730 memset(&payload, 0, sizeof(payload)); 4731 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4732 if (!ccb) 4733 return -SAS_QUEUE_FULL; 4734 4735 payload.tag = cpu_to_le32(ccb->ccb_tag); 4736 4737 if (flag == 1) { 4738 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4739 } else { 4740 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4741 stp_sspsmp_sata = 0x00; /* stp*/ 4742 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4743 dev_is_expander(pm8001_dev->dev_type)) 4744 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4745 } 4746 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4747 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4748 else 4749 phy_id = pm8001_dev->attached_phy; 4750 4751 opc = OPC_INB_REG_DEV; 4752 4753 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4754 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4755 4756 payload.phyid_portid = 4757 cpu_to_le32(((port->port_id) & 0xFF) | 4758 ((phy_id & 0xFF) << 8)); 4759 4760 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4761 ((linkrate & 0x0F) << 24) | 4762 ((stp_sspsmp_sata & 0x03) << 28)); 4763 payload.firstburstsize_ITNexustimeout = 4764 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4765 4766 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4767 SAS_ADDR_SIZE); 4768 4769 pm8001_dbg(pm8001_ha, INIT, 4770 "register device req phy_id 0x%x port_id 0x%x\n", phy_id, 4771 (port->port_id & 0xFF)); 4772 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4773 sizeof(payload), 0); 4774 if (rc) 4775 pm8001_ccb_free(pm8001_ha, ccb); 4776 4777 return rc; 4778 } 4779 4780 /** 4781 * pm80xx_chip_phy_ctl_req - support the local phy operation 4782 * @pm8001_ha: our hba card information. 4783 * @phyId: the phy id which we wanted to operate 4784 * @phy_op: phy operation to request 4785 */ 4786 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4787 u32 phyId, u32 phy_op) 4788 { 4789 u32 tag; 4790 int rc; 4791 struct local_phy_ctl_req payload; 4792 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4793 4794 memset(&payload, 0, sizeof(payload)); 4795 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4796 if (rc) 4797 return rc; 4798 4799 payload.tag = cpu_to_le32(tag); 4800 payload.phyop_phyid = 4801 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4802 4803 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4804 sizeof(payload), 0); 4805 if (rc) 4806 pm8001_tag_free(pm8001_ha, tag); 4807 4808 return rc; 4809 } 4810 4811 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4812 { 4813 u32 value; 4814 4815 if (pm8001_ha->use_msix) 4816 return 1; 4817 4818 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4819 if (value) 4820 return 1; 4821 return 0; 4822 } 4823 4824 /** 4825 * pm80xx_chip_isr - PM8001 isr handler. 4826 * @pm8001_ha: our hba card information. 4827 * @vec: irq number. 4828 */ 4829 static irqreturn_t 4830 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4831 { 4832 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4833 pm8001_dbg(pm8001_ha, DEVIO, 4834 "irq vec %d, ODMR:0x%x\n", 4835 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4836 process_oq(pm8001_ha, vec); 4837 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4838 return IRQ_HANDLED; 4839 } 4840 4841 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4842 u32 operation, u32 phyid, 4843 u32 length, u32 *buf) 4844 { 4845 u32 tag, i, j = 0; 4846 int rc; 4847 struct set_phy_profile_req payload; 4848 u32 opc = OPC_INB_SET_PHY_PROFILE; 4849 4850 memset(&payload, 0, sizeof(payload)); 4851 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4852 if (rc) { 4853 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4854 return; 4855 } 4856 4857 payload.tag = cpu_to_le32(tag); 4858 payload.ppc_phyid = 4859 cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF)); 4860 pm8001_dbg(pm8001_ha, DISC, 4861 " phy profile command for phy %x ,length is %d\n", 4862 le32_to_cpu(payload.ppc_phyid), length); 4863 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4864 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4865 j++; 4866 } 4867 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4868 sizeof(payload), 0); 4869 if (rc) 4870 pm8001_tag_free(pm8001_ha, tag); 4871 } 4872 4873 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4874 u32 length, u8 *buf) 4875 { 4876 u32 i; 4877 4878 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4879 mpi_set_phy_profile_req(pm8001_ha, 4880 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4881 length = length + PHY_DWORD_LENGTH; 4882 } 4883 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 4884 } 4885 4886 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4887 u32 phy, u32 length, u32 *buf) 4888 { 4889 u32 tag, opc; 4890 int rc, i; 4891 struct set_phy_profile_req payload; 4892 4893 memset(&payload, 0, sizeof(payload)); 4894 4895 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4896 if (rc) { 4897 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 4898 return; 4899 } 4900 4901 opc = OPC_INB_SET_PHY_PROFILE; 4902 4903 payload.tag = cpu_to_le32(tag); 4904 payload.ppc_phyid = 4905 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4906 | (phy & 0xFF)); 4907 4908 for (i = 0; i < length; i++) 4909 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4910 4911 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4912 sizeof(payload), 0); 4913 if (rc) 4914 pm8001_tag_free(pm8001_ha, tag); 4915 4916 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 4917 } 4918 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4919 .name = "pmc80xx", 4920 .chip_init = pm80xx_chip_init, 4921 .chip_post_init = pm80xx_chip_post_init, 4922 .chip_soft_rst = pm80xx_chip_soft_rst, 4923 .chip_rst = pm80xx_hw_chip_rst, 4924 .chip_iounmap = pm8001_chip_iounmap, 4925 .isr = pm80xx_chip_isr, 4926 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4927 .isr_process_oq = process_oq, 4928 .interrupt_enable = pm80xx_chip_interrupt_enable, 4929 .interrupt_disable = pm80xx_chip_interrupt_disable, 4930 .make_prd = pm8001_chip_make_sg, 4931 .smp_req = pm80xx_chip_smp_req, 4932 .ssp_io_req = pm80xx_chip_ssp_io_req, 4933 .sata_req = pm80xx_chip_sata_req, 4934 .phy_start_req = pm80xx_chip_phy_start_req, 4935 .phy_stop_req = pm80xx_chip_phy_stop_req, 4936 .reg_dev_req = pm80xx_chip_reg_dev_req, 4937 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4938 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4939 .task_abort = pm8001_chip_abort_task, 4940 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4941 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4942 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4943 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4944 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4945 .fatal_errors = pm80xx_fatal_errors, 4946 .hw_event_ack_req = pm80xx_hw_event_ack_req, 4947 }; 4948