1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *); 60 61 /* 62 * chip info structure to identify chip key functionality as 63 * encryption available/not, no of ports, hw specific function ref 64 */ 65 static const struct pm8001_chip_info pm8001_chips[] = { 66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 77 }; 78 static int pm8001_id; 79 80 LIST_HEAD(hba_list); 81 82 struct workqueue_struct *pm8001_wq; 83 84 static int pm8001_map_queues(struct Scsi_Host *shost) 85 { 86 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 87 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 88 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 89 90 if (pm8001_ha->number_of_intr > 1) 91 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1); 92 93 return blk_mq_map_queues(qmap); 94 } 95 96 /* 97 * The main structure which LLDD must register for scsi core. 98 */ 99 static struct scsi_host_template pm8001_sht = { 100 .module = THIS_MODULE, 101 .name = DRV_NAME, 102 .queuecommand = sas_queuecommand, 103 .dma_need_drain = ata_scsi_dma_need_drain, 104 .target_alloc = sas_target_alloc, 105 .slave_configure = sas_slave_configure, 106 .scan_finished = pm8001_scan_finished, 107 .scan_start = pm8001_scan_start, 108 .change_queue_depth = sas_change_queue_depth, 109 .bios_param = sas_bios_param, 110 .can_queue = 1, 111 .this_id = -1, 112 .sg_tablesize = PM8001_MAX_DMA_SG, 113 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 114 .eh_device_reset_handler = sas_eh_device_reset_handler, 115 .eh_target_reset_handler = sas_eh_target_reset_handler, 116 .slave_alloc = sas_slave_alloc, 117 .target_destroy = sas_target_destroy, 118 .ioctl = sas_ioctl, 119 #ifdef CONFIG_COMPAT 120 .compat_ioctl = sas_ioctl, 121 #endif 122 .shost_groups = pm8001_host_groups, 123 .track_queue_depth = 1, 124 .cmd_per_lun = 32, 125 .map_queues = pm8001_map_queues, 126 }; 127 128 /* 129 * Sas layer call this function to execute specific task. 130 */ 131 static struct sas_domain_function_template pm8001_transport_ops = { 132 .lldd_dev_found = pm8001_dev_found, 133 .lldd_dev_gone = pm8001_dev_gone, 134 135 .lldd_execute_task = pm8001_queue_command, 136 .lldd_control_phy = pm8001_phy_control, 137 138 .lldd_abort_task = pm8001_abort_task, 139 .lldd_abort_task_set = sas_abort_task_set, 140 .lldd_clear_task_set = pm8001_clear_task_set, 141 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 142 .lldd_lu_reset = pm8001_lu_reset, 143 .lldd_query_task = pm8001_query_task, 144 .lldd_port_formed = pm8001_port_formed, 145 .lldd_tmf_exec_complete = pm8001_setds_completion, 146 .lldd_tmf_aborted = pm8001_tmf_aborted, 147 }; 148 149 /** 150 * pm8001_phy_init - initiate our adapter phys 151 * @pm8001_ha: our hba structure. 152 * @phy_id: phy id. 153 */ 154 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 155 { 156 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 157 struct asd_sas_phy *sas_phy = &phy->sas_phy; 158 phy->phy_state = PHY_LINK_DISABLE; 159 phy->pm8001_ha = pm8001_ha; 160 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 161 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 162 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 163 sas_phy->class = SAS; 164 sas_phy->iproto = SAS_PROTOCOL_ALL; 165 sas_phy->tproto = 0; 166 sas_phy->type = PHY_TYPE_PHYSICAL; 167 sas_phy->role = PHY_ROLE_INITIATOR; 168 sas_phy->oob_mode = OOB_NOT_CONNECTED; 169 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 170 sas_phy->id = phy_id; 171 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 172 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 173 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 174 sas_phy->lldd_phy = phy; 175 } 176 177 /** 178 * pm8001_free - free hba 179 * @pm8001_ha: our hba structure. 180 */ 181 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 182 { 183 int i; 184 185 if (!pm8001_ha) 186 return; 187 188 for (i = 0; i < USI_MAX_MEMCNT; i++) { 189 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 190 dma_free_coherent(&pm8001_ha->pdev->dev, 191 (pm8001_ha->memoryMap.region[i].total_len + 192 pm8001_ha->memoryMap.region[i].alignment), 193 pm8001_ha->memoryMap.region[i].virt_ptr, 194 pm8001_ha->memoryMap.region[i].phys_addr); 195 } 196 } 197 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 198 flush_workqueue(pm8001_wq); 199 bitmap_free(pm8001_ha->tags); 200 kfree(pm8001_ha); 201 } 202 203 #ifdef PM8001_USE_TASKLET 204 205 /** 206 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 207 * @opaque: the passed general host adapter struct 208 * Note: pm8001_tasklet is common for pm8001 & pm80xx 209 */ 210 static void pm8001_tasklet(unsigned long opaque) 211 { 212 struct pm8001_hba_info *pm8001_ha; 213 struct isr_param *irq_vector; 214 215 irq_vector = (struct isr_param *)opaque; 216 pm8001_ha = irq_vector->drv_inst; 217 if (unlikely(!pm8001_ha)) 218 BUG_ON(1); 219 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 220 } 221 #endif 222 223 /** 224 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 225 * It obtains the vector number and calls the equivalent bottom 226 * half or services directly. 227 * @irq: interrupt number 228 * @opaque: the passed outbound queue/vector. Host structure is 229 * retrieved from the same. 230 */ 231 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 232 { 233 struct isr_param *irq_vector; 234 struct pm8001_hba_info *pm8001_ha; 235 irqreturn_t ret = IRQ_HANDLED; 236 irq_vector = (struct isr_param *)opaque; 237 pm8001_ha = irq_vector->drv_inst; 238 239 if (unlikely(!pm8001_ha)) 240 return IRQ_NONE; 241 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 242 return IRQ_NONE; 243 #ifdef PM8001_USE_TASKLET 244 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 245 #else 246 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 247 #endif 248 return ret; 249 } 250 251 /** 252 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 253 * @irq: interrupt number 254 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure. 255 */ 256 257 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 258 { 259 struct pm8001_hba_info *pm8001_ha; 260 irqreturn_t ret = IRQ_HANDLED; 261 struct sas_ha_struct *sha = dev_id; 262 pm8001_ha = sha->lldd_ha; 263 if (unlikely(!pm8001_ha)) 264 return IRQ_NONE; 265 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 266 return IRQ_NONE; 267 268 #ifdef PM8001_USE_TASKLET 269 tasklet_schedule(&pm8001_ha->tasklet[0]); 270 #else 271 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 272 #endif 273 return ret; 274 } 275 276 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 277 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 278 279 /** 280 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 281 * @pm8001_ha: our hba structure. 282 * @ent: PCI device ID structure to match on 283 */ 284 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 285 const struct pci_device_id *ent) 286 { 287 int i, count = 0, rc = 0; 288 u32 ci_offset, ib_offset, ob_offset, pi_offset; 289 struct inbound_queue_table *ibq; 290 struct outbound_queue_table *obq; 291 292 spin_lock_init(&pm8001_ha->lock); 293 spin_lock_init(&pm8001_ha->bitmap_lock); 294 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 295 pm8001_ha->chip->n_phy); 296 297 /* Setup Interrupt */ 298 rc = pm8001_setup_irq(pm8001_ha); 299 if (rc) { 300 pm8001_dbg(pm8001_ha, FAIL, 301 "pm8001_setup_irq failed [ret: %d]\n", rc); 302 goto err_out; 303 } 304 /* Request Interrupt */ 305 rc = pm8001_request_irq(pm8001_ha); 306 if (rc) 307 goto err_out; 308 309 count = pm8001_ha->max_q_num; 310 /* Queues are chosen based on the number of cores/msix availability */ 311 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 312 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 313 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 314 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 315 pm8001_ha->max_memcnt = pi_offset + count; 316 317 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 318 pm8001_phy_init(pm8001_ha, i); 319 pm8001_ha->port[i].wide_port_phymap = 0; 320 pm8001_ha->port[i].port_attached = 0; 321 pm8001_ha->port[i].port_state = 0; 322 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 323 } 324 325 /* MPI Memory region 1 for AAP Event Log for fw */ 326 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 327 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 328 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 329 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 330 331 /* MPI Memory region 2 for IOP Event Log for fw */ 332 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 333 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 334 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 335 pm8001_ha->memoryMap.region[IOP].alignment = 32; 336 337 for (i = 0; i < count; i++) { 338 ibq = &pm8001_ha->inbnd_q_tbl[i]; 339 spin_lock_init(&ibq->iq_lock); 340 /* MPI Memory region 3 for consumer Index of inbound queues */ 341 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 342 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 343 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 344 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 345 346 if ((ent->driver_data) != chip_8001) { 347 /* MPI Memory region 5 inbound queues */ 348 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 349 PM8001_MPI_QUEUE; 350 pm8001_ha->memoryMap.region[ib_offset+i].element_size 351 = 128; 352 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 353 PM8001_MPI_QUEUE * 128; 354 pm8001_ha->memoryMap.region[ib_offset+i].alignment 355 = 128; 356 } else { 357 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 358 PM8001_MPI_QUEUE; 359 pm8001_ha->memoryMap.region[ib_offset+i].element_size 360 = 64; 361 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 362 PM8001_MPI_QUEUE * 64; 363 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 364 } 365 } 366 367 for (i = 0; i < count; i++) { 368 obq = &pm8001_ha->outbnd_q_tbl[i]; 369 spin_lock_init(&obq->oq_lock); 370 /* MPI Memory region 4 for producer Index of outbound queues */ 371 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 372 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 373 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 374 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 375 376 if (ent->driver_data != chip_8001) { 377 /* MPI Memory region 6 Outbound queues */ 378 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 379 PM8001_MPI_QUEUE; 380 pm8001_ha->memoryMap.region[ob_offset+i].element_size 381 = 128; 382 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 383 PM8001_MPI_QUEUE * 128; 384 pm8001_ha->memoryMap.region[ob_offset+i].alignment 385 = 128; 386 } else { 387 /* MPI Memory region 6 Outbound queues */ 388 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 389 PM8001_MPI_QUEUE; 390 pm8001_ha->memoryMap.region[ob_offset+i].element_size 391 = 64; 392 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 393 PM8001_MPI_QUEUE * 64; 394 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 395 } 396 397 } 398 /* Memory region write DMA*/ 399 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 400 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 401 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 402 403 /* Memory region for fw flash */ 404 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 405 406 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 407 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 408 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 409 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 410 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 411 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 412 413 if (pm8001_mem_alloc(pm8001_ha->pdev, 414 ®ion->virt_ptr, 415 ®ion->phys_addr, 416 ®ion->phys_addr_hi, 417 ®ion->phys_addr_lo, 418 region->total_len, 419 region->alignment) != 0) { 420 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 421 goto err_out; 422 } 423 } 424 425 /* Memory region for devices*/ 426 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 427 * sizeof(struct pm8001_device), GFP_KERNEL); 428 if (!pm8001_ha->devices) { 429 rc = -ENOMEM; 430 goto err_out_nodev; 431 } 432 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 433 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 434 pm8001_ha->devices[i].id = i; 435 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 436 atomic_set(&pm8001_ha->devices[i].running_req, 0); 437 } 438 pm8001_ha->flags = PM8001F_INIT_TIME; 439 /* Initialize tags */ 440 pm8001_tag_init(pm8001_ha); 441 return 0; 442 443 err_out_nodev: 444 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 445 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 446 dma_free_coherent(&pm8001_ha->pdev->dev, 447 (pm8001_ha->memoryMap.region[i].total_len + 448 pm8001_ha->memoryMap.region[i].alignment), 449 pm8001_ha->memoryMap.region[i].virt_ptr, 450 pm8001_ha->memoryMap.region[i].phys_addr); 451 } 452 } 453 err_out: 454 return 1; 455 } 456 457 /** 458 * pm8001_ioremap - remap the pci high physical address to kernel virtual 459 * address so that we can access them. 460 * @pm8001_ha: our hba structure. 461 */ 462 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 463 { 464 u32 bar; 465 u32 logicalBar = 0; 466 struct pci_dev *pdev; 467 468 pdev = pm8001_ha->pdev; 469 /* map pci mem (PMC pci base 0-3)*/ 470 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 471 /* 472 ** logical BARs for SPC: 473 ** bar 0 and 1 - logical BAR0 474 ** bar 2 and 3 - logical BAR1 475 ** bar4 - logical BAR2 476 ** bar5 - logical BAR3 477 ** Skip the appropriate assignments: 478 */ 479 if ((bar == 1) || (bar == 3)) 480 continue; 481 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 482 pm8001_ha->io_mem[logicalBar].membase = 483 pci_resource_start(pdev, bar); 484 pm8001_ha->io_mem[logicalBar].memsize = 485 pci_resource_len(pdev, bar); 486 pm8001_ha->io_mem[logicalBar].memvirtaddr = 487 ioremap(pm8001_ha->io_mem[logicalBar].membase, 488 pm8001_ha->io_mem[logicalBar].memsize); 489 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 490 pm8001_dbg(pm8001_ha, INIT, 491 "Failed to ioremap bar %d, logicalBar %d", 492 bar, logicalBar); 493 return -ENOMEM; 494 } 495 pm8001_dbg(pm8001_ha, INIT, 496 "base addr %llx virt_addr=%llx len=%d\n", 497 (u64)pm8001_ha->io_mem[logicalBar].membase, 498 (u64)(unsigned long) 499 pm8001_ha->io_mem[logicalBar].memvirtaddr, 500 pm8001_ha->io_mem[logicalBar].memsize); 501 } else { 502 pm8001_ha->io_mem[logicalBar].membase = 0; 503 pm8001_ha->io_mem[logicalBar].memsize = 0; 504 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 505 } 506 logicalBar++; 507 } 508 return 0; 509 } 510 511 /** 512 * pm8001_pci_alloc - initialize our ha card structure 513 * @pdev: pci device. 514 * @ent: ent 515 * @shost: scsi host struct which has been initialized before. 516 */ 517 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 518 const struct pci_device_id *ent, 519 struct Scsi_Host *shost) 520 521 { 522 struct pm8001_hba_info *pm8001_ha; 523 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 524 int j; 525 526 pm8001_ha = sha->lldd_ha; 527 if (!pm8001_ha) 528 return NULL; 529 530 pm8001_ha->pdev = pdev; 531 pm8001_ha->dev = &pdev->dev; 532 pm8001_ha->chip_id = ent->driver_data; 533 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 534 pm8001_ha->irq = pdev->irq; 535 pm8001_ha->sas = sha; 536 pm8001_ha->shost = shost; 537 pm8001_ha->id = pm8001_id++; 538 pm8001_ha->logging_level = logging_level; 539 pm8001_ha->non_fatal_count = 0; 540 if (link_rate >= 1 && link_rate <= 15) 541 pm8001_ha->link_rate = (link_rate << 8); 542 else { 543 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 544 LINKRATE_60 | LINKRATE_120; 545 pm8001_dbg(pm8001_ha, FAIL, 546 "Setting link rate to default value\n"); 547 } 548 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 549 /* IOMB size is 128 for 8088/89 controllers */ 550 if (pm8001_ha->chip_id != chip_8001) 551 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 552 else 553 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 554 555 #ifdef PM8001_USE_TASKLET 556 /* Tasklet for non msi-x interrupt handler */ 557 if ((!pdev->msix_cap || !pci_msi_enabled()) 558 || (pm8001_ha->chip_id == chip_8001)) 559 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 560 (unsigned long)&(pm8001_ha->irq_vector[0])); 561 else 562 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 563 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 564 (unsigned long)&(pm8001_ha->irq_vector[j])); 565 #endif 566 if (pm8001_ioremap(pm8001_ha)) 567 goto failed_pci_alloc; 568 if (!pm8001_alloc(pm8001_ha, ent)) 569 return pm8001_ha; 570 failed_pci_alloc: 571 pm8001_free(pm8001_ha); 572 return NULL; 573 } 574 575 /** 576 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 577 * @pdev: pci device. 578 */ 579 static int pci_go_44(struct pci_dev *pdev) 580 { 581 int rc; 582 583 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 584 if (rc) { 585 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 586 if (rc) 587 dev_printk(KERN_ERR, &pdev->dev, 588 "32-bit DMA enable failed\n"); 589 } 590 return rc; 591 } 592 593 /** 594 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 595 * @shost: scsi host which has been allocated outside. 596 * @chip_info: our ha struct. 597 */ 598 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 599 const struct pm8001_chip_info *chip_info) 600 { 601 int phy_nr, port_nr; 602 struct asd_sas_phy **arr_phy; 603 struct asd_sas_port **arr_port; 604 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 605 606 phy_nr = chip_info->n_phy; 607 port_nr = phy_nr; 608 memset(sha, 0x00, sizeof(*sha)); 609 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 610 if (!arr_phy) 611 goto exit; 612 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 613 if (!arr_port) 614 goto exit_free2; 615 616 sha->sas_phy = arr_phy; 617 sha->sas_port = arr_port; 618 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 619 if (!sha->lldd_ha) 620 goto exit_free1; 621 622 shost->transportt = pm8001_stt; 623 shost->max_id = PM8001_MAX_DEVICES; 624 shost->unique_id = pm8001_id; 625 shost->max_cmd_len = 16; 626 return 0; 627 exit_free1: 628 kfree(arr_port); 629 exit_free2: 630 kfree(arr_phy); 631 exit: 632 return -1; 633 } 634 635 /** 636 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 637 * @shost: scsi host which has been allocated outside 638 * @chip_info: our ha struct. 639 */ 640 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 641 const struct pm8001_chip_info *chip_info) 642 { 643 int i = 0; 644 struct pm8001_hba_info *pm8001_ha; 645 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 646 647 pm8001_ha = sha->lldd_ha; 648 for (i = 0; i < chip_info->n_phy; i++) { 649 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 650 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 651 sha->sas_phy[i]->sas_addr = 652 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 653 } 654 sha->sas_ha_name = DRV_NAME; 655 sha->dev = pm8001_ha->dev; 656 sha->strict_wide_ports = 1; 657 sha->lldd_module = THIS_MODULE; 658 sha->sas_addr = &pm8001_ha->sas_addr[0]; 659 sha->num_phys = chip_info->n_phy; 660 sha->core.shost = shost; 661 } 662 663 /** 664 * pm8001_init_sas_add - initialize sas address 665 * @pm8001_ha: our ha struct. 666 * 667 * Currently we just set the fixed SAS address to our HBA, for manufacture, 668 * it should read from the EEPROM 669 */ 670 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 671 { 672 u8 i, j; 673 u8 sas_add[8]; 674 #ifdef PM8001_READ_VPD 675 /* For new SPC controllers WWN is stored in flash vpd 676 * For SPC/SPCve controllers WWN is stored in EEPROM 677 * For Older SPC WWN is stored in NVMD 678 */ 679 DECLARE_COMPLETION_ONSTACK(completion); 680 struct pm8001_ioctl_payload payload; 681 u16 deviceid; 682 int rc; 683 684 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 685 pm8001_ha->nvmd_completion = &completion; 686 687 if (pm8001_ha->chip_id == chip_8001) { 688 if (deviceid == 0x8081 || deviceid == 0x0042) { 689 payload.minor_function = 4; 690 payload.rd_length = 4096; 691 } else { 692 payload.minor_function = 0; 693 payload.rd_length = 128; 694 } 695 } else if ((pm8001_ha->chip_id == chip_8070 || 696 pm8001_ha->chip_id == chip_8072) && 697 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 698 payload.minor_function = 4; 699 payload.rd_length = 4096; 700 } else { 701 payload.minor_function = 1; 702 payload.rd_length = 4096; 703 } 704 payload.offset = 0; 705 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 706 if (!payload.func_specific) { 707 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); 708 return; 709 } 710 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 711 if (rc) { 712 kfree(payload.func_specific); 713 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 714 return; 715 } 716 wait_for_completion(&completion); 717 718 for (i = 0, j = 0; i <= 7; i++, j++) { 719 if (pm8001_ha->chip_id == chip_8001) { 720 if (deviceid == 0x8081) 721 pm8001_ha->sas_addr[j] = 722 payload.func_specific[0x704 + i]; 723 else if (deviceid == 0x0042) 724 pm8001_ha->sas_addr[j] = 725 payload.func_specific[0x010 + i]; 726 } else if ((pm8001_ha->chip_id == chip_8070 || 727 pm8001_ha->chip_id == chip_8072) && 728 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 729 pm8001_ha->sas_addr[j] = 730 payload.func_specific[0x010 + i]; 731 } else 732 pm8001_ha->sas_addr[j] = 733 payload.func_specific[0x804 + i]; 734 } 735 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 736 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 737 if (i && ((i % 4) == 0)) 738 sas_add[7] = sas_add[7] + 4; 739 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 740 sas_add, SAS_ADDR_SIZE); 741 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 742 pm8001_ha->phy[i].dev_sas_addr); 743 } 744 kfree(payload.func_specific); 745 #else 746 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 747 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 748 pm8001_ha->phy[i].dev_sas_addr = 749 cpu_to_be64((u64) 750 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 751 } 752 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 753 SAS_ADDR_SIZE); 754 #endif 755 } 756 757 /* 758 * pm8001_get_phy_settings_info : Read phy setting values. 759 * @pm8001_ha : our hba. 760 */ 761 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 762 { 763 764 #ifdef PM8001_READ_VPD 765 /*OPTION ROM FLASH read for the SPC cards */ 766 DECLARE_COMPLETION_ONSTACK(completion); 767 struct pm8001_ioctl_payload payload; 768 int rc; 769 770 pm8001_ha->nvmd_completion = &completion; 771 /* SAS ADDRESS read from flash / EEPROM */ 772 payload.minor_function = 6; 773 payload.offset = 0; 774 payload.rd_length = 4096; 775 payload.func_specific = kzalloc(4096, GFP_KERNEL); 776 if (!payload.func_specific) 777 return -ENOMEM; 778 /* Read phy setting values from flash */ 779 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 780 if (rc) { 781 kfree(payload.func_specific); 782 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 783 return -ENOMEM; 784 } 785 wait_for_completion(&completion); 786 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 787 kfree(payload.func_specific); 788 #endif 789 return 0; 790 } 791 792 struct pm8001_mpi3_phy_pg_trx_config { 793 u32 LaneLosCfg; 794 u32 LanePgaCfg1; 795 u32 LanePisoCfg1; 796 u32 LanePisoCfg2; 797 u32 LanePisoCfg3; 798 u32 LanePisoCfg4; 799 u32 LanePisoCfg5; 800 u32 LanePisoCfg6; 801 u32 LaneBctCtrl; 802 }; 803 804 /** 805 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings 806 * @pm8001_ha : our adapter 807 * @phycfg : PHY config page to populate 808 */ 809 static 810 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 811 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 812 { 813 phycfg->LaneLosCfg = 0x00000132; 814 phycfg->LanePgaCfg1 = 0x00203949; 815 phycfg->LanePisoCfg1 = 0x000000FF; 816 phycfg->LanePisoCfg2 = 0xFF000001; 817 phycfg->LanePisoCfg3 = 0xE7011300; 818 phycfg->LanePisoCfg4 = 0x631C40C0; 819 phycfg->LanePisoCfg5 = 0xF8102036; 820 phycfg->LanePisoCfg6 = 0xF74A1000; 821 phycfg->LaneBctCtrl = 0x00FB33F8; 822 } 823 824 /** 825 * pm8001_get_external_phy_settings - Retrieves the external PHY settings 826 * @pm8001_ha : our adapter 827 * @phycfg : PHY config page to populate 828 */ 829 static 830 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 831 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 832 { 833 phycfg->LaneLosCfg = 0x00000132; 834 phycfg->LanePgaCfg1 = 0x00203949; 835 phycfg->LanePisoCfg1 = 0x000000FF; 836 phycfg->LanePisoCfg2 = 0xFF000001; 837 phycfg->LanePisoCfg3 = 0xE7011300; 838 phycfg->LanePisoCfg4 = 0x63349140; 839 phycfg->LanePisoCfg5 = 0xF8102036; 840 phycfg->LanePisoCfg6 = 0xF80D9300; 841 phycfg->LaneBctCtrl = 0x00FB33F8; 842 } 843 844 /** 845 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext 846 * @pm8001_ha : our adapter 847 * @phymask : The PHY mask 848 */ 849 static 850 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 851 { 852 switch (pm8001_ha->pdev->subsystem_device) { 853 case 0x0070: /* H1280 - 8 external 0 internal */ 854 case 0x0072: /* H12F0 - 16 external 0 internal */ 855 *phymask = 0x0000; 856 break; 857 858 case 0x0071: /* H1208 - 0 external 8 internal */ 859 case 0x0073: /* H120F - 0 external 16 internal */ 860 *phymask = 0xFFFF; 861 break; 862 863 case 0x0080: /* H1244 - 4 external 4 internal */ 864 *phymask = 0x00F0; 865 break; 866 867 case 0x0081: /* H1248 - 4 external 8 internal */ 868 *phymask = 0x0FF0; 869 break; 870 871 case 0x0082: /* H1288 - 8 external 8 internal */ 872 *phymask = 0xFF00; 873 break; 874 875 default: 876 pm8001_dbg(pm8001_ha, INIT, 877 "Unknown subsystem device=0x%.04x\n", 878 pm8001_ha->pdev->subsystem_device); 879 } 880 } 881 882 /** 883 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings 884 * @pm8001_ha : our adapter 885 */ 886 static 887 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 888 { 889 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 890 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 891 int phymask = 0; 892 int i = 0; 893 894 memset(&phycfg_int, 0, sizeof(phycfg_int)); 895 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 896 897 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 898 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 899 pm8001_get_phy_mask(pm8001_ha, &phymask); 900 901 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 902 if (phymask & (1 << i)) {/* Internal PHY */ 903 pm8001_set_phy_profile_single(pm8001_ha, i, 904 sizeof(phycfg_int) / sizeof(u32), 905 (u32 *)&phycfg_int); 906 907 } else { /* External PHY */ 908 pm8001_set_phy_profile_single(pm8001_ha, i, 909 sizeof(phycfg_ext) / sizeof(u32), 910 (u32 *)&phycfg_ext); 911 } 912 } 913 914 return 0; 915 } 916 917 /** 918 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID. 919 * @pm8001_ha : our hba. 920 */ 921 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 922 { 923 switch (pm8001_ha->pdev->subsystem_vendor) { 924 case PCI_VENDOR_ID_ATTO: 925 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 926 return 0; 927 else 928 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 929 930 case PCI_VENDOR_ID_ADAPTEC2: 931 case 0: 932 return 0; 933 934 default: 935 return pm8001_get_phy_settings_info(pm8001_ha); 936 } 937 } 938 939 #ifdef PM8001_USE_MSIX 940 /** 941 * pm8001_setup_msix - enable MSI-X interrupt 942 * @pm8001_ha: our ha struct. 943 */ 944 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 945 { 946 unsigned int allocated_irq_vectors; 947 int rc; 948 949 /* SPCv controllers supports 64 msi-x */ 950 if (pm8001_ha->chip_id == chip_8001) { 951 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1, 952 PCI_IRQ_MSIX); 953 } else { 954 /* 955 * Queue index #0 is used always for housekeeping, so don't 956 * include in the affinity spreading. 957 */ 958 struct irq_affinity desc = { 959 .pre_vectors = 1, 960 }; 961 rc = pci_alloc_irq_vectors_affinity( 962 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC, 963 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc); 964 } 965 966 allocated_irq_vectors = rc; 967 if (rc < 0) 968 return rc; 969 970 /* Assigns the number of interrupts */ 971 pm8001_ha->number_of_intr = allocated_irq_vectors; 972 973 /* Maximum queue number updating in HBA structure */ 974 pm8001_ha->max_q_num = allocated_irq_vectors; 975 976 pm8001_dbg(pm8001_ha, INIT, 977 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 978 rc, pm8001_ha->number_of_intr); 979 return 0; 980 } 981 982 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 983 { 984 u32 i = 0, j = 0; 985 int flag = 0, rc = 0; 986 int nr_irqs = pm8001_ha->number_of_intr; 987 988 if (pm8001_ha->chip_id != chip_8001) 989 flag &= ~IRQF_SHARED; 990 991 pm8001_dbg(pm8001_ha, INIT, 992 "pci_enable_msix request number of intr %d\n", 993 pm8001_ha->number_of_intr); 994 995 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 996 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 997 998 for (i = 0; i < nr_irqs; i++) { 999 snprintf(pm8001_ha->intr_drvname[i], 1000 sizeof(pm8001_ha->intr_drvname[0]), 1001 "%s-%d", pm8001_ha->name, i); 1002 pm8001_ha->irq_vector[i].irq_id = i; 1003 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 1004 1005 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 1006 pm8001_interrupt_handler_msix, flag, 1007 pm8001_ha->intr_drvname[i], 1008 &(pm8001_ha->irq_vector[i])); 1009 if (rc) { 1010 for (j = 0; j < i; j++) { 1011 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 1012 &(pm8001_ha->irq_vector[i])); 1013 } 1014 pci_free_irq_vectors(pm8001_ha->pdev); 1015 break; 1016 } 1017 } 1018 1019 return rc; 1020 } 1021 #endif 1022 1023 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 1024 { 1025 struct pci_dev *pdev; 1026 1027 pdev = pm8001_ha->pdev; 1028 1029 #ifdef PM8001_USE_MSIX 1030 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 1031 return pm8001_setup_msix(pm8001_ha); 1032 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1033 #endif 1034 return 0; 1035 } 1036 1037 /** 1038 * pm8001_request_irq - register interrupt 1039 * @pm8001_ha: our ha struct. 1040 */ 1041 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1042 { 1043 struct pci_dev *pdev; 1044 int rc; 1045 1046 pdev = pm8001_ha->pdev; 1047 1048 #ifdef PM8001_USE_MSIX 1049 if (pdev->msix_cap && pci_msi_enabled()) 1050 return pm8001_request_msix(pm8001_ha); 1051 else { 1052 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1053 goto intx; 1054 } 1055 #endif 1056 1057 intx: 1058 /* initialize the INT-X interrupt */ 1059 pm8001_ha->irq_vector[0].irq_id = 0; 1060 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1061 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1062 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1063 return rc; 1064 } 1065 1066 /** 1067 * pm8001_pci_probe - probe supported device 1068 * @pdev: pci device which kernel has been prepared for. 1069 * @ent: pci device id 1070 * 1071 * This function is the main initialization function, when register a new 1072 * pci driver it is invoked, all struct and hardware initialization should be 1073 * done here, also, register interrupt. 1074 */ 1075 static int pm8001_pci_probe(struct pci_dev *pdev, 1076 const struct pci_device_id *ent) 1077 { 1078 unsigned int rc; 1079 u32 pci_reg; 1080 u8 i = 0; 1081 struct pm8001_hba_info *pm8001_ha; 1082 struct Scsi_Host *shost = NULL; 1083 const struct pm8001_chip_info *chip; 1084 struct sas_ha_struct *sha; 1085 1086 dev_printk(KERN_INFO, &pdev->dev, 1087 "pm80xx: driver version %s\n", DRV_VERSION); 1088 rc = pci_enable_device(pdev); 1089 if (rc) 1090 goto err_out_enable; 1091 pci_set_master(pdev); 1092 /* 1093 * Enable pci slot busmaster by setting pci command register. 1094 * This is required by FW for Cyclone card. 1095 */ 1096 1097 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1098 pci_reg |= 0x157; 1099 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1100 rc = pci_request_regions(pdev, DRV_NAME); 1101 if (rc) 1102 goto err_out_disable; 1103 rc = pci_go_44(pdev); 1104 if (rc) 1105 goto err_out_regions; 1106 1107 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1108 if (!shost) { 1109 rc = -ENOMEM; 1110 goto err_out_regions; 1111 } 1112 chip = &pm8001_chips[ent->driver_data]; 1113 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1114 if (!sha) { 1115 rc = -ENOMEM; 1116 goto err_out_free_host; 1117 } 1118 SHOST_TO_SAS_HA(shost) = sha; 1119 1120 rc = pm8001_prep_sas_ha_init(shost, chip); 1121 if (rc) { 1122 rc = -ENOMEM; 1123 goto err_out_free; 1124 } 1125 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1126 /* ent->driver variable is used to differentiate between controllers */ 1127 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1128 if (!pm8001_ha) { 1129 rc = -ENOMEM; 1130 goto err_out_free; 1131 } 1132 1133 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1134 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1135 if (rc) { 1136 pm8001_dbg(pm8001_ha, FAIL, 1137 "chip_init failed [ret: %d]\n", rc); 1138 goto err_out_ha_free; 1139 } 1140 1141 rc = pm8001_init_ccb_tag(pm8001_ha); 1142 if (rc) 1143 goto err_out_enable; 1144 1145 1146 PM8001_CHIP_DISP->chip_post_init(pm8001_ha); 1147 1148 if (pm8001_ha->number_of_intr > 1) { 1149 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1; 1150 /* 1151 * For now, ensure we're not sent too many commands by setting 1152 * host_tagset. This is also required if we start using request 1153 * tag. 1154 */ 1155 shost->host_tagset = 1; 1156 } 1157 1158 rc = scsi_add_host(shost, &pdev->dev); 1159 if (rc) 1160 goto err_out_ha_free; 1161 1162 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1163 if (pm8001_ha->chip_id != chip_8001) { 1164 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1165 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1166 /* setup thermal configuration. */ 1167 pm80xx_set_thermal_config(pm8001_ha); 1168 } 1169 1170 pm8001_init_sas_add(pm8001_ha); 1171 /* phy setting support for motherboard controller */ 1172 rc = pm8001_configure_phy_settings(pm8001_ha); 1173 if (rc) 1174 goto err_out_shost; 1175 1176 pm8001_post_sas_ha_init(shost, chip); 1177 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1178 if (rc) { 1179 pm8001_dbg(pm8001_ha, FAIL, 1180 "sas_register_ha failed [ret: %d]\n", rc); 1181 goto err_out_shost; 1182 } 1183 list_add_tail(&pm8001_ha->list, &hba_list); 1184 pm8001_ha->flags = PM8001F_RUN_TIME; 1185 scsi_scan_host(pm8001_ha->shost); 1186 return 0; 1187 1188 err_out_shost: 1189 scsi_remove_host(pm8001_ha->shost); 1190 err_out_ha_free: 1191 pm8001_free(pm8001_ha); 1192 err_out_free: 1193 kfree(sha); 1194 err_out_free_host: 1195 scsi_host_put(shost); 1196 err_out_regions: 1197 pci_release_regions(pdev); 1198 err_out_disable: 1199 pci_disable_device(pdev); 1200 err_out_enable: 1201 return rc; 1202 } 1203 1204 /** 1205 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1206 * @pm8001_ha: our hba card information. 1207 */ 1208 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha) 1209 { 1210 struct Scsi_Host *shost = pm8001_ha->shost; 1211 struct device *dev = pm8001_ha->dev; 1212 u32 max_out_io, ccb_count; 1213 u32 can_queue; 1214 int i; 1215 1216 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1217 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1218 1219 /* Update to the scsi host*/ 1220 can_queue = ccb_count - PM8001_RESERVE_SLOT; 1221 shost->can_queue = can_queue; 1222 1223 pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL); 1224 if (!pm8001_ha->tags) 1225 goto err_out; 1226 1227 /* Memory region for ccb_info*/ 1228 pm8001_ha->ccb_count = ccb_count; 1229 pm8001_ha->ccb_info = 1230 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1231 if (!pm8001_ha->ccb_info) { 1232 pm8001_dbg(pm8001_ha, FAIL, 1233 "Unable to allocate memory for ccb\n"); 1234 goto err_out_noccb; 1235 } 1236 for (i = 0; i < ccb_count; i++) { 1237 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev, 1238 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1239 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1240 GFP_KERNEL); 1241 if (!pm8001_ha->ccb_info[i].buf_prd) { 1242 pm8001_dbg(pm8001_ha, FAIL, 1243 "ccb prd memory allocation error\n"); 1244 goto err_out; 1245 } 1246 pm8001_ha->ccb_info[i].task = NULL; 1247 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG; 1248 pm8001_ha->ccb_info[i].device = NULL; 1249 ++pm8001_ha->tags_num; 1250 } 1251 1252 return 0; 1253 1254 err_out_noccb: 1255 kfree(pm8001_ha->devices); 1256 err_out: 1257 return -ENOMEM; 1258 } 1259 1260 static void pm8001_pci_remove(struct pci_dev *pdev) 1261 { 1262 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1263 struct pm8001_hba_info *pm8001_ha; 1264 int i, j; 1265 pm8001_ha = sha->lldd_ha; 1266 sas_unregister_ha(sha); 1267 sas_remove_host(pm8001_ha->shost); 1268 list_del(&pm8001_ha->list); 1269 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1270 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1271 1272 #ifdef PM8001_USE_MSIX 1273 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1274 synchronize_irq(pci_irq_vector(pdev, i)); 1275 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1276 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1277 pci_free_irq_vectors(pdev); 1278 #else 1279 free_irq(pm8001_ha->irq, sha); 1280 #endif 1281 #ifdef PM8001_USE_TASKLET 1282 /* For non-msix and msix interrupts */ 1283 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1284 (pm8001_ha->chip_id == chip_8001)) 1285 tasklet_kill(&pm8001_ha->tasklet[0]); 1286 else 1287 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1288 tasklet_kill(&pm8001_ha->tasklet[j]); 1289 #endif 1290 scsi_host_put(pm8001_ha->shost); 1291 1292 for (i = 0; i < pm8001_ha->ccb_count; i++) { 1293 dma_free_coherent(&pm8001_ha->pdev->dev, 1294 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1295 pm8001_ha->ccb_info[i].buf_prd, 1296 pm8001_ha->ccb_info[i].ccb_dma_handle); 1297 } 1298 kfree(pm8001_ha->ccb_info); 1299 kfree(pm8001_ha->devices); 1300 1301 pm8001_free(pm8001_ha); 1302 kfree(sha->sas_phy); 1303 kfree(sha->sas_port); 1304 kfree(sha); 1305 pci_release_regions(pdev); 1306 pci_disable_device(pdev); 1307 } 1308 1309 /** 1310 * pm8001_pci_suspend - power management suspend main entry point 1311 * @dev: Device struct 1312 * 1313 * Return: 0 on success, anything else on error. 1314 */ 1315 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1316 { 1317 struct pci_dev *pdev = to_pci_dev(dev); 1318 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1319 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1320 int i, j; 1321 sas_suspend_ha(sha); 1322 flush_workqueue(pm8001_wq); 1323 scsi_block_requests(pm8001_ha->shost); 1324 if (!pdev->pm_cap) { 1325 dev_err(dev, " PCI PM not supported\n"); 1326 return -ENODEV; 1327 } 1328 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1329 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1330 #ifdef PM8001_USE_MSIX 1331 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1332 synchronize_irq(pci_irq_vector(pdev, i)); 1333 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1334 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1335 pci_free_irq_vectors(pdev); 1336 #else 1337 free_irq(pm8001_ha->irq, sha); 1338 #endif 1339 #ifdef PM8001_USE_TASKLET 1340 /* For non-msix and msix interrupts */ 1341 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1342 (pm8001_ha->chip_id == chip_8001)) 1343 tasklet_kill(&pm8001_ha->tasklet[0]); 1344 else 1345 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1346 tasklet_kill(&pm8001_ha->tasklet[j]); 1347 #endif 1348 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1349 "suspended state\n", pdev, 1350 pm8001_ha->name); 1351 return 0; 1352 } 1353 1354 /** 1355 * pm8001_pci_resume - power management resume main entry point 1356 * @dev: Device struct 1357 * 1358 * Return: 0 on success, anything else on error. 1359 */ 1360 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1361 { 1362 struct pci_dev *pdev = to_pci_dev(dev); 1363 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1364 struct pm8001_hba_info *pm8001_ha; 1365 int rc; 1366 u8 i = 0, j; 1367 DECLARE_COMPLETION_ONSTACK(completion); 1368 1369 pm8001_ha = sha->lldd_ha; 1370 1371 pm8001_info(pm8001_ha, 1372 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1373 pdev, pm8001_ha->name, pdev->current_state); 1374 1375 rc = pci_go_44(pdev); 1376 if (rc) 1377 goto err_out_disable; 1378 sas_prep_resume_ha(sha); 1379 /* chip soft rst only for spc */ 1380 if (pm8001_ha->chip_id == chip_8001) { 1381 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1382 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1383 } 1384 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1385 if (rc) 1386 goto err_out_disable; 1387 1388 /* disable all the interrupt bits */ 1389 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1390 1391 rc = pm8001_request_irq(pm8001_ha); 1392 if (rc) 1393 goto err_out_disable; 1394 #ifdef PM8001_USE_TASKLET 1395 /* Tasklet for non msi-x interrupt handler */ 1396 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1397 (pm8001_ha->chip_id == chip_8001)) 1398 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1399 (unsigned long)&(pm8001_ha->irq_vector[0])); 1400 else 1401 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1402 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1403 (unsigned long)&(pm8001_ha->irq_vector[j])); 1404 #endif 1405 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1406 if (pm8001_ha->chip_id != chip_8001) { 1407 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1408 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1409 } 1410 1411 /* Chip documentation for the 8070 and 8072 SPCv */ 1412 /* states that a 500ms minimum delay is required */ 1413 /* before issuing commands. Otherwise, the firmware */ 1414 /* will enter an unrecoverable state. */ 1415 1416 if (pm8001_ha->chip_id == chip_8070 || 1417 pm8001_ha->chip_id == chip_8072) { 1418 mdelay(500); 1419 } 1420 1421 /* Spin up the PHYs */ 1422 1423 pm8001_ha->flags = PM8001F_RUN_TIME; 1424 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1425 pm8001_ha->phy[i].enable_completion = &completion; 1426 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1427 wait_for_completion(&completion); 1428 } 1429 sas_resume_ha(sha); 1430 return 0; 1431 1432 err_out_disable: 1433 scsi_remove_host(pm8001_ha->shost); 1434 1435 return rc; 1436 } 1437 1438 /* update of pci device, vendor id and driver data with 1439 * unique value for each of the controller 1440 */ 1441 static struct pci_device_id pm8001_pci_table[] = { 1442 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1443 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1444 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1445 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1446 /* Support for SPC/SPCv/SPCve controllers */ 1447 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1448 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1449 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1450 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1451 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1452 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1453 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1454 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1455 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1456 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1457 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1458 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1459 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1460 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1461 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1462 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1463 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1464 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1465 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1466 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1467 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1468 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1469 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1470 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1471 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1472 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1473 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1474 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1475 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1476 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1477 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1478 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1479 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1480 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1481 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1482 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1483 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1484 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1485 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1486 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1487 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1488 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1489 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1490 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1491 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1492 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1493 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1494 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1495 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1496 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1497 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1498 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1499 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1500 { PCI_VENDOR_ID_ATTO, 0x8070, 1501 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1502 { PCI_VENDOR_ID_ATTO, 0x8070, 1503 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1504 { PCI_VENDOR_ID_ATTO, 0x8072, 1505 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1506 { PCI_VENDOR_ID_ATTO, 0x8072, 1507 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1508 { PCI_VENDOR_ID_ATTO, 0x8070, 1509 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1510 { PCI_VENDOR_ID_ATTO, 0x8072, 1511 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1512 { PCI_VENDOR_ID_ATTO, 0x8072, 1513 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1514 {} /* terminate list */ 1515 }; 1516 1517 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1518 pm8001_pci_suspend, 1519 pm8001_pci_resume); 1520 1521 static struct pci_driver pm8001_pci_driver = { 1522 .name = DRV_NAME, 1523 .id_table = pm8001_pci_table, 1524 .probe = pm8001_pci_probe, 1525 .remove = pm8001_pci_remove, 1526 .driver.pm = &pm8001_pci_pm_ops, 1527 }; 1528 1529 /** 1530 * pm8001_init - initialize scsi transport template 1531 */ 1532 static int __init pm8001_init(void) 1533 { 1534 int rc = -ENOMEM; 1535 1536 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1537 if (!pm8001_wq) 1538 goto err; 1539 1540 pm8001_id = 0; 1541 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1542 if (!pm8001_stt) 1543 goto err_wq; 1544 rc = pci_register_driver(&pm8001_pci_driver); 1545 if (rc) 1546 goto err_tp; 1547 return 0; 1548 1549 err_tp: 1550 sas_release_transport(pm8001_stt); 1551 err_wq: 1552 destroy_workqueue(pm8001_wq); 1553 err: 1554 return rc; 1555 } 1556 1557 static void __exit pm8001_exit(void) 1558 { 1559 pci_unregister_driver(&pm8001_pci_driver); 1560 sas_release_transport(pm8001_stt); 1561 destroy_workqueue(pm8001_wq); 1562 } 1563 1564 module_init(pm8001_init); 1565 module_exit(pm8001_exit); 1566 1567 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1568 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1569 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1570 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1571 MODULE_DESCRIPTION( 1572 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1573 "SAS/SATA controller driver"); 1574 MODULE_VERSION(DRV_VERSION); 1575 MODULE_LICENSE("GPL"); 1576 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1577 1578