1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *); 60 61 /* 62 * chip info structure to identify chip key functionality as 63 * encryption available/not, no of ports, hw specific function ref 64 */ 65 static const struct pm8001_chip_info pm8001_chips[] = { 66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 77 }; 78 static int pm8001_id; 79 80 LIST_HEAD(hba_list); 81 82 struct workqueue_struct *pm8001_wq; 83 84 /* 85 * The main structure which LLDD must register for scsi core. 86 */ 87 static struct scsi_host_template pm8001_sht = { 88 .module = THIS_MODULE, 89 .name = DRV_NAME, 90 .queuecommand = sas_queuecommand, 91 .dma_need_drain = ata_scsi_dma_need_drain, 92 .target_alloc = sas_target_alloc, 93 .slave_configure = sas_slave_configure, 94 .scan_finished = pm8001_scan_finished, 95 .scan_start = pm8001_scan_start, 96 .change_queue_depth = sas_change_queue_depth, 97 .bios_param = sas_bios_param, 98 .can_queue = 1, 99 .this_id = -1, 100 .sg_tablesize = PM8001_MAX_DMA_SG, 101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 102 .eh_device_reset_handler = sas_eh_device_reset_handler, 103 .eh_target_reset_handler = sas_eh_target_reset_handler, 104 .target_destroy = sas_target_destroy, 105 .ioctl = sas_ioctl, 106 #ifdef CONFIG_COMPAT 107 .compat_ioctl = sas_ioctl, 108 #endif 109 .shost_attrs = pm8001_host_attrs, 110 .track_queue_depth = 1, 111 }; 112 113 /* 114 * Sas layer call this function to execute specific task. 115 */ 116 static struct sas_domain_function_template pm8001_transport_ops = { 117 .lldd_dev_found = pm8001_dev_found, 118 .lldd_dev_gone = pm8001_dev_gone, 119 120 .lldd_execute_task = pm8001_queue_command, 121 .lldd_control_phy = pm8001_phy_control, 122 123 .lldd_abort_task = pm8001_abort_task, 124 .lldd_abort_task_set = pm8001_abort_task_set, 125 .lldd_clear_aca = pm8001_clear_aca, 126 .lldd_clear_task_set = pm8001_clear_task_set, 127 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 128 .lldd_lu_reset = pm8001_lu_reset, 129 .lldd_query_task = pm8001_query_task, 130 }; 131 132 /** 133 * pm8001_phy_init - initiate our adapter phys 134 * @pm8001_ha: our hba structure. 135 * @phy_id: phy id. 136 */ 137 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 138 { 139 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 140 struct asd_sas_phy *sas_phy = &phy->sas_phy; 141 phy->phy_state = PHY_LINK_DISABLE; 142 phy->pm8001_ha = pm8001_ha; 143 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 144 sas_phy->class = SAS; 145 sas_phy->iproto = SAS_PROTOCOL_ALL; 146 sas_phy->tproto = 0; 147 sas_phy->type = PHY_TYPE_PHYSICAL; 148 sas_phy->role = PHY_ROLE_INITIATOR; 149 sas_phy->oob_mode = OOB_NOT_CONNECTED; 150 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 151 sas_phy->id = phy_id; 152 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 153 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 154 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 155 sas_phy->lldd_phy = phy; 156 } 157 158 /** 159 * pm8001_free - free hba 160 * @pm8001_ha: our hba structure. 161 */ 162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 163 { 164 int i; 165 166 if (!pm8001_ha) 167 return; 168 169 for (i = 0; i < USI_MAX_MEMCNT; i++) { 170 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 171 dma_free_coherent(&pm8001_ha->pdev->dev, 172 (pm8001_ha->memoryMap.region[i].total_len + 173 pm8001_ha->memoryMap.region[i].alignment), 174 pm8001_ha->memoryMap.region[i].virt_ptr, 175 pm8001_ha->memoryMap.region[i].phys_addr); 176 } 177 } 178 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 179 flush_workqueue(pm8001_wq); 180 kfree(pm8001_ha->tags); 181 kfree(pm8001_ha); 182 } 183 184 #ifdef PM8001_USE_TASKLET 185 186 /** 187 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 188 * @opaque: the passed general host adapter struct 189 * Note: pm8001_tasklet is common for pm8001 & pm80xx 190 */ 191 static void pm8001_tasklet(unsigned long opaque) 192 { 193 struct pm8001_hba_info *pm8001_ha; 194 struct isr_param *irq_vector; 195 196 irq_vector = (struct isr_param *)opaque; 197 pm8001_ha = irq_vector->drv_inst; 198 if (unlikely(!pm8001_ha)) 199 BUG_ON(1); 200 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 201 } 202 #endif 203 204 /** 205 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 206 * It obtains the vector number and calls the equivalent bottom 207 * half or services directly. 208 * @irq: interrupt number 209 * @opaque: the passed outbound queue/vector. Host structure is 210 * retrieved from the same. 211 */ 212 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 213 { 214 struct isr_param *irq_vector; 215 struct pm8001_hba_info *pm8001_ha; 216 irqreturn_t ret = IRQ_HANDLED; 217 irq_vector = (struct isr_param *)opaque; 218 pm8001_ha = irq_vector->drv_inst; 219 220 if (unlikely(!pm8001_ha)) 221 return IRQ_NONE; 222 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 223 return IRQ_NONE; 224 #ifdef PM8001_USE_TASKLET 225 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 226 #else 227 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 228 #endif 229 return ret; 230 } 231 232 /** 233 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 234 * @irq: interrupt number 235 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 236 */ 237 238 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 239 { 240 struct pm8001_hba_info *pm8001_ha; 241 irqreturn_t ret = IRQ_HANDLED; 242 struct sas_ha_struct *sha = dev_id; 243 pm8001_ha = sha->lldd_ha; 244 if (unlikely(!pm8001_ha)) 245 return IRQ_NONE; 246 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 247 return IRQ_NONE; 248 249 #ifdef PM8001_USE_TASKLET 250 tasklet_schedule(&pm8001_ha->tasklet[0]); 251 #else 252 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 253 #endif 254 return ret; 255 } 256 257 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 258 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 259 260 /** 261 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 262 * @pm8001_ha: our hba structure. 263 * @ent: PCI device ID structure to match on 264 */ 265 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 266 const struct pci_device_id *ent) 267 { 268 int i, count = 0, rc = 0; 269 u32 ci_offset, ib_offset, ob_offset, pi_offset; 270 struct inbound_queue_table *ibq; 271 struct outbound_queue_table *obq; 272 273 spin_lock_init(&pm8001_ha->lock); 274 spin_lock_init(&pm8001_ha->bitmap_lock); 275 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 276 pm8001_ha->chip->n_phy); 277 278 /* Setup Interrupt */ 279 rc = pm8001_setup_irq(pm8001_ha); 280 if (rc) { 281 pm8001_dbg(pm8001_ha, FAIL, 282 "pm8001_setup_irq failed [ret: %d]\n", rc); 283 goto err_out_shost; 284 } 285 /* Request Interrupt */ 286 rc = pm8001_request_irq(pm8001_ha); 287 if (rc) 288 goto err_out_shost; 289 290 count = pm8001_ha->max_q_num; 291 /* Queues are chosen based on the number of cores/msix availability */ 292 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 293 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 294 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 295 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 296 pm8001_ha->max_memcnt = pi_offset + count; 297 298 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 299 pm8001_phy_init(pm8001_ha, i); 300 pm8001_ha->port[i].wide_port_phymap = 0; 301 pm8001_ha->port[i].port_attached = 0; 302 pm8001_ha->port[i].port_state = 0; 303 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 304 } 305 306 /* MPI Memory region 1 for AAP Event Log for fw */ 307 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 308 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 309 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 310 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 311 312 /* MPI Memory region 2 for IOP Event Log for fw */ 313 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 314 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 315 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 316 pm8001_ha->memoryMap.region[IOP].alignment = 32; 317 318 for (i = 0; i < count; i++) { 319 ibq = &pm8001_ha->inbnd_q_tbl[i]; 320 spin_lock_init(&ibq->iq_lock); 321 /* MPI Memory region 3 for consumer Index of inbound queues */ 322 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 323 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 324 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 325 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 326 327 if ((ent->driver_data) != chip_8001) { 328 /* MPI Memory region 5 inbound queues */ 329 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 330 PM8001_MPI_QUEUE; 331 pm8001_ha->memoryMap.region[ib_offset+i].element_size 332 = 128; 333 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 334 PM8001_MPI_QUEUE * 128; 335 pm8001_ha->memoryMap.region[ib_offset+i].alignment 336 = 128; 337 } else { 338 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 339 PM8001_MPI_QUEUE; 340 pm8001_ha->memoryMap.region[ib_offset+i].element_size 341 = 64; 342 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 343 PM8001_MPI_QUEUE * 64; 344 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 345 } 346 } 347 348 for (i = 0; i < count; i++) { 349 obq = &pm8001_ha->outbnd_q_tbl[i]; 350 spin_lock_init(&obq->oq_lock); 351 /* MPI Memory region 4 for producer Index of outbound queues */ 352 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 353 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 354 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 355 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 356 357 if (ent->driver_data != chip_8001) { 358 /* MPI Memory region 6 Outbound queues */ 359 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 360 PM8001_MPI_QUEUE; 361 pm8001_ha->memoryMap.region[ob_offset+i].element_size 362 = 128; 363 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 364 PM8001_MPI_QUEUE * 128; 365 pm8001_ha->memoryMap.region[ob_offset+i].alignment 366 = 128; 367 } else { 368 /* MPI Memory region 6 Outbound queues */ 369 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 370 PM8001_MPI_QUEUE; 371 pm8001_ha->memoryMap.region[ob_offset+i].element_size 372 = 64; 373 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 374 PM8001_MPI_QUEUE * 64; 375 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 376 } 377 378 } 379 /* Memory region write DMA*/ 380 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 381 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 382 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 383 384 /* Memory region for fw flash */ 385 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 386 387 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 388 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 389 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 390 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 391 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 392 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 393 394 if (pm8001_mem_alloc(pm8001_ha->pdev, 395 ®ion->virt_ptr, 396 ®ion->phys_addr, 397 ®ion->phys_addr_hi, 398 ®ion->phys_addr_lo, 399 region->total_len, 400 region->alignment) != 0) { 401 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 402 goto err_out; 403 } 404 } 405 406 /* Memory region for devices*/ 407 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 408 * sizeof(struct pm8001_device), GFP_KERNEL); 409 if (!pm8001_ha->devices) { 410 rc = -ENOMEM; 411 goto err_out_nodev; 412 } 413 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 414 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 415 pm8001_ha->devices[i].id = i; 416 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 417 atomic_set(&pm8001_ha->devices[i].running_req, 0); 418 } 419 pm8001_ha->flags = PM8001F_INIT_TIME; 420 /* Initialize tags */ 421 pm8001_tag_init(pm8001_ha); 422 return 0; 423 424 err_out_shost: 425 scsi_remove_host(pm8001_ha->shost); 426 err_out_nodev: 427 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 428 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 429 dma_free_coherent(&pm8001_ha->pdev->dev, 430 (pm8001_ha->memoryMap.region[i].total_len + 431 pm8001_ha->memoryMap.region[i].alignment), 432 pm8001_ha->memoryMap.region[i].virt_ptr, 433 pm8001_ha->memoryMap.region[i].phys_addr); 434 } 435 } 436 err_out: 437 return 1; 438 } 439 440 /** 441 * pm8001_ioremap - remap the pci high physical address to kernal virtual 442 * address so that we can access them. 443 * @pm8001_ha:our hba structure. 444 */ 445 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 446 { 447 u32 bar; 448 u32 logicalBar = 0; 449 struct pci_dev *pdev; 450 451 pdev = pm8001_ha->pdev; 452 /* map pci mem (PMC pci base 0-3)*/ 453 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 454 /* 455 ** logical BARs for SPC: 456 ** bar 0 and 1 - logical BAR0 457 ** bar 2 and 3 - logical BAR1 458 ** bar4 - logical BAR2 459 ** bar5 - logical BAR3 460 ** Skip the appropriate assignments: 461 */ 462 if ((bar == 1) || (bar == 3)) 463 continue; 464 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 465 pm8001_ha->io_mem[logicalBar].membase = 466 pci_resource_start(pdev, bar); 467 pm8001_ha->io_mem[logicalBar].memsize = 468 pci_resource_len(pdev, bar); 469 pm8001_ha->io_mem[logicalBar].memvirtaddr = 470 ioremap(pm8001_ha->io_mem[logicalBar].membase, 471 pm8001_ha->io_mem[logicalBar].memsize); 472 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 473 pm8001_dbg(pm8001_ha, INIT, 474 "Failed to ioremap bar %d, logicalBar %d", 475 bar, logicalBar); 476 return -ENOMEM; 477 } 478 pm8001_dbg(pm8001_ha, INIT, 479 "base addr %llx virt_addr=%llx len=%d\n", 480 (u64)pm8001_ha->io_mem[logicalBar].membase, 481 (u64)(unsigned long) 482 pm8001_ha->io_mem[logicalBar].memvirtaddr, 483 pm8001_ha->io_mem[logicalBar].memsize); 484 } else { 485 pm8001_ha->io_mem[logicalBar].membase = 0; 486 pm8001_ha->io_mem[logicalBar].memsize = 0; 487 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 488 } 489 logicalBar++; 490 } 491 return 0; 492 } 493 494 /** 495 * pm8001_pci_alloc - initialize our ha card structure 496 * @pdev: pci device. 497 * @ent: ent 498 * @shost: scsi host struct which has been initialized before. 499 */ 500 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 501 const struct pci_device_id *ent, 502 struct Scsi_Host *shost) 503 504 { 505 struct pm8001_hba_info *pm8001_ha; 506 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 507 int j; 508 509 pm8001_ha = sha->lldd_ha; 510 if (!pm8001_ha) 511 return NULL; 512 513 pm8001_ha->pdev = pdev; 514 pm8001_ha->dev = &pdev->dev; 515 pm8001_ha->chip_id = ent->driver_data; 516 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 517 pm8001_ha->irq = pdev->irq; 518 pm8001_ha->sas = sha; 519 pm8001_ha->shost = shost; 520 pm8001_ha->id = pm8001_id++; 521 pm8001_ha->logging_level = logging_level; 522 pm8001_ha->non_fatal_count = 0; 523 if (link_rate >= 1 && link_rate <= 15) 524 pm8001_ha->link_rate = (link_rate << 8); 525 else { 526 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 527 LINKRATE_60 | LINKRATE_120; 528 pm8001_dbg(pm8001_ha, FAIL, 529 "Setting link rate to default value\n"); 530 } 531 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 532 /* IOMB size is 128 for 8088/89 controllers */ 533 if (pm8001_ha->chip_id != chip_8001) 534 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 535 else 536 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 537 538 #ifdef PM8001_USE_TASKLET 539 /* Tasklet for non msi-x interrupt handler */ 540 if ((!pdev->msix_cap || !pci_msi_enabled()) 541 || (pm8001_ha->chip_id == chip_8001)) 542 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 543 (unsigned long)&(pm8001_ha->irq_vector[0])); 544 else 545 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 546 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 547 (unsigned long)&(pm8001_ha->irq_vector[j])); 548 #endif 549 if (pm8001_ioremap(pm8001_ha)) 550 goto failed_pci_alloc; 551 if (!pm8001_alloc(pm8001_ha, ent)) 552 return pm8001_ha; 553 failed_pci_alloc: 554 pm8001_free(pm8001_ha); 555 return NULL; 556 } 557 558 /** 559 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 560 * @pdev: pci device. 561 */ 562 static int pci_go_44(struct pci_dev *pdev) 563 { 564 int rc; 565 566 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 567 if (rc) { 568 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 569 if (rc) 570 dev_printk(KERN_ERR, &pdev->dev, 571 "32-bit DMA enable failed\n"); 572 } 573 return rc; 574 } 575 576 /** 577 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 578 * @shost: scsi host which has been allocated outside. 579 * @chip_info: our ha struct. 580 */ 581 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 582 const struct pm8001_chip_info *chip_info) 583 { 584 int phy_nr, port_nr; 585 struct asd_sas_phy **arr_phy; 586 struct asd_sas_port **arr_port; 587 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 588 589 phy_nr = chip_info->n_phy; 590 port_nr = phy_nr; 591 memset(sha, 0x00, sizeof(*sha)); 592 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 593 if (!arr_phy) 594 goto exit; 595 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 596 if (!arr_port) 597 goto exit_free2; 598 599 sha->sas_phy = arr_phy; 600 sha->sas_port = arr_port; 601 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 602 if (!sha->lldd_ha) 603 goto exit_free1; 604 605 shost->transportt = pm8001_stt; 606 shost->max_id = PM8001_MAX_DEVICES; 607 shost->max_lun = 8; 608 shost->max_channel = 0; 609 shost->unique_id = pm8001_id; 610 shost->max_cmd_len = 16; 611 shost->can_queue = PM8001_CAN_QUEUE; 612 shost->cmd_per_lun = 32; 613 return 0; 614 exit_free1: 615 kfree(arr_port); 616 exit_free2: 617 kfree(arr_phy); 618 exit: 619 return -1; 620 } 621 622 /** 623 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 624 * @shost: scsi host which has been allocated outside 625 * @chip_info: our ha struct. 626 */ 627 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 628 const struct pm8001_chip_info *chip_info) 629 { 630 int i = 0; 631 struct pm8001_hba_info *pm8001_ha; 632 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 633 634 pm8001_ha = sha->lldd_ha; 635 for (i = 0; i < chip_info->n_phy; i++) { 636 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 637 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 638 sha->sas_phy[i]->sas_addr = 639 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 640 } 641 sha->sas_ha_name = DRV_NAME; 642 sha->dev = pm8001_ha->dev; 643 sha->strict_wide_ports = 1; 644 sha->lldd_module = THIS_MODULE; 645 sha->sas_addr = &pm8001_ha->sas_addr[0]; 646 sha->num_phys = chip_info->n_phy; 647 sha->core.shost = shost; 648 } 649 650 /** 651 * pm8001_init_sas_add - initialize sas address 652 * @pm8001_ha: our ha struct. 653 * 654 * Currently we just set the fixed SAS address to our HBA,for manufacture, 655 * it should read from the EEPROM 656 */ 657 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 658 { 659 u8 i, j; 660 u8 sas_add[8]; 661 #ifdef PM8001_READ_VPD 662 /* For new SPC controllers WWN is stored in flash vpd 663 * For SPC/SPCve controllers WWN is stored in EEPROM 664 * For Older SPC WWN is stored in NVMD 665 */ 666 DECLARE_COMPLETION_ONSTACK(completion); 667 struct pm8001_ioctl_payload payload; 668 u16 deviceid; 669 int rc; 670 671 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 672 pm8001_ha->nvmd_completion = &completion; 673 674 if (pm8001_ha->chip_id == chip_8001) { 675 if (deviceid == 0x8081 || deviceid == 0x0042) { 676 payload.minor_function = 4; 677 payload.rd_length = 4096; 678 } else { 679 payload.minor_function = 0; 680 payload.rd_length = 128; 681 } 682 } else if ((pm8001_ha->chip_id == chip_8070 || 683 pm8001_ha->chip_id == chip_8072) && 684 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 685 payload.minor_function = 4; 686 payload.rd_length = 4096; 687 } else { 688 payload.minor_function = 1; 689 payload.rd_length = 4096; 690 } 691 payload.offset = 0; 692 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 693 if (!payload.func_specific) { 694 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); 695 return; 696 } 697 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 698 if (rc) { 699 kfree(payload.func_specific); 700 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 701 return; 702 } 703 wait_for_completion(&completion); 704 705 for (i = 0, j = 0; i <= 7; i++, j++) { 706 if (pm8001_ha->chip_id == chip_8001) { 707 if (deviceid == 0x8081) 708 pm8001_ha->sas_addr[j] = 709 payload.func_specific[0x704 + i]; 710 else if (deviceid == 0x0042) 711 pm8001_ha->sas_addr[j] = 712 payload.func_specific[0x010 + i]; 713 } else if ((pm8001_ha->chip_id == chip_8070 || 714 pm8001_ha->chip_id == chip_8072) && 715 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 716 pm8001_ha->sas_addr[j] = 717 payload.func_specific[0x010 + i]; 718 } else 719 pm8001_ha->sas_addr[j] = 720 payload.func_specific[0x804 + i]; 721 } 722 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 723 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 724 if (i && ((i % 4) == 0)) 725 sas_add[7] = sas_add[7] + 4; 726 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 727 sas_add, SAS_ADDR_SIZE); 728 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 729 pm8001_ha->phy[i].dev_sas_addr); 730 } 731 kfree(payload.func_specific); 732 #else 733 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 734 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 735 pm8001_ha->phy[i].dev_sas_addr = 736 cpu_to_be64((u64) 737 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 738 } 739 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 740 SAS_ADDR_SIZE); 741 #endif 742 } 743 744 /* 745 * pm8001_get_phy_settings_info : Read phy setting values. 746 * @pm8001_ha : our hba. 747 */ 748 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 749 { 750 751 #ifdef PM8001_READ_VPD 752 /*OPTION ROM FLASH read for the SPC cards */ 753 DECLARE_COMPLETION_ONSTACK(completion); 754 struct pm8001_ioctl_payload payload; 755 int rc; 756 757 pm8001_ha->nvmd_completion = &completion; 758 /* SAS ADDRESS read from flash / EEPROM */ 759 payload.minor_function = 6; 760 payload.offset = 0; 761 payload.rd_length = 4096; 762 payload.func_specific = kzalloc(4096, GFP_KERNEL); 763 if (!payload.func_specific) 764 return -ENOMEM; 765 /* Read phy setting values from flash */ 766 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 767 if (rc) { 768 kfree(payload.func_specific); 769 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 770 return -ENOMEM; 771 } 772 wait_for_completion(&completion); 773 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 774 kfree(payload.func_specific); 775 #endif 776 return 0; 777 } 778 779 struct pm8001_mpi3_phy_pg_trx_config { 780 u32 LaneLosCfg; 781 u32 LanePgaCfg1; 782 u32 LanePisoCfg1; 783 u32 LanePisoCfg2; 784 u32 LanePisoCfg3; 785 u32 LanePisoCfg4; 786 u32 LanePisoCfg5; 787 u32 LanePisoCfg6; 788 u32 LaneBctCtrl; 789 }; 790 791 /** 792 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 793 * @pm8001_ha : our adapter 794 * @phycfg : PHY config page to populate 795 */ 796 static 797 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 798 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 799 { 800 phycfg->LaneLosCfg = 0x00000132; 801 phycfg->LanePgaCfg1 = 0x00203949; 802 phycfg->LanePisoCfg1 = 0x000000FF; 803 phycfg->LanePisoCfg2 = 0xFF000001; 804 phycfg->LanePisoCfg3 = 0xE7011300; 805 phycfg->LanePisoCfg4 = 0x631C40C0; 806 phycfg->LanePisoCfg5 = 0xF8102036; 807 phycfg->LanePisoCfg6 = 0xF74A1000; 808 phycfg->LaneBctCtrl = 0x00FB33F8; 809 } 810 811 /** 812 * pm8001_get_external_phy_settings : Retrieves the external PHY settings 813 * @pm8001_ha : our adapter 814 * @phycfg : PHY config page to populate 815 */ 816 static 817 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 818 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 819 { 820 phycfg->LaneLosCfg = 0x00000132; 821 phycfg->LanePgaCfg1 = 0x00203949; 822 phycfg->LanePisoCfg1 = 0x000000FF; 823 phycfg->LanePisoCfg2 = 0xFF000001; 824 phycfg->LanePisoCfg3 = 0xE7011300; 825 phycfg->LanePisoCfg4 = 0x63349140; 826 phycfg->LanePisoCfg5 = 0xF8102036; 827 phycfg->LanePisoCfg6 = 0xF80D9300; 828 phycfg->LaneBctCtrl = 0x00FB33F8; 829 } 830 831 /** 832 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 833 * @pm8001_ha : our adapter 834 * @phymask : The PHY mask 835 */ 836 static 837 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 838 { 839 switch (pm8001_ha->pdev->subsystem_device) { 840 case 0x0070: /* H1280 - 8 external 0 internal */ 841 case 0x0072: /* H12F0 - 16 external 0 internal */ 842 *phymask = 0x0000; 843 break; 844 845 case 0x0071: /* H1208 - 0 external 8 internal */ 846 case 0x0073: /* H120F - 0 external 16 internal */ 847 *phymask = 0xFFFF; 848 break; 849 850 case 0x0080: /* H1244 - 4 external 4 internal */ 851 *phymask = 0x00F0; 852 break; 853 854 case 0x0081: /* H1248 - 4 external 8 internal */ 855 *phymask = 0x0FF0; 856 break; 857 858 case 0x0082: /* H1288 - 8 external 8 internal */ 859 *phymask = 0xFF00; 860 break; 861 862 default: 863 pm8001_dbg(pm8001_ha, INIT, 864 "Unknown subsystem device=0x%.04x\n", 865 pm8001_ha->pdev->subsystem_device); 866 } 867 } 868 869 /** 870 * pm8001_set_phy_settings_ven_117c_12G() : Configure ATTO 12Gb PHY settings 871 * @pm8001_ha : our adapter 872 */ 873 static 874 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 875 { 876 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 877 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 878 int phymask = 0; 879 int i = 0; 880 881 memset(&phycfg_int, 0, sizeof(phycfg_int)); 882 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 883 884 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 885 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 886 pm8001_get_phy_mask(pm8001_ha, &phymask); 887 888 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 889 if (phymask & (1 << i)) {/* Internal PHY */ 890 pm8001_set_phy_profile_single(pm8001_ha, i, 891 sizeof(phycfg_int) / sizeof(u32), 892 (u32 *)&phycfg_int); 893 894 } else { /* External PHY */ 895 pm8001_set_phy_profile_single(pm8001_ha, i, 896 sizeof(phycfg_ext) / sizeof(u32), 897 (u32 *)&phycfg_ext); 898 } 899 } 900 901 return 0; 902 } 903 904 /** 905 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 906 * @pm8001_ha : our hba. 907 */ 908 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 909 { 910 switch (pm8001_ha->pdev->subsystem_vendor) { 911 case PCI_VENDOR_ID_ATTO: 912 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 913 return 0; 914 else 915 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 916 917 case PCI_VENDOR_ID_ADAPTEC2: 918 case 0: 919 return 0; 920 921 default: 922 return pm8001_get_phy_settings_info(pm8001_ha); 923 } 924 } 925 926 #ifdef PM8001_USE_MSIX 927 /** 928 * pm8001_setup_msix - enable MSI-X interrupt 929 * @pm8001_ha: our ha struct. 930 */ 931 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 932 { 933 u32 number_of_intr; 934 int rc, cpu_online_count; 935 unsigned int allocated_irq_vectors; 936 937 /* SPCv controllers supports 64 msi-x */ 938 if (pm8001_ha->chip_id == chip_8001) { 939 number_of_intr = 1; 940 } else { 941 number_of_intr = PM8001_MAX_MSIX_VEC; 942 } 943 944 cpu_online_count = num_online_cpus(); 945 number_of_intr = min_t(int, cpu_online_count, number_of_intr); 946 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 947 number_of_intr, PCI_IRQ_MSIX); 948 allocated_irq_vectors = rc; 949 if (rc < 0) 950 return rc; 951 952 /* Assigns the number of interrupts */ 953 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr); 954 pm8001_ha->number_of_intr = number_of_intr; 955 956 /* Maximum queue number updating in HBA structure */ 957 pm8001_ha->max_q_num = number_of_intr; 958 959 pm8001_dbg(pm8001_ha, INIT, 960 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 961 rc, pm8001_ha->number_of_intr); 962 return 0; 963 } 964 965 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 966 { 967 u32 i = 0, j = 0; 968 int flag = 0, rc = 0; 969 int nr_irqs = pm8001_ha->number_of_intr; 970 971 if (pm8001_ha->chip_id != chip_8001) 972 flag &= ~IRQF_SHARED; 973 974 pm8001_dbg(pm8001_ha, INIT, 975 "pci_enable_msix request number of intr %d\n", 976 pm8001_ha->number_of_intr); 977 978 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 979 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 980 981 for (i = 0; i < nr_irqs; i++) { 982 snprintf(pm8001_ha->intr_drvname[i], 983 sizeof(pm8001_ha->intr_drvname[0]), 984 "%s-%d", pm8001_ha->name, i); 985 pm8001_ha->irq_vector[i].irq_id = i; 986 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 987 988 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 989 pm8001_interrupt_handler_msix, flag, 990 pm8001_ha->intr_drvname[i], 991 &(pm8001_ha->irq_vector[i])); 992 if (rc) { 993 for (j = 0; j < i; j++) { 994 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 995 &(pm8001_ha->irq_vector[i])); 996 } 997 pci_free_irq_vectors(pm8001_ha->pdev); 998 break; 999 } 1000 } 1001 1002 return rc; 1003 } 1004 #endif 1005 1006 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 1007 { 1008 struct pci_dev *pdev; 1009 1010 pdev = pm8001_ha->pdev; 1011 1012 #ifdef PM8001_USE_MSIX 1013 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 1014 return pm8001_setup_msix(pm8001_ha); 1015 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1016 #endif 1017 return 0; 1018 } 1019 1020 /** 1021 * pm8001_request_irq - register interrupt 1022 * @pm8001_ha: our ha struct. 1023 */ 1024 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1025 { 1026 struct pci_dev *pdev; 1027 int rc; 1028 1029 pdev = pm8001_ha->pdev; 1030 1031 #ifdef PM8001_USE_MSIX 1032 if (pdev->msix_cap && pci_msi_enabled()) 1033 return pm8001_request_msix(pm8001_ha); 1034 else { 1035 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1036 goto intx; 1037 } 1038 #endif 1039 1040 intx: 1041 /* initialize the INT-X interrupt */ 1042 pm8001_ha->irq_vector[0].irq_id = 0; 1043 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1044 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1045 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1046 return rc; 1047 } 1048 1049 /** 1050 * pm8001_pci_probe - probe supported device 1051 * @pdev: pci device which kernel has been prepared for. 1052 * @ent: pci device id 1053 * 1054 * This function is the main initialization function, when register a new 1055 * pci driver it is invoked, all struct an hardware initilization should be done 1056 * here, also, register interrupt 1057 */ 1058 static int pm8001_pci_probe(struct pci_dev *pdev, 1059 const struct pci_device_id *ent) 1060 { 1061 unsigned int rc; 1062 u32 pci_reg; 1063 u8 i = 0; 1064 struct pm8001_hba_info *pm8001_ha; 1065 struct Scsi_Host *shost = NULL; 1066 const struct pm8001_chip_info *chip; 1067 struct sas_ha_struct *sha; 1068 1069 dev_printk(KERN_INFO, &pdev->dev, 1070 "pm80xx: driver version %s\n", DRV_VERSION); 1071 rc = pci_enable_device(pdev); 1072 if (rc) 1073 goto err_out_enable; 1074 pci_set_master(pdev); 1075 /* 1076 * Enable pci slot busmaster by setting pci command register. 1077 * This is required by FW for Cyclone card. 1078 */ 1079 1080 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1081 pci_reg |= 0x157; 1082 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1083 rc = pci_request_regions(pdev, DRV_NAME); 1084 if (rc) 1085 goto err_out_disable; 1086 rc = pci_go_44(pdev); 1087 if (rc) 1088 goto err_out_regions; 1089 1090 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1091 if (!shost) { 1092 rc = -ENOMEM; 1093 goto err_out_regions; 1094 } 1095 chip = &pm8001_chips[ent->driver_data]; 1096 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1097 if (!sha) { 1098 rc = -ENOMEM; 1099 goto err_out_free_host; 1100 } 1101 SHOST_TO_SAS_HA(shost) = sha; 1102 1103 rc = pm8001_prep_sas_ha_init(shost, chip); 1104 if (rc) { 1105 rc = -ENOMEM; 1106 goto err_out_free; 1107 } 1108 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1109 /* ent->driver variable is used to differentiate between controllers */ 1110 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1111 if (!pm8001_ha) { 1112 rc = -ENOMEM; 1113 goto err_out_free; 1114 } 1115 1116 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1117 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1118 if (rc) { 1119 pm8001_dbg(pm8001_ha, FAIL, 1120 "chip_init failed [ret: %d]\n", rc); 1121 goto err_out_ha_free; 1122 } 1123 1124 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev); 1125 if (rc) 1126 goto err_out_enable; 1127 1128 rc = scsi_add_host(shost, &pdev->dev); 1129 if (rc) 1130 goto err_out_ha_free; 1131 1132 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1133 if (pm8001_ha->chip_id != chip_8001) { 1134 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1135 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1136 /* setup thermal configuration. */ 1137 pm80xx_set_thermal_config(pm8001_ha); 1138 } 1139 1140 pm8001_init_sas_add(pm8001_ha); 1141 /* phy setting support for motherboard controller */ 1142 rc = pm8001_configure_phy_settings(pm8001_ha); 1143 if (rc) 1144 goto err_out_shost; 1145 1146 pm8001_post_sas_ha_init(shost, chip); 1147 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1148 if (rc) { 1149 pm8001_dbg(pm8001_ha, FAIL, 1150 "sas_register_ha failed [ret: %d]\n", rc); 1151 goto err_out_shost; 1152 } 1153 list_add_tail(&pm8001_ha->list, &hba_list); 1154 pm8001_ha->flags = PM8001F_RUN_TIME; 1155 scsi_scan_host(pm8001_ha->shost); 1156 return 0; 1157 1158 err_out_shost: 1159 scsi_remove_host(pm8001_ha->shost); 1160 err_out_ha_free: 1161 pm8001_free(pm8001_ha); 1162 err_out_free: 1163 kfree(sha); 1164 err_out_free_host: 1165 scsi_host_put(shost); 1166 err_out_regions: 1167 pci_release_regions(pdev); 1168 err_out_disable: 1169 pci_disable_device(pdev); 1170 err_out_enable: 1171 return rc; 1172 } 1173 1174 /* 1175 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1176 * @pm8001_ha: our hba card information. 1177 * @shost: scsi host which has been allocated outside. 1178 */ 1179 static int 1180 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost, 1181 struct pci_dev *pdev) 1182 { 1183 int i = 0; 1184 u32 max_out_io, ccb_count; 1185 u32 can_queue; 1186 1187 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1188 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1189 1190 /* Update to the scsi host*/ 1191 can_queue = ccb_count - PM8001_RESERVE_SLOT; 1192 shost->can_queue = can_queue; 1193 1194 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL); 1195 if (!pm8001_ha->tags) 1196 goto err_out; 1197 1198 /* Memory region for ccb_info*/ 1199 pm8001_ha->ccb_info = 1200 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1201 if (!pm8001_ha->ccb_info) { 1202 pm8001_dbg(pm8001_ha, FAIL, 1203 "Unable to allocate memory for ccb\n"); 1204 goto err_out_noccb; 1205 } 1206 for (i = 0; i < ccb_count; i++) { 1207 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev, 1208 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1209 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1210 GFP_KERNEL); 1211 if (!pm8001_ha->ccb_info[i].buf_prd) { 1212 pm8001_dbg(pm8001_ha, FAIL, 1213 "ccb prd memory allocation error\n"); 1214 goto err_out; 1215 } 1216 pm8001_ha->ccb_info[i].task = NULL; 1217 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 1218 pm8001_ha->ccb_info[i].device = NULL; 1219 ++pm8001_ha->tags_num; 1220 } 1221 return 0; 1222 1223 err_out_noccb: 1224 kfree(pm8001_ha->devices); 1225 err_out: 1226 return -ENOMEM; 1227 } 1228 1229 static void pm8001_pci_remove(struct pci_dev *pdev) 1230 { 1231 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1232 struct pm8001_hba_info *pm8001_ha; 1233 int i, j; 1234 pm8001_ha = sha->lldd_ha; 1235 sas_unregister_ha(sha); 1236 sas_remove_host(pm8001_ha->shost); 1237 list_del(&pm8001_ha->list); 1238 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1239 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1240 1241 #ifdef PM8001_USE_MSIX 1242 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1243 synchronize_irq(pci_irq_vector(pdev, i)); 1244 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1245 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1246 pci_free_irq_vectors(pdev); 1247 #else 1248 free_irq(pm8001_ha->irq, sha); 1249 #endif 1250 #ifdef PM8001_USE_TASKLET 1251 /* For non-msix and msix interrupts */ 1252 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1253 (pm8001_ha->chip_id == chip_8001)) 1254 tasklet_kill(&pm8001_ha->tasklet[0]); 1255 else 1256 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1257 tasklet_kill(&pm8001_ha->tasklet[j]); 1258 #endif 1259 scsi_host_put(pm8001_ha->shost); 1260 pm8001_free(pm8001_ha); 1261 kfree(sha->sas_phy); 1262 kfree(sha->sas_port); 1263 kfree(sha); 1264 pci_release_regions(pdev); 1265 pci_disable_device(pdev); 1266 } 1267 1268 /** 1269 * pm8001_pci_suspend - power management suspend main entry point 1270 * @dev: Device struct 1271 * 1272 * Returns 0 success, anything else error. 1273 */ 1274 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1275 { 1276 struct pci_dev *pdev = to_pci_dev(dev); 1277 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1278 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1279 int i, j; 1280 sas_suspend_ha(sha); 1281 flush_workqueue(pm8001_wq); 1282 scsi_block_requests(pm8001_ha->shost); 1283 if (!pdev->pm_cap) { 1284 dev_err(dev, " PCI PM not supported\n"); 1285 return -ENODEV; 1286 } 1287 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1288 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1289 #ifdef PM8001_USE_MSIX 1290 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1291 synchronize_irq(pci_irq_vector(pdev, i)); 1292 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1293 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1294 pci_free_irq_vectors(pdev); 1295 #else 1296 free_irq(pm8001_ha->irq, sha); 1297 #endif 1298 #ifdef PM8001_USE_TASKLET 1299 /* For non-msix and msix interrupts */ 1300 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1301 (pm8001_ha->chip_id == chip_8001)) 1302 tasklet_kill(&pm8001_ha->tasklet[0]); 1303 else 1304 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1305 tasklet_kill(&pm8001_ha->tasklet[j]); 1306 #endif 1307 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1308 "suspended state\n", pdev, 1309 pm8001_ha->name); 1310 return 0; 1311 } 1312 1313 /** 1314 * pm8001_pci_resume - power management resume main entry point 1315 * @dev: Device struct 1316 * 1317 * Returns 0 success, anything else error. 1318 */ 1319 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1320 { 1321 struct pci_dev *pdev = to_pci_dev(dev); 1322 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1323 struct pm8001_hba_info *pm8001_ha; 1324 int rc; 1325 u8 i = 0, j; 1326 u32 device_state; 1327 DECLARE_COMPLETION_ONSTACK(completion); 1328 pm8001_ha = sha->lldd_ha; 1329 device_state = pdev->current_state; 1330 1331 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1332 pdev, pm8001_ha->name, device_state); 1333 1334 rc = pci_go_44(pdev); 1335 if (rc) 1336 goto err_out_disable; 1337 sas_prep_resume_ha(sha); 1338 /* chip soft rst only for spc */ 1339 if (pm8001_ha->chip_id == chip_8001) { 1340 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1341 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1342 } 1343 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1344 if (rc) 1345 goto err_out_disable; 1346 1347 /* disable all the interrupt bits */ 1348 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1349 1350 rc = pm8001_request_irq(pm8001_ha); 1351 if (rc) 1352 goto err_out_disable; 1353 #ifdef PM8001_USE_TASKLET 1354 /* Tasklet for non msi-x interrupt handler */ 1355 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1356 (pm8001_ha->chip_id == chip_8001)) 1357 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1358 (unsigned long)&(pm8001_ha->irq_vector[0])); 1359 else 1360 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1361 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1362 (unsigned long)&(pm8001_ha->irq_vector[j])); 1363 #endif 1364 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1365 if (pm8001_ha->chip_id != chip_8001) { 1366 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1367 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1368 } 1369 1370 /* Chip documentation for the 8070 and 8072 SPCv */ 1371 /* states that a 500ms minimum delay is required */ 1372 /* before issuing commands. Otherwise, the firmware */ 1373 /* will enter an unrecoverable state. */ 1374 1375 if (pm8001_ha->chip_id == chip_8070 || 1376 pm8001_ha->chip_id == chip_8072) { 1377 mdelay(500); 1378 } 1379 1380 /* Spin up the PHYs */ 1381 1382 pm8001_ha->flags = PM8001F_RUN_TIME; 1383 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1384 pm8001_ha->phy[i].enable_completion = &completion; 1385 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1386 wait_for_completion(&completion); 1387 } 1388 sas_resume_ha(sha); 1389 return 0; 1390 1391 err_out_disable: 1392 scsi_remove_host(pm8001_ha->shost); 1393 1394 return rc; 1395 } 1396 1397 /* update of pci device, vendor id and driver data with 1398 * unique value for each of the controller 1399 */ 1400 static struct pci_device_id pm8001_pci_table[] = { 1401 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1402 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1403 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1404 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1405 /* Support for SPC/SPCv/SPCve controllers */ 1406 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1407 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1408 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1409 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1410 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1411 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1412 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1413 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1414 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1415 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1416 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1417 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1418 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1419 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1420 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1421 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1422 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1423 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1424 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1425 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1426 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1427 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1428 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1429 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1430 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1431 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1432 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1433 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1434 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1435 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1436 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1438 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1440 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1442 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1444 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1445 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1446 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1447 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1448 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1449 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1450 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1451 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1452 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1453 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1454 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1455 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1456 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1458 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1459 { PCI_VENDOR_ID_ATTO, 0x8070, 1460 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1461 { PCI_VENDOR_ID_ATTO, 0x8070, 1462 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1463 { PCI_VENDOR_ID_ATTO, 0x8072, 1464 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1465 { PCI_VENDOR_ID_ATTO, 0x8072, 1466 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1467 { PCI_VENDOR_ID_ATTO, 0x8070, 1468 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1469 { PCI_VENDOR_ID_ATTO, 0x8072, 1470 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1471 { PCI_VENDOR_ID_ATTO, 0x8072, 1472 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1473 {} /* terminate list */ 1474 }; 1475 1476 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1477 pm8001_pci_suspend, 1478 pm8001_pci_resume); 1479 1480 static struct pci_driver pm8001_pci_driver = { 1481 .name = DRV_NAME, 1482 .id_table = pm8001_pci_table, 1483 .probe = pm8001_pci_probe, 1484 .remove = pm8001_pci_remove, 1485 .driver.pm = &pm8001_pci_pm_ops, 1486 }; 1487 1488 /** 1489 * pm8001_init - initialize scsi transport template 1490 */ 1491 static int __init pm8001_init(void) 1492 { 1493 int rc = -ENOMEM; 1494 1495 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1496 if (!pm8001_wq) 1497 goto err; 1498 1499 pm8001_id = 0; 1500 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1501 if (!pm8001_stt) 1502 goto err_wq; 1503 rc = pci_register_driver(&pm8001_pci_driver); 1504 if (rc) 1505 goto err_tp; 1506 return 0; 1507 1508 err_tp: 1509 sas_release_transport(pm8001_stt); 1510 err_wq: 1511 destroy_workqueue(pm8001_wq); 1512 err: 1513 return rc; 1514 } 1515 1516 static void __exit pm8001_exit(void) 1517 { 1518 pci_unregister_driver(&pm8001_pci_driver); 1519 sas_release_transport(pm8001_stt); 1520 destroy_workqueue(pm8001_wq); 1521 } 1522 1523 module_init(pm8001_init); 1524 module_exit(pm8001_exit); 1525 1526 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1527 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1528 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1529 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1530 MODULE_DESCRIPTION( 1531 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1532 "SAS/SATA controller driver"); 1533 MODULE_VERSION(DRV_VERSION); 1534 MODULE_LICENSE("GPL"); 1535 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1536 1537