1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 54 pm8001_mr32(address, 0x00); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 56 pm8001_mr32(address, 0x04); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 58 pm8001_mr32(address, 0x08); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 60 pm8001_mr32(address, 0x0C); 61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 62 pm8001_mr32(address, 0x10); 63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 64 pm8001_mr32(address, 0x14); 65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 66 pm8001_mr32(address, 0x18); 67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 68 pm8001_mr32(address, MAIN_IBQ_OFFSET); 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 70 pm8001_mr32(address, MAIN_OBQ_OFFSET); 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 73 74 /* read analog Setting offset from the configuration table */ 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 77 78 /* read Error Dump Offset and Length */ 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 87 } 88 89 /** 90 * read_general_status_table - read the general status table and save it. 91 * @pm8001_ha: our hba card information 92 */ 93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 94 { 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 97 pm8001_mr32(address, 0x00); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 99 pm8001_mr32(address, 0x04); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 101 pm8001_mr32(address, 0x08); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 103 pm8001_mr32(address, 0x0C); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 105 pm8001_mr32(address, 0x10); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 107 pm8001_mr32(address, 0x14); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 109 pm8001_mr32(address, 0x18); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 111 pm8001_mr32(address, 0x1C); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 113 pm8001_mr32(address, 0x20); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 115 pm8001_mr32(address, 0x24); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 117 pm8001_mr32(address, 0x28); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 119 pm8001_mr32(address, 0x2C); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 121 pm8001_mr32(address, 0x30); 122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 123 pm8001_mr32(address, 0x34); 124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 125 pm8001_mr32(address, 0x38); 126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 127 pm8001_mr32(address, 0x3C); 128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 129 pm8001_mr32(address, 0x40); 130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 131 pm8001_mr32(address, 0x44); 132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 133 pm8001_mr32(address, 0x48); 134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 135 pm8001_mr32(address, 0x4C); 136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 137 pm8001_mr32(address, 0x50); 138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 139 pm8001_mr32(address, 0x54); 140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 141 pm8001_mr32(address, 0x58); 142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 143 pm8001_mr32(address, 0x5C); 144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 145 pm8001_mr32(address, 0x60); 146 } 147 148 /** 149 * read_inbnd_queue_table - read the inbound queue table and save it. 150 * @pm8001_ha: our hba card information 151 */ 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 153 { 154 int i; 155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 157 u32 offset = i * 0x20; 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 160 pm8001_ha->inbnd_q_tbl[i].pi_offset = 161 pm8001_mr32(address, (offset + 0x18)); 162 } 163 } 164 165 /** 166 * read_outbnd_queue_table - read the outbound queue table and save it. 167 * @pm8001_ha: our hba card information 168 */ 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 170 { 171 int i; 172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 174 u32 offset = i * 0x24; 175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 177 pm8001_ha->outbnd_q_tbl[i].ci_offset = 178 pm8001_mr32(address, (offset + 0x18)); 179 } 180 } 181 182 /** 183 * init_default_table_values - init the default table. 184 * @pm8001_ha: our hba card information 185 */ 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 187 { 188 int i; 189 u32 offsetib, offsetob; 190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 192 u32 ib_offset = pm8001_ha->ib_offset; 193 u32 ob_offset = pm8001_ha->ob_offset; 194 u32 ci_offset = pm8001_ha->ci_offset; 195 u32 pi_offset = pm8001_ha->pi_offset; 196 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 203 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 205 0; 206 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 210 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 212 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 214 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 215 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 216 PM8001_EVENT_LOG_SIZE; 217 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 219 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 221 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 222 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 223 PM8001_EVENT_LOG_SIZE; 224 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 225 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 226 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 227 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 228 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 229 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 230 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 231 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 232 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 233 pm8001_ha->inbnd_q_tbl[i].base_virt = 234 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 235 pm8001_ha->inbnd_q_tbl[i].total_length = 236 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 237 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 238 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 239 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 240 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 241 pm8001_ha->inbnd_q_tbl[i].ci_virt = 242 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 243 offsetib = i * 0x20; 244 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 245 get_pci_bar_index(pm8001_mr32(addressib, 246 (offsetib + 0x14))); 247 pm8001_ha->inbnd_q_tbl[i].pi_offset = 248 pm8001_mr32(addressib, (offsetib + 0x18)); 249 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 250 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 251 } 252 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 253 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 254 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 255 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 256 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 257 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 259 pm8001_ha->outbnd_q_tbl[i].base_virt = 260 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 261 pm8001_ha->outbnd_q_tbl[i].total_length = 262 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 263 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 264 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 265 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 267 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 268 0 | (10 << 16) | (i << 24); 269 pm8001_ha->outbnd_q_tbl[i].pi_virt = 270 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 271 offsetob = i * 0x24; 272 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 273 get_pci_bar_index(pm8001_mr32(addressob, 274 offsetob + 0x14)); 275 pm8001_ha->outbnd_q_tbl[i].ci_offset = 276 pm8001_mr32(addressob, (offsetob + 0x18)); 277 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 278 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 279 } 280 } 281 282 /** 283 * update_main_config_table - update the main default table to the HBA. 284 * @pm8001_ha: our hba card information 285 */ 286 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 287 { 288 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 289 pm8001_mw32(address, 0x24, 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 291 pm8001_mw32(address, 0x28, 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 293 pm8001_mw32(address, 0x2C, 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 295 pm8001_mw32(address, 0x30, 296 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 297 pm8001_mw32(address, 0x34, 298 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 299 pm8001_mw32(address, 0x38, 300 pm8001_ha->main_cfg_tbl.pm8001_tbl. 301 outbound_tgt_ITNexus_event_pid0_3); 302 pm8001_mw32(address, 0x3C, 303 pm8001_ha->main_cfg_tbl.pm8001_tbl. 304 outbound_tgt_ITNexus_event_pid4_7); 305 pm8001_mw32(address, 0x40, 306 pm8001_ha->main_cfg_tbl.pm8001_tbl. 307 outbound_tgt_ssp_event_pid0_3); 308 pm8001_mw32(address, 0x44, 309 pm8001_ha->main_cfg_tbl.pm8001_tbl. 310 outbound_tgt_ssp_event_pid4_7); 311 pm8001_mw32(address, 0x48, 312 pm8001_ha->main_cfg_tbl.pm8001_tbl. 313 outbound_tgt_smp_event_pid0_3); 314 pm8001_mw32(address, 0x4C, 315 pm8001_ha->main_cfg_tbl.pm8001_tbl. 316 outbound_tgt_smp_event_pid4_7); 317 pm8001_mw32(address, 0x50, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 319 pm8001_mw32(address, 0x54, 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 321 pm8001_mw32(address, 0x58, 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 323 pm8001_mw32(address, 0x5C, 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 325 pm8001_mw32(address, 0x60, 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 327 pm8001_mw32(address, 0x64, 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 329 pm8001_mw32(address, 0x68, 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 331 pm8001_mw32(address, 0x6C, 332 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 333 pm8001_mw32(address, 0x70, 334 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 335 } 336 337 /** 338 * update_inbnd_queue_table - update the inbound queue table to the HBA. 339 * @pm8001_ha: our hba card information 340 * @number: entry in the queue 341 */ 342 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 343 int number) 344 { 345 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 346 u16 offset = number * 0x20; 347 pm8001_mw32(address, offset + 0x00, 348 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 349 pm8001_mw32(address, offset + 0x04, 350 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 351 pm8001_mw32(address, offset + 0x08, 352 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 353 pm8001_mw32(address, offset + 0x0C, 354 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 355 pm8001_mw32(address, offset + 0x10, 356 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 357 } 358 359 /** 360 * update_outbnd_queue_table - update the outbound queue table to the HBA. 361 * @pm8001_ha: our hba card information 362 * @number: entry in the queue 363 */ 364 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 365 int number) 366 { 367 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 368 u16 offset = number * 0x24; 369 pm8001_mw32(address, offset + 0x00, 370 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 371 pm8001_mw32(address, offset + 0x04, 372 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 373 pm8001_mw32(address, offset + 0x08, 374 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 375 pm8001_mw32(address, offset + 0x0C, 376 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 377 pm8001_mw32(address, offset + 0x10, 378 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 379 pm8001_mw32(address, offset + 0x1C, 380 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 381 } 382 383 /** 384 * pm8001_bar4_shift - function is called to shift BAR base address 385 * @pm8001_ha : our hba card infomation 386 * @shiftValue : shifting value in memory bar. 387 */ 388 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 389 { 390 u32 regVal; 391 unsigned long start; 392 393 /* program the inbound AXI translation Lower Address */ 394 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 395 396 /* confirm the setting is written */ 397 start = jiffies + HZ; /* 1 sec */ 398 do { 399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 400 } while ((regVal != shiftValue) && time_before(jiffies, start)); 401 402 if (regVal != shiftValue) { 403 pm8001_dbg(pm8001_ha, INIT, 404 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", 405 regVal); 406 return -1; 407 } 408 return 0; 409 } 410 411 /** 412 * mpi_set_phys_g3_with_ssc 413 * @pm8001_ha: our hba card information 414 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 415 */ 416 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 417 u32 SSCbit) 418 { 419 u32 offset, i; 420 unsigned long flags; 421 422 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 423 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 424 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 425 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 426 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 427 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 428 #define SNW3_PHY_CAPABILITIES_PARITY 31 429 430 /* 431 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 432 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 433 */ 434 spin_lock_irqsave(&pm8001_ha->lock, flags); 435 if (-1 == pm8001_bar4_shift(pm8001_ha, 436 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 437 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 438 return; 439 } 440 441 for (i = 0; i < 4; i++) { 442 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 443 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 444 } 445 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 446 if (-1 == pm8001_bar4_shift(pm8001_ha, 447 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 448 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 449 return; 450 } 451 for (i = 4; i < 8; i++) { 452 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 453 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 454 } 455 /************************************************************* 456 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 457 Device MABC SMOD0 Controls 458 Address: (via MEMBASE-III): 459 Using shifted destination address 0x0_0000: with Offset 0xD8 460 461 31:28 R/W Reserved Do not change 462 27:24 R/W SAS_SMOD_SPRDUP 0000 463 23:20 R/W SAS_SMOD_SPRDDN 0000 464 19:0 R/W Reserved Do not change 465 Upon power-up this register will read as 0x8990c016, 466 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 467 so that the written value will be 0x8090c016. 468 This will ensure only down-spreading SSC is enabled on the SPC. 469 *************************************************************/ 470 pm8001_cr32(pm8001_ha, 2, 0xd8); 471 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 472 473 /*set the shifted destination address to 0x0 to avoid error operation */ 474 pm8001_bar4_shift(pm8001_ha, 0x0); 475 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 476 return; 477 } 478 479 /** 480 * mpi_set_open_retry_interval_reg 481 * @pm8001_ha: our hba card information 482 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us. 483 */ 484 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 485 u32 interval) 486 { 487 u32 offset; 488 u32 value; 489 u32 i; 490 unsigned long flags; 491 492 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 493 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 494 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 495 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 496 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 497 498 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 499 spin_lock_irqsave(&pm8001_ha->lock, flags); 500 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 501 if (-1 == pm8001_bar4_shift(pm8001_ha, 502 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 503 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 504 return; 505 } 506 for (i = 0; i < 4; i++) { 507 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 508 pm8001_cw32(pm8001_ha, 2, offset, value); 509 } 510 511 if (-1 == pm8001_bar4_shift(pm8001_ha, 512 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 513 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 514 return; 515 } 516 for (i = 4; i < 8; i++) { 517 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 518 pm8001_cw32(pm8001_ha, 2, offset, value); 519 } 520 /*set the shifted destination address to 0x0 to avoid error operation */ 521 pm8001_bar4_shift(pm8001_ha, 0x0); 522 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 523 return; 524 } 525 526 /** 527 * mpi_init_check - check firmware initialization status. 528 * @pm8001_ha: our hba card information 529 */ 530 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 531 { 532 u32 max_wait_count; 533 u32 value; 534 u32 gst_len_mpistate; 535 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 536 table is updated */ 537 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 538 /* wait until Inbound DoorBell Clear Register toggled */ 539 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 540 do { 541 udelay(1); 542 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 543 value &= SPC_MSGU_CFG_TABLE_UPDATE; 544 } while ((value != 0) && (--max_wait_count)); 545 546 if (!max_wait_count) 547 return -1; 548 /* check the MPI-State for initialization */ 549 gst_len_mpistate = 550 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 551 GST_GSTLEN_MPIS_OFFSET); 552 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 553 return -1; 554 /* check MPI Initialization error */ 555 gst_len_mpistate = gst_len_mpistate >> 16; 556 if (0x0000 != gst_len_mpistate) 557 return -1; 558 return 0; 559 } 560 561 /** 562 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 563 * @pm8001_ha: our hba card information 564 */ 565 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 566 { 567 u32 value, value1; 568 u32 max_wait_count; 569 /* check error state */ 570 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 571 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 572 /* check AAP error */ 573 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 574 /* error state */ 575 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 576 return -1; 577 } 578 579 /* check IOP error */ 580 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 581 /* error state */ 582 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 583 return -1; 584 } 585 586 /* bit 4-31 of scratch pad1 should be zeros if it is not 587 in error state*/ 588 if (value & SCRATCH_PAD1_STATE_MASK) { 589 /* error case */ 590 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 591 return -1; 592 } 593 594 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 595 in error state */ 596 if (value1 & SCRATCH_PAD2_STATE_MASK) { 597 /* error case */ 598 return -1; 599 } 600 601 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 602 603 /* wait until scratch pad 1 and 2 registers in ready state */ 604 do { 605 udelay(1); 606 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 607 & SCRATCH_PAD1_RDY; 608 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 609 & SCRATCH_PAD2_RDY; 610 if ((--max_wait_count) == 0) 611 return -1; 612 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 613 return 0; 614 } 615 616 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 617 { 618 void __iomem *base_addr; 619 u32 value; 620 u32 offset; 621 u32 pcibar; 622 u32 pcilogic; 623 624 value = pm8001_cr32(pm8001_ha, 0, 0x44); 625 offset = value & 0x03FFFFFF; 626 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset); 627 pcilogic = (value & 0xFC000000) >> 26; 628 pcibar = get_pci_bar_index(pcilogic); 629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 630 pm8001_ha->main_cfg_tbl_addr = base_addr = 631 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 632 pm8001_ha->general_stat_tbl_addr = 633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 634 pm8001_ha->inbnd_q_tbl_addr = 635 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 636 pm8001_ha->outbnd_q_tbl_addr = 637 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 638 } 639 640 /** 641 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 642 * @pm8001_ha: our hba card information 643 */ 644 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 645 { 646 u8 i = 0; 647 u16 deviceid; 648 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 649 /* 8081 controllers need BAR shift to access MPI space 650 * as this is shared with BIOS data */ 651 if (deviceid == 0x8081 || deviceid == 0x0042) { 652 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 653 pm8001_dbg(pm8001_ha, FAIL, 654 "Shift Bar4 to 0x%x failed\n", 655 GSM_SM_BASE); 656 return -1; 657 } 658 } 659 /* check the firmware status */ 660 if (-1 == check_fw_ready(pm8001_ha)) { 661 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 662 return -EBUSY; 663 } 664 665 /* Initialize pci space address eg: mpi offset */ 666 init_pci_device_addresses(pm8001_ha); 667 init_default_table_values(pm8001_ha); 668 read_main_config_table(pm8001_ha); 669 read_general_status_table(pm8001_ha); 670 read_inbnd_queue_table(pm8001_ha); 671 read_outbnd_queue_table(pm8001_ha); 672 /* update main config table ,inbound table and outbound table */ 673 update_main_config_table(pm8001_ha); 674 for (i = 0; i < PM8001_MAX_INB_NUM; i++) 675 update_inbnd_queue_table(pm8001_ha, i); 676 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) 677 update_outbnd_queue_table(pm8001_ha, i); 678 /* 8081 controller donot require these operations */ 679 if (deviceid != 0x8081 && deviceid != 0x0042) { 680 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 681 /* 7->130ms, 34->500ms, 119->1.5s */ 682 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 683 } 684 /* notify firmware update finished and check initialization status */ 685 if (0 == mpi_init_check(pm8001_ha)) { 686 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 687 } else 688 return -EBUSY; 689 /*This register is a 16-bit timer with a resolution of 1us. This is the 690 timer used for interrupt delay/coalescing in the PCIe Application Layer. 691 Zero is not a valid value. A value of 1 in the register will cause the 692 interrupts to be normal. A value greater than 1 will cause coalescing 693 delays.*/ 694 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 695 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 696 return 0; 697 } 698 699 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 700 { 701 u32 max_wait_count; 702 u32 value; 703 u32 gst_len_mpistate; 704 u16 deviceid; 705 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 706 if (deviceid == 0x8081 || deviceid == 0x0042) { 707 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 708 pm8001_dbg(pm8001_ha, FAIL, 709 "Shift Bar4 to 0x%x failed\n", 710 GSM_SM_BASE); 711 return -1; 712 } 713 } 714 init_pci_device_addresses(pm8001_ha); 715 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 716 table is stop */ 717 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 718 719 /* wait until Inbound DoorBell Clear Register toggled */ 720 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 721 do { 722 udelay(1); 723 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 724 value &= SPC_MSGU_CFG_TABLE_RESET; 725 } while ((value != 0) && (--max_wait_count)); 726 727 if (!max_wait_count) { 728 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n", 729 value); 730 return -1; 731 } 732 733 /* check the MPI-State for termination in progress */ 734 /* wait until Inbound DoorBell Clear Register toggled */ 735 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 736 do { 737 udelay(1); 738 gst_len_mpistate = 739 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 740 GST_GSTLEN_MPIS_OFFSET); 741 if (GST_MPI_STATE_UNINIT == 742 (gst_len_mpistate & GST_MPI_STATE_MASK)) 743 break; 744 } while (--max_wait_count); 745 if (!max_wait_count) { 746 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 747 gst_len_mpistate & GST_MPI_STATE_MASK); 748 return -1; 749 } 750 return 0; 751 } 752 753 /** 754 * soft_reset_ready_check - Function to check FW is ready for soft reset. 755 * @pm8001_ha: our hba card information 756 */ 757 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 758 { 759 u32 regVal, regVal1, regVal2; 760 if (mpi_uninit_check(pm8001_ha) != 0) { 761 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n"); 762 return -1; 763 } 764 /* read the scratch pad 2 register bit 2 */ 765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 766 & SCRATCH_PAD2_FWRDY_RST; 767 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 768 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n"); 769 } else { 770 unsigned long flags; 771 /* Trigger NMI twice via RB6 */ 772 spin_lock_irqsave(&pm8001_ha->lock, flags); 773 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 774 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 775 pm8001_dbg(pm8001_ha, FAIL, 776 "Shift Bar4 to 0x%x failed\n", 777 RB6_ACCESS_REG); 778 return -1; 779 } 780 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 781 RB6_MAGIC_NUMBER_RST); 782 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 783 /* wait for 100 ms */ 784 mdelay(100); 785 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 786 SCRATCH_PAD2_FWRDY_RST; 787 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 788 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 789 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 790 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 791 regVal1, regVal2); 792 pm8001_dbg(pm8001_ha, FAIL, 793 "SCRATCH_PAD0 value = 0x%x\n", 794 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 795 pm8001_dbg(pm8001_ha, FAIL, 796 "SCRATCH_PAD3 value = 0x%x\n", 797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 798 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 799 return -1; 800 } 801 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 802 } 803 return 0; 804 } 805 806 /** 807 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 808 * the FW register status to the originated status. 809 * @pm8001_ha: our hba card information 810 */ 811 static int 812 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 813 { 814 u32 regVal, toggleVal; 815 u32 max_wait_count; 816 u32 regVal1, regVal2, regVal3; 817 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 818 unsigned long flags; 819 820 /* step1: Check FW is ready for soft reset */ 821 if (soft_reset_ready_check(pm8001_ha) != 0) { 822 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n"); 823 return -1; 824 } 825 826 /* step 2: clear NMI status register on AAP1 and IOP, write the same 827 value to clear */ 828 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 829 spin_lock_irqsave(&pm8001_ha->lock, flags); 830 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 831 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 832 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 833 MBIC_AAP1_ADDR_BASE); 834 return -1; 835 } 836 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 837 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", 838 regVal); 839 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 840 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 841 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 842 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 843 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 844 MBIC_IOP_ADDR_BASE); 845 return -1; 846 } 847 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 848 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", 849 regVal); 850 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 851 852 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 853 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n", 854 regVal); 855 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 856 857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 858 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n", 859 regVal); 860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 861 862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 863 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n", 864 regVal); 865 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 866 867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 868 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal); 869 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 870 871 /* read the scratch pad 1 register bit 2 */ 872 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 873 & SCRATCH_PAD1_RST; 874 toggleVal = regVal ^ SCRATCH_PAD1_RST; 875 876 /* set signature in host scratch pad0 register to tell SPC that the 877 host performs the soft reset */ 878 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 879 880 /* read required registers for confirmming */ 881 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 882 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 883 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 884 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 885 GSM_ADDR_BASE); 886 return -1; 887 } 888 pm8001_dbg(pm8001_ha, INIT, 889 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n", 890 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 891 892 /* step 3: host read GSM Configuration and Reset register */ 893 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 894 /* Put those bits to low */ 895 /* GSM XCBI offset = 0x70 0000 896 0x00 Bit 13 COM_SLV_SW_RSTB 1 897 0x00 Bit 12 QSSP_SW_RSTB 1 898 0x00 Bit 11 RAAE_SW_RSTB 1 899 0x00 Bit 9 RB_1_SW_RSTB 1 900 0x00 Bit 8 SM_SW_RSTB 1 901 */ 902 regVal &= ~(0x00003b00); 903 /* host write GSM Configuration and Reset register */ 904 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 905 pm8001_dbg(pm8001_ha, INIT, 906 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", 907 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 908 909 /* step 4: */ 910 /* disable GSM - Read Address Parity Check */ 911 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 912 pm8001_dbg(pm8001_ha, INIT, 913 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 914 regVal1); 915 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 916 pm8001_dbg(pm8001_ha, INIT, 917 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 918 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 919 920 /* disable GSM - Write Address Parity Check */ 921 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 922 pm8001_dbg(pm8001_ha, INIT, 923 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", 924 regVal2); 925 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 926 pm8001_dbg(pm8001_ha, INIT, 927 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 928 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 929 930 /* disable GSM - Write Data Parity Check */ 931 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 932 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", 933 regVal3); 934 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 935 pm8001_dbg(pm8001_ha, INIT, 936 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n", 937 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 938 939 /* step 5: delay 10 usec */ 940 udelay(10); 941 /* step 5-b: set GPIO-0 output control to tristate anyway */ 942 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 943 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 944 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n", 945 GPIO_ADDR_BASE); 946 return -1; 947 } 948 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 949 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n", 950 regVal); 951 /* set GPIO-0 output control to tri-state */ 952 regVal &= 0xFFFFFFFC; 953 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 954 955 /* Step 6: Reset the IOP and AAP1 */ 956 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 957 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 958 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 959 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 960 SPC_TOP_LEVEL_ADDR_BASE); 961 return -1; 962 } 963 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 964 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n", 965 regVal); 966 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 967 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 968 969 /* step 7: Reset the BDMA/OSSP */ 970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 971 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n", 972 regVal); 973 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 975 976 /* step 8: delay 10 usec */ 977 udelay(10); 978 979 /* step 9: bring the BDMA and OSSP out of reset */ 980 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 981 pm8001_dbg(pm8001_ha, INIT, 982 "Top Register before bringing up BDMA/OSSP:= 0x%x\n", 983 regVal); 984 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 985 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 986 987 /* step 10: delay 10 usec */ 988 udelay(10); 989 990 /* step 11: reads and sets the GSM Configuration and Reset Register */ 991 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 992 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 993 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 994 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 995 GSM_ADDR_BASE); 996 return -1; 997 } 998 pm8001_dbg(pm8001_ha, INIT, 999 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n", 1000 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1001 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1002 /* Put those bits to high */ 1003 /* GSM XCBI offset = 0x70 0000 1004 0x00 Bit 13 COM_SLV_SW_RSTB 1 1005 0x00 Bit 12 QSSP_SW_RSTB 1 1006 0x00 Bit 11 RAAE_SW_RSTB 1 1007 0x00 Bit 9 RB_1_SW_RSTB 1 1008 0x00 Bit 8 SM_SW_RSTB 1 1009 */ 1010 regVal |= (GSM_CONFIG_RESET_VALUE); 1011 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1012 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", 1013 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1014 1015 /* step 12: Restore GSM - Read Address Parity Check */ 1016 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1017 /* just for debugging */ 1018 pm8001_dbg(pm8001_ha, INIT, 1019 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 1020 regVal); 1021 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1022 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 1023 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 1024 /* Restore GSM - Write Address Parity Check */ 1025 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1026 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1027 pm8001_dbg(pm8001_ha, INIT, 1028 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 1029 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 1030 /* Restore GSM - Write Data Parity Check */ 1031 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1032 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1033 pm8001_dbg(pm8001_ha, INIT, 1034 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", 1035 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 1036 1037 /* step 13: bring the IOP and AAP1 out of reset */ 1038 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1039 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1040 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1041 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 1042 SPC_TOP_LEVEL_ADDR_BASE); 1043 return -1; 1044 } 1045 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1046 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1047 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1048 1049 /* step 14: delay 10 usec - Normal Mode */ 1050 udelay(10); 1051 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1052 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1053 /* step 15 (Normal Mode): wait until scratch pad1 register 1054 bit 2 toggled */ 1055 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1056 do { 1057 udelay(1); 1058 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1059 SCRATCH_PAD1_RST; 1060 } while ((regVal != toggleVal) && (--max_wait_count)); 1061 1062 if (!max_wait_count) { 1063 regVal = pm8001_cr32(pm8001_ha, 0, 1064 MSGU_SCRATCH_PAD_1); 1065 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n", 1066 toggleVal, regVal); 1067 pm8001_dbg(pm8001_ha, FAIL, 1068 "SCRATCH_PAD0 value = 0x%x\n", 1069 pm8001_cr32(pm8001_ha, 0, 1070 MSGU_SCRATCH_PAD_0)); 1071 pm8001_dbg(pm8001_ha, FAIL, 1072 "SCRATCH_PAD2 value = 0x%x\n", 1073 pm8001_cr32(pm8001_ha, 0, 1074 MSGU_SCRATCH_PAD_2)); 1075 pm8001_dbg(pm8001_ha, FAIL, 1076 "SCRATCH_PAD3 value = 0x%x\n", 1077 pm8001_cr32(pm8001_ha, 0, 1078 MSGU_SCRATCH_PAD_3)); 1079 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1080 return -1; 1081 } 1082 1083 /* step 16 (Normal) - Clear ODMR and ODCR */ 1084 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1085 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1086 1087 /* step 17 (Normal Mode): wait for the FW and IOP to get 1088 ready - 1 sec timeout */ 1089 /* Wait for the SPC Configuration Table to be ready */ 1090 if (check_fw_ready(pm8001_ha) == -1) { 1091 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1092 /* return error if MPI Configuration Table not ready */ 1093 pm8001_dbg(pm8001_ha, INIT, 1094 "FW not ready SCRATCH_PAD1 = 0x%x\n", 1095 regVal); 1096 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1097 /* return error if MPI Configuration Table not ready */ 1098 pm8001_dbg(pm8001_ha, INIT, 1099 "FW not ready SCRATCH_PAD2 = 0x%x\n", 1100 regVal); 1101 pm8001_dbg(pm8001_ha, INIT, 1102 "SCRATCH_PAD0 value = 0x%x\n", 1103 pm8001_cr32(pm8001_ha, 0, 1104 MSGU_SCRATCH_PAD_0)); 1105 pm8001_dbg(pm8001_ha, INIT, 1106 "SCRATCH_PAD3 value = 0x%x\n", 1107 pm8001_cr32(pm8001_ha, 0, 1108 MSGU_SCRATCH_PAD_3)); 1109 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1110 return -1; 1111 } 1112 } 1113 pm8001_bar4_shift(pm8001_ha, 0); 1114 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1115 1116 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1117 return 0; 1118 } 1119 1120 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1121 { 1122 u32 i; 1123 u32 regVal; 1124 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1125 1126 /* do SPC chip reset. */ 1127 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1128 regVal &= ~(SPC_REG_RESET_DEVICE); 1129 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1130 1131 /* delay 10 usec */ 1132 udelay(10); 1133 1134 /* bring chip reset out of reset */ 1135 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1136 regVal |= SPC_REG_RESET_DEVICE; 1137 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1138 1139 /* delay 10 usec */ 1140 udelay(10); 1141 1142 /* wait for 20 msec until the firmware gets reloaded */ 1143 i = 20; 1144 do { 1145 mdelay(1); 1146 } while ((--i) != 0); 1147 1148 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1149 } 1150 1151 /** 1152 * pm8001_chip_iounmap - which maped when initialized. 1153 * @pm8001_ha: our hba card information 1154 */ 1155 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1156 { 1157 s8 bar, logical = 0; 1158 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1159 /* 1160 ** logical BARs for SPC: 1161 ** bar 0 and 1 - logical BAR0 1162 ** bar 2 and 3 - logical BAR1 1163 ** bar4 - logical BAR2 1164 ** bar5 - logical BAR3 1165 ** Skip the appropriate assignments: 1166 */ 1167 if ((bar == 1) || (bar == 3)) 1168 continue; 1169 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1170 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1171 logical++; 1172 } 1173 } 1174 } 1175 1176 #ifndef PM8001_USE_MSIX 1177 /** 1178 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1179 * @pm8001_ha: our hba card information 1180 */ 1181 static void 1182 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1183 { 1184 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1185 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1186 } 1187 1188 /** 1189 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1190 * @pm8001_ha: our hba card information 1191 */ 1192 static void 1193 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1194 { 1195 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1196 } 1197 1198 #else 1199 1200 /** 1201 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1202 * @pm8001_ha: our hba card information 1203 * @int_vec_idx: interrupt number to enable 1204 */ 1205 static void 1206 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1207 u32 int_vec_idx) 1208 { 1209 u32 msi_index; 1210 u32 value; 1211 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1212 msi_index += MSIX_TABLE_BASE; 1213 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1214 value = (1 << int_vec_idx); 1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1216 1217 } 1218 1219 /** 1220 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1221 * @pm8001_ha: our hba card information 1222 * @int_vec_idx: interrupt number to disable 1223 */ 1224 static void 1225 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1226 u32 int_vec_idx) 1227 { 1228 u32 msi_index; 1229 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1230 msi_index += MSIX_TABLE_BASE; 1231 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1232 } 1233 #endif 1234 1235 /** 1236 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1237 * @pm8001_ha: our hba card information 1238 * @vec: unused 1239 */ 1240 static void 1241 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1242 { 1243 #ifdef PM8001_USE_MSIX 1244 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1245 #else 1246 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1247 #endif 1248 } 1249 1250 /** 1251 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1252 * @pm8001_ha: our hba card information 1253 * @vec: unused 1254 */ 1255 static void 1256 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1257 { 1258 #ifdef PM8001_USE_MSIX 1259 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1260 #else 1261 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1262 #endif 1263 } 1264 1265 /** 1266 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1267 * inbound queue. 1268 * @circularQ: the inbound queue we want to transfer to HBA. 1269 * @messageSize: the message size of this transfer, normally it is 64 bytes 1270 * @messagePtr: the pointer to message. 1271 */ 1272 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1273 u16 messageSize, void **messagePtr) 1274 { 1275 u32 offset, consumer_index; 1276 struct mpi_msg_hdr *msgHeader; 1277 u8 bcCount = 1; /* only support single buffer */ 1278 1279 /* Checks is the requested message size can be allocated in this queue*/ 1280 if (messageSize > IOMB_SIZE_SPCV) { 1281 *messagePtr = NULL; 1282 return -1; 1283 } 1284 1285 /* Stores the new consumer index */ 1286 consumer_index = pm8001_read_32(circularQ->ci_virt); 1287 circularQ->consumer_index = cpu_to_le32(consumer_index); 1288 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1289 le32_to_cpu(circularQ->consumer_index)) { 1290 *messagePtr = NULL; 1291 return -1; 1292 } 1293 /* get memory IOMB buffer address */ 1294 offset = circularQ->producer_idx * messageSize; 1295 /* increment to next bcCount element */ 1296 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1297 % PM8001_MPI_QUEUE; 1298 /* Adds that distance to the base of the region virtual address plus 1299 the message header size*/ 1300 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1301 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1302 return 0; 1303 } 1304 1305 /** 1306 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1307 * FW to tell the fw to get this message from IOMB. 1308 * @pm8001_ha: our hba card information 1309 * @circularQ: the inbound queue we want to transfer to HBA. 1310 * @opCode: the operation code represents commands which LLDD and fw recognized. 1311 * @payload: the command payload of each operation command. 1312 * @nb: size in bytes of the command payload 1313 * @responseQueue: queue to interrupt on w/ command response (if any) 1314 */ 1315 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1316 struct inbound_queue_table *circularQ, 1317 u32 opCode, void *payload, size_t nb, 1318 u32 responseQueue) 1319 { 1320 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1321 void *pMessage; 1322 unsigned long flags; 1323 int q_index = circularQ - pm8001_ha->inbnd_q_tbl; 1324 int rv = -1; 1325 1326 WARN_ON(q_index >= PM8001_MAX_INB_NUM); 1327 spin_lock_irqsave(&circularQ->iq_lock, flags); 1328 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1329 &pMessage); 1330 if (rv < 0) { 1331 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n"); 1332 rv = -ENOMEM; 1333 goto done; 1334 } 1335 1336 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) 1337 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); 1338 memcpy(pMessage, payload, nb); 1339 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) 1340 memset(pMessage + nb, 0, pm8001_ha->iomb_size - 1341 (nb + sizeof(struct mpi_msg_hdr))); 1342 1343 /*Build the header*/ 1344 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1345 | ((responseQueue & 0x3F) << 16) 1346 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1347 1348 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1349 /*Update the PI to the firmware*/ 1350 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1351 circularQ->pi_offset, circularQ->producer_idx); 1352 pm8001_dbg(pm8001_ha, DEVIO, 1353 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1354 responseQueue, opCode, circularQ->producer_idx, 1355 circularQ->consumer_index); 1356 done: 1357 spin_unlock_irqrestore(&circularQ->iq_lock, flags); 1358 return rv; 1359 } 1360 1361 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1362 struct outbound_queue_table *circularQ, u8 bc) 1363 { 1364 u32 producer_index; 1365 struct mpi_msg_hdr *msgHeader; 1366 struct mpi_msg_hdr *pOutBoundMsgHeader; 1367 1368 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1369 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1370 circularQ->consumer_idx * pm8001_ha->iomb_size); 1371 if (pOutBoundMsgHeader != msgHeader) { 1372 pm8001_dbg(pm8001_ha, FAIL, 1373 "consumer_idx = %d msgHeader = %p\n", 1374 circularQ->consumer_idx, msgHeader); 1375 1376 /* Update the producer index from SPC */ 1377 producer_index = pm8001_read_32(circularQ->pi_virt); 1378 circularQ->producer_index = cpu_to_le32(producer_index); 1379 pm8001_dbg(pm8001_ha, FAIL, 1380 "consumer_idx = %d producer_index = %dmsgHeader = %p\n", 1381 circularQ->consumer_idx, 1382 circularQ->producer_index, msgHeader); 1383 return 0; 1384 } 1385 /* free the circular queue buffer elements associated with the message*/ 1386 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1387 % PM8001_MPI_QUEUE; 1388 /* update the CI of outbound queue */ 1389 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1390 circularQ->consumer_idx); 1391 /* Update the producer index from SPC*/ 1392 producer_index = pm8001_read_32(circularQ->pi_virt); 1393 circularQ->producer_index = cpu_to_le32(producer_index); 1394 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n", 1395 circularQ->consumer_idx, circularQ->producer_index); 1396 return 0; 1397 } 1398 1399 /** 1400 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1401 * message table. 1402 * @pm8001_ha: our hba card information 1403 * @circularQ: the outbound queue table. 1404 * @messagePtr1: the message contents of this outbound message. 1405 * @pBC: the message size. 1406 */ 1407 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1408 struct outbound_queue_table *circularQ, 1409 void **messagePtr1, u8 *pBC) 1410 { 1411 struct mpi_msg_hdr *msgHeader; 1412 __le32 msgHeader_tmp; 1413 u32 header_tmp; 1414 do { 1415 /* If there are not-yet-delivered messages ... */ 1416 if (le32_to_cpu(circularQ->producer_index) 1417 != circularQ->consumer_idx) { 1418 /*Get the pointer to the circular queue buffer element*/ 1419 msgHeader = (struct mpi_msg_hdr *) 1420 (circularQ->base_virt + 1421 circularQ->consumer_idx * pm8001_ha->iomb_size); 1422 /* read header */ 1423 header_tmp = pm8001_read_32(msgHeader); 1424 msgHeader_tmp = cpu_to_le32(header_tmp); 1425 pm8001_dbg(pm8001_ha, DEVIO, 1426 "outbound opcode msgheader:%x ci=%d pi=%d\n", 1427 msgHeader_tmp, circularQ->consumer_idx, 1428 circularQ->producer_index); 1429 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1430 if (OPC_OUB_SKIP_ENTRY != 1431 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1432 *messagePtr1 = 1433 ((u8 *)msgHeader) + 1434 sizeof(struct mpi_msg_hdr); 1435 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1436 >> 24) & 0x1f); 1437 pm8001_dbg(pm8001_ha, IO, 1438 ": CI=%d PI=%d msgHeader=%x\n", 1439 circularQ->consumer_idx, 1440 circularQ->producer_index, 1441 msgHeader_tmp); 1442 return MPI_IO_STATUS_SUCCESS; 1443 } else { 1444 circularQ->consumer_idx = 1445 (circularQ->consumer_idx + 1446 ((le32_to_cpu(msgHeader_tmp) 1447 >> 24) & 0x1f)) 1448 % PM8001_MPI_QUEUE; 1449 msgHeader_tmp = 0; 1450 pm8001_write_32(msgHeader, 0, 0); 1451 /* update the CI of outbound queue */ 1452 pm8001_cw32(pm8001_ha, 1453 circularQ->ci_pci_bar, 1454 circularQ->ci_offset, 1455 circularQ->consumer_idx); 1456 } 1457 } else { 1458 circularQ->consumer_idx = 1459 (circularQ->consumer_idx + 1460 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1461 0x1f)) % PM8001_MPI_QUEUE; 1462 msgHeader_tmp = 0; 1463 pm8001_write_32(msgHeader, 0, 0); 1464 /* update the CI of outbound queue */ 1465 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1466 circularQ->ci_offset, 1467 circularQ->consumer_idx); 1468 return MPI_IO_STATUS_FAIL; 1469 } 1470 } else { 1471 u32 producer_index; 1472 void *pi_virt = circularQ->pi_virt; 1473 /* spurious interrupt during setup if 1474 * kexec-ing and driver doing a doorbell access 1475 * with the pre-kexec oq interrupt setup 1476 */ 1477 if (!pi_virt) 1478 break; 1479 /* Update the producer index from SPC */ 1480 producer_index = pm8001_read_32(pi_virt); 1481 circularQ->producer_index = cpu_to_le32(producer_index); 1482 } 1483 } while (le32_to_cpu(circularQ->producer_index) != 1484 circularQ->consumer_idx); 1485 /* while we don't have any more not-yet-delivered message */ 1486 /* report empty */ 1487 return MPI_IO_STATUS_BUSY; 1488 } 1489 1490 void pm8001_work_fn(struct work_struct *work) 1491 { 1492 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1493 struct pm8001_device *pm8001_dev; 1494 struct domain_device *dev; 1495 1496 /* 1497 * So far, all users of this stash an associated structure here. 1498 * If we get here, and this pointer is null, then the action 1499 * was cancelled. This nullification happens when the device 1500 * goes away. 1501 */ 1502 pm8001_dev = pw->data; /* Most stash device structure */ 1503 if ((pm8001_dev == NULL) 1504 || ((pw->handler != IO_XFER_ERROR_BREAK) 1505 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1506 kfree(pw); 1507 return; 1508 } 1509 1510 switch (pw->handler) { 1511 case IO_XFER_ERROR_BREAK: 1512 { /* This one stashes the sas_task instead */ 1513 struct sas_task *t = (struct sas_task *)pm8001_dev; 1514 u32 tag; 1515 struct pm8001_ccb_info *ccb; 1516 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1517 unsigned long flags, flags1; 1518 struct task_status_struct *ts; 1519 int i; 1520 1521 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1522 break; /* Task still on lu */ 1523 spin_lock_irqsave(&pm8001_ha->lock, flags); 1524 1525 spin_lock_irqsave(&t->task_state_lock, flags1); 1526 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1527 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1528 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1529 break; /* Task got completed by another */ 1530 } 1531 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1532 1533 /* Search for a possible ccb that matches the task */ 1534 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1535 ccb = &pm8001_ha->ccb_info[i]; 1536 tag = ccb->ccb_tag; 1537 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1538 break; 1539 } 1540 if (!ccb) { 1541 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1542 break; /* Task got freed by another */ 1543 } 1544 ts = &t->task_status; 1545 ts->resp = SAS_TASK_COMPLETE; 1546 /* Force the midlayer to retry */ 1547 ts->stat = SAS_QUEUE_FULL; 1548 pm8001_dev = ccb->device; 1549 if (pm8001_dev) 1550 atomic_dec(&pm8001_dev->running_req); 1551 spin_lock_irqsave(&t->task_state_lock, flags1); 1552 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1553 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1554 t->task_state_flags |= SAS_TASK_STATE_DONE; 1555 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1556 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1557 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 1558 t, pw->handler, ts->resp, ts->stat); 1559 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1560 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1561 } else { 1562 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1563 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1564 mb();/* in order to force CPU ordering */ 1565 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1566 t->task_done(t); 1567 } 1568 } break; 1569 case IO_XFER_OPEN_RETRY_TIMEOUT: 1570 { /* This one stashes the sas_task instead */ 1571 struct sas_task *t = (struct sas_task *)pm8001_dev; 1572 u32 tag; 1573 struct pm8001_ccb_info *ccb; 1574 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1575 unsigned long flags, flags1; 1576 int i, ret = 0; 1577 1578 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1579 1580 ret = pm8001_query_task(t); 1581 1582 if (ret == TMF_RESP_FUNC_SUCC) 1583 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n"); 1584 else if (ret == TMF_RESP_FUNC_COMPLETE) 1585 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n"); 1586 else 1587 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n"); 1588 1589 spin_lock_irqsave(&pm8001_ha->lock, flags); 1590 1591 spin_lock_irqsave(&t->task_state_lock, flags1); 1592 1593 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1594 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1595 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1596 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1597 (void)pm8001_abort_task(t); 1598 break; /* Task got completed by another */ 1599 } 1600 1601 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1602 1603 /* Search for a possible ccb that matches the task */ 1604 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1605 ccb = &pm8001_ha->ccb_info[i]; 1606 tag = ccb->ccb_tag; 1607 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1608 break; 1609 } 1610 if (!ccb) { 1611 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1612 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1613 (void)pm8001_abort_task(t); 1614 break; /* Task got freed by another */ 1615 } 1616 1617 pm8001_dev = ccb->device; 1618 dev = pm8001_dev->sas_device; 1619 1620 switch (ret) { 1621 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1622 ccb->open_retry = 1; /* Snub completion */ 1623 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1624 ret = pm8001_abort_task(t); 1625 ccb->open_retry = 0; 1626 switch (ret) { 1627 case TMF_RESP_FUNC_SUCC: 1628 case TMF_RESP_FUNC_COMPLETE: 1629 break; 1630 default: /* device misbehavior */ 1631 ret = TMF_RESP_FUNC_FAILED; 1632 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1633 pm8001_I_T_nexus_reset(dev); 1634 break; 1635 } 1636 break; 1637 1638 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1639 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1640 /* Do we need to abort the task locally? */ 1641 break; 1642 1643 default: /* device misbehavior */ 1644 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1645 ret = TMF_RESP_FUNC_FAILED; 1646 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1647 pm8001_I_T_nexus_reset(dev); 1648 } 1649 1650 if (ret == TMF_RESP_FUNC_FAILED) 1651 t = NULL; 1652 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1653 pm8001_dbg(pm8001_ha, IO, "...Complete\n"); 1654 } break; 1655 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1656 dev = pm8001_dev->sas_device; 1657 pm8001_I_T_nexus_event_handler(dev); 1658 break; 1659 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1660 dev = pm8001_dev->sas_device; 1661 pm8001_I_T_nexus_reset(dev); 1662 break; 1663 case IO_DS_IN_ERROR: 1664 dev = pm8001_dev->sas_device; 1665 pm8001_I_T_nexus_reset(dev); 1666 break; 1667 case IO_DS_NON_OPERATIONAL: 1668 dev = pm8001_dev->sas_device; 1669 pm8001_I_T_nexus_reset(dev); 1670 break; 1671 } 1672 kfree(pw); 1673 } 1674 1675 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1676 int handler) 1677 { 1678 struct pm8001_work *pw; 1679 int ret = 0; 1680 1681 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1682 if (pw) { 1683 pw->pm8001_ha = pm8001_ha; 1684 pw->data = data; 1685 pw->handler = handler; 1686 INIT_WORK(&pw->work, pm8001_work_fn); 1687 queue_work(pm8001_wq, &pw->work); 1688 } else 1689 ret = -ENOMEM; 1690 1691 return ret; 1692 } 1693 1694 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1695 struct pm8001_device *pm8001_ha_dev) 1696 { 1697 int res; 1698 u32 ccb_tag; 1699 struct pm8001_ccb_info *ccb; 1700 struct sas_task *task = NULL; 1701 struct task_abort_req task_abort; 1702 struct inbound_queue_table *circularQ; 1703 u32 opc = OPC_INB_SATA_ABORT; 1704 int ret; 1705 1706 if (!pm8001_ha_dev) { 1707 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); 1708 return; 1709 } 1710 1711 task = sas_alloc_slow_task(GFP_ATOMIC); 1712 1713 if (!task) { 1714 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1715 return; 1716 } 1717 1718 task->task_done = pm8001_task_done; 1719 1720 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1721 if (res) 1722 return; 1723 1724 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1725 ccb->device = pm8001_ha_dev; 1726 ccb->ccb_tag = ccb_tag; 1727 ccb->task = task; 1728 1729 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1730 1731 memset(&task_abort, 0, sizeof(task_abort)); 1732 task_abort.abort_all = cpu_to_le32(1); 1733 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1734 task_abort.tag = cpu_to_le32(ccb_tag); 1735 1736 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1737 sizeof(task_abort), 0); 1738 if (ret) 1739 pm8001_tag_free(pm8001_ha, ccb_tag); 1740 1741 } 1742 1743 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, 1744 struct pm8001_device *pm8001_ha_dev) 1745 { 1746 struct sata_start_req sata_cmd; 1747 int res; 1748 u32 ccb_tag; 1749 struct pm8001_ccb_info *ccb; 1750 struct sas_task *task = NULL; 1751 struct host_to_dev_fis fis; 1752 struct domain_device *dev; 1753 struct inbound_queue_table *circularQ; 1754 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1755 1756 task = sas_alloc_slow_task(GFP_ATOMIC); 1757 1758 if (!task) { 1759 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1760 return; 1761 } 1762 task->task_done = pm8001_task_done; 1763 1764 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1765 if (res) { 1766 sas_free_task(task); 1767 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); 1768 return; 1769 } 1770 1771 /* allocate domain device by ourselves as libsas 1772 * is not going to provide any 1773 */ 1774 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1775 if (!dev) { 1776 sas_free_task(task); 1777 pm8001_tag_free(pm8001_ha, ccb_tag); 1778 pm8001_dbg(pm8001_ha, FAIL, 1779 "Domain device cannot be allocated\n"); 1780 return; 1781 } 1782 task->dev = dev; 1783 task->dev->lldd_dev = pm8001_ha_dev; 1784 1785 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1786 ccb->device = pm8001_ha_dev; 1787 ccb->ccb_tag = ccb_tag; 1788 ccb->task = task; 1789 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1790 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1791 1792 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1793 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1794 1795 /* construct read log FIS */ 1796 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1797 fis.fis_type = 0x27; 1798 fis.flags = 0x80; 1799 fis.command = ATA_CMD_READ_LOG_EXT; 1800 fis.lbal = 0x10; 1801 fis.sector_count = 0x1; 1802 1803 sata_cmd.tag = cpu_to_le32(ccb_tag); 1804 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1805 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9)); 1806 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1807 1808 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1809 sizeof(sata_cmd), 0); 1810 if (res) { 1811 sas_free_task(task); 1812 pm8001_tag_free(pm8001_ha, ccb_tag); 1813 kfree(dev); 1814 } 1815 } 1816 1817 /** 1818 * mpi_ssp_completion- process the event that FW response to the SSP request. 1819 * @pm8001_ha: our hba card information 1820 * @piomb: the message contents of this outbound message. 1821 * 1822 * When FW has completed a ssp request for example a IO request, after it has 1823 * filled the SG data with the data, it will trigger this event represent 1824 * that he has finished the job,please check the coresponding buffer. 1825 * So we will tell the caller who maybe waiting the result to tell upper layer 1826 * that the task has been finished. 1827 */ 1828 static void 1829 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1830 { 1831 struct sas_task *t; 1832 struct pm8001_ccb_info *ccb; 1833 unsigned long flags; 1834 u32 status; 1835 u32 param; 1836 u32 tag; 1837 struct ssp_completion_resp *psspPayload; 1838 struct task_status_struct *ts; 1839 struct ssp_response_iu *iu; 1840 struct pm8001_device *pm8001_dev; 1841 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1842 status = le32_to_cpu(psspPayload->status); 1843 tag = le32_to_cpu(psspPayload->tag); 1844 ccb = &pm8001_ha->ccb_info[tag]; 1845 if ((status == IO_ABORTED) && ccb->open_retry) { 1846 /* Being completed by another */ 1847 ccb->open_retry = 0; 1848 return; 1849 } 1850 pm8001_dev = ccb->device; 1851 param = le32_to_cpu(psspPayload->param); 1852 1853 t = ccb->task; 1854 1855 if (status && status != IO_UNDERFLOW) 1856 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1857 if (unlikely(!t || !t->lldd_task || !t->dev)) 1858 return; 1859 ts = &t->task_status; 1860 /* Print sas address of IO failed device */ 1861 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1862 (status != IO_UNDERFLOW)) 1863 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1864 SAS_ADDR(t->dev->sas_addr)); 1865 1866 if (status) 1867 pm8001_dbg(pm8001_ha, IOERR, 1868 "status:0x%x, tag:0x%x, task:0x%p\n", 1869 status, tag, t); 1870 1871 switch (status) { 1872 case IO_SUCCESS: 1873 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n", 1874 param); 1875 if (param == 0) { 1876 ts->resp = SAS_TASK_COMPLETE; 1877 ts->stat = SAM_STAT_GOOD; 1878 } else { 1879 ts->resp = SAS_TASK_COMPLETE; 1880 ts->stat = SAS_PROTO_RESPONSE; 1881 ts->residual = param; 1882 iu = &psspPayload->ssp_resp_iu; 1883 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1884 } 1885 if (pm8001_dev) 1886 atomic_dec(&pm8001_dev->running_req); 1887 break; 1888 case IO_ABORTED: 1889 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1890 ts->resp = SAS_TASK_COMPLETE; 1891 ts->stat = SAS_ABORTED_TASK; 1892 break; 1893 case IO_UNDERFLOW: 1894 /* SSP Completion with error */ 1895 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n", 1896 param); 1897 ts->resp = SAS_TASK_COMPLETE; 1898 ts->stat = SAS_DATA_UNDERRUN; 1899 ts->residual = param; 1900 if (pm8001_dev) 1901 atomic_dec(&pm8001_dev->running_req); 1902 break; 1903 case IO_NO_DEVICE: 1904 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1905 ts->resp = SAS_TASK_UNDELIVERED; 1906 ts->stat = SAS_PHY_DOWN; 1907 break; 1908 case IO_XFER_ERROR_BREAK: 1909 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1910 ts->resp = SAS_TASK_COMPLETE; 1911 ts->stat = SAS_OPEN_REJECT; 1912 /* Force the midlayer to retry */ 1913 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1914 break; 1915 case IO_XFER_ERROR_PHY_NOT_READY: 1916 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1917 ts->resp = SAS_TASK_COMPLETE; 1918 ts->stat = SAS_OPEN_REJECT; 1919 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1920 break; 1921 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1922 pm8001_dbg(pm8001_ha, IO, 1923 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1924 ts->resp = SAS_TASK_COMPLETE; 1925 ts->stat = SAS_OPEN_REJECT; 1926 ts->open_rej_reason = SAS_OREJ_EPROTO; 1927 break; 1928 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1929 pm8001_dbg(pm8001_ha, IO, 1930 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1931 ts->resp = SAS_TASK_COMPLETE; 1932 ts->stat = SAS_OPEN_REJECT; 1933 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1934 break; 1935 case IO_OPEN_CNX_ERROR_BREAK: 1936 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1937 ts->resp = SAS_TASK_COMPLETE; 1938 ts->stat = SAS_OPEN_REJECT; 1939 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1940 break; 1941 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1942 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1943 ts->resp = SAS_TASK_COMPLETE; 1944 ts->stat = SAS_OPEN_REJECT; 1945 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1946 if (!t->uldd_task) 1947 pm8001_handle_event(pm8001_ha, 1948 pm8001_dev, 1949 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1950 break; 1951 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1952 pm8001_dbg(pm8001_ha, IO, 1953 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 1954 ts->resp = SAS_TASK_COMPLETE; 1955 ts->stat = SAS_OPEN_REJECT; 1956 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1957 break; 1958 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1959 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 1960 ts->resp = SAS_TASK_COMPLETE; 1961 ts->stat = SAS_OPEN_REJECT; 1962 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1963 break; 1964 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1965 pm8001_dbg(pm8001_ha, IO, 1966 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 1967 ts->resp = SAS_TASK_UNDELIVERED; 1968 ts->stat = SAS_OPEN_REJECT; 1969 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1970 break; 1971 case IO_XFER_ERROR_NAK_RECEIVED: 1972 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 1973 ts->resp = SAS_TASK_COMPLETE; 1974 ts->stat = SAS_OPEN_REJECT; 1975 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1976 break; 1977 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1978 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 1979 ts->resp = SAS_TASK_COMPLETE; 1980 ts->stat = SAS_NAK_R_ERR; 1981 break; 1982 case IO_XFER_ERROR_DMA: 1983 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 1984 ts->resp = SAS_TASK_COMPLETE; 1985 ts->stat = SAS_OPEN_REJECT; 1986 break; 1987 case IO_XFER_OPEN_RETRY_TIMEOUT: 1988 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1989 ts->resp = SAS_TASK_COMPLETE; 1990 ts->stat = SAS_OPEN_REJECT; 1991 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1992 break; 1993 case IO_XFER_ERROR_OFFSET_MISMATCH: 1994 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 1995 ts->resp = SAS_TASK_COMPLETE; 1996 ts->stat = SAS_OPEN_REJECT; 1997 break; 1998 case IO_PORT_IN_RESET: 1999 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2000 ts->resp = SAS_TASK_COMPLETE; 2001 ts->stat = SAS_OPEN_REJECT; 2002 break; 2003 case IO_DS_NON_OPERATIONAL: 2004 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2005 ts->resp = SAS_TASK_COMPLETE; 2006 ts->stat = SAS_OPEN_REJECT; 2007 if (!t->uldd_task) 2008 pm8001_handle_event(pm8001_ha, 2009 pm8001_dev, 2010 IO_DS_NON_OPERATIONAL); 2011 break; 2012 case IO_DS_IN_RECOVERY: 2013 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2014 ts->resp = SAS_TASK_COMPLETE; 2015 ts->stat = SAS_OPEN_REJECT; 2016 break; 2017 case IO_TM_TAG_NOT_FOUND: 2018 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2019 ts->resp = SAS_TASK_COMPLETE; 2020 ts->stat = SAS_OPEN_REJECT; 2021 break; 2022 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2023 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2024 ts->resp = SAS_TASK_COMPLETE; 2025 ts->stat = SAS_OPEN_REJECT; 2026 break; 2027 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2028 pm8001_dbg(pm8001_ha, IO, 2029 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2030 ts->resp = SAS_TASK_COMPLETE; 2031 ts->stat = SAS_OPEN_REJECT; 2032 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2033 break; 2034 default: 2035 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2036 /* not allowed case. Therefore, return failed status */ 2037 ts->resp = SAS_TASK_COMPLETE; 2038 ts->stat = SAS_OPEN_REJECT; 2039 break; 2040 } 2041 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n", 2042 psspPayload->ssp_resp_iu.status); 2043 spin_lock_irqsave(&t->task_state_lock, flags); 2044 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2045 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2046 t->task_state_flags |= SAS_TASK_STATE_DONE; 2047 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2048 spin_unlock_irqrestore(&t->task_state_lock, flags); 2049 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2050 t, status, ts->resp, ts->stat); 2051 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2052 } else { 2053 spin_unlock_irqrestore(&t->task_state_lock, flags); 2054 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2055 mb();/* in order to force CPU ordering */ 2056 t->task_done(t); 2057 } 2058 } 2059 2060 /*See the comments for mpi_ssp_completion */ 2061 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2062 { 2063 struct sas_task *t; 2064 unsigned long flags; 2065 struct task_status_struct *ts; 2066 struct pm8001_ccb_info *ccb; 2067 struct pm8001_device *pm8001_dev; 2068 struct ssp_event_resp *psspPayload = 2069 (struct ssp_event_resp *)(piomb + 4); 2070 u32 event = le32_to_cpu(psspPayload->event); 2071 u32 tag = le32_to_cpu(psspPayload->tag); 2072 u32 port_id = le32_to_cpu(psspPayload->port_id); 2073 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2074 2075 ccb = &pm8001_ha->ccb_info[tag]; 2076 t = ccb->task; 2077 pm8001_dev = ccb->device; 2078 if (event) 2079 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2080 if (unlikely(!t || !t->lldd_task || !t->dev)) 2081 return; 2082 ts = &t->task_status; 2083 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n", 2084 port_id, dev_id); 2085 switch (event) { 2086 case IO_OVERFLOW: 2087 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2088 ts->resp = SAS_TASK_COMPLETE; 2089 ts->stat = SAS_DATA_OVERRUN; 2090 ts->residual = 0; 2091 if (pm8001_dev) 2092 atomic_dec(&pm8001_dev->running_req); 2093 break; 2094 case IO_XFER_ERROR_BREAK: 2095 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2096 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2097 return; 2098 case IO_XFER_ERROR_PHY_NOT_READY: 2099 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2100 ts->resp = SAS_TASK_COMPLETE; 2101 ts->stat = SAS_OPEN_REJECT; 2102 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2103 break; 2104 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2105 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_OPEN_REJECT; 2108 ts->open_rej_reason = SAS_OREJ_EPROTO; 2109 break; 2110 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2111 pm8001_dbg(pm8001_ha, IO, 2112 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2113 ts->resp = SAS_TASK_COMPLETE; 2114 ts->stat = SAS_OPEN_REJECT; 2115 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2116 break; 2117 case IO_OPEN_CNX_ERROR_BREAK: 2118 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2119 ts->resp = SAS_TASK_COMPLETE; 2120 ts->stat = SAS_OPEN_REJECT; 2121 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2122 break; 2123 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2124 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2125 ts->resp = SAS_TASK_COMPLETE; 2126 ts->stat = SAS_OPEN_REJECT; 2127 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2128 if (!t->uldd_task) 2129 pm8001_handle_event(pm8001_ha, 2130 pm8001_dev, 2131 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2132 break; 2133 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2134 pm8001_dbg(pm8001_ha, IO, 2135 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2136 ts->resp = SAS_TASK_COMPLETE; 2137 ts->stat = SAS_OPEN_REJECT; 2138 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2139 break; 2140 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2141 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2142 ts->resp = SAS_TASK_COMPLETE; 2143 ts->stat = SAS_OPEN_REJECT; 2144 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2145 break; 2146 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2147 pm8001_dbg(pm8001_ha, IO, 2148 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2149 ts->resp = SAS_TASK_COMPLETE; 2150 ts->stat = SAS_OPEN_REJECT; 2151 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2152 break; 2153 case IO_XFER_ERROR_NAK_RECEIVED: 2154 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2155 ts->resp = SAS_TASK_COMPLETE; 2156 ts->stat = SAS_OPEN_REJECT; 2157 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2158 break; 2159 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2160 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2161 ts->resp = SAS_TASK_COMPLETE; 2162 ts->stat = SAS_NAK_R_ERR; 2163 break; 2164 case IO_XFER_OPEN_RETRY_TIMEOUT: 2165 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2166 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2167 return; 2168 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2169 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2170 ts->resp = SAS_TASK_COMPLETE; 2171 ts->stat = SAS_DATA_OVERRUN; 2172 break; 2173 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2174 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2175 ts->resp = SAS_TASK_COMPLETE; 2176 ts->stat = SAS_DATA_OVERRUN; 2177 break; 2178 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2179 pm8001_dbg(pm8001_ha, IO, 2180 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2181 ts->resp = SAS_TASK_COMPLETE; 2182 ts->stat = SAS_DATA_OVERRUN; 2183 break; 2184 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2185 pm8001_dbg(pm8001_ha, IO, 2186 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2187 ts->resp = SAS_TASK_COMPLETE; 2188 ts->stat = SAS_DATA_OVERRUN; 2189 break; 2190 case IO_XFER_ERROR_OFFSET_MISMATCH: 2191 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2192 ts->resp = SAS_TASK_COMPLETE; 2193 ts->stat = SAS_DATA_OVERRUN; 2194 break; 2195 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2196 pm8001_dbg(pm8001_ha, IO, 2197 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2198 ts->resp = SAS_TASK_COMPLETE; 2199 ts->stat = SAS_DATA_OVERRUN; 2200 break; 2201 case IO_XFER_CMD_FRAME_ISSUED: 2202 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2203 return; 2204 default: 2205 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2206 /* not allowed case. Therefore, return failed status */ 2207 ts->resp = SAS_TASK_COMPLETE; 2208 ts->stat = SAS_DATA_OVERRUN; 2209 break; 2210 } 2211 spin_lock_irqsave(&t->task_state_lock, flags); 2212 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2213 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2214 t->task_state_flags |= SAS_TASK_STATE_DONE; 2215 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2216 spin_unlock_irqrestore(&t->task_state_lock, flags); 2217 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2218 t, event, ts->resp, ts->stat); 2219 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2220 } else { 2221 spin_unlock_irqrestore(&t->task_state_lock, flags); 2222 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2223 mb();/* in order to force CPU ordering */ 2224 t->task_done(t); 2225 } 2226 } 2227 2228 /*See the comments for mpi_ssp_completion */ 2229 static void 2230 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2231 { 2232 struct sas_task *t; 2233 struct pm8001_ccb_info *ccb; 2234 u32 param; 2235 u32 status; 2236 u32 tag; 2237 int i, j; 2238 u8 sata_addr_low[4]; 2239 u32 temp_sata_addr_low; 2240 u8 sata_addr_hi[4]; 2241 u32 temp_sata_addr_hi; 2242 struct sata_completion_resp *psataPayload; 2243 struct task_status_struct *ts; 2244 struct ata_task_resp *resp ; 2245 u32 *sata_resp; 2246 struct pm8001_device *pm8001_dev; 2247 unsigned long flags; 2248 2249 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2250 status = le32_to_cpu(psataPayload->status); 2251 tag = le32_to_cpu(psataPayload->tag); 2252 2253 if (!tag) { 2254 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); 2255 return; 2256 } 2257 ccb = &pm8001_ha->ccb_info[tag]; 2258 param = le32_to_cpu(psataPayload->param); 2259 if (ccb) { 2260 t = ccb->task; 2261 pm8001_dev = ccb->device; 2262 } else { 2263 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); 2264 return; 2265 } 2266 2267 if (t) { 2268 if (t->dev && (t->dev->lldd_dev)) 2269 pm8001_dev = t->dev->lldd_dev; 2270 } else { 2271 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2272 return; 2273 } 2274 2275 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2276 && unlikely(!t || !t->lldd_task || !t->dev)) { 2277 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2278 return; 2279 } 2280 2281 ts = &t->task_status; 2282 if (!ts) { 2283 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); 2284 return; 2285 } 2286 2287 if (status) 2288 pm8001_dbg(pm8001_ha, IOERR, 2289 "status:0x%x, tag:0x%x, task::0x%p\n", 2290 status, tag, t); 2291 2292 /* Print sas address of IO failed device */ 2293 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2294 (status != IO_UNDERFLOW)) { 2295 if (!((t->dev->parent) && 2296 (dev_is_expander(t->dev->parent->dev_type)))) { 2297 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++) 2298 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2299 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++) 2300 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2301 memcpy(&temp_sata_addr_low, sata_addr_low, 2302 sizeof(sata_addr_low)); 2303 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2304 sizeof(sata_addr_hi)); 2305 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2306 |((temp_sata_addr_hi << 8) & 2307 0xff0000) | 2308 ((temp_sata_addr_hi >> 8) 2309 & 0xff00) | 2310 ((temp_sata_addr_hi << 24) & 2311 0xff000000)); 2312 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2313 & 0xff) | 2314 ((temp_sata_addr_low << 8) 2315 & 0xff0000) | 2316 ((temp_sata_addr_low >> 8) 2317 & 0xff00) | 2318 ((temp_sata_addr_low << 24) 2319 & 0xff000000)) + 2320 pm8001_dev->attached_phy + 2321 0x10); 2322 pm8001_dbg(pm8001_ha, FAIL, 2323 "SAS Address of IO Failure Drive:%08x%08x\n", 2324 temp_sata_addr_hi, 2325 temp_sata_addr_low); 2326 } else { 2327 pm8001_dbg(pm8001_ha, FAIL, 2328 "SAS Address of IO Failure Drive:%016llx\n", 2329 SAS_ADDR(t->dev->sas_addr)); 2330 } 2331 } 2332 switch (status) { 2333 case IO_SUCCESS: 2334 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2335 if (param == 0) { 2336 ts->resp = SAS_TASK_COMPLETE; 2337 ts->stat = SAM_STAT_GOOD; 2338 /* check if response is for SEND READ LOG */ 2339 if (pm8001_dev && 2340 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2341 /* set new bit for abort_all */ 2342 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2343 /* clear bit for read log */ 2344 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2345 pm8001_send_abort_all(pm8001_ha, pm8001_dev); 2346 /* Free the tag */ 2347 pm8001_tag_free(pm8001_ha, tag); 2348 sas_free_task(t); 2349 return; 2350 } 2351 } else { 2352 u8 len; 2353 ts->resp = SAS_TASK_COMPLETE; 2354 ts->stat = SAS_PROTO_RESPONSE; 2355 ts->residual = param; 2356 pm8001_dbg(pm8001_ha, IO, 2357 "SAS_PROTO_RESPONSE len = %d\n", 2358 param); 2359 sata_resp = &psataPayload->sata_resp[0]; 2360 resp = (struct ata_task_resp *)ts->buf; 2361 if (t->ata_task.dma_xfer == 0 && 2362 t->data_dir == DMA_FROM_DEVICE) { 2363 len = sizeof(struct pio_setup_fis); 2364 pm8001_dbg(pm8001_ha, IO, 2365 "PIO read len = %d\n", len); 2366 } else if (t->ata_task.use_ncq) { 2367 len = sizeof(struct set_dev_bits_fis); 2368 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2369 len); 2370 } else { 2371 len = sizeof(struct dev_to_host_fis); 2372 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2373 len); 2374 } 2375 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2376 resp->frame_len = len; 2377 memcpy(&resp->ending_fis[0], sata_resp, len); 2378 ts->buf_valid_size = sizeof(*resp); 2379 } else 2380 pm8001_dbg(pm8001_ha, IO, 2381 "response too large\n"); 2382 } 2383 if (pm8001_dev) 2384 atomic_dec(&pm8001_dev->running_req); 2385 break; 2386 case IO_ABORTED: 2387 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2388 ts->resp = SAS_TASK_COMPLETE; 2389 ts->stat = SAS_ABORTED_TASK; 2390 if (pm8001_dev) 2391 atomic_dec(&pm8001_dev->running_req); 2392 break; 2393 /* following cases are to do cases */ 2394 case IO_UNDERFLOW: 2395 /* SATA Completion with error */ 2396 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2397 ts->resp = SAS_TASK_COMPLETE; 2398 ts->stat = SAS_DATA_UNDERRUN; 2399 ts->residual = param; 2400 if (pm8001_dev) 2401 atomic_dec(&pm8001_dev->running_req); 2402 break; 2403 case IO_NO_DEVICE: 2404 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2405 ts->resp = SAS_TASK_UNDELIVERED; 2406 ts->stat = SAS_PHY_DOWN; 2407 if (pm8001_dev) 2408 atomic_dec(&pm8001_dev->running_req); 2409 break; 2410 case IO_XFER_ERROR_BREAK: 2411 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2412 ts->resp = SAS_TASK_COMPLETE; 2413 ts->stat = SAS_INTERRUPTED; 2414 if (pm8001_dev) 2415 atomic_dec(&pm8001_dev->running_req); 2416 break; 2417 case IO_XFER_ERROR_PHY_NOT_READY: 2418 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2419 ts->resp = SAS_TASK_COMPLETE; 2420 ts->stat = SAS_OPEN_REJECT; 2421 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2422 if (pm8001_dev) 2423 atomic_dec(&pm8001_dev->running_req); 2424 break; 2425 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2426 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2427 ts->resp = SAS_TASK_COMPLETE; 2428 ts->stat = SAS_OPEN_REJECT; 2429 ts->open_rej_reason = SAS_OREJ_EPROTO; 2430 if (pm8001_dev) 2431 atomic_dec(&pm8001_dev->running_req); 2432 break; 2433 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2434 pm8001_dbg(pm8001_ha, IO, 2435 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2436 ts->resp = SAS_TASK_COMPLETE; 2437 ts->stat = SAS_OPEN_REJECT; 2438 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2439 if (pm8001_dev) 2440 atomic_dec(&pm8001_dev->running_req); 2441 break; 2442 case IO_OPEN_CNX_ERROR_BREAK: 2443 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2444 ts->resp = SAS_TASK_COMPLETE; 2445 ts->stat = SAS_OPEN_REJECT; 2446 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2447 if (pm8001_dev) 2448 atomic_dec(&pm8001_dev->running_req); 2449 break; 2450 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2451 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2452 ts->resp = SAS_TASK_COMPLETE; 2453 ts->stat = SAS_DEV_NO_RESPONSE; 2454 if (!t->uldd_task) { 2455 pm8001_handle_event(pm8001_ha, 2456 pm8001_dev, 2457 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2458 ts->resp = SAS_TASK_UNDELIVERED; 2459 ts->stat = SAS_QUEUE_FULL; 2460 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2461 return; 2462 } 2463 break; 2464 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2465 pm8001_dbg(pm8001_ha, IO, 2466 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2467 ts->resp = SAS_TASK_UNDELIVERED; 2468 ts->stat = SAS_OPEN_REJECT; 2469 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2470 if (!t->uldd_task) { 2471 pm8001_handle_event(pm8001_ha, 2472 pm8001_dev, 2473 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2474 ts->resp = SAS_TASK_UNDELIVERED; 2475 ts->stat = SAS_QUEUE_FULL; 2476 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2477 return; 2478 } 2479 break; 2480 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2481 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2482 ts->resp = SAS_TASK_COMPLETE; 2483 ts->stat = SAS_OPEN_REJECT; 2484 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2485 if (pm8001_dev) 2486 atomic_dec(&pm8001_dev->running_req); 2487 break; 2488 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2489 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAS_DEV_NO_RESPONSE; 2492 if (!t->uldd_task) { 2493 pm8001_handle_event(pm8001_ha, 2494 pm8001_dev, 2495 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2496 ts->resp = SAS_TASK_UNDELIVERED; 2497 ts->stat = SAS_QUEUE_FULL; 2498 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2499 return; 2500 } 2501 break; 2502 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2503 pm8001_dbg(pm8001_ha, IO, 2504 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2505 ts->resp = SAS_TASK_COMPLETE; 2506 ts->stat = SAS_OPEN_REJECT; 2507 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2508 if (pm8001_dev) 2509 atomic_dec(&pm8001_dev->running_req); 2510 break; 2511 case IO_XFER_ERROR_NAK_RECEIVED: 2512 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2513 ts->resp = SAS_TASK_COMPLETE; 2514 ts->stat = SAS_NAK_R_ERR; 2515 if (pm8001_dev) 2516 atomic_dec(&pm8001_dev->running_req); 2517 break; 2518 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2519 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2520 ts->resp = SAS_TASK_COMPLETE; 2521 ts->stat = SAS_NAK_R_ERR; 2522 if (pm8001_dev) 2523 atomic_dec(&pm8001_dev->running_req); 2524 break; 2525 case IO_XFER_ERROR_DMA: 2526 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2527 ts->resp = SAS_TASK_COMPLETE; 2528 ts->stat = SAS_ABORTED_TASK; 2529 if (pm8001_dev) 2530 atomic_dec(&pm8001_dev->running_req); 2531 break; 2532 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2533 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2534 ts->resp = SAS_TASK_UNDELIVERED; 2535 ts->stat = SAS_DEV_NO_RESPONSE; 2536 if (pm8001_dev) 2537 atomic_dec(&pm8001_dev->running_req); 2538 break; 2539 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2540 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2541 ts->resp = SAS_TASK_COMPLETE; 2542 ts->stat = SAS_DATA_UNDERRUN; 2543 if (pm8001_dev) 2544 atomic_dec(&pm8001_dev->running_req); 2545 break; 2546 case IO_XFER_OPEN_RETRY_TIMEOUT: 2547 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2548 ts->resp = SAS_TASK_COMPLETE; 2549 ts->stat = SAS_OPEN_TO; 2550 if (pm8001_dev) 2551 atomic_dec(&pm8001_dev->running_req); 2552 break; 2553 case IO_PORT_IN_RESET: 2554 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2555 ts->resp = SAS_TASK_COMPLETE; 2556 ts->stat = SAS_DEV_NO_RESPONSE; 2557 if (pm8001_dev) 2558 atomic_dec(&pm8001_dev->running_req); 2559 break; 2560 case IO_DS_NON_OPERATIONAL: 2561 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2562 ts->resp = SAS_TASK_COMPLETE; 2563 ts->stat = SAS_DEV_NO_RESPONSE; 2564 if (!t->uldd_task) { 2565 pm8001_handle_event(pm8001_ha, pm8001_dev, 2566 IO_DS_NON_OPERATIONAL); 2567 ts->resp = SAS_TASK_UNDELIVERED; 2568 ts->stat = SAS_QUEUE_FULL; 2569 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2570 return; 2571 } 2572 break; 2573 case IO_DS_IN_RECOVERY: 2574 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n"); 2575 ts->resp = SAS_TASK_COMPLETE; 2576 ts->stat = SAS_DEV_NO_RESPONSE; 2577 if (pm8001_dev) 2578 atomic_dec(&pm8001_dev->running_req); 2579 break; 2580 case IO_DS_IN_ERROR: 2581 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2582 ts->resp = SAS_TASK_COMPLETE; 2583 ts->stat = SAS_DEV_NO_RESPONSE; 2584 if (!t->uldd_task) { 2585 pm8001_handle_event(pm8001_ha, pm8001_dev, 2586 IO_DS_IN_ERROR); 2587 ts->resp = SAS_TASK_UNDELIVERED; 2588 ts->stat = SAS_QUEUE_FULL; 2589 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2590 return; 2591 } 2592 break; 2593 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2594 pm8001_dbg(pm8001_ha, IO, 2595 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2596 ts->resp = SAS_TASK_COMPLETE; 2597 ts->stat = SAS_OPEN_REJECT; 2598 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2599 if (pm8001_dev) 2600 atomic_dec(&pm8001_dev->running_req); 2601 break; 2602 default: 2603 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2604 /* not allowed case. Therefore, return failed status */ 2605 ts->resp = SAS_TASK_COMPLETE; 2606 ts->stat = SAS_DEV_NO_RESPONSE; 2607 if (pm8001_dev) 2608 atomic_dec(&pm8001_dev->running_req); 2609 break; 2610 } 2611 spin_lock_irqsave(&t->task_state_lock, flags); 2612 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2613 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2614 t->task_state_flags |= SAS_TASK_STATE_DONE; 2615 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2616 spin_unlock_irqrestore(&t->task_state_lock, flags); 2617 pm8001_dbg(pm8001_ha, FAIL, 2618 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2619 t, status, ts->resp, ts->stat); 2620 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2621 } else { 2622 spin_unlock_irqrestore(&t->task_state_lock, flags); 2623 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2624 } 2625 } 2626 2627 /*See the comments for mpi_ssp_completion */ 2628 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2629 { 2630 struct sas_task *t; 2631 struct task_status_struct *ts; 2632 struct pm8001_ccb_info *ccb; 2633 struct pm8001_device *pm8001_dev; 2634 struct sata_event_resp *psataPayload = 2635 (struct sata_event_resp *)(piomb + 4); 2636 u32 event = le32_to_cpu(psataPayload->event); 2637 u32 tag = le32_to_cpu(psataPayload->tag); 2638 u32 port_id = le32_to_cpu(psataPayload->port_id); 2639 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2640 unsigned long flags; 2641 2642 ccb = &pm8001_ha->ccb_info[tag]; 2643 2644 if (ccb) { 2645 t = ccb->task; 2646 pm8001_dev = ccb->device; 2647 } else { 2648 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); 2649 } 2650 if (event) 2651 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2652 2653 /* Check if this is NCQ error */ 2654 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2655 /* find device using device id */ 2656 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2657 /* send read log extension */ 2658 if (pm8001_dev) 2659 pm8001_send_read_log(pm8001_ha, pm8001_dev); 2660 return; 2661 } 2662 2663 ccb = &pm8001_ha->ccb_info[tag]; 2664 t = ccb->task; 2665 pm8001_dev = ccb->device; 2666 if (event) 2667 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event); 2668 if (unlikely(!t || !t->lldd_task || !t->dev)) 2669 return; 2670 ts = &t->task_status; 2671 pm8001_dbg(pm8001_ha, DEVIO, 2672 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2673 port_id, dev_id, tag, event); 2674 switch (event) { 2675 case IO_OVERFLOW: 2676 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2677 ts->resp = SAS_TASK_COMPLETE; 2678 ts->stat = SAS_DATA_OVERRUN; 2679 ts->residual = 0; 2680 if (pm8001_dev) 2681 atomic_dec(&pm8001_dev->running_req); 2682 break; 2683 case IO_XFER_ERROR_BREAK: 2684 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2685 ts->resp = SAS_TASK_COMPLETE; 2686 ts->stat = SAS_INTERRUPTED; 2687 break; 2688 case IO_XFER_ERROR_PHY_NOT_READY: 2689 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2690 ts->resp = SAS_TASK_COMPLETE; 2691 ts->stat = SAS_OPEN_REJECT; 2692 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2693 break; 2694 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2695 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2696 ts->resp = SAS_TASK_COMPLETE; 2697 ts->stat = SAS_OPEN_REJECT; 2698 ts->open_rej_reason = SAS_OREJ_EPROTO; 2699 break; 2700 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2701 pm8001_dbg(pm8001_ha, IO, 2702 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2703 ts->resp = SAS_TASK_COMPLETE; 2704 ts->stat = SAS_OPEN_REJECT; 2705 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2706 break; 2707 case IO_OPEN_CNX_ERROR_BREAK: 2708 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2709 ts->resp = SAS_TASK_COMPLETE; 2710 ts->stat = SAS_OPEN_REJECT; 2711 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2712 break; 2713 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2714 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2715 ts->resp = SAS_TASK_UNDELIVERED; 2716 ts->stat = SAS_DEV_NO_RESPONSE; 2717 if (!t->uldd_task) { 2718 pm8001_handle_event(pm8001_ha, 2719 pm8001_dev, 2720 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2721 ts->resp = SAS_TASK_COMPLETE; 2722 ts->stat = SAS_QUEUE_FULL; 2723 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2724 return; 2725 } 2726 break; 2727 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2728 pm8001_dbg(pm8001_ha, IO, 2729 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2730 ts->resp = SAS_TASK_UNDELIVERED; 2731 ts->stat = SAS_OPEN_REJECT; 2732 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2733 break; 2734 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2735 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2736 ts->resp = SAS_TASK_COMPLETE; 2737 ts->stat = SAS_OPEN_REJECT; 2738 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2739 break; 2740 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2741 pm8001_dbg(pm8001_ha, IO, 2742 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2743 ts->resp = SAS_TASK_COMPLETE; 2744 ts->stat = SAS_OPEN_REJECT; 2745 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2746 break; 2747 case IO_XFER_ERROR_NAK_RECEIVED: 2748 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2749 ts->resp = SAS_TASK_COMPLETE; 2750 ts->stat = SAS_NAK_R_ERR; 2751 break; 2752 case IO_XFER_ERROR_PEER_ABORTED: 2753 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2754 ts->resp = SAS_TASK_COMPLETE; 2755 ts->stat = SAS_NAK_R_ERR; 2756 break; 2757 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2758 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2759 ts->resp = SAS_TASK_COMPLETE; 2760 ts->stat = SAS_DATA_UNDERRUN; 2761 break; 2762 case IO_XFER_OPEN_RETRY_TIMEOUT: 2763 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2764 ts->resp = SAS_TASK_COMPLETE; 2765 ts->stat = SAS_OPEN_TO; 2766 break; 2767 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2768 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2769 ts->resp = SAS_TASK_COMPLETE; 2770 ts->stat = SAS_OPEN_TO; 2771 break; 2772 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2773 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2774 ts->resp = SAS_TASK_COMPLETE; 2775 ts->stat = SAS_OPEN_TO; 2776 break; 2777 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2778 pm8001_dbg(pm8001_ha, IO, 2779 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2780 ts->resp = SAS_TASK_COMPLETE; 2781 ts->stat = SAS_OPEN_TO; 2782 break; 2783 case IO_XFER_ERROR_OFFSET_MISMATCH: 2784 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2785 ts->resp = SAS_TASK_COMPLETE; 2786 ts->stat = SAS_OPEN_TO; 2787 break; 2788 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2789 pm8001_dbg(pm8001_ha, IO, 2790 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2791 ts->resp = SAS_TASK_COMPLETE; 2792 ts->stat = SAS_OPEN_TO; 2793 break; 2794 case IO_XFER_CMD_FRAME_ISSUED: 2795 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2796 break; 2797 case IO_XFER_PIO_SETUP_ERROR: 2798 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2799 ts->resp = SAS_TASK_COMPLETE; 2800 ts->stat = SAS_OPEN_TO; 2801 break; 2802 default: 2803 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2804 /* not allowed case. Therefore, return failed status */ 2805 ts->resp = SAS_TASK_COMPLETE; 2806 ts->stat = SAS_OPEN_TO; 2807 break; 2808 } 2809 spin_lock_irqsave(&t->task_state_lock, flags); 2810 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2811 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2812 t->task_state_flags |= SAS_TASK_STATE_DONE; 2813 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2814 spin_unlock_irqrestore(&t->task_state_lock, flags); 2815 pm8001_dbg(pm8001_ha, FAIL, 2816 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2817 t, event, ts->resp, ts->stat); 2818 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2819 } else { 2820 spin_unlock_irqrestore(&t->task_state_lock, flags); 2821 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2822 } 2823 } 2824 2825 /*See the comments for mpi_ssp_completion */ 2826 static void 2827 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2828 { 2829 struct sas_task *t; 2830 struct pm8001_ccb_info *ccb; 2831 unsigned long flags; 2832 u32 status; 2833 u32 tag; 2834 struct smp_completion_resp *psmpPayload; 2835 struct task_status_struct *ts; 2836 struct pm8001_device *pm8001_dev; 2837 2838 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2839 status = le32_to_cpu(psmpPayload->status); 2840 tag = le32_to_cpu(psmpPayload->tag); 2841 2842 ccb = &pm8001_ha->ccb_info[tag]; 2843 t = ccb->task; 2844 ts = &t->task_status; 2845 pm8001_dev = ccb->device; 2846 if (status) { 2847 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2848 pm8001_dbg(pm8001_ha, IOERR, 2849 "status:0x%x, tag:0x%x, task:0x%p\n", 2850 status, tag, t); 2851 } 2852 if (unlikely(!t || !t->lldd_task || !t->dev)) 2853 return; 2854 2855 switch (status) { 2856 case IO_SUCCESS: 2857 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2858 ts->resp = SAS_TASK_COMPLETE; 2859 ts->stat = SAM_STAT_GOOD; 2860 if (pm8001_dev) 2861 atomic_dec(&pm8001_dev->running_req); 2862 break; 2863 case IO_ABORTED: 2864 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 2865 ts->resp = SAS_TASK_COMPLETE; 2866 ts->stat = SAS_ABORTED_TASK; 2867 if (pm8001_dev) 2868 atomic_dec(&pm8001_dev->running_req); 2869 break; 2870 case IO_OVERFLOW: 2871 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2872 ts->resp = SAS_TASK_COMPLETE; 2873 ts->stat = SAS_DATA_OVERRUN; 2874 ts->residual = 0; 2875 if (pm8001_dev) 2876 atomic_dec(&pm8001_dev->running_req); 2877 break; 2878 case IO_NO_DEVICE: 2879 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2880 ts->resp = SAS_TASK_COMPLETE; 2881 ts->stat = SAS_PHY_DOWN; 2882 break; 2883 case IO_ERROR_HW_TIMEOUT: 2884 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 2885 ts->resp = SAS_TASK_COMPLETE; 2886 ts->stat = SAM_STAT_BUSY; 2887 break; 2888 case IO_XFER_ERROR_BREAK: 2889 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2890 ts->resp = SAS_TASK_COMPLETE; 2891 ts->stat = SAM_STAT_BUSY; 2892 break; 2893 case IO_XFER_ERROR_PHY_NOT_READY: 2894 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2895 ts->resp = SAS_TASK_COMPLETE; 2896 ts->stat = SAM_STAT_BUSY; 2897 break; 2898 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2899 pm8001_dbg(pm8001_ha, IO, 2900 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2901 ts->resp = SAS_TASK_COMPLETE; 2902 ts->stat = SAS_OPEN_REJECT; 2903 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2904 break; 2905 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2906 pm8001_dbg(pm8001_ha, IO, 2907 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2908 ts->resp = SAS_TASK_COMPLETE; 2909 ts->stat = SAS_OPEN_REJECT; 2910 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2911 break; 2912 case IO_OPEN_CNX_ERROR_BREAK: 2913 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2914 ts->resp = SAS_TASK_COMPLETE; 2915 ts->stat = SAS_OPEN_REJECT; 2916 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2917 break; 2918 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2919 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2920 ts->resp = SAS_TASK_COMPLETE; 2921 ts->stat = SAS_OPEN_REJECT; 2922 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2923 pm8001_handle_event(pm8001_ha, 2924 pm8001_dev, 2925 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2926 break; 2927 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2928 pm8001_dbg(pm8001_ha, IO, 2929 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2930 ts->resp = SAS_TASK_COMPLETE; 2931 ts->stat = SAS_OPEN_REJECT; 2932 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2933 break; 2934 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2935 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2936 ts->resp = SAS_TASK_COMPLETE; 2937 ts->stat = SAS_OPEN_REJECT; 2938 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2939 break; 2940 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2941 pm8001_dbg(pm8001_ha, IO, 2942 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2943 ts->resp = SAS_TASK_COMPLETE; 2944 ts->stat = SAS_OPEN_REJECT; 2945 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2946 break; 2947 case IO_XFER_ERROR_RX_FRAME: 2948 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 2949 ts->resp = SAS_TASK_COMPLETE; 2950 ts->stat = SAS_DEV_NO_RESPONSE; 2951 break; 2952 case IO_XFER_OPEN_RETRY_TIMEOUT: 2953 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2954 ts->resp = SAS_TASK_COMPLETE; 2955 ts->stat = SAS_OPEN_REJECT; 2956 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2957 break; 2958 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2959 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 2960 ts->resp = SAS_TASK_COMPLETE; 2961 ts->stat = SAS_QUEUE_FULL; 2962 break; 2963 case IO_PORT_IN_RESET: 2964 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2965 ts->resp = SAS_TASK_COMPLETE; 2966 ts->stat = SAS_OPEN_REJECT; 2967 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2968 break; 2969 case IO_DS_NON_OPERATIONAL: 2970 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2971 ts->resp = SAS_TASK_COMPLETE; 2972 ts->stat = SAS_DEV_NO_RESPONSE; 2973 break; 2974 case IO_DS_IN_RECOVERY: 2975 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2976 ts->resp = SAS_TASK_COMPLETE; 2977 ts->stat = SAS_OPEN_REJECT; 2978 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2979 break; 2980 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2981 pm8001_dbg(pm8001_ha, IO, 2982 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2983 ts->resp = SAS_TASK_COMPLETE; 2984 ts->stat = SAS_OPEN_REJECT; 2985 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2986 break; 2987 default: 2988 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2989 ts->resp = SAS_TASK_COMPLETE; 2990 ts->stat = SAS_DEV_NO_RESPONSE; 2991 /* not allowed case. Therefore, return failed status */ 2992 break; 2993 } 2994 spin_lock_irqsave(&t->task_state_lock, flags); 2995 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2996 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2997 t->task_state_flags |= SAS_TASK_STATE_DONE; 2998 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2999 spin_unlock_irqrestore(&t->task_state_lock, flags); 3000 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 3001 t, status, ts->resp, ts->stat); 3002 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3003 } else { 3004 spin_unlock_irqrestore(&t->task_state_lock, flags); 3005 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3006 mb();/* in order to force CPU ordering */ 3007 t->task_done(t); 3008 } 3009 } 3010 3011 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 3012 void *piomb) 3013 { 3014 struct set_dev_state_resp *pPayload = 3015 (struct set_dev_state_resp *)(piomb + 4); 3016 u32 tag = le32_to_cpu(pPayload->tag); 3017 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3018 struct pm8001_device *pm8001_dev = ccb->device; 3019 u32 status = le32_to_cpu(pPayload->status); 3020 u32 device_id = le32_to_cpu(pPayload->device_id); 3021 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 3022 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 3023 pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n", 3024 device_id, pds, nds, status); 3025 complete(pm8001_dev->setds_completion); 3026 ccb->task = NULL; 3027 ccb->ccb_tag = 0xFFFFFFFF; 3028 pm8001_tag_free(pm8001_ha, tag); 3029 } 3030 3031 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3032 { 3033 struct get_nvm_data_resp *pPayload = 3034 (struct get_nvm_data_resp *)(piomb + 4); 3035 u32 tag = le32_to_cpu(pPayload->tag); 3036 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3037 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3038 complete(pm8001_ha->nvmd_completion); 3039 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); 3040 if ((dlen_status & NVMD_STAT) != 0) { 3041 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n"); 3042 return; 3043 } 3044 ccb->task = NULL; 3045 ccb->ccb_tag = 0xFFFFFFFF; 3046 pm8001_tag_free(pm8001_ha, tag); 3047 } 3048 3049 void 3050 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3051 { 3052 struct fw_control_ex *fw_control_context; 3053 struct get_nvm_data_resp *pPayload = 3054 (struct get_nvm_data_resp *)(piomb + 4); 3055 u32 tag = le32_to_cpu(pPayload->tag); 3056 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3057 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3058 u32 ir_tds_bn_dps_das_nvm = 3059 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 3060 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 3061 fw_control_context = ccb->fw_control_context; 3062 3063 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n"); 3064 if ((dlen_status & NVMD_STAT) != 0) { 3065 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n"); 3066 complete(pm8001_ha->nvmd_completion); 3067 return; 3068 } 3069 3070 if (ir_tds_bn_dps_das_nvm & IPMode) { 3071 /* indirect mode - IR bit set */ 3072 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n"); 3073 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 3074 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 3075 memcpy(pm8001_ha->sas_addr, 3076 ((u8 *)virt_addr + 4), 3077 SAS_ADDR_SIZE); 3078 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n"); 3079 } 3080 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 3081 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 3082 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 3083 ; 3084 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 3085 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 3086 ; 3087 } else { 3088 /* Should not be happened*/ 3089 pm8001_dbg(pm8001_ha, MSG, 3090 "(IR=1)Wrong Device type 0x%x\n", 3091 ir_tds_bn_dps_das_nvm); 3092 } 3093 } else /* direct mode */{ 3094 pm8001_dbg(pm8001_ha, MSG, 3095 "Get NVMD success, IR=0, dataLen=%d\n", 3096 (dlen_status & NVMD_LEN) >> 24); 3097 } 3098 /* Though fw_control_context is freed below, usrAddr still needs 3099 * to be updated as this holds the response to the request function 3100 */ 3101 memcpy(fw_control_context->usrAddr, 3102 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3103 fw_control_context->len); 3104 kfree(ccb->fw_control_context); 3105 /* To avoid race condition, complete should be 3106 * called after the message is copied to 3107 * fw_control_context->usrAddr 3108 */ 3109 complete(pm8001_ha->nvmd_completion); 3110 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); 3111 ccb->task = NULL; 3112 ccb->ccb_tag = 0xFFFFFFFF; 3113 pm8001_tag_free(pm8001_ha, tag); 3114 } 3115 3116 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3117 { 3118 u32 tag; 3119 struct local_phy_ctl_resp *pPayload = 3120 (struct local_phy_ctl_resp *)(piomb + 4); 3121 u32 status = le32_to_cpu(pPayload->status); 3122 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3123 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3124 tag = le32_to_cpu(pPayload->tag); 3125 if (status != 0) { 3126 pm8001_dbg(pm8001_ha, MSG, 3127 "%x phy execute %x phy op failed!\n", 3128 phy_id, phy_op); 3129 } else { 3130 pm8001_dbg(pm8001_ha, MSG, 3131 "%x phy execute %x phy op success!\n", 3132 phy_id, phy_op); 3133 pm8001_ha->phy[phy_id].reset_success = true; 3134 } 3135 if (pm8001_ha->phy[phy_id].enable_completion) { 3136 complete(pm8001_ha->phy[phy_id].enable_completion); 3137 pm8001_ha->phy[phy_id].enable_completion = NULL; 3138 } 3139 pm8001_tag_free(pm8001_ha, tag); 3140 return 0; 3141 } 3142 3143 /** 3144 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3145 * @pm8001_ha: our hba card information 3146 * @i: which phy that received the event. 3147 * 3148 * when HBA driver received the identify done event or initiate FIS received 3149 * event(for SATA), it will invoke this function to notify the sas layer that 3150 * the sas toplogy has formed, please discover the the whole sas domain, 3151 * while receive a broadcast(change) primitive just tell the sas 3152 * layer to discover the changed domain rather than the whole domain. 3153 */ 3154 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3155 { 3156 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3157 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3158 if (!phy->phy_attached) 3159 return; 3160 3161 if (sas_phy->phy) { 3162 struct sas_phy *sphy = sas_phy->phy; 3163 sphy->negotiated_linkrate = sas_phy->linkrate; 3164 sphy->minimum_linkrate = phy->minimum_linkrate; 3165 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3166 sphy->maximum_linkrate = phy->maximum_linkrate; 3167 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 3168 } 3169 3170 if (phy->phy_type & PORT_TYPE_SAS) { 3171 struct sas_identify_frame *id; 3172 id = (struct sas_identify_frame *)phy->frame_rcvd; 3173 id->dev_type = phy->identify.device_type; 3174 id->initiator_bits = SAS_PROTOCOL_ALL; 3175 id->target_bits = phy->identify.target_port_protocols; 3176 } else if (phy->phy_type & PORT_TYPE_SATA) { 3177 /*Nothing*/ 3178 } 3179 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i); 3180 3181 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3182 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 3183 } 3184 3185 /* Get the link rate speed */ 3186 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3187 { 3188 struct sas_phy *sas_phy = phy->sas_phy.phy; 3189 3190 switch (link_rate) { 3191 case PHY_SPEED_120: 3192 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3193 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS; 3194 break; 3195 case PHY_SPEED_60: 3196 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3197 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3198 break; 3199 case PHY_SPEED_30: 3200 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3201 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3202 break; 3203 case PHY_SPEED_15: 3204 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3205 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3206 break; 3207 } 3208 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3209 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3210 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3211 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3212 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3213 } 3214 3215 /** 3216 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3217 * @phy: pointer to asd_phy 3218 * @sas_addr: pointer to buffer where the SAS address is to be written 3219 * 3220 * This function extracts the SAS address from an IDENTIFY frame 3221 * received. If OOB is SATA, then a SAS address is generated from the 3222 * HA tables. 3223 * 3224 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3225 * buffer. 3226 */ 3227 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3228 u8 *sas_addr) 3229 { 3230 if (phy->sas_phy.frame_rcvd[0] == 0x34 3231 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3232 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3233 /* FIS device-to-host */ 3234 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3235 addr += phy->sas_phy.id; 3236 *(__be64 *)sas_addr = cpu_to_be64(addr); 3237 } else { 3238 struct sas_identify_frame *idframe = 3239 (void *) phy->sas_phy.frame_rcvd; 3240 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3241 } 3242 } 3243 3244 /** 3245 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3246 * @pm8001_ha: our hba card information 3247 * @Qnum: the outbound queue message number. 3248 * @SEA: source of event to ack 3249 * @port_id: port id. 3250 * @phyId: phy id. 3251 * @param0: parameter 0. 3252 * @param1: parameter 1. 3253 */ 3254 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3255 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3256 { 3257 struct hw_event_ack_req payload; 3258 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3259 3260 struct inbound_queue_table *circularQ; 3261 3262 memset((u8 *)&payload, 0, sizeof(payload)); 3263 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3264 payload.tag = cpu_to_le32(1); 3265 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3266 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3267 payload.param0 = cpu_to_le32(param0); 3268 payload.param1 = cpu_to_le32(param1); 3269 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3270 sizeof(payload), 0); 3271 } 3272 3273 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3274 u32 phyId, u32 phy_op); 3275 3276 /** 3277 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3278 * @pm8001_ha: our hba card information 3279 * @piomb: IO message buffer 3280 */ 3281 static void 3282 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3283 { 3284 struct hw_event_resp *pPayload = 3285 (struct hw_event_resp *)(piomb + 4); 3286 u32 lr_evt_status_phyid_portid = 3287 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3288 u8 link_rate = 3289 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3290 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3291 u8 phy_id = 3292 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3293 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3294 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3295 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3296 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3297 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3298 unsigned long flags; 3299 u8 deviceType = pPayload->sas_identify.dev_type; 3300 port->port_state = portstate; 3301 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3302 pm8001_dbg(pm8001_ha, MSG, 3303 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3304 port_id, phy_id); 3305 3306 switch (deviceType) { 3307 case SAS_PHY_UNUSED: 3308 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3309 break; 3310 case SAS_END_DEVICE: 3311 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3312 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3313 PHY_NOTIFY_ENABLE_SPINUP); 3314 port->port_attached = 1; 3315 pm8001_get_lrate_mode(phy, link_rate); 3316 break; 3317 case SAS_EDGE_EXPANDER_DEVICE: 3318 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3319 port->port_attached = 1; 3320 pm8001_get_lrate_mode(phy, link_rate); 3321 break; 3322 case SAS_FANOUT_EXPANDER_DEVICE: 3323 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3324 port->port_attached = 1; 3325 pm8001_get_lrate_mode(phy, link_rate); 3326 break; 3327 default: 3328 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3329 deviceType); 3330 break; 3331 } 3332 phy->phy_type |= PORT_TYPE_SAS; 3333 phy->identify.device_type = deviceType; 3334 phy->phy_attached = 1; 3335 if (phy->identify.device_type == SAS_END_DEVICE) 3336 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3337 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3338 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3339 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3340 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3341 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3342 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3343 sizeof(struct sas_identify_frame)-4); 3344 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3345 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3346 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3347 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3348 mdelay(200);/*delay a moment to wait disk to spinup*/ 3349 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3350 } 3351 3352 /** 3353 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3354 * @pm8001_ha: our hba card information 3355 * @piomb: IO message buffer 3356 */ 3357 static void 3358 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3359 { 3360 struct hw_event_resp *pPayload = 3361 (struct hw_event_resp *)(piomb + 4); 3362 u32 lr_evt_status_phyid_portid = 3363 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3364 u8 link_rate = 3365 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3366 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3367 u8 phy_id = 3368 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3369 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3370 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3371 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3372 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3373 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3374 unsigned long flags; 3375 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n", 3376 port_id, phy_id); 3377 port->port_state = portstate; 3378 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3379 port->port_attached = 1; 3380 pm8001_get_lrate_mode(phy, link_rate); 3381 phy->phy_type |= PORT_TYPE_SATA; 3382 phy->phy_attached = 1; 3383 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3384 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3385 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3386 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3387 sizeof(struct dev_to_host_fis)); 3388 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3389 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3390 phy->identify.device_type = SAS_SATA_DEV; 3391 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3392 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3393 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3394 } 3395 3396 /** 3397 * hw_event_phy_down -we should notify the libsas the phy is down. 3398 * @pm8001_ha: our hba card information 3399 * @piomb: IO message buffer 3400 */ 3401 static void 3402 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3403 { 3404 struct hw_event_resp *pPayload = 3405 (struct hw_event_resp *)(piomb + 4); 3406 u32 lr_evt_status_phyid_portid = 3407 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3408 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3409 u8 phy_id = 3410 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3411 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3412 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3413 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3414 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3415 port->port_state = portstate; 3416 phy->phy_type = 0; 3417 phy->identify.device_type = 0; 3418 phy->phy_attached = 0; 3419 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3420 switch (portstate) { 3421 case PORT_VALID: 3422 break; 3423 case PORT_INVALID: 3424 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3425 port_id); 3426 pm8001_dbg(pm8001_ha, MSG, 3427 " Last phy Down and port invalid\n"); 3428 port->port_attached = 0; 3429 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3430 port_id, phy_id, 0, 0); 3431 break; 3432 case PORT_IN_RESET: 3433 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3434 port_id); 3435 break; 3436 case PORT_NOT_ESTABLISHED: 3437 pm8001_dbg(pm8001_ha, MSG, 3438 " phy Down and PORT_NOT_ESTABLISHED\n"); 3439 port->port_attached = 0; 3440 break; 3441 case PORT_LOSTCOMM: 3442 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n"); 3443 pm8001_dbg(pm8001_ha, MSG, 3444 " Last phy Down and port invalid\n"); 3445 port->port_attached = 0; 3446 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3447 port_id, phy_id, 0, 0); 3448 break; 3449 default: 3450 port->port_attached = 0; 3451 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n", 3452 portstate); 3453 break; 3454 3455 } 3456 } 3457 3458 /** 3459 * pm8001_mpi_reg_resp -process register device ID response. 3460 * @pm8001_ha: our hba card information 3461 * @piomb: IO message buffer 3462 * 3463 * when sas layer find a device it will notify LLDD, then the driver register 3464 * the domain device to FW, this event is the return device ID which the FW 3465 * has assigned, from now,inter-communication with FW is no longer using the 3466 * SAS address, use device ID which FW assigned. 3467 */ 3468 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3469 { 3470 u32 status; 3471 u32 device_id; 3472 u32 htag; 3473 struct pm8001_ccb_info *ccb; 3474 struct pm8001_device *pm8001_dev; 3475 struct dev_reg_resp *registerRespPayload = 3476 (struct dev_reg_resp *)(piomb + 4); 3477 3478 htag = le32_to_cpu(registerRespPayload->tag); 3479 ccb = &pm8001_ha->ccb_info[htag]; 3480 pm8001_dev = ccb->device; 3481 status = le32_to_cpu(registerRespPayload->status); 3482 device_id = le32_to_cpu(registerRespPayload->device_id); 3483 pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n", 3484 status); 3485 switch (status) { 3486 case DEVREG_SUCCESS: 3487 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n"); 3488 pm8001_dev->device_id = device_id; 3489 break; 3490 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3491 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n"); 3492 break; 3493 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3494 pm8001_dbg(pm8001_ha, MSG, 3495 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"); 3496 break; 3497 case DEVREG_FAILURE_INVALID_PHY_ID: 3498 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n"); 3499 break; 3500 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3501 pm8001_dbg(pm8001_ha, MSG, 3502 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"); 3503 break; 3504 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3505 pm8001_dbg(pm8001_ha, MSG, 3506 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"); 3507 break; 3508 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3509 pm8001_dbg(pm8001_ha, MSG, 3510 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"); 3511 break; 3512 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3513 pm8001_dbg(pm8001_ha, MSG, 3514 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"); 3515 break; 3516 default: 3517 pm8001_dbg(pm8001_ha, MSG, 3518 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"); 3519 break; 3520 } 3521 complete(pm8001_dev->dcompletion); 3522 ccb->task = NULL; 3523 ccb->ccb_tag = 0xFFFFFFFF; 3524 pm8001_tag_free(pm8001_ha, htag); 3525 return 0; 3526 } 3527 3528 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3529 { 3530 u32 status; 3531 u32 device_id; 3532 struct dev_reg_resp *registerRespPayload = 3533 (struct dev_reg_resp *)(piomb + 4); 3534 3535 status = le32_to_cpu(registerRespPayload->status); 3536 device_id = le32_to_cpu(registerRespPayload->device_id); 3537 if (status != 0) 3538 pm8001_dbg(pm8001_ha, MSG, 3539 " deregister device failed ,status = %x, device_id = %x\n", 3540 status, device_id); 3541 return 0; 3542 } 3543 3544 /** 3545 * fw_flash_update_resp - Response from FW for flash update command. 3546 * @pm8001_ha: our hba card information 3547 * @piomb: IO message buffer 3548 */ 3549 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3550 void *piomb) 3551 { 3552 u32 status; 3553 struct fw_flash_Update_resp *ppayload = 3554 (struct fw_flash_Update_resp *)(piomb + 4); 3555 u32 tag = le32_to_cpu(ppayload->tag); 3556 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3557 status = le32_to_cpu(ppayload->status); 3558 switch (status) { 3559 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3560 pm8001_dbg(pm8001_ha, MSG, 3561 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"); 3562 break; 3563 case FLASH_UPDATE_IN_PROGRESS: 3564 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n"); 3565 break; 3566 case FLASH_UPDATE_HDR_ERR: 3567 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n"); 3568 break; 3569 case FLASH_UPDATE_OFFSET_ERR: 3570 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n"); 3571 break; 3572 case FLASH_UPDATE_CRC_ERR: 3573 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n"); 3574 break; 3575 case FLASH_UPDATE_LENGTH_ERR: 3576 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n"); 3577 break; 3578 case FLASH_UPDATE_HW_ERR: 3579 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n"); 3580 break; 3581 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3582 pm8001_dbg(pm8001_ha, MSG, 3583 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"); 3584 break; 3585 case FLASH_UPDATE_DISABLED: 3586 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n"); 3587 break; 3588 default: 3589 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n", 3590 status); 3591 break; 3592 } 3593 kfree(ccb->fw_control_context); 3594 ccb->task = NULL; 3595 ccb->ccb_tag = 0xFFFFFFFF; 3596 pm8001_tag_free(pm8001_ha, tag); 3597 complete(pm8001_ha->nvmd_completion); 3598 return 0; 3599 } 3600 3601 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3602 { 3603 u32 status; 3604 int i; 3605 struct general_event_resp *pPayload = 3606 (struct general_event_resp *)(piomb + 4); 3607 status = le32_to_cpu(pPayload->status); 3608 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status); 3609 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3610 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n", 3611 i, 3612 pPayload->inb_IOMB_payload[i]); 3613 return 0; 3614 } 3615 3616 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3617 { 3618 struct sas_task *t; 3619 struct pm8001_ccb_info *ccb; 3620 unsigned long flags; 3621 u32 status ; 3622 u32 tag, scp; 3623 struct task_status_struct *ts; 3624 struct pm8001_device *pm8001_dev; 3625 3626 struct task_abort_resp *pPayload = 3627 (struct task_abort_resp *)(piomb + 4); 3628 3629 status = le32_to_cpu(pPayload->status); 3630 tag = le32_to_cpu(pPayload->tag); 3631 if (!tag) { 3632 pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n"); 3633 return -1; 3634 } 3635 3636 scp = le32_to_cpu(pPayload->scp); 3637 ccb = &pm8001_ha->ccb_info[tag]; 3638 t = ccb->task; 3639 pm8001_dev = ccb->device; /* retrieve device */ 3640 3641 if (!t) { 3642 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n"); 3643 return -1; 3644 } 3645 ts = &t->task_status; 3646 if (status != 0) 3647 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n", 3648 status, tag, scp); 3649 switch (status) { 3650 case IO_SUCCESS: 3651 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n"); 3652 ts->resp = SAS_TASK_COMPLETE; 3653 ts->stat = SAM_STAT_GOOD; 3654 break; 3655 case IO_NOT_VALID: 3656 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n"); 3657 ts->resp = TMF_RESP_FUNC_FAILED; 3658 break; 3659 } 3660 spin_lock_irqsave(&t->task_state_lock, flags); 3661 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3662 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3663 t->task_state_flags |= SAS_TASK_STATE_DONE; 3664 spin_unlock_irqrestore(&t->task_state_lock, flags); 3665 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3666 mb(); 3667 3668 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) { 3669 pm8001_tag_free(pm8001_ha, tag); 3670 sas_free_task(t); 3671 /* clear the flag */ 3672 pm8001_dev->id &= 0xBFFFFFFF; 3673 } else 3674 t->task_done(t); 3675 3676 return 0; 3677 } 3678 3679 /** 3680 * mpi_hw_event -The hw event has come. 3681 * @pm8001_ha: our hba card information 3682 * @piomb: IO message buffer 3683 */ 3684 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3685 { 3686 unsigned long flags; 3687 struct hw_event_resp *pPayload = 3688 (struct hw_event_resp *)(piomb + 4); 3689 u32 lr_evt_status_phyid_portid = 3690 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3691 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3692 u8 phy_id = 3693 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3694 u16 eventType = 3695 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3696 u8 status = 3697 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3698 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3699 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3700 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3701 pm8001_dbg(pm8001_ha, DEVIO, 3702 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n", 3703 port_id, phy_id, eventType, status); 3704 switch (eventType) { 3705 case HW_EVENT_PHY_START_STATUS: 3706 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n", 3707 status); 3708 if (status == 0) { 3709 phy->phy_state = 1; 3710 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3711 phy->enable_completion != NULL) 3712 complete(phy->enable_completion); 3713 } 3714 break; 3715 case HW_EVENT_SAS_PHY_UP: 3716 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3717 hw_event_sas_phy_up(pm8001_ha, piomb); 3718 break; 3719 case HW_EVENT_SATA_PHY_UP: 3720 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3721 hw_event_sata_phy_up(pm8001_ha, piomb); 3722 break; 3723 case HW_EVENT_PHY_STOP_STATUS: 3724 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n", 3725 status); 3726 if (status == 0) 3727 phy->phy_state = 0; 3728 break; 3729 case HW_EVENT_SATA_SPINUP_HOLD: 3730 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3731 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3732 break; 3733 case HW_EVENT_PHY_DOWN: 3734 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3735 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3736 phy->phy_attached = 0; 3737 phy->phy_state = 0; 3738 hw_event_phy_down(pm8001_ha, piomb); 3739 break; 3740 case HW_EVENT_PORT_INVALID: 3741 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3742 sas_phy_disconnected(sas_phy); 3743 phy->phy_attached = 0; 3744 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3745 break; 3746 /* the broadcast change primitive received, tell the LIBSAS this event 3747 to revalidate the sas domain*/ 3748 case HW_EVENT_BROADCAST_CHANGE: 3749 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3750 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3751 port_id, phy_id, 1, 0); 3752 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3753 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3754 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3755 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3756 break; 3757 case HW_EVENT_PHY_ERROR: 3758 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3759 sas_phy_disconnected(&phy->sas_phy); 3760 phy->phy_attached = 0; 3761 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3762 break; 3763 case HW_EVENT_BROADCAST_EXP: 3764 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3765 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3766 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3767 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3768 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3769 break; 3770 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3771 pm8001_dbg(pm8001_ha, MSG, 3772 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3773 pm8001_hw_event_ack_req(pm8001_ha, 0, 3774 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3775 sas_phy_disconnected(sas_phy); 3776 phy->phy_attached = 0; 3777 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3778 break; 3779 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3780 pm8001_dbg(pm8001_ha, MSG, 3781 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3782 pm8001_hw_event_ack_req(pm8001_ha, 0, 3783 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3784 port_id, phy_id, 0, 0); 3785 sas_phy_disconnected(sas_phy); 3786 phy->phy_attached = 0; 3787 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3788 break; 3789 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3790 pm8001_dbg(pm8001_ha, MSG, 3791 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3792 pm8001_hw_event_ack_req(pm8001_ha, 0, 3793 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3794 port_id, phy_id, 0, 0); 3795 sas_phy_disconnected(sas_phy); 3796 phy->phy_attached = 0; 3797 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3798 break; 3799 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3800 pm8001_dbg(pm8001_ha, MSG, 3801 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3802 pm8001_hw_event_ack_req(pm8001_ha, 0, 3803 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3804 port_id, phy_id, 0, 0); 3805 sas_phy_disconnected(sas_phy); 3806 phy->phy_attached = 0; 3807 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3808 break; 3809 case HW_EVENT_MALFUNCTION: 3810 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3811 break; 3812 case HW_EVENT_BROADCAST_SES: 3813 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3814 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3815 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3816 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3817 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3818 break; 3819 case HW_EVENT_INBOUND_CRC_ERROR: 3820 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3821 pm8001_hw_event_ack_req(pm8001_ha, 0, 3822 HW_EVENT_INBOUND_CRC_ERROR, 3823 port_id, phy_id, 0, 0); 3824 break; 3825 case HW_EVENT_HARD_RESET_RECEIVED: 3826 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3827 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3828 break; 3829 case HW_EVENT_ID_FRAME_TIMEOUT: 3830 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3831 sas_phy_disconnected(sas_phy); 3832 phy->phy_attached = 0; 3833 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3834 break; 3835 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3836 pm8001_dbg(pm8001_ha, MSG, 3837 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3838 pm8001_hw_event_ack_req(pm8001_ha, 0, 3839 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3840 port_id, phy_id, 0, 0); 3841 sas_phy_disconnected(sas_phy); 3842 phy->phy_attached = 0; 3843 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3844 break; 3845 case HW_EVENT_PORT_RESET_TIMER_TMO: 3846 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3847 sas_phy_disconnected(sas_phy); 3848 phy->phy_attached = 0; 3849 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3850 break; 3851 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3852 pm8001_dbg(pm8001_ha, MSG, 3853 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3854 sas_phy_disconnected(sas_phy); 3855 phy->phy_attached = 0; 3856 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3857 break; 3858 case HW_EVENT_PORT_RECOVER: 3859 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3860 break; 3861 case HW_EVENT_PORT_RESET_COMPLETE: 3862 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3863 break; 3864 case EVENT_BROADCAST_ASYNCH_EVENT: 3865 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3866 break; 3867 default: 3868 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n", 3869 eventType); 3870 break; 3871 } 3872 return 0; 3873 } 3874 3875 /** 3876 * process_one_iomb - process one outbound Queue memory block 3877 * @pm8001_ha: our hba card information 3878 * @piomb: IO message buffer 3879 */ 3880 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3881 { 3882 __le32 pHeader = *(__le32 *)piomb; 3883 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 3884 3885 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n"); 3886 3887 switch (opc) { 3888 case OPC_OUB_ECHO: 3889 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3890 break; 3891 case OPC_OUB_HW_EVENT: 3892 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3893 mpi_hw_event(pm8001_ha, piomb); 3894 break; 3895 case OPC_OUB_SSP_COMP: 3896 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3897 mpi_ssp_completion(pm8001_ha, piomb); 3898 break; 3899 case OPC_OUB_SMP_COMP: 3900 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3901 mpi_smp_completion(pm8001_ha, piomb); 3902 break; 3903 case OPC_OUB_LOCAL_PHY_CNTRL: 3904 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3905 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3906 break; 3907 case OPC_OUB_DEV_REGIST: 3908 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3909 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3910 break; 3911 case OPC_OUB_DEREG_DEV: 3912 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3913 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3914 break; 3915 case OPC_OUB_GET_DEV_HANDLE: 3916 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3917 break; 3918 case OPC_OUB_SATA_COMP: 3919 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3920 mpi_sata_completion(pm8001_ha, piomb); 3921 break; 3922 case OPC_OUB_SATA_EVENT: 3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3924 mpi_sata_event(pm8001_ha, piomb); 3925 break; 3926 case OPC_OUB_SSP_EVENT: 3927 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3928 mpi_ssp_event(pm8001_ha, piomb); 3929 break; 3930 case OPC_OUB_DEV_HANDLE_ARRIV: 3931 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3932 /*This is for target*/ 3933 break; 3934 case OPC_OUB_SSP_RECV_EVENT: 3935 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3936 /*This is for target*/ 3937 break; 3938 case OPC_OUB_DEV_INFO: 3939 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n"); 3940 break; 3941 case OPC_OUB_FW_FLASH_UPDATE: 3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3943 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3944 break; 3945 case OPC_OUB_GPIO_RESPONSE: 3946 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3947 break; 3948 case OPC_OUB_GPIO_EVENT: 3949 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3950 break; 3951 case OPC_OUB_GENERAL_EVENT: 3952 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3953 pm8001_mpi_general_event(pm8001_ha, piomb); 3954 break; 3955 case OPC_OUB_SSP_ABORT_RSP: 3956 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3957 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3958 break; 3959 case OPC_OUB_SATA_ABORT_RSP: 3960 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3961 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3962 break; 3963 case OPC_OUB_SAS_DIAG_MODE_START_END: 3964 pm8001_dbg(pm8001_ha, MSG, 3965 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3966 break; 3967 case OPC_OUB_SAS_DIAG_EXECUTE: 3968 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3969 break; 3970 case OPC_OUB_GET_TIME_STAMP: 3971 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3972 break; 3973 case OPC_OUB_SAS_HW_EVENT_ACK: 3974 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3975 break; 3976 case OPC_OUB_PORT_CONTROL: 3977 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3978 break; 3979 case OPC_OUB_SMP_ABORT_RSP: 3980 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3981 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3982 break; 3983 case OPC_OUB_GET_NVMD_DATA: 3984 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3985 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3986 break; 3987 case OPC_OUB_SET_NVMD_DATA: 3988 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3989 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3990 break; 3991 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3992 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3993 break; 3994 case OPC_OUB_SET_DEVICE_STATE: 3995 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3996 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3997 break; 3998 case OPC_OUB_GET_DEVICE_STATE: 3999 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 4000 break; 4001 case OPC_OUB_SET_DEV_INFO: 4002 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 4003 break; 4004 case OPC_OUB_SAS_RE_INITIALIZE: 4005 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n"); 4006 break; 4007 default: 4008 pm8001_dbg(pm8001_ha, DEVIO, 4009 "Unknown outbound Queue IOMB OPC = %x\n", 4010 opc); 4011 break; 4012 } 4013 } 4014 4015 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4016 { 4017 struct outbound_queue_table *circularQ; 4018 void *pMsg1 = NULL; 4019 u8 bc; 4020 u32 ret = MPI_IO_STATUS_FAIL; 4021 unsigned long flags; 4022 4023 spin_lock_irqsave(&pm8001_ha->lock, flags); 4024 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4025 do { 4026 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4027 if (MPI_IO_STATUS_SUCCESS == ret) { 4028 /* process the outbound message */ 4029 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4030 /* free the message from the outbound circular buffer */ 4031 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4032 circularQ, bc); 4033 } 4034 if (MPI_IO_STATUS_BUSY == ret) { 4035 /* Update the producer index from SPC */ 4036 circularQ->producer_index = 4037 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4038 if (le32_to_cpu(circularQ->producer_index) == 4039 circularQ->consumer_idx) 4040 /* OQ is empty */ 4041 break; 4042 } 4043 } while (1); 4044 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4045 return ret; 4046 } 4047 4048 /* DMA_... to our direction translation. */ 4049 static const u8 data_dir_flags[] = { 4050 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4051 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4052 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4053 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4054 }; 4055 void 4056 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 4057 { 4058 int i; 4059 struct scatterlist *sg; 4060 struct pm8001_prd *buf_prd = prd; 4061 4062 for_each_sg(scatter, sg, nr, i) { 4063 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 4064 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 4065 buf_prd->im_len.e = 0; 4066 buf_prd++; 4067 } 4068 } 4069 4070 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 4071 { 4072 psmp_cmd->tag = hTag; 4073 psmp_cmd->device_id = cpu_to_le32(deviceID); 4074 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4075 } 4076 4077 /** 4078 * pm8001_chip_smp_req - send a SMP task to FW 4079 * @pm8001_ha: our hba card information. 4080 * @ccb: the ccb information this request used. 4081 */ 4082 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4083 struct pm8001_ccb_info *ccb) 4084 { 4085 int elem, rc; 4086 struct sas_task *task = ccb->task; 4087 struct domain_device *dev = task->dev; 4088 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4089 struct scatterlist *sg_req, *sg_resp; 4090 u32 req_len, resp_len; 4091 struct smp_req smp_cmd; 4092 u32 opc; 4093 struct inbound_queue_table *circularQ; 4094 4095 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4096 /* 4097 * DMA-map SMP request, response buffers 4098 */ 4099 sg_req = &task->smp_task.smp_req; 4100 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4101 if (!elem) 4102 return -ENOMEM; 4103 req_len = sg_dma_len(sg_req); 4104 4105 sg_resp = &task->smp_task.smp_resp; 4106 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4107 if (!elem) { 4108 rc = -ENOMEM; 4109 goto err_out; 4110 } 4111 resp_len = sg_dma_len(sg_resp); 4112 /* must be in dwords */ 4113 if ((req_len & 0x3) || (resp_len & 0x3)) { 4114 rc = -EINVAL; 4115 goto err_out_2; 4116 } 4117 4118 opc = OPC_INB_SMP_REQUEST; 4119 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4120 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4121 smp_cmd.long_smp_req.long_req_addr = 4122 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4123 smp_cmd.long_smp_req.long_req_size = 4124 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4125 smp_cmd.long_smp_req.long_resp_addr = 4126 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4127 smp_cmd.long_smp_req.long_resp_size = 4128 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4129 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4130 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4131 &smp_cmd, sizeof(smp_cmd), 0); 4132 if (rc) 4133 goto err_out_2; 4134 4135 return 0; 4136 4137 err_out_2: 4138 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4139 DMA_FROM_DEVICE); 4140 err_out: 4141 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4142 DMA_TO_DEVICE); 4143 return rc; 4144 } 4145 4146 /** 4147 * pm8001_chip_ssp_io_req - send a SSP task to FW 4148 * @pm8001_ha: our hba card information. 4149 * @ccb: the ccb information this request used. 4150 */ 4151 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4152 struct pm8001_ccb_info *ccb) 4153 { 4154 struct sas_task *task = ccb->task; 4155 struct domain_device *dev = task->dev; 4156 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4157 struct ssp_ini_io_start_req ssp_cmd; 4158 u32 tag = ccb->ccb_tag; 4159 int ret; 4160 u64 phys_addr; 4161 struct inbound_queue_table *circularQ; 4162 u32 opc = OPC_INB_SSPINIIOSTART; 4163 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4164 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4165 ssp_cmd.dir_m_tlr = 4166 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4167 SAS 1.1 compatible TLR*/ 4168 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4169 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4170 ssp_cmd.tag = cpu_to_le32(tag); 4171 if (task->ssp_task.enable_first_burst) 4172 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4173 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4174 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4175 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4176 task->ssp_task.cmd->cmd_len); 4177 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4178 4179 /* fill in PRD (scatter/gather) table, if any */ 4180 if (task->num_scatter > 1) { 4181 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4182 phys_addr = ccb->ccb_dma_handle; 4183 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4184 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4185 ssp_cmd.esgl = cpu_to_le32(1<<31); 4186 } else if (task->num_scatter == 1) { 4187 u64 dma_addr = sg_dma_address(task->scatter); 4188 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4189 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4190 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4191 ssp_cmd.esgl = 0; 4192 } else if (task->num_scatter == 0) { 4193 ssp_cmd.addr_low = 0; 4194 ssp_cmd.addr_high = 0; 4195 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4196 ssp_cmd.esgl = 0; 4197 } 4198 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 4199 sizeof(ssp_cmd), 0); 4200 return ret; 4201 } 4202 4203 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4204 struct pm8001_ccb_info *ccb) 4205 { 4206 struct sas_task *task = ccb->task; 4207 struct domain_device *dev = task->dev; 4208 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4209 u32 tag = ccb->ccb_tag; 4210 int ret; 4211 struct sata_start_req sata_cmd; 4212 u32 hdr_tag, ncg_tag = 0; 4213 u64 phys_addr; 4214 u32 ATAP = 0x0; 4215 u32 dir; 4216 struct inbound_queue_table *circularQ; 4217 unsigned long flags; 4218 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4219 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4220 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4221 if (task->data_dir == DMA_NONE) { 4222 ATAP = 0x04; /* no data*/ 4223 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4224 } else if (likely(!task->ata_task.device_control_reg_update)) { 4225 if (task->ata_task.dma_xfer) { 4226 ATAP = 0x06; /* DMA */ 4227 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4228 } else { 4229 ATAP = 0x05; /* PIO*/ 4230 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4231 } 4232 if (task->ata_task.use_ncq && 4233 dev->sata_dev.class != ATA_DEV_ATAPI) { 4234 ATAP = 0x07; /* FPDMA */ 4235 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4236 } 4237 } 4238 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4239 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4240 ncg_tag = hdr_tag; 4241 } 4242 dir = data_dir_flags[task->data_dir] << 8; 4243 sata_cmd.tag = cpu_to_le32(tag); 4244 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4245 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4246 sata_cmd.ncqtag_atap_dir_m = 4247 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4248 sata_cmd.sata_fis = task->ata_task.fis; 4249 if (likely(!task->ata_task.device_control_reg_update)) 4250 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4251 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4252 /* fill in PRD (scatter/gather) table, if any */ 4253 if (task->num_scatter > 1) { 4254 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4255 phys_addr = ccb->ccb_dma_handle; 4256 sata_cmd.addr_low = lower_32_bits(phys_addr); 4257 sata_cmd.addr_high = upper_32_bits(phys_addr); 4258 sata_cmd.esgl = cpu_to_le32(1 << 31); 4259 } else if (task->num_scatter == 1) { 4260 u64 dma_addr = sg_dma_address(task->scatter); 4261 sata_cmd.addr_low = lower_32_bits(dma_addr); 4262 sata_cmd.addr_high = upper_32_bits(dma_addr); 4263 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4264 sata_cmd.esgl = 0; 4265 } else if (task->num_scatter == 0) { 4266 sata_cmd.addr_low = 0; 4267 sata_cmd.addr_high = 0; 4268 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4269 sata_cmd.esgl = 0; 4270 } 4271 4272 /* Check for read log for failed drive and return */ 4273 if (sata_cmd.sata_fis.command == 0x2f) { 4274 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4275 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4276 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4277 struct task_status_struct *ts; 4278 4279 pm8001_ha_dev->id &= 0xDFFFFFFF; 4280 ts = &task->task_status; 4281 4282 spin_lock_irqsave(&task->task_state_lock, flags); 4283 ts->resp = SAS_TASK_COMPLETE; 4284 ts->stat = SAM_STAT_GOOD; 4285 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4286 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4287 task->task_state_flags |= SAS_TASK_STATE_DONE; 4288 if (unlikely((task->task_state_flags & 4289 SAS_TASK_STATE_ABORTED))) { 4290 spin_unlock_irqrestore(&task->task_state_lock, 4291 flags); 4292 pm8001_dbg(pm8001_ha, FAIL, 4293 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 4294 task, ts->resp, 4295 ts->stat); 4296 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4297 } else { 4298 spin_unlock_irqrestore(&task->task_state_lock, 4299 flags); 4300 pm8001_ccb_task_free_done(pm8001_ha, task, 4301 ccb, tag); 4302 return 0; 4303 } 4304 } 4305 } 4306 4307 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 4308 sizeof(sata_cmd), 0); 4309 return ret; 4310 } 4311 4312 /** 4313 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4314 * @pm8001_ha: our hba card information. 4315 * @phy_id: the phy id which we wanted to start up. 4316 */ 4317 static int 4318 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4319 { 4320 struct phy_start_req payload; 4321 struct inbound_queue_table *circularQ; 4322 int ret; 4323 u32 tag = 0x01; 4324 u32 opcode = OPC_INB_PHYSTART; 4325 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4326 memset(&payload, 0, sizeof(payload)); 4327 payload.tag = cpu_to_le32(tag); 4328 /* 4329 ** [0:7] PHY Identifier 4330 ** [8:11] link rate 1.5G, 3G, 6G 4331 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4332 ** [14] 0b disable spin up hold; 1b enable spin up hold 4333 */ 4334 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4335 LINKMODE_AUTO | LINKRATE_15 | 4336 LINKRATE_30 | LINKRATE_60 | phy_id); 4337 payload.sas_identify.dev_type = SAS_END_DEVICE; 4338 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4339 memcpy(payload.sas_identify.sas_addr, 4340 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4341 payload.sas_identify.phy_id = phy_id; 4342 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4343 sizeof(payload), 0); 4344 return ret; 4345 } 4346 4347 /** 4348 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4349 * @pm8001_ha: our hba card information. 4350 * @phy_id: the phy id which we wanted to start up. 4351 */ 4352 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4353 u8 phy_id) 4354 { 4355 struct phy_stop_req payload; 4356 struct inbound_queue_table *circularQ; 4357 int ret; 4358 u32 tag = 0x01; 4359 u32 opcode = OPC_INB_PHYSTOP; 4360 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4361 memset(&payload, 0, sizeof(payload)); 4362 payload.tag = cpu_to_le32(tag); 4363 payload.phy_id = cpu_to_le32(phy_id); 4364 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4365 sizeof(payload), 0); 4366 return ret; 4367 } 4368 4369 /* 4370 * see comments on pm8001_mpi_reg_resp. 4371 */ 4372 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4373 struct pm8001_device *pm8001_dev, u32 flag) 4374 { 4375 struct reg_dev_req payload; 4376 u32 opc; 4377 u32 stp_sspsmp_sata = 0x4; 4378 struct inbound_queue_table *circularQ; 4379 u32 linkrate, phy_id; 4380 int rc, tag = 0xdeadbeef; 4381 struct pm8001_ccb_info *ccb; 4382 u8 retryFlag = 0x1; 4383 u16 firstBurstSize = 0; 4384 u16 ITNT = 2000; 4385 struct domain_device *dev = pm8001_dev->sas_device; 4386 struct domain_device *parent_dev = dev->parent; 4387 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4388 4389 memset(&payload, 0, sizeof(payload)); 4390 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4391 if (rc) 4392 return rc; 4393 ccb = &pm8001_ha->ccb_info[tag]; 4394 ccb->device = pm8001_dev; 4395 ccb->ccb_tag = tag; 4396 payload.tag = cpu_to_le32(tag); 4397 if (flag == 1) 4398 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4399 else { 4400 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4401 stp_sspsmp_sata = 0x00; /* stp*/ 4402 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4403 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4404 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4405 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4406 } 4407 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4408 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4409 else 4410 phy_id = pm8001_dev->attached_phy; 4411 opc = OPC_INB_REG_DEV; 4412 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4413 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4414 payload.phyid_portid = 4415 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4416 ((phy_id & 0x0F) << 4)); 4417 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4418 ((linkrate & 0x0F) * 0x1000000) | 4419 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4420 payload.firstburstsize_ITNexustimeout = 4421 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4422 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4423 SAS_ADDR_SIZE); 4424 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4425 sizeof(payload), 0); 4426 return rc; 4427 } 4428 4429 /* 4430 * see comments on pm8001_mpi_reg_resp. 4431 */ 4432 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4433 u32 device_id) 4434 { 4435 struct dereg_dev_req payload; 4436 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4437 int ret; 4438 struct inbound_queue_table *circularQ; 4439 4440 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4441 memset(&payload, 0, sizeof(payload)); 4442 payload.tag = cpu_to_le32(1); 4443 payload.device_id = cpu_to_le32(device_id); 4444 pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n", 4445 device_id); 4446 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4447 sizeof(payload), 0); 4448 return ret; 4449 } 4450 4451 /** 4452 * pm8001_chip_phy_ctl_req - support the local phy operation 4453 * @pm8001_ha: our hba card information. 4454 * @phyId: the phy id which we wanted to operate 4455 * @phy_op: the phy operation to request 4456 */ 4457 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4458 u32 phyId, u32 phy_op) 4459 { 4460 struct local_phy_ctl_req payload; 4461 struct inbound_queue_table *circularQ; 4462 int ret; 4463 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4464 memset(&payload, 0, sizeof(payload)); 4465 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4466 payload.tag = cpu_to_le32(1); 4467 payload.phyop_phyid = 4468 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4469 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4470 sizeof(payload), 0); 4471 return ret; 4472 } 4473 4474 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4475 { 4476 #ifdef PM8001_USE_MSIX 4477 return 1; 4478 #else 4479 u32 value; 4480 4481 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4482 if (value) 4483 return 1; 4484 return 0; 4485 #endif 4486 } 4487 4488 /** 4489 * pm8001_chip_isr - PM8001 isr handler. 4490 * @pm8001_ha: our hba card information. 4491 * @vec: IRQ number 4492 */ 4493 static irqreturn_t 4494 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4495 { 4496 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4497 pm8001_dbg(pm8001_ha, DEVIO, 4498 "irq vec %d, ODMR:0x%x\n", 4499 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4500 process_oq(pm8001_ha, vec); 4501 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4502 return IRQ_HANDLED; 4503 } 4504 4505 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4506 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4507 { 4508 struct task_abort_req task_abort; 4509 struct inbound_queue_table *circularQ; 4510 int ret; 4511 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4512 memset(&task_abort, 0, sizeof(task_abort)); 4513 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4514 task_abort.abort_all = 0; 4515 task_abort.device_id = cpu_to_le32(dev_id); 4516 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4517 task_abort.tag = cpu_to_le32(cmd_tag); 4518 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4519 task_abort.abort_all = cpu_to_le32(1); 4520 task_abort.device_id = cpu_to_le32(dev_id); 4521 task_abort.tag = cpu_to_le32(cmd_tag); 4522 } 4523 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 4524 sizeof(task_abort), 0); 4525 return ret; 4526 } 4527 4528 /* 4529 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4530 */ 4531 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4532 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4533 { 4534 u32 opc, device_id; 4535 int rc = TMF_RESP_FUNC_FAILED; 4536 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n", 4537 cmd_tag, task_tag); 4538 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4539 opc = OPC_INB_SSP_ABORT; 4540 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4541 opc = OPC_INB_SATA_ABORT; 4542 else 4543 opc = OPC_INB_SMP_ABORT;/* SMP */ 4544 device_id = pm8001_dev->device_id; 4545 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4546 task_tag, cmd_tag); 4547 if (rc != TMF_RESP_FUNC_COMPLETE) 4548 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc); 4549 return rc; 4550 } 4551 4552 /** 4553 * pm8001_chip_ssp_tm_req - built the task management command. 4554 * @pm8001_ha: our hba card information. 4555 * @ccb: the ccb information. 4556 * @tmf: task management function. 4557 */ 4558 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4559 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4560 { 4561 struct sas_task *task = ccb->task; 4562 struct domain_device *dev = task->dev; 4563 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4564 u32 opc = OPC_INB_SSPINITMSTART; 4565 struct inbound_queue_table *circularQ; 4566 struct ssp_ini_tm_start_req sspTMCmd; 4567 int ret; 4568 4569 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4570 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4571 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4572 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4573 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4574 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4575 if (pm8001_ha->chip_id != chip_8001) 4576 sspTMCmd.ds_ads_m = 0x08; 4577 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4578 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 4579 sizeof(sspTMCmd), 0); 4580 return ret; 4581 } 4582 4583 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4584 void *payload) 4585 { 4586 u32 opc = OPC_INB_GET_NVMD_DATA; 4587 u32 nvmd_type; 4588 int rc; 4589 u32 tag; 4590 struct pm8001_ccb_info *ccb; 4591 struct inbound_queue_table *circularQ; 4592 struct get_nvm_data_req nvmd_req; 4593 struct fw_control_ex *fw_control_context; 4594 struct pm8001_ioctl_payload *ioctl_payload = payload; 4595 4596 nvmd_type = ioctl_payload->minor_function; 4597 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4598 if (!fw_control_context) 4599 return -ENOMEM; 4600 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4601 fw_control_context->len = ioctl_payload->rd_length; 4602 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4603 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4604 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4605 if (rc) { 4606 kfree(fw_control_context); 4607 return rc; 4608 } 4609 ccb = &pm8001_ha->ccb_info[tag]; 4610 ccb->ccb_tag = tag; 4611 ccb->fw_control_context = fw_control_context; 4612 nvmd_req.tag = cpu_to_le32(tag); 4613 4614 switch (nvmd_type) { 4615 case TWI_DEVICE: { 4616 u32 twi_addr, twi_page_size; 4617 twi_addr = 0xa8; 4618 twi_page_size = 2; 4619 4620 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4621 twi_page_size << 8 | TWI_DEVICE); 4622 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4623 nvmd_req.resp_addr_hi = 4624 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4625 nvmd_req.resp_addr_lo = 4626 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4627 break; 4628 } 4629 case C_SEEPROM: { 4630 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4631 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4632 nvmd_req.resp_addr_hi = 4633 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4634 nvmd_req.resp_addr_lo = 4635 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4636 break; 4637 } 4638 case VPD_FLASH: { 4639 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4640 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4641 nvmd_req.resp_addr_hi = 4642 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4643 nvmd_req.resp_addr_lo = 4644 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4645 break; 4646 } 4647 case EXPAN_ROM: { 4648 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4649 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4650 nvmd_req.resp_addr_hi = 4651 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4652 nvmd_req.resp_addr_lo = 4653 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4654 break; 4655 } 4656 case IOP_RDUMP: { 4657 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4658 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4659 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4660 nvmd_req.resp_addr_hi = 4661 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4662 nvmd_req.resp_addr_lo = 4663 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4664 break; 4665 } 4666 default: 4667 break; 4668 } 4669 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4670 sizeof(nvmd_req), 0); 4671 if (rc) { 4672 kfree(fw_control_context); 4673 pm8001_tag_free(pm8001_ha, tag); 4674 } 4675 return rc; 4676 } 4677 4678 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4679 void *payload) 4680 { 4681 u32 opc = OPC_INB_SET_NVMD_DATA; 4682 u32 nvmd_type; 4683 int rc; 4684 u32 tag; 4685 struct pm8001_ccb_info *ccb; 4686 struct inbound_queue_table *circularQ; 4687 struct set_nvm_data_req nvmd_req; 4688 struct fw_control_ex *fw_control_context; 4689 struct pm8001_ioctl_payload *ioctl_payload = payload; 4690 4691 nvmd_type = ioctl_payload->minor_function; 4692 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4693 if (!fw_control_context) 4694 return -ENOMEM; 4695 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4696 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4697 &ioctl_payload->func_specific, 4698 ioctl_payload->wr_length); 4699 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4700 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4701 if (rc) { 4702 kfree(fw_control_context); 4703 return -EBUSY; 4704 } 4705 ccb = &pm8001_ha->ccb_info[tag]; 4706 ccb->fw_control_context = fw_control_context; 4707 ccb->ccb_tag = tag; 4708 nvmd_req.tag = cpu_to_le32(tag); 4709 switch (nvmd_type) { 4710 case TWI_DEVICE: { 4711 u32 twi_addr, twi_page_size; 4712 twi_addr = 0xa8; 4713 twi_page_size = 2; 4714 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4715 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4716 twi_page_size << 8 | TWI_DEVICE); 4717 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4718 nvmd_req.resp_addr_hi = 4719 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4720 nvmd_req.resp_addr_lo = 4721 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4722 break; 4723 } 4724 case C_SEEPROM: 4725 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4726 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4727 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4728 nvmd_req.resp_addr_hi = 4729 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4730 nvmd_req.resp_addr_lo = 4731 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4732 break; 4733 case VPD_FLASH: 4734 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4735 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4736 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4737 nvmd_req.resp_addr_hi = 4738 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4739 nvmd_req.resp_addr_lo = 4740 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4741 break; 4742 case EXPAN_ROM: 4743 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4744 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4745 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4746 nvmd_req.resp_addr_hi = 4747 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4748 nvmd_req.resp_addr_lo = 4749 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4750 break; 4751 default: 4752 break; 4753 } 4754 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4755 sizeof(nvmd_req), 0); 4756 if (rc) { 4757 kfree(fw_control_context); 4758 pm8001_tag_free(pm8001_ha, tag); 4759 } 4760 return rc; 4761 } 4762 4763 /** 4764 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4765 * @pm8001_ha: our hba card information. 4766 * @fw_flash_updata_info: firmware flash update param 4767 * @tag: Tag to apply to the payload 4768 */ 4769 int 4770 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4771 void *fw_flash_updata_info, u32 tag) 4772 { 4773 struct fw_flash_Update_req payload; 4774 struct fw_flash_updata_info *info; 4775 struct inbound_queue_table *circularQ; 4776 int ret; 4777 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4778 4779 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4780 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4781 info = fw_flash_updata_info; 4782 payload.tag = cpu_to_le32(tag); 4783 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4784 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4785 payload.total_image_len = cpu_to_le32(info->total_image_len); 4786 payload.len = info->sgl.im_len.len ; 4787 payload.sgl_addr_lo = 4788 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4789 payload.sgl_addr_hi = 4790 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4791 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4792 sizeof(payload), 0); 4793 return ret; 4794 } 4795 4796 int 4797 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4798 void *payload) 4799 { 4800 struct fw_flash_updata_info flash_update_info; 4801 struct fw_control_info *fw_control; 4802 struct fw_control_ex *fw_control_context; 4803 int rc; 4804 u32 tag; 4805 struct pm8001_ccb_info *ccb; 4806 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 4807 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 4808 struct pm8001_ioctl_payload *ioctl_payload = payload; 4809 4810 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4811 if (!fw_control_context) 4812 return -ENOMEM; 4813 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 4814 pm8001_dbg(pm8001_ha, DEVIO, 4815 "dma fw_control context input length :%x\n", 4816 fw_control->len); 4817 memcpy(buffer, fw_control->buffer, fw_control->len); 4818 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4819 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4820 flash_update_info.sgl.im_len.e = 0; 4821 flash_update_info.cur_image_offset = fw_control->offset; 4822 flash_update_info.cur_image_len = fw_control->len; 4823 flash_update_info.total_image_len = fw_control->size; 4824 fw_control_context->fw_control = fw_control; 4825 fw_control_context->virtAddr = buffer; 4826 fw_control_context->phys_addr = phys_addr; 4827 fw_control_context->len = fw_control->len; 4828 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4829 if (rc) { 4830 kfree(fw_control_context); 4831 return -EBUSY; 4832 } 4833 ccb = &pm8001_ha->ccb_info[tag]; 4834 ccb->fw_control_context = fw_control_context; 4835 ccb->ccb_tag = tag; 4836 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4837 tag); 4838 return rc; 4839 } 4840 4841 ssize_t 4842 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 4843 { 4844 u32 value, rem, offset = 0, bar = 0; 4845 u32 index, work_offset, dw_length; 4846 u32 shift_value, gsm_base, gsm_dump_offset; 4847 char *direct_data; 4848 struct Scsi_Host *shost = class_to_shost(cdev); 4849 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4850 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 4851 4852 direct_data = buf; 4853 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 4854 4855 /* check max is 1 Mbytes */ 4856 if ((length > 0x100000) || (gsm_dump_offset & 3) || 4857 ((gsm_dump_offset + length) > 0x1000000)) 4858 return -EINVAL; 4859 4860 if (pm8001_ha->chip_id == chip_8001) 4861 bar = 2; 4862 else 4863 bar = 1; 4864 4865 work_offset = gsm_dump_offset & 0xFFFF0000; 4866 offset = gsm_dump_offset & 0x0000FFFF; 4867 gsm_dump_offset = work_offset; 4868 /* adjust length to dword boundary */ 4869 rem = length & 3; 4870 dw_length = length >> 2; 4871 4872 for (index = 0; index < dw_length; index++) { 4873 if ((work_offset + offset) & 0xFFFF0000) { 4874 if (pm8001_ha->chip_id == chip_8001) 4875 shift_value = ((gsm_dump_offset + offset) & 4876 SHIFT_REG_64K_MASK); 4877 else 4878 shift_value = (((gsm_dump_offset + offset) & 4879 SHIFT_REG_64K_MASK) >> 4880 SHIFT_REG_BIT_SHIFT); 4881 4882 if (pm8001_ha->chip_id == chip_8001) { 4883 gsm_base = GSM_BASE; 4884 if (-1 == pm8001_bar4_shift(pm8001_ha, 4885 (gsm_base + shift_value))) 4886 return -EIO; 4887 } else { 4888 gsm_base = 0; 4889 if (-1 == pm80xx_bar4_shift(pm8001_ha, 4890 (gsm_base + shift_value))) 4891 return -EIO; 4892 } 4893 gsm_dump_offset = (gsm_dump_offset + offset) & 4894 0xFFFF0000; 4895 work_offset = 0; 4896 offset = offset & 0x0000FFFF; 4897 } 4898 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4899 0x0000FFFF); 4900 direct_data += sprintf(direct_data, "%08x ", value); 4901 offset += 4; 4902 } 4903 if (rem != 0) { 4904 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4905 0x0000FFFF); 4906 /* xfr for non_dw */ 4907 direct_data += sprintf(direct_data, "%08x ", value); 4908 } 4909 /* Shift back to BAR4 original address */ 4910 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 4911 return -EIO; 4912 pm8001_ha->fatal_forensic_shift_offset += 1024; 4913 4914 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 4915 pm8001_ha->fatal_forensic_shift_offset = 0; 4916 return direct_data - buf; 4917 } 4918 4919 int 4920 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 4921 struct pm8001_device *pm8001_dev, u32 state) 4922 { 4923 struct set_dev_state_req payload; 4924 struct inbound_queue_table *circularQ; 4925 struct pm8001_ccb_info *ccb; 4926 int rc; 4927 u32 tag; 4928 u32 opc = OPC_INB_SET_DEVICE_STATE; 4929 memset(&payload, 0, sizeof(payload)); 4930 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4931 if (rc) 4932 return -1; 4933 ccb = &pm8001_ha->ccb_info[tag]; 4934 ccb->ccb_tag = tag; 4935 ccb->device = pm8001_dev; 4936 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4937 payload.tag = cpu_to_le32(tag); 4938 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 4939 payload.nds = cpu_to_le32(state); 4940 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4941 sizeof(payload), 0); 4942 return rc; 4943 4944 } 4945 4946 static int 4947 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 4948 { 4949 struct sas_re_initialization_req payload; 4950 struct inbound_queue_table *circularQ; 4951 struct pm8001_ccb_info *ccb; 4952 int rc; 4953 u32 tag; 4954 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 4955 memset(&payload, 0, sizeof(payload)); 4956 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4957 if (rc) 4958 return -ENOMEM; 4959 ccb = &pm8001_ha->ccb_info[tag]; 4960 ccb->ccb_tag = tag; 4961 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4962 payload.tag = cpu_to_le32(tag); 4963 payload.SSAHOLT = cpu_to_le32(0xd << 25); 4964 payload.sata_hol_tmo = cpu_to_le32(80); 4965 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 4966 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4967 sizeof(payload), 0); 4968 if (rc) 4969 pm8001_tag_free(pm8001_ha, tag); 4970 return rc; 4971 4972 } 4973 4974 const struct pm8001_dispatch pm8001_8001_dispatch = { 4975 .name = "pmc8001", 4976 .chip_init = pm8001_chip_init, 4977 .chip_soft_rst = pm8001_chip_soft_rst, 4978 .chip_rst = pm8001_hw_chip_rst, 4979 .chip_iounmap = pm8001_chip_iounmap, 4980 .isr = pm8001_chip_isr, 4981 .is_our_interrupt = pm8001_chip_is_our_interrupt, 4982 .isr_process_oq = process_oq, 4983 .interrupt_enable = pm8001_chip_interrupt_enable, 4984 .interrupt_disable = pm8001_chip_interrupt_disable, 4985 .make_prd = pm8001_chip_make_sg, 4986 .smp_req = pm8001_chip_smp_req, 4987 .ssp_io_req = pm8001_chip_ssp_io_req, 4988 .sata_req = pm8001_chip_sata_req, 4989 .phy_start_req = pm8001_chip_phy_start_req, 4990 .phy_stop_req = pm8001_chip_phy_stop_req, 4991 .reg_dev_req = pm8001_chip_reg_dev_req, 4992 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4993 .phy_ctl_req = pm8001_chip_phy_ctl_req, 4994 .task_abort = pm8001_chip_abort_task, 4995 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4996 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4997 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4998 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4999 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5000 .sas_re_init_req = pm8001_chip_sas_re_initialization, 5001 }; 5002