1 /* 2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver 3 * Basic data header 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _NSP32_H 17 #define _NSP32_H 18 19 //#define NSP32_DEBUG 9 20 21 /* 22 * VENDOR/DEVICE ID 23 */ 24 #define PCI_VENDOR_ID_IODATA 0x10fc 25 #define PCI_VENDOR_ID_WORKBIT 0x1145 26 27 #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005 28 #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007 29 #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007 30 #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010 31 #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011 32 #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012 33 #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013 34 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015 35 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009 36 37 /* 38 * MODEL 39 */ 40 enum { 41 MODEL_IODATA = 0, 42 MODEL_KME = 1, 43 MODEL_WORKBIT = 2, 44 MODEL_LOGITEC = 3, 45 MODEL_PCI_WORKBIT = 4, 46 MODEL_PCI_LOGITEC = 5, 47 MODEL_PCI_MELCO = 6, 48 }; 49 50 static char * nsp32_model[] = { 51 "I-O DATA CBSC-II CardBus card", 52 "KME SCSI CardBus card", 53 "Workbit duo SCSI CardBus card", 54 "Logitec CardBus card with external ROM", 55 "Workbit / I-O DATA PCI card", 56 "Logitec PCI card with external ROM", 57 "Melco CardBus/PCI card with external ROM", 58 }; 59 60 61 /* 62 * SCSI Generic Definitions 63 */ 64 #define EXTENDED_SDTR_LEN 0x03 65 66 /* Little Endian */ 67 typedef u32 u32_le; 68 typedef u16 u16_le; 69 70 /* 71 * BASIC Definitions 72 */ 73 #ifndef TRUE 74 # define TRUE 1 75 #endif 76 #ifndef FALSE 77 # define FALSE 0 78 #endif 79 #define ASSERT 1 80 #define NEGATE 0 81 82 83 /*******************/ 84 /* normal register */ 85 /*******************/ 86 /* 87 * Don't access below register with Double Word: 88 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0. 89 */ 90 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */ 91 #define IRQ_STATUS 0x00 /* BASE+00, W, R */ 92 # define IRQSTATUS_LATCHED_MSG BIT(0) 93 # define IRQSTATUS_LATCHED_IO BIT(1) 94 # define IRQSTATUS_LATCHED_CD BIT(2) 95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3) 96 # define IRQSTATUS_RESELECT_OCCUER BIT(4) 97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5) 98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6) 99 # define IRQSTATUS_TIMER_IRQ BIT(7) 100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8) 101 # define IRQSTATUS_PCI_IRQ BIT(9) 102 # define IRQSTATUS_BMCNTERR_IRQ BIT(10) 103 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11) 104 # define PCI_IRQ_MASK BIT(12) 105 # define TIMER_IRQ_MASK BIT(13) 106 # define FIFO_IRQ_MASK BIT(14) 107 # define SCSI_IRQ_MASK BIT(15) 108 # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \ 109 TIMER_IRQ_MASK | \ 110 FIFO_IRQ_MASK | \ 111 SCSI_IRQ_MASK ) 112 # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \ 113 IRQSTATUS_PHASE_CHANGE_IRQ | \ 114 IRQSTATUS_SCSIRESET_IRQ | \ 115 IRQSTATUS_TIMER_IRQ | \ 116 IRQSTATUS_FIFO_SHLD_IRQ | \ 117 IRQSTATUS_PCI_IRQ | \ 118 IRQSTATUS_BMCNTERR_IRQ | \ 119 IRQSTATUS_AUTOSCSI_IRQ ) 120 121 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */ 122 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */ 123 # define CB_MMIO_MODE BIT(0) 124 # define CB_IO_MODE BIT(1) 125 # define BM_TEST BIT(2) 126 # define BM_TEST_DIR BIT(3) 127 # define DUAL_EDGE_ENABLE BIT(4) 128 # define NO_TRANSFER_TO_HOST BIT(5) 129 # define TRANSFER_GO BIT(7) 130 # define BLIEND_MODE BIT(8) 131 # define BM_START BIT(9) 132 # define ADVANCED_BM_WRITE BIT(10) 133 # define BM_SINGLE_MODE BIT(11) 134 # define FIFO_TRUE_FULL BIT(12) 135 # define FIFO_TRUE_EMPTY BIT(13) 136 # define ALL_COUNTER_CLR BIT(14) 137 # define FIFOTEST BIT(15) 138 139 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */ 140 141 #define TIMER_SET 0x06 /* BASE+06, W, R/W */ 142 # define TIMER_CNT_MASK (0xff) 143 # define TIMER_STOP BIT(8) 144 145 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */ 146 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */ 147 148 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */ 149 # define FIFO_REST_MASK 0x1ff 150 # define FIFO_EMPTY_SHLD_FLAG BIT(14) 151 # define FIFO_FULL_SHLD_FLAG BIT(15) 152 153 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */ 154 # define SREQSMPLRATE_RATE0 BIT(0) 155 # define SREQSMPLRATE_RATE1 BIT(1) 156 # define SAMPLING_ENABLE BIT(2) 157 # define SMPL_40M (0) /* 40MHz: 0-100ns/period */ 158 # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */ 159 # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */ 160 161 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */ 162 # define BUSCTL_SEL BIT(0) 163 # define BUSCTL_RST BIT(1) 164 # define BUSCTL_DATAOUT_ENB BIT(2) 165 # define BUSCTL_ATN BIT(3) 166 # define BUSCTL_ACK BIT(4) 167 # define BUSCTL_BSY BIT(5) 168 # define AUTODIRECTION BIT(6) 169 # define ACKENB BIT(7) 170 171 #define CLR_COUNTER 0x12 /* BASE+12, B, W */ 172 # define ACK_COUNTER_CLR BIT(0) 173 # define SREQ_COUNTER_CLR BIT(1) 174 # define FIFO_HOST_POINTER_CLR BIT(2) 175 # define FIFO_REST_COUNT_CLR BIT(3) 176 # define BM_COUNTER_CLR BIT(4) 177 # define SAVED_ACK_CLR BIT(5) 178 # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \ 179 SREQ_COUNTER_CLR | \ 180 FIFO_HOST_POINTER_CLR | \ 181 FIFO_REST_COUNT_CLR | \ 182 BM_COUNTER_CLR | \ 183 SAVED_ACK_CLR ) 184 185 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */ 186 # define BUSMON_MSG BIT(0) 187 # define BUSMON_IO BIT(1) 188 # define BUSMON_CD BIT(2) 189 # define BUSMON_BSY BIT(3) 190 # define BUSMON_ACK BIT(4) 191 # define BUSMON_REQ BIT(5) 192 # define BUSMON_SEL BIT(6) 193 # define BUSMON_ATN BIT(7) 194 195 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */ 196 197 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */ 198 # define PARITY_CHECK_ENABLE BIT(0) 199 # define PARITY_ERROR_CLEAR BIT(1) 200 #define PARITY_STATUS 0x16 /* BASE+16, B, R */ 201 //# define PARITY_CHECK_ENABLE BIT(0) 202 # define PARITY_ERROR_NORMAL BIT(1) 203 # define PARITY_ERROR_LSB BIT(1) 204 # define PARITY_ERROR_MSB BIT(2) 205 206 #define RESELECT_ID 0x18 /* BASE+18, B, R */ 207 208 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */ 209 # define CLEAR_CDB_FIFO_POINTER BIT(0) 210 # define AUTO_COMMAND_PHASE BIT(1) 211 # define AUTOSCSI_START BIT(2) 212 # define AUTOSCSI_RESTART BIT(3) 213 # define AUTO_PARAMETER BIT(4) 214 # define AUTO_ATN BIT(5) 215 # define AUTO_MSGIN_00_OR_04 BIT(6) 216 # define AUTO_MSGIN_02 BIT(7) 217 # define AUTO_MSGIN_03 BIT(8) 218 219 #define SET_ARBIT 0x1a /* BASE+1a, B, W */ 220 # define ARBIT_GO BIT(0) 221 # define ARBIT_CLEAR BIT(1) 222 223 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */ 224 //# define ARBIT_GO BIT(0) 225 # define ARBIT_WIN BIT(1) 226 # define ARBIT_FAIL BIT(2) 227 # define AUTO_PARAMETER_VALID BIT(3) 228 # define SGT_VALID BIT(4) 229 230 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */ 231 232 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */ 233 234 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */ 235 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */ 236 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */ 237 238 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */ 239 #define SCAM_STATUS 0x24 /* BASE+24, B, R */ 240 # define SCAM_MSG BIT(0) 241 # define SCAM_IO BIT(1) 242 # define SCAM_CD BIT(2) 243 # define SCAM_BSY BIT(3) 244 # define SCAM_SEL BIT(4) 245 # define SCAM_XFEROK BIT(5) 246 247 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */ 248 # define SD0 BIT(0) 249 # define SD1 BIT(1) 250 # define SD2 BIT(2) 251 # define SD3 BIT(3) 252 # define SD4 BIT(4) 253 # define SD5 BIT(5) 254 # define SD6 BIT(6) 255 # define SD7 BIT(7) 256 257 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */ 258 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */ 259 260 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */ 261 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */ 262 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */ 263 264 #define BM_CNT 0x38 /* BASE+38, DW, R/W */ 265 # define BM_COUNT_MASK 0x0001ffffUL 266 # define SGTEND BIT(31) /* Last SGT marker */ 267 268 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */ 269 #define WAIT_REG 0x40 /* Bi only */ 270 271 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */ 272 # define COMMAND_PHASE BIT(0) 273 # define DATA_IN_PHASE BIT(1) 274 # define DATA_OUT_PHASE BIT(2) 275 # define MSGOUT_PHASE BIT(3) 276 # define STATUS_PHASE BIT(4) 277 # define ILLEGAL_PHASE BIT(5) 278 # define BUS_FREE_OCCUER BIT(6) 279 # define MSG_IN_OCCUER BIT(7) 280 # define MSG_OUT_OCCUER BIT(8) 281 # define SELECTION_TIMEOUT BIT(9) 282 # define MSGIN_00_VALID BIT(10) 283 # define MSGIN_02_VALID BIT(11) 284 # define MSGIN_03_VALID BIT(12) 285 # define MSGIN_04_VALID BIT(13) 286 # define AUTOSCSI_BUSY BIT(15) 287 288 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */ 289 290 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */ 291 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1)) 292 # define MV_VALID BIT(7) 293 294 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */ 295 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */ 296 297 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */ 298 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */ 299 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */ 300 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */ 301 302 303 /********************/ 304 /* indexed register */ 305 /********************/ 306 307 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */ 308 # define CLOCK_2 BIT(0) /* MCLK/2 */ 309 # define CLOCK_4 BIT(1) /* MCLK/4 */ 310 # define PCICLK BIT(7) /* PCICLK (33MHz) */ 311 312 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */ 313 # define BPWR BIT(0) 314 # define SENSE BIT(1) /* Read Only */ 315 316 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */ 317 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */ 318 # define LED_ON (0) 319 # define LED_OFF BIT(0) 320 321 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */ 322 # define IRQSELECT_RESELECT_IRQ BIT(0) 323 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1) 324 # define IRQSELECT_SCSIRESET_IRQ BIT(2) 325 # define IRQSELECT_TIMER_IRQ BIT(3) 326 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4) 327 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5) 328 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6) 329 # define IRQSELECT_SERR_IRQ BIT(7) 330 # define IRQSELECT_PERR_IRQ BIT(8) 331 # define IRQSELECT_BMCNTERR_IRQ BIT(9) 332 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10) 333 334 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */ 335 # define OLD_MSG BIT(0) 336 # define OLD_IO BIT(1) 337 # define OLD_CD BIT(2) 338 # define OLD_BUSY BIT(3) 339 340 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */ 341 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */ 342 343 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */ 344 # define ROM_WRITE_ENB BIT(0) 345 # define IO_ACCESS_ENB BIT(1) 346 # define ROM_ADR_CLEAR BIT(2) 347 348 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */ 349 350 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */ 351 352 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */ 353 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */ 354 # define OEM1 BIT(2) /* OEM select */ 355 # define OPTB BIT(3) /* KME mode select */ 356 # define OPTC BIT(4) /* KME mode select */ 357 # define OPTD BIT(5) /* KME mode select */ 358 # define OPTE BIT(6) /* KME mode select */ 359 # define OPTF BIT(7) /* Power management */ 360 361 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */ 362 #define MISC_RD 0x0c 363 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0) 364 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */ 365 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */ 366 # define DELAYED_BMSTART BIT(3) 367 # define MASTER_TERMINATION_SELECT BIT(4) 368 # define BMREQ_NEGATE_TIMING_SEL BIT(5) 369 # define AUTOSEL_TIMING_SEL BIT(6) 370 # define MISC_MABORT_MASK BIT(7) 371 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8) 372 373 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */ 374 # define BM_CYCLE0 BIT(0) 375 # define BM_CYCLE1 BIT(1) 376 # define BM_FRAME_ASSERT_TIMING BIT(2) 377 # define BM_IRDY_ASSERT_TIMING BIT(3) 378 # define BM_SINGLE_BUS_MASTER BIT(4) 379 # define MEMRD_CMD0 BIT(5) 380 # define SGT_AUTO_PARA_MEMED_CMD BIT(6) 381 # define MEMRD_CMD1 BIT(7) 382 383 384 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */ 385 # define SREQ_EDGH_SELECT BIT(0) 386 387 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */ 388 # define REQCNT_UP BIT(0) 389 # define ACKCNT_UP BIT(1) 390 # define BMADR_UP BIT(4) 391 # define BMCNT_UP BIT(5) 392 # define SGT_CNT_UP BIT(7) 393 394 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */ 395 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */ 396 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */ 397 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */ 398 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */ 399 400 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */ 401 # define SCL BIT(0) 402 # define ENA BIT(1) 403 # define SDA BIT(2) 404 405 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */ 406 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */ 407 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */ 408 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */ 409 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */ 410 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */ 411 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */ 412 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */ 413 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */ 414 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */ 415 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */ 416 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */ 417 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */ 418 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */ 419 420 421 /* 422 * Useful Bus Monitor status combinations. 423 */ 424 #define BUSMON_BUS_FREE 0 425 #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ ) 426 #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) 427 #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ ) 428 #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ ) 429 #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ ) 430 #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) 431 #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL) 432 #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL) 433 434 #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK ) 435 #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK ) 436 #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK ) 437 #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK ) 438 #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK ) 439 #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK ) 440 #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO ) 441 442 443 /************************************************************************ 444 * structure for DMA/Scatter Gather list 445 */ 446 #define NSP32_SG_SIZE SG_ALL 447 448 typedef struct _nsp32_sgtable { 449 /* values must be little endian */ 450 u32_le addr; /* transfer address */ 451 u32_le len; /* transfer length. BIT(31) is for SGT_END mark */ 452 } __attribute__ ((packed)) nsp32_sgtable; 453 454 typedef struct _nsp32_sglun { 455 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */ 456 } __attribute__ ((packed)) nsp32_sglun; 457 #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN) 458 459 /* Auto parameter mode memory map. */ 460 /* All values must be little endian. */ 461 typedef struct _nsp32_autoparam { 462 u8 cdb[4 * 0x10]; /* SCSI Command */ 463 u32_le msgout; /* outgoing messages */ 464 u8 syncreg; /* sync register value */ 465 u8 ackwidth; /* ack width register value */ 466 u8 target_id; /* target/host device id */ 467 u8 sample_reg; /* hazard killer sampling rate */ 468 u16_le command_control; /* command control register */ 469 u16_le transfer_control; /* transfer control register */ 470 u32_le sgt_pointer; /* SG table physical address for DMA */ 471 u32_le dummy[2]; 472 } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */ 473 474 /* 475 * host data structure 476 */ 477 /* message in/out buffer */ 478 #define MSGOUTBUF_MAX 20 479 #define MSGINBUF_MAX 20 480 481 /* flag for trans_method */ 482 #define NSP32_TRANSFER_BUSMASTER BIT(0) 483 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */ 484 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */ 485 486 487 /* 488 * structure for connected LUN dynamic data 489 * 490 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds 491 * one SCSI command and one state. 492 */ 493 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */ 494 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */ 495 496 typedef struct _nsp32_lunt { 497 struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */ 498 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */ 499 int msgin03; /* auto msg in 03 flag */ 500 unsigned int sg_num; /* Total number of SG entries */ 501 int cur_entry; /* Current SG entry number */ 502 nsp32_sglun *sglun; /* sg table per lun */ 503 dma_addr_t sglun_paddr; /* sglun physical address */ 504 } nsp32_lunt; 505 506 507 /* 508 * SCSI TARGET/LUN definition 509 */ 510 #define NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */ 511 #define MAX_TARGET 8 512 #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */ 513 514 515 typedef struct _nsp32_sync_table { 516 unsigned char period_num; /* period number */ 517 unsigned char ackwidth; /* ack width designated by period */ 518 unsigned char start_period; /* search range - start period */ 519 unsigned char end_period; /* search range - end period */ 520 unsigned char sample_rate; /* hazard killer parameter */ 521 } nsp32_sync_table; 522 523 524 /* 525 * structure for target device static data 526 */ 527 /* flag for nsp32_target.sync_flag */ 528 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */ 529 #define SDTR_TARGET BIT(1) /* sending SDTR from target */ 530 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */ 531 532 /* syncronous period value for nsp32_target.config_max */ 533 #define FAST5M 0x32 534 #define FAST10M 0x19 535 #define ULTRA20M 0x0c 536 537 /* flag for nsp32_target.{sync_offset}, period */ 538 #define ASYNC_OFFSET 0 /* asynchronous transfer */ 539 #define SYNC_OFFSET 0xf /* synchronous transfer max offset */ 540 541 /* syncreg: 542 bit:07 06 05 04 03 02 01 00 543 ---PERIOD-- ---OFFSET-- */ 544 #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f)) 545 546 typedef struct _nsp32_target { 547 unsigned char syncreg; /* value for SYNCREG */ 548 unsigned char ackwidth; /* value for ACKWIDTH */ 549 unsigned char period; /* sync period (0-255) */ 550 unsigned char offset; /* sync offset (0-15) */ 551 int sync_flag; /* SDTR_*, 0 */ 552 int limit_entry; /* max speed limit entry designated 553 by EEPROM configuration */ 554 unsigned char sample_reg; /* SREQ hazard killer register */ 555 } nsp32_target; 556 557 typedef struct _nsp32_hw_data { 558 int IrqNumber; 559 int BaseAddress; 560 int NumAddress; 561 void __iomem *MmioAddress; 562 #define NSP32_MMIO_OFFSET 0x0800 563 unsigned long MmioLength; 564 565 struct scsi_cmnd *CurrentSC; 566 567 struct pci_dev *Pci; 568 const struct pci_device_id *pci_devid; 569 struct Scsi_Host *Host; 570 spinlock_t Lock; 571 572 char info_str[100]; 573 574 /* allocated memory region */ 575 nsp32_sglun *sg_list; /* sglist virtuxal address */ 576 dma_addr_t sg_paddr; /* physical address of hw_sg_table */ 577 nsp32_autoparam *autoparam; /* auto parameter transfer region */ 578 dma_addr_t auto_paddr; /* physical address of autoparam */ 579 int cur_entry; /* current sgt entry */ 580 581 /* target/LUN */ 582 nsp32_lunt *cur_lunt; /* Current connected LUN table */ 583 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */ 584 585 nsp32_target *cur_target; /* Current connected SCSI ID */ 586 nsp32_target target[MAX_TARGET]; /* SCSI ID */ 587 int cur_id; /* Current connected target ID */ 588 int cur_lun; /* Current connected target LUN */ 589 590 /* behavior setting parameters */ 591 int trans_method; /* transfer method flag */ 592 int resettime; /* Reset time */ 593 int clock; /* clock dividing flag */ 594 nsp32_sync_table *synct; /* sync_table determined by clock */ 595 int syncnum; /* the max number of synct element */ 596 597 /* message buffer */ 598 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */ 599 char msgout_len; /* msgoutbuf length */ 600 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */ 601 char msgin_len; /* msginbuf length */ 602 603 } nsp32_hw_data; 604 605 /* 606 * TIME definition 607 */ 608 #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the 609 minimum is 25us) */ 610 #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification 611 (25.6us/1unit) */ 612 #define ARBIT_TIMEOUT_TIME 100 /* 100us */ 613 #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion 614 or negation, 10000us == 10ms */ 615 616 #endif /* _NSP32_H */ 617 /* end */ 618