1 /* 2 * Marvell 88SE64xx/88SE94xx main function head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 #ifndef _MV_SAS_H_ 27 #define _MV_SAS_H_ 28 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/spinlock.h> 32 #include <linux/delay.h> 33 #include <linux/types.h> 34 #include <linux/ctype.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/pci.h> 37 #include <linux/platform_device.h> 38 #include <linux/interrupt.h> 39 #include <linux/irq.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <asm/unaligned.h> 43 #include <scsi/libsas.h> 44 #include <scsi/scsi.h> 45 #include <scsi/scsi_tcq.h> 46 #include <scsi/sas_ata.h> 47 #include "mv_defs.h" 48 49 #define DRV_NAME "mvsas" 50 #define DRV_VERSION "0.8.16" 51 #define MVS_ID_NOT_MAPPED 0x7f 52 #define WIDE_PORT_MAX_PHY 4 53 #define mv_printk(fmt, arg ...) \ 54 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 55 #ifdef MV_DEBUG 56 #define mv_dprintk(format, arg...) \ 57 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 58 #else 59 #define mv_dprintk(format, arg...) 60 #endif 61 #define MV_MAX_U32 0xffffffff 62 63 extern int interrupt_coalescing; 64 extern struct mvs_tgt_initiator mvs_tgt; 65 extern struct mvs_info *tgt_mvi; 66 extern const struct mvs_dispatch mvs_64xx_dispatch; 67 extern const struct mvs_dispatch mvs_94xx_dispatch; 68 extern struct kmem_cache *mvs_task_list_cache; 69 70 #define DEV_IS_EXPANDER(type) \ 71 ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE)) 72 73 #define bit(n) ((u64)1 << n) 74 75 #define for_each_phy(__lseq_mask, __mc, __lseq) \ 76 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 77 (__mc) != 0 ; \ 78 (++__lseq), (__mc) >>= 1) 79 80 #define MVS_PHY_ID (1U << sas_phy->id) 81 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 82 #define UNASSOC_D2H_FIS(id) \ 83 ((void *) mvi->rx_fis + 0x100 * id) 84 #define SATA_RECEIVED_FIS_LIST(reg_set) \ 85 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 86 #define SATA_RECEIVED_SDB_FIS(reg_set) \ 87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 88 #define SATA_RECEIVED_D2H_FIS(reg_set) \ 89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 90 #define SATA_RECEIVED_PIO_FIS(reg_set) \ 91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 92 #define SATA_RECEIVED_DMA_FIS(reg_set) \ 93 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 94 95 enum dev_status { 96 MVS_DEV_NORMAL = 0x0, 97 MVS_DEV_EH = 0x1, 98 }; 99 100 enum dev_reset { 101 MVS_SOFT_RESET = 0, 102 MVS_HARD_RESET = 1, 103 MVS_PHY_TUNE = 2, 104 }; 105 106 struct mvs_info; 107 108 struct mvs_dispatch { 109 char *name; 110 int (*chip_init)(struct mvs_info *mvi); 111 int (*spi_init)(struct mvs_info *mvi); 112 int (*chip_ioremap)(struct mvs_info *mvi); 113 void (*chip_iounmap)(struct mvs_info *mvi); 114 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 115 u32 (*isr_status)(struct mvs_info *mvi, int irq); 116 void (*interrupt_enable)(struct mvs_info *mvi); 117 void (*interrupt_disable)(struct mvs_info *mvi); 118 119 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 120 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 121 122 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 123 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 124 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 125 126 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 127 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 128 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 129 130 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 131 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 132 133 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 134 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 135 136 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 137 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all); 138 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 139 u32 tfs); 140 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 141 u32 (*rx_update)(struct mvs_info *mvi); 142 void (*int_full)(struct mvs_info *mvi); 143 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 144 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 145 u32 (*prd_size)(void); 146 u32 (*prd_count)(void); 147 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 148 void (*detect_porttype)(struct mvs_info *mvi, int i); 149 int (*oob_done)(struct mvs_info *mvi, int i); 150 void (*fix_phy_info)(struct mvs_info *mvi, int i, 151 struct sas_identify_frame *id); 152 void (*phy_work_around)(struct mvs_info *mvi, int i); 153 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 154 struct sas_phy_linkrates *rates); 155 u32 (*phy_max_link_rate)(void); 156 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 157 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 158 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 159 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 160 void (*clear_active_cmds)(struct mvs_info *mvi); 161 u32 (*spi_read_data)(struct mvs_info *mvi); 162 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 163 int (*spi_buildcmd)(struct mvs_info *mvi, 164 u32 *dwCmd, 165 u8 cmd, 166 u8 read, 167 u8 length, 168 u32 addr 169 ); 170 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 171 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 172 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask, 173 int buf_len, int from, void *prd); 174 void (*tune_interrupt)(struct mvs_info *mvi, u32 time); 175 void (*non_spec_ncq_error)(struct mvs_info *mvi); 176 177 }; 178 179 struct mvs_chip_info { 180 u32 n_host; 181 u32 n_phy; 182 u32 fis_offs; 183 u32 fis_count; 184 u32 srs_sz; 185 u32 sg_width; 186 u32 slot_width; 187 const struct mvs_dispatch *dispatch; 188 }; 189 #define MVS_MAX_SG (1U << mvi->chip->sg_width) 190 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 191 #define MVS_RX_FISL_SZ \ 192 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 193 #define MVS_CHIP_DISP (mvi->chip->dispatch) 194 195 struct mvs_err_info { 196 __le32 flags; 197 __le32 flags2; 198 }; 199 200 struct mvs_cmd_hdr { 201 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 202 __le32 lens; /* cmd, max resp frame len */ 203 __le32 tags; /* targ port xfer tag; tag */ 204 __le32 data_len; /* data xfer len */ 205 __le64 cmd_tbl; /* command table address */ 206 __le64 open_frame; /* open addr frame address */ 207 __le64 status_buf; /* status buffer address */ 208 __le64 prd_tbl; /* PRD tbl address */ 209 __le32 reserved[4]; 210 }; 211 212 struct mvs_port { 213 struct asd_sas_port sas_port; 214 u8 port_attached; 215 u8 wide_port_phymap; 216 struct list_head list; 217 }; 218 219 struct mvs_phy { 220 struct mvs_info *mvi; 221 struct mvs_port *port; 222 struct asd_sas_phy sas_phy; 223 struct sas_identify identify; 224 struct scsi_device *sdev; 225 struct timer_list timer; 226 u64 dev_sas_addr; 227 u64 att_dev_sas_addr; 228 u32 att_dev_info; 229 u32 dev_info; 230 u32 phy_type; 231 u32 phy_status; 232 u32 irq_status; 233 u32 frame_rcvd_size; 234 u8 frame_rcvd[32]; 235 u8 phy_attached; 236 u8 phy_mode; 237 u8 reserved[2]; 238 u32 phy_event; 239 enum sas_linkrate minimum_linkrate; 240 enum sas_linkrate maximum_linkrate; 241 }; 242 243 struct mvs_device { 244 struct list_head dev_entry; 245 enum sas_device_type dev_type; 246 struct mvs_info *mvi_info; 247 struct domain_device *sas_device; 248 struct timer_list timer; 249 u32 attached_phy; 250 u32 device_id; 251 u32 running_req; 252 u8 taskfileset; 253 u8 dev_status; 254 u16 reserved; 255 }; 256 257 /* Generate PHY tunning parameters */ 258 struct phy_tuning { 259 /* 1 bit, transmitter emphasis enable */ 260 u8 trans_emp_en:1; 261 /* 4 bits, transmitter emphasis amplitude */ 262 u8 trans_emp_amp:4; 263 /* 3 bits, reserved space */ 264 u8 Reserved_2bit_1:3; 265 /* 5 bits, transmitter amplitude */ 266 u8 trans_amp:5; 267 /* 2 bits, transmitter amplitude adjust */ 268 u8 trans_amp_adj:2; 269 /* 1 bit, reserved space */ 270 u8 resv_2bit_2:1; 271 /* 2 bytes, reserved space */ 272 u8 reserved[2]; 273 }; 274 275 struct ffe_control { 276 /* 4 bits, FFE Capacitor Select (value range 0~F) */ 277 u8 ffe_cap_sel:4; 278 /* 3 bits, FFE Resistor Select (value range 0~7) */ 279 u8 ffe_rss_sel:3; 280 /* 1 bit reserve*/ 281 u8 reserved:1; 282 }; 283 284 /* 285 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes. 286 * The data area is valid only Signature="MRVL". 287 * If any member fills with 0xFF, the member is invalid. 288 */ 289 struct hba_info_page { 290 /* Dword 0 */ 291 /* 4 bytes, structure signature,should be "MRVL" at first initial */ 292 u8 signature[4]; 293 294 /* Dword 1-13 */ 295 u32 reserved1[13]; 296 297 /* Dword 14-29 */ 298 /* 64 bytes, SAS address for each port */ 299 u64 sas_addr[8]; 300 301 /* Dword 30-31 */ 302 /* 8 bytes for vanir 8 port PHY FFE seeting 303 * BIT 0~3 : FFE Capacitor select(value range 0~F) 304 * BIT 4~6 : FFE Resistor select(value range 0~7) 305 * BIT 7: reserve. 306 */ 307 308 struct ffe_control ffe_ctl[8]; 309 /* Dword 32 -43 */ 310 u32 reserved2[12]; 311 312 /* Dword 44-45 */ 313 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */ 314 u8 phy_rate[8]; 315 316 /* Dword 46-53 */ 317 /* 32 bytes, PHY tuning parameters for each PHY*/ 318 struct phy_tuning phy_tuning[8]; 319 320 /* Dword 54-63 */ 321 u32 reserved3[10]; 322 }; /* total 256 bytes */ 323 324 struct mvs_slot_info { 325 struct list_head entry; 326 union { 327 struct sas_task *task; 328 void *tdata; 329 }; 330 u32 n_elem; 331 u32 tx; 332 u32 slot_tag; 333 334 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 335 * and PRD table 336 */ 337 void *buf; 338 dma_addr_t buf_dma; 339 void *response; 340 struct mvs_port *port; 341 struct mvs_device *device; 342 void *open_frame; 343 }; 344 345 struct mvs_info { 346 unsigned long flags; 347 348 /* host-wide lock */ 349 spinlock_t lock; 350 351 /* our device */ 352 struct pci_dev *pdev; 353 struct device *dev; 354 355 /* enhanced mode registers */ 356 void __iomem *regs; 357 358 /* peripheral or soc registers */ 359 void __iomem *regs_ex; 360 u8 sas_addr[SAS_ADDR_SIZE]; 361 362 /* SCSI/SAS glue */ 363 struct sas_ha_struct *sas; 364 struct Scsi_Host *shost; 365 366 /* TX (delivery) DMA ring */ 367 __le32 *tx; 368 dma_addr_t tx_dma; 369 370 /* cached next-producer idx */ 371 u32 tx_prod; 372 373 /* RX (completion) DMA ring */ 374 __le32 *rx; 375 dma_addr_t rx_dma; 376 377 /* RX consumer idx */ 378 u32 rx_cons; 379 380 /* RX'd FIS area */ 381 __le32 *rx_fis; 382 dma_addr_t rx_fis_dma; 383 384 /* DMA command header slots */ 385 struct mvs_cmd_hdr *slot; 386 dma_addr_t slot_dma; 387 388 u32 chip_id; 389 const struct mvs_chip_info *chip; 390 391 int tags_num; 392 unsigned long *tags; 393 /* further per-slot information */ 394 struct mvs_phy phy[MVS_MAX_PHYS]; 395 struct mvs_port port[MVS_MAX_PHYS]; 396 u32 id; 397 u64 sata_reg_set; 398 struct list_head *hba_list; 399 struct list_head soc_entry; 400 struct list_head wq_list; 401 unsigned long instance; 402 u16 flashid; 403 u32 flashsize; 404 u32 flashsectSize; 405 406 void *addon; 407 struct hba_info_page hba_info_param; 408 struct mvs_device devices[MVS_MAX_DEVICES]; 409 void *bulk_buffer; 410 dma_addr_t bulk_buffer_dma; 411 void *bulk_buffer1; 412 dma_addr_t bulk_buffer_dma1; 413 #define TRASH_BUCKET_SIZE 0x20000 414 void *dma_pool; 415 struct mvs_slot_info slot_info[0]; 416 }; 417 418 struct mvs_prv_info{ 419 u8 n_host; 420 u8 n_phy; 421 u8 scan_finished; 422 u8 reserve; 423 struct mvs_info *mvi[2]; 424 struct tasklet_struct mv_tasklet; 425 }; 426 427 struct mvs_wq { 428 struct delayed_work work_q; 429 struct mvs_info *mvi; 430 void *data; 431 int handler; 432 struct list_head entry; 433 }; 434 435 struct mvs_task_exec_info { 436 struct sas_task *task; 437 struct mvs_cmd_hdr *hdr; 438 struct mvs_port *port; 439 u32 tag; 440 int n_elem; 441 }; 442 443 struct mvs_task_list { 444 struct sas_task *task; 445 struct list_head list; 446 }; 447 448 449 /******************** function prototype *********************/ 450 void mvs_get_sas_addr(void *buf, u32 buflen); 451 void mvs_tag_clear(struct mvs_info *mvi, u32 tag); 452 void mvs_tag_free(struct mvs_info *mvi, u32 tag); 453 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); 454 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); 455 void mvs_tag_init(struct mvs_info *mvi); 456 void mvs_iounmap(void __iomem *regs); 457 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 458 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 459 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 460 void *funcdata); 461 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo, 462 u32 off_hi, u64 sas_addr); 463 void mvs_scan_start(struct Scsi_Host *shost); 464 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 465 int mvs_queue_command(struct sas_task *task, const int num, 466 gfp_t gfp_flags); 467 int mvs_abort_task(struct sas_task *task); 468 int mvs_abort_task_set(struct domain_device *dev, u8 *lun); 469 int mvs_clear_aca(struct domain_device *dev, u8 *lun); 470 int mvs_clear_task_set(struct domain_device *dev, u8 * lun); 471 void mvs_port_formed(struct asd_sas_phy *sas_phy); 472 void mvs_port_deformed(struct asd_sas_phy *sas_phy); 473 int mvs_dev_found(struct domain_device *dev); 474 void mvs_dev_gone(struct domain_device *dev); 475 int mvs_lu_reset(struct domain_device *dev, u8 *lun); 476 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 477 int mvs_I_T_nexus_reset(struct domain_device *dev); 478 int mvs_query_task(struct sas_task *task); 479 void mvs_release_task(struct mvs_info *mvi, 480 struct domain_device *dev); 481 void mvs_do_release_task(struct mvs_info *mvi, int phy_no, 482 struct domain_device *dev); 483 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 484 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 485 int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 486 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set); 487 #endif 488 489