1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell 88SE64xx/88SE94xx pci init 4 * 5 * Copyright 2007 Red Hat, Inc. 6 * Copyright 2008 Marvell. <kewei@marvell.com> 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8 */ 9 10 11 #include "mv_sas.h" 12 13 int interrupt_coalescing = 0x80; 14 15 static struct scsi_transport_template *mvs_stt; 16 static const struct mvs_chip_info mvs_chips[] = { 17 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 18 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 19 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 20 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 21 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 22 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 23 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 24 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 25 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 26 }; 27 28 static const struct attribute_group *mvst_host_groups[]; 29 30 #define SOC_SAS_NUM 2 31 32 static const struct scsi_host_template mvs_sht = { 33 LIBSAS_SHT_BASE 34 .scan_finished = mvs_scan_finished, 35 .scan_start = mvs_scan_start, 36 .can_queue = 1, 37 .sg_tablesize = SG_ALL, 38 .shost_groups = mvst_host_groups, 39 .track_queue_depth = 1, 40 }; 41 42 static struct sas_domain_function_template mvs_transport_ops = { 43 .lldd_dev_found = mvs_dev_found, 44 .lldd_dev_gone = mvs_dev_gone, 45 .lldd_execute_task = mvs_queue_command, 46 .lldd_control_phy = mvs_phy_control, 47 48 .lldd_abort_task = mvs_abort_task, 49 .lldd_abort_task_set = sas_abort_task_set, 50 .lldd_clear_task_set = sas_clear_task_set, 51 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 52 .lldd_lu_reset = mvs_lu_reset, 53 .lldd_query_task = mvs_query_task, 54 .lldd_port_formed = mvs_port_formed, 55 .lldd_port_deformed = mvs_port_deformed, 56 57 .lldd_write_gpio = mvs_gpio_write, 58 59 }; 60 61 static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 62 { 63 struct mvs_phy *phy = &mvi->phy[phy_id]; 64 struct asd_sas_phy *sas_phy = &phy->sas_phy; 65 66 phy->mvi = mvi; 67 phy->port = NULL; 68 timer_setup(&phy->timer, NULL, 0); 69 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 70 sas_phy->iproto = SAS_PROTOCOL_ALL; 71 sas_phy->tproto = 0; 72 sas_phy->role = PHY_ROLE_INITIATOR; 73 sas_phy->oob_mode = OOB_NOT_CONNECTED; 74 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 75 76 sas_phy->id = phy_id; 77 sas_phy->sas_addr = &mvi->sas_addr[0]; 78 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 79 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 80 sas_phy->lldd_phy = phy; 81 } 82 83 static void mvs_free(struct mvs_info *mvi) 84 { 85 struct mvs_wq *mwq; 86 int slot_nr; 87 88 if (!mvi) 89 return; 90 91 if (mvi->flags & MVF_FLAG_SOC) 92 slot_nr = MVS_SOC_SLOTS; 93 else 94 slot_nr = MVS_CHIP_SLOT_SZ; 95 96 dma_pool_destroy(mvi->dma_pool); 97 98 if (mvi->tx) 99 dma_free_coherent(mvi->dev, 100 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 101 mvi->tx, mvi->tx_dma); 102 if (mvi->rx_fis) 103 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 104 mvi->rx_fis, mvi->rx_fis_dma); 105 if (mvi->rx) 106 dma_free_coherent(mvi->dev, 107 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 108 mvi->rx, mvi->rx_dma); 109 if (mvi->slot) 110 dma_free_coherent(mvi->dev, 111 sizeof(*mvi->slot) * slot_nr, 112 mvi->slot, mvi->slot_dma); 113 114 if (mvi->bulk_buffer) 115 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 116 mvi->bulk_buffer, mvi->bulk_buffer_dma); 117 if (mvi->bulk_buffer1) 118 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 119 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 120 121 MVS_CHIP_DISP->chip_iounmap(mvi); 122 if (mvi->shost) 123 scsi_host_put(mvi->shost); 124 list_for_each_entry(mwq, &mvi->wq_list, entry) 125 cancel_delayed_work(&mwq->work_q); 126 kfree(mvi->rsvd_tags); 127 kfree(mvi); 128 } 129 130 #ifdef CONFIG_SCSI_MVSAS_TASKLET 131 static void mvs_tasklet(unsigned long opaque) 132 { 133 u32 stat; 134 u16 core_nr, i = 0; 135 136 struct mvs_info *mvi; 137 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 138 139 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 140 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 141 142 if (unlikely(!mvi)) 143 BUG_ON(1); 144 145 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 146 if (!stat) 147 goto out; 148 149 for (i = 0; i < core_nr; i++) { 150 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 151 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 152 } 153 out: 154 MVS_CHIP_DISP->interrupt_enable(mvi); 155 156 } 157 #endif 158 159 static irqreturn_t mvs_interrupt(int irq, void *opaque) 160 { 161 u32 stat; 162 struct mvs_info *mvi; 163 struct sas_ha_struct *sha = opaque; 164 #ifndef CONFIG_SCSI_MVSAS_TASKLET 165 u32 i; 166 u32 core_nr; 167 168 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 169 #endif 170 171 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 172 173 if (unlikely(!mvi)) 174 return IRQ_NONE; 175 #ifdef CONFIG_SCSI_MVSAS_TASKLET 176 MVS_CHIP_DISP->interrupt_disable(mvi); 177 #endif 178 179 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 180 if (!stat) { 181 #ifdef CONFIG_SCSI_MVSAS_TASKLET 182 MVS_CHIP_DISP->interrupt_enable(mvi); 183 #endif 184 return IRQ_NONE; 185 } 186 187 #ifdef CONFIG_SCSI_MVSAS_TASKLET 188 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 189 #else 190 for (i = 0; i < core_nr; i++) { 191 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 192 MVS_CHIP_DISP->isr(mvi, irq, stat); 193 } 194 #endif 195 return IRQ_HANDLED; 196 } 197 198 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 199 { 200 int i = 0, slot_nr; 201 char pool_name[32]; 202 203 if (mvi->flags & MVF_FLAG_SOC) 204 slot_nr = MVS_SOC_SLOTS; 205 else 206 slot_nr = MVS_CHIP_SLOT_SZ; 207 208 spin_lock_init(&mvi->lock); 209 for (i = 0; i < mvi->chip->n_phy; i++) { 210 mvs_phy_init(mvi, i); 211 mvi->port[i].wide_port_phymap = 0; 212 mvi->port[i].port_attached = 0; 213 INIT_LIST_HEAD(&mvi->port[i].list); 214 } 215 for (i = 0; i < MVS_MAX_DEVICES; i++) { 216 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 217 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 218 mvi->devices[i].device_id = i; 219 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 220 } 221 222 /* 223 * alloc and init our DMA areas 224 */ 225 mvi->tx = dma_alloc_coherent(mvi->dev, 226 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 227 &mvi->tx_dma, GFP_KERNEL); 228 if (!mvi->tx) 229 goto err_out; 230 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 231 &mvi->rx_fis_dma, GFP_KERNEL); 232 if (!mvi->rx_fis) 233 goto err_out; 234 235 mvi->rx = dma_alloc_coherent(mvi->dev, 236 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 237 &mvi->rx_dma, GFP_KERNEL); 238 if (!mvi->rx) 239 goto err_out; 240 mvi->rx[0] = cpu_to_le32(0xfff); 241 mvi->rx_cons = 0xfff; 242 243 mvi->slot = dma_alloc_coherent(mvi->dev, 244 sizeof(*mvi->slot) * slot_nr, 245 &mvi->slot_dma, GFP_KERNEL); 246 if (!mvi->slot) 247 goto err_out; 248 249 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 250 TRASH_BUCKET_SIZE, 251 &mvi->bulk_buffer_dma, GFP_KERNEL); 252 if (!mvi->bulk_buffer) 253 goto err_out; 254 255 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 256 TRASH_BUCKET_SIZE, 257 &mvi->bulk_buffer_dma1, GFP_KERNEL); 258 if (!mvi->bulk_buffer1) 259 goto err_out; 260 261 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 262 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev, 263 MVS_SLOT_BUF_SZ, 16, 0); 264 if (!mvi->dma_pool) { 265 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 266 goto err_out; 267 } 268 269 return 0; 270 err_out: 271 return 1; 272 } 273 274 275 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 276 { 277 unsigned long res_start, res_len, res_flag_ex = 0; 278 struct pci_dev *pdev = mvi->pdev; 279 if (bar_ex != -1) { 280 /* 281 * ioremap main and peripheral registers 282 */ 283 res_start = pci_resource_start(pdev, bar_ex); 284 res_len = pci_resource_len(pdev, bar_ex); 285 if (!res_start || !res_len) 286 goto err_out; 287 288 res_flag_ex = pci_resource_flags(pdev, bar_ex); 289 if (res_flag_ex & IORESOURCE_MEM) 290 mvi->regs_ex = ioremap(res_start, res_len); 291 else 292 mvi->regs_ex = (void *)res_start; 293 if (!mvi->regs_ex) 294 goto err_out; 295 } 296 297 res_start = pci_resource_start(pdev, bar); 298 res_len = pci_resource_len(pdev, bar); 299 if (!res_start || !res_len) { 300 iounmap(mvi->regs_ex); 301 mvi->regs_ex = NULL; 302 goto err_out; 303 } 304 305 mvi->regs = ioremap(res_start, res_len); 306 307 if (!mvi->regs) { 308 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 309 iounmap(mvi->regs_ex); 310 mvi->regs_ex = NULL; 311 goto err_out; 312 } 313 314 return 0; 315 err_out: 316 return -1; 317 } 318 319 void mvs_iounmap(void __iomem *regs) 320 { 321 iounmap(regs); 322 } 323 324 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 325 const struct pci_device_id *ent, 326 struct Scsi_Host *shost, unsigned int id) 327 { 328 struct mvs_info *mvi = NULL; 329 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 330 331 mvi = kzalloc(sizeof(*mvi) + 332 (1L << mvs_chips[ent->driver_data].slot_width) * 333 sizeof(struct mvs_slot_info), GFP_KERNEL); 334 if (!mvi) 335 return NULL; 336 337 mvi->pdev = pdev; 338 mvi->dev = &pdev->dev; 339 mvi->chip_id = ent->driver_data; 340 mvi->chip = &mvs_chips[mvi->chip_id]; 341 INIT_LIST_HEAD(&mvi->wq_list); 342 343 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 344 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 345 346 mvi->id = id; 347 mvi->sas = sha; 348 mvi->shost = shost; 349 350 mvi->rsvd_tags = bitmap_zalloc(MVS_RSVD_SLOTS, GFP_KERNEL); 351 if (!mvi->rsvd_tags) 352 goto err_out; 353 354 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 355 goto err_out; 356 if (!mvs_alloc(mvi, shost)) 357 return mvi; 358 err_out: 359 mvs_free(mvi); 360 return NULL; 361 } 362 363 static int pci_go_64(struct pci_dev *pdev) 364 { 365 int rc; 366 367 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 368 if (rc) { 369 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 370 if (rc) { 371 dev_printk(KERN_ERR, &pdev->dev, 372 "32-bit DMA enable failed\n"); 373 return rc; 374 } 375 } 376 377 return rc; 378 } 379 380 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 381 const struct mvs_chip_info *chip_info) 382 { 383 int phy_nr, port_nr; unsigned short core_nr; 384 struct asd_sas_phy **arr_phy; 385 struct asd_sas_port **arr_port; 386 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 387 388 core_nr = chip_info->n_host; 389 phy_nr = core_nr * chip_info->n_phy; 390 port_nr = phy_nr; 391 392 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 393 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 394 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 395 if (!arr_phy || !arr_port) 396 goto exit_free; 397 398 sha->sas_phy = arr_phy; 399 sha->sas_port = arr_port; 400 sha->shost = shost; 401 402 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 403 if (!sha->lldd_ha) 404 goto exit_free; 405 406 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 407 408 shost->transportt = mvs_stt; 409 shost->max_id = MVS_MAX_DEVICES; 410 shost->max_lun = ~0; 411 shost->max_channel = 1; 412 shost->max_cmd_len = 16; 413 414 return 0; 415 exit_free: 416 kfree(arr_phy); 417 kfree(arr_port); 418 return -1; 419 420 } 421 422 static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 423 const struct mvs_chip_info *chip_info) 424 { 425 int can_queue, i = 0, j = 0; 426 struct mvs_info *mvi = NULL; 427 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 428 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 429 430 for (j = 0; j < nr_core; j++) { 431 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 432 for (i = 0; i < chip_info->n_phy; i++) { 433 sha->sas_phy[j * chip_info->n_phy + i] = 434 &mvi->phy[i].sas_phy; 435 sha->sas_port[j * chip_info->n_phy + i] = 436 &mvi->port[i].sas_port; 437 } 438 } 439 440 sha->sas_ha_name = DRV_NAME; 441 sha->dev = mvi->dev; 442 sha->sas_addr = &mvi->sas_addr[0]; 443 444 sha->num_phys = nr_core * chip_info->n_phy; 445 446 if (mvi->flags & MVF_FLAG_SOC) 447 can_queue = MVS_SOC_CAN_QUEUE; 448 else 449 can_queue = MVS_CHIP_SLOT_SZ; 450 451 can_queue -= MVS_RSVD_SLOTS; 452 453 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 454 shost->can_queue = can_queue; 455 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 456 sha->shost = mvi->shost; 457 } 458 459 static void mvs_init_sas_add(struct mvs_info *mvi) 460 { 461 u8 i; 462 for (i = 0; i < mvi->chip->n_phy; i++) { 463 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 464 mvi->phy[i].dev_sas_addr = 465 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 466 } 467 468 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 469 } 470 471 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 472 { 473 unsigned int rc, nhost = 0; 474 struct mvs_info *mvi; 475 irq_handler_t irq_handler = mvs_interrupt; 476 struct Scsi_Host *shost = NULL; 477 const struct mvs_chip_info *chip; 478 479 dev_printk(KERN_INFO, &pdev->dev, 480 "mvsas: driver version %s\n", DRV_VERSION); 481 rc = pci_enable_device(pdev); 482 if (rc) 483 goto err_out_enable; 484 485 pci_set_master(pdev); 486 487 rc = pci_request_regions(pdev, DRV_NAME); 488 if (rc) 489 goto err_out_disable; 490 491 rc = pci_go_64(pdev); 492 if (rc) 493 goto err_out_regions; 494 495 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 496 if (!shost) { 497 rc = -ENOMEM; 498 goto err_out_regions; 499 } 500 501 chip = &mvs_chips[ent->driver_data]; 502 SHOST_TO_SAS_HA(shost) = 503 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 504 if (!SHOST_TO_SAS_HA(shost)) { 505 scsi_host_put(shost); 506 rc = -ENOMEM; 507 goto err_out_regions; 508 } 509 510 rc = mvs_prep_sas_ha_init(shost, chip); 511 if (rc) { 512 scsi_host_put(shost); 513 rc = -ENOMEM; 514 goto err_out_regions; 515 } 516 517 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 518 519 do { 520 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 521 if (!mvi) { 522 rc = -ENOMEM; 523 goto err_out_regions; 524 } 525 526 memset(&mvi->hba_info_param, 0xFF, 527 sizeof(struct hba_info_page)); 528 529 mvs_init_sas_add(mvi); 530 531 mvi->instance = nhost; 532 rc = MVS_CHIP_DISP->chip_init(mvi); 533 if (rc) { 534 mvs_free(mvi); 535 goto err_out_regions; 536 } 537 nhost++; 538 } while (nhost < chip->n_host); 539 #ifdef CONFIG_SCSI_MVSAS_TASKLET 540 { 541 struct mvs_prv_info *mpi = SHOST_TO_SAS_HA(shost)->lldd_ha; 542 543 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 544 (unsigned long)SHOST_TO_SAS_HA(shost)); 545 } 546 #endif 547 548 mvs_post_sas_ha_init(shost, chip); 549 550 rc = scsi_add_host(shost, &pdev->dev); 551 if (rc) 552 goto err_out_shost; 553 554 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 555 if (rc) 556 goto err_out_shost; 557 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 558 DRV_NAME, SHOST_TO_SAS_HA(shost)); 559 if (rc) 560 goto err_not_sas; 561 562 MVS_CHIP_DISP->interrupt_enable(mvi); 563 564 scsi_scan_host(mvi->shost); 565 566 return 0; 567 568 err_not_sas: 569 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 570 err_out_shost: 571 scsi_remove_host(mvi->shost); 572 err_out_regions: 573 pci_release_regions(pdev); 574 err_out_disable: 575 pci_disable_device(pdev); 576 err_out_enable: 577 return rc; 578 } 579 580 static void mvs_pci_remove(struct pci_dev *pdev) 581 { 582 unsigned short core_nr, i = 0; 583 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 584 struct mvs_info *mvi = NULL; 585 586 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 587 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 588 589 #ifdef CONFIG_SCSI_MVSAS_TASKLET 590 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 591 #endif 592 593 sas_unregister_ha(sha); 594 sas_remove_host(mvi->shost); 595 596 MVS_CHIP_DISP->interrupt_disable(mvi); 597 free_irq(mvi->pdev->irq, sha); 598 for (i = 0; i < core_nr; i++) { 599 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 600 mvs_free(mvi); 601 } 602 kfree(sha->sas_phy); 603 kfree(sha->sas_port); 604 kfree(sha); 605 pci_release_regions(pdev); 606 pci_disable_device(pdev); 607 return; 608 } 609 610 static struct pci_device_id mvs_pci_table[] = { 611 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 612 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 613 { 614 .vendor = PCI_VENDOR_ID_MARVELL, 615 .device = 0x6440, 616 .subvendor = PCI_ANY_ID, 617 .subdevice = 0x6480, 618 .class = 0, 619 .class_mask = 0, 620 .driver_data = chip_6485, 621 }, 622 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 623 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 624 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 625 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 626 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 627 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 628 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 629 { PCI_VDEVICE(TTI, 0x2640), chip_6440 }, 630 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 631 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 632 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 633 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 634 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 635 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 636 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 637 { 638 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 639 .device = 0x9480, 640 .subvendor = PCI_ANY_ID, 641 .subdevice = 0x9480, 642 .class = 0, 643 .class_mask = 0, 644 .driver_data = chip_9480, 645 }, 646 { 647 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 648 .device = 0x9445, 649 .subvendor = PCI_ANY_ID, 650 .subdevice = 0x9480, 651 .class = 0, 652 .class_mask = 0, 653 .driver_data = chip_9445, 654 }, 655 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */ 656 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 657 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 658 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 659 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 660 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 661 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 662 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 663 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 664 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 665 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 666 667 { } /* terminate list */ 668 }; 669 670 static struct pci_driver mvs_pci_driver = { 671 .name = DRV_NAME, 672 .id_table = mvs_pci_table, 673 .probe = mvs_pci_init, 674 .remove = mvs_pci_remove, 675 }; 676 677 static ssize_t driver_version_show(struct device *cdev, 678 struct device_attribute *attr, char *buffer) 679 { 680 return sysfs_emit(buffer, "%s\n", DRV_VERSION); 681 } 682 683 static DEVICE_ATTR_RO(driver_version); 684 685 static ssize_t interrupt_coalescing_store(struct device *cdev, 686 struct device_attribute *attr, 687 const char *buffer, size_t size) 688 { 689 unsigned int val = 0; 690 struct mvs_info *mvi = NULL; 691 struct Scsi_Host *shost = class_to_shost(cdev); 692 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 693 u8 i, core_nr; 694 if (buffer == NULL) 695 return size; 696 697 if (sscanf(buffer, "%u", &val) != 1) 698 return -EINVAL; 699 700 if (val >= 0x10000) { 701 mv_dprintk("interrupt coalescing timer %d us is" 702 "too long\n", val); 703 return strlen(buffer); 704 } 705 706 interrupt_coalescing = val; 707 708 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 709 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 710 711 if (unlikely(!mvi)) 712 return -EINVAL; 713 714 for (i = 0; i < core_nr; i++) { 715 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 716 if (MVS_CHIP_DISP->tune_interrupt) 717 MVS_CHIP_DISP->tune_interrupt(mvi, 718 interrupt_coalescing); 719 } 720 mv_dprintk("set interrupt coalescing time to %d us\n", 721 interrupt_coalescing); 722 return strlen(buffer); 723 } 724 725 static ssize_t interrupt_coalescing_show(struct device *cdev, 726 struct device_attribute *attr, char *buffer) 727 { 728 return sysfs_emit(buffer, "%d\n", interrupt_coalescing); 729 } 730 731 static DEVICE_ATTR_RW(interrupt_coalescing); 732 733 static int __init mvs_init(void) 734 { 735 int rc; 736 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 737 if (!mvs_stt) 738 return -ENOMEM; 739 740 rc = pci_register_driver(&mvs_pci_driver); 741 if (rc) 742 goto err_out; 743 744 return 0; 745 746 err_out: 747 sas_release_transport(mvs_stt); 748 return rc; 749 } 750 751 static void __exit mvs_exit(void) 752 { 753 pci_unregister_driver(&mvs_pci_driver); 754 sas_release_transport(mvs_stt); 755 } 756 757 static struct attribute *mvst_host_attrs[] = { 758 &dev_attr_driver_version.attr, 759 &dev_attr_interrupt_coalescing.attr, 760 NULL, 761 }; 762 763 ATTRIBUTE_GROUPS(mvst_host); 764 765 module_init(mvs_init); 766 module_exit(mvs_exit); 767 768 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 769 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 770 MODULE_VERSION(DRV_VERSION); 771 MODULE_LICENSE("GPL"); 772 #ifdef CONFIG_PCI 773 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 774 #endif 775