1 /* 2 * Marvell 88SE64xx/88SE94xx pci init 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 27 #include "mv_sas.h" 28 29 static int lldd_max_execute_num = 1; 30 module_param_named(collector, lldd_max_execute_num, int, S_IRUGO); 31 MODULE_PARM_DESC(collector, "\n" 32 "\tIf greater than one, tells the SAS Layer to run in Task Collector\n" 33 "\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n" 34 "\tThe mvsas SAS LLDD supports both modes.\n" 35 "\tDefault: 1 (Direct Mode).\n"); 36 37 static struct scsi_transport_template *mvs_stt; 38 struct kmem_cache *mvs_task_list_cache; 39 static const struct mvs_chip_info mvs_chips[] = { 40 [chip_6320] = { 1, 2, 0x400, 17, 16, 9, &mvs_64xx_dispatch, }, 41 [chip_6440] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, }, 42 [chip_6485] = { 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, }, 43 [chip_9180] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, }, 44 [chip_9480] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, }, 45 [chip_9445] = { 1, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, }, 46 [chip_9485] = { 2, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, }, 47 [chip_1300] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, }, 48 [chip_1320] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, }, 49 }; 50 51 #define SOC_SAS_NUM 2 52 #define SG_MX 64 53 54 static struct scsi_host_template mvs_sht = { 55 .module = THIS_MODULE, 56 .name = DRV_NAME, 57 .queuecommand = sas_queuecommand, 58 .target_alloc = sas_target_alloc, 59 .slave_configure = mvs_slave_configure, 60 .slave_destroy = sas_slave_destroy, 61 .scan_finished = mvs_scan_finished, 62 .scan_start = mvs_scan_start, 63 .change_queue_depth = sas_change_queue_depth, 64 .change_queue_type = sas_change_queue_type, 65 .bios_param = sas_bios_param, 66 .can_queue = 1, 67 .cmd_per_lun = 1, 68 .this_id = -1, 69 .sg_tablesize = SG_MX, 70 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 71 .use_clustering = ENABLE_CLUSTERING, 72 .eh_device_reset_handler = sas_eh_device_reset_handler, 73 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 74 .slave_alloc = mvs_slave_alloc, 75 .target_destroy = sas_target_destroy, 76 .ioctl = sas_ioctl, 77 }; 78 79 static struct sas_domain_function_template mvs_transport_ops = { 80 .lldd_dev_found = mvs_dev_found, 81 .lldd_dev_gone = mvs_dev_gone, 82 .lldd_execute_task = mvs_queue_command, 83 .lldd_control_phy = mvs_phy_control, 84 85 .lldd_abort_task = mvs_abort_task, 86 .lldd_abort_task_set = mvs_abort_task_set, 87 .lldd_clear_aca = mvs_clear_aca, 88 .lldd_clear_task_set = mvs_clear_task_set, 89 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 90 .lldd_lu_reset = mvs_lu_reset, 91 .lldd_query_task = mvs_query_task, 92 .lldd_port_formed = mvs_port_formed, 93 .lldd_port_deformed = mvs_port_deformed, 94 95 }; 96 97 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id) 98 { 99 struct mvs_phy *phy = &mvi->phy[phy_id]; 100 struct asd_sas_phy *sas_phy = &phy->sas_phy; 101 102 phy->mvi = mvi; 103 init_timer(&phy->timer); 104 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 105 sas_phy->class = SAS; 106 sas_phy->iproto = SAS_PROTOCOL_ALL; 107 sas_phy->tproto = 0; 108 sas_phy->type = PHY_TYPE_PHYSICAL; 109 sas_phy->role = PHY_ROLE_INITIATOR; 110 sas_phy->oob_mode = OOB_NOT_CONNECTED; 111 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 112 113 sas_phy->id = phy_id; 114 sas_phy->sas_addr = &mvi->sas_addr[0]; 115 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 116 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 117 sas_phy->lldd_phy = phy; 118 } 119 120 static void mvs_free(struct mvs_info *mvi) 121 { 122 struct mvs_wq *mwq; 123 int slot_nr; 124 125 if (!mvi) 126 return; 127 128 if (mvi->flags & MVF_FLAG_SOC) 129 slot_nr = MVS_SOC_SLOTS; 130 else 131 slot_nr = MVS_SLOTS; 132 133 if (mvi->dma_pool) 134 pci_pool_destroy(mvi->dma_pool); 135 136 if (mvi->tx) 137 dma_free_coherent(mvi->dev, 138 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 139 mvi->tx, mvi->tx_dma); 140 if (mvi->rx_fis) 141 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 142 mvi->rx_fis, mvi->rx_fis_dma); 143 if (mvi->rx) 144 dma_free_coherent(mvi->dev, 145 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 146 mvi->rx, mvi->rx_dma); 147 if (mvi->slot) 148 dma_free_coherent(mvi->dev, 149 sizeof(*mvi->slot) * slot_nr, 150 mvi->slot, mvi->slot_dma); 151 #ifndef DISABLE_HOTPLUG_DMA_FIX 152 if (mvi->bulk_buffer) 153 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 154 mvi->bulk_buffer, mvi->bulk_buffer_dma); 155 #endif 156 157 MVS_CHIP_DISP->chip_iounmap(mvi); 158 if (mvi->shost) 159 scsi_host_put(mvi->shost); 160 list_for_each_entry(mwq, &mvi->wq_list, entry) 161 cancel_delayed_work(&mwq->work_q); 162 kfree(mvi); 163 } 164 165 #ifdef MVS_USE_TASKLET 166 struct tasklet_struct mv_tasklet; 167 static void mvs_tasklet(unsigned long opaque) 168 { 169 unsigned long flags; 170 u32 stat; 171 u16 core_nr, i = 0; 172 173 struct mvs_info *mvi; 174 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 175 176 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 177 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 178 179 if (unlikely(!mvi)) 180 BUG_ON(1); 181 182 for (i = 0; i < core_nr; i++) { 183 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 184 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->irq); 185 if (stat) 186 MVS_CHIP_DISP->isr(mvi, mvi->irq, stat); 187 } 188 189 } 190 #endif 191 192 static irqreturn_t mvs_interrupt(int irq, void *opaque) 193 { 194 u32 core_nr, i = 0; 195 u32 stat; 196 struct mvs_info *mvi; 197 struct sas_ha_struct *sha = opaque; 198 199 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 200 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 201 202 if (unlikely(!mvi)) 203 return IRQ_NONE; 204 205 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 206 if (!stat) 207 return IRQ_NONE; 208 209 #ifdef MVS_USE_TASKLET 210 tasklet_schedule(&mv_tasklet); 211 #else 212 for (i = 0; i < core_nr; i++) { 213 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 214 MVS_CHIP_DISP->isr(mvi, irq, stat); 215 } 216 #endif 217 return IRQ_HANDLED; 218 } 219 220 static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 221 { 222 int i = 0, slot_nr; 223 char pool_name[32]; 224 225 if (mvi->flags & MVF_FLAG_SOC) 226 slot_nr = MVS_SOC_SLOTS; 227 else 228 slot_nr = MVS_SLOTS; 229 230 spin_lock_init(&mvi->lock); 231 for (i = 0; i < mvi->chip->n_phy; i++) { 232 mvs_phy_init(mvi, i); 233 mvi->port[i].wide_port_phymap = 0; 234 mvi->port[i].port_attached = 0; 235 INIT_LIST_HEAD(&mvi->port[i].list); 236 } 237 for (i = 0; i < MVS_MAX_DEVICES; i++) { 238 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 239 mvi->devices[i].dev_type = NO_DEVICE; 240 mvi->devices[i].device_id = i; 241 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 242 init_timer(&mvi->devices[i].timer); 243 } 244 245 /* 246 * alloc and init our DMA areas 247 */ 248 mvi->tx = dma_alloc_coherent(mvi->dev, 249 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 250 &mvi->tx_dma, GFP_KERNEL); 251 if (!mvi->tx) 252 goto err_out; 253 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 254 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 255 &mvi->rx_fis_dma, GFP_KERNEL); 256 if (!mvi->rx_fis) 257 goto err_out; 258 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 259 260 mvi->rx = dma_alloc_coherent(mvi->dev, 261 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 262 &mvi->rx_dma, GFP_KERNEL); 263 if (!mvi->rx) 264 goto err_out; 265 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 266 mvi->rx[0] = cpu_to_le32(0xfff); 267 mvi->rx_cons = 0xfff; 268 269 mvi->slot = dma_alloc_coherent(mvi->dev, 270 sizeof(*mvi->slot) * slot_nr, 271 &mvi->slot_dma, GFP_KERNEL); 272 if (!mvi->slot) 273 goto err_out; 274 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 275 276 #ifndef DISABLE_HOTPLUG_DMA_FIX 277 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 278 TRASH_BUCKET_SIZE, 279 &mvi->bulk_buffer_dma, GFP_KERNEL); 280 if (!mvi->bulk_buffer) 281 goto err_out; 282 #endif 283 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 284 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0); 285 if (!mvi->dma_pool) { 286 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 287 goto err_out; 288 } 289 mvi->tags_num = slot_nr; 290 291 /* Initialize tags */ 292 mvs_tag_init(mvi); 293 return 0; 294 err_out: 295 return 1; 296 } 297 298 299 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 300 { 301 unsigned long res_start, res_len, res_flag, res_flag_ex = 0; 302 struct pci_dev *pdev = mvi->pdev; 303 if (bar_ex != -1) { 304 /* 305 * ioremap main and peripheral registers 306 */ 307 res_start = pci_resource_start(pdev, bar_ex); 308 res_len = pci_resource_len(pdev, bar_ex); 309 if (!res_start || !res_len) 310 goto err_out; 311 312 res_flag_ex = pci_resource_flags(pdev, bar_ex); 313 if (res_flag_ex & IORESOURCE_MEM) { 314 if (res_flag_ex & IORESOURCE_CACHEABLE) 315 mvi->regs_ex = ioremap(res_start, res_len); 316 else 317 mvi->regs_ex = ioremap_nocache(res_start, 318 res_len); 319 } else 320 mvi->regs_ex = (void *)res_start; 321 if (!mvi->regs_ex) 322 goto err_out; 323 } 324 325 res_start = pci_resource_start(pdev, bar); 326 res_len = pci_resource_len(pdev, bar); 327 if (!res_start || !res_len) 328 goto err_out; 329 330 res_flag = pci_resource_flags(pdev, bar); 331 if (res_flag & IORESOURCE_CACHEABLE) 332 mvi->regs = ioremap(res_start, res_len); 333 else 334 mvi->regs = ioremap_nocache(res_start, res_len); 335 336 if (!mvi->regs) { 337 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 338 iounmap(mvi->regs_ex); 339 mvi->regs_ex = NULL; 340 goto err_out; 341 } 342 343 return 0; 344 err_out: 345 return -1; 346 } 347 348 void mvs_iounmap(void __iomem *regs) 349 { 350 iounmap(regs); 351 } 352 353 static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev, 354 const struct pci_device_id *ent, 355 struct Scsi_Host *shost, unsigned int id) 356 { 357 struct mvs_info *mvi; 358 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 359 360 mvi = kzalloc(sizeof(*mvi) + MVS_SLOTS * sizeof(struct mvs_slot_info), 361 GFP_KERNEL); 362 if (!mvi) 363 return NULL; 364 365 mvi->pdev = pdev; 366 mvi->dev = &pdev->dev; 367 mvi->chip_id = ent->driver_data; 368 mvi->chip = &mvs_chips[mvi->chip_id]; 369 INIT_LIST_HEAD(&mvi->wq_list); 370 mvi->irq = pdev->irq; 371 372 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 373 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 374 375 mvi->id = id; 376 mvi->sas = sha; 377 mvi->shost = shost; 378 #ifdef MVS_USE_TASKLET 379 tasklet_init(&mv_tasklet, mvs_tasklet, (unsigned long)sha); 380 #endif 381 382 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 383 goto err_out; 384 if (!mvs_alloc(mvi, shost)) 385 return mvi; 386 err_out: 387 mvs_free(mvi); 388 return NULL; 389 } 390 391 /* move to PCI layer or libata core? */ 392 static int pci_go_64(struct pci_dev *pdev) 393 { 394 int rc; 395 396 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 397 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 398 if (rc) { 399 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 400 if (rc) { 401 dev_printk(KERN_ERR, &pdev->dev, 402 "64-bit DMA enable failed\n"); 403 return rc; 404 } 405 } 406 } else { 407 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 408 if (rc) { 409 dev_printk(KERN_ERR, &pdev->dev, 410 "32-bit DMA enable failed\n"); 411 return rc; 412 } 413 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 414 if (rc) { 415 dev_printk(KERN_ERR, &pdev->dev, 416 "32-bit consistent DMA enable failed\n"); 417 return rc; 418 } 419 } 420 421 return rc; 422 } 423 424 static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost, 425 const struct mvs_chip_info *chip_info) 426 { 427 int phy_nr, port_nr; unsigned short core_nr; 428 struct asd_sas_phy **arr_phy; 429 struct asd_sas_port **arr_port; 430 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 431 432 core_nr = chip_info->n_host; 433 phy_nr = core_nr * chip_info->n_phy; 434 port_nr = phy_nr; 435 436 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 437 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 438 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 439 if (!arr_phy || !arr_port) 440 goto exit_free; 441 442 sha->sas_phy = arr_phy; 443 sha->sas_port = arr_port; 444 sha->core.shost = shost; 445 446 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 447 if (!sha->lldd_ha) 448 goto exit_free; 449 450 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 451 452 shost->transportt = mvs_stt; 453 shost->max_id = 128; 454 shost->max_lun = ~0; 455 shost->max_channel = 1; 456 shost->max_cmd_len = 16; 457 458 return 0; 459 exit_free: 460 kfree(arr_phy); 461 kfree(arr_port); 462 return -1; 463 464 } 465 466 static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost, 467 const struct mvs_chip_info *chip_info) 468 { 469 int can_queue, i = 0, j = 0; 470 struct mvs_info *mvi = NULL; 471 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 472 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 473 474 for (j = 0; j < nr_core; j++) { 475 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 476 for (i = 0; i < chip_info->n_phy; i++) { 477 sha->sas_phy[j * chip_info->n_phy + i] = 478 &mvi->phy[i].sas_phy; 479 sha->sas_port[j * chip_info->n_phy + i] = 480 &mvi->port[i].sas_port; 481 } 482 } 483 484 sha->sas_ha_name = DRV_NAME; 485 sha->dev = mvi->dev; 486 sha->lldd_module = THIS_MODULE; 487 sha->sas_addr = &mvi->sas_addr[0]; 488 489 sha->num_phys = nr_core * chip_info->n_phy; 490 491 sha->lldd_max_execute_num = lldd_max_execute_num; 492 493 if (mvi->flags & MVF_FLAG_SOC) 494 can_queue = MVS_SOC_CAN_QUEUE; 495 else 496 can_queue = MVS_CAN_QUEUE; 497 498 sha->lldd_queue_size = can_queue; 499 shost->can_queue = can_queue; 500 mvi->shost->cmd_per_lun = MVS_SLOTS/sha->num_phys; 501 sha->core.shost = mvi->shost; 502 } 503 504 static void mvs_init_sas_add(struct mvs_info *mvi) 505 { 506 u8 i; 507 for (i = 0; i < mvi->chip->n_phy; i++) { 508 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 509 mvi->phy[i].dev_sas_addr = 510 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 511 } 512 513 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 514 } 515 516 static int __devinit mvs_pci_init(struct pci_dev *pdev, 517 const struct pci_device_id *ent) 518 { 519 unsigned int rc, nhost = 0; 520 struct mvs_info *mvi; 521 irq_handler_t irq_handler = mvs_interrupt; 522 struct Scsi_Host *shost = NULL; 523 const struct mvs_chip_info *chip; 524 525 dev_printk(KERN_INFO, &pdev->dev, 526 "mvsas: driver version %s\n", DRV_VERSION); 527 rc = pci_enable_device(pdev); 528 if (rc) 529 goto err_out_enable; 530 531 pci_set_master(pdev); 532 533 rc = pci_request_regions(pdev, DRV_NAME); 534 if (rc) 535 goto err_out_disable; 536 537 rc = pci_go_64(pdev); 538 if (rc) 539 goto err_out_regions; 540 541 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 542 if (!shost) { 543 rc = -ENOMEM; 544 goto err_out_regions; 545 } 546 547 chip = &mvs_chips[ent->driver_data]; 548 SHOST_TO_SAS_HA(shost) = 549 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 550 if (!SHOST_TO_SAS_HA(shost)) { 551 kfree(shost); 552 rc = -ENOMEM; 553 goto err_out_regions; 554 } 555 556 rc = mvs_prep_sas_ha_init(shost, chip); 557 if (rc) { 558 kfree(shost); 559 rc = -ENOMEM; 560 goto err_out_regions; 561 } 562 563 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 564 565 do { 566 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 567 if (!mvi) { 568 rc = -ENOMEM; 569 goto err_out_regions; 570 } 571 572 mvs_init_sas_add(mvi); 573 574 mvi->instance = nhost; 575 rc = MVS_CHIP_DISP->chip_init(mvi); 576 if (rc) { 577 mvs_free(mvi); 578 goto err_out_regions; 579 } 580 nhost++; 581 } while (nhost < chip->n_host); 582 #ifdef MVS_USE_TASKLET 583 tasklet_init(&mv_tasklet, mvs_tasklet, 584 (unsigned long)SHOST_TO_SAS_HA(shost)); 585 #endif 586 587 mvs_post_sas_ha_init(shost, chip); 588 589 rc = scsi_add_host(shost, &pdev->dev); 590 if (rc) 591 goto err_out_shost; 592 593 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 594 if (rc) 595 goto err_out_shost; 596 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 597 DRV_NAME, SHOST_TO_SAS_HA(shost)); 598 if (rc) 599 goto err_not_sas; 600 601 MVS_CHIP_DISP->interrupt_enable(mvi); 602 603 scsi_scan_host(mvi->shost); 604 605 return 0; 606 607 err_not_sas: 608 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 609 err_out_shost: 610 scsi_remove_host(mvi->shost); 611 err_out_regions: 612 pci_release_regions(pdev); 613 err_out_disable: 614 pci_disable_device(pdev); 615 err_out_enable: 616 return rc; 617 } 618 619 static void __devexit mvs_pci_remove(struct pci_dev *pdev) 620 { 621 unsigned short core_nr, i = 0; 622 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 623 struct mvs_info *mvi = NULL; 624 625 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 626 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 627 628 #ifdef MVS_USE_TASKLET 629 tasklet_kill(&mv_tasklet); 630 #endif 631 632 pci_set_drvdata(pdev, NULL); 633 sas_unregister_ha(sha); 634 sas_remove_host(mvi->shost); 635 scsi_remove_host(mvi->shost); 636 637 MVS_CHIP_DISP->interrupt_disable(mvi); 638 free_irq(mvi->irq, sha); 639 for (i = 0; i < core_nr; i++) { 640 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 641 mvs_free(mvi); 642 } 643 kfree(sha->sas_phy); 644 kfree(sha->sas_port); 645 kfree(sha); 646 pci_release_regions(pdev); 647 pci_disable_device(pdev); 648 return; 649 } 650 651 static struct pci_device_id __devinitdata mvs_pci_table[] = { 652 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 653 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 654 { 655 .vendor = PCI_VENDOR_ID_MARVELL, 656 .device = 0x6440, 657 .subvendor = PCI_ANY_ID, 658 .subdevice = 0x6480, 659 .class = 0, 660 .class_mask = 0, 661 .driver_data = chip_6485, 662 }, 663 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 664 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 665 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 666 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 667 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 668 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 669 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 670 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 671 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 672 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 673 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 674 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 675 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 676 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 677 { 678 .vendor = 0x1b4b, 679 .device = 0x9445, 680 .subvendor = PCI_ANY_ID, 681 .subdevice = 0x9480, 682 .class = 0, 683 .class_mask = 0, 684 .driver_data = chip_9445, 685 }, 686 { 687 .vendor = 0x1b4b, 688 .device = 0x9485, 689 .subvendor = PCI_ANY_ID, 690 .subdevice = 0x9480, 691 .class = 0, 692 .class_mask = 0, 693 .driver_data = chip_9485, 694 }, 695 696 { } /* terminate list */ 697 }; 698 699 static struct pci_driver mvs_pci_driver = { 700 .name = DRV_NAME, 701 .id_table = mvs_pci_table, 702 .probe = mvs_pci_init, 703 .remove = __devexit_p(mvs_pci_remove), 704 }; 705 706 /* task handler */ 707 struct task_struct *mvs_th; 708 static int __init mvs_init(void) 709 { 710 int rc; 711 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 712 if (!mvs_stt) 713 return -ENOMEM; 714 715 mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list), 716 0, SLAB_HWCACHE_ALIGN, NULL); 717 if (!mvs_task_list_cache) { 718 rc = -ENOMEM; 719 mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__); 720 goto err_out; 721 } 722 723 rc = pci_register_driver(&mvs_pci_driver); 724 725 if (rc) 726 goto err_out; 727 728 return 0; 729 730 err_out: 731 sas_release_transport(mvs_stt); 732 return rc; 733 } 734 735 static void __exit mvs_exit(void) 736 { 737 pci_unregister_driver(&mvs_pci_driver); 738 sas_release_transport(mvs_stt); 739 kmem_cache_destroy(mvs_task_list_cache); 740 } 741 742 module_init(mvs_init); 743 module_exit(mvs_exit); 744 745 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 746 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 747 MODULE_VERSION(DRV_VERSION); 748 MODULE_LICENSE("GPL"); 749 #ifdef CONFIG_PCI 750 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 751 #endif 752