1 /* 2 * Marvell 88SE64xx hardware specific 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * 7 * This file is licensed under GPLv2. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 22 * USA 23 */ 24 25 #include "mv_sas.h" 26 #include "mv_64xx.h" 27 #include "mv_chips.h" 28 29 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i) 30 { 31 void __iomem *regs = mvi->regs; 32 u32 reg; 33 struct mvs_phy *phy = &mvi->phy[i]; 34 35 /* TODO check & save device type */ 36 reg = mr32(MVS_GBL_PORT_TYPE); 37 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 38 if (reg & MODE_SAS_SATA & (1 << i)) 39 phy->phy_type |= PORT_TYPE_SAS; 40 else 41 phy->phy_type |= PORT_TYPE_SATA; 42 } 43 44 static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id) 45 { 46 void __iomem *regs = mvi->regs; 47 u32 tmp; 48 49 tmp = mr32(MVS_PCS); 50 if (mvi->chip->n_phy <= 4) 51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); 52 else 53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); 54 mw32(MVS_PCS, tmp); 55 } 56 57 static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi) 58 { 59 void __iomem *regs = mvi->regs; 60 61 mvs_phy_hacks(mvi); 62 63 if (!(mvi->flags & MVF_FLAG_SOC)) { 64 /* TEST - for phy decoding error, adjust voltage levels */ 65 mw32(MVS_P0_VSR_ADDR + 0, 0x8); 66 mw32(MVS_P0_VSR_DATA + 0, 0x2F0); 67 68 mw32(MVS_P0_VSR_ADDR + 8, 0x8); 69 mw32(MVS_P0_VSR_DATA + 8, 0x2F0); 70 71 mw32(MVS_P0_VSR_ADDR + 16, 0x8); 72 mw32(MVS_P0_VSR_DATA + 16, 0x2F0); 73 74 mw32(MVS_P0_VSR_ADDR + 24, 0x8); 75 mw32(MVS_P0_VSR_DATA + 24, 0x2F0); 76 } else { 77 int i; 78 /* disable auto port detection */ 79 mw32(MVS_GBL_PORT_TYPE, 0); 80 for (i = 0; i < mvi->chip->n_phy; i++) { 81 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); 82 mvs_write_port_vsr_data(mvi, i, 0x90000000); 83 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); 84 mvs_write_port_vsr_data(mvi, i, 0x50f2); 85 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); 86 mvs_write_port_vsr_data(mvi, i, 0x0e); 87 } 88 } 89 } 90 91 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) 92 { 93 void __iomem *regs = mvi->regs; 94 u32 reg, tmp; 95 96 if (!(mvi->flags & MVF_FLAG_SOC)) { 97 if (phy_id < 4) 98 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®); 99 else 100 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®); 101 102 } else 103 reg = mr32(MVS_PHY_CTL); 104 105 tmp = reg; 106 if (phy_id < 4) 107 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; 108 else 109 tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS; 110 111 if (!(mvi->flags & MVF_FLAG_SOC)) { 112 if (phy_id < 4) { 113 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 114 mdelay(10); 115 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg); 116 } else { 117 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 118 mdelay(10); 119 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg); 120 } 121 } else { 122 mw32(MVS_PHY_CTL, tmp); 123 mdelay(10); 124 mw32(MVS_PHY_CTL, reg); 125 } 126 } 127 128 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 129 { 130 u32 tmp; 131 tmp = mvs_read_port_irq_stat(mvi, phy_id); 132 tmp &= ~PHYEV_RDY_CH; 133 mvs_write_port_irq_stat(mvi, phy_id, tmp); 134 tmp = mvs_read_phy_ctl(mvi, phy_id); 135 if (hard == 1) 136 tmp |= PHY_RST_HARD; 137 else if (hard == 0) 138 tmp |= PHY_RST; 139 mvs_write_phy_ctl(mvi, phy_id, tmp); 140 if (hard) { 141 do { 142 tmp = mvs_read_phy_ctl(mvi, phy_id); 143 } while (tmp & PHY_RST_HARD); 144 } 145 } 146 147 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) 148 { 149 void __iomem *regs = mvi->regs; 150 u32 tmp; 151 if (clear_all) { 152 tmp = mr32(MVS_INT_STAT_SRS_0); 153 if (tmp) { 154 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); 155 mw32(MVS_INT_STAT_SRS_0, tmp); 156 } 157 } else { 158 tmp = mr32(MVS_INT_STAT_SRS_0); 159 if (tmp & (1 << (reg_set % 32))) { 160 printk(KERN_DEBUG "register set 0x%x was stopped.\n", 161 reg_set); 162 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); 163 } 164 } 165 } 166 167 static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi) 168 { 169 void __iomem *regs = mvi->regs; 170 u32 tmp; 171 int i; 172 173 /* make sure interrupts are masked immediately (paranoia) */ 174 mw32(MVS_GBL_CTL, 0); 175 tmp = mr32(MVS_GBL_CTL); 176 177 /* Reset Controller */ 178 if (!(tmp & HBA_RST)) { 179 if (mvi->flags & MVF_PHY_PWR_FIX) { 180 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); 181 tmp &= ~PCTL_PWR_OFF; 182 tmp |= PCTL_PHY_DSBL; 183 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 184 185 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); 186 tmp &= ~PCTL_PWR_OFF; 187 tmp |= PCTL_PHY_DSBL; 188 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 189 } 190 } 191 192 /* make sure interrupts are masked immediately (paranoia) */ 193 mw32(MVS_GBL_CTL, 0); 194 tmp = mr32(MVS_GBL_CTL); 195 196 /* Reset Controller */ 197 if (!(tmp & HBA_RST)) { 198 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */ 199 mw32_f(MVS_GBL_CTL, HBA_RST); 200 } 201 202 /* wait for reset to finish; timeout is just a guess */ 203 i = 1000; 204 while (i-- > 0) { 205 msleep(10); 206 207 if (!(mr32(MVS_GBL_CTL) & HBA_RST)) 208 break; 209 } 210 if (mr32(MVS_GBL_CTL) & HBA_RST) { 211 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n"); 212 return -EBUSY; 213 } 214 return 0; 215 } 216 217 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id) 218 { 219 void __iomem *regs = mvi->regs; 220 u32 tmp; 221 if (!(mvi->flags & MVF_FLAG_SOC)) { 222 u32 offs; 223 if (phy_id < 4) 224 offs = PCR_PHY_CTL; 225 else { 226 offs = PCR_PHY_CTL2; 227 phy_id -= 4; 228 } 229 pci_read_config_dword(mvi->pdev, offs, &tmp); 230 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); 231 pci_write_config_dword(mvi->pdev, offs, tmp); 232 } else { 233 tmp = mr32(MVS_PHY_CTL); 234 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); 235 mw32(MVS_PHY_CTL, tmp); 236 } 237 } 238 239 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id) 240 { 241 void __iomem *regs = mvi->regs; 242 u32 tmp; 243 if (!(mvi->flags & MVF_FLAG_SOC)) { 244 u32 offs; 245 if (phy_id < 4) 246 offs = PCR_PHY_CTL; 247 else { 248 offs = PCR_PHY_CTL2; 249 phy_id -= 4; 250 } 251 pci_read_config_dword(mvi->pdev, offs, &tmp); 252 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); 253 pci_write_config_dword(mvi->pdev, offs, tmp); 254 } else { 255 tmp = mr32(MVS_PHY_CTL); 256 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); 257 mw32(MVS_PHY_CTL, tmp); 258 } 259 } 260 261 static int __devinit mvs_64xx_init(struct mvs_info *mvi) 262 { 263 void __iomem *regs = mvi->regs; 264 int i; 265 u32 tmp, cctl; 266 267 if (mvi->pdev && mvi->pdev->revision == 0) 268 mvi->flags |= MVF_PHY_PWR_FIX; 269 if (!(mvi->flags & MVF_FLAG_SOC)) { 270 mvs_show_pcie_usage(mvi); 271 tmp = mvs_64xx_chip_reset(mvi); 272 if (tmp) 273 return tmp; 274 } else { 275 tmp = mr32(MVS_PHY_CTL); 276 tmp &= ~PCTL_PWR_OFF; 277 tmp |= PCTL_PHY_DSBL; 278 mw32(MVS_PHY_CTL, tmp); 279 } 280 281 /* Init Chip */ 282 /* make sure RST is set; HBA_RST /should/ have done that for us */ 283 cctl = mr32(MVS_CTL) & 0xFFFF; 284 if (cctl & CCTL_RST) 285 cctl &= ~CCTL_RST; 286 else 287 mw32_f(MVS_CTL, cctl | CCTL_RST); 288 289 if (!(mvi->flags & MVF_FLAG_SOC)) { 290 /* write to device control _AND_ device status register */ 291 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); 292 tmp &= ~PRD_REQ_MASK; 293 tmp |= PRD_REQ_SIZE; 294 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); 295 296 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); 297 tmp &= ~PCTL_PWR_OFF; 298 tmp &= ~PCTL_PHY_DSBL; 299 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 300 301 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); 302 tmp &= PCTL_PWR_OFF; 303 tmp &= ~PCTL_PHY_DSBL; 304 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 305 } else { 306 tmp = mr32(MVS_PHY_CTL); 307 tmp &= ~PCTL_PWR_OFF; 308 tmp |= PCTL_COM_ON; 309 tmp &= ~PCTL_PHY_DSBL; 310 tmp |= PCTL_LINK_RST; 311 mw32(MVS_PHY_CTL, tmp); 312 msleep(100); 313 tmp &= ~PCTL_LINK_RST; 314 mw32(MVS_PHY_CTL, tmp); 315 msleep(100); 316 } 317 318 /* reset control */ 319 mw32(MVS_PCS, 0); /* MVS_PCS */ 320 /* init phys */ 321 mvs_64xx_phy_hacks(mvi); 322 323 /* enable auto port detection */ 324 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN); 325 326 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); 327 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); 328 329 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); 330 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); 331 332 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); 333 mw32(MVS_TX_LO, mvi->tx_dma); 334 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); 335 336 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); 337 mw32(MVS_RX_LO, mvi->rx_dma); 338 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); 339 340 for (i = 0; i < mvi->chip->n_phy; i++) { 341 /* set phy local SAS address */ 342 /* should set little endian SAS address to 64xx chip */ 343 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI, 344 cpu_to_be64(mvi->phy[i].dev_sas_addr)); 345 346 mvs_64xx_enable_xmt(mvi, i); 347 348 mvs_64xx_phy_reset(mvi, i, 1); 349 msleep(500); 350 mvs_64xx_detect_porttype(mvi, i); 351 } 352 if (mvi->flags & MVF_FLAG_SOC) { 353 /* set select registers */ 354 writel(0x0E008000, regs + 0x000); 355 writel(0x59000008, regs + 0x004); 356 writel(0x20, regs + 0x008); 357 writel(0x20, regs + 0x00c); 358 writel(0x20, regs + 0x010); 359 writel(0x20, regs + 0x014); 360 writel(0x20, regs + 0x018); 361 writel(0x20, regs + 0x01c); 362 } 363 for (i = 0; i < mvi->chip->n_phy; i++) { 364 /* clear phy int status */ 365 tmp = mvs_read_port_irq_stat(mvi, i); 366 tmp &= ~PHYEV_SIG_FIS; 367 mvs_write_port_irq_stat(mvi, i, tmp); 368 369 /* set phy int mask */ 370 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | 371 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR | 372 PHYEV_DEC_ERR; 373 mvs_write_port_irq_mask(mvi, i, tmp); 374 375 msleep(100); 376 mvs_update_phyinfo(mvi, i, 1); 377 } 378 379 /* FIXME: update wide port bitmaps */ 380 381 /* little endian for open address and command table, etc. */ 382 /* 383 * it seems that ( from the spec ) turning on big-endian won't 384 * do us any good on big-endian machines, need further confirmation 385 */ 386 cctl = mr32(MVS_CTL); 387 cctl |= CCTL_ENDIAN_CMD; 388 cctl |= CCTL_ENDIAN_DATA; 389 cctl &= ~CCTL_ENDIAN_OPEN; 390 cctl |= CCTL_ENDIAN_RSP; 391 mw32_f(MVS_CTL, cctl); 392 393 /* reset CMD queue */ 394 tmp = mr32(MVS_PCS); 395 tmp |= PCS_CMD_RST; 396 mw32(MVS_PCS, tmp); 397 /* interrupt coalescing may cause missing HW interrput in some case, 398 * and the max count is 0x1ff, while our max slot is 0x200, 399 * it will make count 0. 400 */ 401 tmp = 0; 402 mw32(MVS_INT_COAL, tmp); 403 404 tmp = 0x100; 405 mw32(MVS_INT_COAL_TMOUT, tmp); 406 407 /* ladies and gentlemen, start your engines */ 408 mw32(MVS_TX_CFG, 0); 409 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); 410 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); 411 /* enable CMD/CMPL_Q/RESP mode */ 412 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | 413 PCS_CMD_EN | PCS_CMD_STOP_ERR); 414 415 /* enable completion queue interrupt */ 416 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | 417 CINT_DMA_PCIE); 418 419 mw32(MVS_INT_MASK, tmp); 420 421 /* Enable SRS interrupt */ 422 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); 423 424 return 0; 425 } 426 427 static int mvs_64xx_ioremap(struct mvs_info *mvi) 428 { 429 if (!mvs_ioremap(mvi, 4, 2)) 430 return 0; 431 return -1; 432 } 433 434 static void mvs_64xx_iounmap(struct mvs_info *mvi) 435 { 436 mvs_iounmap(mvi->regs); 437 mvs_iounmap(mvi->regs_ex); 438 } 439 440 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi) 441 { 442 void __iomem *regs = mvi->regs; 443 u32 tmp; 444 445 tmp = mr32(MVS_GBL_CTL); 446 mw32(MVS_GBL_CTL, tmp | INT_EN); 447 } 448 449 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi) 450 { 451 void __iomem *regs = mvi->regs; 452 u32 tmp; 453 454 tmp = mr32(MVS_GBL_CTL); 455 mw32(MVS_GBL_CTL, tmp & ~INT_EN); 456 } 457 458 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq) 459 { 460 void __iomem *regs = mvi->regs; 461 u32 stat; 462 463 if (!(mvi->flags & MVF_FLAG_SOC)) { 464 stat = mr32(MVS_GBL_INT_STAT); 465 466 if (stat == 0 || stat == 0xffffffff) 467 return 0; 468 } else 469 stat = 1; 470 return stat; 471 } 472 473 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat) 474 { 475 void __iomem *regs = mvi->regs; 476 477 /* clear CMD_CMPLT ASAP */ 478 mw32_f(MVS_INT_STAT, CINT_DONE); 479 #ifndef MVS_USE_TASKLET 480 spin_lock(&mvi->lock); 481 #endif 482 mvs_int_full(mvi); 483 #ifndef MVS_USE_TASKLET 484 spin_unlock(&mvi->lock); 485 #endif 486 return IRQ_HANDLED; 487 } 488 489 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx) 490 { 491 u32 tmp; 492 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32)); 493 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32)); 494 do { 495 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); 496 } while (tmp & 1 << (slot_idx % 32)); 497 do { 498 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); 499 } while (tmp & 1 << (slot_idx % 32)); 500 } 501 502 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, 503 u32 tfs) 504 { 505 void __iomem *regs = mvi->regs; 506 u32 tmp; 507 508 if (type == PORT_TYPE_SATA) { 509 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); 510 mw32(MVS_INT_STAT_SRS_0, tmp); 511 } 512 mw32(MVS_INT_STAT, CINT_CI_STOP); 513 tmp = mr32(MVS_PCS) | 0xFF00; 514 mw32(MVS_PCS, tmp); 515 } 516 517 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) 518 { 519 void __iomem *regs = mvi->regs; 520 u32 tmp, offs; 521 522 if (*tfs == MVS_ID_NOT_MAPPED) 523 return; 524 525 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT); 526 if (*tfs < 16) { 527 tmp = mr32(MVS_PCS); 528 mw32(MVS_PCS, tmp & ~offs); 529 } else { 530 tmp = mr32(MVS_CTL); 531 mw32(MVS_CTL, tmp & ~offs); 532 } 533 534 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); 535 if (tmp) 536 mw32(MVS_INT_STAT_SRS_0, tmp); 537 538 *tfs = MVS_ID_NOT_MAPPED; 539 return; 540 } 541 542 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) 543 { 544 int i; 545 u32 tmp, offs; 546 void __iomem *regs = mvi->regs; 547 548 if (*tfs != MVS_ID_NOT_MAPPED) 549 return 0; 550 551 tmp = mr32(MVS_PCS); 552 553 for (i = 0; i < mvi->chip->srs_sz; i++) { 554 if (i == 16) 555 tmp = mr32(MVS_CTL); 556 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT); 557 if (!(tmp & offs)) { 558 *tfs = i; 559 560 if (i < 16) 561 mw32(MVS_PCS, tmp | offs); 562 else 563 mw32(MVS_CTL, tmp | offs); 564 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); 565 if (tmp) 566 mw32(MVS_INT_STAT_SRS_0, tmp); 567 return 0; 568 } 569 } 570 return MVS_ID_NOT_MAPPED; 571 } 572 573 void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd) 574 { 575 int i; 576 struct scatterlist *sg; 577 struct mvs_prd *buf_prd = prd; 578 for_each_sg(scatter, sg, nr, i) { 579 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 580 buf_prd->len = cpu_to_le32(sg_dma_len(sg)); 581 buf_prd++; 582 } 583 } 584 585 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i) 586 { 587 u32 phy_st; 588 mvs_write_port_cfg_addr(mvi, i, 589 PHYR_PHY_STAT); 590 phy_st = mvs_read_port_cfg_data(mvi, i); 591 if (phy_st & PHY_OOB_DTCTD) 592 return 1; 593 return 0; 594 } 595 596 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i, 597 struct sas_identify_frame *id) 598 599 { 600 struct mvs_phy *phy = &mvi->phy[i]; 601 struct asd_sas_phy *sas_phy = &phy->sas_phy; 602 603 sas_phy->linkrate = 604 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 605 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; 606 607 phy->minimum_linkrate = 608 (phy->phy_status & 609 PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8; 610 phy->maximum_linkrate = 611 (phy->phy_status & 612 PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12; 613 614 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY); 615 phy->dev_info = mvs_read_port_cfg_data(mvi, i); 616 617 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO); 618 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i); 619 620 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI); 621 phy->att_dev_sas_addr = 622 (u64) mvs_read_port_cfg_data(mvi, i) << 32; 623 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO); 624 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i); 625 phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr); 626 } 627 628 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i) 629 { 630 u32 tmp; 631 struct mvs_phy *phy = &mvi->phy[i]; 632 /* workaround for HW phy decoding error on 1.5g disk drive */ 633 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6); 634 tmp = mvs_read_port_vsr_data(mvi, i); 635 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 636 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) == 637 SAS_LINK_RATE_1_5_GBPS) 638 tmp &= ~PHY_MODE6_LATECLK; 639 else 640 tmp |= PHY_MODE6_LATECLK; 641 mvs_write_port_vsr_data(mvi, i, tmp); 642 } 643 644 void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 645 struct sas_phy_linkrates *rates) 646 { 647 u32 lrmin = 0, lrmax = 0; 648 u32 tmp; 649 650 tmp = mvs_read_phy_ctl(mvi, phy_id); 651 lrmin = (rates->minimum_linkrate << 8); 652 lrmax = (rates->maximum_linkrate << 12); 653 654 if (lrmin) { 655 tmp &= ~(0xf << 8); 656 tmp |= lrmin; 657 } 658 if (lrmax) { 659 tmp &= ~(0xf << 12); 660 tmp |= lrmax; 661 } 662 mvs_write_phy_ctl(mvi, phy_id, tmp); 663 mvs_64xx_phy_reset(mvi, phy_id, 1); 664 } 665 666 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi) 667 { 668 u32 tmp; 669 void __iomem *regs = mvi->regs; 670 tmp = mr32(MVS_PCS); 671 mw32(MVS_PCS, tmp & 0xFFFF); 672 mw32(MVS_PCS, tmp); 673 tmp = mr32(MVS_CTL); 674 mw32(MVS_CTL, tmp & 0xFFFF); 675 mw32(MVS_CTL, tmp); 676 } 677 678 679 u32 mvs_64xx_spi_read_data(struct mvs_info *mvi) 680 { 681 void __iomem *regs = mvi->regs_ex; 682 return ior32(SPI_DATA_REG_64XX); 683 } 684 685 void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data) 686 { 687 void __iomem *regs = mvi->regs_ex; 688 iow32(SPI_DATA_REG_64XX, data); 689 } 690 691 692 int mvs_64xx_spi_buildcmd(struct mvs_info *mvi, 693 u32 *dwCmd, 694 u8 cmd, 695 u8 read, 696 u8 length, 697 u32 addr 698 ) 699 { 700 u32 dwTmp; 701 702 dwTmp = ((u32)cmd << 24) | ((u32)length << 19); 703 if (read) 704 dwTmp |= 1U<<23; 705 706 if (addr != MV_MAX_U32) { 707 dwTmp |= 1U<<22; 708 dwTmp |= (addr & 0x0003FFFF); 709 } 710 711 *dwCmd = dwTmp; 712 return 0; 713 } 714 715 716 int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) 717 { 718 void __iomem *regs = mvi->regs_ex; 719 int retry; 720 721 for (retry = 0; retry < 1; retry++) { 722 iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE); 723 iow32(SPI_CMD_REG_64XX, cmd); 724 iow32(SPI_CTRL_REG_64XX, 725 SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART); 726 } 727 728 return 0; 729 } 730 731 int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) 732 { 733 void __iomem *regs = mvi->regs_ex; 734 u32 i, dwTmp; 735 736 for (i = 0; i < timeout; i++) { 737 dwTmp = ior32(SPI_CTRL_REG_64XX); 738 if (!(dwTmp & SPI_CTRL_SPISTART)) 739 return 0; 740 msleep(10); 741 } 742 743 return -1; 744 } 745 746 #ifndef DISABLE_HOTPLUG_DMA_FIX 747 void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd) 748 { 749 int i; 750 struct mvs_prd *buf_prd = prd; 751 buf_prd += from; 752 for (i = 0; i < MAX_SG_ENTRY - from; i++) { 753 buf_prd->addr = cpu_to_le64(buf_dma); 754 buf_prd->len = cpu_to_le32(buf_len); 755 ++buf_prd; 756 } 757 } 758 #endif 759 760 const struct mvs_dispatch mvs_64xx_dispatch = { 761 "mv64xx", 762 mvs_64xx_init, 763 NULL, 764 mvs_64xx_ioremap, 765 mvs_64xx_iounmap, 766 mvs_64xx_isr, 767 mvs_64xx_isr_status, 768 mvs_64xx_interrupt_enable, 769 mvs_64xx_interrupt_disable, 770 mvs_read_phy_ctl, 771 mvs_write_phy_ctl, 772 mvs_read_port_cfg_data, 773 mvs_write_port_cfg_data, 774 mvs_write_port_cfg_addr, 775 mvs_read_port_vsr_data, 776 mvs_write_port_vsr_data, 777 mvs_write_port_vsr_addr, 778 mvs_read_port_irq_stat, 779 mvs_write_port_irq_stat, 780 mvs_read_port_irq_mask, 781 mvs_write_port_irq_mask, 782 mvs_get_sas_addr, 783 mvs_64xx_command_active, 784 mvs_64xx_clear_srs_irq, 785 mvs_64xx_issue_stop, 786 mvs_start_delivery, 787 mvs_rx_update, 788 mvs_int_full, 789 mvs_64xx_assign_reg_set, 790 mvs_64xx_free_reg_set, 791 mvs_get_prd_size, 792 mvs_get_prd_count, 793 mvs_64xx_make_prd, 794 mvs_64xx_detect_porttype, 795 mvs_64xx_oob_done, 796 mvs_64xx_fix_phy_info, 797 mvs_64xx_phy_work_around, 798 mvs_64xx_phy_set_link_rate, 799 mvs_hw_max_link_rate, 800 mvs_64xx_phy_disable, 801 mvs_64xx_phy_enable, 802 mvs_64xx_phy_reset, 803 mvs_64xx_stp_reset, 804 mvs_64xx_clear_active_cmds, 805 mvs_64xx_spi_read_data, 806 mvs_64xx_spi_write_data, 807 mvs_64xx_spi_buildcmd, 808 mvs_64xx_spi_issuecmd, 809 mvs_64xx_spi_waitdataready, 810 #ifndef DISABLE_HOTPLUG_DMA_FIX 811 mvs_64xx_fix_dma, 812 #endif 813 }; 814 815