1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/kthread.h> 61 #include <linux/aer.h> 62 63 64 #include "mpt3sas_base.h" 65 66 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 67 68 69 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 70 71 /* maximum controller queue depth */ 72 #define MAX_HBA_QUEUE_DEPTH 30000 73 #define MAX_CHAIN_DEPTH 100000 74 static int max_queue_depth = -1; 75 module_param(max_queue_depth, int, 0); 76 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 77 78 static int max_sgl_entries = -1; 79 module_param(max_sgl_entries, int, 0); 80 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 81 82 static int msix_disable = -1; 83 module_param(msix_disable, int, 0); 84 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 85 86 static int max_msix_vectors = -1; 87 module_param(max_msix_vectors, int, 0); 88 MODULE_PARM_DESC(max_msix_vectors, 89 " max msix vectors"); 90 91 static int mpt3sas_fwfault_debug; 92 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 93 " enable detection of firmware fault and halt firmware - (default=0)"); 94 95 static int 96 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag); 97 98 /** 99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 100 * 101 */ 102 static int 103 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp) 104 { 105 int ret = param_set_int(val, kp); 106 struct MPT3SAS_ADAPTER *ioc; 107 108 if (ret) 109 return ret; 110 111 /* global ioc spinlock to protect controller list on list operations */ 112 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 113 spin_lock(&gioc_lock); 114 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 115 ioc->fwfault_debug = mpt3sas_fwfault_debug; 116 spin_unlock(&gioc_lock); 117 return 0; 118 } 119 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 120 param_get_int, &mpt3sas_fwfault_debug, 0644); 121 122 /** 123 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 124 * @arg: input argument, used to derive ioc 125 * 126 * Return 0 if controller is removed from pci subsystem. 127 * Return -1 for other case. 128 */ 129 static int mpt3sas_remove_dead_ioc_func(void *arg) 130 { 131 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 132 struct pci_dev *pdev; 133 134 if ((ioc == NULL)) 135 return -1; 136 137 pdev = ioc->pdev; 138 if ((pdev == NULL)) 139 return -1; 140 pci_stop_and_remove_bus_device_locked(pdev); 141 return 0; 142 } 143 144 /** 145 * _base_fault_reset_work - workq handling ioc fault conditions 146 * @work: input argument, used to derive ioc 147 * Context: sleep. 148 * 149 * Return nothing. 150 */ 151 static void 152 _base_fault_reset_work(struct work_struct *work) 153 { 154 struct MPT3SAS_ADAPTER *ioc = 155 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 156 unsigned long flags; 157 u32 doorbell; 158 int rc; 159 struct task_struct *p; 160 161 162 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 163 if (ioc->shost_recovery || ioc->pci_error_recovery) 164 goto rearm_timer; 165 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 166 167 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 168 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 169 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", 170 ioc->name); 171 172 /* It may be possible that EEH recovery can resolve some of 173 * pci bus failure issues rather removing the dead ioc function 174 * by considering controller is in a non-operational state. So 175 * here priority is given to the EEH recovery. If it doesn't 176 * not resolve this issue, mpt3sas driver will consider this 177 * controller to non-operational state and remove the dead ioc 178 * function. 179 */ 180 if (ioc->non_operational_loop++ < 5) { 181 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 182 flags); 183 goto rearm_timer; 184 } 185 186 /* 187 * Call _scsih_flush_pending_cmds callback so that we flush all 188 * pending commands back to OS. This call is required to aovid 189 * deadlock at block layer. Dead IOC will fail to do diag reset, 190 * and this call is safe since dead ioc will never return any 191 * command back from HW. 192 */ 193 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 194 /* 195 * Set remove_host flag early since kernel thread will 196 * take some time to execute. 197 */ 198 ioc->remove_host = 1; 199 /*Remove the Dead Host */ 200 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 201 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 202 if (IS_ERR(p)) 203 pr_err(MPT3SAS_FMT 204 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 205 ioc->name, __func__); 206 else 207 pr_err(MPT3SAS_FMT 208 "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 209 ioc->name, __func__); 210 return; /* don't rearm timer */ 211 } 212 213 ioc->non_operational_loop = 0; 214 215 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 216 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 217 FORCE_BIG_HAMMER); 218 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, 219 __func__, (rc == 0) ? "success" : "failed"); 220 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 221 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 222 mpt3sas_base_fault_info(ioc, doorbell & 223 MPI2_DOORBELL_DATA_MASK); 224 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 225 MPI2_IOC_STATE_OPERATIONAL) 226 return; /* don't rearm timer */ 227 } 228 229 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 230 rearm_timer: 231 if (ioc->fault_reset_work_q) 232 queue_delayed_work(ioc->fault_reset_work_q, 233 &ioc->fault_reset_work, 234 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 235 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 236 } 237 238 /** 239 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 240 * @ioc: per adapter object 241 * Context: sleep. 242 * 243 * Return nothing. 244 */ 245 void 246 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 247 { 248 unsigned long flags; 249 250 if (ioc->fault_reset_work_q) 251 return; 252 253 /* initialize fault polling */ 254 255 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 256 snprintf(ioc->fault_reset_work_q_name, 257 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 258 ioc->driver_name, ioc->id); 259 ioc->fault_reset_work_q = 260 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 261 if (!ioc->fault_reset_work_q) { 262 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", 263 ioc->name, __func__, __LINE__); 264 return; 265 } 266 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 267 if (ioc->fault_reset_work_q) 268 queue_delayed_work(ioc->fault_reset_work_q, 269 &ioc->fault_reset_work, 270 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 271 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 272 } 273 274 /** 275 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 276 * @ioc: per adapter object 277 * Context: sleep. 278 * 279 * Return nothing. 280 */ 281 void 282 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 283 { 284 unsigned long flags; 285 struct workqueue_struct *wq; 286 287 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 288 wq = ioc->fault_reset_work_q; 289 ioc->fault_reset_work_q = NULL; 290 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 291 if (wq) { 292 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 293 flush_workqueue(wq); 294 destroy_workqueue(wq); 295 } 296 } 297 298 /** 299 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 300 * @ioc: per adapter object 301 * @fault_code: fault code 302 * 303 * Return nothing. 304 */ 305 void 306 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 307 { 308 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", 309 ioc->name, fault_code); 310 } 311 312 /** 313 * mpt3sas_halt_firmware - halt's mpt controller firmware 314 * @ioc: per adapter object 315 * 316 * For debugging timeout related issues. Writing 0xCOFFEE00 317 * to the doorbell register will halt controller firmware. With 318 * the purpose to stop both driver and firmware, the enduser can 319 * obtain a ring buffer from controller UART. 320 */ 321 void 322 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 323 { 324 u32 doorbell; 325 326 if (!ioc->fwfault_debug) 327 return; 328 329 dump_stack(); 330 331 doorbell = readl(&ioc->chip->Doorbell); 332 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 333 mpt3sas_base_fault_info(ioc , doorbell); 334 else { 335 writel(0xC0FFEE00, &ioc->chip->Doorbell); 336 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", 337 ioc->name); 338 } 339 340 if (ioc->fwfault_debug == 2) 341 for (;;) 342 ; 343 else 344 panic("panic in %s\n", __func__); 345 } 346 347 /** 348 * _base_sas_ioc_info - verbose translation of the ioc status 349 * @ioc: per adapter object 350 * @mpi_reply: reply mf payload returned from firmware 351 * @request_hdr: request mf 352 * 353 * Return nothing. 354 */ 355 static void 356 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 357 MPI2RequestHeader_t *request_hdr) 358 { 359 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 360 MPI2_IOCSTATUS_MASK; 361 char *desc = NULL; 362 u16 frame_sz; 363 char *func_str = NULL; 364 365 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 366 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 367 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 368 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 369 return; 370 371 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 372 return; 373 374 switch (ioc_status) { 375 376 /**************************************************************************** 377 * Common IOCStatus values for all replies 378 ****************************************************************************/ 379 380 case MPI2_IOCSTATUS_INVALID_FUNCTION: 381 desc = "invalid function"; 382 break; 383 case MPI2_IOCSTATUS_BUSY: 384 desc = "busy"; 385 break; 386 case MPI2_IOCSTATUS_INVALID_SGL: 387 desc = "invalid sgl"; 388 break; 389 case MPI2_IOCSTATUS_INTERNAL_ERROR: 390 desc = "internal error"; 391 break; 392 case MPI2_IOCSTATUS_INVALID_VPID: 393 desc = "invalid vpid"; 394 break; 395 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 396 desc = "insufficient resources"; 397 break; 398 case MPI2_IOCSTATUS_INVALID_FIELD: 399 desc = "invalid field"; 400 break; 401 case MPI2_IOCSTATUS_INVALID_STATE: 402 desc = "invalid state"; 403 break; 404 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 405 desc = "op state not supported"; 406 break; 407 408 /**************************************************************************** 409 * Config IOCStatus values 410 ****************************************************************************/ 411 412 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 413 desc = "config invalid action"; 414 break; 415 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 416 desc = "config invalid type"; 417 break; 418 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 419 desc = "config invalid page"; 420 break; 421 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 422 desc = "config invalid data"; 423 break; 424 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 425 desc = "config no defaults"; 426 break; 427 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 428 desc = "config cant commit"; 429 break; 430 431 /**************************************************************************** 432 * SCSI IO Reply 433 ****************************************************************************/ 434 435 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 436 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 437 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 438 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 439 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 440 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 441 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 442 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 443 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 444 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 445 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 446 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 447 break; 448 449 /**************************************************************************** 450 * For use by SCSI Initiator and SCSI Target end-to-end data protection 451 ****************************************************************************/ 452 453 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 454 desc = "eedp guard error"; 455 break; 456 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 457 desc = "eedp ref tag error"; 458 break; 459 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 460 desc = "eedp app tag error"; 461 break; 462 463 /**************************************************************************** 464 * SCSI Target values 465 ****************************************************************************/ 466 467 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 468 desc = "target invalid io index"; 469 break; 470 case MPI2_IOCSTATUS_TARGET_ABORTED: 471 desc = "target aborted"; 472 break; 473 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 474 desc = "target no conn retryable"; 475 break; 476 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 477 desc = "target no connection"; 478 break; 479 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 480 desc = "target xfer count mismatch"; 481 break; 482 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 483 desc = "target data offset error"; 484 break; 485 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 486 desc = "target too much write data"; 487 break; 488 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 489 desc = "target iu too short"; 490 break; 491 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 492 desc = "target ack nak timeout"; 493 break; 494 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 495 desc = "target nak received"; 496 break; 497 498 /**************************************************************************** 499 * Serial Attached SCSI values 500 ****************************************************************************/ 501 502 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 503 desc = "smp request failed"; 504 break; 505 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 506 desc = "smp data overrun"; 507 break; 508 509 /**************************************************************************** 510 * Diagnostic Buffer Post / Diagnostic Release values 511 ****************************************************************************/ 512 513 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 514 desc = "diagnostic released"; 515 break; 516 default: 517 break; 518 } 519 520 if (!desc) 521 return; 522 523 switch (request_hdr->Function) { 524 case MPI2_FUNCTION_CONFIG: 525 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 526 func_str = "config_page"; 527 break; 528 case MPI2_FUNCTION_SCSI_TASK_MGMT: 529 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 530 func_str = "task_mgmt"; 531 break; 532 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 533 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 534 func_str = "sas_iounit_ctl"; 535 break; 536 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 537 frame_sz = sizeof(Mpi2SepRequest_t); 538 func_str = "enclosure"; 539 break; 540 case MPI2_FUNCTION_IOC_INIT: 541 frame_sz = sizeof(Mpi2IOCInitRequest_t); 542 func_str = "ioc_init"; 543 break; 544 case MPI2_FUNCTION_PORT_ENABLE: 545 frame_sz = sizeof(Mpi2PortEnableRequest_t); 546 func_str = "port_enable"; 547 break; 548 case MPI2_FUNCTION_SMP_PASSTHROUGH: 549 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 550 func_str = "smp_passthru"; 551 break; 552 default: 553 frame_sz = 32; 554 func_str = "unknown"; 555 break; 556 } 557 558 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 559 ioc->name, desc, ioc_status, request_hdr, func_str); 560 561 _debug_dump_mf(request_hdr, frame_sz/4); 562 } 563 564 /** 565 * _base_display_event_data - verbose translation of firmware asyn events 566 * @ioc: per adapter object 567 * @mpi_reply: reply mf payload returned from firmware 568 * 569 * Return nothing. 570 */ 571 static void 572 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 573 Mpi2EventNotificationReply_t *mpi_reply) 574 { 575 char *desc = NULL; 576 u16 event; 577 578 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 579 return; 580 581 event = le16_to_cpu(mpi_reply->Event); 582 583 switch (event) { 584 case MPI2_EVENT_LOG_DATA: 585 desc = "Log Data"; 586 break; 587 case MPI2_EVENT_STATE_CHANGE: 588 desc = "Status Change"; 589 break; 590 case MPI2_EVENT_HARD_RESET_RECEIVED: 591 desc = "Hard Reset Received"; 592 break; 593 case MPI2_EVENT_EVENT_CHANGE: 594 desc = "Event Change"; 595 break; 596 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 597 desc = "Device Status Change"; 598 break; 599 case MPI2_EVENT_IR_OPERATION_STATUS: 600 if (!ioc->hide_ir_msg) 601 desc = "IR Operation Status"; 602 break; 603 case MPI2_EVENT_SAS_DISCOVERY: 604 { 605 Mpi2EventDataSasDiscovery_t *event_data = 606 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 607 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, 608 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? 609 "start" : "stop"); 610 if (event_data->DiscoveryStatus) 611 pr_info("discovery_status(0x%08x)", 612 le32_to_cpu(event_data->DiscoveryStatus)); 613 pr_info("\n"); 614 return; 615 } 616 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 617 desc = "SAS Broadcast Primitive"; 618 break; 619 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 620 desc = "SAS Init Device Status Change"; 621 break; 622 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 623 desc = "SAS Init Table Overflow"; 624 break; 625 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 626 desc = "SAS Topology Change List"; 627 break; 628 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 629 desc = "SAS Enclosure Device Status Change"; 630 break; 631 case MPI2_EVENT_IR_VOLUME: 632 if (!ioc->hide_ir_msg) 633 desc = "IR Volume"; 634 break; 635 case MPI2_EVENT_IR_PHYSICAL_DISK: 636 if (!ioc->hide_ir_msg) 637 desc = "IR Physical Disk"; 638 break; 639 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 640 if (!ioc->hide_ir_msg) 641 desc = "IR Configuration Change List"; 642 break; 643 case MPI2_EVENT_LOG_ENTRY_ADDED: 644 if (!ioc->hide_ir_msg) 645 desc = "Log Entry Added"; 646 break; 647 case MPI2_EVENT_TEMP_THRESHOLD: 648 desc = "Temperature Threshold"; 649 break; 650 } 651 652 if (!desc) 653 return; 654 655 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); 656 } 657 658 /** 659 * _base_sas_log_info - verbose translation of firmware log info 660 * @ioc: per adapter object 661 * @log_info: log info 662 * 663 * Return nothing. 664 */ 665 static void 666 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 667 { 668 union loginfo_type { 669 u32 loginfo; 670 struct { 671 u32 subcode:16; 672 u32 code:8; 673 u32 originator:4; 674 u32 bus_type:4; 675 } dw; 676 }; 677 union loginfo_type sas_loginfo; 678 char *originator_str = NULL; 679 680 sas_loginfo.loginfo = log_info; 681 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 682 return; 683 684 /* each nexus loss loginfo */ 685 if (log_info == 0x31170000) 686 return; 687 688 /* eat the loginfos associated with task aborts */ 689 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 690 0x31140000 || log_info == 0x31130000)) 691 return; 692 693 switch (sas_loginfo.dw.originator) { 694 case 0: 695 originator_str = "IOP"; 696 break; 697 case 1: 698 originator_str = "PL"; 699 break; 700 case 2: 701 if (!ioc->hide_ir_msg) 702 originator_str = "IR"; 703 else 704 originator_str = "WarpDrive"; 705 break; 706 } 707 708 pr_warn(MPT3SAS_FMT 709 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 710 ioc->name, log_info, 711 originator_str, sas_loginfo.dw.code, 712 sas_loginfo.dw.subcode); 713 } 714 715 /** 716 * _base_display_reply_info - 717 * @ioc: per adapter object 718 * @smid: system request message index 719 * @msix_index: MSIX table index supplied by the OS 720 * @reply: reply message frame(lower 32bit addr) 721 * 722 * Return nothing. 723 */ 724 static void 725 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 726 u32 reply) 727 { 728 MPI2DefaultReply_t *mpi_reply; 729 u16 ioc_status; 730 u32 loginfo = 0; 731 732 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 733 if (unlikely(!mpi_reply)) { 734 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", 735 ioc->name, __FILE__, __LINE__, __func__); 736 return; 737 } 738 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 739 740 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 741 (ioc->logging_level & MPT_DEBUG_REPLY)) { 742 _base_sas_ioc_info(ioc , mpi_reply, 743 mpt3sas_base_get_msg_frame(ioc, smid)); 744 } 745 746 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 747 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 748 _base_sas_log_info(ioc, loginfo); 749 } 750 751 if (ioc_status || loginfo) { 752 ioc_status &= MPI2_IOCSTATUS_MASK; 753 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 754 } 755 } 756 757 /** 758 * mpt3sas_base_done - base internal command completion routine 759 * @ioc: per adapter object 760 * @smid: system request message index 761 * @msix_index: MSIX table index supplied by the OS 762 * @reply: reply message frame(lower 32bit addr) 763 * 764 * Return 1 meaning mf should be freed from _base_interrupt 765 * 0 means the mf is freed from this function. 766 */ 767 u8 768 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 769 u32 reply) 770 { 771 MPI2DefaultReply_t *mpi_reply; 772 773 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 774 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 775 return 1; 776 777 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 778 return 1; 779 780 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 781 if (mpi_reply) { 782 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 783 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 784 } 785 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 786 787 complete(&ioc->base_cmds.done); 788 return 1; 789 } 790 791 /** 792 * _base_async_event - main callback handler for firmware asyn events 793 * @ioc: per adapter object 794 * @msix_index: MSIX table index supplied by the OS 795 * @reply: reply message frame(lower 32bit addr) 796 * 797 * Return 1 meaning mf should be freed from _base_interrupt 798 * 0 means the mf is freed from this function. 799 */ 800 static u8 801 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 802 { 803 Mpi2EventNotificationReply_t *mpi_reply; 804 Mpi2EventAckRequest_t *ack_request; 805 u16 smid; 806 807 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 808 if (!mpi_reply) 809 return 1; 810 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 811 return 1; 812 813 _base_display_event_data(ioc, mpi_reply); 814 815 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 816 goto out; 817 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 818 if (!smid) { 819 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 820 ioc->name, __func__); 821 goto out; 822 } 823 824 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 825 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 826 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 827 ack_request->Event = mpi_reply->Event; 828 ack_request->EventContext = mpi_reply->EventContext; 829 ack_request->VF_ID = 0; /* TODO */ 830 ack_request->VP_ID = 0; 831 mpt3sas_base_put_smid_default(ioc, smid); 832 833 out: 834 835 /* scsih callback handler */ 836 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 837 838 /* ctl callback handler */ 839 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 840 841 return 1; 842 } 843 844 /** 845 * _base_get_cb_idx - obtain the callback index 846 * @ioc: per adapter object 847 * @smid: system request message index 848 * 849 * Return callback index. 850 */ 851 static u8 852 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 853 { 854 int i; 855 u8 cb_idx; 856 857 if (smid < ioc->hi_priority_smid) { 858 i = smid - 1; 859 cb_idx = ioc->scsi_lookup[i].cb_idx; 860 } else if (smid < ioc->internal_smid) { 861 i = smid - ioc->hi_priority_smid; 862 cb_idx = ioc->hpr_lookup[i].cb_idx; 863 } else if (smid <= ioc->hba_queue_depth) { 864 i = smid - ioc->internal_smid; 865 cb_idx = ioc->internal_lookup[i].cb_idx; 866 } else 867 cb_idx = 0xFF; 868 return cb_idx; 869 } 870 871 /** 872 * _base_mask_interrupts - disable interrupts 873 * @ioc: per adapter object 874 * 875 * Disabling ResetIRQ, Reply and Doorbell Interrupts 876 * 877 * Return nothing. 878 */ 879 static void 880 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 881 { 882 u32 him_register; 883 884 ioc->mask_interrupts = 1; 885 him_register = readl(&ioc->chip->HostInterruptMask); 886 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 887 writel(him_register, &ioc->chip->HostInterruptMask); 888 readl(&ioc->chip->HostInterruptMask); 889 } 890 891 /** 892 * _base_unmask_interrupts - enable interrupts 893 * @ioc: per adapter object 894 * 895 * Enabling only Reply Interrupts 896 * 897 * Return nothing. 898 */ 899 static void 900 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 901 { 902 u32 him_register; 903 904 him_register = readl(&ioc->chip->HostInterruptMask); 905 him_register &= ~MPI2_HIM_RIM; 906 writel(him_register, &ioc->chip->HostInterruptMask); 907 ioc->mask_interrupts = 0; 908 } 909 910 union reply_descriptor { 911 u64 word; 912 struct { 913 u32 low; 914 u32 high; 915 } u; 916 }; 917 918 /** 919 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 920 * @irq: irq number (not used) 921 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 922 * @r: pt_regs pointer (not used) 923 * 924 * Return IRQ_HANDLE if processed, else IRQ_NONE. 925 */ 926 static irqreturn_t 927 _base_interrupt(int irq, void *bus_id) 928 { 929 struct adapter_reply_queue *reply_q = bus_id; 930 union reply_descriptor rd; 931 u32 completed_cmds; 932 u8 request_desript_type; 933 u16 smid; 934 u8 cb_idx; 935 u32 reply; 936 u8 msix_index = reply_q->msix_index; 937 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 938 Mpi2ReplyDescriptorsUnion_t *rpf; 939 u8 rc; 940 941 if (ioc->mask_interrupts) 942 return IRQ_NONE; 943 944 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 945 return IRQ_NONE; 946 947 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 948 request_desript_type = rpf->Default.ReplyFlags 949 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 950 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 951 atomic_dec(&reply_q->busy); 952 return IRQ_NONE; 953 } 954 955 completed_cmds = 0; 956 cb_idx = 0xFF; 957 do { 958 rd.word = le64_to_cpu(rpf->Words); 959 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 960 goto out; 961 reply = 0; 962 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 963 if (request_desript_type == 964 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 965 request_desript_type == 966 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 967 cb_idx = _base_get_cb_idx(ioc, smid); 968 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 969 (likely(mpt_callbacks[cb_idx] != NULL))) { 970 rc = mpt_callbacks[cb_idx](ioc, smid, 971 msix_index, 0); 972 if (rc) 973 mpt3sas_base_free_smid(ioc, smid); 974 } 975 } else if (request_desript_type == 976 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 977 reply = le32_to_cpu( 978 rpf->AddressReply.ReplyFrameAddress); 979 if (reply > ioc->reply_dma_max_address || 980 reply < ioc->reply_dma_min_address) 981 reply = 0; 982 if (smid) { 983 cb_idx = _base_get_cb_idx(ioc, smid); 984 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 985 (likely(mpt_callbacks[cb_idx] != NULL))) { 986 rc = mpt_callbacks[cb_idx](ioc, smid, 987 msix_index, reply); 988 if (reply) 989 _base_display_reply_info(ioc, 990 smid, msix_index, reply); 991 if (rc) 992 mpt3sas_base_free_smid(ioc, 993 smid); 994 } 995 } else { 996 _base_async_event(ioc, msix_index, reply); 997 } 998 999 /* reply free queue handling */ 1000 if (reply) { 1001 ioc->reply_free_host_index = 1002 (ioc->reply_free_host_index == 1003 (ioc->reply_free_queue_depth - 1)) ? 1004 0 : ioc->reply_free_host_index + 1; 1005 ioc->reply_free[ioc->reply_free_host_index] = 1006 cpu_to_le32(reply); 1007 wmb(); 1008 writel(ioc->reply_free_host_index, 1009 &ioc->chip->ReplyFreeHostIndex); 1010 } 1011 } 1012 1013 rpf->Words = cpu_to_le64(ULLONG_MAX); 1014 reply_q->reply_post_host_index = 1015 (reply_q->reply_post_host_index == 1016 (ioc->reply_post_queue_depth - 1)) ? 0 : 1017 reply_q->reply_post_host_index + 1; 1018 request_desript_type = 1019 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1020 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1021 completed_cmds++; 1022 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1023 goto out; 1024 if (!reply_q->reply_post_host_index) 1025 rpf = reply_q->reply_post_free; 1026 else 1027 rpf++; 1028 } while (1); 1029 1030 out: 1031 1032 if (!completed_cmds) { 1033 atomic_dec(&reply_q->busy); 1034 return IRQ_NONE; 1035 } 1036 1037 wmb(); 1038 if (ioc->is_warpdrive) { 1039 writel(reply_q->reply_post_host_index, 1040 ioc->reply_post_host_index[msix_index]); 1041 atomic_dec(&reply_q->busy); 1042 return IRQ_HANDLED; 1043 } 1044 1045 /* Update Reply Post Host Index. 1046 * For those HBA's which support combined reply queue feature 1047 * 1. Get the correct Supplemental Reply Post Host Index Register. 1048 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1049 * Index Register address bank i.e replyPostRegisterIndex[], 1050 * 2. Then update this register with new reply host index value 1051 * in ReplyPostIndex field and the MSIxIndex field with 1052 * msix_index value reduced to a value between 0 and 7, 1053 * using a modulo 8 operation. Since each Supplemental Reply Post 1054 * Host Index Register supports 8 MSI-X vectors. 1055 * 1056 * For other HBA's just update the Reply Post Host Index register with 1057 * new reply host index value in ReplyPostIndex Field and msix_index 1058 * value in MSIxIndex field. 1059 */ 1060 if (ioc->msix96_vector) 1061 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1062 MPI2_RPHI_MSIX_INDEX_SHIFT), 1063 ioc->replyPostRegisterIndex[msix_index/8]); 1064 else 1065 writel(reply_q->reply_post_host_index | (msix_index << 1066 MPI2_RPHI_MSIX_INDEX_SHIFT), 1067 &ioc->chip->ReplyPostHostIndex); 1068 atomic_dec(&reply_q->busy); 1069 return IRQ_HANDLED; 1070 } 1071 1072 /** 1073 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1074 * @ioc: per adapter object 1075 * 1076 */ 1077 static inline int 1078 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1079 { 1080 return (ioc->facts.IOCCapabilities & 1081 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1082 } 1083 1084 /** 1085 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues 1086 * @ioc: per adapter object 1087 * Context: ISR conext 1088 * 1089 * Called when a Task Management request has completed. We want 1090 * to flush the other reply queues so all the outstanding IO has been 1091 * completed back to OS before we process the TM completetion. 1092 * 1093 * Return nothing. 1094 */ 1095 void 1096 mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1097 { 1098 struct adapter_reply_queue *reply_q; 1099 1100 /* If MSIX capability is turned off 1101 * then multi-queues are not enabled 1102 */ 1103 if (!_base_is_controller_msix_enabled(ioc)) 1104 return; 1105 1106 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1107 if (ioc->shost_recovery) 1108 return; 1109 /* TMs are on msix_index == 0 */ 1110 if (reply_q->msix_index == 0) 1111 continue; 1112 _base_interrupt(reply_q->vector, (void *)reply_q); 1113 } 1114 } 1115 1116 /** 1117 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 1118 * @cb_idx: callback index 1119 * 1120 * Return nothing. 1121 */ 1122 void 1123 mpt3sas_base_release_callback_handler(u8 cb_idx) 1124 { 1125 mpt_callbacks[cb_idx] = NULL; 1126 } 1127 1128 /** 1129 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 1130 * @cb_func: callback function 1131 * 1132 * Returns cb_func. 1133 */ 1134 u8 1135 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 1136 { 1137 u8 cb_idx; 1138 1139 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 1140 if (mpt_callbacks[cb_idx] == NULL) 1141 break; 1142 1143 mpt_callbacks[cb_idx] = cb_func; 1144 return cb_idx; 1145 } 1146 1147 /** 1148 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 1149 * 1150 * Return nothing. 1151 */ 1152 void 1153 mpt3sas_base_initialize_callback_handler(void) 1154 { 1155 u8 cb_idx; 1156 1157 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 1158 mpt3sas_base_release_callback_handler(cb_idx); 1159 } 1160 1161 1162 /** 1163 * _base_build_zero_len_sge - build zero length sg entry 1164 * @ioc: per adapter object 1165 * @paddr: virtual address for SGE 1166 * 1167 * Create a zero length scatter gather entry to insure the IOCs hardware has 1168 * something to use if the target device goes brain dead and tries 1169 * to send data even when none is asked for. 1170 * 1171 * Return nothing. 1172 */ 1173 static void 1174 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1175 { 1176 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 1177 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 1178 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 1179 MPI2_SGE_FLAGS_SHIFT); 1180 ioc->base_add_sg_single(paddr, flags_length, -1); 1181 } 1182 1183 /** 1184 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 1185 * @paddr: virtual address for SGE 1186 * @flags_length: SGE flags and data transfer length 1187 * @dma_addr: Physical address 1188 * 1189 * Return nothing. 1190 */ 1191 static void 1192 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1193 { 1194 Mpi2SGESimple32_t *sgel = paddr; 1195 1196 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 1197 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1198 sgel->FlagsLength = cpu_to_le32(flags_length); 1199 sgel->Address = cpu_to_le32(dma_addr); 1200 } 1201 1202 1203 /** 1204 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 1205 * @paddr: virtual address for SGE 1206 * @flags_length: SGE flags and data transfer length 1207 * @dma_addr: Physical address 1208 * 1209 * Return nothing. 1210 */ 1211 static void 1212 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1213 { 1214 Mpi2SGESimple64_t *sgel = paddr; 1215 1216 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 1217 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1218 sgel->FlagsLength = cpu_to_le32(flags_length); 1219 sgel->Address = cpu_to_le64(dma_addr); 1220 } 1221 1222 /** 1223 * _base_get_chain_buffer_tracker - obtain chain tracker 1224 * @ioc: per adapter object 1225 * @smid: smid associated to an IO request 1226 * 1227 * Returns chain tracker(from ioc->free_chain_list) 1228 */ 1229 static struct chain_tracker * 1230 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1231 { 1232 struct chain_tracker *chain_req; 1233 unsigned long flags; 1234 1235 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 1236 if (list_empty(&ioc->free_chain_list)) { 1237 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1238 dfailprintk(ioc, pr_warn(MPT3SAS_FMT 1239 "chain buffers not available\n", ioc->name)); 1240 return NULL; 1241 } 1242 chain_req = list_entry(ioc->free_chain_list.next, 1243 struct chain_tracker, tracker_list); 1244 list_del_init(&chain_req->tracker_list); 1245 list_add_tail(&chain_req->tracker_list, 1246 &ioc->scsi_lookup[smid - 1].chain_list); 1247 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1248 return chain_req; 1249 } 1250 1251 1252 /** 1253 * _base_build_sg - build generic sg 1254 * @ioc: per adapter object 1255 * @psge: virtual address for SGE 1256 * @data_out_dma: physical address for WRITES 1257 * @data_out_sz: data xfer size for WRITES 1258 * @data_in_dma: physical address for READS 1259 * @data_in_sz: data xfer size for READS 1260 * 1261 * Return nothing. 1262 */ 1263 static void 1264 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 1265 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1266 size_t data_in_sz) 1267 { 1268 u32 sgl_flags; 1269 1270 if (!data_out_sz && !data_in_sz) { 1271 _base_build_zero_len_sge(ioc, psge); 1272 return; 1273 } 1274 1275 if (data_out_sz && data_in_sz) { 1276 /* WRITE sgel first */ 1277 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1278 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 1279 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1280 ioc->base_add_sg_single(psge, sgl_flags | 1281 data_out_sz, data_out_dma); 1282 1283 /* incr sgel */ 1284 psge += ioc->sge_size; 1285 1286 /* READ sgel last */ 1287 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1288 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1289 MPI2_SGE_FLAGS_END_OF_LIST); 1290 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1291 ioc->base_add_sg_single(psge, sgl_flags | 1292 data_in_sz, data_in_dma); 1293 } else if (data_out_sz) /* WRITE */ { 1294 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1295 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1296 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 1297 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1298 ioc->base_add_sg_single(psge, sgl_flags | 1299 data_out_sz, data_out_dma); 1300 } else if (data_in_sz) /* READ */ { 1301 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1302 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1303 MPI2_SGE_FLAGS_END_OF_LIST); 1304 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1305 ioc->base_add_sg_single(psge, sgl_flags | 1306 data_in_sz, data_in_dma); 1307 } 1308 } 1309 1310 /* IEEE format sgls */ 1311 1312 /** 1313 * _base_add_sg_single_ieee - add sg element for IEEE format 1314 * @paddr: virtual address for SGE 1315 * @flags: SGE flags 1316 * @chain_offset: number of 128 byte elements from start of segment 1317 * @length: data transfer length 1318 * @dma_addr: Physical address 1319 * 1320 * Return nothing. 1321 */ 1322 static void 1323 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 1324 dma_addr_t dma_addr) 1325 { 1326 Mpi25IeeeSgeChain64_t *sgel = paddr; 1327 1328 sgel->Flags = flags; 1329 sgel->NextChainOffset = chain_offset; 1330 sgel->Length = cpu_to_le32(length); 1331 sgel->Address = cpu_to_le64(dma_addr); 1332 } 1333 1334 /** 1335 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 1336 * @ioc: per adapter object 1337 * @paddr: virtual address for SGE 1338 * 1339 * Create a zero length scatter gather entry to insure the IOCs hardware has 1340 * something to use if the target device goes brain dead and tries 1341 * to send data even when none is asked for. 1342 * 1343 * Return nothing. 1344 */ 1345 static void 1346 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1347 { 1348 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1349 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 1350 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 1351 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 1352 } 1353 1354 /** 1355 * _base_build_sg_scmd - main sg creation routine 1356 * @ioc: per adapter object 1357 * @scmd: scsi command 1358 * @smid: system request message index 1359 * Context: none. 1360 * 1361 * The main routine that builds scatter gather table from a given 1362 * scsi request sent via the .queuecommand main handler. 1363 * 1364 * Returns 0 success, anything else error 1365 */ 1366 static int 1367 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 1368 struct scsi_cmnd *scmd, u16 smid) 1369 { 1370 Mpi2SCSIIORequest_t *mpi_request; 1371 dma_addr_t chain_dma; 1372 struct scatterlist *sg_scmd; 1373 void *sg_local, *chain; 1374 u32 chain_offset; 1375 u32 chain_length; 1376 u32 chain_flags; 1377 int sges_left; 1378 u32 sges_in_segment; 1379 u32 sgl_flags; 1380 u32 sgl_flags_last_element; 1381 u32 sgl_flags_end_buffer; 1382 struct chain_tracker *chain_req; 1383 1384 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1385 1386 /* init scatter gather flags */ 1387 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 1388 if (scmd->sc_data_direction == DMA_TO_DEVICE) 1389 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 1390 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 1391 << MPI2_SGE_FLAGS_SHIFT; 1392 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 1393 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 1394 << MPI2_SGE_FLAGS_SHIFT; 1395 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1396 1397 sg_scmd = scsi_sglist(scmd); 1398 sges_left = scsi_dma_map(scmd); 1399 if (sges_left < 0) { 1400 sdev_printk(KERN_ERR, scmd->device, 1401 "pci_map_sg failed: request for %d bytes!\n", 1402 scsi_bufflen(scmd)); 1403 return -ENOMEM; 1404 } 1405 1406 sg_local = &mpi_request->SGL; 1407 sges_in_segment = ioc->max_sges_in_main_message; 1408 if (sges_left <= sges_in_segment) 1409 goto fill_in_last_segment; 1410 1411 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 1412 (sges_in_segment * ioc->sge_size))/4; 1413 1414 /* fill in main message segment when there is a chain following */ 1415 while (sges_in_segment) { 1416 if (sges_in_segment == 1) 1417 ioc->base_add_sg_single(sg_local, 1418 sgl_flags_last_element | sg_dma_len(sg_scmd), 1419 sg_dma_address(sg_scmd)); 1420 else 1421 ioc->base_add_sg_single(sg_local, sgl_flags | 1422 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1423 sg_scmd = sg_next(sg_scmd); 1424 sg_local += ioc->sge_size; 1425 sges_left--; 1426 sges_in_segment--; 1427 } 1428 1429 /* initializing the chain flags and pointers */ 1430 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 1431 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1432 if (!chain_req) 1433 return -1; 1434 chain = chain_req->chain_buffer; 1435 chain_dma = chain_req->chain_buffer_dma; 1436 do { 1437 sges_in_segment = (sges_left <= 1438 ioc->max_sges_in_chain_message) ? sges_left : 1439 ioc->max_sges_in_chain_message; 1440 chain_offset = (sges_left == sges_in_segment) ? 1441 0 : (sges_in_segment * ioc->sge_size)/4; 1442 chain_length = sges_in_segment * ioc->sge_size; 1443 if (chain_offset) { 1444 chain_offset = chain_offset << 1445 MPI2_SGE_CHAIN_OFFSET_SHIFT; 1446 chain_length += ioc->sge_size; 1447 } 1448 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 1449 chain_length, chain_dma); 1450 sg_local = chain; 1451 if (!chain_offset) 1452 goto fill_in_last_segment; 1453 1454 /* fill in chain segments */ 1455 while (sges_in_segment) { 1456 if (sges_in_segment == 1) 1457 ioc->base_add_sg_single(sg_local, 1458 sgl_flags_last_element | 1459 sg_dma_len(sg_scmd), 1460 sg_dma_address(sg_scmd)); 1461 else 1462 ioc->base_add_sg_single(sg_local, sgl_flags | 1463 sg_dma_len(sg_scmd), 1464 sg_dma_address(sg_scmd)); 1465 sg_scmd = sg_next(sg_scmd); 1466 sg_local += ioc->sge_size; 1467 sges_left--; 1468 sges_in_segment--; 1469 } 1470 1471 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1472 if (!chain_req) 1473 return -1; 1474 chain = chain_req->chain_buffer; 1475 chain_dma = chain_req->chain_buffer_dma; 1476 } while (1); 1477 1478 1479 fill_in_last_segment: 1480 1481 /* fill the last segment */ 1482 while (sges_left) { 1483 if (sges_left == 1) 1484 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 1485 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1486 else 1487 ioc->base_add_sg_single(sg_local, sgl_flags | 1488 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1489 sg_scmd = sg_next(sg_scmd); 1490 sg_local += ioc->sge_size; 1491 sges_left--; 1492 } 1493 1494 return 0; 1495 } 1496 1497 /** 1498 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 1499 * @ioc: per adapter object 1500 * @scmd: scsi command 1501 * @smid: system request message index 1502 * Context: none. 1503 * 1504 * The main routine that builds scatter gather table from a given 1505 * scsi request sent via the .queuecommand main handler. 1506 * 1507 * Returns 0 success, anything else error 1508 */ 1509 static int 1510 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 1511 struct scsi_cmnd *scmd, u16 smid) 1512 { 1513 Mpi2SCSIIORequest_t *mpi_request; 1514 dma_addr_t chain_dma; 1515 struct scatterlist *sg_scmd; 1516 void *sg_local, *chain; 1517 u32 chain_offset; 1518 u32 chain_length; 1519 int sges_left; 1520 u32 sges_in_segment; 1521 u8 simple_sgl_flags; 1522 u8 simple_sgl_flags_last; 1523 u8 chain_sgl_flags; 1524 struct chain_tracker *chain_req; 1525 1526 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1527 1528 /* init scatter gather flags */ 1529 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1530 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1531 simple_sgl_flags_last = simple_sgl_flags | 1532 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1533 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 1534 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1535 1536 sg_scmd = scsi_sglist(scmd); 1537 sges_left = scsi_dma_map(scmd); 1538 if (sges_left < 0) { 1539 sdev_printk(KERN_ERR, scmd->device, 1540 "pci_map_sg failed: request for %d bytes!\n", 1541 scsi_bufflen(scmd)); 1542 return -ENOMEM; 1543 } 1544 1545 sg_local = &mpi_request->SGL; 1546 sges_in_segment = (ioc->request_sz - 1547 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 1548 if (sges_left <= sges_in_segment) 1549 goto fill_in_last_segment; 1550 1551 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 1552 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 1553 1554 /* fill in main message segment when there is a chain following */ 1555 while (sges_in_segment > 1) { 1556 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1557 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1558 sg_scmd = sg_next(sg_scmd); 1559 sg_local += ioc->sge_size_ieee; 1560 sges_left--; 1561 sges_in_segment--; 1562 } 1563 1564 /* initializing the pointers */ 1565 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1566 if (!chain_req) 1567 return -1; 1568 chain = chain_req->chain_buffer; 1569 chain_dma = chain_req->chain_buffer_dma; 1570 do { 1571 sges_in_segment = (sges_left <= 1572 ioc->max_sges_in_chain_message) ? sges_left : 1573 ioc->max_sges_in_chain_message; 1574 chain_offset = (sges_left == sges_in_segment) ? 1575 0 : sges_in_segment; 1576 chain_length = sges_in_segment * ioc->sge_size_ieee; 1577 if (chain_offset) 1578 chain_length += ioc->sge_size_ieee; 1579 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 1580 chain_offset, chain_length, chain_dma); 1581 1582 sg_local = chain; 1583 if (!chain_offset) 1584 goto fill_in_last_segment; 1585 1586 /* fill in chain segments */ 1587 while (sges_in_segment) { 1588 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1589 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1590 sg_scmd = sg_next(sg_scmd); 1591 sg_local += ioc->sge_size_ieee; 1592 sges_left--; 1593 sges_in_segment--; 1594 } 1595 1596 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1597 if (!chain_req) 1598 return -1; 1599 chain = chain_req->chain_buffer; 1600 chain_dma = chain_req->chain_buffer_dma; 1601 } while (1); 1602 1603 1604 fill_in_last_segment: 1605 1606 /* fill the last segment */ 1607 while (sges_left > 0) { 1608 if (sges_left == 1) 1609 _base_add_sg_single_ieee(sg_local, 1610 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 1611 sg_dma_address(sg_scmd)); 1612 else 1613 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1614 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1615 sg_scmd = sg_next(sg_scmd); 1616 sg_local += ioc->sge_size_ieee; 1617 sges_left--; 1618 } 1619 1620 return 0; 1621 } 1622 1623 /** 1624 * _base_build_sg_ieee - build generic sg for IEEE format 1625 * @ioc: per adapter object 1626 * @psge: virtual address for SGE 1627 * @data_out_dma: physical address for WRITES 1628 * @data_out_sz: data xfer size for WRITES 1629 * @data_in_dma: physical address for READS 1630 * @data_in_sz: data xfer size for READS 1631 * 1632 * Return nothing. 1633 */ 1634 static void 1635 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 1636 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1637 size_t data_in_sz) 1638 { 1639 u8 sgl_flags; 1640 1641 if (!data_out_sz && !data_in_sz) { 1642 _base_build_zero_len_sge_ieee(ioc, psge); 1643 return; 1644 } 1645 1646 if (data_out_sz && data_in_sz) { 1647 /* WRITE sgel first */ 1648 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1649 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1650 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1651 data_out_dma); 1652 1653 /* incr sgel */ 1654 psge += ioc->sge_size_ieee; 1655 1656 /* READ sgel last */ 1657 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1658 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1659 data_in_dma); 1660 } else if (data_out_sz) /* WRITE */ { 1661 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1662 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1663 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1664 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1665 data_out_dma); 1666 } else if (data_in_sz) /* READ */ { 1667 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1668 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1669 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1670 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1671 data_in_dma); 1672 } 1673 } 1674 1675 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 1676 1677 /** 1678 * _base_config_dma_addressing - set dma addressing 1679 * @ioc: per adapter object 1680 * @pdev: PCI device struct 1681 * 1682 * Returns 0 for success, non-zero for failure. 1683 */ 1684 static int 1685 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 1686 { 1687 struct sysinfo s; 1688 u64 consistent_dma_mask; 1689 1690 if (ioc->dma_mask) 1691 consistent_dma_mask = DMA_BIT_MASK(64); 1692 else 1693 consistent_dma_mask = DMA_BIT_MASK(32); 1694 1695 if (sizeof(dma_addr_t) > 4) { 1696 const uint64_t required_mask = 1697 dma_get_required_mask(&pdev->dev); 1698 if ((required_mask > DMA_BIT_MASK(32)) && 1699 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && 1700 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { 1701 ioc->base_add_sg_single = &_base_add_sg_single_64; 1702 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 1703 ioc->dma_mask = 64; 1704 goto out; 1705 } 1706 } 1707 1708 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1709 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1710 ioc->base_add_sg_single = &_base_add_sg_single_32; 1711 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 1712 ioc->dma_mask = 32; 1713 } else 1714 return -ENODEV; 1715 1716 out: 1717 si_meminfo(&s); 1718 pr_info(MPT3SAS_FMT 1719 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 1720 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); 1721 1722 return 0; 1723 } 1724 1725 static int 1726 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, 1727 struct pci_dev *pdev) 1728 { 1729 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 1730 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 1731 return -ENODEV; 1732 } 1733 return 0; 1734 } 1735 1736 /** 1737 * _base_check_enable_msix - checks MSIX capabable. 1738 * @ioc: per adapter object 1739 * 1740 * Check to see if card is capable of MSIX, and set number 1741 * of available msix vectors 1742 */ 1743 static int 1744 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1745 { 1746 int base; 1747 u16 message_control; 1748 1749 /* Check whether controller SAS2008 B0 controller, 1750 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 1751 */ 1752 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 1753 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 1754 return -EINVAL; 1755 } 1756 1757 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 1758 if (!base) { 1759 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", 1760 ioc->name)); 1761 return -EINVAL; 1762 } 1763 1764 /* get msix vector count */ 1765 /* NUMA_IO not supported for older controllers */ 1766 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 1767 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 1768 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 1769 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 1770 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 1771 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 1772 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 1773 ioc->msix_vector_count = 1; 1774 else { 1775 pci_read_config_word(ioc->pdev, base + 2, &message_control); 1776 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 1777 } 1778 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1779 "msix is supported, vector_count(%d)\n", 1780 ioc->name, ioc->msix_vector_count)); 1781 return 0; 1782 } 1783 1784 /** 1785 * _base_free_irq - free irq 1786 * @ioc: per adapter object 1787 * 1788 * Freeing respective reply_queue from the list. 1789 */ 1790 static void 1791 _base_free_irq(struct MPT3SAS_ADAPTER *ioc) 1792 { 1793 struct adapter_reply_queue *reply_q, *next; 1794 1795 if (list_empty(&ioc->reply_queue_list)) 1796 return; 1797 1798 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1799 list_del(&reply_q->list); 1800 irq_set_affinity_hint(reply_q->vector, NULL); 1801 free_cpumask_var(reply_q->affinity_hint); 1802 synchronize_irq(reply_q->vector); 1803 free_irq(reply_q->vector, reply_q); 1804 kfree(reply_q); 1805 } 1806 } 1807 1808 /** 1809 * _base_request_irq - request irq 1810 * @ioc: per adapter object 1811 * @index: msix index into vector table 1812 * @vector: irq vector 1813 * 1814 * Inserting respective reply_queue into the list. 1815 */ 1816 static int 1817 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector) 1818 { 1819 struct adapter_reply_queue *reply_q; 1820 int r; 1821 1822 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 1823 if (!reply_q) { 1824 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", 1825 ioc->name, (int)sizeof(struct adapter_reply_queue)); 1826 return -ENOMEM; 1827 } 1828 reply_q->ioc = ioc; 1829 reply_q->msix_index = index; 1830 reply_q->vector = vector; 1831 1832 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) 1833 return -ENOMEM; 1834 cpumask_clear(reply_q->affinity_hint); 1835 1836 atomic_set(&reply_q->busy, 0); 1837 if (ioc->msix_enable) 1838 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 1839 ioc->driver_name, ioc->id, index); 1840 else 1841 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 1842 ioc->driver_name, ioc->id); 1843 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name, 1844 reply_q); 1845 if (r) { 1846 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", 1847 reply_q->name, vector); 1848 kfree(reply_q); 1849 return -EBUSY; 1850 } 1851 1852 INIT_LIST_HEAD(&reply_q->list); 1853 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 1854 return 0; 1855 } 1856 1857 /** 1858 * _base_assign_reply_queues - assigning msix index for each cpu 1859 * @ioc: per adapter object 1860 * 1861 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 1862 * 1863 * It would nice if we could call irq_set_affinity, however it is not 1864 * an exported symbol 1865 */ 1866 static void 1867 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1868 { 1869 unsigned int cpu, nr_cpus, nr_msix, index = 0; 1870 struct adapter_reply_queue *reply_q; 1871 1872 if (!_base_is_controller_msix_enabled(ioc)) 1873 return; 1874 1875 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 1876 1877 nr_cpus = num_online_cpus(); 1878 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 1879 ioc->facts.MaxMSIxVectors); 1880 if (!nr_msix) 1881 return; 1882 1883 cpu = cpumask_first(cpu_online_mask); 1884 1885 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1886 1887 unsigned int i, group = nr_cpus / nr_msix; 1888 1889 if (cpu >= nr_cpus) 1890 break; 1891 1892 if (index < nr_cpus % nr_msix) 1893 group++; 1894 1895 for (i = 0 ; i < group ; i++) { 1896 ioc->cpu_msix_table[cpu] = index; 1897 cpumask_or(reply_q->affinity_hint, 1898 reply_q->affinity_hint, get_cpu_mask(cpu)); 1899 cpu = cpumask_next(cpu, cpu_online_mask); 1900 } 1901 1902 if (irq_set_affinity_hint(reply_q->vector, 1903 reply_q->affinity_hint)) 1904 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1905 "error setting affinity hint for irq vector %d\n", 1906 ioc->name, reply_q->vector)); 1907 index++; 1908 } 1909 } 1910 1911 /** 1912 * _base_disable_msix - disables msix 1913 * @ioc: per adapter object 1914 * 1915 */ 1916 static void 1917 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 1918 { 1919 if (!ioc->msix_enable) 1920 return; 1921 pci_disable_msix(ioc->pdev); 1922 ioc->msix_enable = 0; 1923 } 1924 1925 /** 1926 * _base_enable_msix - enables msix, failback to io_apic 1927 * @ioc: per adapter object 1928 * 1929 */ 1930 static int 1931 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1932 { 1933 struct msix_entry *entries, *a; 1934 int r; 1935 int i; 1936 u8 try_msix = 0; 1937 1938 if (msix_disable == -1 || msix_disable == 0) 1939 try_msix = 1; 1940 1941 if (!try_msix) 1942 goto try_ioapic; 1943 1944 if (_base_check_enable_msix(ioc) != 0) 1945 goto try_ioapic; 1946 1947 ioc->reply_queue_count = min_t(int, ioc->cpu_count, 1948 ioc->msix_vector_count); 1949 1950 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" 1951 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, 1952 ioc->cpu_count, max_msix_vectors); 1953 1954 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 1955 max_msix_vectors = 8; 1956 1957 if (max_msix_vectors > 0) { 1958 ioc->reply_queue_count = min_t(int, max_msix_vectors, 1959 ioc->reply_queue_count); 1960 ioc->msix_vector_count = ioc->reply_queue_count; 1961 } else if (max_msix_vectors == 0) 1962 goto try_ioapic; 1963 1964 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry), 1965 GFP_KERNEL); 1966 if (!entries) { 1967 dfailprintk(ioc, pr_info(MPT3SAS_FMT 1968 "kcalloc failed @ at %s:%d/%s() !!!\n", 1969 ioc->name, __FILE__, __LINE__, __func__)); 1970 goto try_ioapic; 1971 } 1972 1973 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) 1974 a->entry = i; 1975 1976 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count); 1977 if (r) { 1978 dfailprintk(ioc, pr_info(MPT3SAS_FMT 1979 "pci_enable_msix_exact failed (r=%d) !!!\n", 1980 ioc->name, r)); 1981 kfree(entries); 1982 goto try_ioapic; 1983 } 1984 1985 ioc->msix_enable = 1; 1986 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) { 1987 r = _base_request_irq(ioc, i, a->vector); 1988 if (r) { 1989 _base_free_irq(ioc); 1990 _base_disable_msix(ioc); 1991 kfree(entries); 1992 goto try_ioapic; 1993 } 1994 } 1995 1996 kfree(entries); 1997 return 0; 1998 1999 /* failback to io_apic interrupt routing */ 2000 try_ioapic: 2001 2002 ioc->reply_queue_count = 1; 2003 r = _base_request_irq(ioc, 0, ioc->pdev->irq); 2004 2005 return r; 2006 } 2007 2008 /** 2009 * mpt3sas_base_unmap_resources - free controller resources 2010 * @ioc: per adapter object 2011 */ 2012 void 2013 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 2014 { 2015 struct pci_dev *pdev = ioc->pdev; 2016 2017 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", 2018 ioc->name, __func__)); 2019 2020 _base_free_irq(ioc); 2021 _base_disable_msix(ioc); 2022 2023 if (ioc->msix96_vector) { 2024 kfree(ioc->replyPostRegisterIndex); 2025 ioc->replyPostRegisterIndex = NULL; 2026 } 2027 2028 if (ioc->chip_phys) { 2029 iounmap(ioc->chip); 2030 ioc->chip_phys = 0; 2031 } 2032 2033 if (pci_is_enabled(pdev)) { 2034 pci_release_selected_regions(ioc->pdev, ioc->bars); 2035 pci_disable_pcie_error_reporting(pdev); 2036 pci_disable_device(pdev); 2037 } 2038 } 2039 2040 /** 2041 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 2042 * @ioc: per adapter object 2043 * 2044 * Returns 0 for success, non-zero for failure. 2045 */ 2046 int 2047 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 2048 { 2049 struct pci_dev *pdev = ioc->pdev; 2050 u32 memap_sz; 2051 u32 pio_sz; 2052 int i, r = 0; 2053 u64 pio_chip = 0; 2054 u64 chip_phys = 0; 2055 struct adapter_reply_queue *reply_q; 2056 2057 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", 2058 ioc->name, __func__)); 2059 2060 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 2061 if (pci_enable_device_mem(pdev)) { 2062 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", 2063 ioc->name); 2064 ioc->bars = 0; 2065 return -ENODEV; 2066 } 2067 2068 2069 if (pci_request_selected_regions(pdev, ioc->bars, 2070 ioc->driver_name)) { 2071 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", 2072 ioc->name); 2073 ioc->bars = 0; 2074 r = -ENODEV; 2075 goto out_fail; 2076 } 2077 2078 /* AER (Advanced Error Reporting) hooks */ 2079 pci_enable_pcie_error_reporting(pdev); 2080 2081 pci_set_master(pdev); 2082 2083 2084 if (_base_config_dma_addressing(ioc, pdev) != 0) { 2085 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", 2086 ioc->name, pci_name(pdev)); 2087 r = -ENODEV; 2088 goto out_fail; 2089 } 2090 2091 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 2092 (!memap_sz || !pio_sz); i++) { 2093 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 2094 if (pio_sz) 2095 continue; 2096 pio_chip = (u64)pci_resource_start(pdev, i); 2097 pio_sz = pci_resource_len(pdev, i); 2098 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 2099 if (memap_sz) 2100 continue; 2101 ioc->chip_phys = pci_resource_start(pdev, i); 2102 chip_phys = (u64)ioc->chip_phys; 2103 memap_sz = pci_resource_len(pdev, i); 2104 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 2105 } 2106 } 2107 2108 if (ioc->chip == NULL) { 2109 pr_err(MPT3SAS_FMT "unable to map adapter memory! " 2110 " or resource not found\n", ioc->name); 2111 r = -EINVAL; 2112 goto out_fail; 2113 } 2114 2115 _base_mask_interrupts(ioc); 2116 2117 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 2118 if (r) 2119 goto out_fail; 2120 2121 if (!ioc->rdpq_array_enable_assigned) { 2122 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 2123 ioc->rdpq_array_enable_assigned = 1; 2124 } 2125 2126 r = _base_enable_msix(ioc); 2127 if (r) 2128 goto out_fail; 2129 2130 /* Use the Combined reply queue feature only for SAS3 C0 & higher 2131 * revision HBAs and also only when reply queue count is greater than 8 2132 */ 2133 if (ioc->msix96_vector && ioc->reply_queue_count > 8) { 2134 /* Determine the Supplemental Reply Post Host Index Registers 2135 * Addresse. Supplemental Reply Post Host Index Registers 2136 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 2137 * each register is at offset bytes of 2138 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 2139 */ 2140 ioc->replyPostRegisterIndex = kcalloc( 2141 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT, 2142 sizeof(resource_size_t *), GFP_KERNEL); 2143 if (!ioc->replyPostRegisterIndex) { 2144 dfailprintk(ioc, printk(MPT3SAS_FMT 2145 "allocation for reply Post Register Index failed!!!\n", 2146 ioc->name)); 2147 r = -ENOMEM; 2148 goto out_fail; 2149 } 2150 2151 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) { 2152 ioc->replyPostRegisterIndex[i] = (resource_size_t *) 2153 ((u8 *)&ioc->chip->Doorbell + 2154 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 2155 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 2156 } 2157 } else 2158 ioc->msix96_vector = 0; 2159 2160 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) 2161 pr_info(MPT3SAS_FMT "%s: IRQ %d\n", 2162 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : 2163 "IO-APIC enabled"), reply_q->vector); 2164 2165 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 2166 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz); 2167 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", 2168 ioc->name, (unsigned long long)pio_chip, pio_sz); 2169 2170 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 2171 pci_save_state(pdev); 2172 return 0; 2173 2174 out_fail: 2175 mpt3sas_base_unmap_resources(ioc); 2176 return r; 2177 } 2178 2179 /** 2180 * mpt3sas_base_get_msg_frame - obtain request mf pointer 2181 * @ioc: per adapter object 2182 * @smid: system request message index(smid zero is invalid) 2183 * 2184 * Returns virt pointer to message frame. 2185 */ 2186 void * 2187 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2188 { 2189 return (void *)(ioc->request + (smid * ioc->request_sz)); 2190 } 2191 2192 /** 2193 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 2194 * @ioc: per adapter object 2195 * @smid: system request message index 2196 * 2197 * Returns virt pointer to sense buffer. 2198 */ 2199 void * 2200 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2201 { 2202 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 2203 } 2204 2205 /** 2206 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 2207 * @ioc: per adapter object 2208 * @smid: system request message index 2209 * 2210 * Returns phys pointer to the low 32bit address of the sense buffer. 2211 */ 2212 __le32 2213 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2214 { 2215 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 2216 SCSI_SENSE_BUFFERSIZE)); 2217 } 2218 2219 /** 2220 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 2221 * @ioc: per adapter object 2222 * @phys_addr: lower 32 physical addr of the reply 2223 * 2224 * Converts 32bit lower physical addr into a virt address. 2225 */ 2226 void * 2227 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 2228 { 2229 if (!phys_addr) 2230 return NULL; 2231 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 2232 } 2233 2234 /** 2235 * mpt3sas_base_get_smid - obtain a free smid from internal queue 2236 * @ioc: per adapter object 2237 * @cb_idx: callback index 2238 * 2239 * Returns smid (zero is invalid) 2240 */ 2241 u16 2242 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2243 { 2244 unsigned long flags; 2245 struct request_tracker *request; 2246 u16 smid; 2247 2248 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2249 if (list_empty(&ioc->internal_free_list)) { 2250 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2251 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2252 ioc->name, __func__); 2253 return 0; 2254 } 2255 2256 request = list_entry(ioc->internal_free_list.next, 2257 struct request_tracker, tracker_list); 2258 request->cb_idx = cb_idx; 2259 smid = request->smid; 2260 list_del(&request->tracker_list); 2261 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2262 return smid; 2263 } 2264 2265 /** 2266 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 2267 * @ioc: per adapter object 2268 * @cb_idx: callback index 2269 * @scmd: pointer to scsi command object 2270 * 2271 * Returns smid (zero is invalid) 2272 */ 2273 u16 2274 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 2275 struct scsi_cmnd *scmd) 2276 { 2277 unsigned long flags; 2278 struct scsiio_tracker *request; 2279 u16 smid; 2280 2281 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2282 if (list_empty(&ioc->free_list)) { 2283 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2284 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2285 ioc->name, __func__); 2286 return 0; 2287 } 2288 2289 request = list_entry(ioc->free_list.next, 2290 struct scsiio_tracker, tracker_list); 2291 request->scmd = scmd; 2292 request->cb_idx = cb_idx; 2293 smid = request->smid; 2294 list_del(&request->tracker_list); 2295 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2296 return smid; 2297 } 2298 2299 /** 2300 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 2301 * @ioc: per adapter object 2302 * @cb_idx: callback index 2303 * 2304 * Returns smid (zero is invalid) 2305 */ 2306 u16 2307 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2308 { 2309 unsigned long flags; 2310 struct request_tracker *request; 2311 u16 smid; 2312 2313 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2314 if (list_empty(&ioc->hpr_free_list)) { 2315 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2316 return 0; 2317 } 2318 2319 request = list_entry(ioc->hpr_free_list.next, 2320 struct request_tracker, tracker_list); 2321 request->cb_idx = cb_idx; 2322 smid = request->smid; 2323 list_del(&request->tracker_list); 2324 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2325 return smid; 2326 } 2327 2328 /** 2329 * mpt3sas_base_free_smid - put smid back on free_list 2330 * @ioc: per adapter object 2331 * @smid: system request message index 2332 * 2333 * Return nothing. 2334 */ 2335 void 2336 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2337 { 2338 unsigned long flags; 2339 int i; 2340 struct chain_tracker *chain_req, *next; 2341 2342 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2343 if (smid < ioc->hi_priority_smid) { 2344 /* scsiio queue */ 2345 i = smid - 1; 2346 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) { 2347 list_for_each_entry_safe(chain_req, next, 2348 &ioc->scsi_lookup[i].chain_list, tracker_list) { 2349 list_del_init(&chain_req->tracker_list); 2350 list_add(&chain_req->tracker_list, 2351 &ioc->free_chain_list); 2352 } 2353 } 2354 ioc->scsi_lookup[i].cb_idx = 0xFF; 2355 ioc->scsi_lookup[i].scmd = NULL; 2356 ioc->scsi_lookup[i].direct_io = 0; 2357 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list); 2358 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2359 2360 /* 2361 * See _wait_for_commands_to_complete() call with regards 2362 * to this code. 2363 */ 2364 if (ioc->shost_recovery && ioc->pending_io_count) { 2365 if (ioc->pending_io_count == 1) 2366 wake_up(&ioc->reset_wq); 2367 ioc->pending_io_count--; 2368 } 2369 return; 2370 } else if (smid < ioc->internal_smid) { 2371 /* hi-priority */ 2372 i = smid - ioc->hi_priority_smid; 2373 ioc->hpr_lookup[i].cb_idx = 0xFF; 2374 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 2375 } else if (smid <= ioc->hba_queue_depth) { 2376 /* internal queue */ 2377 i = smid - ioc->internal_smid; 2378 ioc->internal_lookup[i].cb_idx = 0xFF; 2379 list_add(&ioc->internal_lookup[i].tracker_list, 2380 &ioc->internal_free_list); 2381 } 2382 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2383 } 2384 2385 /** 2386 * _base_writeq - 64 bit write to MMIO 2387 * @ioc: per adapter object 2388 * @b: data payload 2389 * @addr: address in MMIO space 2390 * @writeq_lock: spin lock 2391 * 2392 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 2393 * care of 32 bit environment where its not quarenteed to send the entire word 2394 * in one transfer. 2395 */ 2396 #if defined(writeq) && defined(CONFIG_64BIT) 2397 static inline void 2398 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2399 { 2400 writeq(cpu_to_le64(b), addr); 2401 } 2402 #else 2403 static inline void 2404 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2405 { 2406 unsigned long flags; 2407 __u64 data_out = cpu_to_le64(b); 2408 2409 spin_lock_irqsave(writeq_lock, flags); 2410 writel((u32)(data_out), addr); 2411 writel((u32)(data_out >> 32), (addr + 4)); 2412 spin_unlock_irqrestore(writeq_lock, flags); 2413 } 2414 #endif 2415 2416 static inline u8 2417 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) 2418 { 2419 return ioc->cpu_msix_table[raw_smp_processor_id()]; 2420 } 2421 2422 /** 2423 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware 2424 * @ioc: per adapter object 2425 * @smid: system request message index 2426 * @handle: device handle 2427 * 2428 * Return nothing. 2429 */ 2430 void 2431 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 2432 { 2433 Mpi2RequestDescriptorUnion_t descriptor; 2434 u64 *request = (u64 *)&descriptor; 2435 2436 2437 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2438 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2439 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2440 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2441 descriptor.SCSIIO.LMID = 0; 2442 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2443 &ioc->scsi_lookup_lock); 2444 } 2445 2446 /** 2447 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware 2448 * @ioc: per adapter object 2449 * @smid: system request message index 2450 * @handle: device handle 2451 * 2452 * Return nothing. 2453 */ 2454 void 2455 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2456 u16 handle) 2457 { 2458 Mpi2RequestDescriptorUnion_t descriptor; 2459 u64 *request = (u64 *)&descriptor; 2460 2461 descriptor.SCSIIO.RequestFlags = 2462 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2463 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2464 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2465 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2466 descriptor.SCSIIO.LMID = 0; 2467 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2468 &ioc->scsi_lookup_lock); 2469 } 2470 2471 /** 2472 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware 2473 * @ioc: per adapter object 2474 * @smid: system request message index 2475 * 2476 * Return nothing. 2477 */ 2478 void 2479 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2480 { 2481 Mpi2RequestDescriptorUnion_t descriptor; 2482 u64 *request = (u64 *)&descriptor; 2483 2484 descriptor.HighPriority.RequestFlags = 2485 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2486 descriptor.HighPriority.MSIxIndex = 0; 2487 descriptor.HighPriority.SMID = cpu_to_le16(smid); 2488 descriptor.HighPriority.LMID = 0; 2489 descriptor.HighPriority.Reserved1 = 0; 2490 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2491 &ioc->scsi_lookup_lock); 2492 } 2493 2494 /** 2495 * mpt3sas_base_put_smid_default - Default, primarily used for config pages 2496 * @ioc: per adapter object 2497 * @smid: system request message index 2498 * 2499 * Return nothing. 2500 */ 2501 void 2502 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2503 { 2504 Mpi2RequestDescriptorUnion_t descriptor; 2505 u64 *request = (u64 *)&descriptor; 2506 2507 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2508 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 2509 descriptor.Default.SMID = cpu_to_le16(smid); 2510 descriptor.Default.LMID = 0; 2511 descriptor.Default.DescriptorTypeDependent = 0; 2512 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2513 &ioc->scsi_lookup_lock); 2514 } 2515 2516 /** 2517 * _base_display_OEMs_branding - Display branding string 2518 * @ioc: per adapter object 2519 * 2520 * Return nothing. 2521 */ 2522 static void 2523 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 2524 { 2525 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 2526 return; 2527 2528 switch (ioc->pdev->subsystem_vendor) { 2529 case PCI_VENDOR_ID_INTEL: 2530 switch (ioc->pdev->device) { 2531 case MPI2_MFGPAGE_DEVID_SAS2008: 2532 switch (ioc->pdev->subsystem_device) { 2533 case MPT2SAS_INTEL_RMS2LL080_SSDID: 2534 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2535 MPT2SAS_INTEL_RMS2LL080_BRANDING); 2536 break; 2537 case MPT2SAS_INTEL_RMS2LL040_SSDID: 2538 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2539 MPT2SAS_INTEL_RMS2LL040_BRANDING); 2540 break; 2541 case MPT2SAS_INTEL_SSD910_SSDID: 2542 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2543 MPT2SAS_INTEL_SSD910_BRANDING); 2544 break; 2545 default: 2546 pr_info(MPT3SAS_FMT 2547 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2548 ioc->name, ioc->pdev->subsystem_device); 2549 break; 2550 } 2551 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2552 switch (ioc->pdev->subsystem_device) { 2553 case MPT2SAS_INTEL_RS25GB008_SSDID: 2554 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2555 MPT2SAS_INTEL_RS25GB008_BRANDING); 2556 break; 2557 case MPT2SAS_INTEL_RMS25JB080_SSDID: 2558 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2559 MPT2SAS_INTEL_RMS25JB080_BRANDING); 2560 break; 2561 case MPT2SAS_INTEL_RMS25JB040_SSDID: 2562 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2563 MPT2SAS_INTEL_RMS25JB040_BRANDING); 2564 break; 2565 case MPT2SAS_INTEL_RMS25KB080_SSDID: 2566 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2567 MPT2SAS_INTEL_RMS25KB080_BRANDING); 2568 break; 2569 case MPT2SAS_INTEL_RMS25KB040_SSDID: 2570 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2571 MPT2SAS_INTEL_RMS25KB040_BRANDING); 2572 break; 2573 case MPT2SAS_INTEL_RMS25LB040_SSDID: 2574 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2575 MPT2SAS_INTEL_RMS25LB040_BRANDING); 2576 break; 2577 case MPT2SAS_INTEL_RMS25LB080_SSDID: 2578 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2579 MPT2SAS_INTEL_RMS25LB080_BRANDING); 2580 break; 2581 default: 2582 pr_info(MPT3SAS_FMT 2583 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2584 ioc->name, ioc->pdev->subsystem_device); 2585 break; 2586 } 2587 case MPI25_MFGPAGE_DEVID_SAS3008: 2588 switch (ioc->pdev->subsystem_device) { 2589 case MPT3SAS_INTEL_RMS3JC080_SSDID: 2590 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2591 MPT3SAS_INTEL_RMS3JC080_BRANDING); 2592 break; 2593 2594 case MPT3SAS_INTEL_RS3GC008_SSDID: 2595 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2596 MPT3SAS_INTEL_RS3GC008_BRANDING); 2597 break; 2598 case MPT3SAS_INTEL_RS3FC044_SSDID: 2599 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2600 MPT3SAS_INTEL_RS3FC044_BRANDING); 2601 break; 2602 case MPT3SAS_INTEL_RS3UC080_SSDID: 2603 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2604 MPT3SAS_INTEL_RS3UC080_BRANDING); 2605 break; 2606 default: 2607 pr_info(MPT3SAS_FMT 2608 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2609 ioc->name, ioc->pdev->subsystem_device); 2610 break; 2611 } 2612 break; 2613 default: 2614 pr_info(MPT3SAS_FMT 2615 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2616 ioc->name, ioc->pdev->subsystem_device); 2617 break; 2618 } 2619 break; 2620 case PCI_VENDOR_ID_DELL: 2621 switch (ioc->pdev->device) { 2622 case MPI2_MFGPAGE_DEVID_SAS2008: 2623 switch (ioc->pdev->subsystem_device) { 2624 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 2625 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2626 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 2627 break; 2628 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 2629 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2630 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 2631 break; 2632 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 2633 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2634 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 2635 break; 2636 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 2637 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2638 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 2639 break; 2640 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 2641 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2642 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 2643 break; 2644 case MPT2SAS_DELL_PERC_H200_SSDID: 2645 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2646 MPT2SAS_DELL_PERC_H200_BRANDING); 2647 break; 2648 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 2649 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2650 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 2651 break; 2652 default: 2653 pr_info(MPT3SAS_FMT 2654 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 2655 ioc->name, ioc->pdev->subsystem_device); 2656 break; 2657 } 2658 break; 2659 case MPI25_MFGPAGE_DEVID_SAS3008: 2660 switch (ioc->pdev->subsystem_device) { 2661 case MPT3SAS_DELL_12G_HBA_SSDID: 2662 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2663 MPT3SAS_DELL_12G_HBA_BRANDING); 2664 break; 2665 default: 2666 pr_info(MPT3SAS_FMT 2667 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 2668 ioc->name, ioc->pdev->subsystem_device); 2669 break; 2670 } 2671 break; 2672 default: 2673 pr_info(MPT3SAS_FMT 2674 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, 2675 ioc->pdev->subsystem_device); 2676 break; 2677 } 2678 break; 2679 case PCI_VENDOR_ID_CISCO: 2680 switch (ioc->pdev->device) { 2681 case MPI25_MFGPAGE_DEVID_SAS3008: 2682 switch (ioc->pdev->subsystem_device) { 2683 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 2684 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2685 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 2686 break; 2687 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 2688 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2689 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 2690 break; 2691 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2692 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2693 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2694 break; 2695 default: 2696 pr_info(MPT3SAS_FMT 2697 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2698 ioc->name, ioc->pdev->subsystem_device); 2699 break; 2700 } 2701 break; 2702 case MPI25_MFGPAGE_DEVID_SAS3108_1: 2703 switch (ioc->pdev->subsystem_device) { 2704 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2705 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2706 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2707 break; 2708 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 2709 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2710 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING 2711 ); 2712 break; 2713 default: 2714 pr_info(MPT3SAS_FMT 2715 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2716 ioc->name, ioc->pdev->subsystem_device); 2717 break; 2718 } 2719 break; 2720 default: 2721 pr_info(MPT3SAS_FMT 2722 "Cisco SAS HBA: Subsystem ID: 0x%X\n", 2723 ioc->name, ioc->pdev->subsystem_device); 2724 break; 2725 } 2726 break; 2727 case MPT2SAS_HP_3PAR_SSVID: 2728 switch (ioc->pdev->device) { 2729 case MPI2_MFGPAGE_DEVID_SAS2004: 2730 switch (ioc->pdev->subsystem_device) { 2731 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 2732 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2733 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 2734 break; 2735 default: 2736 pr_info(MPT3SAS_FMT 2737 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2738 ioc->name, ioc->pdev->subsystem_device); 2739 break; 2740 } 2741 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2742 switch (ioc->pdev->subsystem_device) { 2743 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 2744 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2745 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 2746 break; 2747 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 2748 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2749 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 2750 break; 2751 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 2752 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2753 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 2754 break; 2755 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 2756 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2757 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 2758 break; 2759 default: 2760 pr_info(MPT3SAS_FMT 2761 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2762 ioc->name, ioc->pdev->subsystem_device); 2763 break; 2764 } 2765 default: 2766 pr_info(MPT3SAS_FMT 2767 "HP SAS HBA: Subsystem ID: 0x%X\n", 2768 ioc->name, ioc->pdev->subsystem_device); 2769 break; 2770 } 2771 default: 2772 break; 2773 } 2774 } 2775 2776 /** 2777 * _base_display_ioc_capabilities - Disply IOC's capabilities. 2778 * @ioc: per adapter object 2779 * 2780 * Return nothing. 2781 */ 2782 static void 2783 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 2784 { 2785 int i = 0; 2786 char desc[16]; 2787 u32 iounit_pg1_flags; 2788 u32 bios_version; 2789 2790 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 2791 strncpy(desc, ioc->manu_pg0.ChipName, 16); 2792 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ 2793 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 2794 ioc->name, desc, 2795 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 2796 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 2797 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 2798 ioc->facts.FWVersion.Word & 0x000000FF, 2799 ioc->pdev->revision, 2800 (bios_version & 0xFF000000) >> 24, 2801 (bios_version & 0x00FF0000) >> 16, 2802 (bios_version & 0x0000FF00) >> 8, 2803 bios_version & 0x000000FF); 2804 2805 _base_display_OEMs_branding(ioc); 2806 2807 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); 2808 2809 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2810 pr_info("Initiator"); 2811 i++; 2812 } 2813 2814 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2815 pr_info("%sTarget", i ? "," : ""); 2816 i++; 2817 } 2818 2819 i = 0; 2820 pr_info("), "); 2821 pr_info("Capabilities=("); 2822 2823 if (!ioc->hide_ir_msg) { 2824 if (ioc->facts.IOCCapabilities & 2825 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 2826 pr_info("Raid"); 2827 i++; 2828 } 2829 } 2830 2831 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 2832 pr_info("%sTLR", i ? "," : ""); 2833 i++; 2834 } 2835 2836 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 2837 pr_info("%sMulticast", i ? "," : ""); 2838 i++; 2839 } 2840 2841 if (ioc->facts.IOCCapabilities & 2842 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 2843 pr_info("%sBIDI Target", i ? "," : ""); 2844 i++; 2845 } 2846 2847 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 2848 pr_info("%sEEDP", i ? "," : ""); 2849 i++; 2850 } 2851 2852 if (ioc->facts.IOCCapabilities & 2853 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 2854 pr_info("%sSnapshot Buffer", i ? "," : ""); 2855 i++; 2856 } 2857 2858 if (ioc->facts.IOCCapabilities & 2859 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 2860 pr_info("%sDiag Trace Buffer", i ? "," : ""); 2861 i++; 2862 } 2863 2864 if (ioc->facts.IOCCapabilities & 2865 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 2866 pr_info("%sDiag Extended Buffer", i ? "," : ""); 2867 i++; 2868 } 2869 2870 if (ioc->facts.IOCCapabilities & 2871 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 2872 pr_info("%sTask Set Full", i ? "," : ""); 2873 i++; 2874 } 2875 2876 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 2877 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 2878 pr_info("%sNCQ", i ? "," : ""); 2879 i++; 2880 } 2881 2882 pr_info(")\n"); 2883 } 2884 2885 /** 2886 * mpt3sas_base_update_missing_delay - change the missing delay timers 2887 * @ioc: per adapter object 2888 * @device_missing_delay: amount of time till device is reported missing 2889 * @io_missing_delay: interval IO is returned when there is a missing device 2890 * 2891 * Return nothing. 2892 * 2893 * Passed on the command line, this function will modify the device missing 2894 * delay, as well as the io missing delay. This should be called at driver 2895 * load time. 2896 */ 2897 void 2898 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 2899 u16 device_missing_delay, u8 io_missing_delay) 2900 { 2901 u16 dmd, dmd_new, dmd_orignal; 2902 u8 io_missing_delay_original; 2903 u16 sz; 2904 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 2905 Mpi2ConfigReply_t mpi_reply; 2906 u8 num_phys = 0; 2907 u16 ioc_status; 2908 2909 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 2910 if (!num_phys) 2911 return; 2912 2913 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 2914 sizeof(Mpi2SasIOUnit1PhyData_t)); 2915 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 2916 if (!sas_iounit_pg1) { 2917 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2918 ioc->name, __FILE__, __LINE__, __func__); 2919 goto out; 2920 } 2921 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 2922 sas_iounit_pg1, sz))) { 2923 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2924 ioc->name, __FILE__, __LINE__, __func__); 2925 goto out; 2926 } 2927 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 2928 MPI2_IOCSTATUS_MASK; 2929 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 2930 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2931 ioc->name, __FILE__, __LINE__, __func__); 2932 goto out; 2933 } 2934 2935 /* device missing delay */ 2936 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 2937 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 2938 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 2939 else 2940 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 2941 dmd_orignal = dmd; 2942 if (device_missing_delay > 0x7F) { 2943 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 2944 device_missing_delay; 2945 dmd = dmd / 16; 2946 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 2947 } else 2948 dmd = device_missing_delay; 2949 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 2950 2951 /* io missing delay */ 2952 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 2953 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 2954 2955 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 2956 sz)) { 2957 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 2958 dmd_new = (dmd & 2959 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 2960 else 2961 dmd_new = 2962 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 2963 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", 2964 ioc->name, dmd_orignal, dmd_new); 2965 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", 2966 ioc->name, io_missing_delay_original, 2967 io_missing_delay); 2968 ioc->device_missing_delay = dmd_new; 2969 ioc->io_missing_delay = io_missing_delay; 2970 } 2971 2972 out: 2973 kfree(sas_iounit_pg1); 2974 } 2975 /** 2976 * _base_static_config_pages - static start of day config pages 2977 * @ioc: per adapter object 2978 * 2979 * Return nothing. 2980 */ 2981 static void 2982 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 2983 { 2984 Mpi2ConfigReply_t mpi_reply; 2985 u32 iounit_pg1_flags; 2986 2987 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); 2988 if (ioc->ir_firmware) 2989 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 2990 &ioc->manu_pg10); 2991 2992 /* 2993 * Ensure correct T10 PI operation if vendor left EEDPTagMode 2994 * flag unset in NVDATA. 2995 */ 2996 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); 2997 if (ioc->manu_pg11.EEDPTagMode == 0) { 2998 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 2999 ioc->name); 3000 ioc->manu_pg11.EEDPTagMode &= ~0x3; 3001 ioc->manu_pg11.EEDPTagMode |= 0x1; 3002 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 3003 &ioc->manu_pg11); 3004 } 3005 3006 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 3007 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 3008 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 3009 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 3010 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3011 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 3012 _base_display_ioc_capabilities(ioc); 3013 3014 /* 3015 * Enable task_set_full handling in iounit_pg1 when the 3016 * facts capabilities indicate that its supported. 3017 */ 3018 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3019 if ((ioc->facts.IOCCapabilities & 3020 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 3021 iounit_pg1_flags &= 3022 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3023 else 3024 iounit_pg1_flags |= 3025 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3026 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 3027 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3028 3029 if (ioc->iounit_pg8.NumSensors) 3030 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 3031 } 3032 3033 /** 3034 * _base_release_memory_pools - release memory 3035 * @ioc: per adapter object 3036 * 3037 * Free memory allocated from _base_allocate_memory_pools. 3038 * 3039 * Return nothing. 3040 */ 3041 static void 3042 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 3043 { 3044 int i = 0; 3045 struct reply_post_struct *rps; 3046 3047 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3048 __func__)); 3049 3050 if (ioc->request) { 3051 pci_free_consistent(ioc->pdev, ioc->request_dma_sz, 3052 ioc->request, ioc->request_dma); 3053 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3054 "request_pool(0x%p): free\n", 3055 ioc->name, ioc->request)); 3056 ioc->request = NULL; 3057 } 3058 3059 if (ioc->sense) { 3060 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 3061 if (ioc->sense_dma_pool) 3062 pci_pool_destroy(ioc->sense_dma_pool); 3063 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3064 "sense_pool(0x%p): free\n", 3065 ioc->name, ioc->sense)); 3066 ioc->sense = NULL; 3067 } 3068 3069 if (ioc->reply) { 3070 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 3071 if (ioc->reply_dma_pool) 3072 pci_pool_destroy(ioc->reply_dma_pool); 3073 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3074 "reply_pool(0x%p): free\n", 3075 ioc->name, ioc->reply)); 3076 ioc->reply = NULL; 3077 } 3078 3079 if (ioc->reply_free) { 3080 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 3081 ioc->reply_free_dma); 3082 if (ioc->reply_free_dma_pool) 3083 pci_pool_destroy(ioc->reply_free_dma_pool); 3084 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3085 "reply_free_pool(0x%p): free\n", 3086 ioc->name, ioc->reply_free)); 3087 ioc->reply_free = NULL; 3088 } 3089 3090 if (ioc->reply_post) { 3091 do { 3092 rps = &ioc->reply_post[i]; 3093 if (rps->reply_post_free) { 3094 pci_pool_free( 3095 ioc->reply_post_free_dma_pool, 3096 rps->reply_post_free, 3097 rps->reply_post_free_dma); 3098 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3099 "reply_post_free_pool(0x%p): free\n", 3100 ioc->name, rps->reply_post_free)); 3101 rps->reply_post_free = NULL; 3102 } 3103 } while (ioc->rdpq_array_enable && 3104 (++i < ioc->reply_queue_count)); 3105 3106 if (ioc->reply_post_free_dma_pool) 3107 pci_pool_destroy(ioc->reply_post_free_dma_pool); 3108 kfree(ioc->reply_post); 3109 } 3110 3111 if (ioc->config_page) { 3112 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3113 "config_page(0x%p): free\n", ioc->name, 3114 ioc->config_page)); 3115 pci_free_consistent(ioc->pdev, ioc->config_page_sz, 3116 ioc->config_page, ioc->config_page_dma); 3117 } 3118 3119 if (ioc->scsi_lookup) { 3120 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages); 3121 ioc->scsi_lookup = NULL; 3122 } 3123 kfree(ioc->hpr_lookup); 3124 kfree(ioc->internal_lookup); 3125 if (ioc->chain_lookup) { 3126 for (i = 0; i < ioc->chain_depth; i++) { 3127 if (ioc->chain_lookup[i].chain_buffer) 3128 pci_pool_free(ioc->chain_dma_pool, 3129 ioc->chain_lookup[i].chain_buffer, 3130 ioc->chain_lookup[i].chain_buffer_dma); 3131 } 3132 if (ioc->chain_dma_pool) 3133 pci_pool_destroy(ioc->chain_dma_pool); 3134 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages); 3135 ioc->chain_lookup = NULL; 3136 } 3137 } 3138 3139 /** 3140 * _base_allocate_memory_pools - allocate start of day memory pools 3141 * @ioc: per adapter object 3142 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3143 * 3144 * Returns 0 success, anything else error 3145 */ 3146 static int 3147 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 3148 { 3149 struct mpt3sas_facts *facts; 3150 u16 max_sge_elements; 3151 u16 chains_needed_per_io; 3152 u32 sz, total_sz, reply_post_free_sz; 3153 u32 retry_sz; 3154 u16 max_request_credit; 3155 unsigned short sg_tablesize; 3156 u16 sge_size; 3157 int i; 3158 3159 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3160 __func__)); 3161 3162 3163 retry_sz = 0; 3164 facts = &ioc->facts; 3165 3166 /* command line tunables for max sgl entries */ 3167 if (max_sgl_entries != -1) 3168 sg_tablesize = max_sgl_entries; 3169 else { 3170 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 3171 sg_tablesize = MPT2SAS_SG_DEPTH; 3172 else 3173 sg_tablesize = MPT3SAS_SG_DEPTH; 3174 } 3175 3176 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 3177 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 3178 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 3179 sg_tablesize = min_t(unsigned short, sg_tablesize, 3180 SCSI_MAX_SG_CHAIN_SEGMENTS); 3181 pr_warn(MPT3SAS_FMT 3182 "sg_tablesize(%u) is bigger than kernel" 3183 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name, 3184 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 3185 } 3186 ioc->shost->sg_tablesize = sg_tablesize; 3187 3188 ioc->hi_priority_depth = facts->HighPriorityCredit; 3189 ioc->internal_depth = ioc->hi_priority_depth + (5); 3190 /* command line tunables for max controller queue depth */ 3191 if (max_queue_depth != -1 && max_queue_depth != 0) { 3192 max_request_credit = min_t(u16, max_queue_depth + 3193 ioc->hi_priority_depth + ioc->internal_depth, 3194 facts->RequestCredit); 3195 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 3196 max_request_credit = MAX_HBA_QUEUE_DEPTH; 3197 } else 3198 max_request_credit = min_t(u16, facts->RequestCredit, 3199 MAX_HBA_QUEUE_DEPTH); 3200 3201 ioc->hba_queue_depth = max_request_credit; 3202 3203 /* request frame size */ 3204 ioc->request_sz = facts->IOCRequestFrameSize * 4; 3205 3206 /* reply frame size */ 3207 ioc->reply_sz = facts->ReplyFrameSize * 4; 3208 3209 /* calculate the max scatter element size */ 3210 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 3211 3212 retry_allocation: 3213 total_sz = 0; 3214 /* calculate number of sg elements left over in the 1st frame */ 3215 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 3216 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 3217 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 3218 3219 /* now do the same for a chain buffer */ 3220 max_sge_elements = ioc->request_sz - sge_size; 3221 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 3222 3223 /* 3224 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 3225 */ 3226 chains_needed_per_io = ((ioc->shost->sg_tablesize - 3227 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 3228 + 1; 3229 if (chains_needed_per_io > facts->MaxChainDepth) { 3230 chains_needed_per_io = facts->MaxChainDepth; 3231 ioc->shost->sg_tablesize = min_t(u16, 3232 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 3233 * chains_needed_per_io), ioc->shost->sg_tablesize); 3234 } 3235 ioc->chains_needed_per_io = chains_needed_per_io; 3236 3237 /* reply free queue sizing - taking into account for 64 FW events */ 3238 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3239 3240 /* calculate reply descriptor post queue depth */ 3241 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 3242 ioc->reply_free_queue_depth + 1 ; 3243 /* align the reply post queue on the next 16 count boundary */ 3244 if (ioc->reply_post_queue_depth % 16) 3245 ioc->reply_post_queue_depth += 16 - 3246 (ioc->reply_post_queue_depth % 16); 3247 3248 3249 if (ioc->reply_post_queue_depth > 3250 facts->MaxReplyDescriptorPostQueueDepth) { 3251 ioc->reply_post_queue_depth = 3252 facts->MaxReplyDescriptorPostQueueDepth - 3253 (facts->MaxReplyDescriptorPostQueueDepth % 16); 3254 ioc->hba_queue_depth = 3255 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 3256 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3257 } 3258 3259 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ 3260 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " 3261 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, 3262 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, 3263 ioc->chains_needed_per_io)); 3264 3265 /* reply post queue, 16 byte align */ 3266 reply_post_free_sz = ioc->reply_post_queue_depth * 3267 sizeof(Mpi2DefaultReplyDescriptor_t); 3268 3269 sz = reply_post_free_sz; 3270 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 3271 sz *= ioc->reply_queue_count; 3272 3273 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? 3274 (ioc->reply_queue_count):1, 3275 sizeof(struct reply_post_struct), GFP_KERNEL); 3276 3277 if (!ioc->reply_post) { 3278 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", 3279 ioc->name); 3280 goto out; 3281 } 3282 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool", 3283 ioc->pdev, sz, 16, 0); 3284 if (!ioc->reply_post_free_dma_pool) { 3285 pr_err(MPT3SAS_FMT 3286 "reply_post_free pool: pci_pool_create failed\n", 3287 ioc->name); 3288 goto out; 3289 } 3290 i = 0; 3291 do { 3292 ioc->reply_post[i].reply_post_free = 3293 pci_pool_alloc(ioc->reply_post_free_dma_pool, 3294 GFP_KERNEL, 3295 &ioc->reply_post[i].reply_post_free_dma); 3296 if (!ioc->reply_post[i].reply_post_free) { 3297 pr_err(MPT3SAS_FMT 3298 "reply_post_free pool: pci_pool_alloc failed\n", 3299 ioc->name); 3300 goto out; 3301 } 3302 memset(ioc->reply_post[i].reply_post_free, 0, sz); 3303 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3304 "reply post free pool (0x%p): depth(%d)," 3305 "element_size(%d), pool_size(%d kB)\n", ioc->name, 3306 ioc->reply_post[i].reply_post_free, 3307 ioc->reply_post_queue_depth, 8, sz/1024)); 3308 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3309 "reply_post_free_dma = (0x%llx)\n", ioc->name, 3310 (unsigned long long) 3311 ioc->reply_post[i].reply_post_free_dma)); 3312 total_sz += sz; 3313 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); 3314 3315 if (ioc->dma_mask == 64) { 3316 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { 3317 pr_warn(MPT3SAS_FMT 3318 "no suitable consistent DMA mask for %s\n", 3319 ioc->name, pci_name(ioc->pdev)); 3320 goto out; 3321 } 3322 } 3323 3324 ioc->scsiio_depth = ioc->hba_queue_depth - 3325 ioc->hi_priority_depth - ioc->internal_depth; 3326 3327 /* set the scsi host can_queue depth 3328 * with some internal commands that could be outstanding 3329 */ 3330 ioc->shost->can_queue = ioc->scsiio_depth; 3331 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3332 "scsi host: can_queue depth (%d)\n", 3333 ioc->name, ioc->shost->can_queue)); 3334 3335 3336 /* contiguous pool for request and chains, 16 byte align, one extra " 3337 * "frame for smid=0 3338 */ 3339 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 3340 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 3341 3342 /* hi-priority queue */ 3343 sz += (ioc->hi_priority_depth * ioc->request_sz); 3344 3345 /* internal queue */ 3346 sz += (ioc->internal_depth * ioc->request_sz); 3347 3348 ioc->request_dma_sz = sz; 3349 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); 3350 if (!ioc->request) { 3351 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3352 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3353 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, 3354 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3355 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 3356 goto out; 3357 retry_sz += 64; 3358 ioc->hba_queue_depth = max_request_credit - retry_sz; 3359 goto retry_allocation; 3360 } 3361 3362 if (retry_sz) 3363 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3364 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3365 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, 3366 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3367 3368 /* hi-priority queue */ 3369 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 3370 ioc->request_sz); 3371 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 3372 ioc->request_sz); 3373 3374 /* internal queue */ 3375 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 3376 ioc->request_sz); 3377 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 3378 ioc->request_sz); 3379 3380 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3381 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3382 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, 3383 (ioc->hba_queue_depth * ioc->request_sz)/1024)); 3384 3385 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", 3386 ioc->name, (unsigned long long) ioc->request_dma)); 3387 total_sz += sz; 3388 3389 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker); 3390 ioc->scsi_lookup_pages = get_order(sz); 3391 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages( 3392 GFP_KERNEL, ioc->scsi_lookup_pages); 3393 if (!ioc->scsi_lookup) { 3394 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n", 3395 ioc->name, (int)sz); 3396 goto out; 3397 } 3398 3399 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", 3400 ioc->name, ioc->request, ioc->scsiio_depth)); 3401 3402 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 3403 sz = ioc->chain_depth * sizeof(struct chain_tracker); 3404 ioc->chain_pages = get_order(sz); 3405 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages( 3406 GFP_KERNEL, ioc->chain_pages); 3407 if (!ioc->chain_lookup) { 3408 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n", 3409 ioc->name); 3410 goto out; 3411 } 3412 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev, 3413 ioc->request_sz, 16, 0); 3414 if (!ioc->chain_dma_pool) { 3415 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n", 3416 ioc->name); 3417 goto out; 3418 } 3419 for (i = 0; i < ioc->chain_depth; i++) { 3420 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc( 3421 ioc->chain_dma_pool , GFP_KERNEL, 3422 &ioc->chain_lookup[i].chain_buffer_dma); 3423 if (!ioc->chain_lookup[i].chain_buffer) { 3424 ioc->chain_depth = i; 3425 goto chain_done; 3426 } 3427 total_sz += ioc->request_sz; 3428 } 3429 chain_done: 3430 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3431 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 3432 ioc->name, ioc->chain_depth, ioc->request_sz, 3433 ((ioc->chain_depth * ioc->request_sz))/1024)); 3434 3435 /* initialize hi-priority queue smid's */ 3436 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 3437 sizeof(struct request_tracker), GFP_KERNEL); 3438 if (!ioc->hpr_lookup) { 3439 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", 3440 ioc->name); 3441 goto out; 3442 } 3443 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 3444 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3445 "hi_priority(0x%p): depth(%d), start smid(%d)\n", 3446 ioc->name, ioc->hi_priority, 3447 ioc->hi_priority_depth, ioc->hi_priority_smid)); 3448 3449 /* initialize internal queue smid's */ 3450 ioc->internal_lookup = kcalloc(ioc->internal_depth, 3451 sizeof(struct request_tracker), GFP_KERNEL); 3452 if (!ioc->internal_lookup) { 3453 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", 3454 ioc->name); 3455 goto out; 3456 } 3457 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 3458 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3459 "internal(0x%p): depth(%d), start smid(%d)\n", 3460 ioc->name, ioc->internal, 3461 ioc->internal_depth, ioc->internal_smid)); 3462 3463 /* sense buffers, 4 byte align */ 3464 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 3465 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4, 3466 0); 3467 if (!ioc->sense_dma_pool) { 3468 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n", 3469 ioc->name); 3470 goto out; 3471 } 3472 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL, 3473 &ioc->sense_dma); 3474 if (!ioc->sense) { 3475 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n", 3476 ioc->name); 3477 goto out; 3478 } 3479 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3480 "sense pool(0x%p): depth(%d), element_size(%d), pool_size" 3481 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, 3482 SCSI_SENSE_BUFFERSIZE, sz/1024)); 3483 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", 3484 ioc->name, (unsigned long long)ioc->sense_dma)); 3485 total_sz += sz; 3486 3487 /* reply pool, 4 byte align */ 3488 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 3489 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4, 3490 0); 3491 if (!ioc->reply_dma_pool) { 3492 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n", 3493 ioc->name); 3494 goto out; 3495 } 3496 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL, 3497 &ioc->reply_dma); 3498 if (!ioc->reply) { 3499 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n", 3500 ioc->name); 3501 goto out; 3502 } 3503 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 3504 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 3505 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3506 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3507 ioc->name, ioc->reply, 3508 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); 3509 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", 3510 ioc->name, (unsigned long long)ioc->reply_dma)); 3511 total_sz += sz; 3512 3513 /* reply free queue, 16 byte align */ 3514 sz = ioc->reply_free_queue_depth * 4; 3515 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool", 3516 ioc->pdev, sz, 16, 0); 3517 if (!ioc->reply_free_dma_pool) { 3518 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n", 3519 ioc->name); 3520 goto out; 3521 } 3522 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL, 3523 &ioc->reply_free_dma); 3524 if (!ioc->reply_free) { 3525 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n", 3526 ioc->name); 3527 goto out; 3528 } 3529 memset(ioc->reply_free, 0, sz); 3530 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ 3531 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, 3532 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 3533 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3534 "reply_free_dma (0x%llx)\n", 3535 ioc->name, (unsigned long long)ioc->reply_free_dma)); 3536 total_sz += sz; 3537 3538 ioc->config_page_sz = 512; 3539 ioc->config_page = pci_alloc_consistent(ioc->pdev, 3540 ioc->config_page_sz, &ioc->config_page_dma); 3541 if (!ioc->config_page) { 3542 pr_err(MPT3SAS_FMT 3543 "config page: pci_pool_alloc failed\n", 3544 ioc->name); 3545 goto out; 3546 } 3547 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3548 "config page(0x%p): size(%d)\n", 3549 ioc->name, ioc->config_page, ioc->config_page_sz)); 3550 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", 3551 ioc->name, (unsigned long long)ioc->config_page_dma)); 3552 total_sz += ioc->config_page_sz; 3553 3554 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", 3555 ioc->name, total_sz/1024); 3556 pr_info(MPT3SAS_FMT 3557 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 3558 ioc->name, ioc->shost->can_queue, facts->RequestCredit); 3559 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", 3560 ioc->name, ioc->shost->sg_tablesize); 3561 return 0; 3562 3563 out: 3564 return -ENOMEM; 3565 } 3566 3567 /** 3568 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 3569 * @ioc: Pointer to MPT_ADAPTER structure 3570 * @cooked: Request raw or cooked IOC state 3571 * 3572 * Returns all IOC Doorbell register bits if cooked==0, else just the 3573 * Doorbell bits in MPI_IOC_STATE_MASK. 3574 */ 3575 u32 3576 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 3577 { 3578 u32 s, sc; 3579 3580 s = readl(&ioc->chip->Doorbell); 3581 sc = s & MPI2_IOC_STATE_MASK; 3582 return cooked ? sc : s; 3583 } 3584 3585 /** 3586 * _base_wait_on_iocstate - waiting on a particular ioc state 3587 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 3588 * @timeout: timeout in second 3589 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3590 * 3591 * Returns 0 for success, non-zero for failure. 3592 */ 3593 static int 3594 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout, 3595 int sleep_flag) 3596 { 3597 u32 count, cntdn; 3598 u32 current_state; 3599 3600 count = 0; 3601 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3602 do { 3603 current_state = mpt3sas_base_get_iocstate(ioc, 1); 3604 if (current_state == ioc_state) 3605 return 0; 3606 if (count && current_state == MPI2_IOC_STATE_FAULT) 3607 break; 3608 if (sleep_flag == CAN_SLEEP) 3609 usleep_range(1000, 1500); 3610 else 3611 udelay(500); 3612 count++; 3613 } while (--cntdn); 3614 3615 return current_state; 3616 } 3617 3618 /** 3619 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 3620 * a write to the doorbell) 3621 * @ioc: per adapter object 3622 * @timeout: timeout in second 3623 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3624 * 3625 * Returns 0 for success, non-zero for failure. 3626 * 3627 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 3628 */ 3629 static int 3630 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag); 3631 3632 static int 3633 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout, 3634 int sleep_flag) 3635 { 3636 u32 cntdn, count; 3637 u32 int_status; 3638 3639 count = 0; 3640 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3641 do { 3642 int_status = readl(&ioc->chip->HostInterruptStatus); 3643 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3644 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3645 "%s: successful count(%d), timeout(%d)\n", 3646 ioc->name, __func__, count, timeout)); 3647 return 0; 3648 } 3649 if (sleep_flag == CAN_SLEEP) 3650 usleep_range(1000, 1500); 3651 else 3652 udelay(500); 3653 count++; 3654 } while (--cntdn); 3655 3656 pr_err(MPT3SAS_FMT 3657 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3658 ioc->name, __func__, count, int_status); 3659 return -EFAULT; 3660 } 3661 3662 /** 3663 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 3664 * @ioc: per adapter object 3665 * @timeout: timeout in second 3666 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3667 * 3668 * Returns 0 for success, non-zero for failure. 3669 * 3670 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 3671 * doorbell. 3672 */ 3673 static int 3674 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout, 3675 int sleep_flag) 3676 { 3677 u32 cntdn, count; 3678 u32 int_status; 3679 u32 doorbell; 3680 3681 count = 0; 3682 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3683 do { 3684 int_status = readl(&ioc->chip->HostInterruptStatus); 3685 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 3686 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3687 "%s: successful count(%d), timeout(%d)\n", 3688 ioc->name, __func__, count, timeout)); 3689 return 0; 3690 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3691 doorbell = readl(&ioc->chip->Doorbell); 3692 if ((doorbell & MPI2_IOC_STATE_MASK) == 3693 MPI2_IOC_STATE_FAULT) { 3694 mpt3sas_base_fault_info(ioc , doorbell); 3695 return -EFAULT; 3696 } 3697 } else if (int_status == 0xFFFFFFFF) 3698 goto out; 3699 3700 if (sleep_flag == CAN_SLEEP) 3701 usleep_range(1000, 1500); 3702 else 3703 udelay(500); 3704 count++; 3705 } while (--cntdn); 3706 3707 out: 3708 pr_err(MPT3SAS_FMT 3709 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3710 ioc->name, __func__, count, int_status); 3711 return -EFAULT; 3712 } 3713 3714 /** 3715 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 3716 * @ioc: per adapter object 3717 * @timeout: timeout in second 3718 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3719 * 3720 * Returns 0 for success, non-zero for failure. 3721 * 3722 */ 3723 static int 3724 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout, 3725 int sleep_flag) 3726 { 3727 u32 cntdn, count; 3728 u32 doorbell_reg; 3729 3730 count = 0; 3731 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3732 do { 3733 doorbell_reg = readl(&ioc->chip->Doorbell); 3734 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 3735 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3736 "%s: successful count(%d), timeout(%d)\n", 3737 ioc->name, __func__, count, timeout)); 3738 return 0; 3739 } 3740 if (sleep_flag == CAN_SLEEP) 3741 usleep_range(1000, 1500); 3742 else 3743 udelay(500); 3744 count++; 3745 } while (--cntdn); 3746 3747 pr_err(MPT3SAS_FMT 3748 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 3749 ioc->name, __func__, count, doorbell_reg); 3750 return -EFAULT; 3751 } 3752 3753 /** 3754 * _base_send_ioc_reset - send doorbell reset 3755 * @ioc: per adapter object 3756 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 3757 * @timeout: timeout in second 3758 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3759 * 3760 * Returns 0 for success, non-zero for failure. 3761 */ 3762 static int 3763 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout, 3764 int sleep_flag) 3765 { 3766 u32 ioc_state; 3767 int r = 0; 3768 3769 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 3770 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", 3771 ioc->name, __func__); 3772 return -EFAULT; 3773 } 3774 3775 if (!(ioc->facts.IOCCapabilities & 3776 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 3777 return -EFAULT; 3778 3779 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); 3780 3781 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 3782 &ioc->chip->Doorbell); 3783 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) { 3784 r = -EFAULT; 3785 goto out; 3786 } 3787 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 3788 timeout, sleep_flag); 3789 if (ioc_state) { 3790 pr_err(MPT3SAS_FMT 3791 "%s: failed going to ready state (ioc_state=0x%x)\n", 3792 ioc->name, __func__, ioc_state); 3793 r = -EFAULT; 3794 goto out; 3795 } 3796 out: 3797 pr_info(MPT3SAS_FMT "message unit reset: %s\n", 3798 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); 3799 return r; 3800 } 3801 3802 /** 3803 * _base_handshake_req_reply_wait - send request thru doorbell interface 3804 * @ioc: per adapter object 3805 * @request_bytes: request length 3806 * @request: pointer having request payload 3807 * @reply_bytes: reply length 3808 * @reply: pointer to reply payload 3809 * @timeout: timeout in second 3810 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3811 * 3812 * Returns 0 for success, non-zero for failure. 3813 */ 3814 static int 3815 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 3816 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag) 3817 { 3818 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 3819 int i; 3820 u8 failed; 3821 u16 dummy; 3822 __le32 *mfp; 3823 3824 /* make sure doorbell is not in use */ 3825 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 3826 pr_err(MPT3SAS_FMT 3827 "doorbell is in use (line=%d)\n", 3828 ioc->name, __LINE__); 3829 return -EFAULT; 3830 } 3831 3832 /* clear pending doorbell interrupts from previous state changes */ 3833 if (readl(&ioc->chip->HostInterruptStatus) & 3834 MPI2_HIS_IOC2SYS_DB_STATUS) 3835 writel(0, &ioc->chip->HostInterruptStatus); 3836 3837 /* send message to ioc */ 3838 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 3839 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 3840 &ioc->chip->Doorbell); 3841 3842 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) { 3843 pr_err(MPT3SAS_FMT 3844 "doorbell handshake int failed (line=%d)\n", 3845 ioc->name, __LINE__); 3846 return -EFAULT; 3847 } 3848 writel(0, &ioc->chip->HostInterruptStatus); 3849 3850 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) { 3851 pr_err(MPT3SAS_FMT 3852 "doorbell handshake ack failed (line=%d)\n", 3853 ioc->name, __LINE__); 3854 return -EFAULT; 3855 } 3856 3857 /* send message 32-bits at a time */ 3858 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 3859 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 3860 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) 3861 failed = 1; 3862 } 3863 3864 if (failed) { 3865 pr_err(MPT3SAS_FMT 3866 "doorbell handshake sending request failed (line=%d)\n", 3867 ioc->name, __LINE__); 3868 return -EFAULT; 3869 } 3870 3871 /* now wait for the reply */ 3872 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) { 3873 pr_err(MPT3SAS_FMT 3874 "doorbell handshake int failed (line=%d)\n", 3875 ioc->name, __LINE__); 3876 return -EFAULT; 3877 } 3878 3879 /* read the first two 16-bits, it gives the total length of the reply */ 3880 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3881 & MPI2_DOORBELL_DATA_MASK); 3882 writel(0, &ioc->chip->HostInterruptStatus); 3883 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { 3884 pr_err(MPT3SAS_FMT 3885 "doorbell handshake int failed (line=%d)\n", 3886 ioc->name, __LINE__); 3887 return -EFAULT; 3888 } 3889 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3890 & MPI2_DOORBELL_DATA_MASK); 3891 writel(0, &ioc->chip->HostInterruptStatus); 3892 3893 for (i = 2; i < default_reply->MsgLength * 2; i++) { 3894 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { 3895 pr_err(MPT3SAS_FMT 3896 "doorbell handshake int failed (line=%d)\n", 3897 ioc->name, __LINE__); 3898 return -EFAULT; 3899 } 3900 if (i >= reply_bytes/2) /* overflow case */ 3901 dummy = readl(&ioc->chip->Doorbell); 3902 else 3903 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3904 & MPI2_DOORBELL_DATA_MASK); 3905 writel(0, &ioc->chip->HostInterruptStatus); 3906 } 3907 3908 _base_wait_for_doorbell_int(ioc, 5, sleep_flag); 3909 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) { 3910 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3911 "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); 3912 } 3913 writel(0, &ioc->chip->HostInterruptStatus); 3914 3915 if (ioc->logging_level & MPT_DEBUG_INIT) { 3916 mfp = (__le32 *)reply; 3917 pr_info("\toffset:data\n"); 3918 for (i = 0; i < reply_bytes/4; i++) 3919 pr_info("\t[0x%02x]:%08x\n", i*4, 3920 le32_to_cpu(mfp[i])); 3921 } 3922 return 0; 3923 } 3924 3925 /** 3926 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 3927 * @ioc: per adapter object 3928 * @mpi_reply: the reply payload from FW 3929 * @mpi_request: the request payload sent to FW 3930 * 3931 * The SAS IO Unit Control Request message allows the host to perform low-level 3932 * operations, such as resets on the PHYs of the IO Unit, also allows the host 3933 * to obtain the IOC assigned device handles for a device if it has other 3934 * identifying information about the device, in addition allows the host to 3935 * remove IOC resources associated with the device. 3936 * 3937 * Returns 0 for success, non-zero for failure. 3938 */ 3939 int 3940 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 3941 Mpi2SasIoUnitControlReply_t *mpi_reply, 3942 Mpi2SasIoUnitControlRequest_t *mpi_request) 3943 { 3944 u16 smid; 3945 u32 ioc_state; 3946 unsigned long timeleft; 3947 bool issue_reset = false; 3948 int rc; 3949 void *request; 3950 u16 wait_state_count; 3951 3952 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3953 __func__)); 3954 3955 mutex_lock(&ioc->base_cmds.mutex); 3956 3957 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 3958 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 3959 ioc->name, __func__); 3960 rc = -EAGAIN; 3961 goto out; 3962 } 3963 3964 wait_state_count = 0; 3965 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3966 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 3967 if (wait_state_count++ == 10) { 3968 pr_err(MPT3SAS_FMT 3969 "%s: failed due to ioc not operational\n", 3970 ioc->name, __func__); 3971 rc = -EFAULT; 3972 goto out; 3973 } 3974 ssleep(1); 3975 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3976 pr_info(MPT3SAS_FMT 3977 "%s: waiting for operational state(count=%d)\n", 3978 ioc->name, __func__, wait_state_count); 3979 } 3980 3981 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 3982 if (!smid) { 3983 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 3984 ioc->name, __func__); 3985 rc = -EAGAIN; 3986 goto out; 3987 } 3988 3989 rc = 0; 3990 ioc->base_cmds.status = MPT3_CMD_PENDING; 3991 request = mpt3sas_base_get_msg_frame(ioc, smid); 3992 ioc->base_cmds.smid = smid; 3993 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 3994 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 3995 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 3996 ioc->ioc_link_reset_in_progress = 1; 3997 init_completion(&ioc->base_cmds.done); 3998 mpt3sas_base_put_smid_default(ioc, smid); 3999 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 4000 msecs_to_jiffies(10000)); 4001 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 4002 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 4003 ioc->ioc_link_reset_in_progress) 4004 ioc->ioc_link_reset_in_progress = 0; 4005 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4006 pr_err(MPT3SAS_FMT "%s: timeout\n", 4007 ioc->name, __func__); 4008 _debug_dump_mf(mpi_request, 4009 sizeof(Mpi2SasIoUnitControlRequest_t)/4); 4010 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4011 issue_reset = true; 4012 goto issue_host_reset; 4013 } 4014 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4015 memcpy(mpi_reply, ioc->base_cmds.reply, 4016 sizeof(Mpi2SasIoUnitControlReply_t)); 4017 else 4018 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 4019 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4020 goto out; 4021 4022 issue_host_reset: 4023 if (issue_reset) 4024 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 4025 FORCE_BIG_HAMMER); 4026 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4027 rc = -EFAULT; 4028 out: 4029 mutex_unlock(&ioc->base_cmds.mutex); 4030 return rc; 4031 } 4032 4033 /** 4034 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 4035 * @ioc: per adapter object 4036 * @mpi_reply: the reply payload from FW 4037 * @mpi_request: the request payload sent to FW 4038 * 4039 * The SCSI Enclosure Processor request message causes the IOC to 4040 * communicate with SES devices to control LED status signals. 4041 * 4042 * Returns 0 for success, non-zero for failure. 4043 */ 4044 int 4045 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 4046 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 4047 { 4048 u16 smid; 4049 u32 ioc_state; 4050 unsigned long timeleft; 4051 bool issue_reset = false; 4052 int rc; 4053 void *request; 4054 u16 wait_state_count; 4055 4056 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4057 __func__)); 4058 4059 mutex_lock(&ioc->base_cmds.mutex); 4060 4061 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 4062 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 4063 ioc->name, __func__); 4064 rc = -EAGAIN; 4065 goto out; 4066 } 4067 4068 wait_state_count = 0; 4069 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4070 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 4071 if (wait_state_count++ == 10) { 4072 pr_err(MPT3SAS_FMT 4073 "%s: failed due to ioc not operational\n", 4074 ioc->name, __func__); 4075 rc = -EFAULT; 4076 goto out; 4077 } 4078 ssleep(1); 4079 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4080 pr_info(MPT3SAS_FMT 4081 "%s: waiting for operational state(count=%d)\n", 4082 ioc->name, 4083 __func__, wait_state_count); 4084 } 4085 4086 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4087 if (!smid) { 4088 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4089 ioc->name, __func__); 4090 rc = -EAGAIN; 4091 goto out; 4092 } 4093 4094 rc = 0; 4095 ioc->base_cmds.status = MPT3_CMD_PENDING; 4096 request = mpt3sas_base_get_msg_frame(ioc, smid); 4097 ioc->base_cmds.smid = smid; 4098 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 4099 init_completion(&ioc->base_cmds.done); 4100 mpt3sas_base_put_smid_default(ioc, smid); 4101 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 4102 msecs_to_jiffies(10000)); 4103 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4104 pr_err(MPT3SAS_FMT "%s: timeout\n", 4105 ioc->name, __func__); 4106 _debug_dump_mf(mpi_request, 4107 sizeof(Mpi2SepRequest_t)/4); 4108 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4109 issue_reset = false; 4110 goto issue_host_reset; 4111 } 4112 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4113 memcpy(mpi_reply, ioc->base_cmds.reply, 4114 sizeof(Mpi2SepReply_t)); 4115 else 4116 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 4117 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4118 goto out; 4119 4120 issue_host_reset: 4121 if (issue_reset) 4122 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 4123 FORCE_BIG_HAMMER); 4124 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4125 rc = -EFAULT; 4126 out: 4127 mutex_unlock(&ioc->base_cmds.mutex); 4128 return rc; 4129 } 4130 4131 /** 4132 * _base_get_port_facts - obtain port facts reply and save in ioc 4133 * @ioc: per adapter object 4134 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4135 * 4136 * Returns 0 for success, non-zero for failure. 4137 */ 4138 static int 4139 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag) 4140 { 4141 Mpi2PortFactsRequest_t mpi_request; 4142 Mpi2PortFactsReply_t mpi_reply; 4143 struct mpt3sas_port_facts *pfacts; 4144 int mpi_reply_sz, mpi_request_sz, r; 4145 4146 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4147 __func__)); 4148 4149 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 4150 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 4151 memset(&mpi_request, 0, mpi_request_sz); 4152 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 4153 mpi_request.PortNumber = port; 4154 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4155 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); 4156 4157 if (r != 0) { 4158 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4159 ioc->name, __func__, r); 4160 return r; 4161 } 4162 4163 pfacts = &ioc->pfacts[port]; 4164 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 4165 pfacts->PortNumber = mpi_reply.PortNumber; 4166 pfacts->VP_ID = mpi_reply.VP_ID; 4167 pfacts->VF_ID = mpi_reply.VF_ID; 4168 pfacts->MaxPostedCmdBuffers = 4169 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 4170 4171 return 0; 4172 } 4173 4174 /** 4175 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 4176 * @ioc: per adapter object 4177 * @timeout: 4178 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4179 * 4180 * Returns 0 for success, non-zero for failure. 4181 */ 4182 static int 4183 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout, 4184 int sleep_flag) 4185 { 4186 u32 ioc_state; 4187 int rc; 4188 4189 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, 4190 __func__)); 4191 4192 if (ioc->pci_error_recovery) { 4193 dfailprintk(ioc, printk(MPT3SAS_FMT 4194 "%s: host in pci error recovery\n", ioc->name, __func__)); 4195 return -EFAULT; 4196 } 4197 4198 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4199 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 4200 ioc->name, __func__, ioc_state)); 4201 4202 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 4203 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 4204 return 0; 4205 4206 if (ioc_state & MPI2_DOORBELL_USED) { 4207 dhsprintk(ioc, printk(MPT3SAS_FMT 4208 "unexpected doorbell active!\n", ioc->name)); 4209 goto issue_diag_reset; 4210 } 4211 4212 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 4213 mpt3sas_base_fault_info(ioc, ioc_state & 4214 MPI2_DOORBELL_DATA_MASK); 4215 goto issue_diag_reset; 4216 } 4217 4218 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 4219 timeout, sleep_flag); 4220 if (ioc_state) { 4221 dfailprintk(ioc, printk(MPT3SAS_FMT 4222 "%s: failed going to ready state (ioc_state=0x%x)\n", 4223 ioc->name, __func__, ioc_state)); 4224 return -EFAULT; 4225 } 4226 4227 issue_diag_reset: 4228 rc = _base_diag_reset(ioc, sleep_flag); 4229 return rc; 4230 } 4231 4232 /** 4233 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 4234 * @ioc: per adapter object 4235 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4236 * 4237 * Returns 0 for success, non-zero for failure. 4238 */ 4239 static int 4240 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4241 { 4242 Mpi2IOCFactsRequest_t mpi_request; 4243 Mpi2IOCFactsReply_t mpi_reply; 4244 struct mpt3sas_facts *facts; 4245 int mpi_reply_sz, mpi_request_sz, r; 4246 4247 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4248 __func__)); 4249 4250 r = _base_wait_for_iocstate(ioc, 10, sleep_flag); 4251 if (r) { 4252 dfailprintk(ioc, printk(MPT3SAS_FMT 4253 "%s: failed getting to correct state\n", 4254 ioc->name, __func__)); 4255 return r; 4256 } 4257 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 4258 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 4259 memset(&mpi_request, 0, mpi_request_sz); 4260 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 4261 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4262 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); 4263 4264 if (r != 0) { 4265 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4266 ioc->name, __func__, r); 4267 return r; 4268 } 4269 4270 facts = &ioc->facts; 4271 memset(facts, 0, sizeof(struct mpt3sas_facts)); 4272 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 4273 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 4274 facts->VP_ID = mpi_reply.VP_ID; 4275 facts->VF_ID = mpi_reply.VF_ID; 4276 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 4277 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 4278 facts->WhoInit = mpi_reply.WhoInit; 4279 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 4280 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 4281 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 4282 facts->MaxReplyDescriptorPostQueueDepth = 4283 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 4284 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 4285 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 4286 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 4287 ioc->ir_firmware = 1; 4288 if ((facts->IOCCapabilities & 4289 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE)) 4290 ioc->rdpq_array_capable = 1; 4291 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 4292 facts->IOCRequestFrameSize = 4293 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 4294 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 4295 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 4296 ioc->shost->max_id = -1; 4297 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 4298 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 4299 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 4300 facts->HighPriorityCredit = 4301 le16_to_cpu(mpi_reply.HighPriorityCredit); 4302 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 4303 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 4304 4305 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4306 "hba queue depth(%d), max chains per io(%d)\n", 4307 ioc->name, facts->RequestCredit, 4308 facts->MaxChainDepth)); 4309 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4310 "request frame size(%d), reply frame size(%d)\n", ioc->name, 4311 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); 4312 return 0; 4313 } 4314 4315 /** 4316 * _base_send_ioc_init - send ioc_init to firmware 4317 * @ioc: per adapter object 4318 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4319 * 4320 * Returns 0 for success, non-zero for failure. 4321 */ 4322 static int 4323 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4324 { 4325 Mpi2IOCInitRequest_t mpi_request; 4326 Mpi2IOCInitReply_t mpi_reply; 4327 int i, r = 0; 4328 struct timeval current_time; 4329 u16 ioc_status; 4330 u32 reply_post_free_array_sz = 0; 4331 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL; 4332 dma_addr_t reply_post_free_array_dma; 4333 4334 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4335 __func__)); 4336 4337 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 4338 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 4339 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 4340 mpi_request.VF_ID = 0; /* TODO */ 4341 mpi_request.VP_ID = 0; 4342 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 4343 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 4344 4345 if (_base_is_controller_msix_enabled(ioc)) 4346 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 4347 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 4348 mpi_request.ReplyDescriptorPostQueueDepth = 4349 cpu_to_le16(ioc->reply_post_queue_depth); 4350 mpi_request.ReplyFreeQueueDepth = 4351 cpu_to_le16(ioc->reply_free_queue_depth); 4352 4353 mpi_request.SenseBufferAddressHigh = 4354 cpu_to_le32((u64)ioc->sense_dma >> 32); 4355 mpi_request.SystemReplyAddressHigh = 4356 cpu_to_le32((u64)ioc->reply_dma >> 32); 4357 mpi_request.SystemRequestFrameBaseAddress = 4358 cpu_to_le64((u64)ioc->request_dma); 4359 mpi_request.ReplyFreeQueueAddress = 4360 cpu_to_le64((u64)ioc->reply_free_dma); 4361 4362 if (ioc->rdpq_array_enable) { 4363 reply_post_free_array_sz = ioc->reply_queue_count * 4364 sizeof(Mpi2IOCInitRDPQArrayEntry); 4365 reply_post_free_array = pci_alloc_consistent(ioc->pdev, 4366 reply_post_free_array_sz, &reply_post_free_array_dma); 4367 if (!reply_post_free_array) { 4368 pr_err(MPT3SAS_FMT 4369 "reply_post_free_array: pci_alloc_consistent failed\n", 4370 ioc->name); 4371 r = -ENOMEM; 4372 goto out; 4373 } 4374 memset(reply_post_free_array, 0, reply_post_free_array_sz); 4375 for (i = 0; i < ioc->reply_queue_count; i++) 4376 reply_post_free_array[i].RDPQBaseAddress = 4377 cpu_to_le64( 4378 (u64)ioc->reply_post[i].reply_post_free_dma); 4379 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 4380 mpi_request.ReplyDescriptorPostQueueAddress = 4381 cpu_to_le64((u64)reply_post_free_array_dma); 4382 } else { 4383 mpi_request.ReplyDescriptorPostQueueAddress = 4384 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 4385 } 4386 4387 /* This time stamp specifies number of milliseconds 4388 * since epoch ~ midnight January 1, 1970. 4389 */ 4390 do_gettimeofday(¤t_time); 4391 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 + 4392 (current_time.tv_usec / 1000)); 4393 4394 if (ioc->logging_level & MPT_DEBUG_INIT) { 4395 __le32 *mfp; 4396 int i; 4397 4398 mfp = (__le32 *)&mpi_request; 4399 pr_info("\toffset:data\n"); 4400 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 4401 pr_info("\t[0x%02x]:%08x\n", i*4, 4402 le32_to_cpu(mfp[i])); 4403 } 4404 4405 r = _base_handshake_req_reply_wait(ioc, 4406 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 4407 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10, 4408 sleep_flag); 4409 4410 if (r != 0) { 4411 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4412 ioc->name, __func__, r); 4413 goto out; 4414 } 4415 4416 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 4417 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 4418 mpi_reply.IOCLogInfo) { 4419 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); 4420 r = -EIO; 4421 } 4422 4423 out: 4424 if (reply_post_free_array) 4425 pci_free_consistent(ioc->pdev, reply_post_free_array_sz, 4426 reply_post_free_array, 4427 reply_post_free_array_dma); 4428 return r; 4429 } 4430 4431 /** 4432 * mpt3sas_port_enable_done - command completion routine for port enable 4433 * @ioc: per adapter object 4434 * @smid: system request message index 4435 * @msix_index: MSIX table index supplied by the OS 4436 * @reply: reply message frame(lower 32bit addr) 4437 * 4438 * Return 1 meaning mf should be freed from _base_interrupt 4439 * 0 means the mf is freed from this function. 4440 */ 4441 u8 4442 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 4443 u32 reply) 4444 { 4445 MPI2DefaultReply_t *mpi_reply; 4446 u16 ioc_status; 4447 4448 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 4449 return 1; 4450 4451 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 4452 if (!mpi_reply) 4453 return 1; 4454 4455 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 4456 return 1; 4457 4458 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 4459 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 4460 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 4461 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 4462 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4463 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 4464 ioc->port_enable_failed = 1; 4465 4466 if (ioc->is_driver_loading) { 4467 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 4468 mpt3sas_port_enable_complete(ioc); 4469 return 1; 4470 } else { 4471 ioc->start_scan_failed = ioc_status; 4472 ioc->start_scan = 0; 4473 return 1; 4474 } 4475 } 4476 complete(&ioc->port_enable_cmds.done); 4477 return 1; 4478 } 4479 4480 /** 4481 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 4482 * @ioc: per adapter object 4483 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4484 * 4485 * Returns 0 for success, non-zero for failure. 4486 */ 4487 static int 4488 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4489 { 4490 Mpi2PortEnableRequest_t *mpi_request; 4491 Mpi2PortEnableReply_t *mpi_reply; 4492 unsigned long timeleft; 4493 int r = 0; 4494 u16 smid; 4495 u16 ioc_status; 4496 4497 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4498 4499 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4500 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4501 ioc->name, __func__); 4502 return -EAGAIN; 4503 } 4504 4505 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4506 if (!smid) { 4507 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4508 ioc->name, __func__); 4509 return -EAGAIN; 4510 } 4511 4512 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4513 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4514 ioc->port_enable_cmds.smid = smid; 4515 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4516 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4517 4518 init_completion(&ioc->port_enable_cmds.done); 4519 mpt3sas_base_put_smid_default(ioc, smid); 4520 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done, 4521 300*HZ); 4522 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 4523 pr_err(MPT3SAS_FMT "%s: timeout\n", 4524 ioc->name, __func__); 4525 _debug_dump_mf(mpi_request, 4526 sizeof(Mpi2PortEnableRequest_t)/4); 4527 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 4528 r = -EFAULT; 4529 else 4530 r = -ETIME; 4531 goto out; 4532 } 4533 4534 mpi_reply = ioc->port_enable_cmds.reply; 4535 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4536 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4537 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", 4538 ioc->name, __func__, ioc_status); 4539 r = -EFAULT; 4540 goto out; 4541 } 4542 4543 out: 4544 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 4545 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? 4546 "SUCCESS" : "FAILED")); 4547 return r; 4548 } 4549 4550 /** 4551 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 4552 * @ioc: per adapter object 4553 * 4554 * Returns 0 for success, non-zero for failure. 4555 */ 4556 int 4557 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 4558 { 4559 Mpi2PortEnableRequest_t *mpi_request; 4560 u16 smid; 4561 4562 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4563 4564 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4565 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4566 ioc->name, __func__); 4567 return -EAGAIN; 4568 } 4569 4570 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4571 if (!smid) { 4572 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4573 ioc->name, __func__); 4574 return -EAGAIN; 4575 } 4576 4577 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4578 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4579 ioc->port_enable_cmds.smid = smid; 4580 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4581 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4582 4583 mpt3sas_base_put_smid_default(ioc, smid); 4584 return 0; 4585 } 4586 4587 /** 4588 * _base_determine_wait_on_discovery - desposition 4589 * @ioc: per adapter object 4590 * 4591 * Decide whether to wait on discovery to complete. Used to either 4592 * locate boot device, or report volumes ahead of physical devices. 4593 * 4594 * Returns 1 for wait, 0 for don't wait 4595 */ 4596 static int 4597 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 4598 { 4599 /* We wait for discovery to complete if IR firmware is loaded. 4600 * The sas topology events arrive before PD events, so we need time to 4601 * turn on the bit in ioc->pd_handles to indicate PD 4602 * Also, it maybe required to report Volumes ahead of physical 4603 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 4604 */ 4605 if (ioc->ir_firmware) 4606 return 1; 4607 4608 /* if no Bios, then we don't need to wait */ 4609 if (!ioc->bios_pg3.BiosVersion) 4610 return 0; 4611 4612 /* Bios is present, then we drop down here. 4613 * 4614 * If there any entries in the Bios Page 2, then we wait 4615 * for discovery to complete. 4616 */ 4617 4618 /* Current Boot Device */ 4619 if ((ioc->bios_pg2.CurrentBootDeviceForm & 4620 MPI2_BIOSPAGE2_FORM_MASK) == 4621 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4622 /* Request Boot Device */ 4623 (ioc->bios_pg2.ReqBootDeviceForm & 4624 MPI2_BIOSPAGE2_FORM_MASK) == 4625 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4626 /* Alternate Request Boot Device */ 4627 (ioc->bios_pg2.ReqAltBootDeviceForm & 4628 MPI2_BIOSPAGE2_FORM_MASK) == 4629 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 4630 return 0; 4631 4632 return 1; 4633 } 4634 4635 /** 4636 * _base_unmask_events - turn on notification for this event 4637 * @ioc: per adapter object 4638 * @event: firmware event 4639 * 4640 * The mask is stored in ioc->event_masks. 4641 */ 4642 static void 4643 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 4644 { 4645 u32 desired_event; 4646 4647 if (event >= 128) 4648 return; 4649 4650 desired_event = (1 << (event % 32)); 4651 4652 if (event < 32) 4653 ioc->event_masks[0] &= ~desired_event; 4654 else if (event < 64) 4655 ioc->event_masks[1] &= ~desired_event; 4656 else if (event < 96) 4657 ioc->event_masks[2] &= ~desired_event; 4658 else if (event < 128) 4659 ioc->event_masks[3] &= ~desired_event; 4660 } 4661 4662 /** 4663 * _base_event_notification - send event notification 4664 * @ioc: per adapter object 4665 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4666 * 4667 * Returns 0 for success, non-zero for failure. 4668 */ 4669 static int 4670 _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4671 { 4672 Mpi2EventNotificationRequest_t *mpi_request; 4673 unsigned long timeleft; 4674 u16 smid; 4675 int r = 0; 4676 int i; 4677 4678 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4679 __func__)); 4680 4681 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4682 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4683 ioc->name, __func__); 4684 return -EAGAIN; 4685 } 4686 4687 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4688 if (!smid) { 4689 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4690 ioc->name, __func__); 4691 return -EAGAIN; 4692 } 4693 ioc->base_cmds.status = MPT3_CMD_PENDING; 4694 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4695 ioc->base_cmds.smid = smid; 4696 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 4697 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 4698 mpi_request->VF_ID = 0; /* TODO */ 4699 mpi_request->VP_ID = 0; 4700 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4701 mpi_request->EventMasks[i] = 4702 cpu_to_le32(ioc->event_masks[i]); 4703 init_completion(&ioc->base_cmds.done); 4704 mpt3sas_base_put_smid_default(ioc, smid); 4705 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 4706 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4707 pr_err(MPT3SAS_FMT "%s: timeout\n", 4708 ioc->name, __func__); 4709 _debug_dump_mf(mpi_request, 4710 sizeof(Mpi2EventNotificationRequest_t)/4); 4711 if (ioc->base_cmds.status & MPT3_CMD_RESET) 4712 r = -EFAULT; 4713 else 4714 r = -ETIME; 4715 } else 4716 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", 4717 ioc->name, __func__)); 4718 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4719 return r; 4720 } 4721 4722 /** 4723 * mpt3sas_base_validate_event_type - validating event types 4724 * @ioc: per adapter object 4725 * @event: firmware event 4726 * 4727 * This will turn on firmware event notification when application 4728 * ask for that event. We don't mask events that are already enabled. 4729 */ 4730 void 4731 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 4732 { 4733 int i, j; 4734 u32 event_mask, desired_event; 4735 u8 send_update_to_fw; 4736 4737 for (i = 0, send_update_to_fw = 0; i < 4738 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 4739 event_mask = ~event_type[i]; 4740 desired_event = 1; 4741 for (j = 0; j < 32; j++) { 4742 if (!(event_mask & desired_event) && 4743 (ioc->event_masks[i] & desired_event)) { 4744 ioc->event_masks[i] &= ~desired_event; 4745 send_update_to_fw = 1; 4746 } 4747 desired_event = (desired_event << 1); 4748 } 4749 } 4750 4751 if (!send_update_to_fw) 4752 return; 4753 4754 mutex_lock(&ioc->base_cmds.mutex); 4755 _base_event_notification(ioc, CAN_SLEEP); 4756 mutex_unlock(&ioc->base_cmds.mutex); 4757 } 4758 4759 /** 4760 * _base_diag_reset - the "big hammer" start of day reset 4761 * @ioc: per adapter object 4762 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4763 * 4764 * Returns 0 for success, non-zero for failure. 4765 */ 4766 static int 4767 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4768 { 4769 u32 host_diagnostic; 4770 u32 ioc_state; 4771 u32 count; 4772 u32 hcb_size; 4773 4774 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); 4775 4776 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", 4777 ioc->name)); 4778 4779 count = 0; 4780 do { 4781 /* Write magic sequence to WriteSequence register 4782 * Loop until in diagnostic mode 4783 */ 4784 drsprintk(ioc, pr_info(MPT3SAS_FMT 4785 "write magic sequence\n", ioc->name)); 4786 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4787 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 4788 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 4789 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 4790 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 4791 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 4792 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 4793 4794 /* wait 100 msec */ 4795 if (sleep_flag == CAN_SLEEP) 4796 msleep(100); 4797 else 4798 mdelay(100); 4799 4800 if (count++ > 20) 4801 goto out; 4802 4803 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4804 drsprintk(ioc, pr_info(MPT3SAS_FMT 4805 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 4806 ioc->name, count, host_diagnostic)); 4807 4808 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 4809 4810 hcb_size = readl(&ioc->chip->HCBSize); 4811 4812 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", 4813 ioc->name)); 4814 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 4815 &ioc->chip->HostDiagnostic); 4816 4817 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 4818 if (sleep_flag == CAN_SLEEP) 4819 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4820 else 4821 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4822 4823 /* Approximately 300 second max wait */ 4824 for (count = 0; count < (300000000 / 4825 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 4826 4827 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4828 4829 if (host_diagnostic == 0xFFFFFFFF) 4830 goto out; 4831 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 4832 break; 4833 4834 /* Wait to pass the second read delay window */ 4835 if (sleep_flag == CAN_SLEEP) 4836 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC 4837 / 1000); 4838 else 4839 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC 4840 / 1000); 4841 } 4842 4843 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 4844 4845 drsprintk(ioc, pr_info(MPT3SAS_FMT 4846 "restart the adapter assuming the HCB Address points to good F/W\n", 4847 ioc->name)); 4848 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 4849 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 4850 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 4851 4852 drsprintk(ioc, pr_info(MPT3SAS_FMT 4853 "re-enable the HCDW\n", ioc->name)); 4854 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 4855 &ioc->chip->HCBSize); 4856 } 4857 4858 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", 4859 ioc->name)); 4860 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 4861 &ioc->chip->HostDiagnostic); 4862 4863 drsprintk(ioc, pr_info(MPT3SAS_FMT 4864 "disable writes to the diagnostic register\n", ioc->name)); 4865 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4866 4867 drsprintk(ioc, pr_info(MPT3SAS_FMT 4868 "Wait for FW to go to the READY state\n", ioc->name)); 4869 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20, 4870 sleep_flag); 4871 if (ioc_state) { 4872 pr_err(MPT3SAS_FMT 4873 "%s: failed going to ready state (ioc_state=0x%x)\n", 4874 ioc->name, __func__, ioc_state); 4875 goto out; 4876 } 4877 4878 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); 4879 return 0; 4880 4881 out: 4882 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); 4883 return -EFAULT; 4884 } 4885 4886 /** 4887 * _base_make_ioc_ready - put controller in READY state 4888 * @ioc: per adapter object 4889 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4890 * @type: FORCE_BIG_HAMMER or SOFT_RESET 4891 * 4892 * Returns 0 for success, non-zero for failure. 4893 */ 4894 static int 4895 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag, 4896 enum reset_type type) 4897 { 4898 u32 ioc_state; 4899 int rc; 4900 int count; 4901 4902 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4903 __func__)); 4904 4905 if (ioc->pci_error_recovery) 4906 return 0; 4907 4908 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4909 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 4910 ioc->name, __func__, ioc_state)); 4911 4912 /* if in RESET state, it should move to READY state shortly */ 4913 count = 0; 4914 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 4915 while ((ioc_state & MPI2_IOC_STATE_MASK) != 4916 MPI2_IOC_STATE_READY) { 4917 if (count++ == 10) { 4918 pr_err(MPT3SAS_FMT 4919 "%s: failed going to ready state (ioc_state=0x%x)\n", 4920 ioc->name, __func__, ioc_state); 4921 return -EFAULT; 4922 } 4923 if (sleep_flag == CAN_SLEEP) 4924 ssleep(1); 4925 else 4926 mdelay(1000); 4927 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4928 } 4929 } 4930 4931 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 4932 return 0; 4933 4934 if (ioc_state & MPI2_DOORBELL_USED) { 4935 dhsprintk(ioc, pr_info(MPT3SAS_FMT 4936 "unexpected doorbell active!\n", 4937 ioc->name)); 4938 goto issue_diag_reset; 4939 } 4940 4941 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 4942 mpt3sas_base_fault_info(ioc, ioc_state & 4943 MPI2_DOORBELL_DATA_MASK); 4944 goto issue_diag_reset; 4945 } 4946 4947 if (type == FORCE_BIG_HAMMER) 4948 goto issue_diag_reset; 4949 4950 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 4951 if (!(_base_send_ioc_reset(ioc, 4952 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) { 4953 return 0; 4954 } 4955 4956 issue_diag_reset: 4957 rc = _base_diag_reset(ioc, CAN_SLEEP); 4958 return rc; 4959 } 4960 4961 /** 4962 * _base_make_ioc_operational - put controller in OPERATIONAL state 4963 * @ioc: per adapter object 4964 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4965 * 4966 * Returns 0 for success, non-zero for failure. 4967 */ 4968 static int 4969 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4970 { 4971 int r, i; 4972 unsigned long flags; 4973 u32 reply_address; 4974 u16 smid; 4975 struct _tr_list *delayed_tr, *delayed_tr_next; 4976 u8 hide_flag; 4977 struct adapter_reply_queue *reply_q; 4978 long reply_post_free; 4979 u32 reply_post_free_sz, index = 0; 4980 4981 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4982 __func__)); 4983 4984 /* clean the delayed target reset list */ 4985 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 4986 &ioc->delayed_tr_list, list) { 4987 list_del(&delayed_tr->list); 4988 kfree(delayed_tr); 4989 } 4990 4991 4992 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 4993 &ioc->delayed_tr_volume_list, list) { 4994 list_del(&delayed_tr->list); 4995 kfree(delayed_tr); 4996 } 4997 4998 /* initialize the scsi lookup free list */ 4999 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5000 INIT_LIST_HEAD(&ioc->free_list); 5001 smid = 1; 5002 for (i = 0; i < ioc->scsiio_depth; i++, smid++) { 5003 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); 5004 ioc->scsi_lookup[i].cb_idx = 0xFF; 5005 ioc->scsi_lookup[i].smid = smid; 5006 ioc->scsi_lookup[i].scmd = NULL; 5007 ioc->scsi_lookup[i].direct_io = 0; 5008 list_add_tail(&ioc->scsi_lookup[i].tracker_list, 5009 &ioc->free_list); 5010 } 5011 5012 /* hi-priority queue */ 5013 INIT_LIST_HEAD(&ioc->hpr_free_list); 5014 smid = ioc->hi_priority_smid; 5015 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 5016 ioc->hpr_lookup[i].cb_idx = 0xFF; 5017 ioc->hpr_lookup[i].smid = smid; 5018 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 5019 &ioc->hpr_free_list); 5020 } 5021 5022 /* internal queue */ 5023 INIT_LIST_HEAD(&ioc->internal_free_list); 5024 smid = ioc->internal_smid; 5025 for (i = 0; i < ioc->internal_depth; i++, smid++) { 5026 ioc->internal_lookup[i].cb_idx = 0xFF; 5027 ioc->internal_lookup[i].smid = smid; 5028 list_add_tail(&ioc->internal_lookup[i].tracker_list, 5029 &ioc->internal_free_list); 5030 } 5031 5032 /* chain pool */ 5033 INIT_LIST_HEAD(&ioc->free_chain_list); 5034 for (i = 0; i < ioc->chain_depth; i++) 5035 list_add_tail(&ioc->chain_lookup[i].tracker_list, 5036 &ioc->free_chain_list); 5037 5038 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5039 5040 /* initialize Reply Free Queue */ 5041 for (i = 0, reply_address = (u32)ioc->reply_dma ; 5042 i < ioc->reply_free_queue_depth ; i++, reply_address += 5043 ioc->reply_sz) 5044 ioc->reply_free[i] = cpu_to_le32(reply_address); 5045 5046 /* initialize reply queues */ 5047 if (ioc->is_driver_loading) 5048 _base_assign_reply_queues(ioc); 5049 5050 /* initialize Reply Post Free Queue */ 5051 reply_post_free_sz = ioc->reply_post_queue_depth * 5052 sizeof(Mpi2DefaultReplyDescriptor_t); 5053 reply_post_free = (long)ioc->reply_post[index].reply_post_free; 5054 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5055 reply_q->reply_post_host_index = 0; 5056 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *) 5057 reply_post_free; 5058 for (i = 0; i < ioc->reply_post_queue_depth; i++) 5059 reply_q->reply_post_free[i].Words = 5060 cpu_to_le64(ULLONG_MAX); 5061 if (!_base_is_controller_msix_enabled(ioc)) 5062 goto skip_init_reply_post_free_queue; 5063 /* 5064 * If RDPQ is enabled, switch to the next allocation. 5065 * Otherwise advance within the contiguous region. 5066 */ 5067 if (ioc->rdpq_array_enable) 5068 reply_post_free = (long) 5069 ioc->reply_post[++index].reply_post_free; 5070 else 5071 reply_post_free += reply_post_free_sz; 5072 } 5073 skip_init_reply_post_free_queue: 5074 5075 r = _base_send_ioc_init(ioc, sleep_flag); 5076 if (r) 5077 return r; 5078 5079 /* initialize reply free host index */ 5080 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 5081 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 5082 5083 /* initialize reply post host index */ 5084 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5085 if (ioc->msix96_vector) 5086 writel((reply_q->msix_index & 7)<< 5087 MPI2_RPHI_MSIX_INDEX_SHIFT, 5088 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 5089 else 5090 writel(reply_q->msix_index << 5091 MPI2_RPHI_MSIX_INDEX_SHIFT, 5092 &ioc->chip->ReplyPostHostIndex); 5093 5094 if (!_base_is_controller_msix_enabled(ioc)) 5095 goto skip_init_reply_post_host_index; 5096 } 5097 5098 skip_init_reply_post_host_index: 5099 5100 _base_unmask_interrupts(ioc); 5101 r = _base_event_notification(ioc, sleep_flag); 5102 if (r) 5103 return r; 5104 5105 if (sleep_flag == CAN_SLEEP) 5106 _base_static_config_pages(ioc); 5107 5108 5109 if (ioc->is_driver_loading) { 5110 5111 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 5112 == 0x80) { 5113 hide_flag = (u8) ( 5114 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 5115 MFG_PAGE10_HIDE_SSDS_MASK); 5116 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 5117 ioc->mfg_pg10_hide_flag = hide_flag; 5118 } 5119 5120 ioc->wait_for_discovery_to_complete = 5121 _base_determine_wait_on_discovery(ioc); 5122 5123 return r; /* scan_start and scan_finished support */ 5124 } 5125 5126 r = _base_send_port_enable(ioc, sleep_flag); 5127 if (r) 5128 return r; 5129 5130 return r; 5131 } 5132 5133 /** 5134 * mpt3sas_base_free_resources - free resources controller resources 5135 * @ioc: per adapter object 5136 * 5137 * Return nothing. 5138 */ 5139 void 5140 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 5141 { 5142 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5143 __func__)); 5144 5145 /* synchronizing freeing resource with pci_access_mutex lock */ 5146 mutex_lock(&ioc->pci_access_mutex); 5147 if (ioc->chip_phys && ioc->chip) { 5148 _base_mask_interrupts(ioc); 5149 ioc->shost_recovery = 1; 5150 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); 5151 ioc->shost_recovery = 0; 5152 } 5153 5154 mpt3sas_base_unmap_resources(ioc); 5155 mutex_unlock(&ioc->pci_access_mutex); 5156 return; 5157 } 5158 5159 /** 5160 * mpt3sas_base_attach - attach controller instance 5161 * @ioc: per adapter object 5162 * 5163 * Returns 0 for success, non-zero for failure. 5164 */ 5165 int 5166 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 5167 { 5168 int r, i; 5169 int cpu_id, last_cpu_id = 0; 5170 5171 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5172 __func__)); 5173 5174 /* setup cpu_msix_table */ 5175 ioc->cpu_count = num_online_cpus(); 5176 for_each_online_cpu(cpu_id) 5177 last_cpu_id = cpu_id; 5178 ioc->cpu_msix_table_sz = last_cpu_id + 1; 5179 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 5180 ioc->reply_queue_count = 1; 5181 if (!ioc->cpu_msix_table) { 5182 dfailprintk(ioc, pr_info(MPT3SAS_FMT 5183 "allocation for cpu_msix_table failed!!!\n", 5184 ioc->name)); 5185 r = -ENOMEM; 5186 goto out_free_resources; 5187 } 5188 5189 if (ioc->is_warpdrive) { 5190 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 5191 sizeof(resource_size_t *), GFP_KERNEL); 5192 if (!ioc->reply_post_host_index) { 5193 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " 5194 "for cpu_msix_table failed!!!\n", ioc->name)); 5195 r = -ENOMEM; 5196 goto out_free_resources; 5197 } 5198 } 5199 5200 ioc->rdpq_array_enable_assigned = 0; 5201 ioc->dma_mask = 0; 5202 r = mpt3sas_base_map_resources(ioc); 5203 if (r) 5204 goto out_free_resources; 5205 5206 if (ioc->is_warpdrive) { 5207 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 5208 &ioc->chip->ReplyPostHostIndex; 5209 5210 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 5211 ioc->reply_post_host_index[i] = 5212 (resource_size_t __iomem *) 5213 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 5214 * 4))); 5215 } 5216 5217 pci_set_drvdata(ioc->pdev, ioc->shost); 5218 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 5219 if (r) 5220 goto out_free_resources; 5221 5222 switch (ioc->hba_mpi_version_belonged) { 5223 case MPI2_VERSION: 5224 ioc->build_sg_scmd = &_base_build_sg_scmd; 5225 ioc->build_sg = &_base_build_sg; 5226 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 5227 break; 5228 case MPI25_VERSION: 5229 /* 5230 * In SAS3.0, 5231 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 5232 * Target Status - all require the IEEE formated scatter gather 5233 * elements. 5234 */ 5235 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 5236 ioc->build_sg = &_base_build_sg_ieee; 5237 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 5238 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 5239 break; 5240 } 5241 5242 /* 5243 * These function pointers for other requests that don't 5244 * the require IEEE scatter gather elements. 5245 * 5246 * For example Configuration Pages and SAS IOUNIT Control don't. 5247 */ 5248 ioc->build_sg_mpi = &_base_build_sg; 5249 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 5250 5251 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); 5252 if (r) 5253 goto out_free_resources; 5254 5255 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 5256 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 5257 if (!ioc->pfacts) { 5258 r = -ENOMEM; 5259 goto out_free_resources; 5260 } 5261 5262 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 5263 r = _base_get_port_facts(ioc, i, CAN_SLEEP); 5264 if (r) 5265 goto out_free_resources; 5266 } 5267 5268 r = _base_allocate_memory_pools(ioc, CAN_SLEEP); 5269 if (r) 5270 goto out_free_resources; 5271 5272 init_waitqueue_head(&ioc->reset_wq); 5273 5274 /* allocate memory pd handle bitmask list */ 5275 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 5276 if (ioc->facts.MaxDevHandle % 8) 5277 ioc->pd_handles_sz++; 5278 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 5279 GFP_KERNEL); 5280 if (!ioc->pd_handles) { 5281 r = -ENOMEM; 5282 goto out_free_resources; 5283 } 5284 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 5285 GFP_KERNEL); 5286 if (!ioc->blocking_handles) { 5287 r = -ENOMEM; 5288 goto out_free_resources; 5289 } 5290 5291 ioc->fwfault_debug = mpt3sas_fwfault_debug; 5292 5293 /* base internal command bits */ 5294 mutex_init(&ioc->base_cmds.mutex); 5295 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5296 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5297 5298 /* port_enable command bits */ 5299 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5300 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 5301 5302 /* transport internal command bits */ 5303 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5304 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 5305 mutex_init(&ioc->transport_cmds.mutex); 5306 5307 /* scsih internal command bits */ 5308 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5309 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 5310 mutex_init(&ioc->scsih_cmds.mutex); 5311 5312 /* task management internal command bits */ 5313 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5314 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 5315 mutex_init(&ioc->tm_cmds.mutex); 5316 5317 /* config page internal command bits */ 5318 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5319 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 5320 mutex_init(&ioc->config_cmds.mutex); 5321 5322 /* ctl module internal command bits */ 5323 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5324 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 5325 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 5326 mutex_init(&ioc->ctl_cmds.mutex); 5327 5328 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply || 5329 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply || 5330 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply || 5331 !ioc->ctl_cmds.sense) { 5332 r = -ENOMEM; 5333 goto out_free_resources; 5334 } 5335 5336 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5337 ioc->event_masks[i] = -1; 5338 5339 /* here we enable the events we care about */ 5340 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 5341 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 5342 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 5343 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 5344 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 5345 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 5346 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 5347 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 5348 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 5349 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 5350 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 5351 5352 r = _base_make_ioc_operational(ioc, CAN_SLEEP); 5353 if (r) 5354 goto out_free_resources; 5355 5356 ioc->non_operational_loop = 0; 5357 return 0; 5358 5359 out_free_resources: 5360 5361 ioc->remove_host = 1; 5362 5363 mpt3sas_base_free_resources(ioc); 5364 _base_release_memory_pools(ioc); 5365 pci_set_drvdata(ioc->pdev, NULL); 5366 kfree(ioc->cpu_msix_table); 5367 if (ioc->is_warpdrive) 5368 kfree(ioc->reply_post_host_index); 5369 kfree(ioc->pd_handles); 5370 kfree(ioc->blocking_handles); 5371 kfree(ioc->tm_cmds.reply); 5372 kfree(ioc->transport_cmds.reply); 5373 kfree(ioc->scsih_cmds.reply); 5374 kfree(ioc->config_cmds.reply); 5375 kfree(ioc->base_cmds.reply); 5376 kfree(ioc->port_enable_cmds.reply); 5377 kfree(ioc->ctl_cmds.reply); 5378 kfree(ioc->ctl_cmds.sense); 5379 kfree(ioc->pfacts); 5380 ioc->ctl_cmds.reply = NULL; 5381 ioc->base_cmds.reply = NULL; 5382 ioc->tm_cmds.reply = NULL; 5383 ioc->scsih_cmds.reply = NULL; 5384 ioc->transport_cmds.reply = NULL; 5385 ioc->config_cmds.reply = NULL; 5386 ioc->pfacts = NULL; 5387 return r; 5388 } 5389 5390 5391 /** 5392 * mpt3sas_base_detach - remove controller instance 5393 * @ioc: per adapter object 5394 * 5395 * Return nothing. 5396 */ 5397 void 5398 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 5399 { 5400 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5401 __func__)); 5402 5403 mpt3sas_base_stop_watchdog(ioc); 5404 mpt3sas_base_free_resources(ioc); 5405 _base_release_memory_pools(ioc); 5406 pci_set_drvdata(ioc->pdev, NULL); 5407 kfree(ioc->cpu_msix_table); 5408 if (ioc->is_warpdrive) 5409 kfree(ioc->reply_post_host_index); 5410 kfree(ioc->pd_handles); 5411 kfree(ioc->blocking_handles); 5412 kfree(ioc->pfacts); 5413 kfree(ioc->ctl_cmds.reply); 5414 kfree(ioc->ctl_cmds.sense); 5415 kfree(ioc->base_cmds.reply); 5416 kfree(ioc->port_enable_cmds.reply); 5417 kfree(ioc->tm_cmds.reply); 5418 kfree(ioc->transport_cmds.reply); 5419 kfree(ioc->scsih_cmds.reply); 5420 kfree(ioc->config_cmds.reply); 5421 } 5422 5423 /** 5424 * _base_reset_handler - reset callback handler (for base) 5425 * @ioc: per adapter object 5426 * @reset_phase: phase 5427 * 5428 * The handler for doing any required cleanup or initialization. 5429 * 5430 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET, 5431 * MPT3_IOC_DONE_RESET 5432 * 5433 * Return nothing. 5434 */ 5435 static void 5436 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase) 5437 { 5438 mpt3sas_scsih_reset_handler(ioc, reset_phase); 5439 mpt3sas_ctl_reset_handler(ioc, reset_phase); 5440 switch (reset_phase) { 5441 case MPT3_IOC_PRE_RESET: 5442 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5443 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); 5444 break; 5445 case MPT3_IOC_AFTER_RESET: 5446 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5447 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); 5448 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 5449 ioc->transport_cmds.status |= MPT3_CMD_RESET; 5450 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 5451 complete(&ioc->transport_cmds.done); 5452 } 5453 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 5454 ioc->base_cmds.status |= MPT3_CMD_RESET; 5455 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 5456 complete(&ioc->base_cmds.done); 5457 } 5458 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 5459 ioc->port_enable_failed = 1; 5460 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 5461 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 5462 if (ioc->is_driver_loading) { 5463 ioc->start_scan_failed = 5464 MPI2_IOCSTATUS_INTERNAL_ERROR; 5465 ioc->start_scan = 0; 5466 ioc->port_enable_cmds.status = 5467 MPT3_CMD_NOT_USED; 5468 } else 5469 complete(&ioc->port_enable_cmds.done); 5470 } 5471 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 5472 ioc->config_cmds.status |= MPT3_CMD_RESET; 5473 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 5474 ioc->config_cmds.smid = USHRT_MAX; 5475 complete(&ioc->config_cmds.done); 5476 } 5477 break; 5478 case MPT3_IOC_DONE_RESET: 5479 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5480 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); 5481 break; 5482 } 5483 } 5484 5485 /** 5486 * _wait_for_commands_to_complete - reset controller 5487 * @ioc: Pointer to MPT_ADAPTER structure 5488 * @sleep_flag: CAN_SLEEP or NO_SLEEP 5489 * 5490 * This function waiting(3s) for all pending commands to complete 5491 * prior to putting controller in reset. 5492 */ 5493 static void 5494 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 5495 { 5496 u32 ioc_state; 5497 unsigned long flags; 5498 u16 i; 5499 5500 ioc->pending_io_count = 0; 5501 if (sleep_flag != CAN_SLEEP) 5502 return; 5503 5504 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5505 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 5506 return; 5507 5508 /* pending command count */ 5509 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5510 for (i = 0; i < ioc->scsiio_depth; i++) 5511 if (ioc->scsi_lookup[i].cb_idx != 0xFF) 5512 ioc->pending_io_count++; 5513 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5514 5515 if (!ioc->pending_io_count) 5516 return; 5517 5518 /* wait for pending commands to complete */ 5519 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 5520 } 5521 5522 /** 5523 * mpt3sas_base_hard_reset_handler - reset controller 5524 * @ioc: Pointer to MPT_ADAPTER structure 5525 * @sleep_flag: CAN_SLEEP or NO_SLEEP 5526 * @type: FORCE_BIG_HAMMER or SOFT_RESET 5527 * 5528 * Returns 0 for success, non-zero for failure. 5529 */ 5530 int 5531 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag, 5532 enum reset_type type) 5533 { 5534 int r; 5535 unsigned long flags; 5536 u32 ioc_state; 5537 u8 is_fault = 0, is_trigger = 0; 5538 5539 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, 5540 __func__)); 5541 5542 if (ioc->pci_error_recovery) { 5543 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", 5544 ioc->name, __func__); 5545 r = 0; 5546 goto out_unlocked; 5547 } 5548 5549 if (mpt3sas_fwfault_debug) 5550 mpt3sas_halt_firmware(ioc); 5551 5552 /* TODO - What we really should be doing is pulling 5553 * out all the code associated with NO_SLEEP; its never used. 5554 * That is legacy code from mpt fusion driver, ported over. 5555 * I will leave this BUG_ON here for now till its been resolved. 5556 */ 5557 BUG_ON(sleep_flag == NO_SLEEP); 5558 5559 /* wait for an active reset in progress to complete */ 5560 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) { 5561 do { 5562 ssleep(1); 5563 } while (ioc->shost_recovery == 1); 5564 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5565 __func__)); 5566 return ioc->ioc_reset_in_progress_status; 5567 } 5568 5569 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5570 ioc->shost_recovery = 1; 5571 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5572 5573 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5574 MPT3_DIAG_BUFFER_IS_REGISTERED) && 5575 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5576 MPT3_DIAG_BUFFER_IS_RELEASED))) { 5577 is_trigger = 1; 5578 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5579 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 5580 is_fault = 1; 5581 } 5582 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET); 5583 _wait_for_commands_to_complete(ioc, sleep_flag); 5584 _base_mask_interrupts(ioc); 5585 r = _base_make_ioc_ready(ioc, sleep_flag, type); 5586 if (r) 5587 goto out; 5588 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET); 5589 5590 /* If this hard reset is called while port enable is active, then 5591 * there is no reason to call make_ioc_operational 5592 */ 5593 if (ioc->is_driver_loading && ioc->port_enable_failed) { 5594 ioc->remove_host = 1; 5595 r = -EFAULT; 5596 goto out; 5597 } 5598 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 5599 if (r) 5600 goto out; 5601 5602 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 5603 panic("%s: Issue occurred with flashing controller firmware." 5604 "Please reboot the system and ensure that the correct" 5605 " firmware version is running\n", ioc->name); 5606 5607 r = _base_make_ioc_operational(ioc, sleep_flag); 5608 if (!r) 5609 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET); 5610 5611 out: 5612 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", 5613 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); 5614 5615 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5616 ioc->ioc_reset_in_progress_status = r; 5617 ioc->shost_recovery = 0; 5618 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5619 ioc->ioc_reset_count++; 5620 mutex_unlock(&ioc->reset_in_progress_mutex); 5621 5622 out_unlocked: 5623 if ((r == 0) && is_trigger) { 5624 if (is_fault) 5625 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 5626 else 5627 mpt3sas_trigger_master(ioc, 5628 MASTER_TRIGGER_ADAPTER_RESET); 5629 } 5630 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5631 __func__)); 5632 return r; 5633 } 5634