1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/ktime.h> 61 #include <linux/kthread.h> 62 #include <asm/page.h> /* To get host page size per arch */ 63 64 65 #include "mpt3sas_base.h" 66 67 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 68 69 70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 71 72 /* maximum controller queue depth */ 73 #define MAX_HBA_QUEUE_DEPTH 30000 74 #define MAX_CHAIN_DEPTH 100000 75 static int max_queue_depth = -1; 76 module_param(max_queue_depth, int, 0444); 77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 78 79 static int max_sgl_entries = -1; 80 module_param(max_sgl_entries, int, 0444); 81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 82 83 static int msix_disable = -1; 84 module_param(msix_disable, int, 0444); 85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 86 87 static int smp_affinity_enable = 1; 88 module_param(smp_affinity_enable, int, 0444); 89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)"); 90 91 static int max_msix_vectors = -1; 92 module_param(max_msix_vectors, int, 0444); 93 MODULE_PARM_DESC(max_msix_vectors, 94 " max msix vectors"); 95 96 static int irqpoll_weight = -1; 97 module_param(irqpoll_weight, int, 0444); 98 MODULE_PARM_DESC(irqpoll_weight, 99 "irq poll weight (default= one fourth of HBA queue depth)"); 100 101 static int mpt3sas_fwfault_debug; 102 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 103 " enable detection of firmware fault and halt firmware - (default=0)"); 104 105 static int perf_mode = -1; 106 module_param(perf_mode, int, 0444); 107 MODULE_PARM_DESC(perf_mode, 108 "Performance mode (only for Aero/Sea Generation), options:\n\t\t" 109 "0 - balanced: high iops mode is enabled &\n\t\t" 110 "interrupt coalescing is enabled only on high iops queues,\n\t\t" 111 "1 - iops: high iops mode is disabled &\n\t\t" 112 "interrupt coalescing is enabled on all queues,\n\t\t" 113 "2 - latency: high iops mode is disabled &\n\t\t" 114 "interrupt coalescing is enabled on all queues with timeout value 0xA,\n" 115 "\t\tdefault - default perf_mode is 'balanced'" 116 ); 117 118 static int poll_queues; 119 module_param(poll_queues, int, 0444); 120 MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t" 121 "This parameter is effective only if host_tagset_enable=1. &\n\t\t" 122 "when poll_queues are enabled then &\n\t\t" 123 "perf_mode is set to latency mode. &\n\t\t" 124 ); 125 126 enum mpt3sas_perf_mode { 127 MPT_PERF_MODE_DEFAULT = -1, 128 MPT_PERF_MODE_BALANCED = 0, 129 MPT_PERF_MODE_IOPS = 1, 130 MPT_PERF_MODE_LATENCY = 2, 131 }; 132 133 static int 134 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, 135 u32 ioc_state, int timeout); 136 static int 137 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); 138 static void 139 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc); 140 141 static u32 142 _base_readl_ext_retry(const void __iomem *addr); 143 144 /** 145 * mpt3sas_base_check_cmd_timeout - Function 146 * to check timeout and command termination due 147 * to Host reset. 148 * 149 * @ioc: per adapter object. 150 * @status: Status of issued command. 151 * @mpi_request:mf request pointer. 152 * @sz: size of buffer. 153 * 154 * Return: 1/0 Reset to be done or Not 155 */ 156 u8 157 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, 158 u8 status, void *mpi_request, int sz) 159 { 160 u8 issue_reset = 0; 161 162 if (!(status & MPT3_CMD_RESET)) 163 issue_reset = 1; 164 165 ioc_err(ioc, "Command %s\n", 166 issue_reset == 0 ? "terminated due to Host Reset" : "Timeout"); 167 _debug_dump_mf(mpi_request, sz); 168 169 return issue_reset; 170 } 171 172 /** 173 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 174 * @val: ? 175 * @kp: ? 176 * 177 * Return: ? 178 */ 179 static int 180 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) 181 { 182 int ret = param_set_int(val, kp); 183 struct MPT3SAS_ADAPTER *ioc; 184 185 if (ret) 186 return ret; 187 188 /* global ioc spinlock to protect controller list on list operations */ 189 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 190 spin_lock(&gioc_lock); 191 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 192 ioc->fwfault_debug = mpt3sas_fwfault_debug; 193 spin_unlock(&gioc_lock); 194 return 0; 195 } 196 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 197 param_get_int, &mpt3sas_fwfault_debug, 0644); 198 199 /** 200 * _base_readl_aero - retry readl for max three times. 201 * @addr: MPT Fusion system interface register address 202 * 203 * Retry the readl() for max three times if it gets zero value 204 * while reading the system interface register. 205 */ 206 static inline u32 207 _base_readl_aero(const void __iomem *addr) 208 { 209 u32 i = 0, ret_val; 210 211 do { 212 ret_val = readl(addr); 213 i++; 214 } while (ret_val == 0 && i < 3); 215 216 return ret_val; 217 } 218 219 static u32 220 _base_readl_ext_retry(const void __iomem *addr) 221 { 222 u32 i, ret_val; 223 224 for (i = 0 ; i < 30 ; i++) { 225 ret_val = readl(addr); 226 if (ret_val != 0) 227 break; 228 } 229 230 return ret_val; 231 } 232 233 static inline u32 234 _base_readl(const void __iomem *addr) 235 { 236 return readl(addr); 237 } 238 239 /** 240 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem 241 * in BAR0 space. 242 * 243 * @ioc: per adapter object 244 * @reply: reply message frame(lower 32bit addr) 245 * @index: System request message index. 246 */ 247 static void 248 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply, 249 u32 index) 250 { 251 /* 252 * 256 is offset within sys register. 253 * 256 offset MPI frame starts. Max MPI frame supported is 32. 254 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts 255 */ 256 u16 cmd_credit = ioc->facts.RequestCredit + 1; 257 void __iomem *reply_free_iomem = (void __iomem *)ioc->chip + 258 MPI_FRAME_START_OFFSET + 259 (cmd_credit * ioc->request_sz) + (index * sizeof(u32)); 260 261 writel(reply, reply_free_iomem); 262 } 263 264 /** 265 * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames 266 * to system/BAR0 region. 267 * 268 * @dst_iomem: Pointer to the destination location in BAR0 space. 269 * @src: Pointer to the Source data. 270 * @size: Size of data to be copied. 271 */ 272 static void 273 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size) 274 { 275 int i; 276 u32 *src_virt_mem = (u32 *)src; 277 278 for (i = 0; i < size/4; i++) 279 writel((u32)src_virt_mem[i], 280 (void __iomem *)dst_iomem + (i * 4)); 281 } 282 283 /** 284 * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region 285 * 286 * @dst_iomem: Pointer to the destination location in BAR0 space. 287 * @src: Pointer to the Source data. 288 * @size: Size of data to be copied. 289 */ 290 static void 291 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size) 292 { 293 int i; 294 u32 *src_virt_mem = (u32 *)(src); 295 296 for (i = 0; i < size/4; i++) 297 writel((u32)src_virt_mem[i], 298 (void __iomem *)dst_iomem + (i * 4)); 299 } 300 301 /** 302 * _base_get_chain - Calculates and Returns virtual chain address 303 * for the provided smid in BAR0 space. 304 * 305 * @ioc: per adapter object 306 * @smid: system request message index 307 * @sge_chain_count: Scatter gather chain count. 308 * 309 * Return: the chain address. 310 */ 311 static inline void __iomem* 312 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid, 313 u8 sge_chain_count) 314 { 315 void __iomem *base_chain, *chain_virt; 316 u16 cmd_credit = ioc->facts.RequestCredit + 1; 317 318 base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET + 319 (cmd_credit * ioc->request_sz) + 320 REPLY_FREE_POOL_SIZE; 321 chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth * 322 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 323 return chain_virt; 324 } 325 326 /** 327 * _base_get_chain_phys - Calculates and Returns physical address 328 * in BAR0 for scatter gather chains, for 329 * the provided smid. 330 * 331 * @ioc: per adapter object 332 * @smid: system request message index 333 * @sge_chain_count: Scatter gather chain count. 334 * 335 * Return: Physical chain address. 336 */ 337 static inline phys_addr_t 338 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid, 339 u8 sge_chain_count) 340 { 341 phys_addr_t base_chain_phys, chain_phys; 342 u16 cmd_credit = ioc->facts.RequestCredit + 1; 343 344 base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET + 345 (cmd_credit * ioc->request_sz) + 346 REPLY_FREE_POOL_SIZE; 347 chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth * 348 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 349 return chain_phys; 350 } 351 352 /** 353 * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host 354 * buffer address for the provided smid. 355 * (Each smid can have 64K starts from 17024) 356 * 357 * @ioc: per adapter object 358 * @smid: system request message index 359 * 360 * Return: Pointer to buffer location in BAR0. 361 */ 362 363 static void __iomem * 364 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 365 { 366 u16 cmd_credit = ioc->facts.RequestCredit + 1; 367 // Added extra 1 to reach end of chain. 368 void __iomem *chain_end = _base_get_chain(ioc, 369 cmd_credit + 1, 370 ioc->facts.MaxChainDepth); 371 return chain_end + (smid * 64 * 1024); 372 } 373 374 /** 375 * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped 376 * Host buffer Physical address for the provided smid. 377 * (Each smid can have 64K starts from 17024) 378 * 379 * @ioc: per adapter object 380 * @smid: system request message index 381 * 382 * Return: Pointer to buffer location in BAR0. 383 */ 384 static phys_addr_t 385 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 386 { 387 u16 cmd_credit = ioc->facts.RequestCredit + 1; 388 phys_addr_t chain_end_phys = _base_get_chain_phys(ioc, 389 cmd_credit + 1, 390 ioc->facts.MaxChainDepth); 391 return chain_end_phys + (smid * 64 * 1024); 392 } 393 394 /** 395 * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain 396 * lookup list and Provides chain_buffer 397 * address for the matching dma address. 398 * (Each smid can have 64K starts from 17024) 399 * 400 * @ioc: per adapter object 401 * @chain_buffer_dma: Chain buffer dma address. 402 * 403 * Return: Pointer to chain buffer. Or Null on Failure. 404 */ 405 static void * 406 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc, 407 dma_addr_t chain_buffer_dma) 408 { 409 u16 index, j; 410 struct chain_tracker *ct; 411 412 for (index = 0; index < ioc->scsiio_depth; index++) { 413 for (j = 0; j < ioc->chains_needed_per_io; j++) { 414 ct = &ioc->chain_lookup[index].chains_per_smid[j]; 415 if (ct && ct->chain_buffer_dma == chain_buffer_dma) 416 return ct->chain_buffer; 417 } 418 } 419 ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n"); 420 return NULL; 421 } 422 423 /** 424 * _clone_sg_entries - MPI EP's scsiio and config requests 425 * are handled here. Base function for 426 * double buffering, before submitting 427 * the requests. 428 * 429 * @ioc: per adapter object. 430 * @mpi_request: mf request pointer. 431 * @smid: system request message index. 432 */ 433 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc, 434 void *mpi_request, u16 smid) 435 { 436 Mpi2SGESimple32_t *sgel, *sgel_next; 437 u32 sgl_flags, sge_chain_count = 0; 438 bool is_write = false; 439 u16 i = 0; 440 void __iomem *buffer_iomem; 441 phys_addr_t buffer_iomem_phys; 442 void __iomem *buff_ptr; 443 phys_addr_t buff_ptr_phys; 444 void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 445 void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 446 phys_addr_t dst_addr_phys; 447 MPI2RequestHeader_t *request_hdr; 448 struct scsi_cmnd *scmd; 449 struct scatterlist *sg_scmd = NULL; 450 int is_scsiio_req = 0; 451 452 request_hdr = (MPI2RequestHeader_t *) mpi_request; 453 454 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 455 Mpi25SCSIIORequest_t *scsiio_request = 456 (Mpi25SCSIIORequest_t *)mpi_request; 457 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL; 458 is_scsiio_req = 1; 459 } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { 460 Mpi2ConfigRequest_t *config_req = 461 (Mpi2ConfigRequest_t *)mpi_request; 462 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE; 463 } else 464 return; 465 466 /* From smid we can get scsi_cmd, once we have sg_scmd, 467 * we just need to get sg_virt and sg_next to get virtual 468 * address associated with sgel->Address. 469 */ 470 471 if (is_scsiio_req) { 472 /* Get scsi_cmd using smid */ 473 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 474 if (scmd == NULL) { 475 ioc_err(ioc, "scmd is NULL\n"); 476 return; 477 } 478 479 /* Get sg_scmd from scmd provided */ 480 sg_scmd = scsi_sglist(scmd); 481 } 482 483 /* 484 * 0 - 255 System register 485 * 256 - 4352 MPI Frame. (This is based on maxCredit 32) 486 * 4352 - 4864 Reply_free pool (512 byte is reserved 487 * considering maxCredit 32. Reply need extra 488 * room, for mCPU case kept four times of 489 * maxCredit). 490 * 4864 - 17152 SGE chain element. (32cmd * 3 chain of 491 * 128 byte size = 12288) 492 * 17152 - x Host buffer mapped with smid. 493 * (Each smid can have 64K Max IO.) 494 * BAR0+Last 1K MSIX Addr and Data 495 * Total size in use 2113664 bytes of 4MB BAR0 496 */ 497 498 buffer_iomem = _base_get_buffer_bar0(ioc, smid); 499 buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid); 500 501 buff_ptr = buffer_iomem; 502 buff_ptr_phys = buffer_iomem_phys; 503 WARN_ON(buff_ptr_phys > U32_MAX); 504 505 if (le32_to_cpu(sgel->FlagsLength) & 506 (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT)) 507 is_write = true; 508 509 for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) { 510 511 sgl_flags = 512 (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT); 513 514 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) { 515 case MPI2_SGE_FLAGS_CHAIN_ELEMENT: 516 /* 517 * Helper function which on passing 518 * chain_buffer_dma returns chain_buffer. Get 519 * the virtual address for sgel->Address 520 */ 521 sgel_next = 522 _base_get_chain_buffer_dma_to_chain_buffer(ioc, 523 le32_to_cpu(sgel->Address)); 524 if (sgel_next == NULL) 525 return; 526 /* 527 * This is coping 128 byte chain 528 * frame (not a host buffer) 529 */ 530 dst_chain_addr[sge_chain_count] = 531 _base_get_chain(ioc, 532 smid, sge_chain_count); 533 src_chain_addr[sge_chain_count] = 534 (void *) sgel_next; 535 dst_addr_phys = _base_get_chain_phys(ioc, 536 smid, sge_chain_count); 537 WARN_ON(dst_addr_phys > U32_MAX); 538 sgel->Address = 539 cpu_to_le32(lower_32_bits(dst_addr_phys)); 540 sgel = sgel_next; 541 sge_chain_count++; 542 break; 543 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT: 544 if (is_write) { 545 if (is_scsiio_req) { 546 _base_clone_to_sys_mem(buff_ptr, 547 sg_virt(sg_scmd), 548 (le32_to_cpu(sgel->FlagsLength) & 549 0x00ffffff)); 550 /* 551 * FIXME: this relies on a a zero 552 * PCI mem_offset. 553 */ 554 sgel->Address = 555 cpu_to_le32((u32)buff_ptr_phys); 556 } else { 557 _base_clone_to_sys_mem(buff_ptr, 558 ioc->config_vaddr, 559 (le32_to_cpu(sgel->FlagsLength) & 560 0x00ffffff)); 561 sgel->Address = 562 cpu_to_le32((u32)buff_ptr_phys); 563 } 564 } 565 buff_ptr += (le32_to_cpu(sgel->FlagsLength) & 566 0x00ffffff); 567 buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) & 568 0x00ffffff); 569 if ((le32_to_cpu(sgel->FlagsLength) & 570 (MPI2_SGE_FLAGS_END_OF_BUFFER 571 << MPI2_SGE_FLAGS_SHIFT))) 572 goto eob_clone_chain; 573 else { 574 /* 575 * Every single element in MPT will have 576 * associated sg_next. Better to sanity that 577 * sg_next is not NULL, but it will be a bug 578 * if it is null. 579 */ 580 if (is_scsiio_req) { 581 sg_scmd = sg_next(sg_scmd); 582 if (sg_scmd) 583 sgel++; 584 else 585 goto eob_clone_chain; 586 } 587 } 588 break; 589 } 590 } 591 592 eob_clone_chain: 593 for (i = 0; i < sge_chain_count; i++) { 594 if (is_scsiio_req) 595 _base_clone_to_sys_mem(dst_chain_addr[i], 596 src_chain_addr[i], ioc->request_sz); 597 } 598 } 599 600 /** 601 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 602 * @arg: input argument, used to derive ioc 603 * 604 * Return: 605 * 0 if controller is removed from pci subsystem. 606 * -1 for other case. 607 */ 608 static int mpt3sas_remove_dead_ioc_func(void *arg) 609 { 610 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 611 struct pci_dev *pdev; 612 613 if (!ioc) 614 return -1; 615 616 pdev = ioc->pdev; 617 if (!pdev) 618 return -1; 619 pci_stop_and_remove_bus_device_locked(pdev); 620 return 0; 621 } 622 623 /** 624 * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp. 625 * @ioc: Per Adapter Object 626 * 627 * Return: nothing. 628 */ 629 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc) 630 { 631 Mpi26IoUnitControlRequest_t *mpi_request; 632 Mpi26IoUnitControlReply_t *mpi_reply; 633 u16 smid; 634 ktime_t current_time; 635 u64 TimeStamp = 0; 636 u8 issue_reset = 0; 637 638 mutex_lock(&ioc->scsih_cmds.mutex); 639 if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) { 640 ioc_err(ioc, "scsih_cmd in use %s\n", __func__); 641 goto out; 642 } 643 ioc->scsih_cmds.status = MPT3_CMD_PENDING; 644 smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx); 645 if (!smid) { 646 ioc_err(ioc, "Failed obtaining a smid %s\n", __func__); 647 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 648 goto out; 649 } 650 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 651 ioc->scsih_cmds.smid = smid; 652 memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t)); 653 mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL; 654 mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER; 655 mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP; 656 current_time = ktime_get_real(); 657 TimeStamp = ktime_to_ms(current_time); 658 mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32); 659 mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF); 660 init_completion(&ioc->scsih_cmds.done); 661 ioc->put_smid_default(ioc, smid); 662 dinitprintk(ioc, ioc_info(ioc, 663 "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n", 664 TimeStamp)); 665 wait_for_completion_timeout(&ioc->scsih_cmds.done, 666 MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ); 667 if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) { 668 mpt3sas_check_cmd_timeout(ioc, 669 ioc->scsih_cmds.status, mpi_request, 670 sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset); 671 goto issue_host_reset; 672 } 673 if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) { 674 mpi_reply = ioc->scsih_cmds.reply; 675 dinitprintk(ioc, ioc_info(ioc, 676 "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n", 677 le16_to_cpu(mpi_reply->IOCStatus), 678 le32_to_cpu(mpi_reply->IOCLogInfo))); 679 } 680 issue_host_reset: 681 if (issue_reset) 682 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 683 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 684 out: 685 mutex_unlock(&ioc->scsih_cmds.mutex); 686 } 687 688 /** 689 * _base_fault_reset_work - workq handling ioc fault conditions 690 * @work: input argument, used to derive ioc 691 * 692 * Context: sleep. 693 */ 694 static void 695 _base_fault_reset_work(struct work_struct *work) 696 { 697 struct MPT3SAS_ADAPTER *ioc = 698 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 699 unsigned long flags; 700 u32 doorbell; 701 int rc; 702 struct task_struct *p; 703 704 705 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 706 if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) || 707 ioc->pci_error_recovery) 708 goto rearm_timer; 709 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 710 711 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 712 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 713 ioc_err(ioc, "SAS host is non-operational !!!!\n"); 714 715 /* It may be possible that EEH recovery can resolve some of 716 * pci bus failure issues rather removing the dead ioc function 717 * by considering controller is in a non-operational state. So 718 * here priority is given to the EEH recovery. If it doesn't 719 * not resolve this issue, mpt3sas driver will consider this 720 * controller to non-operational state and remove the dead ioc 721 * function. 722 */ 723 if (ioc->non_operational_loop++ < 5) { 724 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 725 flags); 726 goto rearm_timer; 727 } 728 729 /* 730 * Call _scsih_flush_pending_cmds callback so that we flush all 731 * pending commands back to OS. This call is required to avoid 732 * deadlock at block layer. Dead IOC will fail to do diag reset, 733 * and this call is safe since dead ioc will never return any 734 * command back from HW. 735 */ 736 mpt3sas_base_pause_mq_polling(ioc); 737 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 738 /* 739 * Set remove_host flag early since kernel thread will 740 * take some time to execute. 741 */ 742 ioc->remove_host = 1; 743 /*Remove the Dead Host */ 744 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 745 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 746 if (IS_ERR(p)) 747 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 748 __func__); 749 else 750 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 751 __func__); 752 return; /* don't rearm timer */ 753 } 754 755 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { 756 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? 757 ioc->manu_pg11.CoreDumpTOSec : 758 MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; 759 760 timeout /= (FAULT_POLLING_INTERVAL/1000); 761 762 if (ioc->ioc_coredump_loop == 0) { 763 mpt3sas_print_coredump_info(ioc, 764 doorbell & MPI2_DOORBELL_DATA_MASK); 765 /* do not accept any IOs and disable the interrupts */ 766 spin_lock_irqsave( 767 &ioc->ioc_reset_in_progress_lock, flags); 768 ioc->shost_recovery = 1; 769 spin_unlock_irqrestore( 770 &ioc->ioc_reset_in_progress_lock, flags); 771 mpt3sas_base_mask_interrupts(ioc); 772 mpt3sas_base_pause_mq_polling(ioc); 773 _base_clear_outstanding_commands(ioc); 774 } 775 776 ioc_info(ioc, "%s: CoreDump loop %d.", 777 __func__, ioc->ioc_coredump_loop); 778 779 /* Wait until CoreDump completes or times out */ 780 if (ioc->ioc_coredump_loop++ < timeout) { 781 spin_lock_irqsave( 782 &ioc->ioc_reset_in_progress_lock, flags); 783 goto rearm_timer; 784 } 785 } 786 787 if (ioc->ioc_coredump_loop) { 788 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP) 789 ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d", 790 __func__, ioc->ioc_coredump_loop); 791 else 792 ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d", 793 __func__, ioc->ioc_coredump_loop); 794 ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE; 795 } 796 ioc->non_operational_loop = 0; 797 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 798 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 799 ioc_warn(ioc, "%s: hard reset: %s\n", 800 __func__, rc == 0 ? "success" : "failed"); 801 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 802 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 803 mpt3sas_print_fault_code(ioc, doorbell & 804 MPI2_DOORBELL_DATA_MASK); 805 } else if ((doorbell & MPI2_IOC_STATE_MASK) == 806 MPI2_IOC_STATE_COREDUMP) 807 mpt3sas_print_coredump_info(ioc, doorbell & 808 MPI2_DOORBELL_DATA_MASK); 809 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 810 MPI2_IOC_STATE_OPERATIONAL) 811 return; /* don't rearm timer */ 812 } 813 ioc->ioc_coredump_loop = 0; 814 if (ioc->time_sync_interval && 815 ++ioc->timestamp_update_count >= ioc->time_sync_interval) { 816 ioc->timestamp_update_count = 0; 817 _base_sync_drv_fw_timestamp(ioc); 818 } 819 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 820 rearm_timer: 821 if (ioc->fault_reset_work_q) 822 queue_delayed_work(ioc->fault_reset_work_q, 823 &ioc->fault_reset_work, 824 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 825 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 826 } 827 828 /** 829 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 830 * @ioc: per adapter object 831 * 832 * Context: sleep. 833 */ 834 void 835 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 836 { 837 unsigned long flags; 838 839 if (ioc->fault_reset_work_q) 840 return; 841 842 ioc->timestamp_update_count = 0; 843 /* initialize fault polling */ 844 845 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 846 snprintf(ioc->fault_reset_work_q_name, 847 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 848 ioc->driver_name, ioc->id); 849 ioc->fault_reset_work_q = 850 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 851 if (!ioc->fault_reset_work_q) { 852 ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__); 853 return; 854 } 855 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 856 if (ioc->fault_reset_work_q) 857 queue_delayed_work(ioc->fault_reset_work_q, 858 &ioc->fault_reset_work, 859 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 860 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 861 } 862 863 /** 864 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 865 * @ioc: per adapter object 866 * 867 * Context: sleep. 868 */ 869 void 870 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 871 { 872 unsigned long flags; 873 struct workqueue_struct *wq; 874 875 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 876 wq = ioc->fault_reset_work_q; 877 ioc->fault_reset_work_q = NULL; 878 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 879 if (wq) { 880 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 881 flush_workqueue(wq); 882 destroy_workqueue(wq); 883 } 884 } 885 886 /** 887 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 888 * @ioc: per adapter object 889 * @fault_code: fault code 890 */ 891 void 892 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code) 893 { 894 ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code); 895 } 896 897 /** 898 * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state 899 * @ioc: per adapter object 900 * @fault_code: fault code 901 * 902 * Return: nothing. 903 */ 904 void 905 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code) 906 { 907 ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code); 908 } 909 910 /** 911 * mpt3sas_base_wait_for_coredump_completion - Wait until coredump 912 * completes or times out 913 * @ioc: per adapter object 914 * @caller: caller function name 915 * 916 * Return: 0 for success, non-zero for failure. 917 */ 918 int 919 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc, 920 const char *caller) 921 { 922 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? 923 ioc->manu_pg11.CoreDumpTOSec : 924 MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; 925 926 int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT, 927 timeout); 928 929 if (ioc_state) 930 ioc_err(ioc, 931 "%s: CoreDump timed out. (ioc_state=0x%x)\n", 932 caller, ioc_state); 933 else 934 ioc_info(ioc, 935 "%s: CoreDump completed. (ioc_state=0x%x)\n", 936 caller, ioc_state); 937 938 return ioc_state; 939 } 940 941 /** 942 * mpt3sas_halt_firmware - halt's mpt controller firmware 943 * @ioc: per adapter object 944 * 945 * For debugging timeout related issues. Writing 0xCOFFEE00 946 * to the doorbell register will halt controller firmware. With 947 * the purpose to stop both driver and firmware, the enduser can 948 * obtain a ring buffer from controller UART. 949 */ 950 void 951 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 952 { 953 u32 doorbell; 954 955 if (!ioc->fwfault_debug) 956 return; 957 958 dump_stack(); 959 960 doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); 961 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 962 mpt3sas_print_fault_code(ioc, doorbell & 963 MPI2_DOORBELL_DATA_MASK); 964 } else if ((doorbell & MPI2_IOC_STATE_MASK) == 965 MPI2_IOC_STATE_COREDUMP) { 966 mpt3sas_print_coredump_info(ioc, doorbell & 967 MPI2_DOORBELL_DATA_MASK); 968 } else { 969 writel(0xC0FFEE00, &ioc->chip->Doorbell); 970 ioc_err(ioc, "Firmware is halted due to command timeout\n"); 971 } 972 973 if (ioc->fwfault_debug == 2) 974 for (;;) 975 ; 976 else 977 panic("panic in %s\n", __func__); 978 } 979 980 /** 981 * _base_sas_ioc_info - verbose translation of the ioc status 982 * @ioc: per adapter object 983 * @mpi_reply: reply mf payload returned from firmware 984 * @request_hdr: request mf 985 */ 986 static void 987 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 988 MPI2RequestHeader_t *request_hdr) 989 { 990 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 991 MPI2_IOCSTATUS_MASK; 992 char *desc = NULL; 993 u16 frame_sz; 994 char *func_str = NULL; 995 996 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 997 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 998 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 999 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 1000 return; 1001 1002 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 1003 return; 1004 /* 1005 * Older Firmware version doesn't support driver trigger pages. 1006 * So, skip displaying 'config invalid type' type 1007 * of error message. 1008 */ 1009 if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { 1010 Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr; 1011 1012 if ((rqst->ExtPageType == 1013 MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) && 1014 !(ioc->logging_level & MPT_DEBUG_CONFIG)) { 1015 return; 1016 } 1017 } 1018 1019 switch (ioc_status) { 1020 1021 /**************************************************************************** 1022 * Common IOCStatus values for all replies 1023 ****************************************************************************/ 1024 1025 case MPI2_IOCSTATUS_INVALID_FUNCTION: 1026 desc = "invalid function"; 1027 break; 1028 case MPI2_IOCSTATUS_BUSY: 1029 desc = "busy"; 1030 break; 1031 case MPI2_IOCSTATUS_INVALID_SGL: 1032 desc = "invalid sgl"; 1033 break; 1034 case MPI2_IOCSTATUS_INTERNAL_ERROR: 1035 desc = "internal error"; 1036 break; 1037 case MPI2_IOCSTATUS_INVALID_VPID: 1038 desc = "invalid vpid"; 1039 break; 1040 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 1041 desc = "insufficient resources"; 1042 break; 1043 case MPI2_IOCSTATUS_INSUFFICIENT_POWER: 1044 desc = "insufficient power"; 1045 break; 1046 case MPI2_IOCSTATUS_INVALID_FIELD: 1047 desc = "invalid field"; 1048 break; 1049 case MPI2_IOCSTATUS_INVALID_STATE: 1050 desc = "invalid state"; 1051 break; 1052 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 1053 desc = "op state not supported"; 1054 break; 1055 1056 /**************************************************************************** 1057 * Config IOCStatus values 1058 ****************************************************************************/ 1059 1060 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 1061 desc = "config invalid action"; 1062 break; 1063 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 1064 desc = "config invalid type"; 1065 break; 1066 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 1067 desc = "config invalid page"; 1068 break; 1069 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 1070 desc = "config invalid data"; 1071 break; 1072 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 1073 desc = "config no defaults"; 1074 break; 1075 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 1076 desc = "config can't commit"; 1077 break; 1078 1079 /**************************************************************************** 1080 * SCSI IO Reply 1081 ****************************************************************************/ 1082 1083 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 1084 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 1085 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 1086 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 1087 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 1088 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 1089 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 1090 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 1091 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 1092 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 1093 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 1094 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 1095 break; 1096 1097 /**************************************************************************** 1098 * For use by SCSI Initiator and SCSI Target end-to-end data protection 1099 ****************************************************************************/ 1100 1101 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 1102 desc = "eedp guard error"; 1103 break; 1104 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 1105 desc = "eedp ref tag error"; 1106 break; 1107 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 1108 desc = "eedp app tag error"; 1109 break; 1110 1111 /**************************************************************************** 1112 * SCSI Target values 1113 ****************************************************************************/ 1114 1115 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 1116 desc = "target invalid io index"; 1117 break; 1118 case MPI2_IOCSTATUS_TARGET_ABORTED: 1119 desc = "target aborted"; 1120 break; 1121 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 1122 desc = "target no conn retryable"; 1123 break; 1124 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 1125 desc = "target no connection"; 1126 break; 1127 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 1128 desc = "target xfer count mismatch"; 1129 break; 1130 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 1131 desc = "target data offset error"; 1132 break; 1133 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 1134 desc = "target too much write data"; 1135 break; 1136 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 1137 desc = "target iu too short"; 1138 break; 1139 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 1140 desc = "target ack nak timeout"; 1141 break; 1142 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 1143 desc = "target nak received"; 1144 break; 1145 1146 /**************************************************************************** 1147 * Serial Attached SCSI values 1148 ****************************************************************************/ 1149 1150 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 1151 desc = "smp request failed"; 1152 break; 1153 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 1154 desc = "smp data overrun"; 1155 break; 1156 1157 /**************************************************************************** 1158 * Diagnostic Buffer Post / Diagnostic Release values 1159 ****************************************************************************/ 1160 1161 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 1162 desc = "diagnostic released"; 1163 break; 1164 default: 1165 break; 1166 } 1167 1168 if (!desc) 1169 return; 1170 1171 switch (request_hdr->Function) { 1172 case MPI2_FUNCTION_CONFIG: 1173 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 1174 func_str = "config_page"; 1175 break; 1176 case MPI2_FUNCTION_SCSI_TASK_MGMT: 1177 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 1178 func_str = "task_mgmt"; 1179 break; 1180 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 1181 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 1182 func_str = "sas_iounit_ctl"; 1183 break; 1184 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 1185 frame_sz = sizeof(Mpi2SepRequest_t); 1186 func_str = "enclosure"; 1187 break; 1188 case MPI2_FUNCTION_IOC_INIT: 1189 frame_sz = sizeof(Mpi2IOCInitRequest_t); 1190 func_str = "ioc_init"; 1191 break; 1192 case MPI2_FUNCTION_PORT_ENABLE: 1193 frame_sz = sizeof(Mpi2PortEnableRequest_t); 1194 func_str = "port_enable"; 1195 break; 1196 case MPI2_FUNCTION_SMP_PASSTHROUGH: 1197 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 1198 func_str = "smp_passthru"; 1199 break; 1200 case MPI2_FUNCTION_NVME_ENCAPSULATED: 1201 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) + 1202 ioc->sge_size; 1203 func_str = "nvme_encapsulated"; 1204 break; 1205 default: 1206 frame_sz = 32; 1207 func_str = "unknown"; 1208 break; 1209 } 1210 1211 ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 1212 desc, ioc_status, request_hdr, func_str); 1213 1214 _debug_dump_mf(request_hdr, frame_sz/4); 1215 } 1216 1217 /** 1218 * _base_display_event_data - verbose translation of firmware asyn events 1219 * @ioc: per adapter object 1220 * @mpi_reply: reply mf payload returned from firmware 1221 */ 1222 static void 1223 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 1224 Mpi2EventNotificationReply_t *mpi_reply) 1225 { 1226 char *desc = NULL; 1227 u16 event; 1228 1229 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 1230 return; 1231 1232 event = le16_to_cpu(mpi_reply->Event); 1233 1234 switch (event) { 1235 case MPI2_EVENT_LOG_DATA: 1236 desc = "Log Data"; 1237 break; 1238 case MPI2_EVENT_STATE_CHANGE: 1239 desc = "Status Change"; 1240 break; 1241 case MPI2_EVENT_HARD_RESET_RECEIVED: 1242 desc = "Hard Reset Received"; 1243 break; 1244 case MPI2_EVENT_EVENT_CHANGE: 1245 desc = "Event Change"; 1246 break; 1247 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 1248 desc = "Device Status Change"; 1249 break; 1250 case MPI2_EVENT_IR_OPERATION_STATUS: 1251 if (!ioc->hide_ir_msg) 1252 desc = "IR Operation Status"; 1253 break; 1254 case MPI2_EVENT_SAS_DISCOVERY: 1255 { 1256 Mpi2EventDataSasDiscovery_t *event_data = 1257 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 1258 ioc_info(ioc, "Discovery: (%s)", 1259 event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ? 1260 "start" : "stop"); 1261 if (event_data->DiscoveryStatus) 1262 pr_cont(" discovery_status(0x%08x)", 1263 le32_to_cpu(event_data->DiscoveryStatus)); 1264 pr_cont("\n"); 1265 return; 1266 } 1267 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 1268 desc = "SAS Broadcast Primitive"; 1269 break; 1270 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 1271 desc = "SAS Init Device Status Change"; 1272 break; 1273 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 1274 desc = "SAS Init Table Overflow"; 1275 break; 1276 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 1277 desc = "SAS Topology Change List"; 1278 break; 1279 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 1280 desc = "SAS Enclosure Device Status Change"; 1281 break; 1282 case MPI2_EVENT_IR_VOLUME: 1283 if (!ioc->hide_ir_msg) 1284 desc = "IR Volume"; 1285 break; 1286 case MPI2_EVENT_IR_PHYSICAL_DISK: 1287 if (!ioc->hide_ir_msg) 1288 desc = "IR Physical Disk"; 1289 break; 1290 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 1291 if (!ioc->hide_ir_msg) 1292 desc = "IR Configuration Change List"; 1293 break; 1294 case MPI2_EVENT_LOG_ENTRY_ADDED: 1295 if (!ioc->hide_ir_msg) 1296 desc = "Log Entry Added"; 1297 break; 1298 case MPI2_EVENT_TEMP_THRESHOLD: 1299 desc = "Temperature Threshold"; 1300 break; 1301 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 1302 desc = "Cable Event"; 1303 break; 1304 case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 1305 desc = "SAS Device Discovery Error"; 1306 break; 1307 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 1308 desc = "PCIE Device Status Change"; 1309 break; 1310 case MPI2_EVENT_PCIE_ENUMERATION: 1311 { 1312 Mpi26EventDataPCIeEnumeration_t *event_data = 1313 (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData; 1314 ioc_info(ioc, "PCIE Enumeration: (%s)", 1315 event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ? 1316 "start" : "stop"); 1317 if (event_data->EnumerationStatus) 1318 pr_cont("enumeration_status(0x%08x)", 1319 le32_to_cpu(event_data->EnumerationStatus)); 1320 pr_cont("\n"); 1321 return; 1322 } 1323 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 1324 desc = "PCIE Topology Change List"; 1325 break; 1326 } 1327 1328 if (!desc) 1329 return; 1330 1331 ioc_info(ioc, "%s\n", desc); 1332 } 1333 1334 /** 1335 * _base_sas_log_info - verbose translation of firmware log info 1336 * @ioc: per adapter object 1337 * @log_info: log info 1338 */ 1339 static void 1340 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc, u32 log_info) 1341 { 1342 union loginfo_type { 1343 u32 loginfo; 1344 struct { 1345 u32 subcode:16; 1346 u32 code:8; 1347 u32 originator:4; 1348 u32 bus_type:4; 1349 } dw; 1350 }; 1351 union loginfo_type sas_loginfo; 1352 char *originator_str = NULL; 1353 1354 sas_loginfo.loginfo = log_info; 1355 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 1356 return; 1357 1358 /* each nexus loss loginfo */ 1359 if (log_info == 0x31170000) 1360 return; 1361 1362 /* eat the loginfos associated with task aborts */ 1363 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 1364 0x31140000 || log_info == 0x31130000)) 1365 return; 1366 1367 switch (sas_loginfo.dw.originator) { 1368 case 0: 1369 originator_str = "IOP"; 1370 break; 1371 case 1: 1372 originator_str = "PL"; 1373 break; 1374 case 2: 1375 if (!ioc->hide_ir_msg) 1376 originator_str = "IR"; 1377 else 1378 originator_str = "WarpDrive"; 1379 break; 1380 } 1381 1382 ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 1383 log_info, 1384 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode); 1385 } 1386 1387 /** 1388 * _base_display_reply_info - handle reply descriptors depending on IOC Status 1389 * @ioc: per adapter object 1390 * @smid: system request message index 1391 * @msix_index: MSIX table index supplied by the OS 1392 * @reply: reply message frame (lower 32bit addr) 1393 */ 1394 static void 1395 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1396 u32 reply) 1397 { 1398 MPI2DefaultReply_t *mpi_reply; 1399 u16 ioc_status; 1400 u32 loginfo = 0; 1401 1402 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1403 if (unlikely(!mpi_reply)) { 1404 ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n", 1405 __FILE__, __LINE__, __func__); 1406 return; 1407 } 1408 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 1409 1410 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 1411 (ioc->logging_level & MPT_DEBUG_REPLY)) { 1412 _base_sas_ioc_info(ioc, mpi_reply, 1413 mpt3sas_base_get_msg_frame(ioc, smid)); 1414 } 1415 1416 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 1417 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 1418 _base_sas_log_info(ioc, loginfo); 1419 } 1420 1421 if (ioc_status || loginfo) { 1422 ioc_status &= MPI2_IOCSTATUS_MASK; 1423 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 1424 } 1425 } 1426 1427 /** 1428 * mpt3sas_base_done - base internal command completion routine 1429 * @ioc: per adapter object 1430 * @smid: system request message index 1431 * @msix_index: MSIX table index supplied by the OS 1432 * @reply: reply message frame(lower 32bit addr) 1433 * 1434 * Return: 1435 * 1 meaning mf should be freed from _base_interrupt 1436 * 0 means the mf is freed from this function. 1437 */ 1438 u8 1439 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1440 u32 reply) 1441 { 1442 MPI2DefaultReply_t *mpi_reply; 1443 1444 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1445 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 1446 return mpt3sas_check_for_pending_internal_cmds(ioc, smid); 1447 1448 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 1449 return 1; 1450 1451 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 1452 if (mpi_reply) { 1453 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 1454 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 1455 } 1456 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 1457 1458 complete(&ioc->base_cmds.done); 1459 return 1; 1460 } 1461 1462 /** 1463 * _base_async_event - main callback handler for firmware asyn events 1464 * @ioc: per adapter object 1465 * @msix_index: MSIX table index supplied by the OS 1466 * @reply: reply message frame(lower 32bit addr) 1467 * 1468 * Return: 1469 * 1 meaning mf should be freed from _base_interrupt 1470 * 0 means the mf is freed from this function. 1471 */ 1472 static u8 1473 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 1474 { 1475 Mpi2EventNotificationReply_t *mpi_reply; 1476 Mpi2EventAckRequest_t *ack_request; 1477 u16 smid; 1478 struct _event_ack_list *delayed_event_ack; 1479 1480 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1481 if (!mpi_reply) 1482 return 1; 1483 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 1484 return 1; 1485 1486 _base_display_event_data(ioc, mpi_reply); 1487 1488 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 1489 goto out; 1490 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 1491 if (!smid) { 1492 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), 1493 GFP_ATOMIC); 1494 if (!delayed_event_ack) 1495 goto out; 1496 INIT_LIST_HEAD(&delayed_event_ack->list); 1497 delayed_event_ack->Event = mpi_reply->Event; 1498 delayed_event_ack->EventContext = mpi_reply->EventContext; 1499 list_add_tail(&delayed_event_ack->list, 1500 &ioc->delayed_event_ack_list); 1501 dewtprintk(ioc, 1502 ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n", 1503 le16_to_cpu(mpi_reply->Event))); 1504 goto out; 1505 } 1506 1507 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 1508 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 1509 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 1510 ack_request->Event = mpi_reply->Event; 1511 ack_request->EventContext = mpi_reply->EventContext; 1512 ack_request->VF_ID = 0; /* TODO */ 1513 ack_request->VP_ID = 0; 1514 ioc->put_smid_default(ioc, smid); 1515 1516 out: 1517 1518 /* scsih callback handler */ 1519 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 1520 1521 /* ctl callback handler */ 1522 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 1523 1524 return 1; 1525 } 1526 1527 static struct scsiio_tracker * 1528 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1529 { 1530 struct scsi_cmnd *cmd; 1531 1532 if (WARN_ON(!smid) || 1533 WARN_ON(smid >= ioc->hi_priority_smid)) 1534 return NULL; 1535 1536 cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 1537 if (cmd) 1538 return scsi_cmd_priv(cmd); 1539 1540 return NULL; 1541 } 1542 1543 /** 1544 * _base_get_cb_idx - obtain the callback index 1545 * @ioc: per adapter object 1546 * @smid: system request message index 1547 * 1548 * Return: callback index. 1549 */ 1550 static u8 1551 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1552 { 1553 int i; 1554 u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1; 1555 u8 cb_idx = 0xFF; 1556 1557 if (smid < ioc->hi_priority_smid) { 1558 struct scsiio_tracker *st; 1559 1560 if (smid < ctl_smid) { 1561 st = _get_st_from_smid(ioc, smid); 1562 if (st) 1563 cb_idx = st->cb_idx; 1564 } else if (smid == ctl_smid) 1565 cb_idx = ioc->ctl_cb_idx; 1566 } else if (smid < ioc->internal_smid) { 1567 i = smid - ioc->hi_priority_smid; 1568 cb_idx = ioc->hpr_lookup[i].cb_idx; 1569 } else if (smid <= ioc->hba_queue_depth) { 1570 i = smid - ioc->internal_smid; 1571 cb_idx = ioc->internal_lookup[i].cb_idx; 1572 } 1573 return cb_idx; 1574 } 1575 1576 /** 1577 * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues 1578 * when driver is flushing out the IOs. 1579 * @ioc: per adapter object 1580 * 1581 * Pause polling on the mq poll (io uring) queues when driver is flushing 1582 * out the IOs. Otherwise we may see the race condition of completing the same 1583 * IO from two paths. 1584 * 1585 * Returns nothing. 1586 */ 1587 void 1588 mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc) 1589 { 1590 int iopoll_q_count = 1591 ioc->reply_queue_count - ioc->iopoll_q_start_index; 1592 int qid; 1593 1594 for (qid = 0; qid < iopoll_q_count; qid++) 1595 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1); 1596 1597 /* 1598 * wait for current poll to complete. 1599 */ 1600 for (qid = 0; qid < iopoll_q_count; qid++) { 1601 while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) { 1602 cpu_relax(); 1603 udelay(500); 1604 } 1605 } 1606 } 1607 1608 /** 1609 * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues. 1610 * @ioc: per adapter object 1611 * 1612 * Returns nothing. 1613 */ 1614 void 1615 mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc) 1616 { 1617 int iopoll_q_count = 1618 ioc->reply_queue_count - ioc->iopoll_q_start_index; 1619 int qid; 1620 1621 for (qid = 0; qid < iopoll_q_count; qid++) 1622 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0); 1623 } 1624 1625 /** 1626 * mpt3sas_base_mask_interrupts - disable interrupts 1627 * @ioc: per adapter object 1628 * 1629 * Disabling ResetIRQ, Reply and Doorbell Interrupts 1630 */ 1631 void 1632 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1633 { 1634 u32 him_register; 1635 1636 ioc->mask_interrupts = 1; 1637 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); 1638 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 1639 writel(him_register, &ioc->chip->HostInterruptMask); 1640 ioc->base_readl(&ioc->chip->HostInterruptMask); 1641 } 1642 1643 /** 1644 * mpt3sas_base_unmask_interrupts - enable interrupts 1645 * @ioc: per adapter object 1646 * 1647 * Enabling only Reply Interrupts 1648 */ 1649 void 1650 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1651 { 1652 u32 him_register; 1653 1654 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); 1655 him_register &= ~MPI2_HIM_RIM; 1656 writel(him_register, &ioc->chip->HostInterruptMask); 1657 ioc->mask_interrupts = 0; 1658 } 1659 1660 union reply_descriptor { 1661 u64 word; 1662 struct { 1663 u32 low; 1664 u32 high; 1665 } u; 1666 }; 1667 1668 static u32 base_mod64(u64 dividend, u32 divisor) 1669 { 1670 u32 remainder; 1671 1672 if (!divisor) 1673 pr_err("mpt3sas: DIVISOR is zero, in div fn\n"); 1674 remainder = do_div(dividend, divisor); 1675 return remainder; 1676 } 1677 1678 /** 1679 * _base_process_reply_queue - Process reply descriptors from reply 1680 * descriptor post queue. 1681 * @reply_q: per IRQ's reply queue object. 1682 * 1683 * Return: number of reply descriptors processed from reply 1684 * descriptor queue. 1685 */ 1686 static int 1687 _base_process_reply_queue(struct adapter_reply_queue *reply_q) 1688 { 1689 union reply_descriptor rd; 1690 u64 completed_cmds; 1691 u8 request_descript_type; 1692 u16 smid; 1693 u8 cb_idx; 1694 u32 reply; 1695 u8 msix_index = reply_q->msix_index; 1696 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 1697 Mpi2ReplyDescriptorsUnion_t *rpf; 1698 u8 rc; 1699 1700 completed_cmds = 0; 1701 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 1702 return completed_cmds; 1703 1704 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 1705 request_descript_type = rpf->Default.ReplyFlags 1706 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1707 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 1708 atomic_dec(&reply_q->busy); 1709 return completed_cmds; 1710 } 1711 1712 cb_idx = 0xFF; 1713 do { 1714 rd.word = le64_to_cpu(rpf->Words); 1715 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 1716 goto out; 1717 reply = 0; 1718 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 1719 if (request_descript_type == 1720 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 1721 request_descript_type == 1722 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 1723 request_descript_type == 1724 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) { 1725 cb_idx = _base_get_cb_idx(ioc, smid); 1726 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1727 (likely(mpt_callbacks[cb_idx] != NULL))) { 1728 rc = mpt_callbacks[cb_idx](ioc, smid, 1729 msix_index, 0); 1730 if (rc) 1731 mpt3sas_base_free_smid(ioc, smid); 1732 } 1733 } else if (request_descript_type == 1734 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 1735 reply = le32_to_cpu( 1736 rpf->AddressReply.ReplyFrameAddress); 1737 if (reply > ioc->reply_dma_max_address || 1738 reply < ioc->reply_dma_min_address) 1739 reply = 0; 1740 if (smid) { 1741 cb_idx = _base_get_cb_idx(ioc, smid); 1742 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1743 (likely(mpt_callbacks[cb_idx] != NULL))) { 1744 rc = mpt_callbacks[cb_idx](ioc, smid, 1745 msix_index, reply); 1746 if (reply) 1747 _base_display_reply_info(ioc, 1748 smid, msix_index, reply); 1749 if (rc) 1750 mpt3sas_base_free_smid(ioc, 1751 smid); 1752 } 1753 } else { 1754 _base_async_event(ioc, msix_index, reply); 1755 } 1756 1757 /* reply free queue handling */ 1758 if (reply) { 1759 ioc->reply_free_host_index = 1760 (ioc->reply_free_host_index == 1761 (ioc->reply_free_queue_depth - 1)) ? 1762 0 : ioc->reply_free_host_index + 1; 1763 ioc->reply_free[ioc->reply_free_host_index] = 1764 cpu_to_le32(reply); 1765 if (ioc->is_mcpu_endpoint) 1766 _base_clone_reply_to_sys_mem(ioc, 1767 reply, 1768 ioc->reply_free_host_index); 1769 writel(ioc->reply_free_host_index, 1770 &ioc->chip->ReplyFreeHostIndex); 1771 } 1772 } 1773 1774 rpf->Words = cpu_to_le64(ULLONG_MAX); 1775 reply_q->reply_post_host_index = 1776 (reply_q->reply_post_host_index == 1777 (ioc->reply_post_queue_depth - 1)) ? 0 : 1778 reply_q->reply_post_host_index + 1; 1779 request_descript_type = 1780 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1781 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1782 completed_cmds++; 1783 /* Update the reply post host index after continuously 1784 * processing the threshold number of Reply Descriptors. 1785 * So that FW can find enough entries to post the Reply 1786 * Descriptors in the reply descriptor post queue. 1787 */ 1788 if (completed_cmds >= ioc->thresh_hold) { 1789 if (ioc->combined_reply_queue) { 1790 writel(reply_q->reply_post_host_index | 1791 ((msix_index & 7) << 1792 MPI2_RPHI_MSIX_INDEX_SHIFT), 1793 ioc->replyPostRegisterIndex[msix_index/8]); 1794 } else { 1795 writel(reply_q->reply_post_host_index | 1796 (msix_index << 1797 MPI2_RPHI_MSIX_INDEX_SHIFT), 1798 &ioc->chip->ReplyPostHostIndex); 1799 } 1800 if (!reply_q->is_iouring_poll_q && 1801 !reply_q->irq_poll_scheduled) { 1802 reply_q->irq_poll_scheduled = true; 1803 irq_poll_sched(&reply_q->irqpoll); 1804 } 1805 atomic_dec(&reply_q->busy); 1806 return completed_cmds; 1807 } 1808 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1809 goto out; 1810 if (!reply_q->reply_post_host_index) 1811 rpf = reply_q->reply_post_free; 1812 else 1813 rpf++; 1814 } while (1); 1815 1816 out: 1817 1818 if (!completed_cmds) { 1819 atomic_dec(&reply_q->busy); 1820 return completed_cmds; 1821 } 1822 1823 if (ioc->is_warpdrive) { 1824 writel(reply_q->reply_post_host_index, 1825 ioc->reply_post_host_index[msix_index]); 1826 atomic_dec(&reply_q->busy); 1827 return completed_cmds; 1828 } 1829 1830 /* Update Reply Post Host Index. 1831 * For those HBA's which support combined reply queue feature 1832 * 1. Get the correct Supplemental Reply Post Host Index Register. 1833 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1834 * Index Register address bank i.e replyPostRegisterIndex[], 1835 * 2. Then update this register with new reply host index value 1836 * in ReplyPostIndex field and the MSIxIndex field with 1837 * msix_index value reduced to a value between 0 and 7, 1838 * using a modulo 8 operation. Since each Supplemental Reply Post 1839 * Host Index Register supports 8 MSI-X vectors. 1840 * 1841 * For other HBA's just update the Reply Post Host Index register with 1842 * new reply host index value in ReplyPostIndex Field and msix_index 1843 * value in MSIxIndex field. 1844 */ 1845 if (ioc->combined_reply_queue) 1846 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1847 MPI2_RPHI_MSIX_INDEX_SHIFT), 1848 ioc->replyPostRegisterIndex[msix_index/8]); 1849 else 1850 writel(reply_q->reply_post_host_index | (msix_index << 1851 MPI2_RPHI_MSIX_INDEX_SHIFT), 1852 &ioc->chip->ReplyPostHostIndex); 1853 atomic_dec(&reply_q->busy); 1854 return completed_cmds; 1855 } 1856 1857 /** 1858 * mpt3sas_blk_mq_poll - poll the blk mq poll queue 1859 * @shost: Scsi_Host object 1860 * @queue_num: hw ctx queue number 1861 * 1862 * Return number of entries that has been processed from poll queue. 1863 */ 1864 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 1865 { 1866 struct MPT3SAS_ADAPTER *ioc = 1867 (struct MPT3SAS_ADAPTER *)shost->hostdata; 1868 struct adapter_reply_queue *reply_q; 1869 int num_entries = 0; 1870 int qid = queue_num - ioc->iopoll_q_start_index; 1871 1872 if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) || 1873 !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1)) 1874 return 0; 1875 1876 reply_q = ioc->io_uring_poll_queues[qid].reply_q; 1877 1878 num_entries = _base_process_reply_queue(reply_q); 1879 atomic_dec(&ioc->io_uring_poll_queues[qid].busy); 1880 1881 return num_entries; 1882 } 1883 1884 /** 1885 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 1886 * @irq: irq number (not used) 1887 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 1888 * 1889 * Return: IRQ_HANDLED if processed, else IRQ_NONE. 1890 */ 1891 static irqreturn_t 1892 _base_interrupt(int irq, void *bus_id) 1893 { 1894 struct adapter_reply_queue *reply_q = bus_id; 1895 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 1896 1897 if (ioc->mask_interrupts) 1898 return IRQ_NONE; 1899 if (reply_q->irq_poll_scheduled) 1900 return IRQ_HANDLED; 1901 return ((_base_process_reply_queue(reply_q) > 0) ? 1902 IRQ_HANDLED : IRQ_NONE); 1903 } 1904 1905 /** 1906 * _base_irqpoll - IRQ poll callback handler 1907 * @irqpoll: irq_poll object 1908 * @budget: irq poll weight 1909 * 1910 * Return: number of reply descriptors processed 1911 */ 1912 static int 1913 _base_irqpoll(struct irq_poll *irqpoll, int budget) 1914 { 1915 struct adapter_reply_queue *reply_q; 1916 int num_entries = 0; 1917 1918 reply_q = container_of(irqpoll, struct adapter_reply_queue, 1919 irqpoll); 1920 if (reply_q->irq_line_enable) { 1921 disable_irq_nosync(reply_q->os_irq); 1922 reply_q->irq_line_enable = false; 1923 } 1924 num_entries = _base_process_reply_queue(reply_q); 1925 if (num_entries < budget) { 1926 irq_poll_complete(irqpoll); 1927 reply_q->irq_poll_scheduled = false; 1928 reply_q->irq_line_enable = true; 1929 enable_irq(reply_q->os_irq); 1930 /* 1931 * Go for one more round of processing the 1932 * reply descriptor post queue in case the HBA 1933 * Firmware has posted some reply descriptors 1934 * while reenabling the IRQ. 1935 */ 1936 _base_process_reply_queue(reply_q); 1937 } 1938 1939 return num_entries; 1940 } 1941 1942 /** 1943 * _base_init_irqpolls - initliaze IRQ polls 1944 * @ioc: per adapter object 1945 * 1946 * Return: nothing 1947 */ 1948 static void 1949 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc) 1950 { 1951 struct adapter_reply_queue *reply_q, *next; 1952 1953 if (list_empty(&ioc->reply_queue_list)) 1954 return; 1955 1956 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1957 if (reply_q->is_iouring_poll_q) 1958 continue; 1959 irq_poll_init(&reply_q->irqpoll, 1960 ioc->hba_queue_depth/4, _base_irqpoll); 1961 reply_q->irq_poll_scheduled = false; 1962 reply_q->irq_line_enable = true; 1963 reply_q->os_irq = pci_irq_vector(ioc->pdev, 1964 reply_q->msix_index); 1965 } 1966 } 1967 1968 /** 1969 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1970 * @ioc: per adapter object 1971 * 1972 * Return: Whether or not MSI/X is enabled. 1973 */ 1974 static inline int 1975 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1976 { 1977 return (ioc->facts.IOCCapabilities & 1978 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1979 } 1980 1981 /** 1982 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts 1983 * @ioc: per adapter object 1984 * @poll: poll over reply descriptor pools incase interrupt for 1985 * timed-out SCSI command got delayed 1986 * Context: non-ISR context 1987 * 1988 * Called when a Task Management request has completed. 1989 */ 1990 void 1991 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll) 1992 { 1993 struct adapter_reply_queue *reply_q; 1994 1995 /* If MSIX capability is turned off 1996 * then multi-queues are not enabled 1997 */ 1998 if (!_base_is_controller_msix_enabled(ioc)) 1999 return; 2000 2001 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 2002 if (ioc->shost_recovery || ioc->remove_host || 2003 ioc->pci_error_recovery) 2004 return; 2005 /* TMs are on msix_index == 0 */ 2006 if (reply_q->msix_index == 0) 2007 continue; 2008 2009 if (reply_q->is_iouring_poll_q) { 2010 _base_process_reply_queue(reply_q); 2011 continue; 2012 } 2013 2014 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); 2015 if (reply_q->irq_poll_scheduled) { 2016 /* Calling irq_poll_disable will wait for any pending 2017 * callbacks to have completed. 2018 */ 2019 irq_poll_disable(&reply_q->irqpoll); 2020 irq_poll_enable(&reply_q->irqpoll); 2021 /* check how the scheduled poll has ended, 2022 * clean up only if necessary 2023 */ 2024 if (reply_q->irq_poll_scheduled) { 2025 reply_q->irq_poll_scheduled = false; 2026 reply_q->irq_line_enable = true; 2027 enable_irq(reply_q->os_irq); 2028 } 2029 } 2030 2031 if (poll) 2032 _base_process_reply_queue(reply_q); 2033 } 2034 } 2035 2036 /** 2037 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 2038 * @cb_idx: callback index 2039 */ 2040 void 2041 mpt3sas_base_release_callback_handler(u8 cb_idx) 2042 { 2043 mpt_callbacks[cb_idx] = NULL; 2044 } 2045 2046 /** 2047 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 2048 * @cb_func: callback function 2049 * 2050 * Return: Index of @cb_func. 2051 */ 2052 u8 2053 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 2054 { 2055 u8 cb_idx; 2056 2057 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 2058 if (mpt_callbacks[cb_idx] == NULL) 2059 break; 2060 2061 mpt_callbacks[cb_idx] = cb_func; 2062 return cb_idx; 2063 } 2064 2065 /** 2066 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 2067 */ 2068 void 2069 mpt3sas_base_initialize_callback_handler(void) 2070 { 2071 u8 cb_idx; 2072 2073 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 2074 mpt3sas_base_release_callback_handler(cb_idx); 2075 } 2076 2077 2078 /** 2079 * _base_build_zero_len_sge - build zero length sg entry 2080 * @ioc: per adapter object 2081 * @paddr: virtual address for SGE 2082 * 2083 * Create a zero length scatter gather entry to insure the IOCs hardware has 2084 * something to use if the target device goes brain dead and tries 2085 * to send data even when none is asked for. 2086 */ 2087 static void 2088 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 2089 { 2090 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 2091 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 2092 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 2093 MPI2_SGE_FLAGS_SHIFT); 2094 ioc->base_add_sg_single(paddr, flags_length, -1); 2095 } 2096 2097 /** 2098 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 2099 * @paddr: virtual address for SGE 2100 * @flags_length: SGE flags and data transfer length 2101 * @dma_addr: Physical address 2102 */ 2103 static void 2104 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 2105 { 2106 Mpi2SGESimple32_t *sgel = paddr; 2107 2108 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 2109 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 2110 sgel->FlagsLength = cpu_to_le32(flags_length); 2111 sgel->Address = cpu_to_le32(dma_addr); 2112 } 2113 2114 2115 /** 2116 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 2117 * @paddr: virtual address for SGE 2118 * @flags_length: SGE flags and data transfer length 2119 * @dma_addr: Physical address 2120 */ 2121 static void 2122 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 2123 { 2124 Mpi2SGESimple64_t *sgel = paddr; 2125 2126 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 2127 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 2128 sgel->FlagsLength = cpu_to_le32(flags_length); 2129 sgel->Address = cpu_to_le64(dma_addr); 2130 } 2131 2132 /** 2133 * _base_get_chain_buffer_tracker - obtain chain tracker 2134 * @ioc: per adapter object 2135 * @scmd: SCSI commands of the IO request 2136 * 2137 * Return: chain tracker from chain_lookup table using key as 2138 * smid and smid's chain_offset. 2139 */ 2140 static struct chain_tracker * 2141 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, 2142 struct scsi_cmnd *scmd) 2143 { 2144 struct chain_tracker *chain_req; 2145 struct scsiio_tracker *st = scsi_cmd_priv(scmd); 2146 u16 smid = st->smid; 2147 u8 chain_offset = 2148 atomic_read(&ioc->chain_lookup[smid - 1].chain_offset); 2149 2150 if (chain_offset == ioc->chains_needed_per_io) 2151 return NULL; 2152 2153 chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset]; 2154 atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset); 2155 return chain_req; 2156 } 2157 2158 2159 /** 2160 * _base_build_sg - build generic sg 2161 * @ioc: per adapter object 2162 * @psge: virtual address for SGE 2163 * @data_out_dma: physical address for WRITES 2164 * @data_out_sz: data xfer size for WRITES 2165 * @data_in_dma: physical address for READS 2166 * @data_in_sz: data xfer size for READS 2167 */ 2168 static void 2169 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 2170 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2171 size_t data_in_sz) 2172 { 2173 u32 sgl_flags; 2174 2175 if (!data_out_sz && !data_in_sz) { 2176 _base_build_zero_len_sge(ioc, psge); 2177 return; 2178 } 2179 2180 if (data_out_sz && data_in_sz) { 2181 /* WRITE sgel first */ 2182 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2183 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 2184 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2185 ioc->base_add_sg_single(psge, sgl_flags | 2186 data_out_sz, data_out_dma); 2187 2188 /* incr sgel */ 2189 psge += ioc->sge_size; 2190 2191 /* READ sgel last */ 2192 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2193 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2194 MPI2_SGE_FLAGS_END_OF_LIST); 2195 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2196 ioc->base_add_sg_single(psge, sgl_flags | 2197 data_in_sz, data_in_dma); 2198 } else if (data_out_sz) /* WRITE */ { 2199 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2200 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2201 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 2202 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2203 ioc->base_add_sg_single(psge, sgl_flags | 2204 data_out_sz, data_out_dma); 2205 } else if (data_in_sz) /* READ */ { 2206 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2207 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2208 MPI2_SGE_FLAGS_END_OF_LIST); 2209 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2210 ioc->base_add_sg_single(psge, sgl_flags | 2211 data_in_sz, data_in_dma); 2212 } 2213 } 2214 2215 /* IEEE format sgls */ 2216 2217 /** 2218 * _base_build_nvme_prp - This function is called for NVMe end devices to build 2219 * a native SGL (NVMe PRP). 2220 * @ioc: per adapter object 2221 * @smid: system request message index for getting asscociated SGL 2222 * @nvme_encap_request: the NVMe request msg frame pointer 2223 * @data_out_dma: physical address for WRITES 2224 * @data_out_sz: data xfer size for WRITES 2225 * @data_in_dma: physical address for READS 2226 * @data_in_sz: data xfer size for READS 2227 * 2228 * The native SGL is built starting in the first PRP 2229 * entry of the NVMe message (PRP1). If the data buffer is small enough to be 2230 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is 2231 * used to describe a larger data buffer. If the data buffer is too large to 2232 * describe using the two PRP entriess inside the NVMe message, then PRP1 2233 * describes the first data memory segment, and PRP2 contains a pointer to a PRP 2234 * list located elsewhere in memory to describe the remaining data memory 2235 * segments. The PRP list will be contiguous. 2236 * 2237 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 2238 * consists of a list of PRP entries to describe a number of noncontigous 2239 * physical memory segments as a single memory buffer, just as a SGL does. Note 2240 * however, that this function is only used by the IOCTL call, so the memory 2241 * given will be guaranteed to be contiguous. There is no need to translate 2242 * non-contiguous SGL into a PRP in this case. All PRPs will describe 2243 * contiguous space that is one page size each. 2244 * 2245 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 2246 * a PRP list pointer or a PRP element, depending upon the command. PRP2 2247 * contains the second PRP element if the memory being described fits within 2 2248 * PRP entries, or a PRP list pointer if the PRP spans more than two entries. 2249 * 2250 * A PRP list pointer contains the address of a PRP list, structured as a linear 2251 * array of PRP entries. Each PRP entry in this list describes a segment of 2252 * physical memory. 2253 * 2254 * Each 64-bit PRP entry comprises an address and an offset field. The address 2255 * always points at the beginning of a 4KB physical memory page, and the offset 2256 * describes where within that 4KB page the memory segment begins. Only the 2257 * first element in a PRP list may contain a non-zero offset, implying that all 2258 * memory segments following the first begin at the start of a 4KB page. 2259 * 2260 * Each PRP element normally describes 4KB of physical memory, with exceptions 2261 * for the first and last elements in the list. If the memory being described 2262 * by the list begins at a non-zero offset within the first 4KB page, then the 2263 * first PRP element will contain a non-zero offset indicating where the region 2264 * begins within the 4KB page. The last memory segment may end before the end 2265 * of the 4KB segment, depending upon the overall size of the memory being 2266 * described by the PRP list. 2267 * 2268 * Since PRP entries lack any indication of size, the overall data buffer length 2269 * is used to determine where the end of the data memory buffer is located, and 2270 * how many PRP entries are required to describe it. 2271 */ 2272 static void 2273 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2274 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, 2275 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2276 size_t data_in_sz) 2277 { 2278 int prp_size = NVME_PRP_SIZE; 2279 __le64 *prp_entry, *prp1_entry, *prp2_entry; 2280 __le64 *prp_page; 2281 dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; 2282 u32 offset, entry_len; 2283 u32 page_mask_result, page_mask; 2284 size_t length; 2285 struct mpt3sas_nvme_cmd *nvme_cmd = 2286 (void *)nvme_encap_request->NVMe_Command; 2287 2288 /* 2289 * Not all commands require a data transfer. If no data, just return 2290 * without constructing any PRP. 2291 */ 2292 if (!data_in_sz && !data_out_sz) 2293 return; 2294 prp1_entry = &nvme_cmd->prp1; 2295 prp2_entry = &nvme_cmd->prp2; 2296 prp_entry = prp1_entry; 2297 /* 2298 * For the PRP entries, use the specially allocated buffer of 2299 * contiguous memory. 2300 */ 2301 prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); 2302 prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 2303 2304 /* 2305 * Check if we are within 1 entry of a page boundary we don't 2306 * want our first entry to be a PRP List entry. 2307 */ 2308 page_mask = ioc->page_size - 1; 2309 page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; 2310 if (!page_mask_result) { 2311 /* Bump up to next page boundary. */ 2312 prp_page = (__le64 *)((u8 *)prp_page + prp_size); 2313 prp_page_dma = prp_page_dma + prp_size; 2314 } 2315 2316 /* 2317 * Set PRP physical pointer, which initially points to the current PRP 2318 * DMA memory page. 2319 */ 2320 prp_entry_dma = prp_page_dma; 2321 2322 /* Get physical address and length of the data buffer. */ 2323 if (data_in_sz) { 2324 dma_addr = data_in_dma; 2325 length = data_in_sz; 2326 } else { 2327 dma_addr = data_out_dma; 2328 length = data_out_sz; 2329 } 2330 2331 /* Loop while the length is not zero. */ 2332 while (length) { 2333 /* 2334 * Check if we need to put a list pointer here if we are at 2335 * page boundary - prp_size (8 bytes). 2336 */ 2337 page_mask_result = (prp_entry_dma + prp_size) & page_mask; 2338 if (!page_mask_result) { 2339 /* 2340 * This is the last entry in a PRP List, so we need to 2341 * put a PRP list pointer here. What this does is: 2342 * - bump the current memory pointer to the next 2343 * address, which will be the next full page. 2344 * - set the PRP Entry to point to that page. This 2345 * is now the PRP List pointer. 2346 * - bump the PRP Entry pointer the start of the 2347 * next page. Since all of this PRP memory is 2348 * contiguous, no need to get a new page - it's 2349 * just the next address. 2350 */ 2351 prp_entry_dma++; 2352 *prp_entry = cpu_to_le64(prp_entry_dma); 2353 prp_entry++; 2354 } 2355 2356 /* Need to handle if entry will be part of a page. */ 2357 offset = dma_addr & page_mask; 2358 entry_len = ioc->page_size - offset; 2359 2360 if (prp_entry == prp1_entry) { 2361 /* 2362 * Must fill in the first PRP pointer (PRP1) before 2363 * moving on. 2364 */ 2365 *prp1_entry = cpu_to_le64(dma_addr); 2366 2367 /* 2368 * Now point to the second PRP entry within the 2369 * command (PRP2). 2370 */ 2371 prp_entry = prp2_entry; 2372 } else if (prp_entry == prp2_entry) { 2373 /* 2374 * Should the PRP2 entry be a PRP List pointer or just 2375 * a regular PRP pointer? If there is more than one 2376 * more page of data, must use a PRP List pointer. 2377 */ 2378 if (length > ioc->page_size) { 2379 /* 2380 * PRP2 will contain a PRP List pointer because 2381 * more PRP's are needed with this command. The 2382 * list will start at the beginning of the 2383 * contiguous buffer. 2384 */ 2385 *prp2_entry = cpu_to_le64(prp_entry_dma); 2386 2387 /* 2388 * The next PRP Entry will be the start of the 2389 * first PRP List. 2390 */ 2391 prp_entry = prp_page; 2392 } else { 2393 /* 2394 * After this, the PRP Entries are complete. 2395 * This command uses 2 PRP's and no PRP list. 2396 */ 2397 *prp2_entry = cpu_to_le64(dma_addr); 2398 } 2399 } else { 2400 /* 2401 * Put entry in list and bump the addresses. 2402 * 2403 * After PRP1 and PRP2 are filled in, this will fill in 2404 * all remaining PRP entries in a PRP List, one per 2405 * each time through the loop. 2406 */ 2407 *prp_entry = cpu_to_le64(dma_addr); 2408 prp_entry++; 2409 prp_entry_dma++; 2410 } 2411 2412 /* 2413 * Bump the phys address of the command's data buffer by the 2414 * entry_len. 2415 */ 2416 dma_addr += entry_len; 2417 2418 /* Decrement length accounting for last partial page. */ 2419 if (entry_len > length) 2420 length = 0; 2421 else 2422 length -= entry_len; 2423 } 2424 } 2425 2426 /** 2427 * base_make_prp_nvme - Prepare PRPs (Physical Region Page) - 2428 * SGLs specific to NVMe drives only 2429 * 2430 * @ioc: per adapter object 2431 * @scmd: SCSI command from the mid-layer 2432 * @mpi_request: mpi request 2433 * @smid: msg Index 2434 * @sge_count: scatter gather element count. 2435 * 2436 * Return: true: PRPs are built 2437 * false: IEEE SGLs needs to be built 2438 */ 2439 static void 2440 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, 2441 struct scsi_cmnd *scmd, 2442 Mpi25SCSIIORequest_t *mpi_request, 2443 u16 smid, int sge_count) 2444 { 2445 int sge_len, num_prp_in_chain = 0; 2446 Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; 2447 __le64 *curr_buff; 2448 dma_addr_t msg_dma, sge_addr, offset; 2449 u32 page_mask, page_mask_result; 2450 struct scatterlist *sg_scmd; 2451 u32 first_prp_len; 2452 int data_len = scsi_bufflen(scmd); 2453 u32 nvme_pg_size; 2454 2455 nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); 2456 /* 2457 * Nvme has a very convoluted prp format. One prp is required 2458 * for each page or partial page. Driver need to split up OS sg_list 2459 * entries if it is longer than one page or cross a page 2460 * boundary. Driver also have to insert a PRP list pointer entry as 2461 * the last entry in each physical page of the PRP list. 2462 * 2463 * NOTE: The first PRP "entry" is actually placed in the first 2464 * SGL entry in the main message as IEEE 64 format. The 2nd 2465 * entry in the main message is the chain element, and the rest 2466 * of the PRP entries are built in the contiguous pcie buffer. 2467 */ 2468 page_mask = nvme_pg_size - 1; 2469 2470 /* 2471 * Native SGL is needed. 2472 * Put a chain element in main message frame that points to the first 2473 * chain buffer. 2474 * 2475 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 2476 * a native SGL. 2477 */ 2478 2479 /* Set main message chain element pointer */ 2480 main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2481 /* 2482 * For NVMe the chain element needs to be the 2nd SG entry in the main 2483 * message. 2484 */ 2485 main_chain_element = (Mpi25IeeeSgeChain64_t *) 2486 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 2487 2488 /* 2489 * For the PRP entries, use the specially allocated buffer of 2490 * contiguous memory. Normal chain buffers can't be used 2491 * because each chain buffer would need to be the size of an OS 2492 * page (4k). 2493 */ 2494 curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); 2495 msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 2496 2497 main_chain_element->Address = cpu_to_le64(msg_dma); 2498 main_chain_element->NextChainOffset = 0; 2499 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2500 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2501 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 2502 2503 /* Build first prp, sge need not to be page aligned*/ 2504 ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2505 sg_scmd = scsi_sglist(scmd); 2506 sge_addr = sg_dma_address(sg_scmd); 2507 sge_len = sg_dma_len(sg_scmd); 2508 2509 offset = sge_addr & page_mask; 2510 first_prp_len = nvme_pg_size - offset; 2511 2512 ptr_first_sgl->Address = cpu_to_le64(sge_addr); 2513 ptr_first_sgl->Length = cpu_to_le32(first_prp_len); 2514 2515 data_len -= first_prp_len; 2516 2517 if (sge_len > first_prp_len) { 2518 sge_addr += first_prp_len; 2519 sge_len -= first_prp_len; 2520 } else if (data_len && (sge_len == first_prp_len)) { 2521 sg_scmd = sg_next(sg_scmd); 2522 sge_addr = sg_dma_address(sg_scmd); 2523 sge_len = sg_dma_len(sg_scmd); 2524 } 2525 2526 for (;;) { 2527 offset = sge_addr & page_mask; 2528 2529 /* Put PRP pointer due to page boundary*/ 2530 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; 2531 if (unlikely(!page_mask_result)) { 2532 scmd_printk(KERN_NOTICE, 2533 scmd, "page boundary curr_buff: 0x%p\n", 2534 curr_buff); 2535 msg_dma += 8; 2536 *curr_buff = cpu_to_le64(msg_dma); 2537 curr_buff++; 2538 num_prp_in_chain++; 2539 } 2540 2541 *curr_buff = cpu_to_le64(sge_addr); 2542 curr_buff++; 2543 msg_dma += 8; 2544 num_prp_in_chain++; 2545 2546 sge_addr += nvme_pg_size; 2547 sge_len -= nvme_pg_size; 2548 data_len -= nvme_pg_size; 2549 2550 if (data_len <= 0) 2551 break; 2552 2553 if (sge_len > 0) 2554 continue; 2555 2556 sg_scmd = sg_next(sg_scmd); 2557 sge_addr = sg_dma_address(sg_scmd); 2558 sge_len = sg_dma_len(sg_scmd); 2559 } 2560 2561 main_chain_element->Length = 2562 cpu_to_le32(num_prp_in_chain * sizeof(u64)); 2563 return; 2564 } 2565 2566 static bool 2567 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, 2568 struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) 2569 { 2570 u32 data_length = 0; 2571 bool build_prp = true; 2572 2573 data_length = scsi_bufflen(scmd); 2574 if (pcie_device && 2575 (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) { 2576 build_prp = false; 2577 return build_prp; 2578 } 2579 2580 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 2581 * we built IEEE SGL 2582 */ 2583 if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) 2584 build_prp = false; 2585 2586 return build_prp; 2587 } 2588 2589 /** 2590 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to 2591 * determine if the driver needs to build a native SGL. If so, that native 2592 * SGL is built in the special contiguous buffers allocated especially for 2593 * PCIe SGL creation. If the driver will not build a native SGL, return 2594 * TRUE and a normal IEEE SGL will be built. Currently this routine 2595 * supports NVMe. 2596 * @ioc: per adapter object 2597 * @mpi_request: mf request pointer 2598 * @smid: system request message index 2599 * @scmd: scsi command 2600 * @pcie_device: points to the PCIe device's info 2601 * 2602 * Return: 0 if native SGL was built, 1 if no SGL was built 2603 */ 2604 static int 2605 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, 2606 Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, 2607 struct _pcie_device *pcie_device) 2608 { 2609 int sges_left; 2610 2611 /* Get the SG list pointer and info. */ 2612 sges_left = scsi_dma_map(scmd); 2613 if (sges_left < 0) 2614 return 1; 2615 2616 /* Check if we need to build a native SG list. */ 2617 if (!base_is_prp_possible(ioc, pcie_device, 2618 scmd, sges_left)) { 2619 /* We built a native SG list, just return. */ 2620 goto out; 2621 } 2622 2623 /* 2624 * Build native NVMe PRP. 2625 */ 2626 base_make_prp_nvme(ioc, scmd, mpi_request, 2627 smid, sges_left); 2628 2629 return 0; 2630 out: 2631 scsi_dma_unmap(scmd); 2632 return 1; 2633 } 2634 2635 /** 2636 * _base_add_sg_single_ieee - add sg element for IEEE format 2637 * @paddr: virtual address for SGE 2638 * @flags: SGE flags 2639 * @chain_offset: number of 128 byte elements from start of segment 2640 * @length: data transfer length 2641 * @dma_addr: Physical address 2642 */ 2643 static void 2644 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 2645 dma_addr_t dma_addr) 2646 { 2647 Mpi25IeeeSgeChain64_t *sgel = paddr; 2648 2649 sgel->Flags = flags; 2650 sgel->NextChainOffset = chain_offset; 2651 sgel->Length = cpu_to_le32(length); 2652 sgel->Address = cpu_to_le64(dma_addr); 2653 } 2654 2655 /** 2656 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 2657 * @ioc: per adapter object 2658 * @paddr: virtual address for SGE 2659 * 2660 * Create a zero length scatter gather entry to insure the IOCs hardware has 2661 * something to use if the target device goes brain dead and tries 2662 * to send data even when none is asked for. 2663 */ 2664 static void 2665 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 2666 { 2667 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2668 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2669 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 2670 2671 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 2672 } 2673 2674 /** 2675 * _base_build_sg_scmd - main sg creation routine 2676 * pcie_device is unused here! 2677 * @ioc: per adapter object 2678 * @scmd: scsi command 2679 * @smid: system request message index 2680 * @unused: unused pcie_device pointer 2681 * Context: none. 2682 * 2683 * The main routine that builds scatter gather table from a given 2684 * scsi request sent via the .queuecommand main handler. 2685 * 2686 * Return: 0 success, anything else error 2687 */ 2688 static int 2689 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 2690 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) 2691 { 2692 Mpi2SCSIIORequest_t *mpi_request; 2693 dma_addr_t chain_dma; 2694 struct scatterlist *sg_scmd; 2695 void *sg_local, *chain; 2696 u32 chain_offset; 2697 u32 chain_length; 2698 u32 chain_flags; 2699 int sges_left; 2700 u32 sges_in_segment; 2701 u32 sgl_flags; 2702 u32 sgl_flags_last_element; 2703 u32 sgl_flags_end_buffer; 2704 struct chain_tracker *chain_req; 2705 2706 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2707 2708 /* init scatter gather flags */ 2709 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 2710 if (scmd->sc_data_direction == DMA_TO_DEVICE) 2711 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 2712 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 2713 << MPI2_SGE_FLAGS_SHIFT; 2714 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 2715 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 2716 << MPI2_SGE_FLAGS_SHIFT; 2717 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2718 2719 sg_scmd = scsi_sglist(scmd); 2720 sges_left = scsi_dma_map(scmd); 2721 if (sges_left < 0) 2722 return -ENOMEM; 2723 2724 sg_local = &mpi_request->SGL; 2725 sges_in_segment = ioc->max_sges_in_main_message; 2726 if (sges_left <= sges_in_segment) 2727 goto fill_in_last_segment; 2728 2729 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 2730 (sges_in_segment * ioc->sge_size))/4; 2731 2732 /* fill in main message segment when there is a chain following */ 2733 while (sges_in_segment) { 2734 if (sges_in_segment == 1) 2735 ioc->base_add_sg_single(sg_local, 2736 sgl_flags_last_element | sg_dma_len(sg_scmd), 2737 sg_dma_address(sg_scmd)); 2738 else 2739 ioc->base_add_sg_single(sg_local, sgl_flags | 2740 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2741 sg_scmd = sg_next(sg_scmd); 2742 sg_local += ioc->sge_size; 2743 sges_left--; 2744 sges_in_segment--; 2745 } 2746 2747 /* initializing the chain flags and pointers */ 2748 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 2749 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2750 if (!chain_req) 2751 return -1; 2752 chain = chain_req->chain_buffer; 2753 chain_dma = chain_req->chain_buffer_dma; 2754 do { 2755 sges_in_segment = (sges_left <= 2756 ioc->max_sges_in_chain_message) ? sges_left : 2757 ioc->max_sges_in_chain_message; 2758 chain_offset = (sges_left == sges_in_segment) ? 2759 0 : (sges_in_segment * ioc->sge_size)/4; 2760 chain_length = sges_in_segment * ioc->sge_size; 2761 if (chain_offset) { 2762 chain_offset = chain_offset << 2763 MPI2_SGE_CHAIN_OFFSET_SHIFT; 2764 chain_length += ioc->sge_size; 2765 } 2766 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 2767 chain_length, chain_dma); 2768 sg_local = chain; 2769 if (!chain_offset) 2770 goto fill_in_last_segment; 2771 2772 /* fill in chain segments */ 2773 while (sges_in_segment) { 2774 if (sges_in_segment == 1) 2775 ioc->base_add_sg_single(sg_local, 2776 sgl_flags_last_element | 2777 sg_dma_len(sg_scmd), 2778 sg_dma_address(sg_scmd)); 2779 else 2780 ioc->base_add_sg_single(sg_local, sgl_flags | 2781 sg_dma_len(sg_scmd), 2782 sg_dma_address(sg_scmd)); 2783 sg_scmd = sg_next(sg_scmd); 2784 sg_local += ioc->sge_size; 2785 sges_left--; 2786 sges_in_segment--; 2787 } 2788 2789 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2790 if (!chain_req) 2791 return -1; 2792 chain = chain_req->chain_buffer; 2793 chain_dma = chain_req->chain_buffer_dma; 2794 } while (1); 2795 2796 2797 fill_in_last_segment: 2798 2799 /* fill the last segment */ 2800 while (sges_left) { 2801 if (sges_left == 1) 2802 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 2803 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2804 else 2805 ioc->base_add_sg_single(sg_local, sgl_flags | 2806 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2807 sg_scmd = sg_next(sg_scmd); 2808 sg_local += ioc->sge_size; 2809 sges_left--; 2810 } 2811 2812 return 0; 2813 } 2814 2815 /** 2816 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 2817 * @ioc: per adapter object 2818 * @scmd: scsi command 2819 * @smid: system request message index 2820 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be 2821 * constructed on need. 2822 * Context: none. 2823 * 2824 * The main routine that builds scatter gather table from a given 2825 * scsi request sent via the .queuecommand main handler. 2826 * 2827 * Return: 0 success, anything else error 2828 */ 2829 static int 2830 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 2831 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) 2832 { 2833 Mpi25SCSIIORequest_t *mpi_request; 2834 dma_addr_t chain_dma; 2835 struct scatterlist *sg_scmd; 2836 void *sg_local, *chain; 2837 u32 chain_offset; 2838 u32 chain_length; 2839 int sges_left; 2840 u32 sges_in_segment; 2841 u8 simple_sgl_flags; 2842 u8 simple_sgl_flags_last; 2843 u8 chain_sgl_flags; 2844 struct chain_tracker *chain_req; 2845 2846 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2847 2848 /* init scatter gather flags */ 2849 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2850 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2851 simple_sgl_flags_last = simple_sgl_flags | 2852 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2853 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2854 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2855 2856 /* Check if we need to build a native SG list. */ 2857 if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, 2858 smid, scmd, pcie_device) == 0)) { 2859 /* We built a native SG list, just return. */ 2860 return 0; 2861 } 2862 2863 sg_scmd = scsi_sglist(scmd); 2864 sges_left = scsi_dma_map(scmd); 2865 if (sges_left < 0) 2866 return -ENOMEM; 2867 2868 sg_local = &mpi_request->SGL; 2869 sges_in_segment = (ioc->request_sz - 2870 offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 2871 if (sges_left <= sges_in_segment) 2872 goto fill_in_last_segment; 2873 2874 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 2875 (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 2876 2877 /* fill in main message segment when there is a chain following */ 2878 while (sges_in_segment > 1) { 2879 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2880 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2881 sg_scmd = sg_next(sg_scmd); 2882 sg_local += ioc->sge_size_ieee; 2883 sges_left--; 2884 sges_in_segment--; 2885 } 2886 2887 /* initializing the pointers */ 2888 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2889 if (!chain_req) 2890 return -1; 2891 chain = chain_req->chain_buffer; 2892 chain_dma = chain_req->chain_buffer_dma; 2893 do { 2894 sges_in_segment = (sges_left <= 2895 ioc->max_sges_in_chain_message) ? sges_left : 2896 ioc->max_sges_in_chain_message; 2897 chain_offset = (sges_left == sges_in_segment) ? 2898 0 : sges_in_segment; 2899 chain_length = sges_in_segment * ioc->sge_size_ieee; 2900 if (chain_offset) 2901 chain_length += ioc->sge_size_ieee; 2902 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 2903 chain_offset, chain_length, chain_dma); 2904 2905 sg_local = chain; 2906 if (!chain_offset) 2907 goto fill_in_last_segment; 2908 2909 /* fill in chain segments */ 2910 while (sges_in_segment) { 2911 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2912 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2913 sg_scmd = sg_next(sg_scmd); 2914 sg_local += ioc->sge_size_ieee; 2915 sges_left--; 2916 sges_in_segment--; 2917 } 2918 2919 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2920 if (!chain_req) 2921 return -1; 2922 chain = chain_req->chain_buffer; 2923 chain_dma = chain_req->chain_buffer_dma; 2924 } while (1); 2925 2926 2927 fill_in_last_segment: 2928 2929 /* fill the last segment */ 2930 while (sges_left > 0) { 2931 if (sges_left == 1) 2932 _base_add_sg_single_ieee(sg_local, 2933 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 2934 sg_dma_address(sg_scmd)); 2935 else 2936 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2937 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2938 sg_scmd = sg_next(sg_scmd); 2939 sg_local += ioc->sge_size_ieee; 2940 sges_left--; 2941 } 2942 2943 return 0; 2944 } 2945 2946 /** 2947 * _base_build_sg_ieee - build generic sg for IEEE format 2948 * @ioc: per adapter object 2949 * @psge: virtual address for SGE 2950 * @data_out_dma: physical address for WRITES 2951 * @data_out_sz: data xfer size for WRITES 2952 * @data_in_dma: physical address for READS 2953 * @data_in_sz: data xfer size for READS 2954 */ 2955 static void 2956 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 2957 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2958 size_t data_in_sz) 2959 { 2960 u8 sgl_flags; 2961 2962 if (!data_out_sz && !data_in_sz) { 2963 _base_build_zero_len_sge_ieee(ioc, psge); 2964 return; 2965 } 2966 2967 if (data_out_sz && data_in_sz) { 2968 /* WRITE sgel first */ 2969 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2970 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2971 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2972 data_out_dma); 2973 2974 /* incr sgel */ 2975 psge += ioc->sge_size_ieee; 2976 2977 /* READ sgel last */ 2978 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2979 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2980 data_in_dma); 2981 } else if (data_out_sz) /* WRITE */ { 2982 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2983 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2984 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2985 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2986 data_out_dma); 2987 } else if (data_in_sz) /* READ */ { 2988 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2989 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2990 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2991 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2992 data_in_dma); 2993 } 2994 } 2995 2996 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 2997 2998 /** 2999 * _base_config_dma_addressing - set dma addressing 3000 * @ioc: per adapter object 3001 * @pdev: PCI device struct 3002 * 3003 * Return: 0 for success, non-zero for failure. 3004 */ 3005 static int 3006 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 3007 { 3008 struct sysinfo s; 3009 u64 coherent_dma_mask, dma_mask; 3010 3011 if (ioc->is_mcpu_endpoint || sizeof(dma_addr_t) == 4) { 3012 ioc->dma_mask = 32; 3013 coherent_dma_mask = dma_mask = DMA_BIT_MASK(32); 3014 /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ 3015 } else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { 3016 ioc->dma_mask = 63; 3017 coherent_dma_mask = dma_mask = DMA_BIT_MASK(63); 3018 } else { 3019 ioc->dma_mask = 64; 3020 coherent_dma_mask = dma_mask = DMA_BIT_MASK(64); 3021 } 3022 3023 if (ioc->use_32bit_dma) 3024 coherent_dma_mask = DMA_BIT_MASK(32); 3025 3026 if (dma_set_mask(&pdev->dev, dma_mask) || 3027 dma_set_coherent_mask(&pdev->dev, coherent_dma_mask)) 3028 return -ENODEV; 3029 3030 if (ioc->dma_mask > 32) { 3031 ioc->base_add_sg_single = &_base_add_sg_single_64; 3032 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 3033 } else { 3034 ioc->base_add_sg_single = &_base_add_sg_single_32; 3035 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 3036 } 3037 3038 si_meminfo(&s); 3039 ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 3040 ioc->dma_mask, convert_to_kb(s.totalram)); 3041 3042 return 0; 3043 } 3044 3045 /** 3046 * _base_check_enable_msix - checks MSIX capabable. 3047 * @ioc: per adapter object 3048 * 3049 * Check to see if card is capable of MSIX, and set number 3050 * of available msix vectors 3051 */ 3052 static int 3053 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 3054 { 3055 int base; 3056 u16 message_control; 3057 3058 /* Check whether controller SAS2008 B0 controller, 3059 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 3060 */ 3061 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 3062 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 3063 return -EINVAL; 3064 } 3065 3066 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 3067 if (!base) { 3068 dfailprintk(ioc, ioc_info(ioc, "msix not supported\n")); 3069 return -EINVAL; 3070 } 3071 3072 /* get msix vector count */ 3073 /* NUMA_IO not supported for older controllers */ 3074 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 3075 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 3076 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 3077 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 3078 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 3079 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 3080 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 3081 ioc->msix_vector_count = 1; 3082 else { 3083 pci_read_config_word(ioc->pdev, base + 2, &message_control); 3084 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 3085 } 3086 dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n", 3087 ioc->msix_vector_count)); 3088 return 0; 3089 } 3090 3091 /** 3092 * mpt3sas_base_free_irq - free irq 3093 * @ioc: per adapter object 3094 * 3095 * Freeing respective reply_queue from the list. 3096 */ 3097 void 3098 mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc) 3099 { 3100 unsigned int irq; 3101 struct adapter_reply_queue *reply_q, *next; 3102 3103 if (list_empty(&ioc->reply_queue_list)) 3104 return; 3105 3106 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 3107 list_del(&reply_q->list); 3108 if (reply_q->is_iouring_poll_q) { 3109 kfree(reply_q); 3110 continue; 3111 } 3112 3113 if (ioc->smp_affinity_enable) { 3114 irq = pci_irq_vector(ioc->pdev, reply_q->msix_index); 3115 irq_update_affinity_hint(irq, NULL); 3116 } 3117 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), 3118 reply_q); 3119 kfree(reply_q); 3120 } 3121 } 3122 3123 /** 3124 * _base_request_irq - request irq 3125 * @ioc: per adapter object 3126 * @index: msix index into vector table 3127 * 3128 * Inserting respective reply_queue into the list. 3129 */ 3130 static int 3131 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) 3132 { 3133 struct pci_dev *pdev = ioc->pdev; 3134 struct adapter_reply_queue *reply_q; 3135 int r, qid; 3136 3137 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 3138 if (!reply_q) { 3139 ioc_err(ioc, "unable to allocate memory %zu!\n", 3140 sizeof(struct adapter_reply_queue)); 3141 return -ENOMEM; 3142 } 3143 reply_q->ioc = ioc; 3144 reply_q->msix_index = index; 3145 3146 atomic_set(&reply_q->busy, 0); 3147 3148 if (index >= ioc->iopoll_q_start_index) { 3149 qid = index - ioc->iopoll_q_start_index; 3150 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d", 3151 ioc->driver_name, ioc->id, qid); 3152 reply_q->is_iouring_poll_q = 1; 3153 ioc->io_uring_poll_queues[qid].reply_q = reply_q; 3154 goto out; 3155 } 3156 3157 3158 if (ioc->msix_enable) 3159 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 3160 ioc->driver_name, ioc->id, index); 3161 else 3162 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 3163 ioc->driver_name, ioc->id); 3164 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, 3165 IRQF_SHARED, reply_q->name, reply_q); 3166 if (r) { 3167 pr_err("%s: unable to allocate interrupt %d!\n", 3168 reply_q->name, pci_irq_vector(pdev, index)); 3169 kfree(reply_q); 3170 return -EBUSY; 3171 } 3172 out: 3173 INIT_LIST_HEAD(&reply_q->list); 3174 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 3175 return 0; 3176 } 3177 3178 /** 3179 * _base_assign_reply_queues - assigning msix index for each cpu 3180 * @ioc: per adapter object 3181 * 3182 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 3183 */ 3184 static void 3185 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 3186 { 3187 unsigned int cpu, nr_cpus, nr_msix, index = 0, irq; 3188 struct adapter_reply_queue *reply_q; 3189 int iopoll_q_count = ioc->reply_queue_count - 3190 ioc->iopoll_q_start_index; 3191 const struct cpumask *mask; 3192 3193 if (!_base_is_controller_msix_enabled(ioc)) 3194 return; 3195 3196 if (ioc->msix_load_balance) 3197 return; 3198 3199 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 3200 3201 nr_cpus = num_online_cpus(); 3202 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 3203 ioc->facts.MaxMSIxVectors); 3204 if (!nr_msix) 3205 return; 3206 3207 if (ioc->smp_affinity_enable) { 3208 3209 /* 3210 * set irq affinity to local numa node for those irqs 3211 * corresponding to high iops queues. 3212 */ 3213 if (ioc->high_iops_queues) { 3214 mask = cpumask_of_node(dev_to_node(&ioc->pdev->dev)); 3215 for (index = 0; index < ioc->high_iops_queues; 3216 index++) { 3217 irq = pci_irq_vector(ioc->pdev, index); 3218 irq_set_affinity_and_hint(irq, mask); 3219 } 3220 } 3221 3222 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3223 const cpumask_t *mask; 3224 3225 if (reply_q->msix_index < ioc->high_iops_queues || 3226 reply_q->msix_index >= ioc->iopoll_q_start_index) 3227 continue; 3228 3229 mask = pci_irq_get_affinity(ioc->pdev, 3230 reply_q->msix_index); 3231 if (!mask) { 3232 ioc_warn(ioc, "no affinity for msi %x\n", 3233 reply_q->msix_index); 3234 goto fall_back; 3235 } 3236 3237 for_each_cpu_and(cpu, mask, cpu_online_mask) { 3238 if (cpu >= ioc->cpu_msix_table_sz) 3239 break; 3240 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 3241 } 3242 } 3243 return; 3244 } 3245 3246 fall_back: 3247 cpu = cpumask_first(cpu_online_mask); 3248 nr_msix -= (ioc->high_iops_queues - iopoll_q_count); 3249 index = 0; 3250 3251 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3252 unsigned int i, group = nr_cpus / nr_msix; 3253 3254 if (reply_q->msix_index < ioc->high_iops_queues || 3255 reply_q->msix_index >= ioc->iopoll_q_start_index) 3256 continue; 3257 3258 if (cpu >= nr_cpus) 3259 break; 3260 3261 if (index < nr_cpus % nr_msix) 3262 group++; 3263 3264 for (i = 0 ; i < group ; i++) { 3265 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 3266 cpu = cpumask_next(cpu, cpu_online_mask); 3267 } 3268 index++; 3269 } 3270 } 3271 3272 /** 3273 * _base_check_and_enable_high_iops_queues - enable high iops mode 3274 * @ioc: per adapter object 3275 * @hba_msix_vector_count: msix vectors supported by HBA 3276 * 3277 * Enable high iops queues only if 3278 * - HBA is a SEA/AERO controller and 3279 * - MSI-Xs vector supported by the HBA is 128 and 3280 * - total CPU count in the system >=16 and 3281 * - loaded driver with default max_msix_vectors module parameter and 3282 * - system booted in non kdump mode 3283 * 3284 * Return: nothing. 3285 */ 3286 static void 3287 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc, 3288 int hba_msix_vector_count) 3289 { 3290 u16 lnksta, speed; 3291 3292 /* 3293 * Disable high iops queues if io uring poll queues are enabled. 3294 */ 3295 if (perf_mode == MPT_PERF_MODE_IOPS || 3296 perf_mode == MPT_PERF_MODE_LATENCY || 3297 ioc->io_uring_poll_queues) { 3298 ioc->high_iops_queues = 0; 3299 return; 3300 } 3301 3302 if (perf_mode == MPT_PERF_MODE_DEFAULT) { 3303 3304 pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta); 3305 speed = lnksta & PCI_EXP_LNKSTA_CLS; 3306 3307 if (speed < 0x4) { 3308 ioc->high_iops_queues = 0; 3309 return; 3310 } 3311 } 3312 3313 if (!reset_devices && ioc->is_aero_ioc && 3314 hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES && 3315 num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES && 3316 max_msix_vectors == -1) 3317 ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES; 3318 else 3319 ioc->high_iops_queues = 0; 3320 } 3321 3322 /** 3323 * mpt3sas_base_disable_msix - disables msix 3324 * @ioc: per adapter object 3325 * 3326 */ 3327 void 3328 mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 3329 { 3330 if (!ioc->msix_enable) 3331 return; 3332 pci_free_irq_vectors(ioc->pdev); 3333 ioc->msix_enable = 0; 3334 kfree(ioc->io_uring_poll_queues); 3335 } 3336 3337 /** 3338 * _base_alloc_irq_vectors - allocate msix vectors 3339 * @ioc: per adapter object 3340 * 3341 */ 3342 static int 3343 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc) 3344 { 3345 int i, irq_flags = PCI_IRQ_MSIX; 3346 struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues }; 3347 struct irq_affinity *descp = &desc; 3348 /* 3349 * Don't allocate msix vectors for poll_queues. 3350 * msix_vectors is always within a range of FW supported reply queue. 3351 */ 3352 int nr_msix_vectors = ioc->iopoll_q_start_index; 3353 3354 3355 if (ioc->smp_affinity_enable) 3356 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 3357 else 3358 descp = NULL; 3359 3360 ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues, 3361 ioc->reply_queue_count, nr_msix_vectors); 3362 3363 i = pci_alloc_irq_vectors_affinity(ioc->pdev, 3364 ioc->high_iops_queues, 3365 nr_msix_vectors, irq_flags, descp); 3366 3367 return i; 3368 } 3369 3370 /** 3371 * _base_enable_msix - enables msix, failback to io_apic 3372 * @ioc: per adapter object 3373 * 3374 */ 3375 static int 3376 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 3377 { 3378 int r; 3379 int i, local_max_msix_vectors; 3380 u8 try_msix = 0; 3381 int iopoll_q_count = 0; 3382 3383 ioc->msix_load_balance = false; 3384 3385 if (msix_disable == -1 || msix_disable == 0) 3386 try_msix = 1; 3387 3388 if (!try_msix) 3389 goto try_ioapic; 3390 3391 if (_base_check_enable_msix(ioc) != 0) 3392 goto try_ioapic; 3393 3394 ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count); 3395 pr_info("\t no of cores: %d, max_msix_vectors: %d\n", 3396 ioc->cpu_count, max_msix_vectors); 3397 3398 ioc->reply_queue_count = 3399 min_t(int, ioc->cpu_count, ioc->msix_vector_count); 3400 3401 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 3402 local_max_msix_vectors = (reset_devices) ? 1 : 8; 3403 else 3404 local_max_msix_vectors = max_msix_vectors; 3405 3406 if (local_max_msix_vectors == 0) 3407 goto try_ioapic; 3408 3409 /* 3410 * Enable msix_load_balance only if combined reply queue mode is 3411 * disabled on SAS3 & above generation HBA devices. 3412 */ 3413 if (!ioc->combined_reply_queue && 3414 ioc->hba_mpi_version_belonged != MPI2_VERSION) { 3415 ioc_info(ioc, 3416 "combined ReplyQueue is off, Enabling msix load balance\n"); 3417 ioc->msix_load_balance = true; 3418 } 3419 3420 /* 3421 * smp affinity setting is not need when msix load balance 3422 * is enabled. 3423 */ 3424 if (ioc->msix_load_balance) 3425 ioc->smp_affinity_enable = 0; 3426 3427 if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1) 3428 ioc->shost->host_tagset = 0; 3429 3430 /* 3431 * Enable io uring poll queues only if host_tagset is enabled. 3432 */ 3433 if (ioc->shost->host_tagset) 3434 iopoll_q_count = poll_queues; 3435 3436 if (iopoll_q_count) { 3437 ioc->io_uring_poll_queues = kcalloc(iopoll_q_count, 3438 sizeof(struct io_uring_poll_queue), GFP_KERNEL); 3439 if (!ioc->io_uring_poll_queues) 3440 iopoll_q_count = 0; 3441 } 3442 3443 if (ioc->is_aero_ioc) 3444 _base_check_and_enable_high_iops_queues(ioc, 3445 ioc->msix_vector_count); 3446 3447 /* 3448 * Add high iops queues count to reply queue count if high iops queues 3449 * are enabled. 3450 */ 3451 ioc->reply_queue_count = min_t(int, 3452 ioc->reply_queue_count + ioc->high_iops_queues, 3453 ioc->msix_vector_count); 3454 3455 /* 3456 * Adjust the reply queue count incase reply queue count 3457 * exceeds the user provided MSIx vectors count. 3458 */ 3459 if (local_max_msix_vectors > 0) 3460 ioc->reply_queue_count = min_t(int, local_max_msix_vectors, 3461 ioc->reply_queue_count); 3462 /* 3463 * Add io uring poll queues count to reply queues count 3464 * if io uring is enabled in driver. 3465 */ 3466 if (iopoll_q_count) { 3467 if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS)) 3468 iopoll_q_count = 0; 3469 ioc->reply_queue_count = min_t(int, 3470 ioc->reply_queue_count + iopoll_q_count, 3471 ioc->msix_vector_count); 3472 } 3473 3474 /* 3475 * Starting index of io uring poll queues in reply queue list. 3476 */ 3477 ioc->iopoll_q_start_index = 3478 ioc->reply_queue_count - iopoll_q_count; 3479 3480 r = _base_alloc_irq_vectors(ioc); 3481 if (r < 0) { 3482 ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r); 3483 goto try_ioapic; 3484 } 3485 3486 /* 3487 * Adjust the reply queue count if the allocated 3488 * MSIx vectors is less then the requested number 3489 * of MSIx vectors. 3490 */ 3491 if (r < ioc->iopoll_q_start_index) { 3492 ioc->reply_queue_count = r + iopoll_q_count; 3493 ioc->iopoll_q_start_index = 3494 ioc->reply_queue_count - iopoll_q_count; 3495 } 3496 3497 ioc->msix_enable = 1; 3498 for (i = 0; i < ioc->reply_queue_count; i++) { 3499 r = _base_request_irq(ioc, i); 3500 if (r) { 3501 mpt3sas_base_free_irq(ioc); 3502 mpt3sas_base_disable_msix(ioc); 3503 goto try_ioapic; 3504 } 3505 } 3506 3507 ioc_info(ioc, "High IOPs queues : %s\n", 3508 ioc->high_iops_queues ? "enabled" : "disabled"); 3509 3510 return 0; 3511 3512 /* failback to io_apic interrupt routing */ 3513 try_ioapic: 3514 ioc->high_iops_queues = 0; 3515 ioc_info(ioc, "High IOPs queues : disabled\n"); 3516 ioc->reply_queue_count = 1; 3517 ioc->iopoll_q_start_index = ioc->reply_queue_count - 0; 3518 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); 3519 if (r < 0) { 3520 dfailprintk(ioc, 3521 ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", 3522 r)); 3523 } else 3524 r = _base_request_irq(ioc, 0); 3525 3526 return r; 3527 } 3528 3529 /** 3530 * mpt3sas_base_unmap_resources - free controller resources 3531 * @ioc: per adapter object 3532 */ 3533 static void 3534 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 3535 { 3536 struct pci_dev *pdev = ioc->pdev; 3537 3538 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 3539 3540 mpt3sas_base_free_irq(ioc); 3541 mpt3sas_base_disable_msix(ioc); 3542 3543 kfree(ioc->replyPostRegisterIndex); 3544 ioc->replyPostRegisterIndex = NULL; 3545 3546 3547 if (ioc->chip_phys) { 3548 iounmap(ioc->chip); 3549 ioc->chip_phys = 0; 3550 } 3551 3552 if (pci_is_enabled(pdev)) { 3553 pci_release_selected_regions(ioc->pdev, ioc->bars); 3554 pci_disable_device(pdev); 3555 } 3556 } 3557 3558 static int 3559 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); 3560 3561 /** 3562 * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state 3563 * and if it is in fault state then issue diag reset. 3564 * @ioc: per adapter object 3565 * 3566 * Return: 0 for success, non-zero for failure. 3567 */ 3568 int 3569 mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc) 3570 { 3571 u32 ioc_state; 3572 int rc = -EFAULT; 3573 3574 dinitprintk(ioc, pr_info("%s\n", __func__)); 3575 if (ioc->pci_error_recovery) 3576 return 0; 3577 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 3578 dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state)); 3579 3580 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 3581 mpt3sas_print_fault_code(ioc, ioc_state & 3582 MPI2_DOORBELL_DATA_MASK); 3583 mpt3sas_base_mask_interrupts(ioc); 3584 rc = _base_diag_reset(ioc); 3585 } else if ((ioc_state & MPI2_IOC_STATE_MASK) == 3586 MPI2_IOC_STATE_COREDUMP) { 3587 mpt3sas_print_coredump_info(ioc, ioc_state & 3588 MPI2_DOORBELL_DATA_MASK); 3589 mpt3sas_base_wait_for_coredump_completion(ioc, __func__); 3590 mpt3sas_base_mask_interrupts(ioc); 3591 rc = _base_diag_reset(ioc); 3592 } 3593 3594 return rc; 3595 } 3596 3597 /** 3598 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 3599 * @ioc: per adapter object 3600 * 3601 * Return: 0 for success, non-zero for failure. 3602 */ 3603 int 3604 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 3605 { 3606 struct pci_dev *pdev = ioc->pdev; 3607 u32 memap_sz; 3608 u32 pio_sz; 3609 int i, r = 0, rc; 3610 u64 pio_chip = 0; 3611 phys_addr_t chip_phys = 0; 3612 struct adapter_reply_queue *reply_q; 3613 int iopoll_q_count = 0; 3614 3615 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 3616 3617 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3618 if (pci_enable_device_mem(pdev)) { 3619 ioc_warn(ioc, "pci_enable_device_mem: failed\n"); 3620 ioc->bars = 0; 3621 return -ENODEV; 3622 } 3623 3624 3625 if (pci_request_selected_regions(pdev, ioc->bars, 3626 ioc->driver_name)) { 3627 ioc_warn(ioc, "pci_request_selected_regions: failed\n"); 3628 ioc->bars = 0; 3629 r = -ENODEV; 3630 goto out_fail; 3631 } 3632 3633 pci_set_master(pdev); 3634 3635 3636 if (_base_config_dma_addressing(ioc, pdev) != 0) { 3637 ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev)); 3638 r = -ENODEV; 3639 goto out_fail; 3640 } 3641 3642 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 3643 (!memap_sz || !pio_sz); i++) { 3644 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 3645 if (pio_sz) 3646 continue; 3647 pio_chip = (u64)pci_resource_start(pdev, i); 3648 pio_sz = pci_resource_len(pdev, i); 3649 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3650 if (memap_sz) 3651 continue; 3652 ioc->chip_phys = pci_resource_start(pdev, i); 3653 chip_phys = ioc->chip_phys; 3654 memap_sz = pci_resource_len(pdev, i); 3655 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 3656 } 3657 } 3658 3659 if (ioc->chip == NULL) { 3660 ioc_err(ioc, 3661 "unable to map adapter memory! or resource not found\n"); 3662 r = -EINVAL; 3663 goto out_fail; 3664 } 3665 3666 mpt3sas_base_mask_interrupts(ioc); 3667 3668 r = _base_get_ioc_facts(ioc); 3669 if (r) { 3670 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 3671 if (rc || (_base_get_ioc_facts(ioc))) 3672 goto out_fail; 3673 } 3674 3675 if (!ioc->rdpq_array_enable_assigned) { 3676 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 3677 ioc->rdpq_array_enable_assigned = 1; 3678 } 3679 3680 r = _base_enable_msix(ioc); 3681 if (r) 3682 goto out_fail; 3683 3684 iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index; 3685 for (i = 0; i < iopoll_q_count; i++) { 3686 atomic_set(&ioc->io_uring_poll_queues[i].busy, 0); 3687 atomic_set(&ioc->io_uring_poll_queues[i].pause, 0); 3688 } 3689 3690 if (!ioc->is_driver_loading) 3691 _base_init_irqpolls(ioc); 3692 /* Use the Combined reply queue feature only for SAS3 C0 & higher 3693 * revision HBAs and also only when reply queue count is greater than 8 3694 */ 3695 if (ioc->combined_reply_queue) { 3696 /* Determine the Supplemental Reply Post Host Index Registers 3697 * Addresse. Supplemental Reply Post Host Index Registers 3698 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 3699 * each register is at offset bytes of 3700 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 3701 */ 3702 ioc->replyPostRegisterIndex = kcalloc( 3703 ioc->combined_reply_index_count, 3704 sizeof(resource_size_t *), GFP_KERNEL); 3705 if (!ioc->replyPostRegisterIndex) { 3706 ioc_err(ioc, 3707 "allocation for replyPostRegisterIndex failed!\n"); 3708 r = -ENOMEM; 3709 goto out_fail; 3710 } 3711 3712 for (i = 0; i < ioc->combined_reply_index_count; i++) { 3713 ioc->replyPostRegisterIndex[i] = 3714 (resource_size_t __iomem *) 3715 ((u8 __force *)&ioc->chip->Doorbell + 3716 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 3717 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 3718 } 3719 } 3720 3721 if (ioc->is_warpdrive) { 3722 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 3723 &ioc->chip->ReplyPostHostIndex; 3724 3725 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 3726 ioc->reply_post_host_index[i] = 3727 (resource_size_t __iomem *) 3728 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 3729 * 4))); 3730 } 3731 3732 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3733 if (reply_q->msix_index >= ioc->iopoll_q_start_index) { 3734 pr_info("%s: enabled: index: %d\n", 3735 reply_q->name, reply_q->msix_index); 3736 continue; 3737 } 3738 3739 pr_info("%s: %s enabled: IRQ %d\n", 3740 reply_q->name, 3741 ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC", 3742 pci_irq_vector(ioc->pdev, reply_q->msix_index)); 3743 } 3744 3745 ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n", 3746 &chip_phys, ioc->chip, memap_sz); 3747 ioc_info(ioc, "ioport(0x%016llx), size(%d)\n", 3748 (unsigned long long)pio_chip, pio_sz); 3749 3750 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 3751 pci_save_state(pdev); 3752 return 0; 3753 3754 out_fail: 3755 mpt3sas_base_unmap_resources(ioc); 3756 return r; 3757 } 3758 3759 /** 3760 * mpt3sas_base_get_msg_frame - obtain request mf pointer 3761 * @ioc: per adapter object 3762 * @smid: system request message index(smid zero is invalid) 3763 * 3764 * Return: virt pointer to message frame. 3765 */ 3766 void * 3767 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3768 { 3769 return (void *)(ioc->request + (smid * ioc->request_sz)); 3770 } 3771 3772 /** 3773 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 3774 * @ioc: per adapter object 3775 * @smid: system request message index 3776 * 3777 * Return: virt pointer to sense buffer. 3778 */ 3779 void * 3780 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3781 { 3782 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 3783 } 3784 3785 /** 3786 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 3787 * @ioc: per adapter object 3788 * @smid: system request message index 3789 * 3790 * Return: phys pointer to the low 32bit address of the sense buffer. 3791 */ 3792 __le32 3793 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3794 { 3795 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 3796 SCSI_SENSE_BUFFERSIZE)); 3797 } 3798 3799 /** 3800 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr 3801 * @ioc: per adapter object 3802 * @smid: system request message index 3803 * 3804 * Return: virt pointer to a PCIe SGL. 3805 */ 3806 void * 3807 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3808 { 3809 return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl); 3810 } 3811 3812 /** 3813 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr 3814 * @ioc: per adapter object 3815 * @smid: system request message index 3816 * 3817 * Return: phys pointer to the address of the PCIe buffer. 3818 */ 3819 dma_addr_t 3820 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3821 { 3822 return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma; 3823 } 3824 3825 /** 3826 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 3827 * @ioc: per adapter object 3828 * @phys_addr: lower 32 physical addr of the reply 3829 * 3830 * Converts 32bit lower physical addr into a virt address. 3831 */ 3832 void * 3833 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 3834 { 3835 if (!phys_addr) 3836 return NULL; 3837 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 3838 } 3839 3840 /** 3841 * _base_get_msix_index - get the msix index 3842 * @ioc: per adapter object 3843 * @scmd: scsi_cmnd object 3844 * 3845 * Return: msix index of general reply queues, 3846 * i.e. reply queue on which IO request's reply 3847 * should be posted by the HBA firmware. 3848 */ 3849 static inline u8 3850 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc, 3851 struct scsi_cmnd *scmd) 3852 { 3853 /* Enables reply_queue load balancing */ 3854 if (ioc->msix_load_balance) 3855 return ioc->reply_queue_count ? 3856 base_mod64(atomic64_add_return(1, 3857 &ioc->total_io_cnt), ioc->reply_queue_count) : 0; 3858 3859 if (scmd && ioc->shost->nr_hw_queues > 1) { 3860 u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); 3861 3862 return blk_mq_unique_tag_to_hwq(tag) + 3863 ioc->high_iops_queues; 3864 } 3865 3866 return ioc->cpu_msix_table[raw_smp_processor_id()]; 3867 } 3868 3869 /** 3870 * _base_get_high_iops_msix_index - get the msix index of 3871 * high iops queues 3872 * @ioc: per adapter object 3873 * @scmd: scsi_cmnd object 3874 * 3875 * Return: msix index of high iops reply queues. 3876 * i.e. high iops reply queue on which IO request's 3877 * reply should be posted by the HBA firmware. 3878 */ 3879 static inline u8 3880 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc, 3881 struct scsi_cmnd *scmd) 3882 { 3883 /** 3884 * Round robin the IO interrupts among the high iops 3885 * reply queues in terms of batch count 16 when outstanding 3886 * IOs on the target device is >=8. 3887 */ 3888 3889 if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH) 3890 return base_mod64(( 3891 atomic64_add_return(1, &ioc->high_iops_outstanding) / 3892 MPT3SAS_HIGH_IOPS_BATCH_COUNT), 3893 MPT3SAS_HIGH_IOPS_REPLY_QUEUES); 3894 3895 return _base_get_msix_index(ioc, scmd); 3896 } 3897 3898 /** 3899 * mpt3sas_base_get_smid - obtain a free smid from internal queue 3900 * @ioc: per adapter object 3901 * @cb_idx: callback index 3902 * 3903 * Return: smid (zero is invalid) 3904 */ 3905 u16 3906 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3907 { 3908 unsigned long flags; 3909 struct request_tracker *request; 3910 u16 smid; 3911 3912 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3913 if (list_empty(&ioc->internal_free_list)) { 3914 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3915 ioc_err(ioc, "%s: smid not available\n", __func__); 3916 return 0; 3917 } 3918 3919 request = list_entry(ioc->internal_free_list.next, 3920 struct request_tracker, tracker_list); 3921 request->cb_idx = cb_idx; 3922 smid = request->smid; 3923 list_del(&request->tracker_list); 3924 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3925 return smid; 3926 } 3927 3928 /** 3929 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 3930 * @ioc: per adapter object 3931 * @cb_idx: callback index 3932 * @scmd: pointer to scsi command object 3933 * 3934 * Return: smid (zero is invalid) 3935 */ 3936 u16 3937 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 3938 struct scsi_cmnd *scmd) 3939 { 3940 struct scsiio_tracker *request = scsi_cmd_priv(scmd); 3941 u16 smid; 3942 u32 tag, unique_tag; 3943 3944 unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); 3945 tag = blk_mq_unique_tag_to_tag(unique_tag); 3946 3947 /* 3948 * Store hw queue number corresponding to the tag. 3949 * This hw queue number is used later to determine 3950 * the unique_tag using the logic below. This unique_tag 3951 * is used to retrieve the scmd pointer corresponding 3952 * to tag using scsi_host_find_tag() API. 3953 * 3954 * tag = smid - 1; 3955 * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag; 3956 */ 3957 ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag); 3958 3959 smid = tag + 1; 3960 request->cb_idx = cb_idx; 3961 request->smid = smid; 3962 request->scmd = scmd; 3963 INIT_LIST_HEAD(&request->chain_list); 3964 return smid; 3965 } 3966 3967 /** 3968 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 3969 * @ioc: per adapter object 3970 * @cb_idx: callback index 3971 * 3972 * Return: smid (zero is invalid) 3973 */ 3974 u16 3975 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3976 { 3977 unsigned long flags; 3978 struct request_tracker *request; 3979 u16 smid; 3980 3981 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3982 if (list_empty(&ioc->hpr_free_list)) { 3983 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3984 return 0; 3985 } 3986 3987 request = list_entry(ioc->hpr_free_list.next, 3988 struct request_tracker, tracker_list); 3989 request->cb_idx = cb_idx; 3990 smid = request->smid; 3991 list_del(&request->tracker_list); 3992 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3993 return smid; 3994 } 3995 3996 static void 3997 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc) 3998 { 3999 /* 4000 * See _wait_for_commands_to_complete() call with regards to this code. 4001 */ 4002 if (ioc->shost_recovery && ioc->pending_io_count) { 4003 ioc->pending_io_count = scsi_host_busy(ioc->shost); 4004 if (ioc->pending_io_count == 0) 4005 wake_up(&ioc->reset_wq); 4006 } 4007 } 4008 4009 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, 4010 struct scsiio_tracker *st) 4011 { 4012 if (WARN_ON(st->smid == 0)) 4013 return; 4014 st->cb_idx = 0xFF; 4015 st->direct_io = 0; 4016 st->scmd = NULL; 4017 atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0); 4018 st->smid = 0; 4019 } 4020 4021 /** 4022 * mpt3sas_base_free_smid - put smid back on free_list 4023 * @ioc: per adapter object 4024 * @smid: system request message index 4025 */ 4026 void 4027 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4028 { 4029 unsigned long flags; 4030 int i; 4031 4032 if (smid < ioc->hi_priority_smid) { 4033 struct scsiio_tracker *st; 4034 void *request; 4035 4036 st = _get_st_from_smid(ioc, smid); 4037 if (!st) { 4038 _base_recovery_check(ioc); 4039 return; 4040 } 4041 4042 /* Clear MPI request frame */ 4043 request = mpt3sas_base_get_msg_frame(ioc, smid); 4044 memset(request, 0, ioc->request_sz); 4045 4046 mpt3sas_base_clear_st(ioc, st); 4047 _base_recovery_check(ioc); 4048 ioc->io_queue_num[smid - 1] = 0; 4049 return; 4050 } 4051 4052 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 4053 if (smid < ioc->internal_smid) { 4054 /* hi-priority */ 4055 i = smid - ioc->hi_priority_smid; 4056 ioc->hpr_lookup[i].cb_idx = 0xFF; 4057 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 4058 } else if (smid <= ioc->hba_queue_depth) { 4059 /* internal queue */ 4060 i = smid - ioc->internal_smid; 4061 ioc->internal_lookup[i].cb_idx = 0xFF; 4062 list_add(&ioc->internal_lookup[i].tracker_list, 4063 &ioc->internal_free_list); 4064 } 4065 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 4066 } 4067 4068 /** 4069 * _base_mpi_ep_writeq - 32 bit write to MMIO 4070 * @b: data payload 4071 * @addr: address in MMIO space 4072 * @writeq_lock: spin lock 4073 * 4074 * This special handling for MPI EP to take care of 32 bit 4075 * environment where its not quarenteed to send the entire word 4076 * in one transfer. 4077 */ 4078 static inline void 4079 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr, 4080 spinlock_t *writeq_lock) 4081 { 4082 unsigned long flags; 4083 4084 spin_lock_irqsave(writeq_lock, flags); 4085 __raw_writel((u32)(b), addr); 4086 __raw_writel((u32)(b >> 32), (addr + 4)); 4087 spin_unlock_irqrestore(writeq_lock, flags); 4088 } 4089 4090 /** 4091 * _base_writeq - 64 bit write to MMIO 4092 * @b: data payload 4093 * @addr: address in MMIO space 4094 * @writeq_lock: spin lock 4095 * 4096 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 4097 * care of 32 bit environment where its not quarenteed to send the entire word 4098 * in one transfer. 4099 */ 4100 #if defined(writeq) && defined(CONFIG_64BIT) 4101 static inline void 4102 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 4103 { 4104 wmb(); 4105 __raw_writeq(b, addr); 4106 barrier(); 4107 } 4108 #else 4109 static inline void 4110 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 4111 { 4112 _base_mpi_ep_writeq(b, addr, writeq_lock); 4113 } 4114 #endif 4115 4116 /** 4117 * _base_set_and_get_msix_index - get the msix index and assign to msix_io 4118 * variable of scsi tracker 4119 * @ioc: per adapter object 4120 * @smid: system request message index 4121 * 4122 * Return: msix index. 4123 */ 4124 static u8 4125 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4126 { 4127 struct scsiio_tracker *st = NULL; 4128 4129 if (smid < ioc->hi_priority_smid) 4130 st = _get_st_from_smid(ioc, smid); 4131 4132 if (st == NULL) 4133 return _base_get_msix_index(ioc, NULL); 4134 4135 st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd); 4136 return st->msix_io; 4137 } 4138 4139 /** 4140 * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware 4141 * @ioc: per adapter object 4142 * @smid: system request message index 4143 * @handle: device handle 4144 */ 4145 static void 4146 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, 4147 u16 smid, u16 handle) 4148 { 4149 Mpi2RequestDescriptorUnion_t descriptor; 4150 u64 *request = (u64 *)&descriptor; 4151 void *mpi_req_iomem; 4152 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4153 4154 _clone_sg_entries(ioc, (void *) mfp, smid); 4155 mpi_req_iomem = (void __force *)ioc->chip + 4156 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 4157 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4158 ioc->request_sz); 4159 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4160 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4161 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4162 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4163 descriptor.SCSIIO.LMID = 0; 4164 _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4165 &ioc->scsi_lookup_lock); 4166 } 4167 4168 /** 4169 * _base_put_smid_scsi_io - send SCSI_IO request to firmware 4170 * @ioc: per adapter object 4171 * @smid: system request message index 4172 * @handle: device handle 4173 */ 4174 static void 4175 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 4176 { 4177 Mpi2RequestDescriptorUnion_t descriptor; 4178 u64 *request = (u64 *)&descriptor; 4179 4180 4181 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4182 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4183 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4184 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4185 descriptor.SCSIIO.LMID = 0; 4186 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4187 &ioc->scsi_lookup_lock); 4188 } 4189 4190 /** 4191 * _base_put_smid_fast_path - send fast path request to firmware 4192 * @ioc: per adapter object 4193 * @smid: system request message index 4194 * @handle: device handle 4195 */ 4196 static void 4197 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4198 u16 handle) 4199 { 4200 Mpi2RequestDescriptorUnion_t descriptor; 4201 u64 *request = (u64 *)&descriptor; 4202 4203 descriptor.SCSIIO.RequestFlags = 4204 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 4205 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4206 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4207 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4208 descriptor.SCSIIO.LMID = 0; 4209 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4210 &ioc->scsi_lookup_lock); 4211 } 4212 4213 /** 4214 * _base_put_smid_hi_priority - send Task Management request to firmware 4215 * @ioc: per adapter object 4216 * @smid: system request message index 4217 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 4218 */ 4219 static void 4220 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4221 u16 msix_task) 4222 { 4223 Mpi2RequestDescriptorUnion_t descriptor; 4224 void *mpi_req_iomem; 4225 u64 *request; 4226 4227 if (ioc->is_mcpu_endpoint) { 4228 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4229 4230 /* TBD 256 is offset within sys register. */ 4231 mpi_req_iomem = (void __force *)ioc->chip 4232 + MPI_FRAME_START_OFFSET 4233 + (smid * ioc->request_sz); 4234 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4235 ioc->request_sz); 4236 } 4237 4238 request = (u64 *)&descriptor; 4239 4240 descriptor.HighPriority.RequestFlags = 4241 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 4242 descriptor.HighPriority.MSIxIndex = msix_task; 4243 descriptor.HighPriority.SMID = cpu_to_le16(smid); 4244 descriptor.HighPriority.LMID = 0; 4245 descriptor.HighPriority.Reserved1 = 0; 4246 if (ioc->is_mcpu_endpoint) 4247 _base_mpi_ep_writeq(*request, 4248 &ioc->chip->RequestDescriptorPostLow, 4249 &ioc->scsi_lookup_lock); 4250 else 4251 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4252 &ioc->scsi_lookup_lock); 4253 } 4254 4255 /** 4256 * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to 4257 * firmware 4258 * @ioc: per adapter object 4259 * @smid: system request message index 4260 */ 4261 void 4262 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4263 { 4264 Mpi2RequestDescriptorUnion_t descriptor; 4265 u64 *request = (u64 *)&descriptor; 4266 4267 descriptor.Default.RequestFlags = 4268 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED; 4269 descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4270 descriptor.Default.SMID = cpu_to_le16(smid); 4271 descriptor.Default.LMID = 0; 4272 descriptor.Default.DescriptorTypeDependent = 0; 4273 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4274 &ioc->scsi_lookup_lock); 4275 } 4276 4277 /** 4278 * _base_put_smid_default - Default, primarily used for config pages 4279 * @ioc: per adapter object 4280 * @smid: system request message index 4281 */ 4282 static void 4283 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4284 { 4285 Mpi2RequestDescriptorUnion_t descriptor; 4286 void *mpi_req_iomem; 4287 u64 *request; 4288 4289 if (ioc->is_mcpu_endpoint) { 4290 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4291 4292 _clone_sg_entries(ioc, (void *) mfp, smid); 4293 /* TBD 256 is offset within sys register */ 4294 mpi_req_iomem = (void __force *)ioc->chip + 4295 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 4296 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4297 ioc->request_sz); 4298 } 4299 request = (u64 *)&descriptor; 4300 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 4301 descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4302 descriptor.Default.SMID = cpu_to_le16(smid); 4303 descriptor.Default.LMID = 0; 4304 descriptor.Default.DescriptorTypeDependent = 0; 4305 if (ioc->is_mcpu_endpoint) 4306 _base_mpi_ep_writeq(*request, 4307 &ioc->chip->RequestDescriptorPostLow, 4308 &ioc->scsi_lookup_lock); 4309 else 4310 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4311 &ioc->scsi_lookup_lock); 4312 } 4313 4314 /** 4315 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using 4316 * Atomic Request Descriptor 4317 * @ioc: per adapter object 4318 * @smid: system request message index 4319 * @handle: device handle, unused in this function, for function type match 4320 * 4321 * Return: nothing. 4322 */ 4323 static void 4324 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4325 u16 handle) 4326 { 4327 Mpi26AtomicRequestDescriptor_t descriptor; 4328 u32 *request = (u32 *)&descriptor; 4329 4330 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4331 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4332 descriptor.SMID = cpu_to_le16(smid); 4333 4334 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4335 } 4336 4337 /** 4338 * _base_put_smid_fast_path_atomic - send fast path request to firmware 4339 * using Atomic Request Descriptor 4340 * @ioc: per adapter object 4341 * @smid: system request message index 4342 * @handle: device handle, unused in this function, for function type match 4343 * Return: nothing 4344 */ 4345 static void 4346 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4347 u16 handle) 4348 { 4349 Mpi26AtomicRequestDescriptor_t descriptor; 4350 u32 *request = (u32 *)&descriptor; 4351 4352 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 4353 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4354 descriptor.SMID = cpu_to_le16(smid); 4355 4356 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4357 } 4358 4359 /** 4360 * _base_put_smid_hi_priority_atomic - send Task Management request to 4361 * firmware using Atomic Request Descriptor 4362 * @ioc: per adapter object 4363 * @smid: system request message index 4364 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 4365 * 4366 * Return: nothing. 4367 */ 4368 static void 4369 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4370 u16 msix_task) 4371 { 4372 Mpi26AtomicRequestDescriptor_t descriptor; 4373 u32 *request = (u32 *)&descriptor; 4374 4375 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 4376 descriptor.MSIxIndex = msix_task; 4377 descriptor.SMID = cpu_to_le16(smid); 4378 4379 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4380 } 4381 4382 /** 4383 * _base_put_smid_default_atomic - Default, primarily used for config pages 4384 * use Atomic Request Descriptor 4385 * @ioc: per adapter object 4386 * @smid: system request message index 4387 * 4388 * Return: nothing. 4389 */ 4390 static void 4391 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4392 { 4393 Mpi26AtomicRequestDescriptor_t descriptor; 4394 u32 *request = (u32 *)&descriptor; 4395 4396 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 4397 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4398 descriptor.SMID = cpu_to_le16(smid); 4399 4400 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4401 } 4402 4403 /** 4404 * _base_display_OEMs_branding - Display branding string 4405 * @ioc: per adapter object 4406 */ 4407 static void 4408 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 4409 { 4410 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 4411 return; 4412 4413 switch (ioc->pdev->subsystem_vendor) { 4414 case PCI_VENDOR_ID_INTEL: 4415 switch (ioc->pdev->device) { 4416 case MPI2_MFGPAGE_DEVID_SAS2008: 4417 switch (ioc->pdev->subsystem_device) { 4418 case MPT2SAS_INTEL_RMS2LL080_SSDID: 4419 ioc_info(ioc, "%s\n", 4420 MPT2SAS_INTEL_RMS2LL080_BRANDING); 4421 break; 4422 case MPT2SAS_INTEL_RMS2LL040_SSDID: 4423 ioc_info(ioc, "%s\n", 4424 MPT2SAS_INTEL_RMS2LL040_BRANDING); 4425 break; 4426 case MPT2SAS_INTEL_SSD910_SSDID: 4427 ioc_info(ioc, "%s\n", 4428 MPT2SAS_INTEL_SSD910_BRANDING); 4429 break; 4430 default: 4431 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4432 ioc->pdev->subsystem_device); 4433 break; 4434 } 4435 break; 4436 case MPI2_MFGPAGE_DEVID_SAS2308_2: 4437 switch (ioc->pdev->subsystem_device) { 4438 case MPT2SAS_INTEL_RS25GB008_SSDID: 4439 ioc_info(ioc, "%s\n", 4440 MPT2SAS_INTEL_RS25GB008_BRANDING); 4441 break; 4442 case MPT2SAS_INTEL_RMS25JB080_SSDID: 4443 ioc_info(ioc, "%s\n", 4444 MPT2SAS_INTEL_RMS25JB080_BRANDING); 4445 break; 4446 case MPT2SAS_INTEL_RMS25JB040_SSDID: 4447 ioc_info(ioc, "%s\n", 4448 MPT2SAS_INTEL_RMS25JB040_BRANDING); 4449 break; 4450 case MPT2SAS_INTEL_RMS25KB080_SSDID: 4451 ioc_info(ioc, "%s\n", 4452 MPT2SAS_INTEL_RMS25KB080_BRANDING); 4453 break; 4454 case MPT2SAS_INTEL_RMS25KB040_SSDID: 4455 ioc_info(ioc, "%s\n", 4456 MPT2SAS_INTEL_RMS25KB040_BRANDING); 4457 break; 4458 case MPT2SAS_INTEL_RMS25LB040_SSDID: 4459 ioc_info(ioc, "%s\n", 4460 MPT2SAS_INTEL_RMS25LB040_BRANDING); 4461 break; 4462 case MPT2SAS_INTEL_RMS25LB080_SSDID: 4463 ioc_info(ioc, "%s\n", 4464 MPT2SAS_INTEL_RMS25LB080_BRANDING); 4465 break; 4466 default: 4467 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4468 ioc->pdev->subsystem_device); 4469 break; 4470 } 4471 break; 4472 case MPI25_MFGPAGE_DEVID_SAS3008: 4473 switch (ioc->pdev->subsystem_device) { 4474 case MPT3SAS_INTEL_RMS3JC080_SSDID: 4475 ioc_info(ioc, "%s\n", 4476 MPT3SAS_INTEL_RMS3JC080_BRANDING); 4477 break; 4478 4479 case MPT3SAS_INTEL_RS3GC008_SSDID: 4480 ioc_info(ioc, "%s\n", 4481 MPT3SAS_INTEL_RS3GC008_BRANDING); 4482 break; 4483 case MPT3SAS_INTEL_RS3FC044_SSDID: 4484 ioc_info(ioc, "%s\n", 4485 MPT3SAS_INTEL_RS3FC044_BRANDING); 4486 break; 4487 case MPT3SAS_INTEL_RS3UC080_SSDID: 4488 ioc_info(ioc, "%s\n", 4489 MPT3SAS_INTEL_RS3UC080_BRANDING); 4490 break; 4491 default: 4492 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4493 ioc->pdev->subsystem_device); 4494 break; 4495 } 4496 break; 4497 default: 4498 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4499 ioc->pdev->subsystem_device); 4500 break; 4501 } 4502 break; 4503 case PCI_VENDOR_ID_DELL: 4504 switch (ioc->pdev->device) { 4505 case MPI2_MFGPAGE_DEVID_SAS2008: 4506 switch (ioc->pdev->subsystem_device) { 4507 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 4508 ioc_info(ioc, "%s\n", 4509 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 4510 break; 4511 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 4512 ioc_info(ioc, "%s\n", 4513 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 4514 break; 4515 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 4516 ioc_info(ioc, "%s\n", 4517 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 4518 break; 4519 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 4520 ioc_info(ioc, "%s\n", 4521 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 4522 break; 4523 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 4524 ioc_info(ioc, "%s\n", 4525 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 4526 break; 4527 case MPT2SAS_DELL_PERC_H200_SSDID: 4528 ioc_info(ioc, "%s\n", 4529 MPT2SAS_DELL_PERC_H200_BRANDING); 4530 break; 4531 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 4532 ioc_info(ioc, "%s\n", 4533 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 4534 break; 4535 default: 4536 ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 4537 ioc->pdev->subsystem_device); 4538 break; 4539 } 4540 break; 4541 case MPI25_MFGPAGE_DEVID_SAS3008: 4542 switch (ioc->pdev->subsystem_device) { 4543 case MPT3SAS_DELL_12G_HBA_SSDID: 4544 ioc_info(ioc, "%s\n", 4545 MPT3SAS_DELL_12G_HBA_BRANDING); 4546 break; 4547 default: 4548 ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 4549 ioc->pdev->subsystem_device); 4550 break; 4551 } 4552 break; 4553 default: 4554 ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n", 4555 ioc->pdev->subsystem_device); 4556 break; 4557 } 4558 break; 4559 case PCI_VENDOR_ID_CISCO: 4560 switch (ioc->pdev->device) { 4561 case MPI25_MFGPAGE_DEVID_SAS3008: 4562 switch (ioc->pdev->subsystem_device) { 4563 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 4564 ioc_info(ioc, "%s\n", 4565 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 4566 break; 4567 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 4568 ioc_info(ioc, "%s\n", 4569 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 4570 break; 4571 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 4572 ioc_info(ioc, "%s\n", 4573 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 4574 break; 4575 default: 4576 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 4577 ioc->pdev->subsystem_device); 4578 break; 4579 } 4580 break; 4581 case MPI25_MFGPAGE_DEVID_SAS3108_1: 4582 switch (ioc->pdev->subsystem_device) { 4583 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 4584 ioc_info(ioc, "%s\n", 4585 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 4586 break; 4587 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 4588 ioc_info(ioc, "%s\n", 4589 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING); 4590 break; 4591 default: 4592 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 4593 ioc->pdev->subsystem_device); 4594 break; 4595 } 4596 break; 4597 default: 4598 ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n", 4599 ioc->pdev->subsystem_device); 4600 break; 4601 } 4602 break; 4603 case MPT2SAS_HP_3PAR_SSVID: 4604 switch (ioc->pdev->device) { 4605 case MPI2_MFGPAGE_DEVID_SAS2004: 4606 switch (ioc->pdev->subsystem_device) { 4607 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 4608 ioc_info(ioc, "%s\n", 4609 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 4610 break; 4611 default: 4612 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 4613 ioc->pdev->subsystem_device); 4614 break; 4615 } 4616 break; 4617 case MPI2_MFGPAGE_DEVID_SAS2308_2: 4618 switch (ioc->pdev->subsystem_device) { 4619 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 4620 ioc_info(ioc, "%s\n", 4621 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 4622 break; 4623 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 4624 ioc_info(ioc, "%s\n", 4625 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 4626 break; 4627 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 4628 ioc_info(ioc, "%s\n", 4629 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 4630 break; 4631 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 4632 ioc_info(ioc, "%s\n", 4633 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 4634 break; 4635 default: 4636 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 4637 ioc->pdev->subsystem_device); 4638 break; 4639 } 4640 break; 4641 default: 4642 ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n", 4643 ioc->pdev->subsystem_device); 4644 break; 4645 } 4646 break; 4647 default: 4648 break; 4649 } 4650 } 4651 4652 /** 4653 * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg 4654 * version from FW Image Header. 4655 * @ioc: per adapter object 4656 * 4657 * Return: 0 for success, non-zero for failure. 4658 */ 4659 static int 4660 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc) 4661 { 4662 Mpi2FWImageHeader_t *fw_img_hdr; 4663 Mpi26ComponentImageHeader_t *cmp_img_hdr; 4664 Mpi25FWUploadRequest_t *mpi_request; 4665 Mpi2FWUploadReply_t mpi_reply; 4666 int r = 0, issue_diag_reset = 0; 4667 u32 package_version = 0; 4668 void *fwpkg_data = NULL; 4669 dma_addr_t fwpkg_data_dma; 4670 u16 smid, ioc_status; 4671 size_t data_length; 4672 4673 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 4674 4675 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4676 ioc_err(ioc, "%s: internal command already in use\n", __func__); 4677 return -EAGAIN; 4678 } 4679 4680 data_length = sizeof(Mpi2FWImageHeader_t); 4681 fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length, 4682 &fwpkg_data_dma, GFP_KERNEL); 4683 if (!fwpkg_data) { 4684 ioc_err(ioc, 4685 "Memory allocation for fwpkg data failed at %s:%d/%s()!\n", 4686 __FILE__, __LINE__, __func__); 4687 return -ENOMEM; 4688 } 4689 4690 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4691 if (!smid) { 4692 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 4693 r = -EAGAIN; 4694 goto out; 4695 } 4696 4697 ioc->base_cmds.status = MPT3_CMD_PENDING; 4698 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4699 ioc->base_cmds.smid = smid; 4700 memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t)); 4701 mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD; 4702 mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH; 4703 mpi_request->ImageSize = cpu_to_le32(data_length); 4704 ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma, 4705 data_length); 4706 init_completion(&ioc->base_cmds.done); 4707 ioc->put_smid_default(ioc, smid); 4708 /* Wait for 15 seconds */ 4709 wait_for_completion_timeout(&ioc->base_cmds.done, 4710 FW_IMG_HDR_READ_TIMEOUT*HZ); 4711 ioc_info(ioc, "%s: complete\n", __func__); 4712 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4713 ioc_err(ioc, "%s: timeout\n", __func__); 4714 _debug_dump_mf(mpi_request, 4715 sizeof(Mpi25FWUploadRequest_t)/4); 4716 issue_diag_reset = 1; 4717 } else { 4718 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t)); 4719 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) { 4720 memcpy(&mpi_reply, ioc->base_cmds.reply, 4721 sizeof(Mpi2FWUploadReply_t)); 4722 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 4723 MPI2_IOCSTATUS_MASK; 4724 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 4725 fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data; 4726 if (le32_to_cpu(fw_img_hdr->Signature) == 4727 MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) { 4728 cmp_img_hdr = 4729 (Mpi26ComponentImageHeader_t *) 4730 (fwpkg_data); 4731 package_version = 4732 le32_to_cpu( 4733 cmp_img_hdr->ApplicationSpecific); 4734 } else 4735 package_version = 4736 le32_to_cpu( 4737 fw_img_hdr->PackageVersion.Word); 4738 if (package_version) 4739 ioc_info(ioc, 4740 "FW Package Ver(%02d.%02d.%02d.%02d)\n", 4741 ((package_version) & 0xFF000000) >> 24, 4742 ((package_version) & 0x00FF0000) >> 16, 4743 ((package_version) & 0x0000FF00) >> 8, 4744 (package_version) & 0x000000FF); 4745 } else { 4746 _debug_dump_mf(&mpi_reply, 4747 sizeof(Mpi2FWUploadReply_t)/4); 4748 } 4749 } 4750 } 4751 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4752 out: 4753 if (fwpkg_data) 4754 dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data, 4755 fwpkg_data_dma); 4756 if (issue_diag_reset) { 4757 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) 4758 return -EFAULT; 4759 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) 4760 return -EFAULT; 4761 r = -EAGAIN; 4762 } 4763 return r; 4764 } 4765 4766 /** 4767 * _base_display_ioc_capabilities - Display IOC's capabilities. 4768 * @ioc: per adapter object 4769 */ 4770 static void 4771 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 4772 { 4773 int i = 0; 4774 char desc[17] = {0}; 4775 u32 iounit_pg1_flags; 4776 4777 strncpy(desc, ioc->manu_pg0.ChipName, 16); 4778 ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x)\n", 4779 desc, 4780 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 4781 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 4782 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 4783 ioc->facts.FWVersion.Word & 0x000000FF, 4784 ioc->pdev->revision); 4785 4786 _base_display_OEMs_branding(ioc); 4787 4788 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 4789 pr_info("%sNVMe", i ? "," : ""); 4790 i++; 4791 } 4792 4793 ioc_info(ioc, "Protocol=("); 4794 4795 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 4796 pr_cont("Initiator"); 4797 i++; 4798 } 4799 4800 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 4801 pr_cont("%sTarget", i ? "," : ""); 4802 i++; 4803 } 4804 4805 i = 0; 4806 pr_cont("), Capabilities=("); 4807 4808 if (!ioc->hide_ir_msg) { 4809 if (ioc->facts.IOCCapabilities & 4810 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 4811 pr_cont("Raid"); 4812 i++; 4813 } 4814 } 4815 4816 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 4817 pr_cont("%sTLR", i ? "," : ""); 4818 i++; 4819 } 4820 4821 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 4822 pr_cont("%sMulticast", i ? "," : ""); 4823 i++; 4824 } 4825 4826 if (ioc->facts.IOCCapabilities & 4827 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 4828 pr_cont("%sBIDI Target", i ? "," : ""); 4829 i++; 4830 } 4831 4832 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 4833 pr_cont("%sEEDP", i ? "," : ""); 4834 i++; 4835 } 4836 4837 if (ioc->facts.IOCCapabilities & 4838 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 4839 pr_cont("%sSnapshot Buffer", i ? "," : ""); 4840 i++; 4841 } 4842 4843 if (ioc->facts.IOCCapabilities & 4844 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 4845 pr_cont("%sDiag Trace Buffer", i ? "," : ""); 4846 i++; 4847 } 4848 4849 if (ioc->facts.IOCCapabilities & 4850 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 4851 pr_cont("%sDiag Extended Buffer", i ? "," : ""); 4852 i++; 4853 } 4854 4855 if (ioc->facts.IOCCapabilities & 4856 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 4857 pr_cont("%sTask Set Full", i ? "," : ""); 4858 i++; 4859 } 4860 4861 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 4862 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 4863 pr_cont("%sNCQ", i ? "," : ""); 4864 i++; 4865 } 4866 4867 pr_cont(")\n"); 4868 } 4869 4870 /** 4871 * mpt3sas_base_update_missing_delay - change the missing delay timers 4872 * @ioc: per adapter object 4873 * @device_missing_delay: amount of time till device is reported missing 4874 * @io_missing_delay: interval IO is returned when there is a missing device 4875 * 4876 * Passed on the command line, this function will modify the device missing 4877 * delay, as well as the io missing delay. This should be called at driver 4878 * load time. 4879 */ 4880 void 4881 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 4882 u16 device_missing_delay, u8 io_missing_delay) 4883 { 4884 u16 dmd, dmd_new, dmd_orignal; 4885 u8 io_missing_delay_original; 4886 u16 sz; 4887 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 4888 Mpi2ConfigReply_t mpi_reply; 4889 u8 num_phys = 0; 4890 u16 ioc_status; 4891 4892 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 4893 if (!num_phys) 4894 return; 4895 4896 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 4897 sizeof(Mpi2SasIOUnit1PhyData_t)); 4898 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 4899 if (!sas_iounit_pg1) { 4900 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4901 __FILE__, __LINE__, __func__); 4902 goto out; 4903 } 4904 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 4905 sas_iounit_pg1, sz))) { 4906 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4907 __FILE__, __LINE__, __func__); 4908 goto out; 4909 } 4910 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 4911 MPI2_IOCSTATUS_MASK; 4912 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4913 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4914 __FILE__, __LINE__, __func__); 4915 goto out; 4916 } 4917 4918 /* device missing delay */ 4919 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 4920 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4921 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4922 else 4923 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4924 dmd_orignal = dmd; 4925 if (device_missing_delay > 0x7F) { 4926 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 4927 device_missing_delay; 4928 dmd = dmd / 16; 4929 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 4930 } else 4931 dmd = device_missing_delay; 4932 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 4933 4934 /* io missing delay */ 4935 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 4936 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 4937 4938 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 4939 sz)) { 4940 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4941 dmd_new = (dmd & 4942 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4943 else 4944 dmd_new = 4945 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4946 ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n", 4947 dmd_orignal, dmd_new); 4948 ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n", 4949 io_missing_delay_original, 4950 io_missing_delay); 4951 ioc->device_missing_delay = dmd_new; 4952 ioc->io_missing_delay = io_missing_delay; 4953 } 4954 4955 out: 4956 kfree(sas_iounit_pg1); 4957 } 4958 4959 /** 4960 * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields 4961 * according to performance mode. 4962 * @ioc : per adapter object 4963 * 4964 * Return: zero on success; otherwise return EAGAIN error code asking the 4965 * caller to retry. 4966 */ 4967 static int 4968 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc) 4969 { 4970 Mpi2IOCPage1_t ioc_pg1; 4971 Mpi2ConfigReply_t mpi_reply; 4972 int rc; 4973 4974 rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy); 4975 if (rc) 4976 return rc; 4977 memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t)); 4978 4979 switch (perf_mode) { 4980 case MPT_PERF_MODE_DEFAULT: 4981 case MPT_PERF_MODE_BALANCED: 4982 if (ioc->high_iops_queues) { 4983 ioc_info(ioc, 4984 "Enable interrupt coalescing only for first\t" 4985 "%d reply queues\n", 4986 MPT3SAS_HIGH_IOPS_REPLY_QUEUES); 4987 /* 4988 * If 31st bit is zero then interrupt coalescing is 4989 * enabled for all reply descriptor post queues. 4990 * If 31st bit is set to one then user can 4991 * enable/disable interrupt coalescing on per reply 4992 * descriptor post queue group(8) basis. So to enable 4993 * interrupt coalescing only on first reply descriptor 4994 * post queue group 31st bit and zero th bit is enabled. 4995 */ 4996 ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 | 4997 ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1)); 4998 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 4999 if (rc) 5000 return rc; 5001 ioc_info(ioc, "performance mode: balanced\n"); 5002 return 0; 5003 } 5004 fallthrough; 5005 case MPT_PERF_MODE_LATENCY: 5006 /* 5007 * Enable interrupt coalescing on all reply queues 5008 * with timeout value 0xA 5009 */ 5010 ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa); 5011 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); 5012 ioc_pg1.ProductSpecific = 0; 5013 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 5014 if (rc) 5015 return rc; 5016 ioc_info(ioc, "performance mode: latency\n"); 5017 break; 5018 case MPT_PERF_MODE_IOPS: 5019 /* 5020 * Enable interrupt coalescing on all reply queues. 5021 */ 5022 ioc_info(ioc, 5023 "performance mode: iops with coalescing timeout: 0x%x\n", 5024 le32_to_cpu(ioc_pg1.CoalescingTimeout)); 5025 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); 5026 ioc_pg1.ProductSpecific = 0; 5027 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 5028 if (rc) 5029 return rc; 5030 break; 5031 } 5032 return 0; 5033 } 5034 5035 /** 5036 * _base_get_event_diag_triggers - get event diag trigger values from 5037 * persistent pages 5038 * @ioc : per adapter object 5039 * 5040 * Return: nothing. 5041 */ 5042 static int 5043 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5044 { 5045 Mpi26DriverTriggerPage2_t trigger_pg2; 5046 struct SL_WH_EVENT_TRIGGER_T *event_tg; 5047 MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg; 5048 Mpi2ConfigReply_t mpi_reply; 5049 int r = 0, i = 0; 5050 u16 count = 0; 5051 u16 ioc_status; 5052 5053 r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply, 5054 &trigger_pg2); 5055 if (r) 5056 return r; 5057 5058 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5059 MPI2_IOCSTATUS_MASK; 5060 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5061 dinitprintk(ioc, 5062 ioc_err(ioc, 5063 "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n", 5064 __func__, ioc_status)); 5065 return 0; 5066 } 5067 5068 if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) { 5069 count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger); 5070 count = min_t(u16, NUM_VALID_ENTRIES, count); 5071 ioc->diag_trigger_event.ValidEntries = count; 5072 5073 event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0]; 5074 mpi_event_tg = &trigger_pg2.MPIEventTriggers[0]; 5075 for (i = 0; i < count; i++) { 5076 event_tg->EventValue = le16_to_cpu( 5077 mpi_event_tg->MPIEventCode); 5078 event_tg->LogEntryQualifier = le16_to_cpu( 5079 mpi_event_tg->MPIEventCodeSpecific); 5080 event_tg++; 5081 mpi_event_tg++; 5082 } 5083 } 5084 return 0; 5085 } 5086 5087 /** 5088 * _base_get_scsi_diag_triggers - get scsi diag trigger values from 5089 * persistent pages 5090 * @ioc : per adapter object 5091 * 5092 * Return: 0 on success; otherwise return failure status. 5093 */ 5094 static int 5095 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5096 { 5097 Mpi26DriverTriggerPage3_t trigger_pg3; 5098 struct SL_WH_SCSI_TRIGGER_T *scsi_tg; 5099 MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg; 5100 Mpi2ConfigReply_t mpi_reply; 5101 int r = 0, i = 0; 5102 u16 count = 0; 5103 u16 ioc_status; 5104 5105 r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply, 5106 &trigger_pg3); 5107 if (r) 5108 return r; 5109 5110 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5111 MPI2_IOCSTATUS_MASK; 5112 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5113 dinitprintk(ioc, 5114 ioc_err(ioc, 5115 "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n", 5116 __func__, ioc_status)); 5117 return 0; 5118 } 5119 5120 if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) { 5121 count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger); 5122 count = min_t(u16, NUM_VALID_ENTRIES, count); 5123 ioc->diag_trigger_scsi.ValidEntries = count; 5124 5125 scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0]; 5126 mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0]; 5127 for (i = 0; i < count; i++) { 5128 scsi_tg->ASCQ = mpi_scsi_tg->ASCQ; 5129 scsi_tg->ASC = mpi_scsi_tg->ASC; 5130 scsi_tg->SenseKey = mpi_scsi_tg->SenseKey; 5131 5132 scsi_tg++; 5133 mpi_scsi_tg++; 5134 } 5135 } 5136 return 0; 5137 } 5138 5139 /** 5140 * _base_get_mpi_diag_triggers - get mpi diag trigger values from 5141 * persistent pages 5142 * @ioc : per adapter object 5143 * 5144 * Return: 0 on success; otherwise return failure status. 5145 */ 5146 static int 5147 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5148 { 5149 Mpi26DriverTriggerPage4_t trigger_pg4; 5150 struct SL_WH_MPI_TRIGGER_T *status_tg; 5151 MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg; 5152 Mpi2ConfigReply_t mpi_reply; 5153 int r = 0, i = 0; 5154 u16 count = 0; 5155 u16 ioc_status; 5156 5157 r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply, 5158 &trigger_pg4); 5159 if (r) 5160 return r; 5161 5162 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5163 MPI2_IOCSTATUS_MASK; 5164 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5165 dinitprintk(ioc, 5166 ioc_err(ioc, 5167 "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n", 5168 __func__, ioc_status)); 5169 return 0; 5170 } 5171 5172 if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) { 5173 count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger); 5174 count = min_t(u16, NUM_VALID_ENTRIES, count); 5175 ioc->diag_trigger_mpi.ValidEntries = count; 5176 5177 status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0]; 5178 mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0]; 5179 5180 for (i = 0; i < count; i++) { 5181 status_tg->IOCStatus = le16_to_cpu( 5182 mpi_status_tg->IOCStatus); 5183 status_tg->IocLogInfo = le32_to_cpu( 5184 mpi_status_tg->LogInfo); 5185 5186 status_tg++; 5187 mpi_status_tg++; 5188 } 5189 } 5190 return 0; 5191 } 5192 5193 /** 5194 * _base_get_master_diag_triggers - get master diag trigger values from 5195 * persistent pages 5196 * @ioc : per adapter object 5197 * 5198 * Return: nothing. 5199 */ 5200 static int 5201 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5202 { 5203 Mpi26DriverTriggerPage1_t trigger_pg1; 5204 Mpi2ConfigReply_t mpi_reply; 5205 int r; 5206 u16 ioc_status; 5207 5208 r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply, 5209 &trigger_pg1); 5210 if (r) 5211 return r; 5212 5213 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5214 MPI2_IOCSTATUS_MASK; 5215 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5216 dinitprintk(ioc, 5217 ioc_err(ioc, 5218 "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n", 5219 __func__, ioc_status)); 5220 return 0; 5221 } 5222 5223 if (le16_to_cpu(trigger_pg1.NumMasterTrigger)) 5224 ioc->diag_trigger_master.MasterData |= 5225 le32_to_cpu( 5226 trigger_pg1.MasterTriggers[0].MasterTriggerFlags); 5227 return 0; 5228 } 5229 5230 /** 5231 * _base_check_for_trigger_pages_support - checks whether HBA FW supports 5232 * driver trigger pages or not 5233 * @ioc : per adapter object 5234 * @trigger_flags : address where trigger page0's TriggerFlags value is copied 5235 * 5236 * Return: trigger flags mask if HBA FW supports driver trigger pages; 5237 * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or 5238 * return EAGAIN if diag reset occurred due to FW fault and asking the 5239 * caller to retry the command. 5240 * 5241 */ 5242 static int 5243 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags) 5244 { 5245 Mpi26DriverTriggerPage0_t trigger_pg0; 5246 int r = 0; 5247 Mpi2ConfigReply_t mpi_reply; 5248 u16 ioc_status; 5249 5250 r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply, 5251 &trigger_pg0); 5252 if (r) 5253 return r; 5254 5255 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5256 MPI2_IOCSTATUS_MASK; 5257 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 5258 return -EFAULT; 5259 5260 *trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags); 5261 return 0; 5262 } 5263 5264 /** 5265 * _base_get_diag_triggers - Retrieve diag trigger values from 5266 * persistent pages. 5267 * @ioc : per adapter object 5268 * 5269 * Return: zero on success; otherwise return EAGAIN error codes 5270 * asking the caller to retry. 5271 */ 5272 static int 5273 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5274 { 5275 int trigger_flags; 5276 int r; 5277 5278 /* 5279 * Default setting of master trigger. 5280 */ 5281 ioc->diag_trigger_master.MasterData = 5282 (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET); 5283 5284 r = _base_check_for_trigger_pages_support(ioc, &trigger_flags); 5285 if (r) { 5286 if (r == -EAGAIN) 5287 return r; 5288 /* 5289 * Don't go for error handling when FW doesn't support 5290 * driver trigger pages. 5291 */ 5292 return 0; 5293 } 5294 5295 ioc->supports_trigger_pages = 1; 5296 5297 /* 5298 * Retrieve master diag trigger values from driver trigger pg1 5299 * if master trigger bit enabled in TriggerFlags. 5300 */ 5301 if ((u16)trigger_flags & 5302 MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) { 5303 r = _base_get_master_diag_triggers(ioc); 5304 if (r) 5305 return r; 5306 } 5307 5308 /* 5309 * Retrieve event diag trigger values from driver trigger pg2 5310 * if event trigger bit enabled in TriggerFlags. 5311 */ 5312 if ((u16)trigger_flags & 5313 MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) { 5314 r = _base_get_event_diag_triggers(ioc); 5315 if (r) 5316 return r; 5317 } 5318 5319 /* 5320 * Retrieve scsi diag trigger values from driver trigger pg3 5321 * if scsi trigger bit enabled in TriggerFlags. 5322 */ 5323 if ((u16)trigger_flags & 5324 MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) { 5325 r = _base_get_scsi_diag_triggers(ioc); 5326 if (r) 5327 return r; 5328 } 5329 /* 5330 * Retrieve mpi error diag trigger values from driver trigger pg4 5331 * if loginfo trigger bit enabled in TriggerFlags. 5332 */ 5333 if ((u16)trigger_flags & 5334 MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) { 5335 r = _base_get_mpi_diag_triggers(ioc); 5336 if (r) 5337 return r; 5338 } 5339 return 0; 5340 } 5341 5342 /** 5343 * _base_update_diag_trigger_pages - Update the driver trigger pages after 5344 * online FW update, in case updated FW supports driver 5345 * trigger pages. 5346 * @ioc : per adapter object 5347 * 5348 * Return: nothing. 5349 */ 5350 static void 5351 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc) 5352 { 5353 5354 if (ioc->diag_trigger_master.MasterData) 5355 mpt3sas_config_update_driver_trigger_pg1(ioc, 5356 &ioc->diag_trigger_master, 1); 5357 5358 if (ioc->diag_trigger_event.ValidEntries) 5359 mpt3sas_config_update_driver_trigger_pg2(ioc, 5360 &ioc->diag_trigger_event, 1); 5361 5362 if (ioc->diag_trigger_scsi.ValidEntries) 5363 mpt3sas_config_update_driver_trigger_pg3(ioc, 5364 &ioc->diag_trigger_scsi, 1); 5365 5366 if (ioc->diag_trigger_mpi.ValidEntries) 5367 mpt3sas_config_update_driver_trigger_pg4(ioc, 5368 &ioc->diag_trigger_mpi, 1); 5369 } 5370 5371 /** 5372 * _base_assign_fw_reported_qd - Get FW reported QD for SAS/SATA devices. 5373 * - On failure set default QD values. 5374 * @ioc : per adapter object 5375 * 5376 * Returns 0 for success, non-zero for failure. 5377 * 5378 */ 5379 static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc) 5380 { 5381 Mpi2ConfigReply_t mpi_reply; 5382 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 5383 Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1; 5384 u16 depth; 5385 int sz; 5386 int rc = 0; 5387 5388 ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH; 5389 ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH; 5390 ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH; 5391 ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH; 5392 if (!ioc->is_gen35_ioc) 5393 goto out; 5394 /* sas iounit page 1 */ 5395 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData); 5396 sas_iounit_pg1 = kzalloc(sizeof(Mpi2SasIOUnitPage1_t), GFP_KERNEL); 5397 if (!sas_iounit_pg1) { 5398 pr_err("%s: failure at %s:%d/%s()!\n", 5399 ioc->name, __FILE__, __LINE__, __func__); 5400 return rc; 5401 } 5402 rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 5403 sas_iounit_pg1, sz); 5404 if (rc) { 5405 pr_err("%s: failure at %s:%d/%s()!\n", 5406 ioc->name, __FILE__, __LINE__, __func__); 5407 goto out; 5408 } 5409 5410 depth = le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth); 5411 ioc->max_wideport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH); 5412 5413 depth = le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth); 5414 ioc->max_narrowport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH); 5415 5416 depth = sas_iounit_pg1->SATAMaxQDepth; 5417 ioc->max_sata_qd = (depth ? depth : MPT3SAS_SATA_QUEUE_DEPTH); 5418 5419 /* pcie iounit page 1 */ 5420 rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply, 5421 &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t)); 5422 if (rc) { 5423 pr_err("%s: failure at %s:%d/%s()!\n", 5424 ioc->name, __FILE__, __LINE__, __func__); 5425 goto out; 5426 } 5427 ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ? 5428 (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) : 5429 MPT3SAS_NVME_QUEUE_DEPTH; 5430 out: 5431 dinitprintk(ioc, pr_err( 5432 "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n", 5433 ioc->max_wideport_qd, ioc->max_narrowport_qd, 5434 ioc->max_sata_qd, ioc->max_nvme_qd)); 5435 kfree(sas_iounit_pg1); 5436 return rc; 5437 } 5438 5439 /** 5440 * mpt3sas_atto_validate_nvram - validate the ATTO nvram read from mfg pg1 5441 * 5442 * @ioc : per adapter object 5443 * @n : ptr to the ATTO nvram structure 5444 * Return: 0 for success, non-zero for failure. 5445 */ 5446 static int 5447 mpt3sas_atto_validate_nvram(struct MPT3SAS_ADAPTER *ioc, 5448 struct ATTO_SAS_NVRAM *n) 5449 { 5450 int r = -EINVAL; 5451 union ATTO_SAS_ADDRESS *s1; 5452 u32 len; 5453 u8 *pb; 5454 u8 ckSum; 5455 5456 /* validate nvram checksum */ 5457 pb = (u8 *) n; 5458 ckSum = ATTO_SASNVR_CKSUM_SEED; 5459 len = sizeof(struct ATTO_SAS_NVRAM); 5460 5461 while (len--) 5462 ckSum = ckSum + pb[len]; 5463 5464 if (ckSum) { 5465 ioc_err(ioc, "Invalid ATTO NVRAM checksum\n"); 5466 return r; 5467 } 5468 5469 s1 = (union ATTO_SAS_ADDRESS *) n->SasAddr; 5470 5471 if (n->Signature[0] != 'E' 5472 || n->Signature[1] != 'S' 5473 || n->Signature[2] != 'A' 5474 || n->Signature[3] != 'S') 5475 ioc_err(ioc, "Invalid ATTO NVRAM signature\n"); 5476 else if (n->Version > ATTO_SASNVR_VERSION) 5477 ioc_info(ioc, "Invalid ATTO NVRAM version"); 5478 else if ((n->SasAddr[7] & (ATTO_SAS_ADDR_ALIGN - 1)) 5479 || s1->b[0] != 0x50 5480 || s1->b[1] != 0x01 5481 || s1->b[2] != 0x08 5482 || (s1->b[3] & 0xF0) != 0x60 5483 || ((s1->b[3] & 0x0F) | le32_to_cpu(s1->d[1])) == 0) { 5484 ioc_err(ioc, "Invalid ATTO SAS address\n"); 5485 } else 5486 r = 0; 5487 return r; 5488 } 5489 5490 /** 5491 * mpt3sas_atto_get_sas_addr - get the ATTO SAS address from mfg page 1 5492 * 5493 * @ioc : per adapter object 5494 * @*sas_addr : return sas address 5495 * Return: 0 for success, non-zero for failure. 5496 */ 5497 static int 5498 mpt3sas_atto_get_sas_addr(struct MPT3SAS_ADAPTER *ioc, union ATTO_SAS_ADDRESS *sas_addr) 5499 { 5500 Mpi2ManufacturingPage1_t mfg_pg1; 5501 Mpi2ConfigReply_t mpi_reply; 5502 struct ATTO_SAS_NVRAM *nvram; 5503 int r; 5504 __be64 addr; 5505 5506 r = mpt3sas_config_get_manufacturing_pg1(ioc, &mpi_reply, &mfg_pg1); 5507 if (r) { 5508 ioc_err(ioc, "Failed to read manufacturing page 1\n"); 5509 return r; 5510 } 5511 5512 /* validate nvram */ 5513 nvram = (struct ATTO_SAS_NVRAM *) mfg_pg1.VPD; 5514 r = mpt3sas_atto_validate_nvram(ioc, nvram); 5515 if (r) 5516 return r; 5517 5518 addr = *((__be64 *) nvram->SasAddr); 5519 sas_addr->q = cpu_to_le64(be64_to_cpu(addr)); 5520 return r; 5521 } 5522 5523 /** 5524 * mpt3sas_atto_init - perform initializaion for ATTO branded 5525 * adapter. 5526 * @ioc : per adapter object 5527 *5 5528 * Return: 0 for success, non-zero for failure. 5529 */ 5530 static int 5531 mpt3sas_atto_init(struct MPT3SAS_ADAPTER *ioc) 5532 { 5533 int sz = 0; 5534 Mpi2BiosPage4_t *bios_pg4 = NULL; 5535 Mpi2ConfigReply_t mpi_reply; 5536 int r; 5537 int ix; 5538 union ATTO_SAS_ADDRESS sas_addr; 5539 union ATTO_SAS_ADDRESS temp; 5540 union ATTO_SAS_ADDRESS bias; 5541 5542 r = mpt3sas_atto_get_sas_addr(ioc, &sas_addr); 5543 if (r) 5544 return r; 5545 5546 /* get header first to get size */ 5547 r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, NULL, 0); 5548 if (r) { 5549 ioc_err(ioc, "Failed to read ATTO bios page 4 header.\n"); 5550 return r; 5551 } 5552 5553 sz = mpi_reply.Header.PageLength * sizeof(u32); 5554 bios_pg4 = kzalloc(sz, GFP_KERNEL); 5555 if (!bios_pg4) { 5556 ioc_err(ioc, "Failed to allocate memory for ATTO bios page.\n"); 5557 return -ENOMEM; 5558 } 5559 5560 /* read bios page 4 */ 5561 r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, bios_pg4, sz); 5562 if (r) { 5563 ioc_err(ioc, "Failed to read ATTO bios page 4\n"); 5564 goto out; 5565 } 5566 5567 /* Update bios page 4 with the ATTO WWID */ 5568 bias.q = sas_addr.q; 5569 bias.b[7] += ATTO_SAS_ADDR_DEVNAME_BIAS; 5570 5571 for (ix = 0; ix < bios_pg4->NumPhys; ix++) { 5572 temp.q = sas_addr.q; 5573 temp.b[7] += ix; 5574 bios_pg4->Phy[ix].ReassignmentWWID = temp.q; 5575 bios_pg4->Phy[ix].ReassignmentDeviceName = bias.q; 5576 } 5577 r = mpt3sas_config_set_bios_pg4(ioc, &mpi_reply, bios_pg4, sz); 5578 5579 out: 5580 kfree(bios_pg4); 5581 return r; 5582 } 5583 5584 /** 5585 * _base_static_config_pages - static start of day config pages 5586 * @ioc: per adapter object 5587 */ 5588 static int 5589 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 5590 { 5591 Mpi2ConfigReply_t mpi_reply; 5592 u32 iounit_pg1_flags; 5593 int tg_flags = 0; 5594 int rc; 5595 ioc->nvme_abort_timeout = 30; 5596 5597 rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, 5598 &ioc->manu_pg0); 5599 if (rc) 5600 return rc; 5601 if (ioc->ir_firmware) { 5602 rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 5603 &ioc->manu_pg10); 5604 if (rc) 5605 return rc; 5606 } 5607 5608 if (ioc->pdev->vendor == MPI2_MFGPAGE_VENDORID_ATTO) { 5609 rc = mpt3sas_atto_init(ioc); 5610 if (rc) 5611 return rc; 5612 } 5613 5614 /* 5615 * Ensure correct T10 PI operation if vendor left EEDPTagMode 5616 * flag unset in NVDATA. 5617 */ 5618 rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, 5619 &ioc->manu_pg11); 5620 if (rc) 5621 return rc; 5622 if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) { 5623 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 5624 ioc->name); 5625 ioc->manu_pg11.EEDPTagMode &= ~0x3; 5626 ioc->manu_pg11.EEDPTagMode |= 0x1; 5627 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 5628 &ioc->manu_pg11); 5629 } 5630 if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK) 5631 ioc->tm_custom_handling = 1; 5632 else { 5633 ioc->tm_custom_handling = 0; 5634 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT) 5635 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT; 5636 else if (ioc->manu_pg11.NVMeAbortTO > 5637 NVME_TASK_ABORT_MAX_TIMEOUT) 5638 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT; 5639 else 5640 ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO; 5641 } 5642 ioc->time_sync_interval = 5643 ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK; 5644 if (ioc->time_sync_interval) { 5645 if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK) 5646 ioc->time_sync_interval = 5647 ioc->time_sync_interval * SECONDS_PER_HOUR; 5648 else 5649 ioc->time_sync_interval = 5650 ioc->time_sync_interval * SECONDS_PER_MIN; 5651 dinitprintk(ioc, ioc_info(ioc, 5652 "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n", 5653 ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval & 5654 MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute")); 5655 } else { 5656 if (ioc->is_gen35_ioc) 5657 ioc_warn(ioc, 5658 "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n"); 5659 } 5660 rc = _base_assign_fw_reported_qd(ioc); 5661 if (rc) 5662 return rc; 5663 5664 /* 5665 * ATTO doesn't use bios page 2 and 3 for bios settings. 5666 */ 5667 if (ioc->pdev->vendor == MPI2_MFGPAGE_VENDORID_ATTO) 5668 ioc->bios_pg3.BiosVersion = 0; 5669 else { 5670 rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 5671 if (rc) 5672 return rc; 5673 rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 5674 if (rc) 5675 return rc; 5676 } 5677 5678 rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 5679 if (rc) 5680 return rc; 5681 rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 5682 if (rc) 5683 return rc; 5684 rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 5685 if (rc) 5686 return rc; 5687 rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 5688 if (rc) 5689 return rc; 5690 _base_display_ioc_capabilities(ioc); 5691 5692 /* 5693 * Enable task_set_full handling in iounit_pg1 when the 5694 * facts capabilities indicate that its supported. 5695 */ 5696 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 5697 if ((ioc->facts.IOCCapabilities & 5698 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 5699 iounit_pg1_flags &= 5700 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 5701 else 5702 iounit_pg1_flags |= 5703 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 5704 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 5705 rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 5706 if (rc) 5707 return rc; 5708 5709 if (ioc->iounit_pg8.NumSensors) 5710 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 5711 if (ioc->is_aero_ioc) { 5712 rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc); 5713 if (rc) 5714 return rc; 5715 } 5716 if (ioc->is_gen35_ioc) { 5717 if (ioc->is_driver_loading) { 5718 rc = _base_get_diag_triggers(ioc); 5719 if (rc) 5720 return rc; 5721 } else { 5722 /* 5723 * In case of online HBA FW update operation, 5724 * check whether updated FW supports the driver trigger 5725 * pages or not. 5726 * - If previous FW has not supported driver trigger 5727 * pages and newer FW supports them then update these 5728 * pages with current diag trigger values. 5729 * - If previous FW has supported driver trigger pages 5730 * and new FW doesn't support them then disable 5731 * support_trigger_pages flag. 5732 */ 5733 _base_check_for_trigger_pages_support(ioc, &tg_flags); 5734 if (!ioc->supports_trigger_pages && tg_flags != -EFAULT) 5735 _base_update_diag_trigger_pages(ioc); 5736 else if (ioc->supports_trigger_pages && 5737 tg_flags == -EFAULT) 5738 ioc->supports_trigger_pages = 0; 5739 } 5740 } 5741 return 0; 5742 } 5743 5744 /** 5745 * mpt3sas_free_enclosure_list - release memory 5746 * @ioc: per adapter object 5747 * 5748 * Free memory allocated during enclosure add. 5749 */ 5750 void 5751 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc) 5752 { 5753 struct _enclosure_node *enclosure_dev, *enclosure_dev_next; 5754 5755 /* Free enclosure list */ 5756 list_for_each_entry_safe(enclosure_dev, 5757 enclosure_dev_next, &ioc->enclosure_list, list) { 5758 list_del(&enclosure_dev->list); 5759 kfree(enclosure_dev); 5760 } 5761 } 5762 5763 /** 5764 * _base_release_memory_pools - release memory 5765 * @ioc: per adapter object 5766 * 5767 * Free memory allocated from _base_allocate_memory_pools. 5768 */ 5769 static void 5770 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 5771 { 5772 int i = 0; 5773 int j = 0; 5774 int dma_alloc_count = 0; 5775 struct chain_tracker *ct; 5776 int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; 5777 5778 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 5779 5780 if (ioc->request) { 5781 dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz, 5782 ioc->request, ioc->request_dma); 5783 dexitprintk(ioc, 5784 ioc_info(ioc, "request_pool(0x%p): free\n", 5785 ioc->request)); 5786 ioc->request = NULL; 5787 } 5788 5789 if (ioc->sense) { 5790 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 5791 dma_pool_destroy(ioc->sense_dma_pool); 5792 dexitprintk(ioc, 5793 ioc_info(ioc, "sense_pool(0x%p): free\n", 5794 ioc->sense)); 5795 ioc->sense = NULL; 5796 } 5797 5798 if (ioc->reply) { 5799 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 5800 dma_pool_destroy(ioc->reply_dma_pool); 5801 dexitprintk(ioc, 5802 ioc_info(ioc, "reply_pool(0x%p): free\n", 5803 ioc->reply)); 5804 ioc->reply = NULL; 5805 } 5806 5807 if (ioc->reply_free) { 5808 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 5809 ioc->reply_free_dma); 5810 dma_pool_destroy(ioc->reply_free_dma_pool); 5811 dexitprintk(ioc, 5812 ioc_info(ioc, "reply_free_pool(0x%p): free\n", 5813 ioc->reply_free)); 5814 ioc->reply_free = NULL; 5815 } 5816 5817 if (ioc->reply_post) { 5818 dma_alloc_count = DIV_ROUND_UP(count, 5819 RDPQ_MAX_INDEX_IN_ONE_CHUNK); 5820 for (i = 0; i < count; i++) { 5821 if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 5822 && dma_alloc_count) { 5823 if (ioc->reply_post[i].reply_post_free) { 5824 dma_pool_free( 5825 ioc->reply_post_free_dma_pool, 5826 ioc->reply_post[i].reply_post_free, 5827 ioc->reply_post[i].reply_post_free_dma); 5828 dexitprintk(ioc, ioc_info(ioc, 5829 "reply_post_free_pool(0x%p): free\n", 5830 ioc->reply_post[i].reply_post_free)); 5831 ioc->reply_post[i].reply_post_free = 5832 NULL; 5833 } 5834 --dma_alloc_count; 5835 } 5836 } 5837 dma_pool_destroy(ioc->reply_post_free_dma_pool); 5838 if (ioc->reply_post_free_array && 5839 ioc->rdpq_array_enable) { 5840 dma_pool_free(ioc->reply_post_free_array_dma_pool, 5841 ioc->reply_post_free_array, 5842 ioc->reply_post_free_array_dma); 5843 ioc->reply_post_free_array = NULL; 5844 } 5845 dma_pool_destroy(ioc->reply_post_free_array_dma_pool); 5846 kfree(ioc->reply_post); 5847 } 5848 5849 if (ioc->pcie_sgl_dma_pool) { 5850 for (i = 0; i < ioc->scsiio_depth; i++) { 5851 dma_pool_free(ioc->pcie_sgl_dma_pool, 5852 ioc->pcie_sg_lookup[i].pcie_sgl, 5853 ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5854 ioc->pcie_sg_lookup[i].pcie_sgl = NULL; 5855 } 5856 dma_pool_destroy(ioc->pcie_sgl_dma_pool); 5857 } 5858 kfree(ioc->pcie_sg_lookup); 5859 ioc->pcie_sg_lookup = NULL; 5860 5861 if (ioc->config_page) { 5862 dexitprintk(ioc, 5863 ioc_info(ioc, "config_page(0x%p): free\n", 5864 ioc->config_page)); 5865 dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz, 5866 ioc->config_page, ioc->config_page_dma); 5867 } 5868 5869 kfree(ioc->hpr_lookup); 5870 ioc->hpr_lookup = NULL; 5871 kfree(ioc->internal_lookup); 5872 ioc->internal_lookup = NULL; 5873 if (ioc->chain_lookup) { 5874 for (i = 0; i < ioc->scsiio_depth; i++) { 5875 for (j = ioc->chains_per_prp_buffer; 5876 j < ioc->chains_needed_per_io; j++) { 5877 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 5878 if (ct && ct->chain_buffer) 5879 dma_pool_free(ioc->chain_dma_pool, 5880 ct->chain_buffer, 5881 ct->chain_buffer_dma); 5882 } 5883 kfree(ioc->chain_lookup[i].chains_per_smid); 5884 } 5885 dma_pool_destroy(ioc->chain_dma_pool); 5886 kfree(ioc->chain_lookup); 5887 ioc->chain_lookup = NULL; 5888 } 5889 5890 kfree(ioc->io_queue_num); 5891 ioc->io_queue_num = NULL; 5892 } 5893 5894 /** 5895 * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are 5896 * having same upper 32bits in their base memory address. 5897 * @start_address: Base address of a reply queue set 5898 * @pool_sz: Size of single Reply Descriptor Post Queues pool size 5899 * 5900 * Return: 1 if reply queues in a set have a same upper 32bits in their base 5901 * memory address, else 0. 5902 */ 5903 static int 5904 mpt3sas_check_same_4gb_region(dma_addr_t start_address, u32 pool_sz) 5905 { 5906 dma_addr_t end_address; 5907 5908 end_address = start_address + pool_sz - 1; 5909 5910 if (upper_32_bits(start_address) == upper_32_bits(end_address)) 5911 return 1; 5912 else 5913 return 0; 5914 } 5915 5916 /** 5917 * _base_reduce_hba_queue_depth- Retry with reduced queue depth 5918 * @ioc: Adapter object 5919 * 5920 * Return: 0 for success, non-zero for failure. 5921 **/ 5922 static inline int 5923 _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc) 5924 { 5925 int reduce_sz = 64; 5926 5927 if ((ioc->hba_queue_depth - reduce_sz) > 5928 (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) { 5929 ioc->hba_queue_depth -= reduce_sz; 5930 return 0; 5931 } else 5932 return -ENOMEM; 5933 } 5934 5935 /** 5936 * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory 5937 * for pcie sgl pools. 5938 * @ioc: Adapter object 5939 * @sz: DMA Pool size 5940 * 5941 * Return: 0 for success, non-zero for failure. 5942 */ 5943 5944 static int 5945 _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5946 { 5947 int i = 0, j = 0; 5948 struct chain_tracker *ct; 5949 5950 ioc->pcie_sgl_dma_pool = 5951 dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 5952 ioc->page_size, 0); 5953 if (!ioc->pcie_sgl_dma_pool) { 5954 ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n"); 5955 return -ENOMEM; 5956 } 5957 5958 ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; 5959 ioc->chains_per_prp_buffer = 5960 min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io); 5961 for (i = 0; i < ioc->scsiio_depth; i++) { 5962 ioc->pcie_sg_lookup[i].pcie_sgl = 5963 dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL, 5964 &ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5965 if (!ioc->pcie_sg_lookup[i].pcie_sgl) { 5966 ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n"); 5967 return -EAGAIN; 5968 } 5969 5970 if (!mpt3sas_check_same_4gb_region( 5971 ioc->pcie_sg_lookup[i].pcie_sgl_dma, sz)) { 5972 ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n", 5973 ioc->pcie_sg_lookup[i].pcie_sgl, 5974 (unsigned long long) 5975 ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5976 ioc->use_32bit_dma = true; 5977 return -EAGAIN; 5978 } 5979 5980 for (j = 0; j < ioc->chains_per_prp_buffer; j++) { 5981 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 5982 ct->chain_buffer = 5983 ioc->pcie_sg_lookup[i].pcie_sgl + 5984 (j * ioc->chain_segment_sz); 5985 ct->chain_buffer_dma = 5986 ioc->pcie_sg_lookup[i].pcie_sgl_dma + 5987 (j * ioc->chain_segment_sz); 5988 } 5989 } 5990 dinitprintk(ioc, ioc_info(ioc, 5991 "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n", 5992 ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); 5993 dinitprintk(ioc, ioc_info(ioc, 5994 "Number of chains can fit in a PRP page(%d)\n", 5995 ioc->chains_per_prp_buffer)); 5996 return 0; 5997 } 5998 5999 /** 6000 * _base_allocate_chain_dma_pool - Allocating DMA'able memory 6001 * for chain dma pool. 6002 * @ioc: Adapter object 6003 * @sz: DMA Pool size 6004 * 6005 * Return: 0 for success, non-zero for failure. 6006 */ 6007 static int 6008 _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 6009 { 6010 int i = 0, j = 0; 6011 struct chain_tracker *ctr; 6012 6013 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, 6014 ioc->chain_segment_sz, 16, 0); 6015 if (!ioc->chain_dma_pool) 6016 return -ENOMEM; 6017 6018 for (i = 0; i < ioc->scsiio_depth; i++) { 6019 for (j = ioc->chains_per_prp_buffer; 6020 j < ioc->chains_needed_per_io; j++) { 6021 ctr = &ioc->chain_lookup[i].chains_per_smid[j]; 6022 ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool, 6023 GFP_KERNEL, &ctr->chain_buffer_dma); 6024 if (!ctr->chain_buffer) 6025 return -EAGAIN; 6026 if (!mpt3sas_check_same_4gb_region( 6027 ctr->chain_buffer_dma, ioc->chain_segment_sz)) { 6028 ioc_err(ioc, 6029 "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n", 6030 ctr->chain_buffer, 6031 (unsigned long long)ctr->chain_buffer_dma); 6032 ioc->use_32bit_dma = true; 6033 return -EAGAIN; 6034 } 6035 } 6036 } 6037 dinitprintk(ioc, ioc_info(ioc, 6038 "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n", 6039 ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth * 6040 (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) * 6041 ioc->chain_segment_sz))/1024)); 6042 return 0; 6043 } 6044 6045 /** 6046 * _base_allocate_sense_dma_pool - Allocating DMA'able memory 6047 * for sense dma pool. 6048 * @ioc: Adapter object 6049 * @sz: DMA Pool size 6050 * Return: 0 for success, non-zero for failure. 6051 */ 6052 static int 6053 _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 6054 { 6055 ioc->sense_dma_pool = 6056 dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0); 6057 if (!ioc->sense_dma_pool) 6058 return -ENOMEM; 6059 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, 6060 GFP_KERNEL, &ioc->sense_dma); 6061 if (!ioc->sense) 6062 return -EAGAIN; 6063 if (!mpt3sas_check_same_4gb_region(ioc->sense_dma, sz)) { 6064 dinitprintk(ioc, pr_err( 6065 "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n", 6066 ioc->sense, (unsigned long long) ioc->sense_dma)); 6067 ioc->use_32bit_dma = true; 6068 return -EAGAIN; 6069 } 6070 ioc_info(ioc, 6071 "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n", 6072 ioc->sense, (unsigned long long)ioc->sense_dma, 6073 ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024); 6074 return 0; 6075 } 6076 6077 /** 6078 * _base_allocate_reply_pool - Allocating DMA'able memory 6079 * for reply pool. 6080 * @ioc: Adapter object 6081 * @sz: DMA Pool size 6082 * Return: 0 for success, non-zero for failure. 6083 */ 6084 static int 6085 _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 6086 { 6087 /* reply pool, 4 byte align */ 6088 ioc->reply_dma_pool = dma_pool_create("reply pool", 6089 &ioc->pdev->dev, sz, 4, 0); 6090 if (!ioc->reply_dma_pool) 6091 return -ENOMEM; 6092 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, 6093 &ioc->reply_dma); 6094 if (!ioc->reply) 6095 return -EAGAIN; 6096 if (!mpt3sas_check_same_4gb_region(ioc->reply_dma, sz)) { 6097 dinitprintk(ioc, pr_err( 6098 "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n", 6099 ioc->reply, (unsigned long long) ioc->reply_dma)); 6100 ioc->use_32bit_dma = true; 6101 return -EAGAIN; 6102 } 6103 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 6104 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 6105 ioc_info(ioc, 6106 "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n", 6107 ioc->reply, (unsigned long long)ioc->reply_dma, 6108 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024); 6109 return 0; 6110 } 6111 6112 /** 6113 * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory 6114 * for reply free dma pool. 6115 * @ioc: Adapter object 6116 * @sz: DMA Pool size 6117 * Return: 0 for success, non-zero for failure. 6118 */ 6119 static int 6120 _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 6121 { 6122 /* reply free queue, 16 byte align */ 6123 ioc->reply_free_dma_pool = dma_pool_create( 6124 "reply_free pool", &ioc->pdev->dev, sz, 16, 0); 6125 if (!ioc->reply_free_dma_pool) 6126 return -ENOMEM; 6127 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, 6128 GFP_KERNEL, &ioc->reply_free_dma); 6129 if (!ioc->reply_free) 6130 return -EAGAIN; 6131 if (!mpt3sas_check_same_4gb_region(ioc->reply_free_dma, sz)) { 6132 dinitprintk(ioc, 6133 pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", 6134 ioc->reply_free, (unsigned long long) ioc->reply_free_dma)); 6135 ioc->use_32bit_dma = true; 6136 return -EAGAIN; 6137 } 6138 memset(ioc->reply_free, 0, sz); 6139 dinitprintk(ioc, ioc_info(ioc, 6140 "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", 6141 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 6142 dinitprintk(ioc, ioc_info(ioc, 6143 "reply_free_dma (0x%llx)\n", 6144 (unsigned long long)ioc->reply_free_dma)); 6145 return 0; 6146 } 6147 6148 /** 6149 * _base_allocate_reply_post_free_array - Allocating DMA'able memory 6150 * for reply post free array. 6151 * @ioc: Adapter object 6152 * @reply_post_free_array_sz: DMA Pool size 6153 * Return: 0 for success, non-zero for failure. 6154 */ 6155 6156 static int 6157 _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc, 6158 u32 reply_post_free_array_sz) 6159 { 6160 ioc->reply_post_free_array_dma_pool = 6161 dma_pool_create("reply_post_free_array pool", 6162 &ioc->pdev->dev, reply_post_free_array_sz, 16, 0); 6163 if (!ioc->reply_post_free_array_dma_pool) 6164 return -ENOMEM; 6165 ioc->reply_post_free_array = 6166 dma_pool_alloc(ioc->reply_post_free_array_dma_pool, 6167 GFP_KERNEL, &ioc->reply_post_free_array_dma); 6168 if (!ioc->reply_post_free_array) 6169 return -EAGAIN; 6170 if (!mpt3sas_check_same_4gb_region(ioc->reply_post_free_array_dma, 6171 reply_post_free_array_sz)) { 6172 dinitprintk(ioc, pr_err( 6173 "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", 6174 ioc->reply_free, 6175 (unsigned long long) ioc->reply_free_dma)); 6176 ioc->use_32bit_dma = true; 6177 return -EAGAIN; 6178 } 6179 return 0; 6180 } 6181 /** 6182 * base_alloc_rdpq_dma_pool - Allocating DMA'able memory 6183 * for reply queues. 6184 * @ioc: per adapter object 6185 * @sz: DMA Pool size 6186 * Return: 0 for success, non-zero for failure. 6187 */ 6188 static int 6189 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) 6190 { 6191 int i = 0; 6192 u32 dma_alloc_count = 0; 6193 int reply_post_free_sz = ioc->reply_post_queue_depth * 6194 sizeof(Mpi2DefaultReplyDescriptor_t); 6195 int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; 6196 6197 ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct), 6198 GFP_KERNEL); 6199 if (!ioc->reply_post) 6200 return -ENOMEM; 6201 /* 6202 * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and 6203 * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should 6204 * be within 4GB boundary i.e reply queues in a set must have same 6205 * upper 32-bits in their memory address. so here driver is allocating 6206 * the DMA'able memory for reply queues according. 6207 * Driver uses limitation of 6208 * VENTURA_SERIES to manage INVADER_SERIES as well. 6209 */ 6210 dma_alloc_count = DIV_ROUND_UP(count, 6211 RDPQ_MAX_INDEX_IN_ONE_CHUNK); 6212 ioc->reply_post_free_dma_pool = 6213 dma_pool_create("reply_post_free pool", 6214 &ioc->pdev->dev, sz, 16, 0); 6215 if (!ioc->reply_post_free_dma_pool) 6216 return -ENOMEM; 6217 for (i = 0; i < count; i++) { 6218 if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { 6219 ioc->reply_post[i].reply_post_free = 6220 dma_pool_zalloc(ioc->reply_post_free_dma_pool, 6221 GFP_KERNEL, 6222 &ioc->reply_post[i].reply_post_free_dma); 6223 if (!ioc->reply_post[i].reply_post_free) 6224 return -ENOMEM; 6225 /* 6226 * Each set of RDPQ pool must satisfy 4gb boundary 6227 * restriction. 6228 * 1) Check if allocated resources for RDPQ pool are in 6229 * the same 4GB range. 6230 * 2) If #1 is true, continue with 64 bit DMA. 6231 * 3) If #1 is false, return 1. which means free all the 6232 * resources and set DMA mask to 32 and allocate. 6233 */ 6234 if (!mpt3sas_check_same_4gb_region( 6235 ioc->reply_post[i].reply_post_free_dma, sz)) { 6236 dinitprintk(ioc, 6237 ioc_err(ioc, "bad Replypost free pool(0x%p)" 6238 "reply_post_free_dma = (0x%llx)\n", 6239 ioc->reply_post[i].reply_post_free, 6240 (unsigned long long) 6241 ioc->reply_post[i].reply_post_free_dma)); 6242 return -EAGAIN; 6243 } 6244 dma_alloc_count--; 6245 6246 } else { 6247 ioc->reply_post[i].reply_post_free = 6248 (Mpi2ReplyDescriptorsUnion_t *) 6249 ((long)ioc->reply_post[i-1].reply_post_free 6250 + reply_post_free_sz); 6251 ioc->reply_post[i].reply_post_free_dma = 6252 (dma_addr_t) 6253 (ioc->reply_post[i-1].reply_post_free_dma + 6254 reply_post_free_sz); 6255 } 6256 } 6257 return 0; 6258 } 6259 6260 /** 6261 * _base_allocate_memory_pools - allocate start of day memory pools 6262 * @ioc: per adapter object 6263 * 6264 * Return: 0 success, anything else error. 6265 */ 6266 static int 6267 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) 6268 { 6269 struct mpt3sas_facts *facts; 6270 u16 max_sge_elements; 6271 u16 chains_needed_per_io; 6272 u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; 6273 u32 retry_sz; 6274 u32 rdpq_sz = 0, sense_sz = 0; 6275 u16 max_request_credit, nvme_blocks_needed; 6276 unsigned short sg_tablesize; 6277 u16 sge_size; 6278 int i; 6279 int ret = 0, rc = 0; 6280 6281 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 6282 6283 6284 retry_sz = 0; 6285 facts = &ioc->facts; 6286 6287 /* command line tunables for max sgl entries */ 6288 if (max_sgl_entries != -1) 6289 sg_tablesize = max_sgl_entries; 6290 else { 6291 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 6292 sg_tablesize = MPT2SAS_SG_DEPTH; 6293 else 6294 sg_tablesize = MPT3SAS_SG_DEPTH; 6295 } 6296 6297 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ 6298 if (reset_devices) 6299 sg_tablesize = min_t(unsigned short, sg_tablesize, 6300 MPT_KDUMP_MIN_PHYS_SEGMENTS); 6301 6302 if (ioc->is_mcpu_endpoint) 6303 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 6304 else { 6305 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 6306 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 6307 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 6308 sg_tablesize = min_t(unsigned short, sg_tablesize, 6309 SG_MAX_SEGMENTS); 6310 ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n", 6311 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 6312 } 6313 ioc->shost->sg_tablesize = sg_tablesize; 6314 } 6315 6316 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), 6317 (facts->RequestCredit / 4)); 6318 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { 6319 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + 6320 INTERNAL_SCSIIO_CMDS_COUNT)) { 6321 ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n", 6322 facts->RequestCredit); 6323 return -ENOMEM; 6324 } 6325 ioc->internal_depth = 10; 6326 } 6327 6328 ioc->hi_priority_depth = ioc->internal_depth - (5); 6329 /* command line tunables for max controller queue depth */ 6330 if (max_queue_depth != -1 && max_queue_depth != 0) { 6331 max_request_credit = min_t(u16, max_queue_depth + 6332 ioc->internal_depth, facts->RequestCredit); 6333 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 6334 max_request_credit = MAX_HBA_QUEUE_DEPTH; 6335 } else if (reset_devices) 6336 max_request_credit = min_t(u16, facts->RequestCredit, 6337 (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); 6338 else 6339 max_request_credit = min_t(u16, facts->RequestCredit, 6340 MAX_HBA_QUEUE_DEPTH); 6341 6342 /* Firmware maintains additional facts->HighPriorityCredit number of 6343 * credits for HiPriprity Request messages, so hba queue depth will be 6344 * sum of max_request_credit and high priority queue depth. 6345 */ 6346 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; 6347 6348 /* request frame size */ 6349 ioc->request_sz = facts->IOCRequestFrameSize * 4; 6350 6351 /* reply frame size */ 6352 ioc->reply_sz = facts->ReplyFrameSize * 4; 6353 6354 /* chain segment size */ 6355 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 6356 if (facts->IOCMaxChainSegmentSize) 6357 ioc->chain_segment_sz = 6358 facts->IOCMaxChainSegmentSize * 6359 MAX_CHAIN_ELEMT_SZ; 6360 else 6361 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ 6362 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * 6363 MAX_CHAIN_ELEMT_SZ; 6364 } else 6365 ioc->chain_segment_sz = ioc->request_sz; 6366 6367 /* calculate the max scatter element size */ 6368 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 6369 6370 retry_allocation: 6371 total_sz = 0; 6372 /* calculate number of sg elements left over in the 1st frame */ 6373 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 6374 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 6375 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 6376 6377 /* now do the same for a chain buffer */ 6378 max_sge_elements = ioc->chain_segment_sz - sge_size; 6379 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 6380 6381 /* 6382 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 6383 */ 6384 chains_needed_per_io = ((ioc->shost->sg_tablesize - 6385 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 6386 + 1; 6387 if (chains_needed_per_io > facts->MaxChainDepth) { 6388 chains_needed_per_io = facts->MaxChainDepth; 6389 ioc->shost->sg_tablesize = min_t(u16, 6390 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 6391 * chains_needed_per_io), ioc->shost->sg_tablesize); 6392 } 6393 ioc->chains_needed_per_io = chains_needed_per_io; 6394 6395 /* reply free queue sizing - taking into account for 64 FW events */ 6396 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 6397 6398 /* mCPU manage single counters for simplicity */ 6399 if (ioc->is_mcpu_endpoint) 6400 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth; 6401 else { 6402 /* calculate reply descriptor post queue depth */ 6403 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 6404 ioc->reply_free_queue_depth + 1; 6405 /* align the reply post queue on the next 16 count boundary */ 6406 if (ioc->reply_post_queue_depth % 16) 6407 ioc->reply_post_queue_depth += 16 - 6408 (ioc->reply_post_queue_depth % 16); 6409 } 6410 6411 if (ioc->reply_post_queue_depth > 6412 facts->MaxReplyDescriptorPostQueueDepth) { 6413 ioc->reply_post_queue_depth = 6414 facts->MaxReplyDescriptorPostQueueDepth - 6415 (facts->MaxReplyDescriptorPostQueueDepth % 16); 6416 ioc->hba_queue_depth = 6417 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 6418 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 6419 } 6420 6421 ioc_info(ioc, 6422 "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), " 6423 "sge_per_io(%d), chains_per_io(%d)\n", 6424 ioc->max_sges_in_main_message, 6425 ioc->max_sges_in_chain_message, 6426 ioc->shost->sg_tablesize, 6427 ioc->chains_needed_per_io); 6428 6429 /* reply post queue, 16 byte align */ 6430 reply_post_free_sz = ioc->reply_post_queue_depth * 6431 sizeof(Mpi2DefaultReplyDescriptor_t); 6432 rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; 6433 if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 6434 || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK)) 6435 rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; 6436 ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz); 6437 if (ret == -EAGAIN) { 6438 /* 6439 * Free allocated bad RDPQ memory pools. 6440 * Change dma coherent mask to 32 bit and reallocate RDPQ 6441 */ 6442 _base_release_memory_pools(ioc); 6443 ioc->use_32bit_dma = true; 6444 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { 6445 ioc_err(ioc, 6446 "32 DMA mask failed %s\n", pci_name(ioc->pdev)); 6447 return -ENODEV; 6448 } 6449 if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) 6450 return -ENOMEM; 6451 } else if (ret == -ENOMEM) 6452 return -ENOMEM; 6453 total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 : 6454 DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK)); 6455 ioc->scsiio_depth = ioc->hba_queue_depth - 6456 ioc->hi_priority_depth - ioc->internal_depth; 6457 6458 /* set the scsi host can_queue depth 6459 * with some internal commands that could be outstanding 6460 */ 6461 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; 6462 dinitprintk(ioc, 6463 ioc_info(ioc, "scsi host: can_queue depth (%d)\n", 6464 ioc->shost->can_queue)); 6465 6466 /* contiguous pool for request and chains, 16 byte align, one extra " 6467 * "frame for smid=0 6468 */ 6469 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 6470 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 6471 6472 /* hi-priority queue */ 6473 sz += (ioc->hi_priority_depth * ioc->request_sz); 6474 6475 /* internal queue */ 6476 sz += (ioc->internal_depth * ioc->request_sz); 6477 6478 ioc->request_dma_sz = sz; 6479 ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz, 6480 &ioc->request_dma, GFP_KERNEL); 6481 if (!ioc->request) { 6482 ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n", 6483 ioc->hba_queue_depth, ioc->chains_needed_per_io, 6484 ioc->request_sz, sz / 1024); 6485 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 6486 goto out; 6487 retry_sz = 64; 6488 ioc->hba_queue_depth -= retry_sz; 6489 _base_release_memory_pools(ioc); 6490 goto retry_allocation; 6491 } 6492 6493 if (retry_sz) 6494 ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n", 6495 ioc->hba_queue_depth, ioc->chains_needed_per_io, 6496 ioc->request_sz, sz / 1024); 6497 6498 /* hi-priority queue */ 6499 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 6500 ioc->request_sz); 6501 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 6502 ioc->request_sz); 6503 6504 /* internal queue */ 6505 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 6506 ioc->request_sz); 6507 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 6508 ioc->request_sz); 6509 6510 ioc_info(ioc, 6511 "request pool(0x%p) - dma(0x%llx): " 6512 "depth(%d), frame_size(%d), pool_size(%d kB)\n", 6513 ioc->request, (unsigned long long) ioc->request_dma, 6514 ioc->hba_queue_depth, ioc->request_sz, 6515 (ioc->hba_queue_depth * ioc->request_sz) / 1024); 6516 6517 total_sz += sz; 6518 6519 dinitprintk(ioc, 6520 ioc_info(ioc, "scsiio(0x%p): depth(%d)\n", 6521 ioc->request, ioc->scsiio_depth)); 6522 6523 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 6524 sz = ioc->scsiio_depth * sizeof(struct chain_lookup); 6525 ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); 6526 if (!ioc->chain_lookup) { 6527 ioc_err(ioc, "chain_lookup: __get_free_pages failed\n"); 6528 goto out; 6529 } 6530 6531 sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker); 6532 for (i = 0; i < ioc->scsiio_depth; i++) { 6533 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL); 6534 if (!ioc->chain_lookup[i].chains_per_smid) { 6535 ioc_err(ioc, "chain_lookup: kzalloc failed\n"); 6536 goto out; 6537 } 6538 } 6539 6540 /* initialize hi-priority queue smid's */ 6541 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 6542 sizeof(struct request_tracker), GFP_KERNEL); 6543 if (!ioc->hpr_lookup) { 6544 ioc_err(ioc, "hpr_lookup: kcalloc failed\n"); 6545 goto out; 6546 } 6547 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 6548 dinitprintk(ioc, 6549 ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n", 6550 ioc->hi_priority, 6551 ioc->hi_priority_depth, ioc->hi_priority_smid)); 6552 6553 /* initialize internal queue smid's */ 6554 ioc->internal_lookup = kcalloc(ioc->internal_depth, 6555 sizeof(struct request_tracker), GFP_KERNEL); 6556 if (!ioc->internal_lookup) { 6557 ioc_err(ioc, "internal_lookup: kcalloc failed\n"); 6558 goto out; 6559 } 6560 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 6561 dinitprintk(ioc, 6562 ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n", 6563 ioc->internal, 6564 ioc->internal_depth, ioc->internal_smid)); 6565 6566 ioc->io_queue_num = kcalloc(ioc->scsiio_depth, 6567 sizeof(u16), GFP_KERNEL); 6568 if (!ioc->io_queue_num) 6569 goto out; 6570 /* 6571 * The number of NVMe page sized blocks needed is: 6572 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 6573 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry 6574 * that is placed in the main message frame. 8 is the size of each PRP 6575 * entry or PRP list pointer entry. 8 is subtracted from page_size 6576 * because of the PRP list pointer entry at the end of a page, so this 6577 * is not counted as a PRP entry. The 1 added page is a round up. 6578 * 6579 * To avoid allocation failures due to the amount of memory that could 6580 * be required for NVMe PRP's, only each set of NVMe blocks will be 6581 * contiguous, so a new set is allocated for each possible I/O. 6582 */ 6583 6584 ioc->chains_per_prp_buffer = 0; 6585 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 6586 nvme_blocks_needed = 6587 (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; 6588 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); 6589 nvme_blocks_needed++; 6590 6591 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth; 6592 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL); 6593 if (!ioc->pcie_sg_lookup) { 6594 ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n"); 6595 goto out; 6596 } 6597 sz = nvme_blocks_needed * ioc->page_size; 6598 rc = _base_allocate_pcie_sgl_pool(ioc, sz); 6599 if (rc == -ENOMEM) 6600 return -ENOMEM; 6601 else if (rc == -EAGAIN) 6602 goto try_32bit_dma; 6603 total_sz += sz * ioc->scsiio_depth; 6604 } 6605 6606 rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz); 6607 if (rc == -ENOMEM) 6608 return -ENOMEM; 6609 else if (rc == -EAGAIN) 6610 goto try_32bit_dma; 6611 total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io - 6612 ioc->chains_per_prp_buffer) * ioc->scsiio_depth); 6613 dinitprintk(ioc, 6614 ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 6615 ioc->chain_depth, ioc->chain_segment_sz, 6616 (ioc->chain_depth * ioc->chain_segment_sz) / 1024)); 6617 /* sense buffers, 4 byte align */ 6618 sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 6619 rc = _base_allocate_sense_dma_pool(ioc, sense_sz); 6620 if (rc == -ENOMEM) 6621 return -ENOMEM; 6622 else if (rc == -EAGAIN) 6623 goto try_32bit_dma; 6624 total_sz += sense_sz; 6625 /* reply pool, 4 byte align */ 6626 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 6627 rc = _base_allocate_reply_pool(ioc, sz); 6628 if (rc == -ENOMEM) 6629 return -ENOMEM; 6630 else if (rc == -EAGAIN) 6631 goto try_32bit_dma; 6632 total_sz += sz; 6633 6634 /* reply free queue, 16 byte align */ 6635 sz = ioc->reply_free_queue_depth * 4; 6636 rc = _base_allocate_reply_free_dma_pool(ioc, sz); 6637 if (rc == -ENOMEM) 6638 return -ENOMEM; 6639 else if (rc == -EAGAIN) 6640 goto try_32bit_dma; 6641 dinitprintk(ioc, 6642 ioc_info(ioc, "reply_free_dma (0x%llx)\n", 6643 (unsigned long long)ioc->reply_free_dma)); 6644 total_sz += sz; 6645 if (ioc->rdpq_array_enable) { 6646 reply_post_free_array_sz = ioc->reply_queue_count * 6647 sizeof(Mpi2IOCInitRDPQArrayEntry); 6648 rc = _base_allocate_reply_post_free_array(ioc, 6649 reply_post_free_array_sz); 6650 if (rc == -ENOMEM) 6651 return -ENOMEM; 6652 else if (rc == -EAGAIN) 6653 goto try_32bit_dma; 6654 } 6655 ioc->config_page_sz = 512; 6656 ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev, 6657 ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL); 6658 if (!ioc->config_page) { 6659 ioc_err(ioc, "config page: dma_pool_alloc failed\n"); 6660 goto out; 6661 } 6662 6663 ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n", 6664 ioc->config_page, (unsigned long long)ioc->config_page_dma, 6665 ioc->config_page_sz); 6666 total_sz += ioc->config_page_sz; 6667 6668 ioc_info(ioc, "Allocated physical memory: size(%d kB)\n", 6669 total_sz / 1024); 6670 ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 6671 ioc->shost->can_queue, facts->RequestCredit); 6672 ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n", 6673 ioc->shost->sg_tablesize); 6674 return 0; 6675 6676 try_32bit_dma: 6677 _base_release_memory_pools(ioc); 6678 if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) { 6679 /* Change dma coherent mask to 32 bit and reallocate */ 6680 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { 6681 pr_err("Setting 32 bit coherent DMA mask Failed %s\n", 6682 pci_name(ioc->pdev)); 6683 return -ENODEV; 6684 } 6685 } else if (_base_reduce_hba_queue_depth(ioc) != 0) 6686 return -ENOMEM; 6687 goto retry_allocation; 6688 6689 out: 6690 return -ENOMEM; 6691 } 6692 6693 /** 6694 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 6695 * @ioc: Pointer to MPT_ADAPTER structure 6696 * @cooked: Request raw or cooked IOC state 6697 * 6698 * Return: all IOC Doorbell register bits if cooked==0, else just the 6699 * Doorbell bits in MPI_IOC_STATE_MASK. 6700 */ 6701 u32 6702 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 6703 { 6704 u32 s, sc; 6705 6706 s = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); 6707 sc = s & MPI2_IOC_STATE_MASK; 6708 return cooked ? sc : s; 6709 } 6710 6711 /** 6712 * _base_wait_on_iocstate - waiting on a particular ioc state 6713 * @ioc: ? 6714 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 6715 * @timeout: timeout in second 6716 * 6717 * Return: 0 for success, non-zero for failure. 6718 */ 6719 static int 6720 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) 6721 { 6722 u32 count, cntdn; 6723 u32 current_state; 6724 6725 count = 0; 6726 cntdn = 1000 * timeout; 6727 do { 6728 current_state = mpt3sas_base_get_iocstate(ioc, 1); 6729 if (current_state == ioc_state) 6730 return 0; 6731 if (count && current_state == MPI2_IOC_STATE_FAULT) 6732 break; 6733 if (count && current_state == MPI2_IOC_STATE_COREDUMP) 6734 break; 6735 6736 usleep_range(1000, 1500); 6737 count++; 6738 } while (--cntdn); 6739 6740 return current_state; 6741 } 6742 6743 /** 6744 * _base_dump_reg_set - This function will print hexdump of register set. 6745 * @ioc: per adapter object 6746 * 6747 * Return: nothing. 6748 */ 6749 static inline void 6750 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc) 6751 { 6752 unsigned int i, sz = 256; 6753 u32 __iomem *reg = (u32 __iomem *)ioc->chip; 6754 6755 ioc_info(ioc, "System Register set:\n"); 6756 for (i = 0; i < (sz / sizeof(u32)); i++) 6757 pr_info("%08x: %08x\n", (i * 4), readl(®[i])); 6758 } 6759 6760 /** 6761 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 6762 * a write to the doorbell) 6763 * @ioc: per adapter object 6764 * @timeout: timeout in seconds 6765 * 6766 * Return: 0 for success, non-zero for failure. 6767 * 6768 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 6769 */ 6770 6771 static int 6772 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 6773 { 6774 u32 cntdn, count; 6775 u32 int_status; 6776 6777 count = 0; 6778 cntdn = 1000 * timeout; 6779 do { 6780 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6781 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6782 dhsprintk(ioc, 6783 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6784 __func__, count, timeout)); 6785 return 0; 6786 } 6787 6788 usleep_range(1000, 1500); 6789 count++; 6790 } while (--cntdn); 6791 6792 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6793 __func__, count, int_status); 6794 return -EFAULT; 6795 } 6796 6797 static int 6798 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 6799 { 6800 u32 cntdn, count; 6801 u32 int_status; 6802 6803 count = 0; 6804 cntdn = 2000 * timeout; 6805 do { 6806 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6807 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6808 dhsprintk(ioc, 6809 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6810 __func__, count, timeout)); 6811 return 0; 6812 } 6813 6814 udelay(500); 6815 count++; 6816 } while (--cntdn); 6817 6818 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6819 __func__, count, int_status); 6820 return -EFAULT; 6821 6822 } 6823 6824 /** 6825 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 6826 * @ioc: per adapter object 6827 * @timeout: timeout in second 6828 * 6829 * Return: 0 for success, non-zero for failure. 6830 * 6831 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 6832 * doorbell. 6833 */ 6834 static int 6835 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) 6836 { 6837 u32 cntdn, count; 6838 u32 int_status; 6839 u32 doorbell; 6840 6841 count = 0; 6842 cntdn = 1000 * timeout; 6843 do { 6844 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6845 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 6846 dhsprintk(ioc, 6847 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6848 __func__, count, timeout)); 6849 return 0; 6850 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6851 doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); 6852 if ((doorbell & MPI2_IOC_STATE_MASK) == 6853 MPI2_IOC_STATE_FAULT) { 6854 mpt3sas_print_fault_code(ioc, doorbell); 6855 return -EFAULT; 6856 } 6857 if ((doorbell & MPI2_IOC_STATE_MASK) == 6858 MPI2_IOC_STATE_COREDUMP) { 6859 mpt3sas_print_coredump_info(ioc, doorbell); 6860 return -EFAULT; 6861 } 6862 } else if (int_status == 0xFFFFFFFF) 6863 goto out; 6864 6865 usleep_range(1000, 1500); 6866 count++; 6867 } while (--cntdn); 6868 6869 out: 6870 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6871 __func__, count, int_status); 6872 return -EFAULT; 6873 } 6874 6875 /** 6876 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 6877 * @ioc: per adapter object 6878 * @timeout: timeout in second 6879 * 6880 * Return: 0 for success, non-zero for failure. 6881 */ 6882 static int 6883 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) 6884 { 6885 u32 cntdn, count; 6886 u32 doorbell_reg; 6887 6888 count = 0; 6889 cntdn = 1000 * timeout; 6890 do { 6891 doorbell_reg = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); 6892 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 6893 dhsprintk(ioc, 6894 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6895 __func__, count, timeout)); 6896 return 0; 6897 } 6898 6899 usleep_range(1000, 1500); 6900 count++; 6901 } while (--cntdn); 6902 6903 ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 6904 __func__, count, doorbell_reg); 6905 return -EFAULT; 6906 } 6907 6908 /** 6909 * _base_send_ioc_reset - send doorbell reset 6910 * @ioc: per adapter object 6911 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 6912 * @timeout: timeout in second 6913 * 6914 * Return: 0 for success, non-zero for failure. 6915 */ 6916 static int 6917 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) 6918 { 6919 u32 ioc_state; 6920 int r = 0; 6921 unsigned long flags; 6922 6923 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 6924 ioc_err(ioc, "%s: unknown reset_type\n", __func__); 6925 return -EFAULT; 6926 } 6927 6928 if (!(ioc->facts.IOCCapabilities & 6929 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 6930 return -EFAULT; 6931 6932 ioc_info(ioc, "sending message unit reset !!\n"); 6933 6934 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 6935 &ioc->chip->Doorbell); 6936 if ((_base_wait_for_doorbell_ack(ioc, 15))) { 6937 r = -EFAULT; 6938 goto out; 6939 } 6940 6941 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 6942 if (ioc_state) { 6943 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 6944 __func__, ioc_state); 6945 r = -EFAULT; 6946 goto out; 6947 } 6948 out: 6949 if (r != 0) { 6950 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6951 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 6952 /* 6953 * Wait for IOC state CoreDump to clear only during 6954 * HBA initialization & release time. 6955 */ 6956 if ((ioc_state & MPI2_IOC_STATE_MASK) == 6957 MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 || 6958 ioc->fault_reset_work_q == NULL)) { 6959 spin_unlock_irqrestore( 6960 &ioc->ioc_reset_in_progress_lock, flags); 6961 mpt3sas_print_coredump_info(ioc, ioc_state); 6962 mpt3sas_base_wait_for_coredump_completion(ioc, 6963 __func__); 6964 spin_lock_irqsave( 6965 &ioc->ioc_reset_in_progress_lock, flags); 6966 } 6967 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 6968 } 6969 ioc_info(ioc, "message unit reset: %s\n", 6970 r == 0 ? "SUCCESS" : "FAILED"); 6971 return r; 6972 } 6973 6974 /** 6975 * mpt3sas_wait_for_ioc - IOC's operational state is checked here. 6976 * @ioc: per adapter object 6977 * @timeout: timeout in seconds 6978 * 6979 * Return: Waits up to timeout seconds for the IOC to 6980 * become operational. Returns 0 if IOC is present 6981 * and operational; otherwise returns %-EFAULT. 6982 */ 6983 6984 int 6985 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout) 6986 { 6987 int wait_state_count = 0; 6988 u32 ioc_state; 6989 6990 do { 6991 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 6992 if (ioc_state == MPI2_IOC_STATE_OPERATIONAL) 6993 break; 6994 6995 /* 6996 * Watchdog thread will be started after IOC Initialization, so 6997 * no need to wait here for IOC state to become operational 6998 * when IOC Initialization is on. Instead the driver will 6999 * return ETIME status, so that calling function can issue 7000 * diag reset operation and retry the command. 7001 */ 7002 if (ioc->is_driver_loading) 7003 return -ETIME; 7004 7005 ssleep(1); 7006 ioc_info(ioc, "%s: waiting for operational state(count=%d)\n", 7007 __func__, ++wait_state_count); 7008 } while (--timeout); 7009 if (!timeout) { 7010 ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__); 7011 return -EFAULT; 7012 } 7013 if (wait_state_count) 7014 ioc_info(ioc, "ioc is operational\n"); 7015 return 0; 7016 } 7017 7018 /** 7019 * _base_handshake_req_reply_wait - send request thru doorbell interface 7020 * @ioc: per adapter object 7021 * @request_bytes: request length 7022 * @request: pointer having request payload 7023 * @reply_bytes: reply length 7024 * @reply: pointer to reply payload 7025 * @timeout: timeout in second 7026 * 7027 * Return: 0 for success, non-zero for failure. 7028 */ 7029 static int 7030 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 7031 u32 *request, int reply_bytes, u16 *reply, int timeout) 7032 { 7033 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 7034 int i; 7035 u8 failed; 7036 __le32 *mfp; 7037 7038 /* make sure doorbell is not in use */ 7039 if ((ioc->base_readl_ext_retry(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 7040 ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__); 7041 return -EFAULT; 7042 } 7043 7044 /* clear pending doorbell interrupts from previous state changes */ 7045 if (ioc->base_readl(&ioc->chip->HostInterruptStatus) & 7046 MPI2_HIS_IOC2SYS_DB_STATUS) 7047 writel(0, &ioc->chip->HostInterruptStatus); 7048 7049 /* send message to ioc */ 7050 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 7051 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 7052 &ioc->chip->Doorbell); 7053 7054 if ((_base_spin_on_doorbell_int(ioc, 5))) { 7055 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 7056 __LINE__); 7057 return -EFAULT; 7058 } 7059 writel(0, &ioc->chip->HostInterruptStatus); 7060 7061 if ((_base_wait_for_doorbell_ack(ioc, 5))) { 7062 ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n", 7063 __LINE__); 7064 return -EFAULT; 7065 } 7066 7067 /* send message 32-bits at a time */ 7068 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 7069 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 7070 if ((_base_wait_for_doorbell_ack(ioc, 5))) 7071 failed = 1; 7072 } 7073 7074 if (failed) { 7075 ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n", 7076 __LINE__); 7077 return -EFAULT; 7078 } 7079 7080 /* now wait for the reply */ 7081 if ((_base_wait_for_doorbell_int(ioc, timeout))) { 7082 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 7083 __LINE__); 7084 return -EFAULT; 7085 } 7086 7087 /* read the first two 16-bits, it gives the total length of the reply */ 7088 reply[0] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell) 7089 & MPI2_DOORBELL_DATA_MASK); 7090 writel(0, &ioc->chip->HostInterruptStatus); 7091 if ((_base_wait_for_doorbell_int(ioc, 5))) { 7092 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 7093 __LINE__); 7094 return -EFAULT; 7095 } 7096 reply[1] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell) 7097 & MPI2_DOORBELL_DATA_MASK); 7098 writel(0, &ioc->chip->HostInterruptStatus); 7099 7100 for (i = 2; i < default_reply->MsgLength * 2; i++) { 7101 if ((_base_wait_for_doorbell_int(ioc, 5))) { 7102 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 7103 __LINE__); 7104 return -EFAULT; 7105 } 7106 if (i >= reply_bytes/2) /* overflow case */ 7107 ioc->base_readl_ext_retry(&ioc->chip->Doorbell); 7108 else 7109 reply[i] = le16_to_cpu( 7110 ioc->base_readl_ext_retry(&ioc->chip->Doorbell) 7111 & MPI2_DOORBELL_DATA_MASK); 7112 writel(0, &ioc->chip->HostInterruptStatus); 7113 } 7114 7115 _base_wait_for_doorbell_int(ioc, 5); 7116 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { 7117 dhsprintk(ioc, 7118 ioc_info(ioc, "doorbell is in use (line=%d)\n", 7119 __LINE__)); 7120 } 7121 writel(0, &ioc->chip->HostInterruptStatus); 7122 7123 if (ioc->logging_level & MPT_DEBUG_INIT) { 7124 mfp = (__le32 *)reply; 7125 pr_info("\toffset:data\n"); 7126 for (i = 0; i < reply_bytes/4; i++) 7127 ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, 7128 le32_to_cpu(mfp[i])); 7129 } 7130 return 0; 7131 } 7132 7133 /** 7134 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 7135 * @ioc: per adapter object 7136 * @mpi_reply: the reply payload from FW 7137 * @mpi_request: the request payload sent to FW 7138 * 7139 * The SAS IO Unit Control Request message allows the host to perform low-level 7140 * operations, such as resets on the PHYs of the IO Unit, also allows the host 7141 * to obtain the IOC assigned device handles for a device if it has other 7142 * identifying information about the device, in addition allows the host to 7143 * remove IOC resources associated with the device. 7144 * 7145 * Return: 0 for success, non-zero for failure. 7146 */ 7147 int 7148 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 7149 Mpi2SasIoUnitControlReply_t *mpi_reply, 7150 Mpi2SasIoUnitControlRequest_t *mpi_request) 7151 { 7152 u16 smid; 7153 u8 issue_reset = 0; 7154 int rc; 7155 void *request; 7156 7157 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7158 7159 mutex_lock(&ioc->base_cmds.mutex); 7160 7161 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 7162 ioc_err(ioc, "%s: base_cmd in use\n", __func__); 7163 rc = -EAGAIN; 7164 goto out; 7165 } 7166 7167 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); 7168 if (rc) 7169 goto out; 7170 7171 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 7172 if (!smid) { 7173 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7174 rc = -EAGAIN; 7175 goto out; 7176 } 7177 7178 rc = 0; 7179 ioc->base_cmds.status = MPT3_CMD_PENDING; 7180 request = mpt3sas_base_get_msg_frame(ioc, smid); 7181 ioc->base_cmds.smid = smid; 7182 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 7183 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 7184 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 7185 ioc->ioc_link_reset_in_progress = 1; 7186 init_completion(&ioc->base_cmds.done); 7187 ioc->put_smid_default(ioc, smid); 7188 wait_for_completion_timeout(&ioc->base_cmds.done, 7189 msecs_to_jiffies(10000)); 7190 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 7191 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 7192 ioc->ioc_link_reset_in_progress) 7193 ioc->ioc_link_reset_in_progress = 0; 7194 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7195 mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status, 7196 mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4, 7197 issue_reset); 7198 goto issue_host_reset; 7199 } 7200 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 7201 memcpy(mpi_reply, ioc->base_cmds.reply, 7202 sizeof(Mpi2SasIoUnitControlReply_t)); 7203 else 7204 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 7205 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7206 goto out; 7207 7208 issue_host_reset: 7209 if (issue_reset) 7210 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 7211 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7212 rc = -EFAULT; 7213 out: 7214 mutex_unlock(&ioc->base_cmds.mutex); 7215 return rc; 7216 } 7217 7218 /** 7219 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 7220 * @ioc: per adapter object 7221 * @mpi_reply: the reply payload from FW 7222 * @mpi_request: the request payload sent to FW 7223 * 7224 * The SCSI Enclosure Processor request message causes the IOC to 7225 * communicate with SES devices to control LED status signals. 7226 * 7227 * Return: 0 for success, non-zero for failure. 7228 */ 7229 int 7230 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 7231 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 7232 { 7233 u16 smid; 7234 u8 issue_reset = 0; 7235 int rc; 7236 void *request; 7237 7238 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7239 7240 mutex_lock(&ioc->base_cmds.mutex); 7241 7242 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 7243 ioc_err(ioc, "%s: base_cmd in use\n", __func__); 7244 rc = -EAGAIN; 7245 goto out; 7246 } 7247 7248 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); 7249 if (rc) 7250 goto out; 7251 7252 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 7253 if (!smid) { 7254 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7255 rc = -EAGAIN; 7256 goto out; 7257 } 7258 7259 rc = 0; 7260 ioc->base_cmds.status = MPT3_CMD_PENDING; 7261 request = mpt3sas_base_get_msg_frame(ioc, smid); 7262 ioc->base_cmds.smid = smid; 7263 memset(request, 0, ioc->request_sz); 7264 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 7265 init_completion(&ioc->base_cmds.done); 7266 ioc->put_smid_default(ioc, smid); 7267 wait_for_completion_timeout(&ioc->base_cmds.done, 7268 msecs_to_jiffies(10000)); 7269 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7270 mpt3sas_check_cmd_timeout(ioc, 7271 ioc->base_cmds.status, mpi_request, 7272 sizeof(Mpi2SepRequest_t)/4, issue_reset); 7273 goto issue_host_reset; 7274 } 7275 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 7276 memcpy(mpi_reply, ioc->base_cmds.reply, 7277 sizeof(Mpi2SepReply_t)); 7278 else 7279 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 7280 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7281 goto out; 7282 7283 issue_host_reset: 7284 if (issue_reset) 7285 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 7286 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7287 rc = -EFAULT; 7288 out: 7289 mutex_unlock(&ioc->base_cmds.mutex); 7290 return rc; 7291 } 7292 7293 /** 7294 * _base_get_port_facts - obtain port facts reply and save in ioc 7295 * @ioc: per adapter object 7296 * @port: ? 7297 * 7298 * Return: 0 for success, non-zero for failure. 7299 */ 7300 static int 7301 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) 7302 { 7303 Mpi2PortFactsRequest_t mpi_request; 7304 Mpi2PortFactsReply_t mpi_reply; 7305 struct mpt3sas_port_facts *pfacts; 7306 int mpi_reply_sz, mpi_request_sz, r; 7307 7308 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7309 7310 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 7311 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 7312 memset(&mpi_request, 0, mpi_request_sz); 7313 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 7314 mpi_request.PortNumber = port; 7315 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 7316 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 7317 7318 if (r != 0) { 7319 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7320 return r; 7321 } 7322 7323 pfacts = &ioc->pfacts[port]; 7324 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 7325 pfacts->PortNumber = mpi_reply.PortNumber; 7326 pfacts->VP_ID = mpi_reply.VP_ID; 7327 pfacts->VF_ID = mpi_reply.VF_ID; 7328 pfacts->MaxPostedCmdBuffers = 7329 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 7330 7331 return 0; 7332 } 7333 7334 /** 7335 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 7336 * @ioc: per adapter object 7337 * @timeout: 7338 * 7339 * Return: 0 for success, non-zero for failure. 7340 */ 7341 static int 7342 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) 7343 { 7344 u32 ioc_state; 7345 int rc; 7346 7347 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7348 7349 if (ioc->pci_error_recovery) { 7350 dfailprintk(ioc, 7351 ioc_info(ioc, "%s: host in pci error recovery\n", 7352 __func__)); 7353 return -EFAULT; 7354 } 7355 7356 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 7357 dhsprintk(ioc, 7358 ioc_info(ioc, "%s: ioc_state(0x%08x)\n", 7359 __func__, ioc_state)); 7360 7361 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 7362 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 7363 return 0; 7364 7365 if (ioc_state & MPI2_DOORBELL_USED) { 7366 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n")); 7367 goto issue_diag_reset; 7368 } 7369 7370 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 7371 mpt3sas_print_fault_code(ioc, ioc_state & 7372 MPI2_DOORBELL_DATA_MASK); 7373 goto issue_diag_reset; 7374 } else if ((ioc_state & MPI2_IOC_STATE_MASK) == 7375 MPI2_IOC_STATE_COREDUMP) { 7376 ioc_info(ioc, 7377 "%s: Skipping the diag reset here. (ioc_state=0x%x)\n", 7378 __func__, ioc_state); 7379 return -EFAULT; 7380 } 7381 7382 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 7383 if (ioc_state) { 7384 dfailprintk(ioc, 7385 ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 7386 __func__, ioc_state)); 7387 return -EFAULT; 7388 } 7389 7390 issue_diag_reset: 7391 rc = _base_diag_reset(ioc); 7392 return rc; 7393 } 7394 7395 /** 7396 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 7397 * @ioc: per adapter object 7398 * 7399 * Return: 0 for success, non-zero for failure. 7400 */ 7401 static int 7402 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 7403 { 7404 Mpi2IOCFactsRequest_t mpi_request; 7405 Mpi2IOCFactsReply_t mpi_reply; 7406 struct mpt3sas_facts *facts; 7407 int mpi_reply_sz, mpi_request_sz, r; 7408 7409 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7410 7411 r = _base_wait_for_iocstate(ioc, 10); 7412 if (r) { 7413 dfailprintk(ioc, 7414 ioc_info(ioc, "%s: failed getting to correct state\n", 7415 __func__)); 7416 return r; 7417 } 7418 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 7419 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 7420 memset(&mpi_request, 0, mpi_request_sz); 7421 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 7422 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 7423 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 7424 7425 if (r != 0) { 7426 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7427 return r; 7428 } 7429 7430 facts = &ioc->facts; 7431 memset(facts, 0, sizeof(struct mpt3sas_facts)); 7432 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 7433 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 7434 facts->VP_ID = mpi_reply.VP_ID; 7435 facts->VF_ID = mpi_reply.VF_ID; 7436 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 7437 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 7438 facts->WhoInit = mpi_reply.WhoInit; 7439 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 7440 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 7441 if (ioc->msix_enable && (facts->MaxMSIxVectors <= 7442 MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) 7443 ioc->combined_reply_queue = 0; 7444 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 7445 facts->MaxReplyDescriptorPostQueueDepth = 7446 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 7447 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 7448 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 7449 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 7450 ioc->ir_firmware = 1; 7451 if ((facts->IOCCapabilities & 7452 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) 7453 ioc->rdpq_array_capable = 1; 7454 if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) 7455 && ioc->is_aero_ioc) 7456 ioc->atomic_desc_capable = 1; 7457 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 7458 facts->IOCRequestFrameSize = 7459 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 7460 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 7461 facts->IOCMaxChainSegmentSize = 7462 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); 7463 } 7464 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 7465 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 7466 ioc->shost->max_id = -1; 7467 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 7468 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 7469 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 7470 facts->HighPriorityCredit = 7471 le16_to_cpu(mpi_reply.HighPriorityCredit); 7472 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 7473 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 7474 facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; 7475 7476 /* 7477 * Get the Page Size from IOC Facts. If it's 0, default to 4k. 7478 */ 7479 ioc->page_size = 1 << facts->CurrentHostPageSize; 7480 if (ioc->page_size == 1) { 7481 ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n"); 7482 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; 7483 } 7484 dinitprintk(ioc, 7485 ioc_info(ioc, "CurrentHostPageSize(%d)\n", 7486 facts->CurrentHostPageSize)); 7487 7488 dinitprintk(ioc, 7489 ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n", 7490 facts->RequestCredit, facts->MaxChainDepth)); 7491 dinitprintk(ioc, 7492 ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n", 7493 facts->IOCRequestFrameSize * 4, 7494 facts->ReplyFrameSize * 4)); 7495 return 0; 7496 } 7497 7498 /** 7499 * _base_send_ioc_init - send ioc_init to firmware 7500 * @ioc: per adapter object 7501 * 7502 * Return: 0 for success, non-zero for failure. 7503 */ 7504 static int 7505 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) 7506 { 7507 Mpi2IOCInitRequest_t mpi_request; 7508 Mpi2IOCInitReply_t mpi_reply; 7509 int i, r = 0; 7510 ktime_t current_time; 7511 u16 ioc_status; 7512 u32 reply_post_free_array_sz = 0; 7513 7514 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7515 7516 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 7517 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 7518 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 7519 mpi_request.VF_ID = 0; /* TODO */ 7520 mpi_request.VP_ID = 0; 7521 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 7522 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 7523 mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; 7524 7525 if (_base_is_controller_msix_enabled(ioc)) 7526 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 7527 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 7528 mpi_request.ReplyDescriptorPostQueueDepth = 7529 cpu_to_le16(ioc->reply_post_queue_depth); 7530 mpi_request.ReplyFreeQueueDepth = 7531 cpu_to_le16(ioc->reply_free_queue_depth); 7532 7533 mpi_request.SenseBufferAddressHigh = 7534 cpu_to_le32((u64)ioc->sense_dma >> 32); 7535 mpi_request.SystemReplyAddressHigh = 7536 cpu_to_le32((u64)ioc->reply_dma >> 32); 7537 mpi_request.SystemRequestFrameBaseAddress = 7538 cpu_to_le64((u64)ioc->request_dma); 7539 mpi_request.ReplyFreeQueueAddress = 7540 cpu_to_le64((u64)ioc->reply_free_dma); 7541 7542 if (ioc->rdpq_array_enable) { 7543 reply_post_free_array_sz = ioc->reply_queue_count * 7544 sizeof(Mpi2IOCInitRDPQArrayEntry); 7545 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz); 7546 for (i = 0; i < ioc->reply_queue_count; i++) 7547 ioc->reply_post_free_array[i].RDPQBaseAddress = 7548 cpu_to_le64( 7549 (u64)ioc->reply_post[i].reply_post_free_dma); 7550 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 7551 mpi_request.ReplyDescriptorPostQueueAddress = 7552 cpu_to_le64((u64)ioc->reply_post_free_array_dma); 7553 } else { 7554 mpi_request.ReplyDescriptorPostQueueAddress = 7555 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 7556 } 7557 7558 /* 7559 * Set the flag to enable CoreDump state feature in IOC firmware. 7560 */ 7561 mpi_request.ConfigurationFlags |= 7562 cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE); 7563 7564 /* This time stamp specifies number of milliseconds 7565 * since epoch ~ midnight January 1, 1970. 7566 */ 7567 current_time = ktime_get_real(); 7568 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); 7569 7570 if (ioc->logging_level & MPT_DEBUG_INIT) { 7571 __le32 *mfp; 7572 int i; 7573 7574 mfp = (__le32 *)&mpi_request; 7575 ioc_info(ioc, "\toffset:data\n"); 7576 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 7577 ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, 7578 le32_to_cpu(mfp[i])); 7579 } 7580 7581 r = _base_handshake_req_reply_wait(ioc, 7582 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 7583 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30); 7584 7585 if (r != 0) { 7586 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7587 return r; 7588 } 7589 7590 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 7591 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 7592 mpi_reply.IOCLogInfo) { 7593 ioc_err(ioc, "%s: failed\n", __func__); 7594 r = -EIO; 7595 } 7596 7597 /* Reset TimeSync Counter*/ 7598 ioc->timestamp_update_count = 0; 7599 return r; 7600 } 7601 7602 /** 7603 * mpt3sas_port_enable_done - command completion routine for port enable 7604 * @ioc: per adapter object 7605 * @smid: system request message index 7606 * @msix_index: MSIX table index supplied by the OS 7607 * @reply: reply message frame(lower 32bit addr) 7608 * 7609 * Return: 1 meaning mf should be freed from _base_interrupt 7610 * 0 means the mf is freed from this function. 7611 */ 7612 u8 7613 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 7614 u32 reply) 7615 { 7616 MPI2DefaultReply_t *mpi_reply; 7617 u16 ioc_status; 7618 7619 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 7620 return 1; 7621 7622 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 7623 if (!mpi_reply) 7624 return 1; 7625 7626 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 7627 return 1; 7628 7629 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 7630 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 7631 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 7632 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 7633 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 7634 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 7635 ioc->port_enable_failed = 1; 7636 7637 if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) { 7638 ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC; 7639 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 7640 mpt3sas_port_enable_complete(ioc); 7641 return 1; 7642 } else { 7643 ioc->start_scan_failed = ioc_status; 7644 ioc->start_scan = 0; 7645 return 1; 7646 } 7647 } 7648 complete(&ioc->port_enable_cmds.done); 7649 return 1; 7650 } 7651 7652 /** 7653 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 7654 * @ioc: per adapter object 7655 * 7656 * Return: 0 for success, non-zero for failure. 7657 */ 7658 static int 7659 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) 7660 { 7661 Mpi2PortEnableRequest_t *mpi_request; 7662 Mpi2PortEnableReply_t *mpi_reply; 7663 int r = 0; 7664 u16 smid; 7665 u16 ioc_status; 7666 7667 ioc_info(ioc, "sending port enable !!\n"); 7668 7669 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 7670 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7671 return -EAGAIN; 7672 } 7673 7674 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 7675 if (!smid) { 7676 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7677 return -EAGAIN; 7678 } 7679 7680 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 7681 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7682 ioc->port_enable_cmds.smid = smid; 7683 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 7684 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 7685 7686 init_completion(&ioc->port_enable_cmds.done); 7687 ioc->put_smid_default(ioc, smid); 7688 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); 7689 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 7690 ioc_err(ioc, "%s: timeout\n", __func__); 7691 _debug_dump_mf(mpi_request, 7692 sizeof(Mpi2PortEnableRequest_t)/4); 7693 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 7694 r = -EFAULT; 7695 else 7696 r = -ETIME; 7697 goto out; 7698 } 7699 7700 mpi_reply = ioc->port_enable_cmds.reply; 7701 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 7702 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 7703 ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n", 7704 __func__, ioc_status); 7705 r = -EFAULT; 7706 goto out; 7707 } 7708 7709 out: 7710 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 7711 ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED"); 7712 return r; 7713 } 7714 7715 /** 7716 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 7717 * @ioc: per adapter object 7718 * 7719 * Return: 0 for success, non-zero for failure. 7720 */ 7721 int 7722 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 7723 { 7724 Mpi2PortEnableRequest_t *mpi_request; 7725 u16 smid; 7726 7727 ioc_info(ioc, "sending port enable !!\n"); 7728 7729 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 7730 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7731 return -EAGAIN; 7732 } 7733 7734 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 7735 if (!smid) { 7736 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7737 return -EAGAIN; 7738 } 7739 ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED; 7740 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 7741 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC; 7742 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7743 ioc->port_enable_cmds.smid = smid; 7744 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 7745 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 7746 7747 ioc->put_smid_default(ioc, smid); 7748 return 0; 7749 } 7750 7751 /** 7752 * _base_determine_wait_on_discovery - desposition 7753 * @ioc: per adapter object 7754 * 7755 * Decide whether to wait on discovery to complete. Used to either 7756 * locate boot device, or report volumes ahead of physical devices. 7757 * 7758 * Return: 1 for wait, 0 for don't wait. 7759 */ 7760 static int 7761 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 7762 { 7763 /* We wait for discovery to complete if IR firmware is loaded. 7764 * The sas topology events arrive before PD events, so we need time to 7765 * turn on the bit in ioc->pd_handles to indicate PD 7766 * Also, it maybe required to report Volumes ahead of physical 7767 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 7768 */ 7769 if (ioc->ir_firmware) 7770 return 1; 7771 7772 /* if no Bios, then we don't need to wait */ 7773 if (!ioc->bios_pg3.BiosVersion) 7774 return 0; 7775 7776 /* Bios is present, then we drop down here. 7777 * 7778 * If there any entries in the Bios Page 2, then we wait 7779 * for discovery to complete. 7780 */ 7781 7782 /* Current Boot Device */ 7783 if ((ioc->bios_pg2.CurrentBootDeviceForm & 7784 MPI2_BIOSPAGE2_FORM_MASK) == 7785 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 7786 /* Request Boot Device */ 7787 (ioc->bios_pg2.ReqBootDeviceForm & 7788 MPI2_BIOSPAGE2_FORM_MASK) == 7789 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 7790 /* Alternate Request Boot Device */ 7791 (ioc->bios_pg2.ReqAltBootDeviceForm & 7792 MPI2_BIOSPAGE2_FORM_MASK) == 7793 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 7794 return 0; 7795 7796 return 1; 7797 } 7798 7799 /** 7800 * _base_unmask_events - turn on notification for this event 7801 * @ioc: per adapter object 7802 * @event: firmware event 7803 * 7804 * The mask is stored in ioc->event_masks. 7805 */ 7806 static void 7807 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 7808 { 7809 u32 desired_event; 7810 7811 if (event >= 128) 7812 return; 7813 7814 desired_event = (1 << (event % 32)); 7815 7816 if (event < 32) 7817 ioc->event_masks[0] &= ~desired_event; 7818 else if (event < 64) 7819 ioc->event_masks[1] &= ~desired_event; 7820 else if (event < 96) 7821 ioc->event_masks[2] &= ~desired_event; 7822 else if (event < 128) 7823 ioc->event_masks[3] &= ~desired_event; 7824 } 7825 7826 /** 7827 * _base_event_notification - send event notification 7828 * @ioc: per adapter object 7829 * 7830 * Return: 0 for success, non-zero for failure. 7831 */ 7832 static int 7833 _base_event_notification(struct MPT3SAS_ADAPTER *ioc) 7834 { 7835 Mpi2EventNotificationRequest_t *mpi_request; 7836 u16 smid; 7837 int r = 0; 7838 int i, issue_diag_reset = 0; 7839 7840 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7841 7842 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 7843 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7844 return -EAGAIN; 7845 } 7846 7847 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 7848 if (!smid) { 7849 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7850 return -EAGAIN; 7851 } 7852 ioc->base_cmds.status = MPT3_CMD_PENDING; 7853 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7854 ioc->base_cmds.smid = smid; 7855 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 7856 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 7857 mpi_request->VF_ID = 0; /* TODO */ 7858 mpi_request->VP_ID = 0; 7859 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 7860 mpi_request->EventMasks[i] = 7861 cpu_to_le32(ioc->event_masks[i]); 7862 init_completion(&ioc->base_cmds.done); 7863 ioc->put_smid_default(ioc, smid); 7864 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 7865 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7866 ioc_err(ioc, "%s: timeout\n", __func__); 7867 _debug_dump_mf(mpi_request, 7868 sizeof(Mpi2EventNotificationRequest_t)/4); 7869 if (ioc->base_cmds.status & MPT3_CMD_RESET) 7870 r = -EFAULT; 7871 else 7872 issue_diag_reset = 1; 7873 7874 } else 7875 dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__)); 7876 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7877 7878 if (issue_diag_reset) { 7879 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) 7880 return -EFAULT; 7881 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) 7882 return -EFAULT; 7883 r = -EAGAIN; 7884 } 7885 return r; 7886 } 7887 7888 /** 7889 * mpt3sas_base_validate_event_type - validating event types 7890 * @ioc: per adapter object 7891 * @event_type: firmware event 7892 * 7893 * This will turn on firmware event notification when application 7894 * ask for that event. We don't mask events that are already enabled. 7895 */ 7896 void 7897 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 7898 { 7899 int i, j; 7900 u32 event_mask, desired_event; 7901 u8 send_update_to_fw; 7902 7903 for (i = 0, send_update_to_fw = 0; i < 7904 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 7905 event_mask = ~event_type[i]; 7906 desired_event = 1; 7907 for (j = 0; j < 32; j++) { 7908 if (!(event_mask & desired_event) && 7909 (ioc->event_masks[i] & desired_event)) { 7910 ioc->event_masks[i] &= ~desired_event; 7911 send_update_to_fw = 1; 7912 } 7913 desired_event = (desired_event << 1); 7914 } 7915 } 7916 7917 if (!send_update_to_fw) 7918 return; 7919 7920 mutex_lock(&ioc->base_cmds.mutex); 7921 _base_event_notification(ioc); 7922 mutex_unlock(&ioc->base_cmds.mutex); 7923 } 7924 7925 /** 7926 * _base_diag_reset - the "big hammer" start of day reset 7927 * @ioc: per adapter object 7928 * 7929 * Return: 0 for success, non-zero for failure. 7930 */ 7931 static int 7932 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) 7933 { 7934 u32 host_diagnostic; 7935 u32 ioc_state; 7936 u32 count; 7937 u32 hcb_size; 7938 7939 ioc_info(ioc, "sending diag reset !!\n"); 7940 7941 pci_cfg_access_lock(ioc->pdev); 7942 7943 drsprintk(ioc, ioc_info(ioc, "clear interrupts\n")); 7944 7945 count = 0; 7946 do { 7947 /* Write magic sequence to WriteSequence register 7948 * Loop until in diagnostic mode 7949 */ 7950 drsprintk(ioc, ioc_info(ioc, "write magic sequence\n")); 7951 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 7952 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 7953 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 7954 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 7955 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 7956 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 7957 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 7958 7959 /* wait 100 msec */ 7960 msleep(100); 7961 7962 if (count++ > 20) { 7963 ioc_info(ioc, 7964 "Stop writing magic sequence after 20 retries\n"); 7965 _base_dump_reg_set(ioc); 7966 goto out; 7967 } 7968 7969 host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic); 7970 drsprintk(ioc, 7971 ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 7972 count, host_diagnostic)); 7973 7974 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 7975 7976 hcb_size = ioc->base_readl(&ioc->chip->HCBSize); 7977 7978 drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n")); 7979 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 7980 &ioc->chip->HostDiagnostic); 7981 7982 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 7983 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 7984 7985 /* Approximately 300 second max wait */ 7986 for (count = 0; count < (300000000 / 7987 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 7988 7989 host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic); 7990 7991 if (host_diagnostic == 0xFFFFFFFF) { 7992 ioc_info(ioc, 7993 "Invalid host diagnostic register value\n"); 7994 _base_dump_reg_set(ioc); 7995 goto out; 7996 } 7997 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 7998 break; 7999 8000 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); 8001 } 8002 8003 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 8004 8005 drsprintk(ioc, 8006 ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n")); 8007 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 8008 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 8009 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 8010 8011 drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n")); 8012 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 8013 &ioc->chip->HCBSize); 8014 } 8015 8016 drsprintk(ioc, ioc_info(ioc, "restart the adapter\n")); 8017 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 8018 &ioc->chip->HostDiagnostic); 8019 8020 drsprintk(ioc, 8021 ioc_info(ioc, "disable writes to the diagnostic register\n")); 8022 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 8023 8024 drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n")); 8025 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); 8026 if (ioc_state) { 8027 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 8028 __func__, ioc_state); 8029 _base_dump_reg_set(ioc); 8030 goto out; 8031 } 8032 8033 pci_cfg_access_unlock(ioc->pdev); 8034 ioc_info(ioc, "diag reset: SUCCESS\n"); 8035 return 0; 8036 8037 out: 8038 pci_cfg_access_unlock(ioc->pdev); 8039 ioc_err(ioc, "diag reset: FAILED\n"); 8040 return -EFAULT; 8041 } 8042 8043 /** 8044 * mpt3sas_base_make_ioc_ready - put controller in READY state 8045 * @ioc: per adapter object 8046 * @type: FORCE_BIG_HAMMER or SOFT_RESET 8047 * 8048 * Return: 0 for success, non-zero for failure. 8049 */ 8050 int 8051 mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) 8052 { 8053 u32 ioc_state; 8054 int rc; 8055 int count; 8056 8057 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8058 8059 if (ioc->pci_error_recovery) 8060 return 0; 8061 8062 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8063 dhsprintk(ioc, 8064 ioc_info(ioc, "%s: ioc_state(0x%08x)\n", 8065 __func__, ioc_state)); 8066 8067 /* if in RESET state, it should move to READY state shortly */ 8068 count = 0; 8069 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 8070 while ((ioc_state & MPI2_IOC_STATE_MASK) != 8071 MPI2_IOC_STATE_READY) { 8072 if (count++ == 10) { 8073 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 8074 __func__, ioc_state); 8075 return -EFAULT; 8076 } 8077 ssleep(1); 8078 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8079 } 8080 } 8081 8082 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 8083 return 0; 8084 8085 if (ioc_state & MPI2_DOORBELL_USED) { 8086 ioc_info(ioc, "unexpected doorbell active!\n"); 8087 goto issue_diag_reset; 8088 } 8089 8090 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 8091 mpt3sas_print_fault_code(ioc, ioc_state & 8092 MPI2_DOORBELL_DATA_MASK); 8093 goto issue_diag_reset; 8094 } 8095 8096 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { 8097 /* 8098 * if host reset is invoked while watch dog thread is waiting 8099 * for IOC state to be changed to Fault state then driver has 8100 * to wait here for CoreDump state to clear otherwise reset 8101 * will be issued to the FW and FW move the IOC state to 8102 * reset state without copying the FW logs to coredump region. 8103 */ 8104 if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) { 8105 mpt3sas_print_coredump_info(ioc, ioc_state & 8106 MPI2_DOORBELL_DATA_MASK); 8107 mpt3sas_base_wait_for_coredump_completion(ioc, 8108 __func__); 8109 } 8110 goto issue_diag_reset; 8111 } 8112 8113 if (type == FORCE_BIG_HAMMER) 8114 goto issue_diag_reset; 8115 8116 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 8117 if (!(_base_send_ioc_reset(ioc, 8118 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { 8119 return 0; 8120 } 8121 8122 issue_diag_reset: 8123 rc = _base_diag_reset(ioc); 8124 return rc; 8125 } 8126 8127 /** 8128 * _base_make_ioc_operational - put controller in OPERATIONAL state 8129 * @ioc: per adapter object 8130 * 8131 * Return: 0 for success, non-zero for failure. 8132 */ 8133 static int 8134 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) 8135 { 8136 int r, i, index, rc; 8137 unsigned long flags; 8138 u32 reply_address; 8139 u16 smid; 8140 struct _tr_list *delayed_tr, *delayed_tr_next; 8141 struct _sc_list *delayed_sc, *delayed_sc_next; 8142 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; 8143 u8 hide_flag; 8144 struct adapter_reply_queue *reply_q; 8145 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; 8146 8147 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8148 8149 /* clean the delayed target reset list */ 8150 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 8151 &ioc->delayed_tr_list, list) { 8152 list_del(&delayed_tr->list); 8153 kfree(delayed_tr); 8154 } 8155 8156 8157 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 8158 &ioc->delayed_tr_volume_list, list) { 8159 list_del(&delayed_tr->list); 8160 kfree(delayed_tr); 8161 } 8162 8163 list_for_each_entry_safe(delayed_sc, delayed_sc_next, 8164 &ioc->delayed_sc_list, list) { 8165 list_del(&delayed_sc->list); 8166 kfree(delayed_sc); 8167 } 8168 8169 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, 8170 &ioc->delayed_event_ack_list, list) { 8171 list_del(&delayed_event_ack->list); 8172 kfree(delayed_event_ack); 8173 } 8174 8175 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 8176 8177 /* hi-priority queue */ 8178 INIT_LIST_HEAD(&ioc->hpr_free_list); 8179 smid = ioc->hi_priority_smid; 8180 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 8181 ioc->hpr_lookup[i].cb_idx = 0xFF; 8182 ioc->hpr_lookup[i].smid = smid; 8183 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 8184 &ioc->hpr_free_list); 8185 } 8186 8187 /* internal queue */ 8188 INIT_LIST_HEAD(&ioc->internal_free_list); 8189 smid = ioc->internal_smid; 8190 for (i = 0; i < ioc->internal_depth; i++, smid++) { 8191 ioc->internal_lookup[i].cb_idx = 0xFF; 8192 ioc->internal_lookup[i].smid = smid; 8193 list_add_tail(&ioc->internal_lookup[i].tracker_list, 8194 &ioc->internal_free_list); 8195 } 8196 8197 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 8198 8199 /* initialize Reply Free Queue */ 8200 for (i = 0, reply_address = (u32)ioc->reply_dma ; 8201 i < ioc->reply_free_queue_depth ; i++, reply_address += 8202 ioc->reply_sz) { 8203 ioc->reply_free[i] = cpu_to_le32(reply_address); 8204 if (ioc->is_mcpu_endpoint) 8205 _base_clone_reply_to_sys_mem(ioc, 8206 reply_address, i); 8207 } 8208 8209 /* initialize reply queues */ 8210 if (ioc->is_driver_loading) 8211 _base_assign_reply_queues(ioc); 8212 8213 /* initialize Reply Post Free Queue */ 8214 index = 0; 8215 reply_post_free_contig = ioc->reply_post[0].reply_post_free; 8216 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 8217 /* 8218 * If RDPQ is enabled, switch to the next allocation. 8219 * Otherwise advance within the contiguous region. 8220 */ 8221 if (ioc->rdpq_array_enable) { 8222 reply_q->reply_post_free = 8223 ioc->reply_post[index++].reply_post_free; 8224 } else { 8225 reply_q->reply_post_free = reply_post_free_contig; 8226 reply_post_free_contig += ioc->reply_post_queue_depth; 8227 } 8228 8229 reply_q->reply_post_host_index = 0; 8230 for (i = 0; i < ioc->reply_post_queue_depth; i++) 8231 reply_q->reply_post_free[i].Words = 8232 cpu_to_le64(ULLONG_MAX); 8233 if (!_base_is_controller_msix_enabled(ioc)) 8234 goto skip_init_reply_post_free_queue; 8235 } 8236 skip_init_reply_post_free_queue: 8237 8238 r = _base_send_ioc_init(ioc); 8239 if (r) { 8240 /* 8241 * No need to check IOC state for fault state & issue 8242 * diag reset during host reset. This check is need 8243 * only during driver load time. 8244 */ 8245 if (!ioc->is_driver_loading) 8246 return r; 8247 8248 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8249 if (rc || (_base_send_ioc_init(ioc))) 8250 return r; 8251 } 8252 8253 /* initialize reply free host index */ 8254 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 8255 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 8256 8257 /* initialize reply post host index */ 8258 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 8259 if (ioc->combined_reply_queue) 8260 writel((reply_q->msix_index & 7)<< 8261 MPI2_RPHI_MSIX_INDEX_SHIFT, 8262 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 8263 else 8264 writel(reply_q->msix_index << 8265 MPI2_RPHI_MSIX_INDEX_SHIFT, 8266 &ioc->chip->ReplyPostHostIndex); 8267 8268 if (!_base_is_controller_msix_enabled(ioc)) 8269 goto skip_init_reply_post_host_index; 8270 } 8271 8272 skip_init_reply_post_host_index: 8273 8274 mpt3sas_base_unmask_interrupts(ioc); 8275 8276 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 8277 r = _base_display_fwpkg_version(ioc); 8278 if (r) 8279 return r; 8280 } 8281 8282 r = _base_static_config_pages(ioc); 8283 if (r) 8284 return r; 8285 8286 r = _base_event_notification(ioc); 8287 if (r) 8288 return r; 8289 8290 if (!ioc->shost_recovery) { 8291 8292 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 8293 == 0x80) { 8294 hide_flag = (u8) ( 8295 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 8296 MFG_PAGE10_HIDE_SSDS_MASK); 8297 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 8298 ioc->mfg_pg10_hide_flag = hide_flag; 8299 } 8300 8301 ioc->wait_for_discovery_to_complete = 8302 _base_determine_wait_on_discovery(ioc); 8303 8304 return r; /* scan_start and scan_finished support */ 8305 } 8306 8307 r = _base_send_port_enable(ioc); 8308 if (r) 8309 return r; 8310 8311 return r; 8312 } 8313 8314 /** 8315 * mpt3sas_base_free_resources - free resources controller resources 8316 * @ioc: per adapter object 8317 */ 8318 void 8319 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 8320 { 8321 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8322 8323 /* synchronizing freeing resource with pci_access_mutex lock */ 8324 mutex_lock(&ioc->pci_access_mutex); 8325 if (ioc->chip_phys && ioc->chip) { 8326 mpt3sas_base_mask_interrupts(ioc); 8327 ioc->shost_recovery = 1; 8328 mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); 8329 ioc->shost_recovery = 0; 8330 } 8331 8332 mpt3sas_base_unmap_resources(ioc); 8333 mutex_unlock(&ioc->pci_access_mutex); 8334 return; 8335 } 8336 8337 /** 8338 * mpt3sas_base_attach - attach controller instance 8339 * @ioc: per adapter object 8340 * 8341 * Return: 0 for success, non-zero for failure. 8342 */ 8343 int 8344 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 8345 { 8346 int r, i, rc; 8347 int cpu_id, last_cpu_id = 0; 8348 8349 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8350 8351 /* setup cpu_msix_table */ 8352 ioc->cpu_count = num_online_cpus(); 8353 for_each_online_cpu(cpu_id) 8354 last_cpu_id = cpu_id; 8355 ioc->cpu_msix_table_sz = last_cpu_id + 1; 8356 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 8357 ioc->reply_queue_count = 1; 8358 if (!ioc->cpu_msix_table) { 8359 ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n"); 8360 r = -ENOMEM; 8361 goto out_free_resources; 8362 } 8363 8364 if (ioc->is_warpdrive) { 8365 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 8366 sizeof(resource_size_t *), GFP_KERNEL); 8367 if (!ioc->reply_post_host_index) { 8368 ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n"); 8369 r = -ENOMEM; 8370 goto out_free_resources; 8371 } 8372 } 8373 8374 ioc->smp_affinity_enable = smp_affinity_enable; 8375 8376 ioc->rdpq_array_enable_assigned = 0; 8377 ioc->use_32bit_dma = false; 8378 ioc->dma_mask = 64; 8379 if (ioc->is_aero_ioc) { 8380 ioc->base_readl = &_base_readl_aero; 8381 ioc->base_readl_ext_retry = &_base_readl_ext_retry; 8382 } else { 8383 ioc->base_readl = &_base_readl; 8384 ioc->base_readl_ext_retry = &_base_readl; 8385 } 8386 r = mpt3sas_base_map_resources(ioc); 8387 if (r) 8388 goto out_free_resources; 8389 8390 pci_set_drvdata(ioc->pdev, ioc->shost); 8391 r = _base_get_ioc_facts(ioc); 8392 if (r) { 8393 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8394 if (rc || (_base_get_ioc_facts(ioc))) 8395 goto out_free_resources; 8396 } 8397 8398 switch (ioc->hba_mpi_version_belonged) { 8399 case MPI2_VERSION: 8400 ioc->build_sg_scmd = &_base_build_sg_scmd; 8401 ioc->build_sg = &_base_build_sg; 8402 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 8403 ioc->get_msix_index_for_smlio = &_base_get_msix_index; 8404 break; 8405 case MPI25_VERSION: 8406 case MPI26_VERSION: 8407 /* 8408 * In SAS3.0, 8409 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 8410 * Target Status - all require the IEEE formatted scatter gather 8411 * elements. 8412 */ 8413 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 8414 ioc->build_sg = &_base_build_sg_ieee; 8415 ioc->build_nvme_prp = &_base_build_nvme_prp; 8416 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 8417 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 8418 if (ioc->high_iops_queues) 8419 ioc->get_msix_index_for_smlio = 8420 &_base_get_high_iops_msix_index; 8421 else 8422 ioc->get_msix_index_for_smlio = &_base_get_msix_index; 8423 break; 8424 } 8425 if (ioc->atomic_desc_capable) { 8426 ioc->put_smid_default = &_base_put_smid_default_atomic; 8427 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; 8428 ioc->put_smid_fast_path = 8429 &_base_put_smid_fast_path_atomic; 8430 ioc->put_smid_hi_priority = 8431 &_base_put_smid_hi_priority_atomic; 8432 } else { 8433 ioc->put_smid_default = &_base_put_smid_default; 8434 ioc->put_smid_fast_path = &_base_put_smid_fast_path; 8435 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; 8436 if (ioc->is_mcpu_endpoint) 8437 ioc->put_smid_scsi_io = 8438 &_base_put_smid_mpi_ep_scsi_io; 8439 else 8440 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; 8441 } 8442 /* 8443 * These function pointers for other requests that don't 8444 * the require IEEE scatter gather elements. 8445 * 8446 * For example Configuration Pages and SAS IOUNIT Control don't. 8447 */ 8448 ioc->build_sg_mpi = &_base_build_sg; 8449 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 8450 8451 r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); 8452 if (r) 8453 goto out_free_resources; 8454 8455 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 8456 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 8457 if (!ioc->pfacts) { 8458 r = -ENOMEM; 8459 goto out_free_resources; 8460 } 8461 8462 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 8463 r = _base_get_port_facts(ioc, i); 8464 if (r) { 8465 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8466 if (rc || (_base_get_port_facts(ioc, i))) 8467 goto out_free_resources; 8468 } 8469 } 8470 8471 r = _base_allocate_memory_pools(ioc); 8472 if (r) 8473 goto out_free_resources; 8474 8475 if (irqpoll_weight > 0) 8476 ioc->thresh_hold = irqpoll_weight; 8477 else 8478 ioc->thresh_hold = ioc->hba_queue_depth/4; 8479 8480 _base_init_irqpolls(ioc); 8481 init_waitqueue_head(&ioc->reset_wq); 8482 8483 /* allocate memory pd handle bitmask list */ 8484 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 8485 if (ioc->facts.MaxDevHandle % 8) 8486 ioc->pd_handles_sz++; 8487 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 8488 GFP_KERNEL); 8489 if (!ioc->pd_handles) { 8490 r = -ENOMEM; 8491 goto out_free_resources; 8492 } 8493 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 8494 GFP_KERNEL); 8495 if (!ioc->blocking_handles) { 8496 r = -ENOMEM; 8497 goto out_free_resources; 8498 } 8499 8500 /* allocate memory for pending OS device add list */ 8501 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); 8502 if (ioc->facts.MaxDevHandle % 8) 8503 ioc->pend_os_device_add_sz++; 8504 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, 8505 GFP_KERNEL); 8506 if (!ioc->pend_os_device_add) { 8507 r = -ENOMEM; 8508 goto out_free_resources; 8509 } 8510 8511 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; 8512 ioc->device_remove_in_progress = 8513 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); 8514 if (!ioc->device_remove_in_progress) { 8515 r = -ENOMEM; 8516 goto out_free_resources; 8517 } 8518 8519 ioc->fwfault_debug = mpt3sas_fwfault_debug; 8520 8521 /* base internal command bits */ 8522 mutex_init(&ioc->base_cmds.mutex); 8523 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8524 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 8525 8526 /* port_enable command bits */ 8527 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8528 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 8529 8530 /* transport internal command bits */ 8531 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8532 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 8533 mutex_init(&ioc->transport_cmds.mutex); 8534 8535 /* scsih internal command bits */ 8536 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8537 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 8538 mutex_init(&ioc->scsih_cmds.mutex); 8539 8540 /* task management internal command bits */ 8541 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8542 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 8543 mutex_init(&ioc->tm_cmds.mutex); 8544 8545 /* config page internal command bits */ 8546 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8547 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 8548 mutex_init(&ioc->config_cmds.mutex); 8549 8550 /* ctl module internal command bits */ 8551 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8552 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 8553 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 8554 mutex_init(&ioc->ctl_cmds.mutex); 8555 8556 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || 8557 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || 8558 !ioc->tm_cmds.reply || !ioc->config_cmds.reply || 8559 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { 8560 r = -ENOMEM; 8561 goto out_free_resources; 8562 } 8563 8564 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 8565 ioc->event_masks[i] = -1; 8566 8567 /* here we enable the events we care about */ 8568 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 8569 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 8570 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 8571 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 8572 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 8573 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 8574 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 8575 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 8576 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 8577 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 8578 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 8579 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); 8580 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 8581 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) { 8582 if (ioc->is_gen35_ioc) { 8583 _base_unmask_events(ioc, 8584 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE); 8585 _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION); 8586 _base_unmask_events(ioc, 8587 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 8588 } 8589 } 8590 r = _base_make_ioc_operational(ioc); 8591 if (r == -EAGAIN) { 8592 r = _base_make_ioc_operational(ioc); 8593 if (r) 8594 goto out_free_resources; 8595 } 8596 8597 /* 8598 * Copy current copy of IOCFacts in prev_fw_facts 8599 * and it will be used during online firmware upgrade. 8600 */ 8601 memcpy(&ioc->prev_fw_facts, &ioc->facts, 8602 sizeof(struct mpt3sas_facts)); 8603 8604 ioc->non_operational_loop = 0; 8605 ioc->ioc_coredump_loop = 0; 8606 ioc->got_task_abort_from_ioctl = 0; 8607 return 0; 8608 8609 out_free_resources: 8610 8611 ioc->remove_host = 1; 8612 8613 mpt3sas_base_free_resources(ioc); 8614 _base_release_memory_pools(ioc); 8615 pci_set_drvdata(ioc->pdev, NULL); 8616 kfree(ioc->cpu_msix_table); 8617 if (ioc->is_warpdrive) 8618 kfree(ioc->reply_post_host_index); 8619 kfree(ioc->pd_handles); 8620 kfree(ioc->blocking_handles); 8621 kfree(ioc->device_remove_in_progress); 8622 kfree(ioc->pend_os_device_add); 8623 kfree(ioc->tm_cmds.reply); 8624 kfree(ioc->transport_cmds.reply); 8625 kfree(ioc->scsih_cmds.reply); 8626 kfree(ioc->config_cmds.reply); 8627 kfree(ioc->base_cmds.reply); 8628 kfree(ioc->port_enable_cmds.reply); 8629 kfree(ioc->ctl_cmds.reply); 8630 kfree(ioc->ctl_cmds.sense); 8631 kfree(ioc->pfacts); 8632 ioc->ctl_cmds.reply = NULL; 8633 ioc->base_cmds.reply = NULL; 8634 ioc->tm_cmds.reply = NULL; 8635 ioc->scsih_cmds.reply = NULL; 8636 ioc->transport_cmds.reply = NULL; 8637 ioc->config_cmds.reply = NULL; 8638 ioc->pfacts = NULL; 8639 return r; 8640 } 8641 8642 8643 /** 8644 * mpt3sas_base_detach - remove controller instance 8645 * @ioc: per adapter object 8646 */ 8647 void 8648 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 8649 { 8650 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8651 8652 mpt3sas_base_stop_watchdog(ioc); 8653 mpt3sas_base_free_resources(ioc); 8654 _base_release_memory_pools(ioc); 8655 mpt3sas_free_enclosure_list(ioc); 8656 pci_set_drvdata(ioc->pdev, NULL); 8657 kfree(ioc->cpu_msix_table); 8658 if (ioc->is_warpdrive) 8659 kfree(ioc->reply_post_host_index); 8660 kfree(ioc->pd_handles); 8661 kfree(ioc->blocking_handles); 8662 kfree(ioc->device_remove_in_progress); 8663 kfree(ioc->pend_os_device_add); 8664 kfree(ioc->pfacts); 8665 kfree(ioc->ctl_cmds.reply); 8666 kfree(ioc->ctl_cmds.sense); 8667 kfree(ioc->base_cmds.reply); 8668 kfree(ioc->port_enable_cmds.reply); 8669 kfree(ioc->tm_cmds.reply); 8670 kfree(ioc->transport_cmds.reply); 8671 kfree(ioc->scsih_cmds.reply); 8672 kfree(ioc->config_cmds.reply); 8673 } 8674 8675 /** 8676 * _base_pre_reset_handler - pre reset handler 8677 * @ioc: per adapter object 8678 */ 8679 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc) 8680 { 8681 mpt3sas_scsih_pre_reset_handler(ioc); 8682 mpt3sas_ctl_pre_reset_handler(ioc); 8683 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__)); 8684 } 8685 8686 /** 8687 * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands 8688 * @ioc: per adapter object 8689 */ 8690 static void 8691 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc) 8692 { 8693 dtmprintk(ioc, 8694 ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__)); 8695 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 8696 ioc->transport_cmds.status |= MPT3_CMD_RESET; 8697 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 8698 complete(&ioc->transport_cmds.done); 8699 } 8700 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 8701 ioc->base_cmds.status |= MPT3_CMD_RESET; 8702 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 8703 complete(&ioc->base_cmds.done); 8704 } 8705 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 8706 ioc->port_enable_failed = 1; 8707 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 8708 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 8709 if (ioc->is_driver_loading) { 8710 ioc->start_scan_failed = 8711 MPI2_IOCSTATUS_INTERNAL_ERROR; 8712 ioc->start_scan = 0; 8713 } else { 8714 complete(&ioc->port_enable_cmds.done); 8715 } 8716 } 8717 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 8718 ioc->config_cmds.status |= MPT3_CMD_RESET; 8719 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 8720 ioc->config_cmds.smid = USHRT_MAX; 8721 complete(&ioc->config_cmds.done); 8722 } 8723 } 8724 8725 /** 8726 * _base_clear_outstanding_commands - clear all outstanding commands 8727 * @ioc: per adapter object 8728 */ 8729 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc) 8730 { 8731 mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc); 8732 mpt3sas_ctl_clear_outstanding_ioctls(ioc); 8733 _base_clear_outstanding_mpt_commands(ioc); 8734 } 8735 8736 /** 8737 * _base_reset_done_handler - reset done handler 8738 * @ioc: per adapter object 8739 */ 8740 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc) 8741 { 8742 mpt3sas_scsih_reset_done_handler(ioc); 8743 mpt3sas_ctl_reset_done_handler(ioc); 8744 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__)); 8745 } 8746 8747 /** 8748 * mpt3sas_wait_for_commands_to_complete - reset controller 8749 * @ioc: Pointer to MPT_ADAPTER structure 8750 * 8751 * This function is waiting 10s for all pending commands to complete 8752 * prior to putting controller in reset. 8753 */ 8754 void 8755 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) 8756 { 8757 u32 ioc_state; 8758 8759 ioc->pending_io_count = 0; 8760 8761 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8762 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 8763 return; 8764 8765 /* pending command count */ 8766 ioc->pending_io_count = scsi_host_busy(ioc->shost); 8767 8768 if (!ioc->pending_io_count) 8769 return; 8770 8771 /* wait for pending commands to complete */ 8772 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 8773 } 8774 8775 /** 8776 * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts 8777 * attributes during online firmware upgrade and update the corresponding 8778 * IOC variables accordingly. 8779 * 8780 * @ioc: Pointer to MPT_ADAPTER structure 8781 */ 8782 static int 8783 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc) 8784 { 8785 u16 pd_handles_sz; 8786 void *pd_handles = NULL, *blocking_handles = NULL; 8787 void *pend_os_device_add = NULL, *device_remove_in_progress = NULL; 8788 struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts; 8789 8790 if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) { 8791 pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 8792 if (ioc->facts.MaxDevHandle % 8) 8793 pd_handles_sz++; 8794 8795 pd_handles = krealloc(ioc->pd_handles, pd_handles_sz, 8796 GFP_KERNEL); 8797 if (!pd_handles) { 8798 ioc_info(ioc, 8799 "Unable to allocate the memory for pd_handles of sz: %d\n", 8800 pd_handles_sz); 8801 return -ENOMEM; 8802 } 8803 memset(pd_handles + ioc->pd_handles_sz, 0, 8804 (pd_handles_sz - ioc->pd_handles_sz)); 8805 ioc->pd_handles = pd_handles; 8806 8807 blocking_handles = krealloc(ioc->blocking_handles, 8808 pd_handles_sz, GFP_KERNEL); 8809 if (!blocking_handles) { 8810 ioc_info(ioc, 8811 "Unable to allocate the memory for " 8812 "blocking_handles of sz: %d\n", 8813 pd_handles_sz); 8814 return -ENOMEM; 8815 } 8816 memset(blocking_handles + ioc->pd_handles_sz, 0, 8817 (pd_handles_sz - ioc->pd_handles_sz)); 8818 ioc->blocking_handles = blocking_handles; 8819 ioc->pd_handles_sz = pd_handles_sz; 8820 8821 pend_os_device_add = krealloc(ioc->pend_os_device_add, 8822 pd_handles_sz, GFP_KERNEL); 8823 if (!pend_os_device_add) { 8824 ioc_info(ioc, 8825 "Unable to allocate the memory for pend_os_device_add of sz: %d\n", 8826 pd_handles_sz); 8827 return -ENOMEM; 8828 } 8829 memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0, 8830 (pd_handles_sz - ioc->pend_os_device_add_sz)); 8831 ioc->pend_os_device_add = pend_os_device_add; 8832 ioc->pend_os_device_add_sz = pd_handles_sz; 8833 8834 device_remove_in_progress = krealloc( 8835 ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL); 8836 if (!device_remove_in_progress) { 8837 ioc_info(ioc, 8838 "Unable to allocate the memory for " 8839 "device_remove_in_progress of sz: %d\n " 8840 , pd_handles_sz); 8841 return -ENOMEM; 8842 } 8843 memset(device_remove_in_progress + 8844 ioc->device_remove_in_progress_sz, 0, 8845 (pd_handles_sz - ioc->device_remove_in_progress_sz)); 8846 ioc->device_remove_in_progress = device_remove_in_progress; 8847 ioc->device_remove_in_progress_sz = pd_handles_sz; 8848 } 8849 8850 memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts)); 8851 return 0; 8852 } 8853 8854 /** 8855 * mpt3sas_base_hard_reset_handler - reset controller 8856 * @ioc: Pointer to MPT_ADAPTER structure 8857 * @type: FORCE_BIG_HAMMER or SOFT_RESET 8858 * 8859 * Return: 0 for success, non-zero for failure. 8860 */ 8861 int 8862 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 8863 enum reset_type type) 8864 { 8865 int r; 8866 unsigned long flags; 8867 u32 ioc_state; 8868 u8 is_fault = 0, is_trigger = 0; 8869 8870 dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__)); 8871 8872 if (ioc->pci_error_recovery) { 8873 ioc_err(ioc, "%s: pci error recovery reset\n", __func__); 8874 r = 0; 8875 goto out_unlocked; 8876 } 8877 8878 if (mpt3sas_fwfault_debug) 8879 mpt3sas_halt_firmware(ioc); 8880 8881 /* wait for an active reset in progress to complete */ 8882 mutex_lock(&ioc->reset_in_progress_mutex); 8883 8884 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 8885 ioc->shost_recovery = 1; 8886 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 8887 8888 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 8889 MPT3_DIAG_BUFFER_IS_REGISTERED) && 8890 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 8891 MPT3_DIAG_BUFFER_IS_RELEASED))) { 8892 is_trigger = 1; 8893 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8894 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT || 8895 (ioc_state & MPI2_IOC_STATE_MASK) == 8896 MPI2_IOC_STATE_COREDUMP) { 8897 is_fault = 1; 8898 ioc->htb_rel.trigger_info_dwords[1] = 8899 (ioc_state & MPI2_DOORBELL_DATA_MASK); 8900 } 8901 } 8902 _base_pre_reset_handler(ioc); 8903 mpt3sas_wait_for_commands_to_complete(ioc); 8904 mpt3sas_base_mask_interrupts(ioc); 8905 mpt3sas_base_pause_mq_polling(ioc); 8906 r = mpt3sas_base_make_ioc_ready(ioc, type); 8907 if (r) 8908 goto out; 8909 _base_clear_outstanding_commands(ioc); 8910 8911 /* If this hard reset is called while port enable is active, then 8912 * there is no reason to call make_ioc_operational 8913 */ 8914 if (ioc->is_driver_loading && ioc->port_enable_failed) { 8915 ioc->remove_host = 1; 8916 r = -EFAULT; 8917 goto out; 8918 } 8919 r = _base_get_ioc_facts(ioc); 8920 if (r) 8921 goto out; 8922 8923 r = _base_check_ioc_facts_changes(ioc); 8924 if (r) { 8925 ioc_info(ioc, 8926 "Some of the parameters got changed in this new firmware" 8927 " image and it requires system reboot\n"); 8928 goto out; 8929 } 8930 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 8931 panic("%s: Issue occurred with flashing controller firmware." 8932 "Please reboot the system and ensure that the correct" 8933 " firmware version is running\n", ioc->name); 8934 8935 r = _base_make_ioc_operational(ioc); 8936 if (!r) 8937 _base_reset_done_handler(ioc); 8938 8939 out: 8940 ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED"); 8941 8942 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 8943 ioc->shost_recovery = 0; 8944 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 8945 ioc->ioc_reset_count++; 8946 mutex_unlock(&ioc->reset_in_progress_mutex); 8947 mpt3sas_base_resume_mq_polling(ioc); 8948 8949 out_unlocked: 8950 if ((r == 0) && is_trigger) { 8951 if (is_fault) 8952 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 8953 else 8954 mpt3sas_trigger_master(ioc, 8955 MASTER_TRIGGER_ADAPTER_RESET); 8956 } 8957 dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__)); 8958 return r; 8959 } 8960