1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/ktime.h> 61 #include <linux/kthread.h> 62 #include <asm/page.h> /* To get host page size per arch */ 63 #include <linux/aer.h> 64 65 66 #include "mpt3sas_base.h" 67 68 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 69 70 71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 72 73 /* maximum controller queue depth */ 74 #define MAX_HBA_QUEUE_DEPTH 30000 75 #define MAX_CHAIN_DEPTH 100000 76 static int max_queue_depth = -1; 77 module_param(max_queue_depth, int, 0444); 78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 79 80 static int max_sgl_entries = -1; 81 module_param(max_sgl_entries, int, 0444); 82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 83 84 static int msix_disable = -1; 85 module_param(msix_disable, int, 0444); 86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 87 88 static int smp_affinity_enable = 1; 89 module_param(smp_affinity_enable, int, 0444); 90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)"); 91 92 static int max_msix_vectors = -1; 93 module_param(max_msix_vectors, int, 0444); 94 MODULE_PARM_DESC(max_msix_vectors, 95 " max msix vectors"); 96 97 static int irqpoll_weight = -1; 98 module_param(irqpoll_weight, int, 0444); 99 MODULE_PARM_DESC(irqpoll_weight, 100 "irq poll weight (default= one fourth of HBA queue depth)"); 101 102 static int mpt3sas_fwfault_debug; 103 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 104 " enable detection of firmware fault and halt firmware - (default=0)"); 105 106 static int perf_mode = -1; 107 module_param(perf_mode, int, 0444); 108 MODULE_PARM_DESC(perf_mode, 109 "Performance mode (only for Aero/Sea Generation), options:\n\t\t" 110 "0 - balanced: high iops mode is enabled &\n\t\t" 111 "interrupt coalescing is enabled only on high iops queues,\n\t\t" 112 "1 - iops: high iops mode is disabled &\n\t\t" 113 "interrupt coalescing is enabled on all queues,\n\t\t" 114 "2 - latency: high iops mode is disabled &\n\t\t" 115 "interrupt coalescing is enabled on all queues with timeout value 0xA,\n" 116 "\t\tdefault - default perf_mode is 'balanced'" 117 ); 118 119 static int poll_queues; 120 module_param(poll_queues, int, 0444); 121 MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t" 122 "This parameter is effective only if host_tagset_enable=1. &\n\t\t" 123 "when poll_queues are enabled then &\n\t\t" 124 "perf_mode is set to latency mode. &\n\t\t" 125 ); 126 127 enum mpt3sas_perf_mode { 128 MPT_PERF_MODE_DEFAULT = -1, 129 MPT_PERF_MODE_BALANCED = 0, 130 MPT_PERF_MODE_IOPS = 1, 131 MPT_PERF_MODE_LATENCY = 2, 132 }; 133 134 static int 135 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, 136 u32 ioc_state, int timeout); 137 static int 138 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); 139 static void 140 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc); 141 142 /** 143 * mpt3sas_base_check_cmd_timeout - Function 144 * to check timeout and command termination due 145 * to Host reset. 146 * 147 * @ioc: per adapter object. 148 * @status: Status of issued command. 149 * @mpi_request:mf request pointer. 150 * @sz: size of buffer. 151 * 152 * Return: 1/0 Reset to be done or Not 153 */ 154 u8 155 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, 156 u8 status, void *mpi_request, int sz) 157 { 158 u8 issue_reset = 0; 159 160 if (!(status & MPT3_CMD_RESET)) 161 issue_reset = 1; 162 163 ioc_err(ioc, "Command %s\n", 164 issue_reset == 0 ? "terminated due to Host Reset" : "Timeout"); 165 _debug_dump_mf(mpi_request, sz); 166 167 return issue_reset; 168 } 169 170 /** 171 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 172 * @val: ? 173 * @kp: ? 174 * 175 * Return: ? 176 */ 177 static int 178 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) 179 { 180 int ret = param_set_int(val, kp); 181 struct MPT3SAS_ADAPTER *ioc; 182 183 if (ret) 184 return ret; 185 186 /* global ioc spinlock to protect controller list on list operations */ 187 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 188 spin_lock(&gioc_lock); 189 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 190 ioc->fwfault_debug = mpt3sas_fwfault_debug; 191 spin_unlock(&gioc_lock); 192 return 0; 193 } 194 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 195 param_get_int, &mpt3sas_fwfault_debug, 0644); 196 197 /** 198 * _base_readl_aero - retry readl for max three times. 199 * @addr: MPT Fusion system interface register address 200 * 201 * Retry the readl() for max three times if it gets zero value 202 * while reading the system interface register. 203 */ 204 static inline u32 205 _base_readl_aero(const volatile void __iomem *addr) 206 { 207 u32 i = 0, ret_val; 208 209 do { 210 ret_val = readl(addr); 211 i++; 212 } while (ret_val == 0 && i < 3); 213 214 return ret_val; 215 } 216 217 static inline u32 218 _base_readl(const volatile void __iomem *addr) 219 { 220 return readl(addr); 221 } 222 223 /** 224 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem 225 * in BAR0 space. 226 * 227 * @ioc: per adapter object 228 * @reply: reply message frame(lower 32bit addr) 229 * @index: System request message index. 230 */ 231 static void 232 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply, 233 u32 index) 234 { 235 /* 236 * 256 is offset within sys register. 237 * 256 offset MPI frame starts. Max MPI frame supported is 32. 238 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts 239 */ 240 u16 cmd_credit = ioc->facts.RequestCredit + 1; 241 void __iomem *reply_free_iomem = (void __iomem *)ioc->chip + 242 MPI_FRAME_START_OFFSET + 243 (cmd_credit * ioc->request_sz) + (index * sizeof(u32)); 244 245 writel(reply, reply_free_iomem); 246 } 247 248 /** 249 * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames 250 * to system/BAR0 region. 251 * 252 * @dst_iomem: Pointer to the destination location in BAR0 space. 253 * @src: Pointer to the Source data. 254 * @size: Size of data to be copied. 255 */ 256 static void 257 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size) 258 { 259 int i; 260 u32 *src_virt_mem = (u32 *)src; 261 262 for (i = 0; i < size/4; i++) 263 writel((u32)src_virt_mem[i], 264 (void __iomem *)dst_iomem + (i * 4)); 265 } 266 267 /** 268 * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region 269 * 270 * @dst_iomem: Pointer to the destination location in BAR0 space. 271 * @src: Pointer to the Source data. 272 * @size: Size of data to be copied. 273 */ 274 static void 275 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size) 276 { 277 int i; 278 u32 *src_virt_mem = (u32 *)(src); 279 280 for (i = 0; i < size/4; i++) 281 writel((u32)src_virt_mem[i], 282 (void __iomem *)dst_iomem + (i * 4)); 283 } 284 285 /** 286 * _base_get_chain - Calculates and Returns virtual chain address 287 * for the provided smid in BAR0 space. 288 * 289 * @ioc: per adapter object 290 * @smid: system request message index 291 * @sge_chain_count: Scatter gather chain count. 292 * 293 * Return: the chain address. 294 */ 295 static inline void __iomem* 296 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid, 297 u8 sge_chain_count) 298 { 299 void __iomem *base_chain, *chain_virt; 300 u16 cmd_credit = ioc->facts.RequestCredit + 1; 301 302 base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET + 303 (cmd_credit * ioc->request_sz) + 304 REPLY_FREE_POOL_SIZE; 305 chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth * 306 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 307 return chain_virt; 308 } 309 310 /** 311 * _base_get_chain_phys - Calculates and Returns physical address 312 * in BAR0 for scatter gather chains, for 313 * the provided smid. 314 * 315 * @ioc: per adapter object 316 * @smid: system request message index 317 * @sge_chain_count: Scatter gather chain count. 318 * 319 * Return: Physical chain address. 320 */ 321 static inline phys_addr_t 322 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid, 323 u8 sge_chain_count) 324 { 325 phys_addr_t base_chain_phys, chain_phys; 326 u16 cmd_credit = ioc->facts.RequestCredit + 1; 327 328 base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET + 329 (cmd_credit * ioc->request_sz) + 330 REPLY_FREE_POOL_SIZE; 331 chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth * 332 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 333 return chain_phys; 334 } 335 336 /** 337 * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host 338 * buffer address for the provided smid. 339 * (Each smid can have 64K starts from 17024) 340 * 341 * @ioc: per adapter object 342 * @smid: system request message index 343 * 344 * Return: Pointer to buffer location in BAR0. 345 */ 346 347 static void __iomem * 348 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 349 { 350 u16 cmd_credit = ioc->facts.RequestCredit + 1; 351 // Added extra 1 to reach end of chain. 352 void __iomem *chain_end = _base_get_chain(ioc, 353 cmd_credit + 1, 354 ioc->facts.MaxChainDepth); 355 return chain_end + (smid * 64 * 1024); 356 } 357 358 /** 359 * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped 360 * Host buffer Physical address for the provided smid. 361 * (Each smid can have 64K starts from 17024) 362 * 363 * @ioc: per adapter object 364 * @smid: system request message index 365 * 366 * Return: Pointer to buffer location in BAR0. 367 */ 368 static phys_addr_t 369 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 370 { 371 u16 cmd_credit = ioc->facts.RequestCredit + 1; 372 phys_addr_t chain_end_phys = _base_get_chain_phys(ioc, 373 cmd_credit + 1, 374 ioc->facts.MaxChainDepth); 375 return chain_end_phys + (smid * 64 * 1024); 376 } 377 378 /** 379 * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain 380 * lookup list and Provides chain_buffer 381 * address for the matching dma address. 382 * (Each smid can have 64K starts from 17024) 383 * 384 * @ioc: per adapter object 385 * @chain_buffer_dma: Chain buffer dma address. 386 * 387 * Return: Pointer to chain buffer. Or Null on Failure. 388 */ 389 static void * 390 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc, 391 dma_addr_t chain_buffer_dma) 392 { 393 u16 index, j; 394 struct chain_tracker *ct; 395 396 for (index = 0; index < ioc->scsiio_depth; index++) { 397 for (j = 0; j < ioc->chains_needed_per_io; j++) { 398 ct = &ioc->chain_lookup[index].chains_per_smid[j]; 399 if (ct && ct->chain_buffer_dma == chain_buffer_dma) 400 return ct->chain_buffer; 401 } 402 } 403 ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n"); 404 return NULL; 405 } 406 407 /** 408 * _clone_sg_entries - MPI EP's scsiio and config requests 409 * are handled here. Base function for 410 * double buffering, before submitting 411 * the requests. 412 * 413 * @ioc: per adapter object. 414 * @mpi_request: mf request pointer. 415 * @smid: system request message index. 416 */ 417 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc, 418 void *mpi_request, u16 smid) 419 { 420 Mpi2SGESimple32_t *sgel, *sgel_next; 421 u32 sgl_flags, sge_chain_count = 0; 422 bool is_write = false; 423 u16 i = 0; 424 void __iomem *buffer_iomem; 425 phys_addr_t buffer_iomem_phys; 426 void __iomem *buff_ptr; 427 phys_addr_t buff_ptr_phys; 428 void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 429 void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 430 phys_addr_t dst_addr_phys; 431 MPI2RequestHeader_t *request_hdr; 432 struct scsi_cmnd *scmd; 433 struct scatterlist *sg_scmd = NULL; 434 int is_scsiio_req = 0; 435 436 request_hdr = (MPI2RequestHeader_t *) mpi_request; 437 438 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 439 Mpi25SCSIIORequest_t *scsiio_request = 440 (Mpi25SCSIIORequest_t *)mpi_request; 441 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL; 442 is_scsiio_req = 1; 443 } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { 444 Mpi2ConfigRequest_t *config_req = 445 (Mpi2ConfigRequest_t *)mpi_request; 446 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE; 447 } else 448 return; 449 450 /* From smid we can get scsi_cmd, once we have sg_scmd, 451 * we just need to get sg_virt and sg_next to get virtual 452 * address associated with sgel->Address. 453 */ 454 455 if (is_scsiio_req) { 456 /* Get scsi_cmd using smid */ 457 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 458 if (scmd == NULL) { 459 ioc_err(ioc, "scmd is NULL\n"); 460 return; 461 } 462 463 /* Get sg_scmd from scmd provided */ 464 sg_scmd = scsi_sglist(scmd); 465 } 466 467 /* 468 * 0 - 255 System register 469 * 256 - 4352 MPI Frame. (This is based on maxCredit 32) 470 * 4352 - 4864 Reply_free pool (512 byte is reserved 471 * considering maxCredit 32. Reply need extra 472 * room, for mCPU case kept four times of 473 * maxCredit). 474 * 4864 - 17152 SGE chain element. (32cmd * 3 chain of 475 * 128 byte size = 12288) 476 * 17152 - x Host buffer mapped with smid. 477 * (Each smid can have 64K Max IO.) 478 * BAR0+Last 1K MSIX Addr and Data 479 * Total size in use 2113664 bytes of 4MB BAR0 480 */ 481 482 buffer_iomem = _base_get_buffer_bar0(ioc, smid); 483 buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid); 484 485 buff_ptr = buffer_iomem; 486 buff_ptr_phys = buffer_iomem_phys; 487 WARN_ON(buff_ptr_phys > U32_MAX); 488 489 if (le32_to_cpu(sgel->FlagsLength) & 490 (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT)) 491 is_write = true; 492 493 for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) { 494 495 sgl_flags = 496 (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT); 497 498 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) { 499 case MPI2_SGE_FLAGS_CHAIN_ELEMENT: 500 /* 501 * Helper function which on passing 502 * chain_buffer_dma returns chain_buffer. Get 503 * the virtual address for sgel->Address 504 */ 505 sgel_next = 506 _base_get_chain_buffer_dma_to_chain_buffer(ioc, 507 le32_to_cpu(sgel->Address)); 508 if (sgel_next == NULL) 509 return; 510 /* 511 * This is coping 128 byte chain 512 * frame (not a host buffer) 513 */ 514 dst_chain_addr[sge_chain_count] = 515 _base_get_chain(ioc, 516 smid, sge_chain_count); 517 src_chain_addr[sge_chain_count] = 518 (void *) sgel_next; 519 dst_addr_phys = _base_get_chain_phys(ioc, 520 smid, sge_chain_count); 521 WARN_ON(dst_addr_phys > U32_MAX); 522 sgel->Address = 523 cpu_to_le32(lower_32_bits(dst_addr_phys)); 524 sgel = sgel_next; 525 sge_chain_count++; 526 break; 527 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT: 528 if (is_write) { 529 if (is_scsiio_req) { 530 _base_clone_to_sys_mem(buff_ptr, 531 sg_virt(sg_scmd), 532 (le32_to_cpu(sgel->FlagsLength) & 533 0x00ffffff)); 534 /* 535 * FIXME: this relies on a a zero 536 * PCI mem_offset. 537 */ 538 sgel->Address = 539 cpu_to_le32((u32)buff_ptr_phys); 540 } else { 541 _base_clone_to_sys_mem(buff_ptr, 542 ioc->config_vaddr, 543 (le32_to_cpu(sgel->FlagsLength) & 544 0x00ffffff)); 545 sgel->Address = 546 cpu_to_le32((u32)buff_ptr_phys); 547 } 548 } 549 buff_ptr += (le32_to_cpu(sgel->FlagsLength) & 550 0x00ffffff); 551 buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) & 552 0x00ffffff); 553 if ((le32_to_cpu(sgel->FlagsLength) & 554 (MPI2_SGE_FLAGS_END_OF_BUFFER 555 << MPI2_SGE_FLAGS_SHIFT))) 556 goto eob_clone_chain; 557 else { 558 /* 559 * Every single element in MPT will have 560 * associated sg_next. Better to sanity that 561 * sg_next is not NULL, but it will be a bug 562 * if it is null. 563 */ 564 if (is_scsiio_req) { 565 sg_scmd = sg_next(sg_scmd); 566 if (sg_scmd) 567 sgel++; 568 else 569 goto eob_clone_chain; 570 } 571 } 572 break; 573 } 574 } 575 576 eob_clone_chain: 577 for (i = 0; i < sge_chain_count; i++) { 578 if (is_scsiio_req) 579 _base_clone_to_sys_mem(dst_chain_addr[i], 580 src_chain_addr[i], ioc->request_sz); 581 } 582 } 583 584 /** 585 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 586 * @arg: input argument, used to derive ioc 587 * 588 * Return: 589 * 0 if controller is removed from pci subsystem. 590 * -1 for other case. 591 */ 592 static int mpt3sas_remove_dead_ioc_func(void *arg) 593 { 594 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 595 struct pci_dev *pdev; 596 597 if (!ioc) 598 return -1; 599 600 pdev = ioc->pdev; 601 if (!pdev) 602 return -1; 603 pci_stop_and_remove_bus_device_locked(pdev); 604 return 0; 605 } 606 607 /** 608 * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp. 609 * @ioc: Per Adapter Object 610 * 611 * Return: nothing. 612 */ 613 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc) 614 { 615 Mpi26IoUnitControlRequest_t *mpi_request; 616 Mpi26IoUnitControlReply_t *mpi_reply; 617 u16 smid; 618 ktime_t current_time; 619 u64 TimeStamp = 0; 620 u8 issue_reset = 0; 621 622 mutex_lock(&ioc->scsih_cmds.mutex); 623 if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) { 624 ioc_err(ioc, "scsih_cmd in use %s\n", __func__); 625 goto out; 626 } 627 ioc->scsih_cmds.status = MPT3_CMD_PENDING; 628 smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx); 629 if (!smid) { 630 ioc_err(ioc, "Failed obtaining a smid %s\n", __func__); 631 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 632 goto out; 633 } 634 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 635 ioc->scsih_cmds.smid = smid; 636 memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t)); 637 mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL; 638 mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER; 639 mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP; 640 current_time = ktime_get_real(); 641 TimeStamp = ktime_to_ms(current_time); 642 mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32); 643 mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF); 644 init_completion(&ioc->scsih_cmds.done); 645 ioc->put_smid_default(ioc, smid); 646 dinitprintk(ioc, ioc_info(ioc, 647 "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n", 648 TimeStamp)); 649 wait_for_completion_timeout(&ioc->scsih_cmds.done, 650 MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ); 651 if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) { 652 mpt3sas_check_cmd_timeout(ioc, 653 ioc->scsih_cmds.status, mpi_request, 654 sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset); 655 goto issue_host_reset; 656 } 657 if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) { 658 mpi_reply = ioc->scsih_cmds.reply; 659 dinitprintk(ioc, ioc_info(ioc, 660 "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n", 661 le16_to_cpu(mpi_reply->IOCStatus), 662 le32_to_cpu(mpi_reply->IOCLogInfo))); 663 } 664 issue_host_reset: 665 if (issue_reset) 666 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 667 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 668 out: 669 mutex_unlock(&ioc->scsih_cmds.mutex); 670 } 671 672 /** 673 * _base_fault_reset_work - workq handling ioc fault conditions 674 * @work: input argument, used to derive ioc 675 * 676 * Context: sleep. 677 */ 678 static void 679 _base_fault_reset_work(struct work_struct *work) 680 { 681 struct MPT3SAS_ADAPTER *ioc = 682 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 683 unsigned long flags; 684 u32 doorbell; 685 int rc; 686 struct task_struct *p; 687 688 689 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 690 if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) || 691 ioc->pci_error_recovery) 692 goto rearm_timer; 693 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 694 695 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 696 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 697 ioc_err(ioc, "SAS host is non-operational !!!!\n"); 698 699 /* It may be possible that EEH recovery can resolve some of 700 * pci bus failure issues rather removing the dead ioc function 701 * by considering controller is in a non-operational state. So 702 * here priority is given to the EEH recovery. If it doesn't 703 * not resolve this issue, mpt3sas driver will consider this 704 * controller to non-operational state and remove the dead ioc 705 * function. 706 */ 707 if (ioc->non_operational_loop++ < 5) { 708 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 709 flags); 710 goto rearm_timer; 711 } 712 713 /* 714 * Call _scsih_flush_pending_cmds callback so that we flush all 715 * pending commands back to OS. This call is required to avoid 716 * deadlock at block layer. Dead IOC will fail to do diag reset, 717 * and this call is safe since dead ioc will never return any 718 * command back from HW. 719 */ 720 mpt3sas_base_pause_mq_polling(ioc); 721 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 722 /* 723 * Set remove_host flag early since kernel thread will 724 * take some time to execute. 725 */ 726 ioc->remove_host = 1; 727 /*Remove the Dead Host */ 728 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 729 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 730 if (IS_ERR(p)) 731 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 732 __func__); 733 else 734 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 735 __func__); 736 return; /* don't rearm timer */ 737 } 738 739 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { 740 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? 741 ioc->manu_pg11.CoreDumpTOSec : 742 MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; 743 744 timeout /= (FAULT_POLLING_INTERVAL/1000); 745 746 if (ioc->ioc_coredump_loop == 0) { 747 mpt3sas_print_coredump_info(ioc, 748 doorbell & MPI2_DOORBELL_DATA_MASK); 749 /* do not accept any IOs and disable the interrupts */ 750 spin_lock_irqsave( 751 &ioc->ioc_reset_in_progress_lock, flags); 752 ioc->shost_recovery = 1; 753 spin_unlock_irqrestore( 754 &ioc->ioc_reset_in_progress_lock, flags); 755 mpt3sas_base_mask_interrupts(ioc); 756 mpt3sas_base_pause_mq_polling(ioc); 757 _base_clear_outstanding_commands(ioc); 758 } 759 760 ioc_info(ioc, "%s: CoreDump loop %d.", 761 __func__, ioc->ioc_coredump_loop); 762 763 /* Wait until CoreDump completes or times out */ 764 if (ioc->ioc_coredump_loop++ < timeout) { 765 spin_lock_irqsave( 766 &ioc->ioc_reset_in_progress_lock, flags); 767 goto rearm_timer; 768 } 769 } 770 771 if (ioc->ioc_coredump_loop) { 772 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP) 773 ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d", 774 __func__, ioc->ioc_coredump_loop); 775 else 776 ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d", 777 __func__, ioc->ioc_coredump_loop); 778 ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE; 779 } 780 ioc->non_operational_loop = 0; 781 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 782 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 783 ioc_warn(ioc, "%s: hard reset: %s\n", 784 __func__, rc == 0 ? "success" : "failed"); 785 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 786 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 787 mpt3sas_print_fault_code(ioc, doorbell & 788 MPI2_DOORBELL_DATA_MASK); 789 } else if ((doorbell & MPI2_IOC_STATE_MASK) == 790 MPI2_IOC_STATE_COREDUMP) 791 mpt3sas_print_coredump_info(ioc, doorbell & 792 MPI2_DOORBELL_DATA_MASK); 793 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 794 MPI2_IOC_STATE_OPERATIONAL) 795 return; /* don't rearm timer */ 796 } 797 ioc->ioc_coredump_loop = 0; 798 if (ioc->time_sync_interval && 799 ++ioc->timestamp_update_count >= ioc->time_sync_interval) { 800 ioc->timestamp_update_count = 0; 801 _base_sync_drv_fw_timestamp(ioc); 802 } 803 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 804 rearm_timer: 805 if (ioc->fault_reset_work_q) 806 queue_delayed_work(ioc->fault_reset_work_q, 807 &ioc->fault_reset_work, 808 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 809 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 810 } 811 812 /** 813 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 814 * @ioc: per adapter object 815 * 816 * Context: sleep. 817 */ 818 void 819 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 820 { 821 unsigned long flags; 822 823 if (ioc->fault_reset_work_q) 824 return; 825 826 ioc->timestamp_update_count = 0; 827 /* initialize fault polling */ 828 829 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 830 snprintf(ioc->fault_reset_work_q_name, 831 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 832 ioc->driver_name, ioc->id); 833 ioc->fault_reset_work_q = 834 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 835 if (!ioc->fault_reset_work_q) { 836 ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__); 837 return; 838 } 839 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 840 if (ioc->fault_reset_work_q) 841 queue_delayed_work(ioc->fault_reset_work_q, 842 &ioc->fault_reset_work, 843 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 844 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 845 } 846 847 /** 848 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 849 * @ioc: per adapter object 850 * 851 * Context: sleep. 852 */ 853 void 854 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 855 { 856 unsigned long flags; 857 struct workqueue_struct *wq; 858 859 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 860 wq = ioc->fault_reset_work_q; 861 ioc->fault_reset_work_q = NULL; 862 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 863 if (wq) { 864 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 865 flush_workqueue(wq); 866 destroy_workqueue(wq); 867 } 868 } 869 870 /** 871 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 872 * @ioc: per adapter object 873 * @fault_code: fault code 874 */ 875 void 876 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 877 { 878 ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code); 879 } 880 881 /** 882 * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state 883 * @ioc: per adapter object 884 * @fault_code: fault code 885 * 886 * Return: nothing. 887 */ 888 void 889 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code) 890 { 891 ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code); 892 } 893 894 /** 895 * mpt3sas_base_wait_for_coredump_completion - Wait until coredump 896 * completes or times out 897 * @ioc: per adapter object 898 * @caller: caller function name 899 * 900 * Return: 0 for success, non-zero for failure. 901 */ 902 int 903 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc, 904 const char *caller) 905 { 906 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? 907 ioc->manu_pg11.CoreDumpTOSec : 908 MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; 909 910 int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT, 911 timeout); 912 913 if (ioc_state) 914 ioc_err(ioc, 915 "%s: CoreDump timed out. (ioc_state=0x%x)\n", 916 caller, ioc_state); 917 else 918 ioc_info(ioc, 919 "%s: CoreDump completed. (ioc_state=0x%x)\n", 920 caller, ioc_state); 921 922 return ioc_state; 923 } 924 925 /** 926 * mpt3sas_halt_firmware - halt's mpt controller firmware 927 * @ioc: per adapter object 928 * 929 * For debugging timeout related issues. Writing 0xCOFFEE00 930 * to the doorbell register will halt controller firmware. With 931 * the purpose to stop both driver and firmware, the enduser can 932 * obtain a ring buffer from controller UART. 933 */ 934 void 935 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 936 { 937 u32 doorbell; 938 939 if (!ioc->fwfault_debug) 940 return; 941 942 dump_stack(); 943 944 doorbell = ioc->base_readl(&ioc->chip->Doorbell); 945 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 946 mpt3sas_print_fault_code(ioc, doorbell & 947 MPI2_DOORBELL_DATA_MASK); 948 } else if ((doorbell & MPI2_IOC_STATE_MASK) == 949 MPI2_IOC_STATE_COREDUMP) { 950 mpt3sas_print_coredump_info(ioc, doorbell & 951 MPI2_DOORBELL_DATA_MASK); 952 } else { 953 writel(0xC0FFEE00, &ioc->chip->Doorbell); 954 ioc_err(ioc, "Firmware is halted due to command timeout\n"); 955 } 956 957 if (ioc->fwfault_debug == 2) 958 for (;;) 959 ; 960 else 961 panic("panic in %s\n", __func__); 962 } 963 964 /** 965 * _base_sas_ioc_info - verbose translation of the ioc status 966 * @ioc: per adapter object 967 * @mpi_reply: reply mf payload returned from firmware 968 * @request_hdr: request mf 969 */ 970 static void 971 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 972 MPI2RequestHeader_t *request_hdr) 973 { 974 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 975 MPI2_IOCSTATUS_MASK; 976 char *desc = NULL; 977 u16 frame_sz; 978 char *func_str = NULL; 979 980 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 981 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 982 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 983 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 984 return; 985 986 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 987 return; 988 /* 989 * Older Firmware version doesn't support driver trigger pages. 990 * So, skip displaying 'config invalid type' type 991 * of error message. 992 */ 993 if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { 994 Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr; 995 996 if ((rqst->ExtPageType == 997 MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) && 998 !(ioc->logging_level & MPT_DEBUG_CONFIG)) { 999 return; 1000 } 1001 } 1002 1003 switch (ioc_status) { 1004 1005 /**************************************************************************** 1006 * Common IOCStatus values for all replies 1007 ****************************************************************************/ 1008 1009 case MPI2_IOCSTATUS_INVALID_FUNCTION: 1010 desc = "invalid function"; 1011 break; 1012 case MPI2_IOCSTATUS_BUSY: 1013 desc = "busy"; 1014 break; 1015 case MPI2_IOCSTATUS_INVALID_SGL: 1016 desc = "invalid sgl"; 1017 break; 1018 case MPI2_IOCSTATUS_INTERNAL_ERROR: 1019 desc = "internal error"; 1020 break; 1021 case MPI2_IOCSTATUS_INVALID_VPID: 1022 desc = "invalid vpid"; 1023 break; 1024 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 1025 desc = "insufficient resources"; 1026 break; 1027 case MPI2_IOCSTATUS_INSUFFICIENT_POWER: 1028 desc = "insufficient power"; 1029 break; 1030 case MPI2_IOCSTATUS_INVALID_FIELD: 1031 desc = "invalid field"; 1032 break; 1033 case MPI2_IOCSTATUS_INVALID_STATE: 1034 desc = "invalid state"; 1035 break; 1036 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 1037 desc = "op state not supported"; 1038 break; 1039 1040 /**************************************************************************** 1041 * Config IOCStatus values 1042 ****************************************************************************/ 1043 1044 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 1045 desc = "config invalid action"; 1046 break; 1047 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 1048 desc = "config invalid type"; 1049 break; 1050 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 1051 desc = "config invalid page"; 1052 break; 1053 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 1054 desc = "config invalid data"; 1055 break; 1056 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 1057 desc = "config no defaults"; 1058 break; 1059 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 1060 desc = "config cant commit"; 1061 break; 1062 1063 /**************************************************************************** 1064 * SCSI IO Reply 1065 ****************************************************************************/ 1066 1067 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 1068 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 1069 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 1070 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 1071 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 1072 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 1073 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 1074 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 1075 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 1076 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 1077 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 1078 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 1079 break; 1080 1081 /**************************************************************************** 1082 * For use by SCSI Initiator and SCSI Target end-to-end data protection 1083 ****************************************************************************/ 1084 1085 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 1086 desc = "eedp guard error"; 1087 break; 1088 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 1089 desc = "eedp ref tag error"; 1090 break; 1091 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 1092 desc = "eedp app tag error"; 1093 break; 1094 1095 /**************************************************************************** 1096 * SCSI Target values 1097 ****************************************************************************/ 1098 1099 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 1100 desc = "target invalid io index"; 1101 break; 1102 case MPI2_IOCSTATUS_TARGET_ABORTED: 1103 desc = "target aborted"; 1104 break; 1105 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 1106 desc = "target no conn retryable"; 1107 break; 1108 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 1109 desc = "target no connection"; 1110 break; 1111 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 1112 desc = "target xfer count mismatch"; 1113 break; 1114 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 1115 desc = "target data offset error"; 1116 break; 1117 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 1118 desc = "target too much write data"; 1119 break; 1120 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 1121 desc = "target iu too short"; 1122 break; 1123 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 1124 desc = "target ack nak timeout"; 1125 break; 1126 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 1127 desc = "target nak received"; 1128 break; 1129 1130 /**************************************************************************** 1131 * Serial Attached SCSI values 1132 ****************************************************************************/ 1133 1134 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 1135 desc = "smp request failed"; 1136 break; 1137 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 1138 desc = "smp data overrun"; 1139 break; 1140 1141 /**************************************************************************** 1142 * Diagnostic Buffer Post / Diagnostic Release values 1143 ****************************************************************************/ 1144 1145 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 1146 desc = "diagnostic released"; 1147 break; 1148 default: 1149 break; 1150 } 1151 1152 if (!desc) 1153 return; 1154 1155 switch (request_hdr->Function) { 1156 case MPI2_FUNCTION_CONFIG: 1157 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 1158 func_str = "config_page"; 1159 break; 1160 case MPI2_FUNCTION_SCSI_TASK_MGMT: 1161 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 1162 func_str = "task_mgmt"; 1163 break; 1164 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 1165 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 1166 func_str = "sas_iounit_ctl"; 1167 break; 1168 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 1169 frame_sz = sizeof(Mpi2SepRequest_t); 1170 func_str = "enclosure"; 1171 break; 1172 case MPI2_FUNCTION_IOC_INIT: 1173 frame_sz = sizeof(Mpi2IOCInitRequest_t); 1174 func_str = "ioc_init"; 1175 break; 1176 case MPI2_FUNCTION_PORT_ENABLE: 1177 frame_sz = sizeof(Mpi2PortEnableRequest_t); 1178 func_str = "port_enable"; 1179 break; 1180 case MPI2_FUNCTION_SMP_PASSTHROUGH: 1181 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 1182 func_str = "smp_passthru"; 1183 break; 1184 case MPI2_FUNCTION_NVME_ENCAPSULATED: 1185 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) + 1186 ioc->sge_size; 1187 func_str = "nvme_encapsulated"; 1188 break; 1189 default: 1190 frame_sz = 32; 1191 func_str = "unknown"; 1192 break; 1193 } 1194 1195 ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 1196 desc, ioc_status, request_hdr, func_str); 1197 1198 _debug_dump_mf(request_hdr, frame_sz/4); 1199 } 1200 1201 /** 1202 * _base_display_event_data - verbose translation of firmware asyn events 1203 * @ioc: per adapter object 1204 * @mpi_reply: reply mf payload returned from firmware 1205 */ 1206 static void 1207 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 1208 Mpi2EventNotificationReply_t *mpi_reply) 1209 { 1210 char *desc = NULL; 1211 u16 event; 1212 1213 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 1214 return; 1215 1216 event = le16_to_cpu(mpi_reply->Event); 1217 1218 switch (event) { 1219 case MPI2_EVENT_LOG_DATA: 1220 desc = "Log Data"; 1221 break; 1222 case MPI2_EVENT_STATE_CHANGE: 1223 desc = "Status Change"; 1224 break; 1225 case MPI2_EVENT_HARD_RESET_RECEIVED: 1226 desc = "Hard Reset Received"; 1227 break; 1228 case MPI2_EVENT_EVENT_CHANGE: 1229 desc = "Event Change"; 1230 break; 1231 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 1232 desc = "Device Status Change"; 1233 break; 1234 case MPI2_EVENT_IR_OPERATION_STATUS: 1235 if (!ioc->hide_ir_msg) 1236 desc = "IR Operation Status"; 1237 break; 1238 case MPI2_EVENT_SAS_DISCOVERY: 1239 { 1240 Mpi2EventDataSasDiscovery_t *event_data = 1241 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 1242 ioc_info(ioc, "Discovery: (%s)", 1243 event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ? 1244 "start" : "stop"); 1245 if (event_data->DiscoveryStatus) 1246 pr_cont(" discovery_status(0x%08x)", 1247 le32_to_cpu(event_data->DiscoveryStatus)); 1248 pr_cont("\n"); 1249 return; 1250 } 1251 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 1252 desc = "SAS Broadcast Primitive"; 1253 break; 1254 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 1255 desc = "SAS Init Device Status Change"; 1256 break; 1257 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 1258 desc = "SAS Init Table Overflow"; 1259 break; 1260 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 1261 desc = "SAS Topology Change List"; 1262 break; 1263 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 1264 desc = "SAS Enclosure Device Status Change"; 1265 break; 1266 case MPI2_EVENT_IR_VOLUME: 1267 if (!ioc->hide_ir_msg) 1268 desc = "IR Volume"; 1269 break; 1270 case MPI2_EVENT_IR_PHYSICAL_DISK: 1271 if (!ioc->hide_ir_msg) 1272 desc = "IR Physical Disk"; 1273 break; 1274 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 1275 if (!ioc->hide_ir_msg) 1276 desc = "IR Configuration Change List"; 1277 break; 1278 case MPI2_EVENT_LOG_ENTRY_ADDED: 1279 if (!ioc->hide_ir_msg) 1280 desc = "Log Entry Added"; 1281 break; 1282 case MPI2_EVENT_TEMP_THRESHOLD: 1283 desc = "Temperature Threshold"; 1284 break; 1285 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 1286 desc = "Cable Event"; 1287 break; 1288 case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 1289 desc = "SAS Device Discovery Error"; 1290 break; 1291 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 1292 desc = "PCIE Device Status Change"; 1293 break; 1294 case MPI2_EVENT_PCIE_ENUMERATION: 1295 { 1296 Mpi26EventDataPCIeEnumeration_t *event_data = 1297 (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData; 1298 ioc_info(ioc, "PCIE Enumeration: (%s)", 1299 event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ? 1300 "start" : "stop"); 1301 if (event_data->EnumerationStatus) 1302 pr_cont("enumeration_status(0x%08x)", 1303 le32_to_cpu(event_data->EnumerationStatus)); 1304 pr_cont("\n"); 1305 return; 1306 } 1307 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 1308 desc = "PCIE Topology Change List"; 1309 break; 1310 } 1311 1312 if (!desc) 1313 return; 1314 1315 ioc_info(ioc, "%s\n", desc); 1316 } 1317 1318 /** 1319 * _base_sas_log_info - verbose translation of firmware log info 1320 * @ioc: per adapter object 1321 * @log_info: log info 1322 */ 1323 static void 1324 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 1325 { 1326 union loginfo_type { 1327 u32 loginfo; 1328 struct { 1329 u32 subcode:16; 1330 u32 code:8; 1331 u32 originator:4; 1332 u32 bus_type:4; 1333 } dw; 1334 }; 1335 union loginfo_type sas_loginfo; 1336 char *originator_str = NULL; 1337 1338 sas_loginfo.loginfo = log_info; 1339 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 1340 return; 1341 1342 /* each nexus loss loginfo */ 1343 if (log_info == 0x31170000) 1344 return; 1345 1346 /* eat the loginfos associated with task aborts */ 1347 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 1348 0x31140000 || log_info == 0x31130000)) 1349 return; 1350 1351 switch (sas_loginfo.dw.originator) { 1352 case 0: 1353 originator_str = "IOP"; 1354 break; 1355 case 1: 1356 originator_str = "PL"; 1357 break; 1358 case 2: 1359 if (!ioc->hide_ir_msg) 1360 originator_str = "IR"; 1361 else 1362 originator_str = "WarpDrive"; 1363 break; 1364 } 1365 1366 ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 1367 log_info, 1368 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode); 1369 } 1370 1371 /** 1372 * _base_display_reply_info - handle reply descriptors depending on IOC Status 1373 * @ioc: per adapter object 1374 * @smid: system request message index 1375 * @msix_index: MSIX table index supplied by the OS 1376 * @reply: reply message frame (lower 32bit addr) 1377 */ 1378 static void 1379 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1380 u32 reply) 1381 { 1382 MPI2DefaultReply_t *mpi_reply; 1383 u16 ioc_status; 1384 u32 loginfo = 0; 1385 1386 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1387 if (unlikely(!mpi_reply)) { 1388 ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n", 1389 __FILE__, __LINE__, __func__); 1390 return; 1391 } 1392 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 1393 1394 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 1395 (ioc->logging_level & MPT_DEBUG_REPLY)) { 1396 _base_sas_ioc_info(ioc , mpi_reply, 1397 mpt3sas_base_get_msg_frame(ioc, smid)); 1398 } 1399 1400 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 1401 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 1402 _base_sas_log_info(ioc, loginfo); 1403 } 1404 1405 if (ioc_status || loginfo) { 1406 ioc_status &= MPI2_IOCSTATUS_MASK; 1407 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 1408 } 1409 } 1410 1411 /** 1412 * mpt3sas_base_done - base internal command completion routine 1413 * @ioc: per adapter object 1414 * @smid: system request message index 1415 * @msix_index: MSIX table index supplied by the OS 1416 * @reply: reply message frame(lower 32bit addr) 1417 * 1418 * Return: 1419 * 1 meaning mf should be freed from _base_interrupt 1420 * 0 means the mf is freed from this function. 1421 */ 1422 u8 1423 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1424 u32 reply) 1425 { 1426 MPI2DefaultReply_t *mpi_reply; 1427 1428 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1429 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 1430 return mpt3sas_check_for_pending_internal_cmds(ioc, smid); 1431 1432 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 1433 return 1; 1434 1435 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 1436 if (mpi_reply) { 1437 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 1438 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 1439 } 1440 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 1441 1442 complete(&ioc->base_cmds.done); 1443 return 1; 1444 } 1445 1446 /** 1447 * _base_async_event - main callback handler for firmware asyn events 1448 * @ioc: per adapter object 1449 * @msix_index: MSIX table index supplied by the OS 1450 * @reply: reply message frame(lower 32bit addr) 1451 * 1452 * Return: 1453 * 1 meaning mf should be freed from _base_interrupt 1454 * 0 means the mf is freed from this function. 1455 */ 1456 static u8 1457 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 1458 { 1459 Mpi2EventNotificationReply_t *mpi_reply; 1460 Mpi2EventAckRequest_t *ack_request; 1461 u16 smid; 1462 struct _event_ack_list *delayed_event_ack; 1463 1464 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1465 if (!mpi_reply) 1466 return 1; 1467 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 1468 return 1; 1469 1470 _base_display_event_data(ioc, mpi_reply); 1471 1472 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 1473 goto out; 1474 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 1475 if (!smid) { 1476 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), 1477 GFP_ATOMIC); 1478 if (!delayed_event_ack) 1479 goto out; 1480 INIT_LIST_HEAD(&delayed_event_ack->list); 1481 delayed_event_ack->Event = mpi_reply->Event; 1482 delayed_event_ack->EventContext = mpi_reply->EventContext; 1483 list_add_tail(&delayed_event_ack->list, 1484 &ioc->delayed_event_ack_list); 1485 dewtprintk(ioc, 1486 ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n", 1487 le16_to_cpu(mpi_reply->Event))); 1488 goto out; 1489 } 1490 1491 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 1492 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 1493 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 1494 ack_request->Event = mpi_reply->Event; 1495 ack_request->EventContext = mpi_reply->EventContext; 1496 ack_request->VF_ID = 0; /* TODO */ 1497 ack_request->VP_ID = 0; 1498 ioc->put_smid_default(ioc, smid); 1499 1500 out: 1501 1502 /* scsih callback handler */ 1503 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 1504 1505 /* ctl callback handler */ 1506 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 1507 1508 return 1; 1509 } 1510 1511 static struct scsiio_tracker * 1512 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1513 { 1514 struct scsi_cmnd *cmd; 1515 1516 if (WARN_ON(!smid) || 1517 WARN_ON(smid >= ioc->hi_priority_smid)) 1518 return NULL; 1519 1520 cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 1521 if (cmd) 1522 return scsi_cmd_priv(cmd); 1523 1524 return NULL; 1525 } 1526 1527 /** 1528 * _base_get_cb_idx - obtain the callback index 1529 * @ioc: per adapter object 1530 * @smid: system request message index 1531 * 1532 * Return: callback index. 1533 */ 1534 static u8 1535 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1536 { 1537 int i; 1538 u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1; 1539 u8 cb_idx = 0xFF; 1540 1541 if (smid < ioc->hi_priority_smid) { 1542 struct scsiio_tracker *st; 1543 1544 if (smid < ctl_smid) { 1545 st = _get_st_from_smid(ioc, smid); 1546 if (st) 1547 cb_idx = st->cb_idx; 1548 } else if (smid == ctl_smid) 1549 cb_idx = ioc->ctl_cb_idx; 1550 } else if (smid < ioc->internal_smid) { 1551 i = smid - ioc->hi_priority_smid; 1552 cb_idx = ioc->hpr_lookup[i].cb_idx; 1553 } else if (smid <= ioc->hba_queue_depth) { 1554 i = smid - ioc->internal_smid; 1555 cb_idx = ioc->internal_lookup[i].cb_idx; 1556 } 1557 return cb_idx; 1558 } 1559 1560 /** 1561 * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues 1562 * when driver is flushing out the IOs. 1563 * @ioc: per adapter object 1564 * 1565 * Pause polling on the mq poll (io uring) queues when driver is flushing 1566 * out the IOs. Otherwise we may see the race condition of completing the same 1567 * IO from two paths. 1568 * 1569 * Returns nothing. 1570 */ 1571 void 1572 mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc) 1573 { 1574 int iopoll_q_count = 1575 ioc->reply_queue_count - ioc->iopoll_q_start_index; 1576 int qid; 1577 1578 for (qid = 0; qid < iopoll_q_count; qid++) 1579 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1); 1580 1581 /* 1582 * wait for current poll to complete. 1583 */ 1584 for (qid = 0; qid < iopoll_q_count; qid++) { 1585 while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) { 1586 cpu_relax(); 1587 udelay(500); 1588 } 1589 } 1590 } 1591 1592 /** 1593 * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues. 1594 * @ioc: per adapter object 1595 * 1596 * Returns nothing. 1597 */ 1598 void 1599 mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc) 1600 { 1601 int iopoll_q_count = 1602 ioc->reply_queue_count - ioc->iopoll_q_start_index; 1603 int qid; 1604 1605 for (qid = 0; qid < iopoll_q_count; qid++) 1606 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0); 1607 } 1608 1609 /** 1610 * mpt3sas_base_mask_interrupts - disable interrupts 1611 * @ioc: per adapter object 1612 * 1613 * Disabling ResetIRQ, Reply and Doorbell Interrupts 1614 */ 1615 void 1616 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1617 { 1618 u32 him_register; 1619 1620 ioc->mask_interrupts = 1; 1621 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); 1622 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 1623 writel(him_register, &ioc->chip->HostInterruptMask); 1624 ioc->base_readl(&ioc->chip->HostInterruptMask); 1625 } 1626 1627 /** 1628 * mpt3sas_base_unmask_interrupts - enable interrupts 1629 * @ioc: per adapter object 1630 * 1631 * Enabling only Reply Interrupts 1632 */ 1633 void 1634 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1635 { 1636 u32 him_register; 1637 1638 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); 1639 him_register &= ~MPI2_HIM_RIM; 1640 writel(him_register, &ioc->chip->HostInterruptMask); 1641 ioc->mask_interrupts = 0; 1642 } 1643 1644 union reply_descriptor { 1645 u64 word; 1646 struct { 1647 u32 low; 1648 u32 high; 1649 } u; 1650 }; 1651 1652 static u32 base_mod64(u64 dividend, u32 divisor) 1653 { 1654 u32 remainder; 1655 1656 if (!divisor) 1657 pr_err("mpt3sas: DIVISOR is zero, in div fn\n"); 1658 remainder = do_div(dividend, divisor); 1659 return remainder; 1660 } 1661 1662 /** 1663 * _base_process_reply_queue - Process reply descriptors from reply 1664 * descriptor post queue. 1665 * @reply_q: per IRQ's reply queue object. 1666 * 1667 * Return: number of reply descriptors processed from reply 1668 * descriptor queue. 1669 */ 1670 static int 1671 _base_process_reply_queue(struct adapter_reply_queue *reply_q) 1672 { 1673 union reply_descriptor rd; 1674 u64 completed_cmds; 1675 u8 request_descript_type; 1676 u16 smid; 1677 u8 cb_idx; 1678 u32 reply; 1679 u8 msix_index = reply_q->msix_index; 1680 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 1681 Mpi2ReplyDescriptorsUnion_t *rpf; 1682 u8 rc; 1683 1684 completed_cmds = 0; 1685 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 1686 return completed_cmds; 1687 1688 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 1689 request_descript_type = rpf->Default.ReplyFlags 1690 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1691 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 1692 atomic_dec(&reply_q->busy); 1693 return completed_cmds; 1694 } 1695 1696 cb_idx = 0xFF; 1697 do { 1698 rd.word = le64_to_cpu(rpf->Words); 1699 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 1700 goto out; 1701 reply = 0; 1702 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 1703 if (request_descript_type == 1704 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 1705 request_descript_type == 1706 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 1707 request_descript_type == 1708 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) { 1709 cb_idx = _base_get_cb_idx(ioc, smid); 1710 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1711 (likely(mpt_callbacks[cb_idx] != NULL))) { 1712 rc = mpt_callbacks[cb_idx](ioc, smid, 1713 msix_index, 0); 1714 if (rc) 1715 mpt3sas_base_free_smid(ioc, smid); 1716 } 1717 } else if (request_descript_type == 1718 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 1719 reply = le32_to_cpu( 1720 rpf->AddressReply.ReplyFrameAddress); 1721 if (reply > ioc->reply_dma_max_address || 1722 reply < ioc->reply_dma_min_address) 1723 reply = 0; 1724 if (smid) { 1725 cb_idx = _base_get_cb_idx(ioc, smid); 1726 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1727 (likely(mpt_callbacks[cb_idx] != NULL))) { 1728 rc = mpt_callbacks[cb_idx](ioc, smid, 1729 msix_index, reply); 1730 if (reply) 1731 _base_display_reply_info(ioc, 1732 smid, msix_index, reply); 1733 if (rc) 1734 mpt3sas_base_free_smid(ioc, 1735 smid); 1736 } 1737 } else { 1738 _base_async_event(ioc, msix_index, reply); 1739 } 1740 1741 /* reply free queue handling */ 1742 if (reply) { 1743 ioc->reply_free_host_index = 1744 (ioc->reply_free_host_index == 1745 (ioc->reply_free_queue_depth - 1)) ? 1746 0 : ioc->reply_free_host_index + 1; 1747 ioc->reply_free[ioc->reply_free_host_index] = 1748 cpu_to_le32(reply); 1749 if (ioc->is_mcpu_endpoint) 1750 _base_clone_reply_to_sys_mem(ioc, 1751 reply, 1752 ioc->reply_free_host_index); 1753 writel(ioc->reply_free_host_index, 1754 &ioc->chip->ReplyFreeHostIndex); 1755 } 1756 } 1757 1758 rpf->Words = cpu_to_le64(ULLONG_MAX); 1759 reply_q->reply_post_host_index = 1760 (reply_q->reply_post_host_index == 1761 (ioc->reply_post_queue_depth - 1)) ? 0 : 1762 reply_q->reply_post_host_index + 1; 1763 request_descript_type = 1764 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1765 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1766 completed_cmds++; 1767 /* Update the reply post host index after continuously 1768 * processing the threshold number of Reply Descriptors. 1769 * So that FW can find enough entries to post the Reply 1770 * Descriptors in the reply descriptor post queue. 1771 */ 1772 if (completed_cmds >= ioc->thresh_hold) { 1773 if (ioc->combined_reply_queue) { 1774 writel(reply_q->reply_post_host_index | 1775 ((msix_index & 7) << 1776 MPI2_RPHI_MSIX_INDEX_SHIFT), 1777 ioc->replyPostRegisterIndex[msix_index/8]); 1778 } else { 1779 writel(reply_q->reply_post_host_index | 1780 (msix_index << 1781 MPI2_RPHI_MSIX_INDEX_SHIFT), 1782 &ioc->chip->ReplyPostHostIndex); 1783 } 1784 if (!reply_q->is_iouring_poll_q && 1785 !reply_q->irq_poll_scheduled) { 1786 reply_q->irq_poll_scheduled = true; 1787 irq_poll_sched(&reply_q->irqpoll); 1788 } 1789 atomic_dec(&reply_q->busy); 1790 return completed_cmds; 1791 } 1792 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1793 goto out; 1794 if (!reply_q->reply_post_host_index) 1795 rpf = reply_q->reply_post_free; 1796 else 1797 rpf++; 1798 } while (1); 1799 1800 out: 1801 1802 if (!completed_cmds) { 1803 atomic_dec(&reply_q->busy); 1804 return completed_cmds; 1805 } 1806 1807 if (ioc->is_warpdrive) { 1808 writel(reply_q->reply_post_host_index, 1809 ioc->reply_post_host_index[msix_index]); 1810 atomic_dec(&reply_q->busy); 1811 return completed_cmds; 1812 } 1813 1814 /* Update Reply Post Host Index. 1815 * For those HBA's which support combined reply queue feature 1816 * 1. Get the correct Supplemental Reply Post Host Index Register. 1817 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1818 * Index Register address bank i.e replyPostRegisterIndex[], 1819 * 2. Then update this register with new reply host index value 1820 * in ReplyPostIndex field and the MSIxIndex field with 1821 * msix_index value reduced to a value between 0 and 7, 1822 * using a modulo 8 operation. Since each Supplemental Reply Post 1823 * Host Index Register supports 8 MSI-X vectors. 1824 * 1825 * For other HBA's just update the Reply Post Host Index register with 1826 * new reply host index value in ReplyPostIndex Field and msix_index 1827 * value in MSIxIndex field. 1828 */ 1829 if (ioc->combined_reply_queue) 1830 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1831 MPI2_RPHI_MSIX_INDEX_SHIFT), 1832 ioc->replyPostRegisterIndex[msix_index/8]); 1833 else 1834 writel(reply_q->reply_post_host_index | (msix_index << 1835 MPI2_RPHI_MSIX_INDEX_SHIFT), 1836 &ioc->chip->ReplyPostHostIndex); 1837 atomic_dec(&reply_q->busy); 1838 return completed_cmds; 1839 } 1840 1841 /** 1842 * mpt3sas_blk_mq_poll - poll the blk mq poll queue 1843 * @shost: Scsi_Host object 1844 * @queue_num: hw ctx queue number 1845 * 1846 * Return number of entries that has been processed from poll queue. 1847 */ 1848 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 1849 { 1850 struct MPT3SAS_ADAPTER *ioc = 1851 (struct MPT3SAS_ADAPTER *)shost->hostdata; 1852 struct adapter_reply_queue *reply_q; 1853 int num_entries = 0; 1854 int qid = queue_num - ioc->iopoll_q_start_index; 1855 1856 if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) || 1857 !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1)) 1858 return 0; 1859 1860 reply_q = ioc->io_uring_poll_queues[qid].reply_q; 1861 1862 num_entries = _base_process_reply_queue(reply_q); 1863 atomic_dec(&ioc->io_uring_poll_queues[qid].busy); 1864 1865 return num_entries; 1866 } 1867 1868 /** 1869 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 1870 * @irq: irq number (not used) 1871 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 1872 * 1873 * Return: IRQ_HANDLED if processed, else IRQ_NONE. 1874 */ 1875 static irqreturn_t 1876 _base_interrupt(int irq, void *bus_id) 1877 { 1878 struct adapter_reply_queue *reply_q = bus_id; 1879 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 1880 1881 if (ioc->mask_interrupts) 1882 return IRQ_NONE; 1883 if (reply_q->irq_poll_scheduled) 1884 return IRQ_HANDLED; 1885 return ((_base_process_reply_queue(reply_q) > 0) ? 1886 IRQ_HANDLED : IRQ_NONE); 1887 } 1888 1889 /** 1890 * _base_irqpoll - IRQ poll callback handler 1891 * @irqpoll: irq_poll object 1892 * @budget: irq poll weight 1893 * 1894 * Return: number of reply descriptors processed 1895 */ 1896 static int 1897 _base_irqpoll(struct irq_poll *irqpoll, int budget) 1898 { 1899 struct adapter_reply_queue *reply_q; 1900 int num_entries = 0; 1901 1902 reply_q = container_of(irqpoll, struct adapter_reply_queue, 1903 irqpoll); 1904 if (reply_q->irq_line_enable) { 1905 disable_irq_nosync(reply_q->os_irq); 1906 reply_q->irq_line_enable = false; 1907 } 1908 num_entries = _base_process_reply_queue(reply_q); 1909 if (num_entries < budget) { 1910 irq_poll_complete(irqpoll); 1911 reply_q->irq_poll_scheduled = false; 1912 reply_q->irq_line_enable = true; 1913 enable_irq(reply_q->os_irq); 1914 /* 1915 * Go for one more round of processing the 1916 * reply descriptor post queue in case the HBA 1917 * Firmware has posted some reply descriptors 1918 * while reenabling the IRQ. 1919 */ 1920 _base_process_reply_queue(reply_q); 1921 } 1922 1923 return num_entries; 1924 } 1925 1926 /** 1927 * _base_init_irqpolls - initliaze IRQ polls 1928 * @ioc: per adapter object 1929 * 1930 * Return: nothing 1931 */ 1932 static void 1933 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc) 1934 { 1935 struct adapter_reply_queue *reply_q, *next; 1936 1937 if (list_empty(&ioc->reply_queue_list)) 1938 return; 1939 1940 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1941 if (reply_q->is_iouring_poll_q) 1942 continue; 1943 irq_poll_init(&reply_q->irqpoll, 1944 ioc->hba_queue_depth/4, _base_irqpoll); 1945 reply_q->irq_poll_scheduled = false; 1946 reply_q->irq_line_enable = true; 1947 reply_q->os_irq = pci_irq_vector(ioc->pdev, 1948 reply_q->msix_index); 1949 } 1950 } 1951 1952 /** 1953 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1954 * @ioc: per adapter object 1955 * 1956 * Return: Whether or not MSI/X is enabled. 1957 */ 1958 static inline int 1959 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1960 { 1961 return (ioc->facts.IOCCapabilities & 1962 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1963 } 1964 1965 /** 1966 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts 1967 * @ioc: per adapter object 1968 * @poll: poll over reply descriptor pools incase interrupt for 1969 * timed-out SCSI command got delayed 1970 * Context: non-ISR context 1971 * 1972 * Called when a Task Management request has completed. 1973 */ 1974 void 1975 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll) 1976 { 1977 struct adapter_reply_queue *reply_q; 1978 1979 /* If MSIX capability is turned off 1980 * then multi-queues are not enabled 1981 */ 1982 if (!_base_is_controller_msix_enabled(ioc)) 1983 return; 1984 1985 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1986 if (ioc->shost_recovery || ioc->remove_host || 1987 ioc->pci_error_recovery) 1988 return; 1989 /* TMs are on msix_index == 0 */ 1990 if (reply_q->msix_index == 0) 1991 continue; 1992 1993 if (reply_q->is_iouring_poll_q) { 1994 _base_process_reply_queue(reply_q); 1995 continue; 1996 } 1997 1998 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); 1999 if (reply_q->irq_poll_scheduled) { 2000 /* Calling irq_poll_disable will wait for any pending 2001 * callbacks to have completed. 2002 */ 2003 irq_poll_disable(&reply_q->irqpoll); 2004 irq_poll_enable(&reply_q->irqpoll); 2005 /* check how the scheduled poll has ended, 2006 * clean up only if necessary 2007 */ 2008 if (reply_q->irq_poll_scheduled) { 2009 reply_q->irq_poll_scheduled = false; 2010 reply_q->irq_line_enable = true; 2011 enable_irq(reply_q->os_irq); 2012 } 2013 } 2014 2015 if (poll) 2016 _base_process_reply_queue(reply_q); 2017 } 2018 } 2019 2020 /** 2021 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 2022 * @cb_idx: callback index 2023 */ 2024 void 2025 mpt3sas_base_release_callback_handler(u8 cb_idx) 2026 { 2027 mpt_callbacks[cb_idx] = NULL; 2028 } 2029 2030 /** 2031 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 2032 * @cb_func: callback function 2033 * 2034 * Return: Index of @cb_func. 2035 */ 2036 u8 2037 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 2038 { 2039 u8 cb_idx; 2040 2041 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 2042 if (mpt_callbacks[cb_idx] == NULL) 2043 break; 2044 2045 mpt_callbacks[cb_idx] = cb_func; 2046 return cb_idx; 2047 } 2048 2049 /** 2050 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 2051 */ 2052 void 2053 mpt3sas_base_initialize_callback_handler(void) 2054 { 2055 u8 cb_idx; 2056 2057 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 2058 mpt3sas_base_release_callback_handler(cb_idx); 2059 } 2060 2061 2062 /** 2063 * _base_build_zero_len_sge - build zero length sg entry 2064 * @ioc: per adapter object 2065 * @paddr: virtual address for SGE 2066 * 2067 * Create a zero length scatter gather entry to insure the IOCs hardware has 2068 * something to use if the target device goes brain dead and tries 2069 * to send data even when none is asked for. 2070 */ 2071 static void 2072 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 2073 { 2074 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 2075 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 2076 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 2077 MPI2_SGE_FLAGS_SHIFT); 2078 ioc->base_add_sg_single(paddr, flags_length, -1); 2079 } 2080 2081 /** 2082 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 2083 * @paddr: virtual address for SGE 2084 * @flags_length: SGE flags and data transfer length 2085 * @dma_addr: Physical address 2086 */ 2087 static void 2088 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 2089 { 2090 Mpi2SGESimple32_t *sgel = paddr; 2091 2092 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 2093 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 2094 sgel->FlagsLength = cpu_to_le32(flags_length); 2095 sgel->Address = cpu_to_le32(dma_addr); 2096 } 2097 2098 2099 /** 2100 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 2101 * @paddr: virtual address for SGE 2102 * @flags_length: SGE flags and data transfer length 2103 * @dma_addr: Physical address 2104 */ 2105 static void 2106 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 2107 { 2108 Mpi2SGESimple64_t *sgel = paddr; 2109 2110 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 2111 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 2112 sgel->FlagsLength = cpu_to_le32(flags_length); 2113 sgel->Address = cpu_to_le64(dma_addr); 2114 } 2115 2116 /** 2117 * _base_get_chain_buffer_tracker - obtain chain tracker 2118 * @ioc: per adapter object 2119 * @scmd: SCSI commands of the IO request 2120 * 2121 * Return: chain tracker from chain_lookup table using key as 2122 * smid and smid's chain_offset. 2123 */ 2124 static struct chain_tracker * 2125 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, 2126 struct scsi_cmnd *scmd) 2127 { 2128 struct chain_tracker *chain_req; 2129 struct scsiio_tracker *st = scsi_cmd_priv(scmd); 2130 u16 smid = st->smid; 2131 u8 chain_offset = 2132 atomic_read(&ioc->chain_lookup[smid - 1].chain_offset); 2133 2134 if (chain_offset == ioc->chains_needed_per_io) 2135 return NULL; 2136 2137 chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset]; 2138 atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset); 2139 return chain_req; 2140 } 2141 2142 2143 /** 2144 * _base_build_sg - build generic sg 2145 * @ioc: per adapter object 2146 * @psge: virtual address for SGE 2147 * @data_out_dma: physical address for WRITES 2148 * @data_out_sz: data xfer size for WRITES 2149 * @data_in_dma: physical address for READS 2150 * @data_in_sz: data xfer size for READS 2151 */ 2152 static void 2153 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 2154 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2155 size_t data_in_sz) 2156 { 2157 u32 sgl_flags; 2158 2159 if (!data_out_sz && !data_in_sz) { 2160 _base_build_zero_len_sge(ioc, psge); 2161 return; 2162 } 2163 2164 if (data_out_sz && data_in_sz) { 2165 /* WRITE sgel first */ 2166 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2167 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 2168 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2169 ioc->base_add_sg_single(psge, sgl_flags | 2170 data_out_sz, data_out_dma); 2171 2172 /* incr sgel */ 2173 psge += ioc->sge_size; 2174 2175 /* READ sgel last */ 2176 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2177 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2178 MPI2_SGE_FLAGS_END_OF_LIST); 2179 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2180 ioc->base_add_sg_single(psge, sgl_flags | 2181 data_in_sz, data_in_dma); 2182 } else if (data_out_sz) /* WRITE */ { 2183 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2184 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2185 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 2186 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2187 ioc->base_add_sg_single(psge, sgl_flags | 2188 data_out_sz, data_out_dma); 2189 } else if (data_in_sz) /* READ */ { 2190 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 2191 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 2192 MPI2_SGE_FLAGS_END_OF_LIST); 2193 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2194 ioc->base_add_sg_single(psge, sgl_flags | 2195 data_in_sz, data_in_dma); 2196 } 2197 } 2198 2199 /* IEEE format sgls */ 2200 2201 /** 2202 * _base_build_nvme_prp - This function is called for NVMe end devices to build 2203 * a native SGL (NVMe PRP). 2204 * @ioc: per adapter object 2205 * @smid: system request message index for getting asscociated SGL 2206 * @nvme_encap_request: the NVMe request msg frame pointer 2207 * @data_out_dma: physical address for WRITES 2208 * @data_out_sz: data xfer size for WRITES 2209 * @data_in_dma: physical address for READS 2210 * @data_in_sz: data xfer size for READS 2211 * 2212 * The native SGL is built starting in the first PRP 2213 * entry of the NVMe message (PRP1). If the data buffer is small enough to be 2214 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is 2215 * used to describe a larger data buffer. If the data buffer is too large to 2216 * describe using the two PRP entriess inside the NVMe message, then PRP1 2217 * describes the first data memory segment, and PRP2 contains a pointer to a PRP 2218 * list located elsewhere in memory to describe the remaining data memory 2219 * segments. The PRP list will be contiguous. 2220 * 2221 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 2222 * consists of a list of PRP entries to describe a number of noncontigous 2223 * physical memory segments as a single memory buffer, just as a SGL does. Note 2224 * however, that this function is only used by the IOCTL call, so the memory 2225 * given will be guaranteed to be contiguous. There is no need to translate 2226 * non-contiguous SGL into a PRP in this case. All PRPs will describe 2227 * contiguous space that is one page size each. 2228 * 2229 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 2230 * a PRP list pointer or a PRP element, depending upon the command. PRP2 2231 * contains the second PRP element if the memory being described fits within 2 2232 * PRP entries, or a PRP list pointer if the PRP spans more than two entries. 2233 * 2234 * A PRP list pointer contains the address of a PRP list, structured as a linear 2235 * array of PRP entries. Each PRP entry in this list describes a segment of 2236 * physical memory. 2237 * 2238 * Each 64-bit PRP entry comprises an address and an offset field. The address 2239 * always points at the beginning of a 4KB physical memory page, and the offset 2240 * describes where within that 4KB page the memory segment begins. Only the 2241 * first element in a PRP list may contain a non-zero offset, implying that all 2242 * memory segments following the first begin at the start of a 4KB page. 2243 * 2244 * Each PRP element normally describes 4KB of physical memory, with exceptions 2245 * for the first and last elements in the list. If the memory being described 2246 * by the list begins at a non-zero offset within the first 4KB page, then the 2247 * first PRP element will contain a non-zero offset indicating where the region 2248 * begins within the 4KB page. The last memory segment may end before the end 2249 * of the 4KB segment, depending upon the overall size of the memory being 2250 * described by the PRP list. 2251 * 2252 * Since PRP entries lack any indication of size, the overall data buffer length 2253 * is used to determine where the end of the data memory buffer is located, and 2254 * how many PRP entries are required to describe it. 2255 */ 2256 static void 2257 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2258 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, 2259 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2260 size_t data_in_sz) 2261 { 2262 int prp_size = NVME_PRP_SIZE; 2263 __le64 *prp_entry, *prp1_entry, *prp2_entry; 2264 __le64 *prp_page; 2265 dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; 2266 u32 offset, entry_len; 2267 u32 page_mask_result, page_mask; 2268 size_t length; 2269 struct mpt3sas_nvme_cmd *nvme_cmd = 2270 (void *)nvme_encap_request->NVMe_Command; 2271 2272 /* 2273 * Not all commands require a data transfer. If no data, just return 2274 * without constructing any PRP. 2275 */ 2276 if (!data_in_sz && !data_out_sz) 2277 return; 2278 prp1_entry = &nvme_cmd->prp1; 2279 prp2_entry = &nvme_cmd->prp2; 2280 prp_entry = prp1_entry; 2281 /* 2282 * For the PRP entries, use the specially allocated buffer of 2283 * contiguous memory. 2284 */ 2285 prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); 2286 prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 2287 2288 /* 2289 * Check if we are within 1 entry of a page boundary we don't 2290 * want our first entry to be a PRP List entry. 2291 */ 2292 page_mask = ioc->page_size - 1; 2293 page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; 2294 if (!page_mask_result) { 2295 /* Bump up to next page boundary. */ 2296 prp_page = (__le64 *)((u8 *)prp_page + prp_size); 2297 prp_page_dma = prp_page_dma + prp_size; 2298 } 2299 2300 /* 2301 * Set PRP physical pointer, which initially points to the current PRP 2302 * DMA memory page. 2303 */ 2304 prp_entry_dma = prp_page_dma; 2305 2306 /* Get physical address and length of the data buffer. */ 2307 if (data_in_sz) { 2308 dma_addr = data_in_dma; 2309 length = data_in_sz; 2310 } else { 2311 dma_addr = data_out_dma; 2312 length = data_out_sz; 2313 } 2314 2315 /* Loop while the length is not zero. */ 2316 while (length) { 2317 /* 2318 * Check if we need to put a list pointer here if we are at 2319 * page boundary - prp_size (8 bytes). 2320 */ 2321 page_mask_result = (prp_entry_dma + prp_size) & page_mask; 2322 if (!page_mask_result) { 2323 /* 2324 * This is the last entry in a PRP List, so we need to 2325 * put a PRP list pointer here. What this does is: 2326 * - bump the current memory pointer to the next 2327 * address, which will be the next full page. 2328 * - set the PRP Entry to point to that page. This 2329 * is now the PRP List pointer. 2330 * - bump the PRP Entry pointer the start of the 2331 * next page. Since all of this PRP memory is 2332 * contiguous, no need to get a new page - it's 2333 * just the next address. 2334 */ 2335 prp_entry_dma++; 2336 *prp_entry = cpu_to_le64(prp_entry_dma); 2337 prp_entry++; 2338 } 2339 2340 /* Need to handle if entry will be part of a page. */ 2341 offset = dma_addr & page_mask; 2342 entry_len = ioc->page_size - offset; 2343 2344 if (prp_entry == prp1_entry) { 2345 /* 2346 * Must fill in the first PRP pointer (PRP1) before 2347 * moving on. 2348 */ 2349 *prp1_entry = cpu_to_le64(dma_addr); 2350 2351 /* 2352 * Now point to the second PRP entry within the 2353 * command (PRP2). 2354 */ 2355 prp_entry = prp2_entry; 2356 } else if (prp_entry == prp2_entry) { 2357 /* 2358 * Should the PRP2 entry be a PRP List pointer or just 2359 * a regular PRP pointer? If there is more than one 2360 * more page of data, must use a PRP List pointer. 2361 */ 2362 if (length > ioc->page_size) { 2363 /* 2364 * PRP2 will contain a PRP List pointer because 2365 * more PRP's are needed with this command. The 2366 * list will start at the beginning of the 2367 * contiguous buffer. 2368 */ 2369 *prp2_entry = cpu_to_le64(prp_entry_dma); 2370 2371 /* 2372 * The next PRP Entry will be the start of the 2373 * first PRP List. 2374 */ 2375 prp_entry = prp_page; 2376 } else { 2377 /* 2378 * After this, the PRP Entries are complete. 2379 * This command uses 2 PRP's and no PRP list. 2380 */ 2381 *prp2_entry = cpu_to_le64(dma_addr); 2382 } 2383 } else { 2384 /* 2385 * Put entry in list and bump the addresses. 2386 * 2387 * After PRP1 and PRP2 are filled in, this will fill in 2388 * all remaining PRP entries in a PRP List, one per 2389 * each time through the loop. 2390 */ 2391 *prp_entry = cpu_to_le64(dma_addr); 2392 prp_entry++; 2393 prp_entry_dma++; 2394 } 2395 2396 /* 2397 * Bump the phys address of the command's data buffer by the 2398 * entry_len. 2399 */ 2400 dma_addr += entry_len; 2401 2402 /* Decrement length accounting for last partial page. */ 2403 if (entry_len > length) 2404 length = 0; 2405 else 2406 length -= entry_len; 2407 } 2408 } 2409 2410 /** 2411 * base_make_prp_nvme - Prepare PRPs (Physical Region Page) - 2412 * SGLs specific to NVMe drives only 2413 * 2414 * @ioc: per adapter object 2415 * @scmd: SCSI command from the mid-layer 2416 * @mpi_request: mpi request 2417 * @smid: msg Index 2418 * @sge_count: scatter gather element count. 2419 * 2420 * Return: true: PRPs are built 2421 * false: IEEE SGLs needs to be built 2422 */ 2423 static void 2424 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, 2425 struct scsi_cmnd *scmd, 2426 Mpi25SCSIIORequest_t *mpi_request, 2427 u16 smid, int sge_count) 2428 { 2429 int sge_len, num_prp_in_chain = 0; 2430 Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; 2431 __le64 *curr_buff; 2432 dma_addr_t msg_dma, sge_addr, offset; 2433 u32 page_mask, page_mask_result; 2434 struct scatterlist *sg_scmd; 2435 u32 first_prp_len; 2436 int data_len = scsi_bufflen(scmd); 2437 u32 nvme_pg_size; 2438 2439 nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); 2440 /* 2441 * Nvme has a very convoluted prp format. One prp is required 2442 * for each page or partial page. Driver need to split up OS sg_list 2443 * entries if it is longer than one page or cross a page 2444 * boundary. Driver also have to insert a PRP list pointer entry as 2445 * the last entry in each physical page of the PRP list. 2446 * 2447 * NOTE: The first PRP "entry" is actually placed in the first 2448 * SGL entry in the main message as IEEE 64 format. The 2nd 2449 * entry in the main message is the chain element, and the rest 2450 * of the PRP entries are built in the contiguous pcie buffer. 2451 */ 2452 page_mask = nvme_pg_size - 1; 2453 2454 /* 2455 * Native SGL is needed. 2456 * Put a chain element in main message frame that points to the first 2457 * chain buffer. 2458 * 2459 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 2460 * a native SGL. 2461 */ 2462 2463 /* Set main message chain element pointer */ 2464 main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2465 /* 2466 * For NVMe the chain element needs to be the 2nd SG entry in the main 2467 * message. 2468 */ 2469 main_chain_element = (Mpi25IeeeSgeChain64_t *) 2470 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 2471 2472 /* 2473 * For the PRP entries, use the specially allocated buffer of 2474 * contiguous memory. Normal chain buffers can't be used 2475 * because each chain buffer would need to be the size of an OS 2476 * page (4k). 2477 */ 2478 curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); 2479 msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 2480 2481 main_chain_element->Address = cpu_to_le64(msg_dma); 2482 main_chain_element->NextChainOffset = 0; 2483 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2484 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2485 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 2486 2487 /* Build first prp, sge need not to be page aligned*/ 2488 ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2489 sg_scmd = scsi_sglist(scmd); 2490 sge_addr = sg_dma_address(sg_scmd); 2491 sge_len = sg_dma_len(sg_scmd); 2492 2493 offset = sge_addr & page_mask; 2494 first_prp_len = nvme_pg_size - offset; 2495 2496 ptr_first_sgl->Address = cpu_to_le64(sge_addr); 2497 ptr_first_sgl->Length = cpu_to_le32(first_prp_len); 2498 2499 data_len -= first_prp_len; 2500 2501 if (sge_len > first_prp_len) { 2502 sge_addr += first_prp_len; 2503 sge_len -= first_prp_len; 2504 } else if (data_len && (sge_len == first_prp_len)) { 2505 sg_scmd = sg_next(sg_scmd); 2506 sge_addr = sg_dma_address(sg_scmd); 2507 sge_len = sg_dma_len(sg_scmd); 2508 } 2509 2510 for (;;) { 2511 offset = sge_addr & page_mask; 2512 2513 /* Put PRP pointer due to page boundary*/ 2514 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; 2515 if (unlikely(!page_mask_result)) { 2516 scmd_printk(KERN_NOTICE, 2517 scmd, "page boundary curr_buff: 0x%p\n", 2518 curr_buff); 2519 msg_dma += 8; 2520 *curr_buff = cpu_to_le64(msg_dma); 2521 curr_buff++; 2522 num_prp_in_chain++; 2523 } 2524 2525 *curr_buff = cpu_to_le64(sge_addr); 2526 curr_buff++; 2527 msg_dma += 8; 2528 num_prp_in_chain++; 2529 2530 sge_addr += nvme_pg_size; 2531 sge_len -= nvme_pg_size; 2532 data_len -= nvme_pg_size; 2533 2534 if (data_len <= 0) 2535 break; 2536 2537 if (sge_len > 0) 2538 continue; 2539 2540 sg_scmd = sg_next(sg_scmd); 2541 sge_addr = sg_dma_address(sg_scmd); 2542 sge_len = sg_dma_len(sg_scmd); 2543 } 2544 2545 main_chain_element->Length = 2546 cpu_to_le32(num_prp_in_chain * sizeof(u64)); 2547 return; 2548 } 2549 2550 static bool 2551 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, 2552 struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) 2553 { 2554 u32 data_length = 0; 2555 bool build_prp = true; 2556 2557 data_length = scsi_bufflen(scmd); 2558 if (pcie_device && 2559 (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) { 2560 build_prp = false; 2561 return build_prp; 2562 } 2563 2564 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 2565 * we built IEEE SGL 2566 */ 2567 if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) 2568 build_prp = false; 2569 2570 return build_prp; 2571 } 2572 2573 /** 2574 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to 2575 * determine if the driver needs to build a native SGL. If so, that native 2576 * SGL is built in the special contiguous buffers allocated especially for 2577 * PCIe SGL creation. If the driver will not build a native SGL, return 2578 * TRUE and a normal IEEE SGL will be built. Currently this routine 2579 * supports NVMe. 2580 * @ioc: per adapter object 2581 * @mpi_request: mf request pointer 2582 * @smid: system request message index 2583 * @scmd: scsi command 2584 * @pcie_device: points to the PCIe device's info 2585 * 2586 * Return: 0 if native SGL was built, 1 if no SGL was built 2587 */ 2588 static int 2589 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, 2590 Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, 2591 struct _pcie_device *pcie_device) 2592 { 2593 int sges_left; 2594 2595 /* Get the SG list pointer and info. */ 2596 sges_left = scsi_dma_map(scmd); 2597 if (sges_left < 0) 2598 return 1; 2599 2600 /* Check if we need to build a native SG list. */ 2601 if (!base_is_prp_possible(ioc, pcie_device, 2602 scmd, sges_left)) { 2603 /* We built a native SG list, just return. */ 2604 goto out; 2605 } 2606 2607 /* 2608 * Build native NVMe PRP. 2609 */ 2610 base_make_prp_nvme(ioc, scmd, mpi_request, 2611 smid, sges_left); 2612 2613 return 0; 2614 out: 2615 scsi_dma_unmap(scmd); 2616 return 1; 2617 } 2618 2619 /** 2620 * _base_add_sg_single_ieee - add sg element for IEEE format 2621 * @paddr: virtual address for SGE 2622 * @flags: SGE flags 2623 * @chain_offset: number of 128 byte elements from start of segment 2624 * @length: data transfer length 2625 * @dma_addr: Physical address 2626 */ 2627 static void 2628 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 2629 dma_addr_t dma_addr) 2630 { 2631 Mpi25IeeeSgeChain64_t *sgel = paddr; 2632 2633 sgel->Flags = flags; 2634 sgel->NextChainOffset = chain_offset; 2635 sgel->Length = cpu_to_le32(length); 2636 sgel->Address = cpu_to_le64(dma_addr); 2637 } 2638 2639 /** 2640 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 2641 * @ioc: per adapter object 2642 * @paddr: virtual address for SGE 2643 * 2644 * Create a zero length scatter gather entry to insure the IOCs hardware has 2645 * something to use if the target device goes brain dead and tries 2646 * to send data even when none is asked for. 2647 */ 2648 static void 2649 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 2650 { 2651 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2652 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2653 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 2654 2655 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 2656 } 2657 2658 /** 2659 * _base_build_sg_scmd - main sg creation routine 2660 * pcie_device is unused here! 2661 * @ioc: per adapter object 2662 * @scmd: scsi command 2663 * @smid: system request message index 2664 * @unused: unused pcie_device pointer 2665 * Context: none. 2666 * 2667 * The main routine that builds scatter gather table from a given 2668 * scsi request sent via the .queuecommand main handler. 2669 * 2670 * Return: 0 success, anything else error 2671 */ 2672 static int 2673 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 2674 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) 2675 { 2676 Mpi2SCSIIORequest_t *mpi_request; 2677 dma_addr_t chain_dma; 2678 struct scatterlist *sg_scmd; 2679 void *sg_local, *chain; 2680 u32 chain_offset; 2681 u32 chain_length; 2682 u32 chain_flags; 2683 int sges_left; 2684 u32 sges_in_segment; 2685 u32 sgl_flags; 2686 u32 sgl_flags_last_element; 2687 u32 sgl_flags_end_buffer; 2688 struct chain_tracker *chain_req; 2689 2690 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2691 2692 /* init scatter gather flags */ 2693 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 2694 if (scmd->sc_data_direction == DMA_TO_DEVICE) 2695 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 2696 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 2697 << MPI2_SGE_FLAGS_SHIFT; 2698 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 2699 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 2700 << MPI2_SGE_FLAGS_SHIFT; 2701 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2702 2703 sg_scmd = scsi_sglist(scmd); 2704 sges_left = scsi_dma_map(scmd); 2705 if (sges_left < 0) 2706 return -ENOMEM; 2707 2708 sg_local = &mpi_request->SGL; 2709 sges_in_segment = ioc->max_sges_in_main_message; 2710 if (sges_left <= sges_in_segment) 2711 goto fill_in_last_segment; 2712 2713 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 2714 (sges_in_segment * ioc->sge_size))/4; 2715 2716 /* fill in main message segment when there is a chain following */ 2717 while (sges_in_segment) { 2718 if (sges_in_segment == 1) 2719 ioc->base_add_sg_single(sg_local, 2720 sgl_flags_last_element | sg_dma_len(sg_scmd), 2721 sg_dma_address(sg_scmd)); 2722 else 2723 ioc->base_add_sg_single(sg_local, sgl_flags | 2724 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2725 sg_scmd = sg_next(sg_scmd); 2726 sg_local += ioc->sge_size; 2727 sges_left--; 2728 sges_in_segment--; 2729 } 2730 2731 /* initializing the chain flags and pointers */ 2732 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 2733 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2734 if (!chain_req) 2735 return -1; 2736 chain = chain_req->chain_buffer; 2737 chain_dma = chain_req->chain_buffer_dma; 2738 do { 2739 sges_in_segment = (sges_left <= 2740 ioc->max_sges_in_chain_message) ? sges_left : 2741 ioc->max_sges_in_chain_message; 2742 chain_offset = (sges_left == sges_in_segment) ? 2743 0 : (sges_in_segment * ioc->sge_size)/4; 2744 chain_length = sges_in_segment * ioc->sge_size; 2745 if (chain_offset) { 2746 chain_offset = chain_offset << 2747 MPI2_SGE_CHAIN_OFFSET_SHIFT; 2748 chain_length += ioc->sge_size; 2749 } 2750 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 2751 chain_length, chain_dma); 2752 sg_local = chain; 2753 if (!chain_offset) 2754 goto fill_in_last_segment; 2755 2756 /* fill in chain segments */ 2757 while (sges_in_segment) { 2758 if (sges_in_segment == 1) 2759 ioc->base_add_sg_single(sg_local, 2760 sgl_flags_last_element | 2761 sg_dma_len(sg_scmd), 2762 sg_dma_address(sg_scmd)); 2763 else 2764 ioc->base_add_sg_single(sg_local, sgl_flags | 2765 sg_dma_len(sg_scmd), 2766 sg_dma_address(sg_scmd)); 2767 sg_scmd = sg_next(sg_scmd); 2768 sg_local += ioc->sge_size; 2769 sges_left--; 2770 sges_in_segment--; 2771 } 2772 2773 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2774 if (!chain_req) 2775 return -1; 2776 chain = chain_req->chain_buffer; 2777 chain_dma = chain_req->chain_buffer_dma; 2778 } while (1); 2779 2780 2781 fill_in_last_segment: 2782 2783 /* fill the last segment */ 2784 while (sges_left) { 2785 if (sges_left == 1) 2786 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 2787 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2788 else 2789 ioc->base_add_sg_single(sg_local, sgl_flags | 2790 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2791 sg_scmd = sg_next(sg_scmd); 2792 sg_local += ioc->sge_size; 2793 sges_left--; 2794 } 2795 2796 return 0; 2797 } 2798 2799 /** 2800 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 2801 * @ioc: per adapter object 2802 * @scmd: scsi command 2803 * @smid: system request message index 2804 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be 2805 * constructed on need. 2806 * Context: none. 2807 * 2808 * The main routine that builds scatter gather table from a given 2809 * scsi request sent via the .queuecommand main handler. 2810 * 2811 * Return: 0 success, anything else error 2812 */ 2813 static int 2814 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 2815 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) 2816 { 2817 Mpi25SCSIIORequest_t *mpi_request; 2818 dma_addr_t chain_dma; 2819 struct scatterlist *sg_scmd; 2820 void *sg_local, *chain; 2821 u32 chain_offset; 2822 u32 chain_length; 2823 int sges_left; 2824 u32 sges_in_segment; 2825 u8 simple_sgl_flags; 2826 u8 simple_sgl_flags_last; 2827 u8 chain_sgl_flags; 2828 struct chain_tracker *chain_req; 2829 2830 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2831 2832 /* init scatter gather flags */ 2833 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2834 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2835 simple_sgl_flags_last = simple_sgl_flags | 2836 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2837 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2838 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2839 2840 /* Check if we need to build a native SG list. */ 2841 if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, 2842 smid, scmd, pcie_device) == 0)) { 2843 /* We built a native SG list, just return. */ 2844 return 0; 2845 } 2846 2847 sg_scmd = scsi_sglist(scmd); 2848 sges_left = scsi_dma_map(scmd); 2849 if (sges_left < 0) 2850 return -ENOMEM; 2851 2852 sg_local = &mpi_request->SGL; 2853 sges_in_segment = (ioc->request_sz - 2854 offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 2855 if (sges_left <= sges_in_segment) 2856 goto fill_in_last_segment; 2857 2858 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 2859 (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 2860 2861 /* fill in main message segment when there is a chain following */ 2862 while (sges_in_segment > 1) { 2863 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2864 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2865 sg_scmd = sg_next(sg_scmd); 2866 sg_local += ioc->sge_size_ieee; 2867 sges_left--; 2868 sges_in_segment--; 2869 } 2870 2871 /* initializing the pointers */ 2872 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2873 if (!chain_req) 2874 return -1; 2875 chain = chain_req->chain_buffer; 2876 chain_dma = chain_req->chain_buffer_dma; 2877 do { 2878 sges_in_segment = (sges_left <= 2879 ioc->max_sges_in_chain_message) ? sges_left : 2880 ioc->max_sges_in_chain_message; 2881 chain_offset = (sges_left == sges_in_segment) ? 2882 0 : sges_in_segment; 2883 chain_length = sges_in_segment * ioc->sge_size_ieee; 2884 if (chain_offset) 2885 chain_length += ioc->sge_size_ieee; 2886 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 2887 chain_offset, chain_length, chain_dma); 2888 2889 sg_local = chain; 2890 if (!chain_offset) 2891 goto fill_in_last_segment; 2892 2893 /* fill in chain segments */ 2894 while (sges_in_segment) { 2895 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2896 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2897 sg_scmd = sg_next(sg_scmd); 2898 sg_local += ioc->sge_size_ieee; 2899 sges_left--; 2900 sges_in_segment--; 2901 } 2902 2903 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2904 if (!chain_req) 2905 return -1; 2906 chain = chain_req->chain_buffer; 2907 chain_dma = chain_req->chain_buffer_dma; 2908 } while (1); 2909 2910 2911 fill_in_last_segment: 2912 2913 /* fill the last segment */ 2914 while (sges_left > 0) { 2915 if (sges_left == 1) 2916 _base_add_sg_single_ieee(sg_local, 2917 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 2918 sg_dma_address(sg_scmd)); 2919 else 2920 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2921 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2922 sg_scmd = sg_next(sg_scmd); 2923 sg_local += ioc->sge_size_ieee; 2924 sges_left--; 2925 } 2926 2927 return 0; 2928 } 2929 2930 /** 2931 * _base_build_sg_ieee - build generic sg for IEEE format 2932 * @ioc: per adapter object 2933 * @psge: virtual address for SGE 2934 * @data_out_dma: physical address for WRITES 2935 * @data_out_sz: data xfer size for WRITES 2936 * @data_in_dma: physical address for READS 2937 * @data_in_sz: data xfer size for READS 2938 */ 2939 static void 2940 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 2941 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2942 size_t data_in_sz) 2943 { 2944 u8 sgl_flags; 2945 2946 if (!data_out_sz && !data_in_sz) { 2947 _base_build_zero_len_sge_ieee(ioc, psge); 2948 return; 2949 } 2950 2951 if (data_out_sz && data_in_sz) { 2952 /* WRITE sgel first */ 2953 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2954 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2955 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2956 data_out_dma); 2957 2958 /* incr sgel */ 2959 psge += ioc->sge_size_ieee; 2960 2961 /* READ sgel last */ 2962 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2963 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2964 data_in_dma); 2965 } else if (data_out_sz) /* WRITE */ { 2966 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2967 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2968 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2969 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2970 data_out_dma); 2971 } else if (data_in_sz) /* READ */ { 2972 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2973 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2974 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2975 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2976 data_in_dma); 2977 } 2978 } 2979 2980 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 2981 2982 /** 2983 * _base_config_dma_addressing - set dma addressing 2984 * @ioc: per adapter object 2985 * @pdev: PCI device struct 2986 * 2987 * Return: 0 for success, non-zero for failure. 2988 */ 2989 static int 2990 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 2991 { 2992 struct sysinfo s; 2993 2994 if (ioc->is_mcpu_endpoint || 2995 sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma || 2996 dma_get_required_mask(&pdev->dev) <= 32) 2997 ioc->dma_mask = 32; 2998 /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ 2999 else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) 3000 ioc->dma_mask = 63; 3001 else 3002 ioc->dma_mask = 64; 3003 3004 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) || 3005 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask))) 3006 return -ENODEV; 3007 3008 if (ioc->dma_mask > 32) { 3009 ioc->base_add_sg_single = &_base_add_sg_single_64; 3010 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 3011 } else { 3012 ioc->base_add_sg_single = &_base_add_sg_single_32; 3013 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 3014 } 3015 3016 si_meminfo(&s); 3017 ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 3018 ioc->dma_mask, convert_to_kb(s.totalram)); 3019 3020 return 0; 3021 } 3022 3023 /** 3024 * _base_check_enable_msix - checks MSIX capabable. 3025 * @ioc: per adapter object 3026 * 3027 * Check to see if card is capable of MSIX, and set number 3028 * of available msix vectors 3029 */ 3030 static int 3031 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 3032 { 3033 int base; 3034 u16 message_control; 3035 3036 /* Check whether controller SAS2008 B0 controller, 3037 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 3038 */ 3039 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 3040 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 3041 return -EINVAL; 3042 } 3043 3044 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 3045 if (!base) { 3046 dfailprintk(ioc, ioc_info(ioc, "msix not supported\n")); 3047 return -EINVAL; 3048 } 3049 3050 /* get msix vector count */ 3051 /* NUMA_IO not supported for older controllers */ 3052 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 3053 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 3054 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 3055 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 3056 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 3057 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 3058 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 3059 ioc->msix_vector_count = 1; 3060 else { 3061 pci_read_config_word(ioc->pdev, base + 2, &message_control); 3062 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 3063 } 3064 dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n", 3065 ioc->msix_vector_count)); 3066 return 0; 3067 } 3068 3069 /** 3070 * mpt3sas_base_free_irq - free irq 3071 * @ioc: per adapter object 3072 * 3073 * Freeing respective reply_queue from the list. 3074 */ 3075 void 3076 mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc) 3077 { 3078 unsigned int irq; 3079 struct adapter_reply_queue *reply_q, *next; 3080 3081 if (list_empty(&ioc->reply_queue_list)) 3082 return; 3083 3084 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 3085 list_del(&reply_q->list); 3086 if (reply_q->is_iouring_poll_q) { 3087 kfree(reply_q); 3088 continue; 3089 } 3090 3091 if (ioc->smp_affinity_enable) { 3092 irq = pci_irq_vector(ioc->pdev, reply_q->msix_index); 3093 irq_update_affinity_hint(irq, NULL); 3094 } 3095 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), 3096 reply_q); 3097 kfree(reply_q); 3098 } 3099 } 3100 3101 /** 3102 * _base_request_irq - request irq 3103 * @ioc: per adapter object 3104 * @index: msix index into vector table 3105 * 3106 * Inserting respective reply_queue into the list. 3107 */ 3108 static int 3109 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) 3110 { 3111 struct pci_dev *pdev = ioc->pdev; 3112 struct adapter_reply_queue *reply_q; 3113 int r, qid; 3114 3115 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 3116 if (!reply_q) { 3117 ioc_err(ioc, "unable to allocate memory %zu!\n", 3118 sizeof(struct adapter_reply_queue)); 3119 return -ENOMEM; 3120 } 3121 reply_q->ioc = ioc; 3122 reply_q->msix_index = index; 3123 3124 atomic_set(&reply_q->busy, 0); 3125 3126 if (index >= ioc->iopoll_q_start_index) { 3127 qid = index - ioc->iopoll_q_start_index; 3128 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d", 3129 ioc->driver_name, ioc->id, qid); 3130 reply_q->is_iouring_poll_q = 1; 3131 ioc->io_uring_poll_queues[qid].reply_q = reply_q; 3132 goto out; 3133 } 3134 3135 3136 if (ioc->msix_enable) 3137 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 3138 ioc->driver_name, ioc->id, index); 3139 else 3140 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 3141 ioc->driver_name, ioc->id); 3142 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, 3143 IRQF_SHARED, reply_q->name, reply_q); 3144 if (r) { 3145 pr_err("%s: unable to allocate interrupt %d!\n", 3146 reply_q->name, pci_irq_vector(pdev, index)); 3147 kfree(reply_q); 3148 return -EBUSY; 3149 } 3150 out: 3151 INIT_LIST_HEAD(&reply_q->list); 3152 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 3153 return 0; 3154 } 3155 3156 /** 3157 * _base_assign_reply_queues - assigning msix index for each cpu 3158 * @ioc: per adapter object 3159 * 3160 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 3161 */ 3162 static void 3163 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 3164 { 3165 unsigned int cpu, nr_cpus, nr_msix, index = 0, irq; 3166 struct adapter_reply_queue *reply_q; 3167 int iopoll_q_count = ioc->reply_queue_count - 3168 ioc->iopoll_q_start_index; 3169 const struct cpumask *mask; 3170 3171 if (!_base_is_controller_msix_enabled(ioc)) 3172 return; 3173 3174 if (ioc->msix_load_balance) 3175 return; 3176 3177 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 3178 3179 nr_cpus = num_online_cpus(); 3180 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 3181 ioc->facts.MaxMSIxVectors); 3182 if (!nr_msix) 3183 return; 3184 3185 if (ioc->smp_affinity_enable) { 3186 3187 /* 3188 * set irq affinity to local numa node for those irqs 3189 * corresponding to high iops queues. 3190 */ 3191 if (ioc->high_iops_queues) { 3192 mask = cpumask_of_node(dev_to_node(&ioc->pdev->dev)); 3193 for (index = 0; index < ioc->high_iops_queues; 3194 index++) { 3195 irq = pci_irq_vector(ioc->pdev, index); 3196 irq_set_affinity_and_hint(irq, mask); 3197 } 3198 } 3199 3200 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3201 const cpumask_t *mask; 3202 3203 if (reply_q->msix_index < ioc->high_iops_queues || 3204 reply_q->msix_index >= ioc->iopoll_q_start_index) 3205 continue; 3206 3207 mask = pci_irq_get_affinity(ioc->pdev, 3208 reply_q->msix_index); 3209 if (!mask) { 3210 ioc_warn(ioc, "no affinity for msi %x\n", 3211 reply_q->msix_index); 3212 goto fall_back; 3213 } 3214 3215 for_each_cpu_and(cpu, mask, cpu_online_mask) { 3216 if (cpu >= ioc->cpu_msix_table_sz) 3217 break; 3218 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 3219 } 3220 } 3221 return; 3222 } 3223 3224 fall_back: 3225 cpu = cpumask_first(cpu_online_mask); 3226 nr_msix -= (ioc->high_iops_queues - iopoll_q_count); 3227 index = 0; 3228 3229 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3230 unsigned int i, group = nr_cpus / nr_msix; 3231 3232 if (reply_q->msix_index < ioc->high_iops_queues || 3233 reply_q->msix_index >= ioc->iopoll_q_start_index) 3234 continue; 3235 3236 if (cpu >= nr_cpus) 3237 break; 3238 3239 if (index < nr_cpus % nr_msix) 3240 group++; 3241 3242 for (i = 0 ; i < group ; i++) { 3243 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 3244 cpu = cpumask_next(cpu, cpu_online_mask); 3245 } 3246 index++; 3247 } 3248 } 3249 3250 /** 3251 * _base_check_and_enable_high_iops_queues - enable high iops mode 3252 * @ioc: per adapter object 3253 * @hba_msix_vector_count: msix vectors supported by HBA 3254 * 3255 * Enable high iops queues only if 3256 * - HBA is a SEA/AERO controller and 3257 * - MSI-Xs vector supported by the HBA is 128 and 3258 * - total CPU count in the system >=16 and 3259 * - loaded driver with default max_msix_vectors module parameter and 3260 * - system booted in non kdump mode 3261 * 3262 * Return: nothing. 3263 */ 3264 static void 3265 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc, 3266 int hba_msix_vector_count) 3267 { 3268 u16 lnksta, speed; 3269 3270 /* 3271 * Disable high iops queues if io uring poll queues are enabled. 3272 */ 3273 if (perf_mode == MPT_PERF_MODE_IOPS || 3274 perf_mode == MPT_PERF_MODE_LATENCY || 3275 ioc->io_uring_poll_queues) { 3276 ioc->high_iops_queues = 0; 3277 return; 3278 } 3279 3280 if (perf_mode == MPT_PERF_MODE_DEFAULT) { 3281 3282 pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta); 3283 speed = lnksta & PCI_EXP_LNKSTA_CLS; 3284 3285 if (speed < 0x4) { 3286 ioc->high_iops_queues = 0; 3287 return; 3288 } 3289 } 3290 3291 if (!reset_devices && ioc->is_aero_ioc && 3292 hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES && 3293 num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES && 3294 max_msix_vectors == -1) 3295 ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES; 3296 else 3297 ioc->high_iops_queues = 0; 3298 } 3299 3300 /** 3301 * mpt3sas_base_disable_msix - disables msix 3302 * @ioc: per adapter object 3303 * 3304 */ 3305 void 3306 mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 3307 { 3308 if (!ioc->msix_enable) 3309 return; 3310 pci_free_irq_vectors(ioc->pdev); 3311 ioc->msix_enable = 0; 3312 kfree(ioc->io_uring_poll_queues); 3313 } 3314 3315 /** 3316 * _base_alloc_irq_vectors - allocate msix vectors 3317 * @ioc: per adapter object 3318 * 3319 */ 3320 static int 3321 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc) 3322 { 3323 int i, irq_flags = PCI_IRQ_MSIX; 3324 struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues }; 3325 struct irq_affinity *descp = &desc; 3326 /* 3327 * Don't allocate msix vectors for poll_queues. 3328 * msix_vectors is always within a range of FW supported reply queue. 3329 */ 3330 int nr_msix_vectors = ioc->iopoll_q_start_index; 3331 3332 3333 if (ioc->smp_affinity_enable) 3334 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 3335 else 3336 descp = NULL; 3337 3338 ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues, 3339 ioc->reply_queue_count, nr_msix_vectors); 3340 3341 i = pci_alloc_irq_vectors_affinity(ioc->pdev, 3342 ioc->high_iops_queues, 3343 nr_msix_vectors, irq_flags, descp); 3344 3345 return i; 3346 } 3347 3348 /** 3349 * _base_enable_msix - enables msix, failback to io_apic 3350 * @ioc: per adapter object 3351 * 3352 */ 3353 static int 3354 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 3355 { 3356 int r; 3357 int i, local_max_msix_vectors; 3358 u8 try_msix = 0; 3359 int iopoll_q_count = 0; 3360 3361 ioc->msix_load_balance = false; 3362 3363 if (msix_disable == -1 || msix_disable == 0) 3364 try_msix = 1; 3365 3366 if (!try_msix) 3367 goto try_ioapic; 3368 3369 if (_base_check_enable_msix(ioc) != 0) 3370 goto try_ioapic; 3371 3372 ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count); 3373 pr_info("\t no of cores: %d, max_msix_vectors: %d\n", 3374 ioc->cpu_count, max_msix_vectors); 3375 3376 ioc->reply_queue_count = 3377 min_t(int, ioc->cpu_count, ioc->msix_vector_count); 3378 3379 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 3380 local_max_msix_vectors = (reset_devices) ? 1 : 8; 3381 else 3382 local_max_msix_vectors = max_msix_vectors; 3383 3384 if (local_max_msix_vectors == 0) 3385 goto try_ioapic; 3386 3387 /* 3388 * Enable msix_load_balance only if combined reply queue mode is 3389 * disabled on SAS3 & above generation HBA devices. 3390 */ 3391 if (!ioc->combined_reply_queue && 3392 ioc->hba_mpi_version_belonged != MPI2_VERSION) { 3393 ioc_info(ioc, 3394 "combined ReplyQueue is off, Enabling msix load balance\n"); 3395 ioc->msix_load_balance = true; 3396 } 3397 3398 /* 3399 * smp affinity setting is not need when msix load balance 3400 * is enabled. 3401 */ 3402 if (ioc->msix_load_balance) 3403 ioc->smp_affinity_enable = 0; 3404 3405 if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1) 3406 ioc->shost->host_tagset = 0; 3407 3408 /* 3409 * Enable io uring poll queues only if host_tagset is enabled. 3410 */ 3411 if (ioc->shost->host_tagset) 3412 iopoll_q_count = poll_queues; 3413 3414 if (iopoll_q_count) { 3415 ioc->io_uring_poll_queues = kcalloc(iopoll_q_count, 3416 sizeof(struct io_uring_poll_queue), GFP_KERNEL); 3417 if (!ioc->io_uring_poll_queues) 3418 iopoll_q_count = 0; 3419 } 3420 3421 if (ioc->is_aero_ioc) 3422 _base_check_and_enable_high_iops_queues(ioc, 3423 ioc->msix_vector_count); 3424 3425 /* 3426 * Add high iops queues count to reply queue count if high iops queues 3427 * are enabled. 3428 */ 3429 ioc->reply_queue_count = min_t(int, 3430 ioc->reply_queue_count + ioc->high_iops_queues, 3431 ioc->msix_vector_count); 3432 3433 /* 3434 * Adjust the reply queue count incase reply queue count 3435 * exceeds the user provided MSIx vectors count. 3436 */ 3437 if (local_max_msix_vectors > 0) 3438 ioc->reply_queue_count = min_t(int, local_max_msix_vectors, 3439 ioc->reply_queue_count); 3440 /* 3441 * Add io uring poll queues count to reply queues count 3442 * if io uring is enabled in driver. 3443 */ 3444 if (iopoll_q_count) { 3445 if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS)) 3446 iopoll_q_count = 0; 3447 ioc->reply_queue_count = min_t(int, 3448 ioc->reply_queue_count + iopoll_q_count, 3449 ioc->msix_vector_count); 3450 } 3451 3452 /* 3453 * Starting index of io uring poll queues in reply queue list. 3454 */ 3455 ioc->iopoll_q_start_index = 3456 ioc->reply_queue_count - iopoll_q_count; 3457 3458 r = _base_alloc_irq_vectors(ioc); 3459 if (r < 0) { 3460 ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r); 3461 goto try_ioapic; 3462 } 3463 3464 /* 3465 * Adjust the reply queue count if the allocated 3466 * MSIx vectors is less then the requested number 3467 * of MSIx vectors. 3468 */ 3469 if (r < ioc->iopoll_q_start_index) { 3470 ioc->reply_queue_count = r + iopoll_q_count; 3471 ioc->iopoll_q_start_index = 3472 ioc->reply_queue_count - iopoll_q_count; 3473 } 3474 3475 ioc->msix_enable = 1; 3476 for (i = 0; i < ioc->reply_queue_count; i++) { 3477 r = _base_request_irq(ioc, i); 3478 if (r) { 3479 mpt3sas_base_free_irq(ioc); 3480 mpt3sas_base_disable_msix(ioc); 3481 goto try_ioapic; 3482 } 3483 } 3484 3485 ioc_info(ioc, "High IOPs queues : %s\n", 3486 ioc->high_iops_queues ? "enabled" : "disabled"); 3487 3488 return 0; 3489 3490 /* failback to io_apic interrupt routing */ 3491 try_ioapic: 3492 ioc->high_iops_queues = 0; 3493 ioc_info(ioc, "High IOPs queues : disabled\n"); 3494 ioc->reply_queue_count = 1; 3495 ioc->iopoll_q_start_index = ioc->reply_queue_count - 0; 3496 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); 3497 if (r < 0) { 3498 dfailprintk(ioc, 3499 ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", 3500 r)); 3501 } else 3502 r = _base_request_irq(ioc, 0); 3503 3504 return r; 3505 } 3506 3507 /** 3508 * mpt3sas_base_unmap_resources - free controller resources 3509 * @ioc: per adapter object 3510 */ 3511 static void 3512 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 3513 { 3514 struct pci_dev *pdev = ioc->pdev; 3515 3516 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 3517 3518 mpt3sas_base_free_irq(ioc); 3519 mpt3sas_base_disable_msix(ioc); 3520 3521 kfree(ioc->replyPostRegisterIndex); 3522 ioc->replyPostRegisterIndex = NULL; 3523 3524 3525 if (ioc->chip_phys) { 3526 iounmap(ioc->chip); 3527 ioc->chip_phys = 0; 3528 } 3529 3530 if (pci_is_enabled(pdev)) { 3531 pci_release_selected_regions(ioc->pdev, ioc->bars); 3532 pci_disable_pcie_error_reporting(pdev); 3533 pci_disable_device(pdev); 3534 } 3535 } 3536 3537 static int 3538 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); 3539 3540 /** 3541 * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state 3542 * and if it is in fault state then issue diag reset. 3543 * @ioc: per adapter object 3544 * 3545 * Return: 0 for success, non-zero for failure. 3546 */ 3547 int 3548 mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc) 3549 { 3550 u32 ioc_state; 3551 int rc = -EFAULT; 3552 3553 dinitprintk(ioc, pr_info("%s\n", __func__)); 3554 if (ioc->pci_error_recovery) 3555 return 0; 3556 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 3557 dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state)); 3558 3559 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 3560 mpt3sas_print_fault_code(ioc, ioc_state & 3561 MPI2_DOORBELL_DATA_MASK); 3562 mpt3sas_base_mask_interrupts(ioc); 3563 rc = _base_diag_reset(ioc); 3564 } else if ((ioc_state & MPI2_IOC_STATE_MASK) == 3565 MPI2_IOC_STATE_COREDUMP) { 3566 mpt3sas_print_coredump_info(ioc, ioc_state & 3567 MPI2_DOORBELL_DATA_MASK); 3568 mpt3sas_base_wait_for_coredump_completion(ioc, __func__); 3569 mpt3sas_base_mask_interrupts(ioc); 3570 rc = _base_diag_reset(ioc); 3571 } 3572 3573 return rc; 3574 } 3575 3576 /** 3577 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 3578 * @ioc: per adapter object 3579 * 3580 * Return: 0 for success, non-zero for failure. 3581 */ 3582 int 3583 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 3584 { 3585 struct pci_dev *pdev = ioc->pdev; 3586 u32 memap_sz; 3587 u32 pio_sz; 3588 int i, r = 0, rc; 3589 u64 pio_chip = 0; 3590 phys_addr_t chip_phys = 0; 3591 struct adapter_reply_queue *reply_q; 3592 int iopoll_q_count = 0; 3593 3594 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 3595 3596 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3597 if (pci_enable_device_mem(pdev)) { 3598 ioc_warn(ioc, "pci_enable_device_mem: failed\n"); 3599 ioc->bars = 0; 3600 return -ENODEV; 3601 } 3602 3603 3604 if (pci_request_selected_regions(pdev, ioc->bars, 3605 ioc->driver_name)) { 3606 ioc_warn(ioc, "pci_request_selected_regions: failed\n"); 3607 ioc->bars = 0; 3608 r = -ENODEV; 3609 goto out_fail; 3610 } 3611 3612 /* AER (Advanced Error Reporting) hooks */ 3613 pci_enable_pcie_error_reporting(pdev); 3614 3615 pci_set_master(pdev); 3616 3617 3618 if (_base_config_dma_addressing(ioc, pdev) != 0) { 3619 ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev)); 3620 r = -ENODEV; 3621 goto out_fail; 3622 } 3623 3624 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 3625 (!memap_sz || !pio_sz); i++) { 3626 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 3627 if (pio_sz) 3628 continue; 3629 pio_chip = (u64)pci_resource_start(pdev, i); 3630 pio_sz = pci_resource_len(pdev, i); 3631 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3632 if (memap_sz) 3633 continue; 3634 ioc->chip_phys = pci_resource_start(pdev, i); 3635 chip_phys = ioc->chip_phys; 3636 memap_sz = pci_resource_len(pdev, i); 3637 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 3638 } 3639 } 3640 3641 if (ioc->chip == NULL) { 3642 ioc_err(ioc, 3643 "unable to map adapter memory! or resource not found\n"); 3644 r = -EINVAL; 3645 goto out_fail; 3646 } 3647 3648 mpt3sas_base_mask_interrupts(ioc); 3649 3650 r = _base_get_ioc_facts(ioc); 3651 if (r) { 3652 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 3653 if (rc || (_base_get_ioc_facts(ioc))) 3654 goto out_fail; 3655 } 3656 3657 if (!ioc->rdpq_array_enable_assigned) { 3658 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 3659 ioc->rdpq_array_enable_assigned = 1; 3660 } 3661 3662 r = _base_enable_msix(ioc); 3663 if (r) 3664 goto out_fail; 3665 3666 iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index; 3667 for (i = 0; i < iopoll_q_count; i++) { 3668 atomic_set(&ioc->io_uring_poll_queues[i].busy, 0); 3669 atomic_set(&ioc->io_uring_poll_queues[i].pause, 0); 3670 } 3671 3672 if (!ioc->is_driver_loading) 3673 _base_init_irqpolls(ioc); 3674 /* Use the Combined reply queue feature only for SAS3 C0 & higher 3675 * revision HBAs and also only when reply queue count is greater than 8 3676 */ 3677 if (ioc->combined_reply_queue) { 3678 /* Determine the Supplemental Reply Post Host Index Registers 3679 * Addresse. Supplemental Reply Post Host Index Registers 3680 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 3681 * each register is at offset bytes of 3682 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 3683 */ 3684 ioc->replyPostRegisterIndex = kcalloc( 3685 ioc->combined_reply_index_count, 3686 sizeof(resource_size_t *), GFP_KERNEL); 3687 if (!ioc->replyPostRegisterIndex) { 3688 ioc_err(ioc, 3689 "allocation for replyPostRegisterIndex failed!\n"); 3690 r = -ENOMEM; 3691 goto out_fail; 3692 } 3693 3694 for (i = 0; i < ioc->combined_reply_index_count; i++) { 3695 ioc->replyPostRegisterIndex[i] = (resource_size_t *) 3696 ((u8 __force *)&ioc->chip->Doorbell + 3697 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 3698 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 3699 } 3700 } 3701 3702 if (ioc->is_warpdrive) { 3703 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 3704 &ioc->chip->ReplyPostHostIndex; 3705 3706 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 3707 ioc->reply_post_host_index[i] = 3708 (resource_size_t __iomem *) 3709 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 3710 * 4))); 3711 } 3712 3713 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 3714 if (reply_q->msix_index >= ioc->iopoll_q_start_index) { 3715 pr_info("%s: enabled: index: %d\n", 3716 reply_q->name, reply_q->msix_index); 3717 continue; 3718 } 3719 3720 pr_info("%s: %s enabled: IRQ %d\n", 3721 reply_q->name, 3722 ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC", 3723 pci_irq_vector(ioc->pdev, reply_q->msix_index)); 3724 } 3725 3726 ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n", 3727 &chip_phys, ioc->chip, memap_sz); 3728 ioc_info(ioc, "ioport(0x%016llx), size(%d)\n", 3729 (unsigned long long)pio_chip, pio_sz); 3730 3731 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 3732 pci_save_state(pdev); 3733 return 0; 3734 3735 out_fail: 3736 mpt3sas_base_unmap_resources(ioc); 3737 return r; 3738 } 3739 3740 /** 3741 * mpt3sas_base_get_msg_frame - obtain request mf pointer 3742 * @ioc: per adapter object 3743 * @smid: system request message index(smid zero is invalid) 3744 * 3745 * Return: virt pointer to message frame. 3746 */ 3747 void * 3748 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3749 { 3750 return (void *)(ioc->request + (smid * ioc->request_sz)); 3751 } 3752 3753 /** 3754 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 3755 * @ioc: per adapter object 3756 * @smid: system request message index 3757 * 3758 * Return: virt pointer to sense buffer. 3759 */ 3760 void * 3761 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3762 { 3763 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 3764 } 3765 3766 /** 3767 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 3768 * @ioc: per adapter object 3769 * @smid: system request message index 3770 * 3771 * Return: phys pointer to the low 32bit address of the sense buffer. 3772 */ 3773 __le32 3774 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3775 { 3776 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 3777 SCSI_SENSE_BUFFERSIZE)); 3778 } 3779 3780 /** 3781 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr 3782 * @ioc: per adapter object 3783 * @smid: system request message index 3784 * 3785 * Return: virt pointer to a PCIe SGL. 3786 */ 3787 void * 3788 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3789 { 3790 return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl); 3791 } 3792 3793 /** 3794 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr 3795 * @ioc: per adapter object 3796 * @smid: system request message index 3797 * 3798 * Return: phys pointer to the address of the PCIe buffer. 3799 */ 3800 dma_addr_t 3801 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3802 { 3803 return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma; 3804 } 3805 3806 /** 3807 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 3808 * @ioc: per adapter object 3809 * @phys_addr: lower 32 physical addr of the reply 3810 * 3811 * Converts 32bit lower physical addr into a virt address. 3812 */ 3813 void * 3814 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 3815 { 3816 if (!phys_addr) 3817 return NULL; 3818 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 3819 } 3820 3821 /** 3822 * _base_get_msix_index - get the msix index 3823 * @ioc: per adapter object 3824 * @scmd: scsi_cmnd object 3825 * 3826 * Return: msix index of general reply queues, 3827 * i.e. reply queue on which IO request's reply 3828 * should be posted by the HBA firmware. 3829 */ 3830 static inline u8 3831 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc, 3832 struct scsi_cmnd *scmd) 3833 { 3834 /* Enables reply_queue load balancing */ 3835 if (ioc->msix_load_balance) 3836 return ioc->reply_queue_count ? 3837 base_mod64(atomic64_add_return(1, 3838 &ioc->total_io_cnt), ioc->reply_queue_count) : 0; 3839 3840 if (scmd && ioc->shost->nr_hw_queues > 1) { 3841 u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); 3842 3843 return blk_mq_unique_tag_to_hwq(tag) + 3844 ioc->high_iops_queues; 3845 } 3846 3847 return ioc->cpu_msix_table[raw_smp_processor_id()]; 3848 } 3849 3850 /** 3851 * _base_get_high_iops_msix_index - get the msix index of 3852 * high iops queues 3853 * @ioc: per adapter object 3854 * @scmd: scsi_cmnd object 3855 * 3856 * Return: msix index of high iops reply queues. 3857 * i.e. high iops reply queue on which IO request's 3858 * reply should be posted by the HBA firmware. 3859 */ 3860 static inline u8 3861 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc, 3862 struct scsi_cmnd *scmd) 3863 { 3864 /** 3865 * Round robin the IO interrupts among the high iops 3866 * reply queues in terms of batch count 16 when outstanding 3867 * IOs on the target device is >=8. 3868 */ 3869 3870 if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH) 3871 return base_mod64(( 3872 atomic64_add_return(1, &ioc->high_iops_outstanding) / 3873 MPT3SAS_HIGH_IOPS_BATCH_COUNT), 3874 MPT3SAS_HIGH_IOPS_REPLY_QUEUES); 3875 3876 return _base_get_msix_index(ioc, scmd); 3877 } 3878 3879 /** 3880 * mpt3sas_base_get_smid - obtain a free smid from internal queue 3881 * @ioc: per adapter object 3882 * @cb_idx: callback index 3883 * 3884 * Return: smid (zero is invalid) 3885 */ 3886 u16 3887 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3888 { 3889 unsigned long flags; 3890 struct request_tracker *request; 3891 u16 smid; 3892 3893 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3894 if (list_empty(&ioc->internal_free_list)) { 3895 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3896 ioc_err(ioc, "%s: smid not available\n", __func__); 3897 return 0; 3898 } 3899 3900 request = list_entry(ioc->internal_free_list.next, 3901 struct request_tracker, tracker_list); 3902 request->cb_idx = cb_idx; 3903 smid = request->smid; 3904 list_del(&request->tracker_list); 3905 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3906 return smid; 3907 } 3908 3909 /** 3910 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 3911 * @ioc: per adapter object 3912 * @cb_idx: callback index 3913 * @scmd: pointer to scsi command object 3914 * 3915 * Return: smid (zero is invalid) 3916 */ 3917 u16 3918 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 3919 struct scsi_cmnd *scmd) 3920 { 3921 struct scsiio_tracker *request = scsi_cmd_priv(scmd); 3922 u16 smid; 3923 u32 tag, unique_tag; 3924 3925 unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); 3926 tag = blk_mq_unique_tag_to_tag(unique_tag); 3927 3928 /* 3929 * Store hw queue number corresponding to the tag. 3930 * This hw queue number is used later to determine 3931 * the unique_tag using the logic below. This unique_tag 3932 * is used to retrieve the scmd pointer corresponding 3933 * to tag using scsi_host_find_tag() API. 3934 * 3935 * tag = smid - 1; 3936 * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag; 3937 */ 3938 ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag); 3939 3940 smid = tag + 1; 3941 request->cb_idx = cb_idx; 3942 request->smid = smid; 3943 request->scmd = scmd; 3944 INIT_LIST_HEAD(&request->chain_list); 3945 return smid; 3946 } 3947 3948 /** 3949 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 3950 * @ioc: per adapter object 3951 * @cb_idx: callback index 3952 * 3953 * Return: smid (zero is invalid) 3954 */ 3955 u16 3956 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3957 { 3958 unsigned long flags; 3959 struct request_tracker *request; 3960 u16 smid; 3961 3962 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3963 if (list_empty(&ioc->hpr_free_list)) { 3964 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3965 return 0; 3966 } 3967 3968 request = list_entry(ioc->hpr_free_list.next, 3969 struct request_tracker, tracker_list); 3970 request->cb_idx = cb_idx; 3971 smid = request->smid; 3972 list_del(&request->tracker_list); 3973 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3974 return smid; 3975 } 3976 3977 static void 3978 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc) 3979 { 3980 /* 3981 * See _wait_for_commands_to_complete() call with regards to this code. 3982 */ 3983 if (ioc->shost_recovery && ioc->pending_io_count) { 3984 ioc->pending_io_count = scsi_host_busy(ioc->shost); 3985 if (ioc->pending_io_count == 0) 3986 wake_up(&ioc->reset_wq); 3987 } 3988 } 3989 3990 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, 3991 struct scsiio_tracker *st) 3992 { 3993 if (WARN_ON(st->smid == 0)) 3994 return; 3995 st->cb_idx = 0xFF; 3996 st->direct_io = 0; 3997 st->scmd = NULL; 3998 atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0); 3999 st->smid = 0; 4000 } 4001 4002 /** 4003 * mpt3sas_base_free_smid - put smid back on free_list 4004 * @ioc: per adapter object 4005 * @smid: system request message index 4006 */ 4007 void 4008 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4009 { 4010 unsigned long flags; 4011 int i; 4012 4013 if (smid < ioc->hi_priority_smid) { 4014 struct scsiio_tracker *st; 4015 void *request; 4016 4017 st = _get_st_from_smid(ioc, smid); 4018 if (!st) { 4019 _base_recovery_check(ioc); 4020 return; 4021 } 4022 4023 /* Clear MPI request frame */ 4024 request = mpt3sas_base_get_msg_frame(ioc, smid); 4025 memset(request, 0, ioc->request_sz); 4026 4027 mpt3sas_base_clear_st(ioc, st); 4028 _base_recovery_check(ioc); 4029 ioc->io_queue_num[smid - 1] = 0; 4030 return; 4031 } 4032 4033 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 4034 if (smid < ioc->internal_smid) { 4035 /* hi-priority */ 4036 i = smid - ioc->hi_priority_smid; 4037 ioc->hpr_lookup[i].cb_idx = 0xFF; 4038 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 4039 } else if (smid <= ioc->hba_queue_depth) { 4040 /* internal queue */ 4041 i = smid - ioc->internal_smid; 4042 ioc->internal_lookup[i].cb_idx = 0xFF; 4043 list_add(&ioc->internal_lookup[i].tracker_list, 4044 &ioc->internal_free_list); 4045 } 4046 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 4047 } 4048 4049 /** 4050 * _base_mpi_ep_writeq - 32 bit write to MMIO 4051 * @b: data payload 4052 * @addr: address in MMIO space 4053 * @writeq_lock: spin lock 4054 * 4055 * This special handling for MPI EP to take care of 32 bit 4056 * environment where its not quarenteed to send the entire word 4057 * in one transfer. 4058 */ 4059 static inline void 4060 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr, 4061 spinlock_t *writeq_lock) 4062 { 4063 unsigned long flags; 4064 4065 spin_lock_irqsave(writeq_lock, flags); 4066 __raw_writel((u32)(b), addr); 4067 __raw_writel((u32)(b >> 32), (addr + 4)); 4068 spin_unlock_irqrestore(writeq_lock, flags); 4069 } 4070 4071 /** 4072 * _base_writeq - 64 bit write to MMIO 4073 * @b: data payload 4074 * @addr: address in MMIO space 4075 * @writeq_lock: spin lock 4076 * 4077 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 4078 * care of 32 bit environment where its not quarenteed to send the entire word 4079 * in one transfer. 4080 */ 4081 #if defined(writeq) && defined(CONFIG_64BIT) 4082 static inline void 4083 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 4084 { 4085 wmb(); 4086 __raw_writeq(b, addr); 4087 barrier(); 4088 } 4089 #else 4090 static inline void 4091 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 4092 { 4093 _base_mpi_ep_writeq(b, addr, writeq_lock); 4094 } 4095 #endif 4096 4097 /** 4098 * _base_set_and_get_msix_index - get the msix index and assign to msix_io 4099 * variable of scsi tracker 4100 * @ioc: per adapter object 4101 * @smid: system request message index 4102 * 4103 * Return: msix index. 4104 */ 4105 static u8 4106 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4107 { 4108 struct scsiio_tracker *st = NULL; 4109 4110 if (smid < ioc->hi_priority_smid) 4111 st = _get_st_from_smid(ioc, smid); 4112 4113 if (st == NULL) 4114 return _base_get_msix_index(ioc, NULL); 4115 4116 st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd); 4117 return st->msix_io; 4118 } 4119 4120 /** 4121 * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware 4122 * @ioc: per adapter object 4123 * @smid: system request message index 4124 * @handle: device handle 4125 */ 4126 static void 4127 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, 4128 u16 smid, u16 handle) 4129 { 4130 Mpi2RequestDescriptorUnion_t descriptor; 4131 u64 *request = (u64 *)&descriptor; 4132 void *mpi_req_iomem; 4133 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4134 4135 _clone_sg_entries(ioc, (void *) mfp, smid); 4136 mpi_req_iomem = (void __force *)ioc->chip + 4137 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 4138 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4139 ioc->request_sz); 4140 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4141 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4142 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4143 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4144 descriptor.SCSIIO.LMID = 0; 4145 _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4146 &ioc->scsi_lookup_lock); 4147 } 4148 4149 /** 4150 * _base_put_smid_scsi_io - send SCSI_IO request to firmware 4151 * @ioc: per adapter object 4152 * @smid: system request message index 4153 * @handle: device handle 4154 */ 4155 static void 4156 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 4157 { 4158 Mpi2RequestDescriptorUnion_t descriptor; 4159 u64 *request = (u64 *)&descriptor; 4160 4161 4162 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4163 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4164 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4165 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4166 descriptor.SCSIIO.LMID = 0; 4167 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4168 &ioc->scsi_lookup_lock); 4169 } 4170 4171 /** 4172 * _base_put_smid_fast_path - send fast path request to firmware 4173 * @ioc: per adapter object 4174 * @smid: system request message index 4175 * @handle: device handle 4176 */ 4177 static void 4178 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4179 u16 handle) 4180 { 4181 Mpi2RequestDescriptorUnion_t descriptor; 4182 u64 *request = (u64 *)&descriptor; 4183 4184 descriptor.SCSIIO.RequestFlags = 4185 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 4186 descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4187 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 4188 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 4189 descriptor.SCSIIO.LMID = 0; 4190 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4191 &ioc->scsi_lookup_lock); 4192 } 4193 4194 /** 4195 * _base_put_smid_hi_priority - send Task Management request to firmware 4196 * @ioc: per adapter object 4197 * @smid: system request message index 4198 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 4199 */ 4200 static void 4201 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4202 u16 msix_task) 4203 { 4204 Mpi2RequestDescriptorUnion_t descriptor; 4205 void *mpi_req_iomem; 4206 u64 *request; 4207 4208 if (ioc->is_mcpu_endpoint) { 4209 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4210 4211 /* TBD 256 is offset within sys register. */ 4212 mpi_req_iomem = (void __force *)ioc->chip 4213 + MPI_FRAME_START_OFFSET 4214 + (smid * ioc->request_sz); 4215 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4216 ioc->request_sz); 4217 } 4218 4219 request = (u64 *)&descriptor; 4220 4221 descriptor.HighPriority.RequestFlags = 4222 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 4223 descriptor.HighPriority.MSIxIndex = msix_task; 4224 descriptor.HighPriority.SMID = cpu_to_le16(smid); 4225 descriptor.HighPriority.LMID = 0; 4226 descriptor.HighPriority.Reserved1 = 0; 4227 if (ioc->is_mcpu_endpoint) 4228 _base_mpi_ep_writeq(*request, 4229 &ioc->chip->RequestDescriptorPostLow, 4230 &ioc->scsi_lookup_lock); 4231 else 4232 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4233 &ioc->scsi_lookup_lock); 4234 } 4235 4236 /** 4237 * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to 4238 * firmware 4239 * @ioc: per adapter object 4240 * @smid: system request message index 4241 */ 4242 void 4243 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4244 { 4245 Mpi2RequestDescriptorUnion_t descriptor; 4246 u64 *request = (u64 *)&descriptor; 4247 4248 descriptor.Default.RequestFlags = 4249 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED; 4250 descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4251 descriptor.Default.SMID = cpu_to_le16(smid); 4252 descriptor.Default.LMID = 0; 4253 descriptor.Default.DescriptorTypeDependent = 0; 4254 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4255 &ioc->scsi_lookup_lock); 4256 } 4257 4258 /** 4259 * _base_put_smid_default - Default, primarily used for config pages 4260 * @ioc: per adapter object 4261 * @smid: system request message index 4262 */ 4263 static void 4264 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4265 { 4266 Mpi2RequestDescriptorUnion_t descriptor; 4267 void *mpi_req_iomem; 4268 u64 *request; 4269 4270 if (ioc->is_mcpu_endpoint) { 4271 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 4272 4273 _clone_sg_entries(ioc, (void *) mfp, smid); 4274 /* TBD 256 is offset within sys register */ 4275 mpi_req_iomem = (void __force *)ioc->chip + 4276 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 4277 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 4278 ioc->request_sz); 4279 } 4280 request = (u64 *)&descriptor; 4281 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 4282 descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4283 descriptor.Default.SMID = cpu_to_le16(smid); 4284 descriptor.Default.LMID = 0; 4285 descriptor.Default.DescriptorTypeDependent = 0; 4286 if (ioc->is_mcpu_endpoint) 4287 _base_mpi_ep_writeq(*request, 4288 &ioc->chip->RequestDescriptorPostLow, 4289 &ioc->scsi_lookup_lock); 4290 else 4291 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 4292 &ioc->scsi_lookup_lock); 4293 } 4294 4295 /** 4296 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using 4297 * Atomic Request Descriptor 4298 * @ioc: per adapter object 4299 * @smid: system request message index 4300 * @handle: device handle, unused in this function, for function type match 4301 * 4302 * Return: nothing. 4303 */ 4304 static void 4305 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4306 u16 handle) 4307 { 4308 Mpi26AtomicRequestDescriptor_t descriptor; 4309 u32 *request = (u32 *)&descriptor; 4310 4311 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 4312 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4313 descriptor.SMID = cpu_to_le16(smid); 4314 4315 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4316 } 4317 4318 /** 4319 * _base_put_smid_fast_path_atomic - send fast path request to firmware 4320 * using Atomic Request Descriptor 4321 * @ioc: per adapter object 4322 * @smid: system request message index 4323 * @handle: device handle, unused in this function, for function type match 4324 * Return: nothing 4325 */ 4326 static void 4327 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4328 u16 handle) 4329 { 4330 Mpi26AtomicRequestDescriptor_t descriptor; 4331 u32 *request = (u32 *)&descriptor; 4332 4333 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 4334 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4335 descriptor.SMID = cpu_to_le16(smid); 4336 4337 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4338 } 4339 4340 /** 4341 * _base_put_smid_hi_priority_atomic - send Task Management request to 4342 * firmware using Atomic Request Descriptor 4343 * @ioc: per adapter object 4344 * @smid: system request message index 4345 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 4346 * 4347 * Return: nothing. 4348 */ 4349 static void 4350 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 4351 u16 msix_task) 4352 { 4353 Mpi26AtomicRequestDescriptor_t descriptor; 4354 u32 *request = (u32 *)&descriptor; 4355 4356 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 4357 descriptor.MSIxIndex = msix_task; 4358 descriptor.SMID = cpu_to_le16(smid); 4359 4360 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4361 } 4362 4363 /** 4364 * _base_put_smid_default_atomic - Default, primarily used for config pages 4365 * use Atomic Request Descriptor 4366 * @ioc: per adapter object 4367 * @smid: system request message index 4368 * 4369 * Return: nothing. 4370 */ 4371 static void 4372 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) 4373 { 4374 Mpi26AtomicRequestDescriptor_t descriptor; 4375 u32 *request = (u32 *)&descriptor; 4376 4377 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 4378 descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); 4379 descriptor.SMID = cpu_to_le16(smid); 4380 4381 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 4382 } 4383 4384 /** 4385 * _base_display_OEMs_branding - Display branding string 4386 * @ioc: per adapter object 4387 */ 4388 static void 4389 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 4390 { 4391 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 4392 return; 4393 4394 switch (ioc->pdev->subsystem_vendor) { 4395 case PCI_VENDOR_ID_INTEL: 4396 switch (ioc->pdev->device) { 4397 case MPI2_MFGPAGE_DEVID_SAS2008: 4398 switch (ioc->pdev->subsystem_device) { 4399 case MPT2SAS_INTEL_RMS2LL080_SSDID: 4400 ioc_info(ioc, "%s\n", 4401 MPT2SAS_INTEL_RMS2LL080_BRANDING); 4402 break; 4403 case MPT2SAS_INTEL_RMS2LL040_SSDID: 4404 ioc_info(ioc, "%s\n", 4405 MPT2SAS_INTEL_RMS2LL040_BRANDING); 4406 break; 4407 case MPT2SAS_INTEL_SSD910_SSDID: 4408 ioc_info(ioc, "%s\n", 4409 MPT2SAS_INTEL_SSD910_BRANDING); 4410 break; 4411 default: 4412 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4413 ioc->pdev->subsystem_device); 4414 break; 4415 } 4416 break; 4417 case MPI2_MFGPAGE_DEVID_SAS2308_2: 4418 switch (ioc->pdev->subsystem_device) { 4419 case MPT2SAS_INTEL_RS25GB008_SSDID: 4420 ioc_info(ioc, "%s\n", 4421 MPT2SAS_INTEL_RS25GB008_BRANDING); 4422 break; 4423 case MPT2SAS_INTEL_RMS25JB080_SSDID: 4424 ioc_info(ioc, "%s\n", 4425 MPT2SAS_INTEL_RMS25JB080_BRANDING); 4426 break; 4427 case MPT2SAS_INTEL_RMS25JB040_SSDID: 4428 ioc_info(ioc, "%s\n", 4429 MPT2SAS_INTEL_RMS25JB040_BRANDING); 4430 break; 4431 case MPT2SAS_INTEL_RMS25KB080_SSDID: 4432 ioc_info(ioc, "%s\n", 4433 MPT2SAS_INTEL_RMS25KB080_BRANDING); 4434 break; 4435 case MPT2SAS_INTEL_RMS25KB040_SSDID: 4436 ioc_info(ioc, "%s\n", 4437 MPT2SAS_INTEL_RMS25KB040_BRANDING); 4438 break; 4439 case MPT2SAS_INTEL_RMS25LB040_SSDID: 4440 ioc_info(ioc, "%s\n", 4441 MPT2SAS_INTEL_RMS25LB040_BRANDING); 4442 break; 4443 case MPT2SAS_INTEL_RMS25LB080_SSDID: 4444 ioc_info(ioc, "%s\n", 4445 MPT2SAS_INTEL_RMS25LB080_BRANDING); 4446 break; 4447 default: 4448 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4449 ioc->pdev->subsystem_device); 4450 break; 4451 } 4452 break; 4453 case MPI25_MFGPAGE_DEVID_SAS3008: 4454 switch (ioc->pdev->subsystem_device) { 4455 case MPT3SAS_INTEL_RMS3JC080_SSDID: 4456 ioc_info(ioc, "%s\n", 4457 MPT3SAS_INTEL_RMS3JC080_BRANDING); 4458 break; 4459 4460 case MPT3SAS_INTEL_RS3GC008_SSDID: 4461 ioc_info(ioc, "%s\n", 4462 MPT3SAS_INTEL_RS3GC008_BRANDING); 4463 break; 4464 case MPT3SAS_INTEL_RS3FC044_SSDID: 4465 ioc_info(ioc, "%s\n", 4466 MPT3SAS_INTEL_RS3FC044_BRANDING); 4467 break; 4468 case MPT3SAS_INTEL_RS3UC080_SSDID: 4469 ioc_info(ioc, "%s\n", 4470 MPT3SAS_INTEL_RS3UC080_BRANDING); 4471 break; 4472 default: 4473 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4474 ioc->pdev->subsystem_device); 4475 break; 4476 } 4477 break; 4478 default: 4479 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", 4480 ioc->pdev->subsystem_device); 4481 break; 4482 } 4483 break; 4484 case PCI_VENDOR_ID_DELL: 4485 switch (ioc->pdev->device) { 4486 case MPI2_MFGPAGE_DEVID_SAS2008: 4487 switch (ioc->pdev->subsystem_device) { 4488 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 4489 ioc_info(ioc, "%s\n", 4490 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 4491 break; 4492 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 4493 ioc_info(ioc, "%s\n", 4494 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 4495 break; 4496 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 4497 ioc_info(ioc, "%s\n", 4498 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 4499 break; 4500 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 4501 ioc_info(ioc, "%s\n", 4502 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 4503 break; 4504 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 4505 ioc_info(ioc, "%s\n", 4506 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 4507 break; 4508 case MPT2SAS_DELL_PERC_H200_SSDID: 4509 ioc_info(ioc, "%s\n", 4510 MPT2SAS_DELL_PERC_H200_BRANDING); 4511 break; 4512 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 4513 ioc_info(ioc, "%s\n", 4514 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 4515 break; 4516 default: 4517 ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 4518 ioc->pdev->subsystem_device); 4519 break; 4520 } 4521 break; 4522 case MPI25_MFGPAGE_DEVID_SAS3008: 4523 switch (ioc->pdev->subsystem_device) { 4524 case MPT3SAS_DELL_12G_HBA_SSDID: 4525 ioc_info(ioc, "%s\n", 4526 MPT3SAS_DELL_12G_HBA_BRANDING); 4527 break; 4528 default: 4529 ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 4530 ioc->pdev->subsystem_device); 4531 break; 4532 } 4533 break; 4534 default: 4535 ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n", 4536 ioc->pdev->subsystem_device); 4537 break; 4538 } 4539 break; 4540 case PCI_VENDOR_ID_CISCO: 4541 switch (ioc->pdev->device) { 4542 case MPI25_MFGPAGE_DEVID_SAS3008: 4543 switch (ioc->pdev->subsystem_device) { 4544 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 4545 ioc_info(ioc, "%s\n", 4546 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 4547 break; 4548 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 4549 ioc_info(ioc, "%s\n", 4550 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 4551 break; 4552 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 4553 ioc_info(ioc, "%s\n", 4554 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 4555 break; 4556 default: 4557 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 4558 ioc->pdev->subsystem_device); 4559 break; 4560 } 4561 break; 4562 case MPI25_MFGPAGE_DEVID_SAS3108_1: 4563 switch (ioc->pdev->subsystem_device) { 4564 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 4565 ioc_info(ioc, "%s\n", 4566 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 4567 break; 4568 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 4569 ioc_info(ioc, "%s\n", 4570 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING); 4571 break; 4572 default: 4573 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 4574 ioc->pdev->subsystem_device); 4575 break; 4576 } 4577 break; 4578 default: 4579 ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n", 4580 ioc->pdev->subsystem_device); 4581 break; 4582 } 4583 break; 4584 case MPT2SAS_HP_3PAR_SSVID: 4585 switch (ioc->pdev->device) { 4586 case MPI2_MFGPAGE_DEVID_SAS2004: 4587 switch (ioc->pdev->subsystem_device) { 4588 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 4589 ioc_info(ioc, "%s\n", 4590 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 4591 break; 4592 default: 4593 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 4594 ioc->pdev->subsystem_device); 4595 break; 4596 } 4597 break; 4598 case MPI2_MFGPAGE_DEVID_SAS2308_2: 4599 switch (ioc->pdev->subsystem_device) { 4600 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 4601 ioc_info(ioc, "%s\n", 4602 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 4603 break; 4604 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 4605 ioc_info(ioc, "%s\n", 4606 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 4607 break; 4608 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 4609 ioc_info(ioc, "%s\n", 4610 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 4611 break; 4612 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 4613 ioc_info(ioc, "%s\n", 4614 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 4615 break; 4616 default: 4617 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 4618 ioc->pdev->subsystem_device); 4619 break; 4620 } 4621 break; 4622 default: 4623 ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n", 4624 ioc->pdev->subsystem_device); 4625 break; 4626 } 4627 break; 4628 default: 4629 break; 4630 } 4631 } 4632 4633 /** 4634 * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg 4635 * version from FW Image Header. 4636 * @ioc: per adapter object 4637 * 4638 * Return: 0 for success, non-zero for failure. 4639 */ 4640 static int 4641 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc) 4642 { 4643 Mpi2FWImageHeader_t *fw_img_hdr; 4644 Mpi26ComponentImageHeader_t *cmp_img_hdr; 4645 Mpi25FWUploadRequest_t *mpi_request; 4646 Mpi2FWUploadReply_t mpi_reply; 4647 int r = 0, issue_diag_reset = 0; 4648 u32 package_version = 0; 4649 void *fwpkg_data = NULL; 4650 dma_addr_t fwpkg_data_dma; 4651 u16 smid, ioc_status; 4652 size_t data_length; 4653 4654 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 4655 4656 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4657 ioc_err(ioc, "%s: internal command already in use\n", __func__); 4658 return -EAGAIN; 4659 } 4660 4661 data_length = sizeof(Mpi2FWImageHeader_t); 4662 fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length, 4663 &fwpkg_data_dma, GFP_KERNEL); 4664 if (!fwpkg_data) { 4665 ioc_err(ioc, 4666 "Memory allocation for fwpkg data failed at %s:%d/%s()!\n", 4667 __FILE__, __LINE__, __func__); 4668 return -ENOMEM; 4669 } 4670 4671 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4672 if (!smid) { 4673 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 4674 r = -EAGAIN; 4675 goto out; 4676 } 4677 4678 ioc->base_cmds.status = MPT3_CMD_PENDING; 4679 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4680 ioc->base_cmds.smid = smid; 4681 memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t)); 4682 mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD; 4683 mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH; 4684 mpi_request->ImageSize = cpu_to_le32(data_length); 4685 ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma, 4686 data_length); 4687 init_completion(&ioc->base_cmds.done); 4688 ioc->put_smid_default(ioc, smid); 4689 /* Wait for 15 seconds */ 4690 wait_for_completion_timeout(&ioc->base_cmds.done, 4691 FW_IMG_HDR_READ_TIMEOUT*HZ); 4692 ioc_info(ioc, "%s: complete\n", __func__); 4693 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4694 ioc_err(ioc, "%s: timeout\n", __func__); 4695 _debug_dump_mf(mpi_request, 4696 sizeof(Mpi25FWUploadRequest_t)/4); 4697 issue_diag_reset = 1; 4698 } else { 4699 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t)); 4700 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) { 4701 memcpy(&mpi_reply, ioc->base_cmds.reply, 4702 sizeof(Mpi2FWUploadReply_t)); 4703 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 4704 MPI2_IOCSTATUS_MASK; 4705 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 4706 fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data; 4707 if (le32_to_cpu(fw_img_hdr->Signature) == 4708 MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) { 4709 cmp_img_hdr = 4710 (Mpi26ComponentImageHeader_t *) 4711 (fwpkg_data); 4712 package_version = 4713 le32_to_cpu( 4714 cmp_img_hdr->ApplicationSpecific); 4715 } else 4716 package_version = 4717 le32_to_cpu( 4718 fw_img_hdr->PackageVersion.Word); 4719 if (package_version) 4720 ioc_info(ioc, 4721 "FW Package Ver(%02d.%02d.%02d.%02d)\n", 4722 ((package_version) & 0xFF000000) >> 24, 4723 ((package_version) & 0x00FF0000) >> 16, 4724 ((package_version) & 0x0000FF00) >> 8, 4725 (package_version) & 0x000000FF); 4726 } else { 4727 _debug_dump_mf(&mpi_reply, 4728 sizeof(Mpi2FWUploadReply_t)/4); 4729 } 4730 } 4731 } 4732 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4733 out: 4734 if (fwpkg_data) 4735 dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data, 4736 fwpkg_data_dma); 4737 if (issue_diag_reset) { 4738 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) 4739 return -EFAULT; 4740 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) 4741 return -EFAULT; 4742 r = -EAGAIN; 4743 } 4744 return r; 4745 } 4746 4747 /** 4748 * _base_display_ioc_capabilities - Display IOC's capabilities. 4749 * @ioc: per adapter object 4750 */ 4751 static void 4752 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 4753 { 4754 int i = 0; 4755 char desc[16]; 4756 u32 iounit_pg1_flags; 4757 u32 bios_version; 4758 4759 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 4760 strncpy(desc, ioc->manu_pg0.ChipName, 16); 4761 ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 4762 desc, 4763 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 4764 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 4765 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 4766 ioc->facts.FWVersion.Word & 0x000000FF, 4767 ioc->pdev->revision, 4768 (bios_version & 0xFF000000) >> 24, 4769 (bios_version & 0x00FF0000) >> 16, 4770 (bios_version & 0x0000FF00) >> 8, 4771 bios_version & 0x000000FF); 4772 4773 _base_display_OEMs_branding(ioc); 4774 4775 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 4776 pr_info("%sNVMe", i ? "," : ""); 4777 i++; 4778 } 4779 4780 ioc_info(ioc, "Protocol=("); 4781 4782 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 4783 pr_cont("Initiator"); 4784 i++; 4785 } 4786 4787 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 4788 pr_cont("%sTarget", i ? "," : ""); 4789 i++; 4790 } 4791 4792 i = 0; 4793 pr_cont("), Capabilities=("); 4794 4795 if (!ioc->hide_ir_msg) { 4796 if (ioc->facts.IOCCapabilities & 4797 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 4798 pr_cont("Raid"); 4799 i++; 4800 } 4801 } 4802 4803 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 4804 pr_cont("%sTLR", i ? "," : ""); 4805 i++; 4806 } 4807 4808 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 4809 pr_cont("%sMulticast", i ? "," : ""); 4810 i++; 4811 } 4812 4813 if (ioc->facts.IOCCapabilities & 4814 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 4815 pr_cont("%sBIDI Target", i ? "," : ""); 4816 i++; 4817 } 4818 4819 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 4820 pr_cont("%sEEDP", i ? "," : ""); 4821 i++; 4822 } 4823 4824 if (ioc->facts.IOCCapabilities & 4825 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 4826 pr_cont("%sSnapshot Buffer", i ? "," : ""); 4827 i++; 4828 } 4829 4830 if (ioc->facts.IOCCapabilities & 4831 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 4832 pr_cont("%sDiag Trace Buffer", i ? "," : ""); 4833 i++; 4834 } 4835 4836 if (ioc->facts.IOCCapabilities & 4837 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 4838 pr_cont("%sDiag Extended Buffer", i ? "," : ""); 4839 i++; 4840 } 4841 4842 if (ioc->facts.IOCCapabilities & 4843 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 4844 pr_cont("%sTask Set Full", i ? "," : ""); 4845 i++; 4846 } 4847 4848 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 4849 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 4850 pr_cont("%sNCQ", i ? "," : ""); 4851 i++; 4852 } 4853 4854 pr_cont(")\n"); 4855 } 4856 4857 /** 4858 * mpt3sas_base_update_missing_delay - change the missing delay timers 4859 * @ioc: per adapter object 4860 * @device_missing_delay: amount of time till device is reported missing 4861 * @io_missing_delay: interval IO is returned when there is a missing device 4862 * 4863 * Passed on the command line, this function will modify the device missing 4864 * delay, as well as the io missing delay. This should be called at driver 4865 * load time. 4866 */ 4867 void 4868 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 4869 u16 device_missing_delay, u8 io_missing_delay) 4870 { 4871 u16 dmd, dmd_new, dmd_orignal; 4872 u8 io_missing_delay_original; 4873 u16 sz; 4874 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 4875 Mpi2ConfigReply_t mpi_reply; 4876 u8 num_phys = 0; 4877 u16 ioc_status; 4878 4879 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 4880 if (!num_phys) 4881 return; 4882 4883 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 4884 sizeof(Mpi2SasIOUnit1PhyData_t)); 4885 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 4886 if (!sas_iounit_pg1) { 4887 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4888 __FILE__, __LINE__, __func__); 4889 goto out; 4890 } 4891 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 4892 sas_iounit_pg1, sz))) { 4893 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4894 __FILE__, __LINE__, __func__); 4895 goto out; 4896 } 4897 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 4898 MPI2_IOCSTATUS_MASK; 4899 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4900 ioc_err(ioc, "failure at %s:%d/%s()!\n", 4901 __FILE__, __LINE__, __func__); 4902 goto out; 4903 } 4904 4905 /* device missing delay */ 4906 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 4907 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4908 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4909 else 4910 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4911 dmd_orignal = dmd; 4912 if (device_missing_delay > 0x7F) { 4913 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 4914 device_missing_delay; 4915 dmd = dmd / 16; 4916 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 4917 } else 4918 dmd = device_missing_delay; 4919 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 4920 4921 /* io missing delay */ 4922 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 4923 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 4924 4925 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 4926 sz)) { 4927 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4928 dmd_new = (dmd & 4929 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4930 else 4931 dmd_new = 4932 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4933 ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n", 4934 dmd_orignal, dmd_new); 4935 ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n", 4936 io_missing_delay_original, 4937 io_missing_delay); 4938 ioc->device_missing_delay = dmd_new; 4939 ioc->io_missing_delay = io_missing_delay; 4940 } 4941 4942 out: 4943 kfree(sas_iounit_pg1); 4944 } 4945 4946 /** 4947 * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields 4948 * according to performance mode. 4949 * @ioc : per adapter object 4950 * 4951 * Return: zero on success; otherwise return EAGAIN error code asking the 4952 * caller to retry. 4953 */ 4954 static int 4955 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc) 4956 { 4957 Mpi2IOCPage1_t ioc_pg1; 4958 Mpi2ConfigReply_t mpi_reply; 4959 int rc; 4960 4961 rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy); 4962 if (rc) 4963 return rc; 4964 memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t)); 4965 4966 switch (perf_mode) { 4967 case MPT_PERF_MODE_DEFAULT: 4968 case MPT_PERF_MODE_BALANCED: 4969 if (ioc->high_iops_queues) { 4970 ioc_info(ioc, 4971 "Enable interrupt coalescing only for first\t" 4972 "%d reply queues\n", 4973 MPT3SAS_HIGH_IOPS_REPLY_QUEUES); 4974 /* 4975 * If 31st bit is zero then interrupt coalescing is 4976 * enabled for all reply descriptor post queues. 4977 * If 31st bit is set to one then user can 4978 * enable/disable interrupt coalescing on per reply 4979 * descriptor post queue group(8) basis. So to enable 4980 * interrupt coalescing only on first reply descriptor 4981 * post queue group 31st bit and zero th bit is enabled. 4982 */ 4983 ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 | 4984 ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1)); 4985 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 4986 if (rc) 4987 return rc; 4988 ioc_info(ioc, "performance mode: balanced\n"); 4989 return 0; 4990 } 4991 fallthrough; 4992 case MPT_PERF_MODE_LATENCY: 4993 /* 4994 * Enable interrupt coalescing on all reply queues 4995 * with timeout value 0xA 4996 */ 4997 ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa); 4998 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); 4999 ioc_pg1.ProductSpecific = 0; 5000 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 5001 if (rc) 5002 return rc; 5003 ioc_info(ioc, "performance mode: latency\n"); 5004 break; 5005 case MPT_PERF_MODE_IOPS: 5006 /* 5007 * Enable interrupt coalescing on all reply queues. 5008 */ 5009 ioc_info(ioc, 5010 "performance mode: iops with coalescing timeout: 0x%x\n", 5011 le32_to_cpu(ioc_pg1.CoalescingTimeout)); 5012 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); 5013 ioc_pg1.ProductSpecific = 0; 5014 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); 5015 if (rc) 5016 return rc; 5017 break; 5018 } 5019 return 0; 5020 } 5021 5022 /** 5023 * _base_get_event_diag_triggers - get event diag trigger values from 5024 * persistent pages 5025 * @ioc : per adapter object 5026 * 5027 * Return: nothing. 5028 */ 5029 static int 5030 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5031 { 5032 Mpi26DriverTriggerPage2_t trigger_pg2; 5033 struct SL_WH_EVENT_TRIGGER_T *event_tg; 5034 MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg; 5035 Mpi2ConfigReply_t mpi_reply; 5036 int r = 0, i = 0; 5037 u16 count = 0; 5038 u16 ioc_status; 5039 5040 r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply, 5041 &trigger_pg2); 5042 if (r) 5043 return r; 5044 5045 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5046 MPI2_IOCSTATUS_MASK; 5047 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5048 dinitprintk(ioc, 5049 ioc_err(ioc, 5050 "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n", 5051 __func__, ioc_status)); 5052 return 0; 5053 } 5054 5055 if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) { 5056 count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger); 5057 count = min_t(u16, NUM_VALID_ENTRIES, count); 5058 ioc->diag_trigger_event.ValidEntries = count; 5059 5060 event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0]; 5061 mpi_event_tg = &trigger_pg2.MPIEventTriggers[0]; 5062 for (i = 0; i < count; i++) { 5063 event_tg->EventValue = le16_to_cpu( 5064 mpi_event_tg->MPIEventCode); 5065 event_tg->LogEntryQualifier = le16_to_cpu( 5066 mpi_event_tg->MPIEventCodeSpecific); 5067 event_tg++; 5068 mpi_event_tg++; 5069 } 5070 } 5071 return 0; 5072 } 5073 5074 /** 5075 * _base_get_scsi_diag_triggers - get scsi diag trigger values from 5076 * persistent pages 5077 * @ioc : per adapter object 5078 * 5079 * Return: 0 on success; otherwise return failure status. 5080 */ 5081 static int 5082 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5083 { 5084 Mpi26DriverTriggerPage3_t trigger_pg3; 5085 struct SL_WH_SCSI_TRIGGER_T *scsi_tg; 5086 MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg; 5087 Mpi2ConfigReply_t mpi_reply; 5088 int r = 0, i = 0; 5089 u16 count = 0; 5090 u16 ioc_status; 5091 5092 r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply, 5093 &trigger_pg3); 5094 if (r) 5095 return r; 5096 5097 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5098 MPI2_IOCSTATUS_MASK; 5099 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5100 dinitprintk(ioc, 5101 ioc_err(ioc, 5102 "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n", 5103 __func__, ioc_status)); 5104 return 0; 5105 } 5106 5107 if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) { 5108 count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger); 5109 count = min_t(u16, NUM_VALID_ENTRIES, count); 5110 ioc->diag_trigger_scsi.ValidEntries = count; 5111 5112 scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0]; 5113 mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0]; 5114 for (i = 0; i < count; i++) { 5115 scsi_tg->ASCQ = mpi_scsi_tg->ASCQ; 5116 scsi_tg->ASC = mpi_scsi_tg->ASC; 5117 scsi_tg->SenseKey = mpi_scsi_tg->SenseKey; 5118 5119 scsi_tg++; 5120 mpi_scsi_tg++; 5121 } 5122 } 5123 return 0; 5124 } 5125 5126 /** 5127 * _base_get_mpi_diag_triggers - get mpi diag trigger values from 5128 * persistent pages 5129 * @ioc : per adapter object 5130 * 5131 * Return: 0 on success; otherwise return failure status. 5132 */ 5133 static int 5134 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5135 { 5136 Mpi26DriverTriggerPage4_t trigger_pg4; 5137 struct SL_WH_MPI_TRIGGER_T *status_tg; 5138 MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg; 5139 Mpi2ConfigReply_t mpi_reply; 5140 int r = 0, i = 0; 5141 u16 count = 0; 5142 u16 ioc_status; 5143 5144 r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply, 5145 &trigger_pg4); 5146 if (r) 5147 return r; 5148 5149 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5150 MPI2_IOCSTATUS_MASK; 5151 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5152 dinitprintk(ioc, 5153 ioc_err(ioc, 5154 "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n", 5155 __func__, ioc_status)); 5156 return 0; 5157 } 5158 5159 if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) { 5160 count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger); 5161 count = min_t(u16, NUM_VALID_ENTRIES, count); 5162 ioc->diag_trigger_mpi.ValidEntries = count; 5163 5164 status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0]; 5165 mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0]; 5166 5167 for (i = 0; i < count; i++) { 5168 status_tg->IOCStatus = le16_to_cpu( 5169 mpi_status_tg->IOCStatus); 5170 status_tg->IocLogInfo = le32_to_cpu( 5171 mpi_status_tg->LogInfo); 5172 5173 status_tg++; 5174 mpi_status_tg++; 5175 } 5176 } 5177 return 0; 5178 } 5179 5180 /** 5181 * _base_get_master_diag_triggers - get master diag trigger values from 5182 * persistent pages 5183 * @ioc : per adapter object 5184 * 5185 * Return: nothing. 5186 */ 5187 static int 5188 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5189 { 5190 Mpi26DriverTriggerPage1_t trigger_pg1; 5191 Mpi2ConfigReply_t mpi_reply; 5192 int r; 5193 u16 ioc_status; 5194 5195 r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply, 5196 &trigger_pg1); 5197 if (r) 5198 return r; 5199 5200 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5201 MPI2_IOCSTATUS_MASK; 5202 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5203 dinitprintk(ioc, 5204 ioc_err(ioc, 5205 "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n", 5206 __func__, ioc_status)); 5207 return 0; 5208 } 5209 5210 if (le16_to_cpu(trigger_pg1.NumMasterTrigger)) 5211 ioc->diag_trigger_master.MasterData |= 5212 le32_to_cpu( 5213 trigger_pg1.MasterTriggers[0].MasterTriggerFlags); 5214 return 0; 5215 } 5216 5217 /** 5218 * _base_check_for_trigger_pages_support - checks whether HBA FW supports 5219 * driver trigger pages or not 5220 * @ioc : per adapter object 5221 * @trigger_flags : address where trigger page0's TriggerFlags value is copied 5222 * 5223 * Return: trigger flags mask if HBA FW supports driver trigger pages; 5224 * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or 5225 * return EAGAIN if diag reset occurred due to FW fault and asking the 5226 * caller to retry the command. 5227 * 5228 */ 5229 static int 5230 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags) 5231 { 5232 Mpi26DriverTriggerPage0_t trigger_pg0; 5233 int r = 0; 5234 Mpi2ConfigReply_t mpi_reply; 5235 u16 ioc_status; 5236 5237 r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply, 5238 &trigger_pg0); 5239 if (r) 5240 return r; 5241 5242 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 5243 MPI2_IOCSTATUS_MASK; 5244 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 5245 return -EFAULT; 5246 5247 *trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags); 5248 return 0; 5249 } 5250 5251 /** 5252 * _base_get_diag_triggers - Retrieve diag trigger values from 5253 * persistent pages. 5254 * @ioc : per adapter object 5255 * 5256 * Return: zero on success; otherwise return EAGAIN error codes 5257 * asking the caller to retry. 5258 */ 5259 static int 5260 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc) 5261 { 5262 int trigger_flags; 5263 int r; 5264 5265 /* 5266 * Default setting of master trigger. 5267 */ 5268 ioc->diag_trigger_master.MasterData = 5269 (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET); 5270 5271 r = _base_check_for_trigger_pages_support(ioc, &trigger_flags); 5272 if (r) { 5273 if (r == -EAGAIN) 5274 return r; 5275 /* 5276 * Don't go for error handling when FW doesn't support 5277 * driver trigger pages. 5278 */ 5279 return 0; 5280 } 5281 5282 ioc->supports_trigger_pages = 1; 5283 5284 /* 5285 * Retrieve master diag trigger values from driver trigger pg1 5286 * if master trigger bit enabled in TriggerFlags. 5287 */ 5288 if ((u16)trigger_flags & 5289 MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) { 5290 r = _base_get_master_diag_triggers(ioc); 5291 if (r) 5292 return r; 5293 } 5294 5295 /* 5296 * Retrieve event diag trigger values from driver trigger pg2 5297 * if event trigger bit enabled in TriggerFlags. 5298 */ 5299 if ((u16)trigger_flags & 5300 MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) { 5301 r = _base_get_event_diag_triggers(ioc); 5302 if (r) 5303 return r; 5304 } 5305 5306 /* 5307 * Retrieve scsi diag trigger values from driver trigger pg3 5308 * if scsi trigger bit enabled in TriggerFlags. 5309 */ 5310 if ((u16)trigger_flags & 5311 MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) { 5312 r = _base_get_scsi_diag_triggers(ioc); 5313 if (r) 5314 return r; 5315 } 5316 /* 5317 * Retrieve mpi error diag trigger values from driver trigger pg4 5318 * if loginfo trigger bit enabled in TriggerFlags. 5319 */ 5320 if ((u16)trigger_flags & 5321 MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) { 5322 r = _base_get_mpi_diag_triggers(ioc); 5323 if (r) 5324 return r; 5325 } 5326 return 0; 5327 } 5328 5329 /** 5330 * _base_update_diag_trigger_pages - Update the driver trigger pages after 5331 * online FW update, in case updated FW supports driver 5332 * trigger pages. 5333 * @ioc : per adapter object 5334 * 5335 * Return: nothing. 5336 */ 5337 static void 5338 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc) 5339 { 5340 5341 if (ioc->diag_trigger_master.MasterData) 5342 mpt3sas_config_update_driver_trigger_pg1(ioc, 5343 &ioc->diag_trigger_master, 1); 5344 5345 if (ioc->diag_trigger_event.ValidEntries) 5346 mpt3sas_config_update_driver_trigger_pg2(ioc, 5347 &ioc->diag_trigger_event, 1); 5348 5349 if (ioc->diag_trigger_scsi.ValidEntries) 5350 mpt3sas_config_update_driver_trigger_pg3(ioc, 5351 &ioc->diag_trigger_scsi, 1); 5352 5353 if (ioc->diag_trigger_mpi.ValidEntries) 5354 mpt3sas_config_update_driver_trigger_pg4(ioc, 5355 &ioc->diag_trigger_mpi, 1); 5356 } 5357 5358 /** 5359 * _base_assign_fw_reported_qd - Get FW reported QD for SAS/SATA devices. 5360 * - On failure set default QD values. 5361 * @ioc : per adapter object 5362 * 5363 * Returns 0 for success, non-zero for failure. 5364 * 5365 */ 5366 static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc) 5367 { 5368 Mpi2ConfigReply_t mpi_reply; 5369 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 5370 Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1; 5371 int sz; 5372 int rc = 0; 5373 5374 ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH; 5375 ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH; 5376 ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH; 5377 ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH; 5378 if (!ioc->is_gen35_ioc) 5379 goto out; 5380 /* sas iounit page 1 */ 5381 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData); 5382 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 5383 if (!sas_iounit_pg1) { 5384 pr_err("%s: failure at %s:%d/%s()!\n", 5385 ioc->name, __FILE__, __LINE__, __func__); 5386 return rc; 5387 } 5388 rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 5389 sas_iounit_pg1, sz); 5390 if (rc) { 5391 pr_err("%s: failure at %s:%d/%s()!\n", 5392 ioc->name, __FILE__, __LINE__, __func__); 5393 goto out; 5394 } 5395 ioc->max_wideport_qd = 5396 (le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth)) ? 5397 le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth) : 5398 MPT3SAS_SAS_QUEUE_DEPTH; 5399 ioc->max_narrowport_qd = 5400 (le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth)) ? 5401 le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth) : 5402 MPT3SAS_SAS_QUEUE_DEPTH; 5403 ioc->max_sata_qd = (sas_iounit_pg1->SATAMaxQDepth) ? 5404 sas_iounit_pg1->SATAMaxQDepth : MPT3SAS_SATA_QUEUE_DEPTH; 5405 /* pcie iounit page 1 */ 5406 rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply, 5407 &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t)); 5408 if (rc) { 5409 pr_err("%s: failure at %s:%d/%s()!\n", 5410 ioc->name, __FILE__, __LINE__, __func__); 5411 goto out; 5412 } 5413 ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ? 5414 (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) : 5415 MPT3SAS_NVME_QUEUE_DEPTH; 5416 out: 5417 dinitprintk(ioc, pr_err( 5418 "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n", 5419 ioc->max_wideport_qd, ioc->max_narrowport_qd, 5420 ioc->max_sata_qd, ioc->max_nvme_qd)); 5421 kfree(sas_iounit_pg1); 5422 return rc; 5423 } 5424 5425 /** 5426 * _base_static_config_pages - static start of day config pages 5427 * @ioc: per adapter object 5428 */ 5429 static int 5430 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 5431 { 5432 Mpi2ConfigReply_t mpi_reply; 5433 u32 iounit_pg1_flags; 5434 int tg_flags = 0; 5435 int rc; 5436 ioc->nvme_abort_timeout = 30; 5437 5438 rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, 5439 &ioc->manu_pg0); 5440 if (rc) 5441 return rc; 5442 if (ioc->ir_firmware) { 5443 rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 5444 &ioc->manu_pg10); 5445 if (rc) 5446 return rc; 5447 } 5448 /* 5449 * Ensure correct T10 PI operation if vendor left EEDPTagMode 5450 * flag unset in NVDATA. 5451 */ 5452 rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, 5453 &ioc->manu_pg11); 5454 if (rc) 5455 return rc; 5456 if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) { 5457 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 5458 ioc->name); 5459 ioc->manu_pg11.EEDPTagMode &= ~0x3; 5460 ioc->manu_pg11.EEDPTagMode |= 0x1; 5461 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 5462 &ioc->manu_pg11); 5463 } 5464 if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK) 5465 ioc->tm_custom_handling = 1; 5466 else { 5467 ioc->tm_custom_handling = 0; 5468 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT) 5469 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT; 5470 else if (ioc->manu_pg11.NVMeAbortTO > 5471 NVME_TASK_ABORT_MAX_TIMEOUT) 5472 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT; 5473 else 5474 ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO; 5475 } 5476 ioc->time_sync_interval = 5477 ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK; 5478 if (ioc->time_sync_interval) { 5479 if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK) 5480 ioc->time_sync_interval = 5481 ioc->time_sync_interval * SECONDS_PER_HOUR; 5482 else 5483 ioc->time_sync_interval = 5484 ioc->time_sync_interval * SECONDS_PER_MIN; 5485 dinitprintk(ioc, ioc_info(ioc, 5486 "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n", 5487 ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval & 5488 MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute")); 5489 } else { 5490 if (ioc->is_gen35_ioc) 5491 ioc_warn(ioc, 5492 "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n"); 5493 } 5494 rc = _base_assign_fw_reported_qd(ioc); 5495 if (rc) 5496 return rc; 5497 rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 5498 if (rc) 5499 return rc; 5500 rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 5501 if (rc) 5502 return rc; 5503 rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 5504 if (rc) 5505 return rc; 5506 rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 5507 if (rc) 5508 return rc; 5509 rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 5510 if (rc) 5511 return rc; 5512 rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 5513 if (rc) 5514 return rc; 5515 _base_display_ioc_capabilities(ioc); 5516 5517 /* 5518 * Enable task_set_full handling in iounit_pg1 when the 5519 * facts capabilities indicate that its supported. 5520 */ 5521 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 5522 if ((ioc->facts.IOCCapabilities & 5523 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 5524 iounit_pg1_flags &= 5525 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 5526 else 5527 iounit_pg1_flags |= 5528 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 5529 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 5530 rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 5531 if (rc) 5532 return rc; 5533 5534 if (ioc->iounit_pg8.NumSensors) 5535 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 5536 if (ioc->is_aero_ioc) { 5537 rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc); 5538 if (rc) 5539 return rc; 5540 } 5541 if (ioc->is_gen35_ioc) { 5542 if (ioc->is_driver_loading) { 5543 rc = _base_get_diag_triggers(ioc); 5544 if (rc) 5545 return rc; 5546 } else { 5547 /* 5548 * In case of online HBA FW update operation, 5549 * check whether updated FW supports the driver trigger 5550 * pages or not. 5551 * - If previous FW has not supported driver trigger 5552 * pages and newer FW supports them then update these 5553 * pages with current diag trigger values. 5554 * - If previous FW has supported driver trigger pages 5555 * and new FW doesn't support them then disable 5556 * support_trigger_pages flag. 5557 */ 5558 _base_check_for_trigger_pages_support(ioc, &tg_flags); 5559 if (!ioc->supports_trigger_pages && tg_flags != -EFAULT) 5560 _base_update_diag_trigger_pages(ioc); 5561 else if (ioc->supports_trigger_pages && 5562 tg_flags == -EFAULT) 5563 ioc->supports_trigger_pages = 0; 5564 } 5565 } 5566 return 0; 5567 } 5568 5569 /** 5570 * mpt3sas_free_enclosure_list - release memory 5571 * @ioc: per adapter object 5572 * 5573 * Free memory allocated during enclosure add. 5574 */ 5575 void 5576 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc) 5577 { 5578 struct _enclosure_node *enclosure_dev, *enclosure_dev_next; 5579 5580 /* Free enclosure list */ 5581 list_for_each_entry_safe(enclosure_dev, 5582 enclosure_dev_next, &ioc->enclosure_list, list) { 5583 list_del(&enclosure_dev->list); 5584 kfree(enclosure_dev); 5585 } 5586 } 5587 5588 /** 5589 * _base_release_memory_pools - release memory 5590 * @ioc: per adapter object 5591 * 5592 * Free memory allocated from _base_allocate_memory_pools. 5593 */ 5594 static void 5595 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 5596 { 5597 int i = 0; 5598 int j = 0; 5599 int dma_alloc_count = 0; 5600 struct chain_tracker *ct; 5601 int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; 5602 5603 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 5604 5605 if (ioc->request) { 5606 dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz, 5607 ioc->request, ioc->request_dma); 5608 dexitprintk(ioc, 5609 ioc_info(ioc, "request_pool(0x%p): free\n", 5610 ioc->request)); 5611 ioc->request = NULL; 5612 } 5613 5614 if (ioc->sense) { 5615 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 5616 dma_pool_destroy(ioc->sense_dma_pool); 5617 dexitprintk(ioc, 5618 ioc_info(ioc, "sense_pool(0x%p): free\n", 5619 ioc->sense)); 5620 ioc->sense = NULL; 5621 } 5622 5623 if (ioc->reply) { 5624 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 5625 dma_pool_destroy(ioc->reply_dma_pool); 5626 dexitprintk(ioc, 5627 ioc_info(ioc, "reply_pool(0x%p): free\n", 5628 ioc->reply)); 5629 ioc->reply = NULL; 5630 } 5631 5632 if (ioc->reply_free) { 5633 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 5634 ioc->reply_free_dma); 5635 dma_pool_destroy(ioc->reply_free_dma_pool); 5636 dexitprintk(ioc, 5637 ioc_info(ioc, "reply_free_pool(0x%p): free\n", 5638 ioc->reply_free)); 5639 ioc->reply_free = NULL; 5640 } 5641 5642 if (ioc->reply_post) { 5643 dma_alloc_count = DIV_ROUND_UP(count, 5644 RDPQ_MAX_INDEX_IN_ONE_CHUNK); 5645 for (i = 0; i < count; i++) { 5646 if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 5647 && dma_alloc_count) { 5648 if (ioc->reply_post[i].reply_post_free) { 5649 dma_pool_free( 5650 ioc->reply_post_free_dma_pool, 5651 ioc->reply_post[i].reply_post_free, 5652 ioc->reply_post[i].reply_post_free_dma); 5653 dexitprintk(ioc, ioc_info(ioc, 5654 "reply_post_free_pool(0x%p): free\n", 5655 ioc->reply_post[i].reply_post_free)); 5656 ioc->reply_post[i].reply_post_free = 5657 NULL; 5658 } 5659 --dma_alloc_count; 5660 } 5661 } 5662 dma_pool_destroy(ioc->reply_post_free_dma_pool); 5663 if (ioc->reply_post_free_array && 5664 ioc->rdpq_array_enable) { 5665 dma_pool_free(ioc->reply_post_free_array_dma_pool, 5666 ioc->reply_post_free_array, 5667 ioc->reply_post_free_array_dma); 5668 ioc->reply_post_free_array = NULL; 5669 } 5670 dma_pool_destroy(ioc->reply_post_free_array_dma_pool); 5671 kfree(ioc->reply_post); 5672 } 5673 5674 if (ioc->pcie_sgl_dma_pool) { 5675 for (i = 0; i < ioc->scsiio_depth; i++) { 5676 dma_pool_free(ioc->pcie_sgl_dma_pool, 5677 ioc->pcie_sg_lookup[i].pcie_sgl, 5678 ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5679 ioc->pcie_sg_lookup[i].pcie_sgl = NULL; 5680 } 5681 dma_pool_destroy(ioc->pcie_sgl_dma_pool); 5682 } 5683 if (ioc->config_page) { 5684 dexitprintk(ioc, 5685 ioc_info(ioc, "config_page(0x%p): free\n", 5686 ioc->config_page)); 5687 dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz, 5688 ioc->config_page, ioc->config_page_dma); 5689 } 5690 5691 kfree(ioc->hpr_lookup); 5692 ioc->hpr_lookup = NULL; 5693 kfree(ioc->internal_lookup); 5694 ioc->internal_lookup = NULL; 5695 if (ioc->chain_lookup) { 5696 for (i = 0; i < ioc->scsiio_depth; i++) { 5697 for (j = ioc->chains_per_prp_buffer; 5698 j < ioc->chains_needed_per_io; j++) { 5699 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 5700 if (ct && ct->chain_buffer) 5701 dma_pool_free(ioc->chain_dma_pool, 5702 ct->chain_buffer, 5703 ct->chain_buffer_dma); 5704 } 5705 kfree(ioc->chain_lookup[i].chains_per_smid); 5706 } 5707 dma_pool_destroy(ioc->chain_dma_pool); 5708 kfree(ioc->chain_lookup); 5709 ioc->chain_lookup = NULL; 5710 } 5711 5712 kfree(ioc->io_queue_num); 5713 ioc->io_queue_num = NULL; 5714 } 5715 5716 /** 5717 * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are 5718 * having same upper 32bits in their base memory address. 5719 * @start_address: Base address of a reply queue set 5720 * @pool_sz: Size of single Reply Descriptor Post Queues pool size 5721 * 5722 * Return: 1 if reply queues in a set have a same upper 32bits in their base 5723 * memory address, else 0. 5724 */ 5725 static int 5726 mpt3sas_check_same_4gb_region(dma_addr_t start_address, u32 pool_sz) 5727 { 5728 dma_addr_t end_address; 5729 5730 end_address = start_address + pool_sz - 1; 5731 5732 if (upper_32_bits(start_address) == upper_32_bits(end_address)) 5733 return 1; 5734 else 5735 return 0; 5736 } 5737 5738 /** 5739 * _base_reduce_hba_queue_depth- Retry with reduced queue depth 5740 * @ioc: Adapter object 5741 * 5742 * Return: 0 for success, non-zero for failure. 5743 **/ 5744 static inline int 5745 _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc) 5746 { 5747 int reduce_sz = 64; 5748 5749 if ((ioc->hba_queue_depth - reduce_sz) > 5750 (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) { 5751 ioc->hba_queue_depth -= reduce_sz; 5752 return 0; 5753 } else 5754 return -ENOMEM; 5755 } 5756 5757 /** 5758 * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory 5759 * for pcie sgl pools. 5760 * @ioc: Adapter object 5761 * @sz: DMA Pool size 5762 * 5763 * Return: 0 for success, non-zero for failure. 5764 */ 5765 5766 static int 5767 _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5768 { 5769 int i = 0, j = 0; 5770 struct chain_tracker *ct; 5771 5772 ioc->pcie_sgl_dma_pool = 5773 dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 5774 ioc->page_size, 0); 5775 if (!ioc->pcie_sgl_dma_pool) { 5776 ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n"); 5777 return -ENOMEM; 5778 } 5779 5780 ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; 5781 ioc->chains_per_prp_buffer = 5782 min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io); 5783 for (i = 0; i < ioc->scsiio_depth; i++) { 5784 ioc->pcie_sg_lookup[i].pcie_sgl = 5785 dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL, 5786 &ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5787 if (!ioc->pcie_sg_lookup[i].pcie_sgl) { 5788 ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n"); 5789 return -EAGAIN; 5790 } 5791 5792 if (!mpt3sas_check_same_4gb_region( 5793 ioc->pcie_sg_lookup[i].pcie_sgl_dma, sz)) { 5794 ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n", 5795 ioc->pcie_sg_lookup[i].pcie_sgl, 5796 (unsigned long long) 5797 ioc->pcie_sg_lookup[i].pcie_sgl_dma); 5798 ioc->use_32bit_dma = true; 5799 return -EAGAIN; 5800 } 5801 5802 for (j = 0; j < ioc->chains_per_prp_buffer; j++) { 5803 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 5804 ct->chain_buffer = 5805 ioc->pcie_sg_lookup[i].pcie_sgl + 5806 (j * ioc->chain_segment_sz); 5807 ct->chain_buffer_dma = 5808 ioc->pcie_sg_lookup[i].pcie_sgl_dma + 5809 (j * ioc->chain_segment_sz); 5810 } 5811 } 5812 dinitprintk(ioc, ioc_info(ioc, 5813 "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n", 5814 ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); 5815 dinitprintk(ioc, ioc_info(ioc, 5816 "Number of chains can fit in a PRP page(%d)\n", 5817 ioc->chains_per_prp_buffer)); 5818 return 0; 5819 } 5820 5821 /** 5822 * _base_allocate_chain_dma_pool - Allocating DMA'able memory 5823 * for chain dma pool. 5824 * @ioc: Adapter object 5825 * @sz: DMA Pool size 5826 * 5827 * Return: 0 for success, non-zero for failure. 5828 */ 5829 static int 5830 _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5831 { 5832 int i = 0, j = 0; 5833 struct chain_tracker *ctr; 5834 5835 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, 5836 ioc->chain_segment_sz, 16, 0); 5837 if (!ioc->chain_dma_pool) 5838 return -ENOMEM; 5839 5840 for (i = 0; i < ioc->scsiio_depth; i++) { 5841 for (j = ioc->chains_per_prp_buffer; 5842 j < ioc->chains_needed_per_io; j++) { 5843 ctr = &ioc->chain_lookup[i].chains_per_smid[j]; 5844 ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool, 5845 GFP_KERNEL, &ctr->chain_buffer_dma); 5846 if (!ctr->chain_buffer) 5847 return -EAGAIN; 5848 if (!mpt3sas_check_same_4gb_region( 5849 ctr->chain_buffer_dma, ioc->chain_segment_sz)) { 5850 ioc_err(ioc, 5851 "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n", 5852 ctr->chain_buffer, 5853 (unsigned long long)ctr->chain_buffer_dma); 5854 ioc->use_32bit_dma = true; 5855 return -EAGAIN; 5856 } 5857 } 5858 } 5859 dinitprintk(ioc, ioc_info(ioc, 5860 "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n", 5861 ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth * 5862 (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) * 5863 ioc->chain_segment_sz))/1024)); 5864 return 0; 5865 } 5866 5867 /** 5868 * _base_allocate_sense_dma_pool - Allocating DMA'able memory 5869 * for sense dma pool. 5870 * @ioc: Adapter object 5871 * @sz: DMA Pool size 5872 * Return: 0 for success, non-zero for failure. 5873 */ 5874 static int 5875 _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5876 { 5877 ioc->sense_dma_pool = 5878 dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0); 5879 if (!ioc->sense_dma_pool) 5880 return -ENOMEM; 5881 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, 5882 GFP_KERNEL, &ioc->sense_dma); 5883 if (!ioc->sense) 5884 return -EAGAIN; 5885 if (!mpt3sas_check_same_4gb_region(ioc->sense_dma, sz)) { 5886 dinitprintk(ioc, pr_err( 5887 "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n", 5888 ioc->sense, (unsigned long long) ioc->sense_dma)); 5889 ioc->use_32bit_dma = true; 5890 return -EAGAIN; 5891 } 5892 ioc_info(ioc, 5893 "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n", 5894 ioc->sense, (unsigned long long)ioc->sense_dma, 5895 ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024); 5896 return 0; 5897 } 5898 5899 /** 5900 * _base_allocate_reply_pool - Allocating DMA'able memory 5901 * for reply pool. 5902 * @ioc: Adapter object 5903 * @sz: DMA Pool size 5904 * Return: 0 for success, non-zero for failure. 5905 */ 5906 static int 5907 _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5908 { 5909 /* reply pool, 4 byte align */ 5910 ioc->reply_dma_pool = dma_pool_create("reply pool", 5911 &ioc->pdev->dev, sz, 4, 0); 5912 if (!ioc->reply_dma_pool) 5913 return -ENOMEM; 5914 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, 5915 &ioc->reply_dma); 5916 if (!ioc->reply) 5917 return -EAGAIN; 5918 if (!mpt3sas_check_same_4gb_region(ioc->reply_dma, sz)) { 5919 dinitprintk(ioc, pr_err( 5920 "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n", 5921 ioc->reply, (unsigned long long) ioc->reply_dma)); 5922 ioc->use_32bit_dma = true; 5923 return -EAGAIN; 5924 } 5925 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 5926 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 5927 ioc_info(ioc, 5928 "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n", 5929 ioc->reply, (unsigned long long)ioc->reply_dma, 5930 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024); 5931 return 0; 5932 } 5933 5934 /** 5935 * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory 5936 * for reply free dma pool. 5937 * @ioc: Adapter object 5938 * @sz: DMA Pool size 5939 * Return: 0 for success, non-zero for failure. 5940 */ 5941 static int 5942 _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) 5943 { 5944 /* reply free queue, 16 byte align */ 5945 ioc->reply_free_dma_pool = dma_pool_create( 5946 "reply_free pool", &ioc->pdev->dev, sz, 16, 0); 5947 if (!ioc->reply_free_dma_pool) 5948 return -ENOMEM; 5949 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, 5950 GFP_KERNEL, &ioc->reply_free_dma); 5951 if (!ioc->reply_free) 5952 return -EAGAIN; 5953 if (!mpt3sas_check_same_4gb_region(ioc->reply_free_dma, sz)) { 5954 dinitprintk(ioc, 5955 pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", 5956 ioc->reply_free, (unsigned long long) ioc->reply_free_dma)); 5957 ioc->use_32bit_dma = true; 5958 return -EAGAIN; 5959 } 5960 memset(ioc->reply_free, 0, sz); 5961 dinitprintk(ioc, ioc_info(ioc, 5962 "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", 5963 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 5964 dinitprintk(ioc, ioc_info(ioc, 5965 "reply_free_dma (0x%llx)\n", 5966 (unsigned long long)ioc->reply_free_dma)); 5967 return 0; 5968 } 5969 5970 /** 5971 * _base_allocate_reply_post_free_array - Allocating DMA'able memory 5972 * for reply post free array. 5973 * @ioc: Adapter object 5974 * @reply_post_free_array_sz: DMA Pool size 5975 * Return: 0 for success, non-zero for failure. 5976 */ 5977 5978 static int 5979 _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc, 5980 u32 reply_post_free_array_sz) 5981 { 5982 ioc->reply_post_free_array_dma_pool = 5983 dma_pool_create("reply_post_free_array pool", 5984 &ioc->pdev->dev, reply_post_free_array_sz, 16, 0); 5985 if (!ioc->reply_post_free_array_dma_pool) 5986 return -ENOMEM; 5987 ioc->reply_post_free_array = 5988 dma_pool_alloc(ioc->reply_post_free_array_dma_pool, 5989 GFP_KERNEL, &ioc->reply_post_free_array_dma); 5990 if (!ioc->reply_post_free_array) 5991 return -EAGAIN; 5992 if (!mpt3sas_check_same_4gb_region(ioc->reply_post_free_array_dma, 5993 reply_post_free_array_sz)) { 5994 dinitprintk(ioc, pr_err( 5995 "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", 5996 ioc->reply_free, 5997 (unsigned long long) ioc->reply_free_dma)); 5998 ioc->use_32bit_dma = true; 5999 return -EAGAIN; 6000 } 6001 return 0; 6002 } 6003 /** 6004 * base_alloc_rdpq_dma_pool - Allocating DMA'able memory 6005 * for reply queues. 6006 * @ioc: per adapter object 6007 * @sz: DMA Pool size 6008 * Return: 0 for success, non-zero for failure. 6009 */ 6010 static int 6011 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) 6012 { 6013 int i = 0; 6014 u32 dma_alloc_count = 0; 6015 int reply_post_free_sz = ioc->reply_post_queue_depth * 6016 sizeof(Mpi2DefaultReplyDescriptor_t); 6017 int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; 6018 6019 ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct), 6020 GFP_KERNEL); 6021 if (!ioc->reply_post) 6022 return -ENOMEM; 6023 /* 6024 * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and 6025 * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should 6026 * be within 4GB boundary i.e reply queues in a set must have same 6027 * upper 32-bits in their memory address. so here driver is allocating 6028 * the DMA'able memory for reply queues according. 6029 * Driver uses limitation of 6030 * VENTURA_SERIES to manage INVADER_SERIES as well. 6031 */ 6032 dma_alloc_count = DIV_ROUND_UP(count, 6033 RDPQ_MAX_INDEX_IN_ONE_CHUNK); 6034 ioc->reply_post_free_dma_pool = 6035 dma_pool_create("reply_post_free pool", 6036 &ioc->pdev->dev, sz, 16, 0); 6037 if (!ioc->reply_post_free_dma_pool) 6038 return -ENOMEM; 6039 for (i = 0; i < count; i++) { 6040 if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { 6041 ioc->reply_post[i].reply_post_free = 6042 dma_pool_zalloc(ioc->reply_post_free_dma_pool, 6043 GFP_KERNEL, 6044 &ioc->reply_post[i].reply_post_free_dma); 6045 if (!ioc->reply_post[i].reply_post_free) 6046 return -ENOMEM; 6047 /* 6048 * Each set of RDPQ pool must satisfy 4gb boundary 6049 * restriction. 6050 * 1) Check if allocated resources for RDPQ pool are in 6051 * the same 4GB range. 6052 * 2) If #1 is true, continue with 64 bit DMA. 6053 * 3) If #1 is false, return 1. which means free all the 6054 * resources and set DMA mask to 32 and allocate. 6055 */ 6056 if (!mpt3sas_check_same_4gb_region( 6057 ioc->reply_post[i].reply_post_free_dma, sz)) { 6058 dinitprintk(ioc, 6059 ioc_err(ioc, "bad Replypost free pool(0x%p)" 6060 "reply_post_free_dma = (0x%llx)\n", 6061 ioc->reply_post[i].reply_post_free, 6062 (unsigned long long) 6063 ioc->reply_post[i].reply_post_free_dma)); 6064 return -EAGAIN; 6065 } 6066 dma_alloc_count--; 6067 6068 } else { 6069 ioc->reply_post[i].reply_post_free = 6070 (Mpi2ReplyDescriptorsUnion_t *) 6071 ((long)ioc->reply_post[i-1].reply_post_free 6072 + reply_post_free_sz); 6073 ioc->reply_post[i].reply_post_free_dma = 6074 (dma_addr_t) 6075 (ioc->reply_post[i-1].reply_post_free_dma + 6076 reply_post_free_sz); 6077 } 6078 } 6079 return 0; 6080 } 6081 6082 /** 6083 * _base_allocate_memory_pools - allocate start of day memory pools 6084 * @ioc: per adapter object 6085 * 6086 * Return: 0 success, anything else error. 6087 */ 6088 static int 6089 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) 6090 { 6091 struct mpt3sas_facts *facts; 6092 u16 max_sge_elements; 6093 u16 chains_needed_per_io; 6094 u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; 6095 u32 retry_sz; 6096 u32 rdpq_sz = 0, sense_sz = 0; 6097 u16 max_request_credit, nvme_blocks_needed; 6098 unsigned short sg_tablesize; 6099 u16 sge_size; 6100 int i; 6101 int ret = 0, rc = 0; 6102 6103 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 6104 6105 6106 retry_sz = 0; 6107 facts = &ioc->facts; 6108 6109 /* command line tunables for max sgl entries */ 6110 if (max_sgl_entries != -1) 6111 sg_tablesize = max_sgl_entries; 6112 else { 6113 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 6114 sg_tablesize = MPT2SAS_SG_DEPTH; 6115 else 6116 sg_tablesize = MPT3SAS_SG_DEPTH; 6117 } 6118 6119 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ 6120 if (reset_devices) 6121 sg_tablesize = min_t(unsigned short, sg_tablesize, 6122 MPT_KDUMP_MIN_PHYS_SEGMENTS); 6123 6124 if (ioc->is_mcpu_endpoint) 6125 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 6126 else { 6127 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 6128 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 6129 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 6130 sg_tablesize = min_t(unsigned short, sg_tablesize, 6131 SG_MAX_SEGMENTS); 6132 ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n", 6133 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 6134 } 6135 ioc->shost->sg_tablesize = sg_tablesize; 6136 } 6137 6138 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), 6139 (facts->RequestCredit / 4)); 6140 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { 6141 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + 6142 INTERNAL_SCSIIO_CMDS_COUNT)) { 6143 ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n", 6144 facts->RequestCredit); 6145 return -ENOMEM; 6146 } 6147 ioc->internal_depth = 10; 6148 } 6149 6150 ioc->hi_priority_depth = ioc->internal_depth - (5); 6151 /* command line tunables for max controller queue depth */ 6152 if (max_queue_depth != -1 && max_queue_depth != 0) { 6153 max_request_credit = min_t(u16, max_queue_depth + 6154 ioc->internal_depth, facts->RequestCredit); 6155 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 6156 max_request_credit = MAX_HBA_QUEUE_DEPTH; 6157 } else if (reset_devices) 6158 max_request_credit = min_t(u16, facts->RequestCredit, 6159 (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); 6160 else 6161 max_request_credit = min_t(u16, facts->RequestCredit, 6162 MAX_HBA_QUEUE_DEPTH); 6163 6164 /* Firmware maintains additional facts->HighPriorityCredit number of 6165 * credits for HiPriprity Request messages, so hba queue depth will be 6166 * sum of max_request_credit and high priority queue depth. 6167 */ 6168 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; 6169 6170 /* request frame size */ 6171 ioc->request_sz = facts->IOCRequestFrameSize * 4; 6172 6173 /* reply frame size */ 6174 ioc->reply_sz = facts->ReplyFrameSize * 4; 6175 6176 /* chain segment size */ 6177 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 6178 if (facts->IOCMaxChainSegmentSize) 6179 ioc->chain_segment_sz = 6180 facts->IOCMaxChainSegmentSize * 6181 MAX_CHAIN_ELEMT_SZ; 6182 else 6183 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ 6184 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * 6185 MAX_CHAIN_ELEMT_SZ; 6186 } else 6187 ioc->chain_segment_sz = ioc->request_sz; 6188 6189 /* calculate the max scatter element size */ 6190 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 6191 6192 retry_allocation: 6193 total_sz = 0; 6194 /* calculate number of sg elements left over in the 1st frame */ 6195 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 6196 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 6197 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 6198 6199 /* now do the same for a chain buffer */ 6200 max_sge_elements = ioc->chain_segment_sz - sge_size; 6201 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 6202 6203 /* 6204 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 6205 */ 6206 chains_needed_per_io = ((ioc->shost->sg_tablesize - 6207 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 6208 + 1; 6209 if (chains_needed_per_io > facts->MaxChainDepth) { 6210 chains_needed_per_io = facts->MaxChainDepth; 6211 ioc->shost->sg_tablesize = min_t(u16, 6212 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 6213 * chains_needed_per_io), ioc->shost->sg_tablesize); 6214 } 6215 ioc->chains_needed_per_io = chains_needed_per_io; 6216 6217 /* reply free queue sizing - taking into account for 64 FW events */ 6218 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 6219 6220 /* mCPU manage single counters for simplicity */ 6221 if (ioc->is_mcpu_endpoint) 6222 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth; 6223 else { 6224 /* calculate reply descriptor post queue depth */ 6225 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 6226 ioc->reply_free_queue_depth + 1; 6227 /* align the reply post queue on the next 16 count boundary */ 6228 if (ioc->reply_post_queue_depth % 16) 6229 ioc->reply_post_queue_depth += 16 - 6230 (ioc->reply_post_queue_depth % 16); 6231 } 6232 6233 if (ioc->reply_post_queue_depth > 6234 facts->MaxReplyDescriptorPostQueueDepth) { 6235 ioc->reply_post_queue_depth = 6236 facts->MaxReplyDescriptorPostQueueDepth - 6237 (facts->MaxReplyDescriptorPostQueueDepth % 16); 6238 ioc->hba_queue_depth = 6239 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 6240 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 6241 } 6242 6243 ioc_info(ioc, 6244 "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), " 6245 "sge_per_io(%d), chains_per_io(%d)\n", 6246 ioc->max_sges_in_main_message, 6247 ioc->max_sges_in_chain_message, 6248 ioc->shost->sg_tablesize, 6249 ioc->chains_needed_per_io); 6250 6251 /* reply post queue, 16 byte align */ 6252 reply_post_free_sz = ioc->reply_post_queue_depth * 6253 sizeof(Mpi2DefaultReplyDescriptor_t); 6254 rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; 6255 if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 6256 || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK)) 6257 rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; 6258 ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz); 6259 if (ret == -EAGAIN) { 6260 /* 6261 * Free allocated bad RDPQ memory pools. 6262 * Change dma coherent mask to 32 bit and reallocate RDPQ 6263 */ 6264 _base_release_memory_pools(ioc); 6265 ioc->use_32bit_dma = true; 6266 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { 6267 ioc_err(ioc, 6268 "32 DMA mask failed %s\n", pci_name(ioc->pdev)); 6269 return -ENODEV; 6270 } 6271 if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) 6272 return -ENOMEM; 6273 } else if (ret == -ENOMEM) 6274 return -ENOMEM; 6275 total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 : 6276 DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK)); 6277 ioc->scsiio_depth = ioc->hba_queue_depth - 6278 ioc->hi_priority_depth - ioc->internal_depth; 6279 6280 /* set the scsi host can_queue depth 6281 * with some internal commands that could be outstanding 6282 */ 6283 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; 6284 dinitprintk(ioc, 6285 ioc_info(ioc, "scsi host: can_queue depth (%d)\n", 6286 ioc->shost->can_queue)); 6287 6288 /* contiguous pool for request and chains, 16 byte align, one extra " 6289 * "frame for smid=0 6290 */ 6291 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 6292 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 6293 6294 /* hi-priority queue */ 6295 sz += (ioc->hi_priority_depth * ioc->request_sz); 6296 6297 /* internal queue */ 6298 sz += (ioc->internal_depth * ioc->request_sz); 6299 6300 ioc->request_dma_sz = sz; 6301 ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz, 6302 &ioc->request_dma, GFP_KERNEL); 6303 if (!ioc->request) { 6304 ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n", 6305 ioc->hba_queue_depth, ioc->chains_needed_per_io, 6306 ioc->request_sz, sz / 1024); 6307 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 6308 goto out; 6309 retry_sz = 64; 6310 ioc->hba_queue_depth -= retry_sz; 6311 _base_release_memory_pools(ioc); 6312 goto retry_allocation; 6313 } 6314 6315 if (retry_sz) 6316 ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n", 6317 ioc->hba_queue_depth, ioc->chains_needed_per_io, 6318 ioc->request_sz, sz / 1024); 6319 6320 /* hi-priority queue */ 6321 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 6322 ioc->request_sz); 6323 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 6324 ioc->request_sz); 6325 6326 /* internal queue */ 6327 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 6328 ioc->request_sz); 6329 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 6330 ioc->request_sz); 6331 6332 ioc_info(ioc, 6333 "request pool(0x%p) - dma(0x%llx): " 6334 "depth(%d), frame_size(%d), pool_size(%d kB)\n", 6335 ioc->request, (unsigned long long) ioc->request_dma, 6336 ioc->hba_queue_depth, ioc->request_sz, 6337 (ioc->hba_queue_depth * ioc->request_sz) / 1024); 6338 6339 total_sz += sz; 6340 6341 dinitprintk(ioc, 6342 ioc_info(ioc, "scsiio(0x%p): depth(%d)\n", 6343 ioc->request, ioc->scsiio_depth)); 6344 6345 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 6346 sz = ioc->scsiio_depth * sizeof(struct chain_lookup); 6347 ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); 6348 if (!ioc->chain_lookup) { 6349 ioc_err(ioc, "chain_lookup: __get_free_pages failed\n"); 6350 goto out; 6351 } 6352 6353 sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker); 6354 for (i = 0; i < ioc->scsiio_depth; i++) { 6355 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL); 6356 if (!ioc->chain_lookup[i].chains_per_smid) { 6357 ioc_err(ioc, "chain_lookup: kzalloc failed\n"); 6358 goto out; 6359 } 6360 } 6361 6362 /* initialize hi-priority queue smid's */ 6363 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 6364 sizeof(struct request_tracker), GFP_KERNEL); 6365 if (!ioc->hpr_lookup) { 6366 ioc_err(ioc, "hpr_lookup: kcalloc failed\n"); 6367 goto out; 6368 } 6369 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 6370 dinitprintk(ioc, 6371 ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n", 6372 ioc->hi_priority, 6373 ioc->hi_priority_depth, ioc->hi_priority_smid)); 6374 6375 /* initialize internal queue smid's */ 6376 ioc->internal_lookup = kcalloc(ioc->internal_depth, 6377 sizeof(struct request_tracker), GFP_KERNEL); 6378 if (!ioc->internal_lookup) { 6379 ioc_err(ioc, "internal_lookup: kcalloc failed\n"); 6380 goto out; 6381 } 6382 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 6383 dinitprintk(ioc, 6384 ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n", 6385 ioc->internal, 6386 ioc->internal_depth, ioc->internal_smid)); 6387 6388 ioc->io_queue_num = kcalloc(ioc->scsiio_depth, 6389 sizeof(u16), GFP_KERNEL); 6390 if (!ioc->io_queue_num) 6391 goto out; 6392 /* 6393 * The number of NVMe page sized blocks needed is: 6394 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 6395 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry 6396 * that is placed in the main message frame. 8 is the size of each PRP 6397 * entry or PRP list pointer entry. 8 is subtracted from page_size 6398 * because of the PRP list pointer entry at the end of a page, so this 6399 * is not counted as a PRP entry. The 1 added page is a round up. 6400 * 6401 * To avoid allocation failures due to the amount of memory that could 6402 * be required for NVMe PRP's, only each set of NVMe blocks will be 6403 * contiguous, so a new set is allocated for each possible I/O. 6404 */ 6405 6406 ioc->chains_per_prp_buffer = 0; 6407 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 6408 nvme_blocks_needed = 6409 (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; 6410 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); 6411 nvme_blocks_needed++; 6412 6413 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth; 6414 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL); 6415 if (!ioc->pcie_sg_lookup) { 6416 ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n"); 6417 goto out; 6418 } 6419 sz = nvme_blocks_needed * ioc->page_size; 6420 rc = _base_allocate_pcie_sgl_pool(ioc, sz); 6421 if (rc == -ENOMEM) 6422 return -ENOMEM; 6423 else if (rc == -EAGAIN) 6424 goto try_32bit_dma; 6425 total_sz += sz * ioc->scsiio_depth; 6426 } 6427 6428 rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz); 6429 if (rc == -ENOMEM) 6430 return -ENOMEM; 6431 else if (rc == -EAGAIN) 6432 goto try_32bit_dma; 6433 total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io - 6434 ioc->chains_per_prp_buffer) * ioc->scsiio_depth); 6435 dinitprintk(ioc, 6436 ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 6437 ioc->chain_depth, ioc->chain_segment_sz, 6438 (ioc->chain_depth * ioc->chain_segment_sz) / 1024)); 6439 /* sense buffers, 4 byte align */ 6440 sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 6441 rc = _base_allocate_sense_dma_pool(ioc, sense_sz); 6442 if (rc == -ENOMEM) 6443 return -ENOMEM; 6444 else if (rc == -EAGAIN) 6445 goto try_32bit_dma; 6446 total_sz += sense_sz; 6447 ioc_info(ioc, 6448 "sense pool(0x%p)- dma(0x%llx): depth(%d)," 6449 "element_size(%d), pool_size(%d kB)\n", 6450 ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth, 6451 SCSI_SENSE_BUFFERSIZE, sz / 1024); 6452 /* reply pool, 4 byte align */ 6453 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 6454 rc = _base_allocate_reply_pool(ioc, sz); 6455 if (rc == -ENOMEM) 6456 return -ENOMEM; 6457 else if (rc == -EAGAIN) 6458 goto try_32bit_dma; 6459 total_sz += sz; 6460 6461 /* reply free queue, 16 byte align */ 6462 sz = ioc->reply_free_queue_depth * 4; 6463 rc = _base_allocate_reply_free_dma_pool(ioc, sz); 6464 if (rc == -ENOMEM) 6465 return -ENOMEM; 6466 else if (rc == -EAGAIN) 6467 goto try_32bit_dma; 6468 dinitprintk(ioc, 6469 ioc_info(ioc, "reply_free_dma (0x%llx)\n", 6470 (unsigned long long)ioc->reply_free_dma)); 6471 total_sz += sz; 6472 if (ioc->rdpq_array_enable) { 6473 reply_post_free_array_sz = ioc->reply_queue_count * 6474 sizeof(Mpi2IOCInitRDPQArrayEntry); 6475 rc = _base_allocate_reply_post_free_array(ioc, 6476 reply_post_free_array_sz); 6477 if (rc == -ENOMEM) 6478 return -ENOMEM; 6479 else if (rc == -EAGAIN) 6480 goto try_32bit_dma; 6481 } 6482 ioc->config_page_sz = 512; 6483 ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev, 6484 ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL); 6485 if (!ioc->config_page) { 6486 ioc_err(ioc, "config page: dma_pool_alloc failed\n"); 6487 goto out; 6488 } 6489 6490 ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n", 6491 ioc->config_page, (unsigned long long)ioc->config_page_dma, 6492 ioc->config_page_sz); 6493 total_sz += ioc->config_page_sz; 6494 6495 ioc_info(ioc, "Allocated physical memory: size(%d kB)\n", 6496 total_sz / 1024); 6497 ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 6498 ioc->shost->can_queue, facts->RequestCredit); 6499 ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n", 6500 ioc->shost->sg_tablesize); 6501 return 0; 6502 6503 try_32bit_dma: 6504 _base_release_memory_pools(ioc); 6505 if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) { 6506 /* Change dma coherent mask to 32 bit and reallocate */ 6507 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { 6508 pr_err("Setting 32 bit coherent DMA mask Failed %s\n", 6509 pci_name(ioc->pdev)); 6510 return -ENODEV; 6511 } 6512 } else if (_base_reduce_hba_queue_depth(ioc) != 0) 6513 return -ENOMEM; 6514 goto retry_allocation; 6515 6516 out: 6517 return -ENOMEM; 6518 } 6519 6520 /** 6521 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 6522 * @ioc: Pointer to MPT_ADAPTER structure 6523 * @cooked: Request raw or cooked IOC state 6524 * 6525 * Return: all IOC Doorbell register bits if cooked==0, else just the 6526 * Doorbell bits in MPI_IOC_STATE_MASK. 6527 */ 6528 u32 6529 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 6530 { 6531 u32 s, sc; 6532 6533 s = ioc->base_readl(&ioc->chip->Doorbell); 6534 sc = s & MPI2_IOC_STATE_MASK; 6535 return cooked ? sc : s; 6536 } 6537 6538 /** 6539 * _base_wait_on_iocstate - waiting on a particular ioc state 6540 * @ioc: ? 6541 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 6542 * @timeout: timeout in second 6543 * 6544 * Return: 0 for success, non-zero for failure. 6545 */ 6546 static int 6547 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) 6548 { 6549 u32 count, cntdn; 6550 u32 current_state; 6551 6552 count = 0; 6553 cntdn = 1000 * timeout; 6554 do { 6555 current_state = mpt3sas_base_get_iocstate(ioc, 1); 6556 if (current_state == ioc_state) 6557 return 0; 6558 if (count && current_state == MPI2_IOC_STATE_FAULT) 6559 break; 6560 if (count && current_state == MPI2_IOC_STATE_COREDUMP) 6561 break; 6562 6563 usleep_range(1000, 1500); 6564 count++; 6565 } while (--cntdn); 6566 6567 return current_state; 6568 } 6569 6570 /** 6571 * _base_dump_reg_set - This function will print hexdump of register set. 6572 * @ioc: per adapter object 6573 * 6574 * Return: nothing. 6575 */ 6576 static inline void 6577 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc) 6578 { 6579 unsigned int i, sz = 256; 6580 u32 __iomem *reg = (u32 __iomem *)ioc->chip; 6581 6582 ioc_info(ioc, "System Register set:\n"); 6583 for (i = 0; i < (sz / sizeof(u32)); i++) 6584 pr_info("%08x: %08x\n", (i * 4), readl(®[i])); 6585 } 6586 6587 /** 6588 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 6589 * a write to the doorbell) 6590 * @ioc: per adapter object 6591 * @timeout: timeout in seconds 6592 * 6593 * Return: 0 for success, non-zero for failure. 6594 * 6595 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 6596 */ 6597 6598 static int 6599 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 6600 { 6601 u32 cntdn, count; 6602 u32 int_status; 6603 6604 count = 0; 6605 cntdn = 1000 * timeout; 6606 do { 6607 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6608 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6609 dhsprintk(ioc, 6610 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6611 __func__, count, timeout)); 6612 return 0; 6613 } 6614 6615 usleep_range(1000, 1500); 6616 count++; 6617 } while (--cntdn); 6618 6619 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6620 __func__, count, int_status); 6621 return -EFAULT; 6622 } 6623 6624 static int 6625 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 6626 { 6627 u32 cntdn, count; 6628 u32 int_status; 6629 6630 count = 0; 6631 cntdn = 2000 * timeout; 6632 do { 6633 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6634 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6635 dhsprintk(ioc, 6636 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6637 __func__, count, timeout)); 6638 return 0; 6639 } 6640 6641 udelay(500); 6642 count++; 6643 } while (--cntdn); 6644 6645 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6646 __func__, count, int_status); 6647 return -EFAULT; 6648 6649 } 6650 6651 /** 6652 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 6653 * @ioc: per adapter object 6654 * @timeout: timeout in second 6655 * 6656 * Return: 0 for success, non-zero for failure. 6657 * 6658 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 6659 * doorbell. 6660 */ 6661 static int 6662 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) 6663 { 6664 u32 cntdn, count; 6665 u32 int_status; 6666 u32 doorbell; 6667 6668 count = 0; 6669 cntdn = 1000 * timeout; 6670 do { 6671 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); 6672 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 6673 dhsprintk(ioc, 6674 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6675 __func__, count, timeout)); 6676 return 0; 6677 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 6678 doorbell = ioc->base_readl(&ioc->chip->Doorbell); 6679 if ((doorbell & MPI2_IOC_STATE_MASK) == 6680 MPI2_IOC_STATE_FAULT) { 6681 mpt3sas_print_fault_code(ioc, doorbell); 6682 return -EFAULT; 6683 } 6684 if ((doorbell & MPI2_IOC_STATE_MASK) == 6685 MPI2_IOC_STATE_COREDUMP) { 6686 mpt3sas_print_coredump_info(ioc, doorbell); 6687 return -EFAULT; 6688 } 6689 } else if (int_status == 0xFFFFFFFF) 6690 goto out; 6691 6692 usleep_range(1000, 1500); 6693 count++; 6694 } while (--cntdn); 6695 6696 out: 6697 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", 6698 __func__, count, int_status); 6699 return -EFAULT; 6700 } 6701 6702 /** 6703 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 6704 * @ioc: per adapter object 6705 * @timeout: timeout in second 6706 * 6707 * Return: 0 for success, non-zero for failure. 6708 */ 6709 static int 6710 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) 6711 { 6712 u32 cntdn, count; 6713 u32 doorbell_reg; 6714 6715 count = 0; 6716 cntdn = 1000 * timeout; 6717 do { 6718 doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell); 6719 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 6720 dhsprintk(ioc, 6721 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", 6722 __func__, count, timeout)); 6723 return 0; 6724 } 6725 6726 usleep_range(1000, 1500); 6727 count++; 6728 } while (--cntdn); 6729 6730 ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 6731 __func__, count, doorbell_reg); 6732 return -EFAULT; 6733 } 6734 6735 /** 6736 * _base_send_ioc_reset - send doorbell reset 6737 * @ioc: per adapter object 6738 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 6739 * @timeout: timeout in second 6740 * 6741 * Return: 0 for success, non-zero for failure. 6742 */ 6743 static int 6744 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) 6745 { 6746 u32 ioc_state; 6747 int r = 0; 6748 unsigned long flags; 6749 6750 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 6751 ioc_err(ioc, "%s: unknown reset_type\n", __func__); 6752 return -EFAULT; 6753 } 6754 6755 if (!(ioc->facts.IOCCapabilities & 6756 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 6757 return -EFAULT; 6758 6759 ioc_info(ioc, "sending message unit reset !!\n"); 6760 6761 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 6762 &ioc->chip->Doorbell); 6763 if ((_base_wait_for_doorbell_ack(ioc, 15))) { 6764 r = -EFAULT; 6765 goto out; 6766 } 6767 6768 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 6769 if (ioc_state) { 6770 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 6771 __func__, ioc_state); 6772 r = -EFAULT; 6773 goto out; 6774 } 6775 out: 6776 if (r != 0) { 6777 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6778 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 6779 /* 6780 * Wait for IOC state CoreDump to clear only during 6781 * HBA initialization & release time. 6782 */ 6783 if ((ioc_state & MPI2_IOC_STATE_MASK) == 6784 MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 || 6785 ioc->fault_reset_work_q == NULL)) { 6786 spin_unlock_irqrestore( 6787 &ioc->ioc_reset_in_progress_lock, flags); 6788 mpt3sas_print_coredump_info(ioc, ioc_state); 6789 mpt3sas_base_wait_for_coredump_completion(ioc, 6790 __func__); 6791 spin_lock_irqsave( 6792 &ioc->ioc_reset_in_progress_lock, flags); 6793 } 6794 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 6795 } 6796 ioc_info(ioc, "message unit reset: %s\n", 6797 r == 0 ? "SUCCESS" : "FAILED"); 6798 return r; 6799 } 6800 6801 /** 6802 * mpt3sas_wait_for_ioc - IOC's operational state is checked here. 6803 * @ioc: per adapter object 6804 * @timeout: timeout in seconds 6805 * 6806 * Return: Waits up to timeout seconds for the IOC to 6807 * become operational. Returns 0 if IOC is present 6808 * and operational; otherwise returns %-EFAULT. 6809 */ 6810 6811 int 6812 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout) 6813 { 6814 int wait_state_count = 0; 6815 u32 ioc_state; 6816 6817 do { 6818 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 6819 if (ioc_state == MPI2_IOC_STATE_OPERATIONAL) 6820 break; 6821 6822 /* 6823 * Watchdog thread will be started after IOC Initialization, so 6824 * no need to wait here for IOC state to become operational 6825 * when IOC Initialization is on. Instead the driver will 6826 * return ETIME status, so that calling function can issue 6827 * diag reset operation and retry the command. 6828 */ 6829 if (ioc->is_driver_loading) 6830 return -ETIME; 6831 6832 ssleep(1); 6833 ioc_info(ioc, "%s: waiting for operational state(count=%d)\n", 6834 __func__, ++wait_state_count); 6835 } while (--timeout); 6836 if (!timeout) { 6837 ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__); 6838 return -EFAULT; 6839 } 6840 if (wait_state_count) 6841 ioc_info(ioc, "ioc is operational\n"); 6842 return 0; 6843 } 6844 6845 /** 6846 * _base_handshake_req_reply_wait - send request thru doorbell interface 6847 * @ioc: per adapter object 6848 * @request_bytes: request length 6849 * @request: pointer having request payload 6850 * @reply_bytes: reply length 6851 * @reply: pointer to reply payload 6852 * @timeout: timeout in second 6853 * 6854 * Return: 0 for success, non-zero for failure. 6855 */ 6856 static int 6857 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 6858 u32 *request, int reply_bytes, u16 *reply, int timeout) 6859 { 6860 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 6861 int i; 6862 u8 failed; 6863 __le32 *mfp; 6864 6865 /* make sure doorbell is not in use */ 6866 if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 6867 ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__); 6868 return -EFAULT; 6869 } 6870 6871 /* clear pending doorbell interrupts from previous state changes */ 6872 if (ioc->base_readl(&ioc->chip->HostInterruptStatus) & 6873 MPI2_HIS_IOC2SYS_DB_STATUS) 6874 writel(0, &ioc->chip->HostInterruptStatus); 6875 6876 /* send message to ioc */ 6877 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 6878 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 6879 &ioc->chip->Doorbell); 6880 6881 if ((_base_spin_on_doorbell_int(ioc, 5))) { 6882 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 6883 __LINE__); 6884 return -EFAULT; 6885 } 6886 writel(0, &ioc->chip->HostInterruptStatus); 6887 6888 if ((_base_wait_for_doorbell_ack(ioc, 5))) { 6889 ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n", 6890 __LINE__); 6891 return -EFAULT; 6892 } 6893 6894 /* send message 32-bits at a time */ 6895 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 6896 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 6897 if ((_base_wait_for_doorbell_ack(ioc, 5))) 6898 failed = 1; 6899 } 6900 6901 if (failed) { 6902 ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n", 6903 __LINE__); 6904 return -EFAULT; 6905 } 6906 6907 /* now wait for the reply */ 6908 if ((_base_wait_for_doorbell_int(ioc, timeout))) { 6909 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 6910 __LINE__); 6911 return -EFAULT; 6912 } 6913 6914 /* read the first two 16-bits, it gives the total length of the reply */ 6915 reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell) 6916 & MPI2_DOORBELL_DATA_MASK); 6917 writel(0, &ioc->chip->HostInterruptStatus); 6918 if ((_base_wait_for_doorbell_int(ioc, 5))) { 6919 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 6920 __LINE__); 6921 return -EFAULT; 6922 } 6923 reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell) 6924 & MPI2_DOORBELL_DATA_MASK); 6925 writel(0, &ioc->chip->HostInterruptStatus); 6926 6927 for (i = 2; i < default_reply->MsgLength * 2; i++) { 6928 if ((_base_wait_for_doorbell_int(ioc, 5))) { 6929 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", 6930 __LINE__); 6931 return -EFAULT; 6932 } 6933 if (i >= reply_bytes/2) /* overflow case */ 6934 ioc->base_readl(&ioc->chip->Doorbell); 6935 else 6936 reply[i] = le16_to_cpu( 6937 ioc->base_readl(&ioc->chip->Doorbell) 6938 & MPI2_DOORBELL_DATA_MASK); 6939 writel(0, &ioc->chip->HostInterruptStatus); 6940 } 6941 6942 _base_wait_for_doorbell_int(ioc, 5); 6943 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { 6944 dhsprintk(ioc, 6945 ioc_info(ioc, "doorbell is in use (line=%d)\n", 6946 __LINE__)); 6947 } 6948 writel(0, &ioc->chip->HostInterruptStatus); 6949 6950 if (ioc->logging_level & MPT_DEBUG_INIT) { 6951 mfp = (__le32 *)reply; 6952 pr_info("\toffset:data\n"); 6953 for (i = 0; i < reply_bytes/4; i++) 6954 ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, 6955 le32_to_cpu(mfp[i])); 6956 } 6957 return 0; 6958 } 6959 6960 /** 6961 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 6962 * @ioc: per adapter object 6963 * @mpi_reply: the reply payload from FW 6964 * @mpi_request: the request payload sent to FW 6965 * 6966 * The SAS IO Unit Control Request message allows the host to perform low-level 6967 * operations, such as resets on the PHYs of the IO Unit, also allows the host 6968 * to obtain the IOC assigned device handles for a device if it has other 6969 * identifying information about the device, in addition allows the host to 6970 * remove IOC resources associated with the device. 6971 * 6972 * Return: 0 for success, non-zero for failure. 6973 */ 6974 int 6975 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 6976 Mpi2SasIoUnitControlReply_t *mpi_reply, 6977 Mpi2SasIoUnitControlRequest_t *mpi_request) 6978 { 6979 u16 smid; 6980 u8 issue_reset = 0; 6981 int rc; 6982 void *request; 6983 6984 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 6985 6986 mutex_lock(&ioc->base_cmds.mutex); 6987 6988 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 6989 ioc_err(ioc, "%s: base_cmd in use\n", __func__); 6990 rc = -EAGAIN; 6991 goto out; 6992 } 6993 6994 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); 6995 if (rc) 6996 goto out; 6997 6998 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 6999 if (!smid) { 7000 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7001 rc = -EAGAIN; 7002 goto out; 7003 } 7004 7005 rc = 0; 7006 ioc->base_cmds.status = MPT3_CMD_PENDING; 7007 request = mpt3sas_base_get_msg_frame(ioc, smid); 7008 ioc->base_cmds.smid = smid; 7009 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 7010 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 7011 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 7012 ioc->ioc_link_reset_in_progress = 1; 7013 init_completion(&ioc->base_cmds.done); 7014 ioc->put_smid_default(ioc, smid); 7015 wait_for_completion_timeout(&ioc->base_cmds.done, 7016 msecs_to_jiffies(10000)); 7017 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 7018 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 7019 ioc->ioc_link_reset_in_progress) 7020 ioc->ioc_link_reset_in_progress = 0; 7021 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7022 mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status, 7023 mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4, 7024 issue_reset); 7025 goto issue_host_reset; 7026 } 7027 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 7028 memcpy(mpi_reply, ioc->base_cmds.reply, 7029 sizeof(Mpi2SasIoUnitControlReply_t)); 7030 else 7031 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 7032 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7033 goto out; 7034 7035 issue_host_reset: 7036 if (issue_reset) 7037 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 7038 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7039 rc = -EFAULT; 7040 out: 7041 mutex_unlock(&ioc->base_cmds.mutex); 7042 return rc; 7043 } 7044 7045 /** 7046 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 7047 * @ioc: per adapter object 7048 * @mpi_reply: the reply payload from FW 7049 * @mpi_request: the request payload sent to FW 7050 * 7051 * The SCSI Enclosure Processor request message causes the IOC to 7052 * communicate with SES devices to control LED status signals. 7053 * 7054 * Return: 0 for success, non-zero for failure. 7055 */ 7056 int 7057 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 7058 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 7059 { 7060 u16 smid; 7061 u8 issue_reset = 0; 7062 int rc; 7063 void *request; 7064 7065 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7066 7067 mutex_lock(&ioc->base_cmds.mutex); 7068 7069 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 7070 ioc_err(ioc, "%s: base_cmd in use\n", __func__); 7071 rc = -EAGAIN; 7072 goto out; 7073 } 7074 7075 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); 7076 if (rc) 7077 goto out; 7078 7079 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 7080 if (!smid) { 7081 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7082 rc = -EAGAIN; 7083 goto out; 7084 } 7085 7086 rc = 0; 7087 ioc->base_cmds.status = MPT3_CMD_PENDING; 7088 request = mpt3sas_base_get_msg_frame(ioc, smid); 7089 ioc->base_cmds.smid = smid; 7090 memset(request, 0, ioc->request_sz); 7091 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 7092 init_completion(&ioc->base_cmds.done); 7093 ioc->put_smid_default(ioc, smid); 7094 wait_for_completion_timeout(&ioc->base_cmds.done, 7095 msecs_to_jiffies(10000)); 7096 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7097 mpt3sas_check_cmd_timeout(ioc, 7098 ioc->base_cmds.status, mpi_request, 7099 sizeof(Mpi2SepRequest_t)/4, issue_reset); 7100 goto issue_host_reset; 7101 } 7102 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 7103 memcpy(mpi_reply, ioc->base_cmds.reply, 7104 sizeof(Mpi2SepReply_t)); 7105 else 7106 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 7107 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7108 goto out; 7109 7110 issue_host_reset: 7111 if (issue_reset) 7112 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 7113 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7114 rc = -EFAULT; 7115 out: 7116 mutex_unlock(&ioc->base_cmds.mutex); 7117 return rc; 7118 } 7119 7120 /** 7121 * _base_get_port_facts - obtain port facts reply and save in ioc 7122 * @ioc: per adapter object 7123 * @port: ? 7124 * 7125 * Return: 0 for success, non-zero for failure. 7126 */ 7127 static int 7128 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) 7129 { 7130 Mpi2PortFactsRequest_t mpi_request; 7131 Mpi2PortFactsReply_t mpi_reply; 7132 struct mpt3sas_port_facts *pfacts; 7133 int mpi_reply_sz, mpi_request_sz, r; 7134 7135 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7136 7137 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 7138 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 7139 memset(&mpi_request, 0, mpi_request_sz); 7140 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 7141 mpi_request.PortNumber = port; 7142 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 7143 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 7144 7145 if (r != 0) { 7146 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7147 return r; 7148 } 7149 7150 pfacts = &ioc->pfacts[port]; 7151 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 7152 pfacts->PortNumber = mpi_reply.PortNumber; 7153 pfacts->VP_ID = mpi_reply.VP_ID; 7154 pfacts->VF_ID = mpi_reply.VF_ID; 7155 pfacts->MaxPostedCmdBuffers = 7156 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 7157 7158 return 0; 7159 } 7160 7161 /** 7162 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 7163 * @ioc: per adapter object 7164 * @timeout: 7165 * 7166 * Return: 0 for success, non-zero for failure. 7167 */ 7168 static int 7169 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) 7170 { 7171 u32 ioc_state; 7172 int rc; 7173 7174 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7175 7176 if (ioc->pci_error_recovery) { 7177 dfailprintk(ioc, 7178 ioc_info(ioc, "%s: host in pci error recovery\n", 7179 __func__)); 7180 return -EFAULT; 7181 } 7182 7183 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 7184 dhsprintk(ioc, 7185 ioc_info(ioc, "%s: ioc_state(0x%08x)\n", 7186 __func__, ioc_state)); 7187 7188 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 7189 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 7190 return 0; 7191 7192 if (ioc_state & MPI2_DOORBELL_USED) { 7193 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n")); 7194 goto issue_diag_reset; 7195 } 7196 7197 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 7198 mpt3sas_print_fault_code(ioc, ioc_state & 7199 MPI2_DOORBELL_DATA_MASK); 7200 goto issue_diag_reset; 7201 } else if ((ioc_state & MPI2_IOC_STATE_MASK) == 7202 MPI2_IOC_STATE_COREDUMP) { 7203 ioc_info(ioc, 7204 "%s: Skipping the diag reset here. (ioc_state=0x%x)\n", 7205 __func__, ioc_state); 7206 return -EFAULT; 7207 } 7208 7209 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 7210 if (ioc_state) { 7211 dfailprintk(ioc, 7212 ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 7213 __func__, ioc_state)); 7214 return -EFAULT; 7215 } 7216 7217 issue_diag_reset: 7218 rc = _base_diag_reset(ioc); 7219 return rc; 7220 } 7221 7222 /** 7223 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 7224 * @ioc: per adapter object 7225 * 7226 * Return: 0 for success, non-zero for failure. 7227 */ 7228 static int 7229 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 7230 { 7231 Mpi2IOCFactsRequest_t mpi_request; 7232 Mpi2IOCFactsReply_t mpi_reply; 7233 struct mpt3sas_facts *facts; 7234 int mpi_reply_sz, mpi_request_sz, r; 7235 7236 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7237 7238 r = _base_wait_for_iocstate(ioc, 10); 7239 if (r) { 7240 dfailprintk(ioc, 7241 ioc_info(ioc, "%s: failed getting to correct state\n", 7242 __func__)); 7243 return r; 7244 } 7245 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 7246 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 7247 memset(&mpi_request, 0, mpi_request_sz); 7248 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 7249 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 7250 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 7251 7252 if (r != 0) { 7253 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7254 return r; 7255 } 7256 7257 facts = &ioc->facts; 7258 memset(facts, 0, sizeof(struct mpt3sas_facts)); 7259 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 7260 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 7261 facts->VP_ID = mpi_reply.VP_ID; 7262 facts->VF_ID = mpi_reply.VF_ID; 7263 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 7264 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 7265 facts->WhoInit = mpi_reply.WhoInit; 7266 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 7267 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 7268 if (ioc->msix_enable && (facts->MaxMSIxVectors <= 7269 MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) 7270 ioc->combined_reply_queue = 0; 7271 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 7272 facts->MaxReplyDescriptorPostQueueDepth = 7273 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 7274 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 7275 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 7276 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 7277 ioc->ir_firmware = 1; 7278 if ((facts->IOCCapabilities & 7279 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) 7280 ioc->rdpq_array_capable = 1; 7281 if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) 7282 && ioc->is_aero_ioc) 7283 ioc->atomic_desc_capable = 1; 7284 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 7285 facts->IOCRequestFrameSize = 7286 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 7287 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 7288 facts->IOCMaxChainSegmentSize = 7289 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); 7290 } 7291 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 7292 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 7293 ioc->shost->max_id = -1; 7294 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 7295 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 7296 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 7297 facts->HighPriorityCredit = 7298 le16_to_cpu(mpi_reply.HighPriorityCredit); 7299 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 7300 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 7301 facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; 7302 7303 /* 7304 * Get the Page Size from IOC Facts. If it's 0, default to 4k. 7305 */ 7306 ioc->page_size = 1 << facts->CurrentHostPageSize; 7307 if (ioc->page_size == 1) { 7308 ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n"); 7309 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; 7310 } 7311 dinitprintk(ioc, 7312 ioc_info(ioc, "CurrentHostPageSize(%d)\n", 7313 facts->CurrentHostPageSize)); 7314 7315 dinitprintk(ioc, 7316 ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n", 7317 facts->RequestCredit, facts->MaxChainDepth)); 7318 dinitprintk(ioc, 7319 ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n", 7320 facts->IOCRequestFrameSize * 4, 7321 facts->ReplyFrameSize * 4)); 7322 return 0; 7323 } 7324 7325 /** 7326 * _base_send_ioc_init - send ioc_init to firmware 7327 * @ioc: per adapter object 7328 * 7329 * Return: 0 for success, non-zero for failure. 7330 */ 7331 static int 7332 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) 7333 { 7334 Mpi2IOCInitRequest_t mpi_request; 7335 Mpi2IOCInitReply_t mpi_reply; 7336 int i, r = 0; 7337 ktime_t current_time; 7338 u16 ioc_status; 7339 u32 reply_post_free_array_sz = 0; 7340 7341 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7342 7343 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 7344 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 7345 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 7346 mpi_request.VF_ID = 0; /* TODO */ 7347 mpi_request.VP_ID = 0; 7348 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 7349 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 7350 mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; 7351 7352 if (_base_is_controller_msix_enabled(ioc)) 7353 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 7354 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 7355 mpi_request.ReplyDescriptorPostQueueDepth = 7356 cpu_to_le16(ioc->reply_post_queue_depth); 7357 mpi_request.ReplyFreeQueueDepth = 7358 cpu_to_le16(ioc->reply_free_queue_depth); 7359 7360 mpi_request.SenseBufferAddressHigh = 7361 cpu_to_le32((u64)ioc->sense_dma >> 32); 7362 mpi_request.SystemReplyAddressHigh = 7363 cpu_to_le32((u64)ioc->reply_dma >> 32); 7364 mpi_request.SystemRequestFrameBaseAddress = 7365 cpu_to_le64((u64)ioc->request_dma); 7366 mpi_request.ReplyFreeQueueAddress = 7367 cpu_to_le64((u64)ioc->reply_free_dma); 7368 7369 if (ioc->rdpq_array_enable) { 7370 reply_post_free_array_sz = ioc->reply_queue_count * 7371 sizeof(Mpi2IOCInitRDPQArrayEntry); 7372 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz); 7373 for (i = 0; i < ioc->reply_queue_count; i++) 7374 ioc->reply_post_free_array[i].RDPQBaseAddress = 7375 cpu_to_le64( 7376 (u64)ioc->reply_post[i].reply_post_free_dma); 7377 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 7378 mpi_request.ReplyDescriptorPostQueueAddress = 7379 cpu_to_le64((u64)ioc->reply_post_free_array_dma); 7380 } else { 7381 mpi_request.ReplyDescriptorPostQueueAddress = 7382 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 7383 } 7384 7385 /* 7386 * Set the flag to enable CoreDump state feature in IOC firmware. 7387 */ 7388 mpi_request.ConfigurationFlags |= 7389 cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE); 7390 7391 /* This time stamp specifies number of milliseconds 7392 * since epoch ~ midnight January 1, 1970. 7393 */ 7394 current_time = ktime_get_real(); 7395 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); 7396 7397 if (ioc->logging_level & MPT_DEBUG_INIT) { 7398 __le32 *mfp; 7399 int i; 7400 7401 mfp = (__le32 *)&mpi_request; 7402 ioc_info(ioc, "\toffset:data\n"); 7403 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 7404 ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, 7405 le32_to_cpu(mfp[i])); 7406 } 7407 7408 r = _base_handshake_req_reply_wait(ioc, 7409 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 7410 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30); 7411 7412 if (r != 0) { 7413 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); 7414 return r; 7415 } 7416 7417 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 7418 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 7419 mpi_reply.IOCLogInfo) { 7420 ioc_err(ioc, "%s: failed\n", __func__); 7421 r = -EIO; 7422 } 7423 7424 /* Reset TimeSync Counter*/ 7425 ioc->timestamp_update_count = 0; 7426 return r; 7427 } 7428 7429 /** 7430 * mpt3sas_port_enable_done - command completion routine for port enable 7431 * @ioc: per adapter object 7432 * @smid: system request message index 7433 * @msix_index: MSIX table index supplied by the OS 7434 * @reply: reply message frame(lower 32bit addr) 7435 * 7436 * Return: 1 meaning mf should be freed from _base_interrupt 7437 * 0 means the mf is freed from this function. 7438 */ 7439 u8 7440 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 7441 u32 reply) 7442 { 7443 MPI2DefaultReply_t *mpi_reply; 7444 u16 ioc_status; 7445 7446 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 7447 return 1; 7448 7449 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 7450 if (!mpi_reply) 7451 return 1; 7452 7453 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 7454 return 1; 7455 7456 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 7457 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 7458 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 7459 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 7460 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 7461 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 7462 ioc->port_enable_failed = 1; 7463 7464 if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) { 7465 ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC; 7466 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 7467 mpt3sas_port_enable_complete(ioc); 7468 return 1; 7469 } else { 7470 ioc->start_scan_failed = ioc_status; 7471 ioc->start_scan = 0; 7472 return 1; 7473 } 7474 } 7475 complete(&ioc->port_enable_cmds.done); 7476 return 1; 7477 } 7478 7479 /** 7480 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 7481 * @ioc: per adapter object 7482 * 7483 * Return: 0 for success, non-zero for failure. 7484 */ 7485 static int 7486 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) 7487 { 7488 Mpi2PortEnableRequest_t *mpi_request; 7489 Mpi2PortEnableReply_t *mpi_reply; 7490 int r = 0; 7491 u16 smid; 7492 u16 ioc_status; 7493 7494 ioc_info(ioc, "sending port enable !!\n"); 7495 7496 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 7497 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7498 return -EAGAIN; 7499 } 7500 7501 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 7502 if (!smid) { 7503 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7504 return -EAGAIN; 7505 } 7506 7507 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 7508 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7509 ioc->port_enable_cmds.smid = smid; 7510 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 7511 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 7512 7513 init_completion(&ioc->port_enable_cmds.done); 7514 ioc->put_smid_default(ioc, smid); 7515 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); 7516 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 7517 ioc_err(ioc, "%s: timeout\n", __func__); 7518 _debug_dump_mf(mpi_request, 7519 sizeof(Mpi2PortEnableRequest_t)/4); 7520 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 7521 r = -EFAULT; 7522 else 7523 r = -ETIME; 7524 goto out; 7525 } 7526 7527 mpi_reply = ioc->port_enable_cmds.reply; 7528 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 7529 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 7530 ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n", 7531 __func__, ioc_status); 7532 r = -EFAULT; 7533 goto out; 7534 } 7535 7536 out: 7537 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 7538 ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED"); 7539 return r; 7540 } 7541 7542 /** 7543 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 7544 * @ioc: per adapter object 7545 * 7546 * Return: 0 for success, non-zero for failure. 7547 */ 7548 int 7549 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 7550 { 7551 Mpi2PortEnableRequest_t *mpi_request; 7552 u16 smid; 7553 7554 ioc_info(ioc, "sending port enable !!\n"); 7555 7556 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 7557 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7558 return -EAGAIN; 7559 } 7560 7561 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 7562 if (!smid) { 7563 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7564 return -EAGAIN; 7565 } 7566 ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED; 7567 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 7568 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC; 7569 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7570 ioc->port_enable_cmds.smid = smid; 7571 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 7572 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 7573 7574 ioc->put_smid_default(ioc, smid); 7575 return 0; 7576 } 7577 7578 /** 7579 * _base_determine_wait_on_discovery - desposition 7580 * @ioc: per adapter object 7581 * 7582 * Decide whether to wait on discovery to complete. Used to either 7583 * locate boot device, or report volumes ahead of physical devices. 7584 * 7585 * Return: 1 for wait, 0 for don't wait. 7586 */ 7587 static int 7588 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 7589 { 7590 /* We wait for discovery to complete if IR firmware is loaded. 7591 * The sas topology events arrive before PD events, so we need time to 7592 * turn on the bit in ioc->pd_handles to indicate PD 7593 * Also, it maybe required to report Volumes ahead of physical 7594 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 7595 */ 7596 if (ioc->ir_firmware) 7597 return 1; 7598 7599 /* if no Bios, then we don't need to wait */ 7600 if (!ioc->bios_pg3.BiosVersion) 7601 return 0; 7602 7603 /* Bios is present, then we drop down here. 7604 * 7605 * If there any entries in the Bios Page 2, then we wait 7606 * for discovery to complete. 7607 */ 7608 7609 /* Current Boot Device */ 7610 if ((ioc->bios_pg2.CurrentBootDeviceForm & 7611 MPI2_BIOSPAGE2_FORM_MASK) == 7612 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 7613 /* Request Boot Device */ 7614 (ioc->bios_pg2.ReqBootDeviceForm & 7615 MPI2_BIOSPAGE2_FORM_MASK) == 7616 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 7617 /* Alternate Request Boot Device */ 7618 (ioc->bios_pg2.ReqAltBootDeviceForm & 7619 MPI2_BIOSPAGE2_FORM_MASK) == 7620 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 7621 return 0; 7622 7623 return 1; 7624 } 7625 7626 /** 7627 * _base_unmask_events - turn on notification for this event 7628 * @ioc: per adapter object 7629 * @event: firmware event 7630 * 7631 * The mask is stored in ioc->event_masks. 7632 */ 7633 static void 7634 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 7635 { 7636 u32 desired_event; 7637 7638 if (event >= 128) 7639 return; 7640 7641 desired_event = (1 << (event % 32)); 7642 7643 if (event < 32) 7644 ioc->event_masks[0] &= ~desired_event; 7645 else if (event < 64) 7646 ioc->event_masks[1] &= ~desired_event; 7647 else if (event < 96) 7648 ioc->event_masks[2] &= ~desired_event; 7649 else if (event < 128) 7650 ioc->event_masks[3] &= ~desired_event; 7651 } 7652 7653 /** 7654 * _base_event_notification - send event notification 7655 * @ioc: per adapter object 7656 * 7657 * Return: 0 for success, non-zero for failure. 7658 */ 7659 static int 7660 _base_event_notification(struct MPT3SAS_ADAPTER *ioc) 7661 { 7662 Mpi2EventNotificationRequest_t *mpi_request; 7663 u16 smid; 7664 int r = 0; 7665 int i, issue_diag_reset = 0; 7666 7667 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7668 7669 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 7670 ioc_err(ioc, "%s: internal command already in use\n", __func__); 7671 return -EAGAIN; 7672 } 7673 7674 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 7675 if (!smid) { 7676 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); 7677 return -EAGAIN; 7678 } 7679 ioc->base_cmds.status = MPT3_CMD_PENDING; 7680 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 7681 ioc->base_cmds.smid = smid; 7682 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 7683 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 7684 mpi_request->VF_ID = 0; /* TODO */ 7685 mpi_request->VP_ID = 0; 7686 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 7687 mpi_request->EventMasks[i] = 7688 cpu_to_le32(ioc->event_masks[i]); 7689 init_completion(&ioc->base_cmds.done); 7690 ioc->put_smid_default(ioc, smid); 7691 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 7692 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 7693 ioc_err(ioc, "%s: timeout\n", __func__); 7694 _debug_dump_mf(mpi_request, 7695 sizeof(Mpi2EventNotificationRequest_t)/4); 7696 if (ioc->base_cmds.status & MPT3_CMD_RESET) 7697 r = -EFAULT; 7698 else 7699 issue_diag_reset = 1; 7700 7701 } else 7702 dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__)); 7703 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 7704 7705 if (issue_diag_reset) { 7706 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) 7707 return -EFAULT; 7708 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) 7709 return -EFAULT; 7710 r = -EAGAIN; 7711 } 7712 return r; 7713 } 7714 7715 /** 7716 * mpt3sas_base_validate_event_type - validating event types 7717 * @ioc: per adapter object 7718 * @event_type: firmware event 7719 * 7720 * This will turn on firmware event notification when application 7721 * ask for that event. We don't mask events that are already enabled. 7722 */ 7723 void 7724 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 7725 { 7726 int i, j; 7727 u32 event_mask, desired_event; 7728 u8 send_update_to_fw; 7729 7730 for (i = 0, send_update_to_fw = 0; i < 7731 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 7732 event_mask = ~event_type[i]; 7733 desired_event = 1; 7734 for (j = 0; j < 32; j++) { 7735 if (!(event_mask & desired_event) && 7736 (ioc->event_masks[i] & desired_event)) { 7737 ioc->event_masks[i] &= ~desired_event; 7738 send_update_to_fw = 1; 7739 } 7740 desired_event = (desired_event << 1); 7741 } 7742 } 7743 7744 if (!send_update_to_fw) 7745 return; 7746 7747 mutex_lock(&ioc->base_cmds.mutex); 7748 _base_event_notification(ioc); 7749 mutex_unlock(&ioc->base_cmds.mutex); 7750 } 7751 7752 /** 7753 * _base_diag_reset - the "big hammer" start of day reset 7754 * @ioc: per adapter object 7755 * 7756 * Return: 0 for success, non-zero for failure. 7757 */ 7758 static int 7759 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) 7760 { 7761 u32 host_diagnostic; 7762 u32 ioc_state; 7763 u32 count; 7764 u32 hcb_size; 7765 7766 ioc_info(ioc, "sending diag reset !!\n"); 7767 7768 pci_cfg_access_lock(ioc->pdev); 7769 7770 drsprintk(ioc, ioc_info(ioc, "clear interrupts\n")); 7771 7772 count = 0; 7773 do { 7774 /* Write magic sequence to WriteSequence register 7775 * Loop until in diagnostic mode 7776 */ 7777 drsprintk(ioc, ioc_info(ioc, "write magic sequence\n")); 7778 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 7779 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 7780 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 7781 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 7782 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 7783 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 7784 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 7785 7786 /* wait 100 msec */ 7787 msleep(100); 7788 7789 if (count++ > 20) { 7790 ioc_info(ioc, 7791 "Stop writing magic sequence after 20 retries\n"); 7792 _base_dump_reg_set(ioc); 7793 goto out; 7794 } 7795 7796 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic); 7797 drsprintk(ioc, 7798 ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 7799 count, host_diagnostic)); 7800 7801 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 7802 7803 hcb_size = ioc->base_readl(&ioc->chip->HCBSize); 7804 7805 drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n")); 7806 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 7807 &ioc->chip->HostDiagnostic); 7808 7809 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 7810 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 7811 7812 /* Approximately 300 second max wait */ 7813 for (count = 0; count < (300000000 / 7814 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 7815 7816 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic); 7817 7818 if (host_diagnostic == 0xFFFFFFFF) { 7819 ioc_info(ioc, 7820 "Invalid host diagnostic register value\n"); 7821 _base_dump_reg_set(ioc); 7822 goto out; 7823 } 7824 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 7825 break; 7826 7827 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); 7828 } 7829 7830 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 7831 7832 drsprintk(ioc, 7833 ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n")); 7834 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 7835 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 7836 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 7837 7838 drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n")); 7839 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 7840 &ioc->chip->HCBSize); 7841 } 7842 7843 drsprintk(ioc, ioc_info(ioc, "restart the adapter\n")); 7844 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 7845 &ioc->chip->HostDiagnostic); 7846 7847 drsprintk(ioc, 7848 ioc_info(ioc, "disable writes to the diagnostic register\n")); 7849 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 7850 7851 drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n")); 7852 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); 7853 if (ioc_state) { 7854 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 7855 __func__, ioc_state); 7856 _base_dump_reg_set(ioc); 7857 goto out; 7858 } 7859 7860 pci_cfg_access_unlock(ioc->pdev); 7861 ioc_info(ioc, "diag reset: SUCCESS\n"); 7862 return 0; 7863 7864 out: 7865 pci_cfg_access_unlock(ioc->pdev); 7866 ioc_err(ioc, "diag reset: FAILED\n"); 7867 return -EFAULT; 7868 } 7869 7870 /** 7871 * mpt3sas_base_make_ioc_ready - put controller in READY state 7872 * @ioc: per adapter object 7873 * @type: FORCE_BIG_HAMMER or SOFT_RESET 7874 * 7875 * Return: 0 for success, non-zero for failure. 7876 */ 7877 int 7878 mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) 7879 { 7880 u32 ioc_state; 7881 int rc; 7882 int count; 7883 7884 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7885 7886 if (ioc->pci_error_recovery) 7887 return 0; 7888 7889 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 7890 dhsprintk(ioc, 7891 ioc_info(ioc, "%s: ioc_state(0x%08x)\n", 7892 __func__, ioc_state)); 7893 7894 /* if in RESET state, it should move to READY state shortly */ 7895 count = 0; 7896 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 7897 while ((ioc_state & MPI2_IOC_STATE_MASK) != 7898 MPI2_IOC_STATE_READY) { 7899 if (count++ == 10) { 7900 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", 7901 __func__, ioc_state); 7902 return -EFAULT; 7903 } 7904 ssleep(1); 7905 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 7906 } 7907 } 7908 7909 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 7910 return 0; 7911 7912 if (ioc_state & MPI2_DOORBELL_USED) { 7913 ioc_info(ioc, "unexpected doorbell active!\n"); 7914 goto issue_diag_reset; 7915 } 7916 7917 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 7918 mpt3sas_print_fault_code(ioc, ioc_state & 7919 MPI2_DOORBELL_DATA_MASK); 7920 goto issue_diag_reset; 7921 } 7922 7923 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { 7924 /* 7925 * if host reset is invoked while watch dog thread is waiting 7926 * for IOC state to be changed to Fault state then driver has 7927 * to wait here for CoreDump state to clear otherwise reset 7928 * will be issued to the FW and FW move the IOC state to 7929 * reset state without copying the FW logs to coredump region. 7930 */ 7931 if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) { 7932 mpt3sas_print_coredump_info(ioc, ioc_state & 7933 MPI2_DOORBELL_DATA_MASK); 7934 mpt3sas_base_wait_for_coredump_completion(ioc, 7935 __func__); 7936 } 7937 goto issue_diag_reset; 7938 } 7939 7940 if (type == FORCE_BIG_HAMMER) 7941 goto issue_diag_reset; 7942 7943 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 7944 if (!(_base_send_ioc_reset(ioc, 7945 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { 7946 return 0; 7947 } 7948 7949 issue_diag_reset: 7950 rc = _base_diag_reset(ioc); 7951 return rc; 7952 } 7953 7954 /** 7955 * _base_make_ioc_operational - put controller in OPERATIONAL state 7956 * @ioc: per adapter object 7957 * 7958 * Return: 0 for success, non-zero for failure. 7959 */ 7960 static int 7961 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) 7962 { 7963 int r, i, index, rc; 7964 unsigned long flags; 7965 u32 reply_address; 7966 u16 smid; 7967 struct _tr_list *delayed_tr, *delayed_tr_next; 7968 struct _sc_list *delayed_sc, *delayed_sc_next; 7969 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; 7970 u8 hide_flag; 7971 struct adapter_reply_queue *reply_q; 7972 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; 7973 7974 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 7975 7976 /* clean the delayed target reset list */ 7977 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 7978 &ioc->delayed_tr_list, list) { 7979 list_del(&delayed_tr->list); 7980 kfree(delayed_tr); 7981 } 7982 7983 7984 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 7985 &ioc->delayed_tr_volume_list, list) { 7986 list_del(&delayed_tr->list); 7987 kfree(delayed_tr); 7988 } 7989 7990 list_for_each_entry_safe(delayed_sc, delayed_sc_next, 7991 &ioc->delayed_sc_list, list) { 7992 list_del(&delayed_sc->list); 7993 kfree(delayed_sc); 7994 } 7995 7996 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, 7997 &ioc->delayed_event_ack_list, list) { 7998 list_del(&delayed_event_ack->list); 7999 kfree(delayed_event_ack); 8000 } 8001 8002 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 8003 8004 /* hi-priority queue */ 8005 INIT_LIST_HEAD(&ioc->hpr_free_list); 8006 smid = ioc->hi_priority_smid; 8007 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 8008 ioc->hpr_lookup[i].cb_idx = 0xFF; 8009 ioc->hpr_lookup[i].smid = smid; 8010 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 8011 &ioc->hpr_free_list); 8012 } 8013 8014 /* internal queue */ 8015 INIT_LIST_HEAD(&ioc->internal_free_list); 8016 smid = ioc->internal_smid; 8017 for (i = 0; i < ioc->internal_depth; i++, smid++) { 8018 ioc->internal_lookup[i].cb_idx = 0xFF; 8019 ioc->internal_lookup[i].smid = smid; 8020 list_add_tail(&ioc->internal_lookup[i].tracker_list, 8021 &ioc->internal_free_list); 8022 } 8023 8024 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 8025 8026 /* initialize Reply Free Queue */ 8027 for (i = 0, reply_address = (u32)ioc->reply_dma ; 8028 i < ioc->reply_free_queue_depth ; i++, reply_address += 8029 ioc->reply_sz) { 8030 ioc->reply_free[i] = cpu_to_le32(reply_address); 8031 if (ioc->is_mcpu_endpoint) 8032 _base_clone_reply_to_sys_mem(ioc, 8033 reply_address, i); 8034 } 8035 8036 /* initialize reply queues */ 8037 if (ioc->is_driver_loading) 8038 _base_assign_reply_queues(ioc); 8039 8040 /* initialize Reply Post Free Queue */ 8041 index = 0; 8042 reply_post_free_contig = ioc->reply_post[0].reply_post_free; 8043 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 8044 /* 8045 * If RDPQ is enabled, switch to the next allocation. 8046 * Otherwise advance within the contiguous region. 8047 */ 8048 if (ioc->rdpq_array_enable) { 8049 reply_q->reply_post_free = 8050 ioc->reply_post[index++].reply_post_free; 8051 } else { 8052 reply_q->reply_post_free = reply_post_free_contig; 8053 reply_post_free_contig += ioc->reply_post_queue_depth; 8054 } 8055 8056 reply_q->reply_post_host_index = 0; 8057 for (i = 0; i < ioc->reply_post_queue_depth; i++) 8058 reply_q->reply_post_free[i].Words = 8059 cpu_to_le64(ULLONG_MAX); 8060 if (!_base_is_controller_msix_enabled(ioc)) 8061 goto skip_init_reply_post_free_queue; 8062 } 8063 skip_init_reply_post_free_queue: 8064 8065 r = _base_send_ioc_init(ioc); 8066 if (r) { 8067 /* 8068 * No need to check IOC state for fault state & issue 8069 * diag reset during host reset. This check is need 8070 * only during driver load time. 8071 */ 8072 if (!ioc->is_driver_loading) 8073 return r; 8074 8075 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8076 if (rc || (_base_send_ioc_init(ioc))) 8077 return r; 8078 } 8079 8080 /* initialize reply free host index */ 8081 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 8082 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 8083 8084 /* initialize reply post host index */ 8085 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 8086 if (ioc->combined_reply_queue) 8087 writel((reply_q->msix_index & 7)<< 8088 MPI2_RPHI_MSIX_INDEX_SHIFT, 8089 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 8090 else 8091 writel(reply_q->msix_index << 8092 MPI2_RPHI_MSIX_INDEX_SHIFT, 8093 &ioc->chip->ReplyPostHostIndex); 8094 8095 if (!_base_is_controller_msix_enabled(ioc)) 8096 goto skip_init_reply_post_host_index; 8097 } 8098 8099 skip_init_reply_post_host_index: 8100 8101 mpt3sas_base_unmask_interrupts(ioc); 8102 8103 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 8104 r = _base_display_fwpkg_version(ioc); 8105 if (r) 8106 return r; 8107 } 8108 8109 r = _base_static_config_pages(ioc); 8110 if (r) 8111 return r; 8112 8113 r = _base_event_notification(ioc); 8114 if (r) 8115 return r; 8116 8117 if (!ioc->shost_recovery) { 8118 8119 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 8120 == 0x80) { 8121 hide_flag = (u8) ( 8122 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 8123 MFG_PAGE10_HIDE_SSDS_MASK); 8124 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 8125 ioc->mfg_pg10_hide_flag = hide_flag; 8126 } 8127 8128 ioc->wait_for_discovery_to_complete = 8129 _base_determine_wait_on_discovery(ioc); 8130 8131 return r; /* scan_start and scan_finished support */ 8132 } 8133 8134 r = _base_send_port_enable(ioc); 8135 if (r) 8136 return r; 8137 8138 return r; 8139 } 8140 8141 /** 8142 * mpt3sas_base_free_resources - free resources controller resources 8143 * @ioc: per adapter object 8144 */ 8145 void 8146 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 8147 { 8148 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8149 8150 /* synchronizing freeing resource with pci_access_mutex lock */ 8151 mutex_lock(&ioc->pci_access_mutex); 8152 if (ioc->chip_phys && ioc->chip) { 8153 mpt3sas_base_mask_interrupts(ioc); 8154 ioc->shost_recovery = 1; 8155 mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); 8156 ioc->shost_recovery = 0; 8157 } 8158 8159 mpt3sas_base_unmap_resources(ioc); 8160 mutex_unlock(&ioc->pci_access_mutex); 8161 return; 8162 } 8163 8164 /** 8165 * mpt3sas_base_attach - attach controller instance 8166 * @ioc: per adapter object 8167 * 8168 * Return: 0 for success, non-zero for failure. 8169 */ 8170 int 8171 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 8172 { 8173 int r, i, rc; 8174 int cpu_id, last_cpu_id = 0; 8175 8176 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8177 8178 /* setup cpu_msix_table */ 8179 ioc->cpu_count = num_online_cpus(); 8180 for_each_online_cpu(cpu_id) 8181 last_cpu_id = cpu_id; 8182 ioc->cpu_msix_table_sz = last_cpu_id + 1; 8183 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 8184 ioc->reply_queue_count = 1; 8185 if (!ioc->cpu_msix_table) { 8186 ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n"); 8187 r = -ENOMEM; 8188 goto out_free_resources; 8189 } 8190 8191 if (ioc->is_warpdrive) { 8192 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 8193 sizeof(resource_size_t *), GFP_KERNEL); 8194 if (!ioc->reply_post_host_index) { 8195 ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n"); 8196 r = -ENOMEM; 8197 goto out_free_resources; 8198 } 8199 } 8200 8201 ioc->smp_affinity_enable = smp_affinity_enable; 8202 8203 ioc->rdpq_array_enable_assigned = 0; 8204 ioc->use_32bit_dma = false; 8205 ioc->dma_mask = 64; 8206 if (ioc->is_aero_ioc) 8207 ioc->base_readl = &_base_readl_aero; 8208 else 8209 ioc->base_readl = &_base_readl; 8210 r = mpt3sas_base_map_resources(ioc); 8211 if (r) 8212 goto out_free_resources; 8213 8214 pci_set_drvdata(ioc->pdev, ioc->shost); 8215 r = _base_get_ioc_facts(ioc); 8216 if (r) { 8217 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8218 if (rc || (_base_get_ioc_facts(ioc))) 8219 goto out_free_resources; 8220 } 8221 8222 switch (ioc->hba_mpi_version_belonged) { 8223 case MPI2_VERSION: 8224 ioc->build_sg_scmd = &_base_build_sg_scmd; 8225 ioc->build_sg = &_base_build_sg; 8226 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 8227 ioc->get_msix_index_for_smlio = &_base_get_msix_index; 8228 break; 8229 case MPI25_VERSION: 8230 case MPI26_VERSION: 8231 /* 8232 * In SAS3.0, 8233 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 8234 * Target Status - all require the IEEE formatted scatter gather 8235 * elements. 8236 */ 8237 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 8238 ioc->build_sg = &_base_build_sg_ieee; 8239 ioc->build_nvme_prp = &_base_build_nvme_prp; 8240 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 8241 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 8242 if (ioc->high_iops_queues) 8243 ioc->get_msix_index_for_smlio = 8244 &_base_get_high_iops_msix_index; 8245 else 8246 ioc->get_msix_index_for_smlio = &_base_get_msix_index; 8247 break; 8248 } 8249 if (ioc->atomic_desc_capable) { 8250 ioc->put_smid_default = &_base_put_smid_default_atomic; 8251 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; 8252 ioc->put_smid_fast_path = 8253 &_base_put_smid_fast_path_atomic; 8254 ioc->put_smid_hi_priority = 8255 &_base_put_smid_hi_priority_atomic; 8256 } else { 8257 ioc->put_smid_default = &_base_put_smid_default; 8258 ioc->put_smid_fast_path = &_base_put_smid_fast_path; 8259 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; 8260 if (ioc->is_mcpu_endpoint) 8261 ioc->put_smid_scsi_io = 8262 &_base_put_smid_mpi_ep_scsi_io; 8263 else 8264 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; 8265 } 8266 /* 8267 * These function pointers for other requests that don't 8268 * the require IEEE scatter gather elements. 8269 * 8270 * For example Configuration Pages and SAS IOUNIT Control don't. 8271 */ 8272 ioc->build_sg_mpi = &_base_build_sg; 8273 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 8274 8275 r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); 8276 if (r) 8277 goto out_free_resources; 8278 8279 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 8280 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 8281 if (!ioc->pfacts) { 8282 r = -ENOMEM; 8283 goto out_free_resources; 8284 } 8285 8286 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 8287 r = _base_get_port_facts(ioc, i); 8288 if (r) { 8289 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); 8290 if (rc || (_base_get_port_facts(ioc, i))) 8291 goto out_free_resources; 8292 } 8293 } 8294 8295 r = _base_allocate_memory_pools(ioc); 8296 if (r) 8297 goto out_free_resources; 8298 8299 if (irqpoll_weight > 0) 8300 ioc->thresh_hold = irqpoll_weight; 8301 else 8302 ioc->thresh_hold = ioc->hba_queue_depth/4; 8303 8304 _base_init_irqpolls(ioc); 8305 init_waitqueue_head(&ioc->reset_wq); 8306 8307 /* allocate memory pd handle bitmask list */ 8308 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 8309 if (ioc->facts.MaxDevHandle % 8) 8310 ioc->pd_handles_sz++; 8311 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 8312 GFP_KERNEL); 8313 if (!ioc->pd_handles) { 8314 r = -ENOMEM; 8315 goto out_free_resources; 8316 } 8317 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 8318 GFP_KERNEL); 8319 if (!ioc->blocking_handles) { 8320 r = -ENOMEM; 8321 goto out_free_resources; 8322 } 8323 8324 /* allocate memory for pending OS device add list */ 8325 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); 8326 if (ioc->facts.MaxDevHandle % 8) 8327 ioc->pend_os_device_add_sz++; 8328 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, 8329 GFP_KERNEL); 8330 if (!ioc->pend_os_device_add) { 8331 r = -ENOMEM; 8332 goto out_free_resources; 8333 } 8334 8335 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; 8336 ioc->device_remove_in_progress = 8337 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); 8338 if (!ioc->device_remove_in_progress) { 8339 r = -ENOMEM; 8340 goto out_free_resources; 8341 } 8342 8343 ioc->fwfault_debug = mpt3sas_fwfault_debug; 8344 8345 /* base internal command bits */ 8346 mutex_init(&ioc->base_cmds.mutex); 8347 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8348 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 8349 8350 /* port_enable command bits */ 8351 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8352 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 8353 8354 /* transport internal command bits */ 8355 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8356 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 8357 mutex_init(&ioc->transport_cmds.mutex); 8358 8359 /* scsih internal command bits */ 8360 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8361 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 8362 mutex_init(&ioc->scsih_cmds.mutex); 8363 8364 /* task management internal command bits */ 8365 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8366 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 8367 mutex_init(&ioc->tm_cmds.mutex); 8368 8369 /* config page internal command bits */ 8370 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8371 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 8372 mutex_init(&ioc->config_cmds.mutex); 8373 8374 /* ctl module internal command bits */ 8375 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 8376 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 8377 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 8378 mutex_init(&ioc->ctl_cmds.mutex); 8379 8380 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || 8381 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || 8382 !ioc->tm_cmds.reply || !ioc->config_cmds.reply || 8383 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { 8384 r = -ENOMEM; 8385 goto out_free_resources; 8386 } 8387 8388 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 8389 ioc->event_masks[i] = -1; 8390 8391 /* here we enable the events we care about */ 8392 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 8393 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 8394 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 8395 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 8396 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 8397 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 8398 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 8399 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 8400 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 8401 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 8402 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 8403 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); 8404 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 8405 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) { 8406 if (ioc->is_gen35_ioc) { 8407 _base_unmask_events(ioc, 8408 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE); 8409 _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION); 8410 _base_unmask_events(ioc, 8411 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 8412 } 8413 } 8414 r = _base_make_ioc_operational(ioc); 8415 if (r == -EAGAIN) { 8416 r = _base_make_ioc_operational(ioc); 8417 if (r) 8418 goto out_free_resources; 8419 } 8420 8421 /* 8422 * Copy current copy of IOCFacts in prev_fw_facts 8423 * and it will be used during online firmware upgrade. 8424 */ 8425 memcpy(&ioc->prev_fw_facts, &ioc->facts, 8426 sizeof(struct mpt3sas_facts)); 8427 8428 ioc->non_operational_loop = 0; 8429 ioc->ioc_coredump_loop = 0; 8430 ioc->got_task_abort_from_ioctl = 0; 8431 return 0; 8432 8433 out_free_resources: 8434 8435 ioc->remove_host = 1; 8436 8437 mpt3sas_base_free_resources(ioc); 8438 _base_release_memory_pools(ioc); 8439 pci_set_drvdata(ioc->pdev, NULL); 8440 kfree(ioc->cpu_msix_table); 8441 if (ioc->is_warpdrive) 8442 kfree(ioc->reply_post_host_index); 8443 kfree(ioc->pd_handles); 8444 kfree(ioc->blocking_handles); 8445 kfree(ioc->device_remove_in_progress); 8446 kfree(ioc->pend_os_device_add); 8447 kfree(ioc->tm_cmds.reply); 8448 kfree(ioc->transport_cmds.reply); 8449 kfree(ioc->scsih_cmds.reply); 8450 kfree(ioc->config_cmds.reply); 8451 kfree(ioc->base_cmds.reply); 8452 kfree(ioc->port_enable_cmds.reply); 8453 kfree(ioc->ctl_cmds.reply); 8454 kfree(ioc->ctl_cmds.sense); 8455 kfree(ioc->pfacts); 8456 ioc->ctl_cmds.reply = NULL; 8457 ioc->base_cmds.reply = NULL; 8458 ioc->tm_cmds.reply = NULL; 8459 ioc->scsih_cmds.reply = NULL; 8460 ioc->transport_cmds.reply = NULL; 8461 ioc->config_cmds.reply = NULL; 8462 ioc->pfacts = NULL; 8463 return r; 8464 } 8465 8466 8467 /** 8468 * mpt3sas_base_detach - remove controller instance 8469 * @ioc: per adapter object 8470 */ 8471 void 8472 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 8473 { 8474 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); 8475 8476 mpt3sas_base_stop_watchdog(ioc); 8477 mpt3sas_base_free_resources(ioc); 8478 _base_release_memory_pools(ioc); 8479 mpt3sas_free_enclosure_list(ioc); 8480 pci_set_drvdata(ioc->pdev, NULL); 8481 kfree(ioc->cpu_msix_table); 8482 if (ioc->is_warpdrive) 8483 kfree(ioc->reply_post_host_index); 8484 kfree(ioc->pd_handles); 8485 kfree(ioc->blocking_handles); 8486 kfree(ioc->device_remove_in_progress); 8487 kfree(ioc->pend_os_device_add); 8488 kfree(ioc->pfacts); 8489 kfree(ioc->ctl_cmds.reply); 8490 kfree(ioc->ctl_cmds.sense); 8491 kfree(ioc->base_cmds.reply); 8492 kfree(ioc->port_enable_cmds.reply); 8493 kfree(ioc->tm_cmds.reply); 8494 kfree(ioc->transport_cmds.reply); 8495 kfree(ioc->scsih_cmds.reply); 8496 kfree(ioc->config_cmds.reply); 8497 } 8498 8499 /** 8500 * _base_pre_reset_handler - pre reset handler 8501 * @ioc: per adapter object 8502 */ 8503 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc) 8504 { 8505 mpt3sas_scsih_pre_reset_handler(ioc); 8506 mpt3sas_ctl_pre_reset_handler(ioc); 8507 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__)); 8508 } 8509 8510 /** 8511 * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands 8512 * @ioc: per adapter object 8513 */ 8514 static void 8515 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc) 8516 { 8517 dtmprintk(ioc, 8518 ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__)); 8519 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 8520 ioc->transport_cmds.status |= MPT3_CMD_RESET; 8521 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 8522 complete(&ioc->transport_cmds.done); 8523 } 8524 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 8525 ioc->base_cmds.status |= MPT3_CMD_RESET; 8526 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 8527 complete(&ioc->base_cmds.done); 8528 } 8529 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 8530 ioc->port_enable_failed = 1; 8531 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 8532 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 8533 if (ioc->is_driver_loading) { 8534 ioc->start_scan_failed = 8535 MPI2_IOCSTATUS_INTERNAL_ERROR; 8536 ioc->start_scan = 0; 8537 } else { 8538 complete(&ioc->port_enable_cmds.done); 8539 } 8540 } 8541 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 8542 ioc->config_cmds.status |= MPT3_CMD_RESET; 8543 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 8544 ioc->config_cmds.smid = USHRT_MAX; 8545 complete(&ioc->config_cmds.done); 8546 } 8547 } 8548 8549 /** 8550 * _base_clear_outstanding_commands - clear all outstanding commands 8551 * @ioc: per adapter object 8552 */ 8553 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc) 8554 { 8555 mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc); 8556 mpt3sas_ctl_clear_outstanding_ioctls(ioc); 8557 _base_clear_outstanding_mpt_commands(ioc); 8558 } 8559 8560 /** 8561 * _base_reset_done_handler - reset done handler 8562 * @ioc: per adapter object 8563 */ 8564 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc) 8565 { 8566 mpt3sas_scsih_reset_done_handler(ioc); 8567 mpt3sas_ctl_reset_done_handler(ioc); 8568 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__)); 8569 } 8570 8571 /** 8572 * mpt3sas_wait_for_commands_to_complete - reset controller 8573 * @ioc: Pointer to MPT_ADAPTER structure 8574 * 8575 * This function is waiting 10s for all pending commands to complete 8576 * prior to putting controller in reset. 8577 */ 8578 void 8579 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) 8580 { 8581 u32 ioc_state; 8582 8583 ioc->pending_io_count = 0; 8584 8585 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8586 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 8587 return; 8588 8589 /* pending command count */ 8590 ioc->pending_io_count = scsi_host_busy(ioc->shost); 8591 8592 if (!ioc->pending_io_count) 8593 return; 8594 8595 /* wait for pending commands to complete */ 8596 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 8597 } 8598 8599 /** 8600 * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts 8601 * attributes during online firmware upgrade and update the corresponding 8602 * IOC variables accordingly. 8603 * 8604 * @ioc: Pointer to MPT_ADAPTER structure 8605 */ 8606 static int 8607 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc) 8608 { 8609 u16 pd_handles_sz; 8610 void *pd_handles = NULL, *blocking_handles = NULL; 8611 void *pend_os_device_add = NULL, *device_remove_in_progress = NULL; 8612 struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts; 8613 8614 if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) { 8615 pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 8616 if (ioc->facts.MaxDevHandle % 8) 8617 pd_handles_sz++; 8618 8619 pd_handles = krealloc(ioc->pd_handles, pd_handles_sz, 8620 GFP_KERNEL); 8621 if (!pd_handles) { 8622 ioc_info(ioc, 8623 "Unable to allocate the memory for pd_handles of sz: %d\n", 8624 pd_handles_sz); 8625 return -ENOMEM; 8626 } 8627 memset(pd_handles + ioc->pd_handles_sz, 0, 8628 (pd_handles_sz - ioc->pd_handles_sz)); 8629 ioc->pd_handles = pd_handles; 8630 8631 blocking_handles = krealloc(ioc->blocking_handles, 8632 pd_handles_sz, GFP_KERNEL); 8633 if (!blocking_handles) { 8634 ioc_info(ioc, 8635 "Unable to allocate the memory for " 8636 "blocking_handles of sz: %d\n", 8637 pd_handles_sz); 8638 return -ENOMEM; 8639 } 8640 memset(blocking_handles + ioc->pd_handles_sz, 0, 8641 (pd_handles_sz - ioc->pd_handles_sz)); 8642 ioc->blocking_handles = blocking_handles; 8643 ioc->pd_handles_sz = pd_handles_sz; 8644 8645 pend_os_device_add = krealloc(ioc->pend_os_device_add, 8646 pd_handles_sz, GFP_KERNEL); 8647 if (!pend_os_device_add) { 8648 ioc_info(ioc, 8649 "Unable to allocate the memory for pend_os_device_add of sz: %d\n", 8650 pd_handles_sz); 8651 return -ENOMEM; 8652 } 8653 memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0, 8654 (pd_handles_sz - ioc->pend_os_device_add_sz)); 8655 ioc->pend_os_device_add = pend_os_device_add; 8656 ioc->pend_os_device_add_sz = pd_handles_sz; 8657 8658 device_remove_in_progress = krealloc( 8659 ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL); 8660 if (!device_remove_in_progress) { 8661 ioc_info(ioc, 8662 "Unable to allocate the memory for " 8663 "device_remove_in_progress of sz: %d\n " 8664 , pd_handles_sz); 8665 return -ENOMEM; 8666 } 8667 memset(device_remove_in_progress + 8668 ioc->device_remove_in_progress_sz, 0, 8669 (pd_handles_sz - ioc->device_remove_in_progress_sz)); 8670 ioc->device_remove_in_progress = device_remove_in_progress; 8671 ioc->device_remove_in_progress_sz = pd_handles_sz; 8672 } 8673 8674 memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts)); 8675 return 0; 8676 } 8677 8678 /** 8679 * mpt3sas_base_hard_reset_handler - reset controller 8680 * @ioc: Pointer to MPT_ADAPTER structure 8681 * @type: FORCE_BIG_HAMMER or SOFT_RESET 8682 * 8683 * Return: 0 for success, non-zero for failure. 8684 */ 8685 int 8686 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 8687 enum reset_type type) 8688 { 8689 int r; 8690 unsigned long flags; 8691 u32 ioc_state; 8692 u8 is_fault = 0, is_trigger = 0; 8693 8694 dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__)); 8695 8696 if (ioc->pci_error_recovery) { 8697 ioc_err(ioc, "%s: pci error recovery reset\n", __func__); 8698 r = 0; 8699 goto out_unlocked; 8700 } 8701 8702 if (mpt3sas_fwfault_debug) 8703 mpt3sas_halt_firmware(ioc); 8704 8705 /* wait for an active reset in progress to complete */ 8706 mutex_lock(&ioc->reset_in_progress_mutex); 8707 8708 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 8709 ioc->shost_recovery = 1; 8710 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 8711 8712 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 8713 MPT3_DIAG_BUFFER_IS_REGISTERED) && 8714 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 8715 MPT3_DIAG_BUFFER_IS_RELEASED))) { 8716 is_trigger = 1; 8717 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 8718 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT || 8719 (ioc_state & MPI2_IOC_STATE_MASK) == 8720 MPI2_IOC_STATE_COREDUMP) { 8721 is_fault = 1; 8722 ioc->htb_rel.trigger_info_dwords[1] = 8723 (ioc_state & MPI2_DOORBELL_DATA_MASK); 8724 } 8725 } 8726 _base_pre_reset_handler(ioc); 8727 mpt3sas_wait_for_commands_to_complete(ioc); 8728 mpt3sas_base_mask_interrupts(ioc); 8729 mpt3sas_base_pause_mq_polling(ioc); 8730 r = mpt3sas_base_make_ioc_ready(ioc, type); 8731 if (r) 8732 goto out; 8733 _base_clear_outstanding_commands(ioc); 8734 8735 /* If this hard reset is called while port enable is active, then 8736 * there is no reason to call make_ioc_operational 8737 */ 8738 if (ioc->is_driver_loading && ioc->port_enable_failed) { 8739 ioc->remove_host = 1; 8740 r = -EFAULT; 8741 goto out; 8742 } 8743 r = _base_get_ioc_facts(ioc); 8744 if (r) 8745 goto out; 8746 8747 r = _base_check_ioc_facts_changes(ioc); 8748 if (r) { 8749 ioc_info(ioc, 8750 "Some of the parameters got changed in this new firmware" 8751 " image and it requires system reboot\n"); 8752 goto out; 8753 } 8754 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 8755 panic("%s: Issue occurred with flashing controller firmware." 8756 "Please reboot the system and ensure that the correct" 8757 " firmware version is running\n", ioc->name); 8758 8759 r = _base_make_ioc_operational(ioc); 8760 if (!r) 8761 _base_reset_done_handler(ioc); 8762 8763 out: 8764 ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED"); 8765 8766 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 8767 ioc->shost_recovery = 0; 8768 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 8769 ioc->ioc_reset_count++; 8770 mutex_unlock(&ioc->reset_in_progress_mutex); 8771 mpt3sas_base_resume_mq_polling(ioc); 8772 8773 out_unlocked: 8774 if ((r == 0) && is_trigger) { 8775 if (is_fault) 8776 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 8777 else 8778 mpt3sas_trigger_master(ioc, 8779 MASTER_TRIGGER_ADAPTER_RESET); 8780 } 8781 dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__)); 8782 return r; 8783 } 8784