1 /* 2 * Copyright (c) 2000-2014 LSI Corporation. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.26 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 23 * Added Manufacturing Page 11. 24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 25 * define. 26 * 06-26-07 02.00.02 Adding generic structure for product-specific 27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 28 * Rework of BIOS Page 2 configuration page. 29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 30 * forms. 31 * Added configuration pages IOC Page 8 and Driver 32 * Persistent Mapping Page 0. 33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 35 * RAID Physical Disk Pages 0 and 1, RAID Configuration 36 * Page 0). 37 * Added new value for AccessStatus field of SAS Device 38 * Page 0 (_SATA_NEEDS_INITIALIZATION). 39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 42 * NVDATA. 43 * Modified IOC Page 7 to use masks and added field for 44 * SASBroadcastPrimitiveMasks. 45 * Added MPI2_CONFIG_PAGE_BIOS_4. 46 * Added MPI2_CONFIG_PAGE_LOG_0. 47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 48 * Added SAS Device IDs. 49 * Updated Integrated RAID configuration pages including 50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 51 * Page 0. 52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 55 * Added missing MaxNumRoutedSasAddresses field to 56 * MPI2_CONFIG_PAGE_EXPANDER_0. 57 * Added SAS Port Page 0. 58 * Modified structure layout for 59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 63 * to 0x000000FF. 64 * Added two new values for the Physical Disk Coercion Size 65 * bits in the Flags field of Manufacturing Page 4. 66 * Added product-specific Manufacturing pages 16 to 31. 67 * Modified Flags bits for controlling write cache on SATA 68 * drives in IO Unit Page 1. 69 * Added new bit to AdditionalControlFlags of SAS IO Unit 70 * Page 1 to control Invalid Topology Correction. 71 * Added additional defines for RAID Volume Page 0 72 * VolumeStatusFlags field. 73 * Modified meaning of RAID Volume Page 0 VolumeSettings 74 * define for auto-configure of hot-swap drives. 75 * Added SupportedPhysDisks field to RAID Volume Page 1 and 76 * added related defines. 77 * Added PhysDiskAttributes field (and related defines) to 78 * RAID Physical Disk Page 0. 79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 80 * Added three new DiscoveryStatus bits for SAS IO Unit 81 * Page 0 and SAS Expander Page 0. 82 * Removed multiplexing information from SAS IO Unit pages. 83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 84 * Removed Zone Address Resolved bit from PhyInfo and from 85 * Expander Page 0 Flags field. 86 * Added two new AccessStatus values to SAS Device Page 0 87 * for indicating routing problems. Added 3 reserved words 88 * to this page. 89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 90 * Inserted missing reserved field into structure for IOC 91 * Page 6. 92 * Added more pending task bits to RAID Volume Page 0 93 * VolumeStatusFlags defines. 94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 96 * and SAS Expander Page 0 to flag a downstream initiator 97 * when in simplified routing mode. 98 * Removed SATA Init Failure defines for DiscoveryStatus 99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 101 * Added PortGroups, DmaGroup, and ControlGroup fields to 102 * SAS Device Page 0. 103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 104 * Unit Page 6. 105 * Added expander reduced functionality data to SAS 106 * Expander Page 0. 107 * Added SAS PHY Page 2 and SAS PHY Page 3. 108 * 07-30-09 02.00.12 Added IO Unit Page 7. 109 * Added new device ids. 110 * Added SAS IO Unit Page 5. 111 * Added partial and slumber power management capable flags 112 * to SAS Device Page 0 Flags field. 113 * Added PhyInfo defines for power condition. 114 * Added Ethernet configuration pages. 115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 116 * Added SAS PHY Page 4 structure and defines. 117 * 02-10-10 02.00.14 Modified the comments for the configuration page 118 * structures that contain an array of data. The host 119 * should use the "count" field in the page data (e.g. the 120 * NumPhys field) to determine the number of valid elements 121 * in the array. 122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 123 * Added PowerManagementCapabilities to IO Unit Page 7. 124 * Added PortWidthModGroup field to 125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 130 * define. 131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 134 * defines. 135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 137 * the Pinout field. 138 * Added BoardTemperature and BoardTemperatureUnits fields 139 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 143 * Added IO Unit Page 8, IO Unit Page 9, 144 * and IO Unit Page 10. 145 * Added SASNotifyPrimitiveMasks field to 146 * MPI2_CONFIG_PAGE_IOC_7. 147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 148 * 05-25-11 02.00.20 Cleaned up a few comments. 149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 150 * for PCIe link as obsolete. 151 * Added SpinupFlags field containing a Disable Spin-up bit 152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 153 * Unit Page 4. 154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 155 * Added UEFIVersion field to BIOS Page 1 and defined new 156 * BiosOptions bits. 157 * Incorporating additions for MPI v2.5. 158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 161 * obsolete for MPI v2.5 and later. 162 * Added some defines for 12G SAS speeds. 163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 165 * match the specification. 166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 167 * future use. 168 * -------------------------------------------------------------------------- 169 */ 170 171 #ifndef MPI2_CNFG_H 172 #define MPI2_CNFG_H 173 174 /***************************************************************************** 175 * Configuration Page Header and defines 176 *****************************************************************************/ 177 178 /*Config Page Header */ 179 typedef struct _MPI2_CONFIG_PAGE_HEADER { 180 U8 PageVersion; /*0x00 */ 181 U8 PageLength; /*0x01 */ 182 U8 PageNumber; /*0x02 */ 183 U8 PageType; /*0x03 */ 184 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 185 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 186 187 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 188 MPI2_CONFIG_PAGE_HEADER Struct; 189 U8 Bytes[4]; 190 U16 Word16[2]; 191 U32 Word32; 192 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 193 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 194 195 /*Extended Config Page Header */ 196 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 197 U8 PageVersion; /*0x00 */ 198 U8 Reserved1; /*0x01 */ 199 U8 PageNumber; /*0x02 */ 200 U8 PageType; /*0x03 */ 201 U16 ExtPageLength; /*0x04 */ 202 U8 ExtPageType; /*0x06 */ 203 U8 Reserved2; /*0x07 */ 204 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 205 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 206 Mpi2ConfigExtendedPageHeader_t, 207 *pMpi2ConfigExtendedPageHeader_t; 208 209 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 210 MPI2_CONFIG_PAGE_HEADER Struct; 211 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 212 U8 Bytes[8]; 213 U16 Word16[4]; 214 U32 Word32[2]; 215 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 216 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 217 Mpi2ConfigPageExtendedHeaderUnion, 218 *pMpi2ConfigPageExtendedHeaderUnion; 219 220 221 /*PageType field values */ 222 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 223 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 224 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 225 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 226 227 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 228 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 229 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 230 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 231 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 232 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 233 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 234 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 235 236 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 237 238 239 /*ExtPageType field values */ 240 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 241 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 242 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 244 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 245 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 246 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 247 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 248 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 249 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 250 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 251 252 253 /***************************************************************************** 254 * PageAddress defines 255 *****************************************************************************/ 256 257 /*RAID Volume PageAddress format */ 258 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 259 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 260 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 261 262 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 263 264 265 /*RAID Physical Disk PageAddress format */ 266 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 267 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 268 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 269 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 270 271 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 272 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 273 274 275 /*SAS Expander PageAddress format */ 276 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 277 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 278 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 279 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 280 281 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 282 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 283 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 284 285 286 /*SAS Device PageAddress format */ 287 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 288 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 289 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 290 291 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 292 293 294 /*SAS PHY PageAddress format */ 295 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 296 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 297 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 298 299 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 300 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 301 302 303 /*SAS Port PageAddress format */ 304 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 305 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 306 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 307 308 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 309 310 311 /*SAS Enclosure PageAddress format */ 312 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 313 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 314 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 315 316 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 317 318 319 /*RAID Configuration PageAddress format */ 320 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 321 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 322 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 323 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 324 325 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 326 327 328 /*Driver Persistent Mapping PageAddress format */ 329 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 330 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 331 332 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 333 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 334 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 335 336 337 /*Ethernet PageAddress format */ 338 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 339 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 340 341 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 342 343 344 345 /**************************************************************************** 346 * Configuration messages 347 ****************************************************************************/ 348 349 /*Configuration Request Message */ 350 typedef struct _MPI2_CONFIG_REQUEST { 351 U8 Action; /*0x00 */ 352 U8 SGLFlags; /*0x01 */ 353 U8 ChainOffset; /*0x02 */ 354 U8 Function; /*0x03 */ 355 U16 ExtPageLength; /*0x04 */ 356 U8 ExtPageType; /*0x06 */ 357 U8 MsgFlags; /*0x07 */ 358 U8 VP_ID; /*0x08 */ 359 U8 VF_ID; /*0x09 */ 360 U16 Reserved1; /*0x0A */ 361 U8 Reserved2; /*0x0C */ 362 U8 ProxyVF_ID; /*0x0D */ 363 U16 Reserved4; /*0x0E */ 364 U32 Reserved3; /*0x10 */ 365 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 366 U32 PageAddress; /*0x18 */ 367 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 368 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 369 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 370 371 /*values for the Action field */ 372 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 373 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 374 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 375 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 376 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 377 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 378 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 379 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 380 381 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 382 383 384 /*Config Reply Message */ 385 typedef struct _MPI2_CONFIG_REPLY { 386 U8 Action; /*0x00 */ 387 U8 SGLFlags; /*0x01 */ 388 U8 MsgLength; /*0x02 */ 389 U8 Function; /*0x03 */ 390 U16 ExtPageLength; /*0x04 */ 391 U8 ExtPageType; /*0x06 */ 392 U8 MsgFlags; /*0x07 */ 393 U8 VP_ID; /*0x08 */ 394 U8 VF_ID; /*0x09 */ 395 U16 Reserved1; /*0x0A */ 396 U16 Reserved2; /*0x0C */ 397 U16 IOCStatus; /*0x0E */ 398 U32 IOCLogInfo; /*0x10 */ 399 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 400 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 401 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 402 403 404 405 /***************************************************************************** 406 * 407 * C o n f i g u r a t i o n P a g e s 408 * 409 *****************************************************************************/ 410 411 /**************************************************************************** 412 * Manufacturing Config pages 413 ****************************************************************************/ 414 415 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 416 417 /*MPI v2.0 SAS products */ 418 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 419 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 420 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 421 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 422 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 423 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 424 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 425 426 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 427 428 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 429 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 430 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 431 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 432 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 433 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 434 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 435 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 436 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 437 438 /*MPI v2.5 SAS products */ 439 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 440 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 441 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 442 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 443 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 444 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 445 446 447 448 449 /*Manufacturing Page 0 */ 450 451 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 452 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 453 U8 ChipName[16]; /*0x04 */ 454 U8 ChipRevision[8]; /*0x14 */ 455 U8 BoardName[16]; /*0x1C */ 456 U8 BoardAssembly[16]; /*0x2C */ 457 U8 BoardTracerNumber[16]; /*0x3C */ 458 } MPI2_CONFIG_PAGE_MAN_0, 459 *PTR_MPI2_CONFIG_PAGE_MAN_0, 460 Mpi2ManufacturingPage0_t, 461 *pMpi2ManufacturingPage0_t; 462 463 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 464 465 466 /*Manufacturing Page 1 */ 467 468 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 469 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 470 U8 VPD[256]; /*0x04 */ 471 } MPI2_CONFIG_PAGE_MAN_1, 472 *PTR_MPI2_CONFIG_PAGE_MAN_1, 473 Mpi2ManufacturingPage1_t, 474 *pMpi2ManufacturingPage1_t; 475 476 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 477 478 479 typedef struct _MPI2_CHIP_REVISION_ID { 480 U16 DeviceID; /*0x00 */ 481 U8 PCIRevisionID; /*0x02 */ 482 U8 Reserved; /*0x03 */ 483 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 484 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 485 486 487 /*Manufacturing Page 2 */ 488 489 /* 490 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 491 *one and check Header.PageLength at runtime. 492 */ 493 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 494 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 495 #endif 496 497 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 498 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 499 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 500 U32 501 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 502 } MPI2_CONFIG_PAGE_MAN_2, 503 *PTR_MPI2_CONFIG_PAGE_MAN_2, 504 Mpi2ManufacturingPage2_t, 505 *pMpi2ManufacturingPage2_t; 506 507 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 508 509 510 /*Manufacturing Page 3 */ 511 512 /* 513 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 514 *one and check Header.PageLength at runtime. 515 */ 516 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 517 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 518 #endif 519 520 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 521 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 522 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 523 U32 524 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 525 } MPI2_CONFIG_PAGE_MAN_3, 526 *PTR_MPI2_CONFIG_PAGE_MAN_3, 527 Mpi2ManufacturingPage3_t, 528 *pMpi2ManufacturingPage3_t; 529 530 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 531 532 533 /*Manufacturing Page 4 */ 534 535 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 536 U8 PowerSaveFlags; /*0x00 */ 537 U8 InternalOperationsSleepTime; /*0x01 */ 538 U8 InternalOperationsRunTime; /*0x02 */ 539 U8 HostIdleTime; /*0x03 */ 540 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 541 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 542 Mpi2ManPage4PwrSaveSettings_t, 543 *pMpi2ManPage4PwrSaveSettings_t; 544 545 /*defines for the PowerSaveFlags field */ 546 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 547 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 548 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 549 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 550 551 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 552 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 553 U32 Reserved1; /*0x04 */ 554 U32 Flags; /*0x08 */ 555 U8 InquirySize; /*0x0C */ 556 U8 Reserved2; /*0x0D */ 557 U16 Reserved3; /*0x0E */ 558 U8 InquiryData[56]; /*0x10 */ 559 U32 RAID0VolumeSettings; /*0x48 */ 560 U32 RAID1EVolumeSettings; /*0x4C */ 561 U32 RAID1VolumeSettings; /*0x50 */ 562 U32 RAID10VolumeSettings; /*0x54 */ 563 U32 Reserved4; /*0x58 */ 564 U32 Reserved5; /*0x5C */ 565 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 566 U8 MaxOCEDisks; /*0x64 */ 567 U8 ResyncRate; /*0x65 */ 568 U16 DataScrubDuration; /*0x66 */ 569 U8 MaxHotSpares; /*0x68 */ 570 U8 MaxPhysDisksPerVol; /*0x69 */ 571 U8 MaxPhysDisks; /*0x6A */ 572 U8 MaxVolumes; /*0x6B */ 573 } MPI2_CONFIG_PAGE_MAN_4, 574 *PTR_MPI2_CONFIG_PAGE_MAN_4, 575 Mpi2ManufacturingPage4_t, 576 *pMpi2ManufacturingPage4_t; 577 578 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 579 580 /*Manufacturing Page 4 Flags field */ 581 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 582 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 583 584 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 585 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 586 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 587 588 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 589 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 590 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 591 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 592 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 593 594 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 595 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 596 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 597 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 598 599 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 600 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 601 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 602 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 603 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 604 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 605 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 606 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 607 608 609 /*Manufacturing Page 5 */ 610 611 /* 612 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 613 *one and check the value returned for NumPhys at runtime. 614 */ 615 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 616 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 617 #endif 618 619 typedef struct _MPI2_MANUFACTURING5_ENTRY { 620 U64 WWID; /*0x00 */ 621 U64 DeviceName; /*0x08 */ 622 } MPI2_MANUFACTURING5_ENTRY, 623 *PTR_MPI2_MANUFACTURING5_ENTRY, 624 Mpi2Manufacturing5Entry_t, 625 *pMpi2Manufacturing5Entry_t; 626 627 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 628 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 629 U8 NumPhys; /*0x04 */ 630 U8 Reserved1; /*0x05 */ 631 U16 Reserved2; /*0x06 */ 632 U32 Reserved3; /*0x08 */ 633 U32 Reserved4; /*0x0C */ 634 MPI2_MANUFACTURING5_ENTRY 635 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 636 } MPI2_CONFIG_PAGE_MAN_5, 637 *PTR_MPI2_CONFIG_PAGE_MAN_5, 638 Mpi2ManufacturingPage5_t, 639 *pMpi2ManufacturingPage5_t; 640 641 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 642 643 644 /*Manufacturing Page 6 */ 645 646 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 647 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 648 U32 ProductSpecificInfo;/*0x04 */ 649 } MPI2_CONFIG_PAGE_MAN_6, 650 *PTR_MPI2_CONFIG_PAGE_MAN_6, 651 Mpi2ManufacturingPage6_t, 652 *pMpi2ManufacturingPage6_t; 653 654 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 655 656 657 /*Manufacturing Page 7 */ 658 659 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 660 U32 Pinout; /*0x00 */ 661 U8 Connector[16]; /*0x04 */ 662 U8 Location; /*0x14 */ 663 U8 ReceptacleID; /*0x15 */ 664 U16 Slot; /*0x16 */ 665 U32 Reserved2; /*0x18 */ 666 } MPI2_MANPAGE7_CONNECTOR_INFO, 667 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 668 Mpi2ManPage7ConnectorInfo_t, 669 *pMpi2ManPage7ConnectorInfo_t; 670 671 /*defines for the Pinout field */ 672 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 673 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 674 675 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 676 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 677 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 678 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 679 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 680 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 681 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 682 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 683 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 684 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 685 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 686 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 687 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 688 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 689 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 690 691 /*defines for the Location field */ 692 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 693 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 694 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 695 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 696 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 697 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 698 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 699 700 /* 701 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 702 *one and check the value returned for NumPhys at runtime. 703 */ 704 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 705 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 706 #endif 707 708 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 709 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 710 U32 Reserved1; /*0x04 */ 711 U32 Reserved2; /*0x08 */ 712 U32 Flags; /*0x0C */ 713 U8 EnclosureName[16]; /*0x10 */ 714 U8 NumPhys; /*0x20 */ 715 U8 Reserved3; /*0x21 */ 716 U16 Reserved4; /*0x22 */ 717 MPI2_MANPAGE7_CONNECTOR_INFO 718 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 719 } MPI2_CONFIG_PAGE_MAN_7, 720 *PTR_MPI2_CONFIG_PAGE_MAN_7, 721 Mpi2ManufacturingPage7_t, 722 *pMpi2ManufacturingPage7_t; 723 724 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 725 726 /*defines for the Flags field */ 727 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 728 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 729 730 731 /* 732 *Generic structure to use for product-specific manufacturing pages 733 *(currently Manufacturing Page 8 through Manufacturing Page 31). 734 */ 735 736 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 737 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 738 U32 ProductSpecificInfo;/*0x04 */ 739 } MPI2_CONFIG_PAGE_MAN_PS, 740 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 741 Mpi2ManufacturingPagePS_t, 742 *pMpi2ManufacturingPagePS_t; 743 744 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 745 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 746 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 747 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 748 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 749 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 750 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 751 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 752 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 753 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 754 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 755 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 756 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 757 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 758 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 759 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 760 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 761 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 762 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 763 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 764 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 765 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 766 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 767 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 768 769 770 /**************************************************************************** 771 * IO Unit Config Pages 772 ****************************************************************************/ 773 774 /*IO Unit Page 0 */ 775 776 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 777 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 778 U64 UniqueValue; /*0x04 */ 779 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 780 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 781 } MPI2_CONFIG_PAGE_IO_UNIT_0, 782 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 783 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 784 785 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 786 787 788 /*IO Unit Page 1 */ 789 790 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 791 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 792 U32 Flags; /*0x04 */ 793 } MPI2_CONFIG_PAGE_IO_UNIT_1, 794 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 795 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 796 797 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 798 799 /*IO Unit Page 1 Flags defines */ 800 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 801 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 802 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 803 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 804 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 805 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 806 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 807 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 808 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 809 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 810 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 811 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 812 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 813 814 815 /*IO Unit Page 3 */ 816 817 /* 818 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 819 *one and check the value returned for GPIOCount at runtime. 820 */ 821 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 822 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 823 #endif 824 825 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 826 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 827 U8 GPIOCount; /*0x04 */ 828 U8 Reserved1; /*0x05 */ 829 U16 Reserved2; /*0x06 */ 830 U16 831 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 832 } MPI2_CONFIG_PAGE_IO_UNIT_3, 833 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 834 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 835 836 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 837 838 /*defines for IO Unit Page 3 GPIOVal field */ 839 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 840 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 841 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 842 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 843 844 845 /*IO Unit Page 5 */ 846 847 /* 848 *Upper layer code (drivers, utilities, etc.) should leave this define set to 849 *one and check the value returned for NumDmaEngines at runtime. 850 */ 851 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 852 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 853 #endif 854 855 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 856 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 857 U64 858 RaidAcceleratorBufferBaseAddress; /*0x04 */ 859 U64 860 RaidAcceleratorBufferSize; /*0x0C */ 861 U64 862 RaidAcceleratorControlBaseAddress; /*0x14 */ 863 U8 RAControlSize; /*0x1C */ 864 U8 NumDmaEngines; /*0x1D */ 865 U8 RAMinControlSize; /*0x1E */ 866 U8 RAMaxControlSize; /*0x1F */ 867 U32 Reserved1; /*0x20 */ 868 U32 Reserved2; /*0x24 */ 869 U32 Reserved3; /*0x28 */ 870 U32 871 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 872 } MPI2_CONFIG_PAGE_IO_UNIT_5, 873 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 874 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 875 876 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 877 878 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 879 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 880 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 881 882 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 883 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 884 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 885 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 886 887 888 /*IO Unit Page 6 */ 889 890 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 891 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 892 U16 Flags; /*0x04 */ 893 U8 RAHostControlSize; /*0x06 */ 894 U8 Reserved0; /*0x07 */ 895 U64 896 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 897 U32 Reserved1; /*0x10 */ 898 U32 Reserved2; /*0x14 */ 899 U32 Reserved3; /*0x18 */ 900 } MPI2_CONFIG_PAGE_IO_UNIT_6, 901 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 902 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 903 904 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 905 906 /*defines for IO Unit Page 6 Flags field */ 907 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 908 909 910 /*IO Unit Page 7 */ 911 912 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 913 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 914 U8 CurrentPowerMode; /*0x04 */ 915 U8 PreviousPowerMode; /*0x05 */ 916 U8 PCIeWidth; /*0x06 */ 917 U8 PCIeSpeed; /*0x07 */ 918 U32 ProcessorState; /*0x08 */ 919 U32 920 PowerManagementCapabilities; /*0x0C */ 921 U16 IOCTemperature; /*0x10 */ 922 U8 923 IOCTemperatureUnits; /*0x12 */ 924 U8 IOCSpeed; /*0x13 */ 925 U16 BoardTemperature; /*0x14 */ 926 U8 927 BoardTemperatureUnits; /*0x16 */ 928 U8 Reserved3; /*0x17 */ 929 U32 Reserved4; /* 0x18 */ 930 U32 Reserved5; /* 0x1C */ 931 U32 Reserved6; /* 0x20 */ 932 U32 Reserved7; /* 0x24 */ 933 } MPI2_CONFIG_PAGE_IO_UNIT_7, 934 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 935 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 936 937 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04) 938 939 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 940 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 941 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 942 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 943 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 944 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 945 946 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 947 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 948 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 949 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 950 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 951 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 952 953 954 /*defines for IO Unit Page 7 PCIeWidth field */ 955 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 956 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 957 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 958 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 959 960 /*defines for IO Unit Page 7 PCIeSpeed field */ 961 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 962 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 963 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 964 965 /*defines for IO Unit Page 7 ProcessorState field */ 966 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 967 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 968 969 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 970 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 971 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 972 973 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 974 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 975 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 976 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 977 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 978 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 979 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 980 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 981 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 982 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 983 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 984 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 985 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 986 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 987 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 988 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 989 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 990 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 991 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 992 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 993 994 /*obsolete names for the PowerManagementCapabilities bits (above) */ 995 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 996 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 997 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 998 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 999 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1000 1001 1002 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1003 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1004 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1005 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1006 1007 /*defines for IO Unit Page 7 IOCSpeed field */ 1008 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1009 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1010 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1011 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1012 1013 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1014 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1015 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1016 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1017 1018 1019 /*IO Unit Page 8 */ 1020 1021 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1022 1023 typedef struct _MPI2_IOUNIT8_SENSOR { 1024 U16 Flags; /*0x00 */ 1025 U16 Reserved1; /*0x02 */ 1026 U16 1027 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1028 U32 Reserved2; /*0x0C */ 1029 U32 Reserved3; /*0x10 */ 1030 U32 Reserved4; /*0x14 */ 1031 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1032 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1033 1034 /*defines for IO Unit Page 8 Sensor Flags field */ 1035 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1036 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1037 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1038 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1039 1040 /* 1041 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1042 *one and check the value returned for NumSensors at runtime. 1043 */ 1044 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1045 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1046 #endif 1047 1048 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1049 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1050 U32 Reserved1; /*0x04 */ 1051 U32 Reserved2; /*0x08 */ 1052 U8 NumSensors; /*0x0C */ 1053 U8 PollingInterval; /*0x0D */ 1054 U16 Reserved3; /*0x0E */ 1055 MPI2_IOUNIT8_SENSOR 1056 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1057 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1058 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1059 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1060 1061 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1062 1063 1064 /*IO Unit Page 9 */ 1065 1066 typedef struct _MPI2_IOUNIT9_SENSOR { 1067 U16 CurrentTemperature; /*0x00 */ 1068 U16 Reserved1; /*0x02 */ 1069 U8 Flags; /*0x04 */ 1070 U8 Reserved2; /*0x05 */ 1071 U16 Reserved3; /*0x06 */ 1072 U32 Reserved4; /*0x08 */ 1073 U32 Reserved5; /*0x0C */ 1074 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1075 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1076 1077 /*defines for IO Unit Page 9 Sensor Flags field */ 1078 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1079 1080 /* 1081 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1082 *one and check the value returned for NumSensors at runtime. 1083 */ 1084 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1085 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1086 #endif 1087 1088 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1089 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1090 U32 Reserved1; /*0x04 */ 1091 U32 Reserved2; /*0x08 */ 1092 U8 NumSensors; /*0x0C */ 1093 U8 Reserved4; /*0x0D */ 1094 U16 Reserved3; /*0x0E */ 1095 MPI2_IOUNIT9_SENSOR 1096 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1097 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1098 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1099 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1100 1101 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1102 1103 1104 /*IO Unit Page 10 */ 1105 1106 typedef struct _MPI2_IOUNIT10_FUNCTION { 1107 U8 CreditPercent; /*0x00 */ 1108 U8 Reserved1; /*0x01 */ 1109 U16 Reserved2; /*0x02 */ 1110 } MPI2_IOUNIT10_FUNCTION, 1111 *PTR_MPI2_IOUNIT10_FUNCTION, 1112 Mpi2IOUnit10Function_t, 1113 *pMpi2IOUnit10Function_t; 1114 1115 /* 1116 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1117 *one and check the value returned for NumFunctions at runtime. 1118 */ 1119 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1120 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1121 #endif 1122 1123 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1124 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1125 U8 NumFunctions; /*0x04 */ 1126 U8 Reserved1; /*0x05 */ 1127 U16 Reserved2; /*0x06 */ 1128 U32 Reserved3; /*0x08 */ 1129 U32 Reserved4; /*0x0C */ 1130 MPI2_IOUNIT10_FUNCTION 1131 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1132 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1133 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1134 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1135 1136 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1137 1138 1139 1140 /**************************************************************************** 1141 * IOC Config Pages 1142 ****************************************************************************/ 1143 1144 /*IOC Page 0 */ 1145 1146 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1147 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1148 U32 Reserved1; /*0x04 */ 1149 U32 Reserved2; /*0x08 */ 1150 U16 VendorID; /*0x0C */ 1151 U16 DeviceID; /*0x0E */ 1152 U8 RevisionID; /*0x10 */ 1153 U8 Reserved3; /*0x11 */ 1154 U16 Reserved4; /*0x12 */ 1155 U32 ClassCode; /*0x14 */ 1156 U16 SubsystemVendorID; /*0x18 */ 1157 U16 SubsystemID; /*0x1A */ 1158 } MPI2_CONFIG_PAGE_IOC_0, 1159 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1160 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1161 1162 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1163 1164 1165 /*IOC Page 1 */ 1166 1167 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1168 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1169 U32 Flags; /*0x04 */ 1170 U32 CoalescingTimeout; /*0x08 */ 1171 U8 CoalescingDepth; /*0x0C */ 1172 U8 PCISlotNum; /*0x0D */ 1173 U8 PCIBusNum; /*0x0E */ 1174 U8 PCIDomainSegment; /*0x0F */ 1175 U32 Reserved1; /*0x10 */ 1176 U32 Reserved2; /*0x14 */ 1177 } MPI2_CONFIG_PAGE_IOC_1, 1178 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1179 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1180 1181 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1182 1183 /*defines for IOC Page 1 Flags field */ 1184 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1185 1186 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1187 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1188 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1189 1190 /*IOC Page 6 */ 1191 1192 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1193 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1194 U32 1195 CapabilitiesFlags; /*0x04 */ 1196 U8 MaxDrivesRAID0; /*0x08 */ 1197 U8 MaxDrivesRAID1; /*0x09 */ 1198 U8 1199 MaxDrivesRAID1E; /*0x0A */ 1200 U8 1201 MaxDrivesRAID10; /*0x0B */ 1202 U8 MinDrivesRAID0; /*0x0C */ 1203 U8 MinDrivesRAID1; /*0x0D */ 1204 U8 1205 MinDrivesRAID1E; /*0x0E */ 1206 U8 1207 MinDrivesRAID10; /*0x0F */ 1208 U32 Reserved1; /*0x10 */ 1209 U8 1210 MaxGlobalHotSpares; /*0x14 */ 1211 U8 MaxPhysDisks; /*0x15 */ 1212 U8 MaxVolumes; /*0x16 */ 1213 U8 MaxConfigs; /*0x17 */ 1214 U8 MaxOCEDisks; /*0x18 */ 1215 U8 Reserved2; /*0x19 */ 1216 U16 Reserved3; /*0x1A */ 1217 U32 1218 SupportedStripeSizeMapRAID0; /*0x1C */ 1219 U32 1220 SupportedStripeSizeMapRAID1E; /*0x20 */ 1221 U32 1222 SupportedStripeSizeMapRAID10; /*0x24 */ 1223 U32 Reserved4; /*0x28 */ 1224 U32 Reserved5; /*0x2C */ 1225 U16 1226 DefaultMetadataSize; /*0x30 */ 1227 U16 Reserved6; /*0x32 */ 1228 U16 1229 MaxBadBlockTableEntries; /*0x34 */ 1230 U16 Reserved7; /*0x36 */ 1231 U32 1232 IRNvsramVersion; /*0x38 */ 1233 } MPI2_CONFIG_PAGE_IOC_6, 1234 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1235 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1236 1237 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1238 1239 /*defines for IOC Page 6 CapabilitiesFlags */ 1240 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1241 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1242 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1243 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1244 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1245 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1246 1247 1248 /*IOC Page 7 */ 1249 1250 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1251 1252 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1253 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1254 U32 Reserved1; /*0x04 */ 1255 U32 1256 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1257 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1258 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1259 U32 Reserved3; /*0x1C */ 1260 } MPI2_CONFIG_PAGE_IOC_7, 1261 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1262 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1263 1264 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1265 1266 1267 /*IOC Page 8 */ 1268 1269 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1270 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1271 U8 NumDevsPerEnclosure; /*0x04 */ 1272 U8 Reserved1; /*0x05 */ 1273 U16 Reserved2; /*0x06 */ 1274 U16 MaxPersistentEntries; /*0x08 */ 1275 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1276 U16 Flags; /*0x0C */ 1277 U16 Reserved3; /*0x0E */ 1278 U16 IRVolumeMappingFlags; /*0x10 */ 1279 U16 Reserved4; /*0x12 */ 1280 U32 Reserved5; /*0x14 */ 1281 } MPI2_CONFIG_PAGE_IOC_8, 1282 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1283 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1284 1285 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1286 1287 /*defines for IOC Page 8 Flags field */ 1288 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1289 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1290 1291 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1292 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1293 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1294 1295 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1296 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1297 1298 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1299 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1300 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1301 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1302 1303 1304 /**************************************************************************** 1305 * BIOS Config Pages 1306 ****************************************************************************/ 1307 1308 /*BIOS Page 1 */ 1309 1310 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1311 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1312 U32 BiosOptions; /*0x04 */ 1313 U32 IOCSettings; /*0x08 */ 1314 U32 Reserved1; /*0x0C */ 1315 U32 DeviceSettings; /*0x10 */ 1316 U16 NumberOfDevices; /*0x14 */ 1317 U16 UEFIVersion; /*0x16 */ 1318 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1319 U16 IOTimeoutSequential; /*0x1A */ 1320 U16 IOTimeoutOther; /*0x1C */ 1321 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1322 } MPI2_CONFIG_PAGE_BIOS_1, 1323 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1324 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1325 1326 #define MPI2_BIOSPAGE1_PAGEVERSION (0x05) 1327 1328 /*values for BIOS Page 1 BiosOptions field */ 1329 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1330 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1331 1332 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1333 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1334 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1335 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1336 1337 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1338 1339 /*values for BIOS Page 1 IOCSettings field */ 1340 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1341 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1342 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1343 1344 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1345 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1346 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1347 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1348 1349 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1350 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1351 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1352 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1353 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1354 1355 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1356 1357 /*values for BIOS Page 1 DeviceSettings field */ 1358 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1359 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1360 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1361 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1362 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1363 1364 /*defines for BIOS Page 1 UEFIVersion field */ 1365 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1366 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1367 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1368 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1369 1370 1371 1372 /*BIOS Page 2 */ 1373 1374 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1375 U32 Reserved1; /*0x00 */ 1376 U32 Reserved2; /*0x04 */ 1377 U32 Reserved3; /*0x08 */ 1378 U32 Reserved4; /*0x0C */ 1379 U32 Reserved5; /*0x10 */ 1380 U32 Reserved6; /*0x14 */ 1381 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1382 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1383 Mpi2BootDeviceAdapterOrder_t, 1384 *pMpi2BootDeviceAdapterOrder_t; 1385 1386 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1387 U64 SASAddress; /*0x00 */ 1388 U8 LUN[8]; /*0x08 */ 1389 U32 Reserved1; /*0x10 */ 1390 U32 Reserved2; /*0x14 */ 1391 } MPI2_BOOT_DEVICE_SAS_WWID, 1392 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1393 Mpi2BootDeviceSasWwid_t, 1394 *pMpi2BootDeviceSasWwid_t; 1395 1396 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1397 U64 EnclosureLogicalID; /*0x00 */ 1398 U32 Reserved1; /*0x08 */ 1399 U32 Reserved2; /*0x0C */ 1400 U16 SlotNumber; /*0x10 */ 1401 U16 Reserved3; /*0x12 */ 1402 U32 Reserved4; /*0x14 */ 1403 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1404 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1405 Mpi2BootDeviceEnclosureSlot_t, 1406 *pMpi2BootDeviceEnclosureSlot_t; 1407 1408 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1409 U64 DeviceName; /*0x00 */ 1410 U8 LUN[8]; /*0x08 */ 1411 U32 Reserved1; /*0x10 */ 1412 U32 Reserved2; /*0x14 */ 1413 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1414 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1415 Mpi2BootDeviceDeviceName_t, 1416 *pMpi2BootDeviceDeviceName_t; 1417 1418 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1419 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1420 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1421 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1422 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1423 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1424 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1425 Mpi2BiosPage2BootDevice_t, 1426 *pMpi2BiosPage2BootDevice_t; 1427 1428 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1429 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1430 U32 Reserved1; /*0x04 */ 1431 U32 Reserved2; /*0x08 */ 1432 U32 Reserved3; /*0x0C */ 1433 U32 Reserved4; /*0x10 */ 1434 U32 Reserved5; /*0x14 */ 1435 U32 Reserved6; /*0x18 */ 1436 U8 ReqBootDeviceForm; /*0x1C */ 1437 U8 Reserved7; /*0x1D */ 1438 U16 Reserved8; /*0x1E */ 1439 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1440 U8 ReqAltBootDeviceForm; /*0x38 */ 1441 U8 Reserved9; /*0x39 */ 1442 U16 Reserved10; /*0x3A */ 1443 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1444 U8 CurrentBootDeviceForm; /*0x58 */ 1445 U8 Reserved11; /*0x59 */ 1446 U16 Reserved12; /*0x5A */ 1447 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1448 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1449 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1450 1451 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1452 1453 /*values for BIOS Page 2 BootDeviceForm fields */ 1454 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1455 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1456 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1457 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1458 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1459 1460 1461 /*BIOS Page 3 */ 1462 1463 typedef struct _MPI2_ADAPTER_INFO { 1464 U8 PciBusNumber; /*0x00 */ 1465 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1466 U16 AdapterFlags; /*0x02 */ 1467 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1468 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1469 1470 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1471 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1472 1473 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1474 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1475 U32 GlobalFlags; /*0x04 */ 1476 U32 BiosVersion; /*0x08 */ 1477 MPI2_ADAPTER_INFO AdapterOrder[4]; /*0x0C */ 1478 U32 Reserved1; /*0x1C */ 1479 } MPI2_CONFIG_PAGE_BIOS_3, 1480 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1481 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1482 1483 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1484 1485 /*values for BIOS Page 3 GlobalFlags */ 1486 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1487 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1488 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1489 1490 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1491 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1492 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1493 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1494 1495 1496 /*BIOS Page 4 */ 1497 1498 /* 1499 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1500 *one and check the value returned for NumPhys at runtime. 1501 */ 1502 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1503 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1504 #endif 1505 1506 typedef struct _MPI2_BIOS4_ENTRY { 1507 U64 ReassignmentWWID; /*0x00 */ 1508 U64 ReassignmentDeviceName; /*0x08 */ 1509 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1510 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1511 1512 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1513 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1514 U8 NumPhys; /*0x04 */ 1515 U8 Reserved1; /*0x05 */ 1516 U16 Reserved2; /*0x06 */ 1517 MPI2_BIOS4_ENTRY 1518 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1519 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1520 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1521 1522 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1523 1524 1525 /**************************************************************************** 1526 * RAID Volume Config Pages 1527 ****************************************************************************/ 1528 1529 /*RAID Volume Page 0 */ 1530 1531 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1532 U8 RAIDSetNum; /*0x00 */ 1533 U8 PhysDiskMap; /*0x01 */ 1534 U8 PhysDiskNum; /*0x02 */ 1535 U8 Reserved; /*0x03 */ 1536 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1537 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1538 1539 /*defines for the PhysDiskMap field */ 1540 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1541 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1542 1543 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1544 U16 Settings; /*0x00 */ 1545 U8 HotSparePool; /*0x01 */ 1546 U8 Reserved; /*0x02 */ 1547 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1548 Mpi2RaidVol0Settings_t, 1549 *pMpi2RaidVol0Settings_t; 1550 1551 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1552 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1553 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1554 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1555 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1556 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1557 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1558 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1559 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1560 1561 /*RAID Volume Page 0 VolumeSettings defines */ 1562 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1563 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1564 1565 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1566 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1567 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1568 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1569 1570 /* 1571 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1572 *one and check the value returned for NumPhysDisks at runtime. 1573 */ 1574 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1575 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1576 #endif 1577 1578 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1579 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1580 U16 DevHandle; /*0x04 */ 1581 U8 VolumeState; /*0x06 */ 1582 U8 VolumeType; /*0x07 */ 1583 U32 VolumeStatusFlags; /*0x08 */ 1584 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1585 U64 MaxLBA; /*0x10 */ 1586 U32 StripeSize; /*0x18 */ 1587 U16 BlockSize; /*0x1C */ 1588 U16 Reserved1; /*0x1E */ 1589 U8 SupportedPhysDisks;/*0x20 */ 1590 U8 ResyncRate; /*0x21 */ 1591 U16 DataScrubDuration; /*0x22 */ 1592 U8 NumPhysDisks; /*0x24 */ 1593 U8 Reserved2; /*0x25 */ 1594 U8 Reserved3; /*0x26 */ 1595 U8 InactiveStatus; /*0x27 */ 1596 MPI2_RAIDVOL0_PHYS_DISK 1597 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1598 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1599 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1600 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1601 1602 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1603 1604 /*values for RAID VolumeState */ 1605 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1606 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1607 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1608 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1609 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1610 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1611 1612 /*values for RAID VolumeType */ 1613 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1614 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1615 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1616 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1617 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1618 1619 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1620 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1621 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1622 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1623 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1624 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1625 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1626 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1627 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1628 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1629 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1630 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1631 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1632 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1633 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1634 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1635 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1636 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1637 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1638 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1639 1640 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1641 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1642 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1643 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1644 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1645 1646 /*values for RAID Volume Page 0 InactiveStatus field */ 1647 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1648 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1649 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1650 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1651 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1652 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1653 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1654 1655 1656 /*RAID Volume Page 1 */ 1657 1658 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1659 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1660 U16 DevHandle; /*0x04 */ 1661 U16 Reserved0; /*0x06 */ 1662 U8 GUID[24]; /*0x08 */ 1663 U8 Name[16]; /*0x20 */ 1664 U64 WWID; /*0x30 */ 1665 U32 Reserved1; /*0x38 */ 1666 U32 Reserved2; /*0x3C */ 1667 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1668 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1669 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1670 1671 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1672 1673 1674 /**************************************************************************** 1675 * RAID Physical Disk Config Pages 1676 ****************************************************************************/ 1677 1678 /*RAID Physical Disk Page 0 */ 1679 1680 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1681 U16 Reserved1; /*0x00 */ 1682 U8 HotSparePool; /*0x02 */ 1683 U8 Reserved2; /*0x03 */ 1684 } MPI2_RAIDPHYSDISK0_SETTINGS, 1685 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1686 Mpi2RaidPhysDisk0Settings_t, 1687 *pMpi2RaidPhysDisk0Settings_t; 1688 1689 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1690 1691 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1692 U8 VendorID[8]; /*0x00 */ 1693 U8 ProductID[16]; /*0x08 */ 1694 U8 ProductRevLevel[4]; /*0x18 */ 1695 U8 SerialNum[32]; /*0x1C */ 1696 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1697 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1698 Mpi2RaidPhysDisk0InquiryData_t, 1699 *pMpi2RaidPhysDisk0InquiryData_t; 1700 1701 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1702 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1703 U16 DevHandle; /*0x04 */ 1704 U8 Reserved1; /*0x06 */ 1705 U8 PhysDiskNum; /*0x07 */ 1706 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1707 U32 Reserved2; /*0x0C */ 1708 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1709 U32 Reserved3; /*0x4C */ 1710 U8 PhysDiskState; /*0x50 */ 1711 U8 OfflineReason; /*0x51 */ 1712 U8 IncompatibleReason; /*0x52 */ 1713 U8 PhysDiskAttributes; /*0x53 */ 1714 U32 PhysDiskStatusFlags;/*0x54 */ 1715 U64 DeviceMaxLBA; /*0x58 */ 1716 U64 HostMaxLBA; /*0x60 */ 1717 U64 CoercedMaxLBA; /*0x68 */ 1718 U16 BlockSize; /*0x70 */ 1719 U16 Reserved5; /*0x72 */ 1720 U32 Reserved6; /*0x74 */ 1721 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1722 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1723 Mpi2RaidPhysDiskPage0_t, 1724 *pMpi2RaidPhysDiskPage0_t; 1725 1726 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1727 1728 /*PhysDiskState defines */ 1729 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1730 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1731 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1732 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1733 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1734 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1735 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1736 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1737 1738 /*OfflineReason defines */ 1739 #define MPI2_PHYSDISK0_ONLINE (0x00) 1740 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1741 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1742 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1743 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1744 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1745 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1746 1747 /*IncompatibleReason defines */ 1748 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1749 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1750 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1751 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1752 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1753 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1754 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1755 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1756 1757 /*PhysDiskAttributes defines */ 1758 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1759 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1760 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1761 1762 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1763 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1764 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1765 1766 /*PhysDiskStatusFlags defines */ 1767 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1768 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1769 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1770 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1771 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1772 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1773 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1774 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1775 1776 1777 /*RAID Physical Disk Page 1 */ 1778 1779 /* 1780 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1781 *one and check the value returned for NumPhysDiskPaths at runtime. 1782 */ 1783 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1784 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1785 #endif 1786 1787 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 1788 U16 DevHandle; /*0x00 */ 1789 U16 Reserved1; /*0x02 */ 1790 U64 WWID; /*0x04 */ 1791 U64 OwnerWWID; /*0x0C */ 1792 U8 OwnerIdentifier; /*0x14 */ 1793 U8 Reserved2; /*0x15 */ 1794 U16 Flags; /*0x16 */ 1795 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 1796 Mpi2RaidPhysDisk1Path_t, 1797 *pMpi2RaidPhysDisk1Path_t; 1798 1799 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1800 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1801 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1802 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1803 1804 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 1805 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1806 U8 NumPhysDiskPaths; /*0x04 */ 1807 U8 PhysDiskNum; /*0x05 */ 1808 U16 Reserved1; /*0x06 */ 1809 U32 Reserved2; /*0x08 */ 1810 MPI2_RAIDPHYSDISK1_PATH 1811 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 1812 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1813 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1814 Mpi2RaidPhysDiskPage1_t, 1815 *pMpi2RaidPhysDiskPage1_t; 1816 1817 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1818 1819 1820 /**************************************************************************** 1821 * values for fields used by several types of SAS Config Pages 1822 ****************************************************************************/ 1823 1824 /*values for NegotiatedLinkRates fields */ 1825 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1826 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1827 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1828 /*link rates used for Negotiated Physical and Logical Link Rate */ 1829 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1830 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1831 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1832 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1833 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1834 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1835 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1836 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1837 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1838 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1839 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1840 1841 1842 /*values for AttachedPhyInfo fields */ 1843 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1844 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1845 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1846 1847 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1848 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1849 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1850 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1851 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1852 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1853 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1854 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1855 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1856 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1857 1858 1859 /*values for PhyInfo fields */ 1860 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1861 1862 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1863 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1864 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1865 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1866 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1867 1868 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1869 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1870 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1871 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1872 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1873 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1874 1875 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1876 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1877 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1878 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1879 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1880 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1881 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1882 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1883 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1884 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1885 1886 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1887 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1888 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1889 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1890 1891 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1892 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1893 1894 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1895 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1896 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1897 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1898 1899 1900 /*values for SAS ProgrammedLinkRate fields */ 1901 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1902 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1903 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1904 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1905 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1906 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 1907 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1908 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1909 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1910 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1911 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1912 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 1913 1914 1915 /*values for SAS HwLinkRate fields */ 1916 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1917 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1918 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1919 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1920 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 1921 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1922 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1923 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1924 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1925 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 1926 1927 1928 1929 /**************************************************************************** 1930 * SAS IO Unit Config Pages 1931 ****************************************************************************/ 1932 1933 /*SAS IO Unit Page 0 */ 1934 1935 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 1936 U8 Port; /*0x00 */ 1937 U8 PortFlags; /*0x01 */ 1938 U8 PhyFlags; /*0x02 */ 1939 U8 NegotiatedLinkRate; /*0x03 */ 1940 U32 ControllerPhyDeviceInfo;/*0x04 */ 1941 U16 AttachedDevHandle; /*0x08 */ 1942 U16 ControllerDevHandle; /*0x0A */ 1943 U32 DiscoveryStatus; /*0x0C */ 1944 U32 Reserved; /*0x10 */ 1945 } MPI2_SAS_IO_UNIT0_PHY_DATA, 1946 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1947 Mpi2SasIOUnit0PhyData_t, 1948 *pMpi2SasIOUnit0PhyData_t; 1949 1950 /* 1951 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1952 *one and check the value returned for NumPhys at runtime. 1953 */ 1954 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1955 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1956 #endif 1957 1958 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 1959 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 1960 U32 Reserved1;/*0x08 */ 1961 U8 NumPhys; /*0x0C */ 1962 U8 Reserved2;/*0x0D */ 1963 U16 Reserved3;/*0x0E */ 1964 MPI2_SAS_IO_UNIT0_PHY_DATA 1965 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 1966 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1967 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1968 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 1969 1970 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1971 1972 /*values for SAS IO Unit Page 0 PortFlags */ 1973 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1974 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1975 1976 /*values for SAS IO Unit Page 0 PhyFlags */ 1977 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1978 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1979 1980 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1981 1982 /*see mpi2_sas.h for values for 1983 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1984 1985 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 1986 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1987 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1988 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1989 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1990 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1991 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1992 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1993 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1994 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1995 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1996 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1997 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1998 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1999 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2000 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2001 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2002 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2003 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2004 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2005 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2006 2007 2008 /*SAS IO Unit Page 1 */ 2009 2010 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2011 U8 Port; /*0x00 */ 2012 U8 PortFlags; /*0x01 */ 2013 U8 PhyFlags; /*0x02 */ 2014 U8 MaxMinLinkRate; /*0x03 */ 2015 U32 ControllerPhyDeviceInfo; /*0x04 */ 2016 U16 MaxTargetPortConnectTime; /*0x08 */ 2017 U16 Reserved1; /*0x0A */ 2018 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2019 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2020 Mpi2SasIOUnit1PhyData_t, 2021 *pMpi2SasIOUnit1PhyData_t; 2022 2023 /* 2024 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2025 *one and check the value returned for NumPhys at runtime. 2026 */ 2027 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2028 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2029 #endif 2030 2031 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2032 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2033 U16 2034 ControlFlags; /*0x08 */ 2035 U16 2036 SASNarrowMaxQueueDepth; /*0x0A */ 2037 U16 2038 AdditionalControlFlags; /*0x0C */ 2039 U16 2040 SASWideMaxQueueDepth; /*0x0E */ 2041 U8 2042 NumPhys; /*0x10 */ 2043 U8 2044 SATAMaxQDepth; /*0x11 */ 2045 U8 2046 ReportDeviceMissingDelay; /*0x12 */ 2047 U8 2048 IODeviceMissingDelay; /*0x13 */ 2049 MPI2_SAS_IO_UNIT1_PHY_DATA 2050 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2051 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2052 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2053 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2054 2055 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2056 2057 /*values for SAS IO Unit Page 1 ControlFlags */ 2058 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2059 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2060 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2061 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2062 2063 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2064 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2065 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2066 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2067 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2068 2069 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2070 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2071 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2072 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2073 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2074 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2075 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2076 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2077 2078 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2079 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2080 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2081 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2082 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2083 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2084 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2085 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2086 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2087 2088 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2089 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2090 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2091 2092 /*values for SAS IO Unit Page 1 PortFlags */ 2093 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2094 2095 /*values for SAS IO Unit Page 1 PhyFlags */ 2096 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2097 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2098 2099 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2100 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2101 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2102 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2103 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2104 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2105 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2106 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2107 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2108 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2109 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2110 2111 /*see mpi2_sas.h for values for 2112 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2113 2114 2115 /*SAS IO Unit Page 4 */ 2116 2117 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2118 U8 MaxTargetSpinup; /*0x00 */ 2119 U8 SpinupDelay; /*0x01 */ 2120 U8 SpinupFlags; /*0x02 */ 2121 U8 Reserved1; /*0x03 */ 2122 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2123 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2124 Mpi2SasIOUnit4SpinupGroup_t, 2125 *pMpi2SasIOUnit4SpinupGroup_t; 2126 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2127 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2128 2129 2130 /* 2131 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2132 *one and check the value returned for NumPhys at runtime. 2133 */ 2134 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2135 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2136 #endif 2137 2138 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2139 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2140 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2141 SpinupGroupParameters[4]; /*0x08 */ 2142 U32 2143 Reserved1; /*0x18 */ 2144 U32 2145 Reserved2; /*0x1C */ 2146 U32 2147 Reserved3; /*0x20 */ 2148 U8 2149 BootDeviceWaitTime; /*0x24 */ 2150 U8 2151 Reserved4; /*0x25 */ 2152 U16 2153 Reserved5; /*0x26 */ 2154 U8 2155 NumPhys; /*0x28 */ 2156 U8 2157 PEInitialSpinupDelay; /*0x29 */ 2158 U8 2159 PEReplyDelay; /*0x2A */ 2160 U8 2161 Flags; /*0x2B */ 2162 U8 2163 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2164 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2165 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2166 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2167 2168 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2169 2170 /*defines for Flags field */ 2171 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2172 2173 /*defines for PHY field */ 2174 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2175 2176 2177 /*SAS IO Unit Page 5 */ 2178 2179 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2180 U8 ControlFlags; /*0x00 */ 2181 U8 PortWidthModGroup; /*0x01 */ 2182 U16 InactivityTimerExponent; /*0x02 */ 2183 U8 SATAPartialTimeout; /*0x04 */ 2184 U8 Reserved2; /*0x05 */ 2185 U8 SATASlumberTimeout; /*0x06 */ 2186 U8 Reserved3; /*0x07 */ 2187 U8 SASPartialTimeout; /*0x08 */ 2188 U8 Reserved4; /*0x09 */ 2189 U8 SASSlumberTimeout; /*0x0A */ 2190 U8 Reserved5; /*0x0B */ 2191 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2192 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2193 Mpi2SasIOUnit5PhyPmSettings_t, 2194 *pMpi2SasIOUnit5PhyPmSettings_t; 2195 2196 /*defines for ControlFlags field */ 2197 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2198 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2199 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2200 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2201 2202 /*defines for PortWidthModeGroup field */ 2203 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2204 2205 /*defines for InactivityTimerExponent field */ 2206 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2207 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2208 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2209 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2210 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2211 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2212 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2213 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2214 2215 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2216 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2217 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2218 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2219 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2220 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2221 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2222 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2223 2224 /* 2225 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2226 *one and check the value returned for NumPhys at runtime. 2227 */ 2228 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2229 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2230 #endif 2231 2232 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2233 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2234 U8 NumPhys; /*0x08 */ 2235 U8 Reserved1;/*0x09 */ 2236 U16 Reserved2;/*0x0A */ 2237 U32 Reserved3;/*0x0C */ 2238 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2239 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2240 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2241 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2242 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2243 2244 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2245 2246 2247 /*SAS IO Unit Page 6 */ 2248 2249 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2250 U8 CurrentStatus; /*0x00 */ 2251 U8 CurrentModulation; /*0x01 */ 2252 U8 CurrentUtilization; /*0x02 */ 2253 U8 Reserved1; /*0x03 */ 2254 U32 Reserved2; /*0x04 */ 2255 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2256 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2257 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2258 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2259 2260 /*defines for CurrentStatus field */ 2261 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2262 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2263 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2264 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2265 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2266 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2267 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2268 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2269 2270 /*defines for CurrentModulation field */ 2271 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2272 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2273 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2274 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2275 2276 /* 2277 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2278 *one and check the value returned for NumGroups at runtime. 2279 */ 2280 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2281 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2282 #endif 2283 2284 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2285 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2286 U32 Reserved1; /*0x08 */ 2287 U32 Reserved2; /*0x0C */ 2288 U8 NumGroups; /*0x10 */ 2289 U8 Reserved3; /*0x11 */ 2290 U16 Reserved4; /*0x12 */ 2291 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2292 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2293 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2294 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2295 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2296 2297 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2298 2299 2300 /*SAS IO Unit Page 7 */ 2301 2302 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2303 U8 Flags; /*0x00 */ 2304 U8 Reserved1; /*0x01 */ 2305 U16 Reserved2; /*0x02 */ 2306 U8 Threshold75Pct; /*0x04 */ 2307 U8 Threshold50Pct; /*0x05 */ 2308 U8 Threshold25Pct; /*0x06 */ 2309 U8 Reserved3; /*0x07 */ 2310 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2311 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2312 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2313 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2314 2315 /*defines for Flags field */ 2316 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2317 2318 2319 /* 2320 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2321 *one and check the value returned for NumGroups at runtime. 2322 */ 2323 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2324 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2325 #endif 2326 2327 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2328 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2329 U8 SamplingInterval; /*0x08 */ 2330 U8 WindowLength; /*0x09 */ 2331 U16 Reserved1; /*0x0A */ 2332 U32 Reserved2; /*0x0C */ 2333 U32 Reserved3; /*0x10 */ 2334 U8 NumGroups; /*0x14 */ 2335 U8 Reserved4; /*0x15 */ 2336 U16 Reserved5; /*0x16 */ 2337 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2338 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2339 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2340 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2341 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2342 2343 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2344 2345 2346 /*SAS IO Unit Page 8 */ 2347 2348 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2349 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2350 Header; /*0x00 */ 2351 U32 2352 Reserved1; /*0x08 */ 2353 U32 2354 PowerManagementCapabilities; /*0x0C */ 2355 U8 2356 TxRxSleepStatus; /*0x10 */ 2357 U8 2358 Reserved2; /*0x11 */ 2359 U16 2360 Reserved3; /*0x12 */ 2361 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2362 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2363 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2364 2365 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2366 2367 /*defines for PowerManagementCapabilities field */ 2368 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2369 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2370 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2371 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2372 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2373 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2374 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2375 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2376 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2377 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2378 2379 /*defines for TxRxSleepStatus field */ 2380 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2381 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2382 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2383 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2384 2385 2386 2387 /*SAS IO Unit Page 16 */ 2388 2389 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2390 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2391 Header; /*0x00 */ 2392 U64 2393 TimeStamp; /*0x08 */ 2394 U32 2395 Reserved1; /*0x10 */ 2396 U32 2397 Reserved2; /*0x14 */ 2398 U32 2399 FastPathPendedRequests; /*0x18 */ 2400 U32 2401 FastPathUnPendedRequests; /*0x1C */ 2402 U32 2403 FastPathHostRequestStarts; /*0x20 */ 2404 U32 2405 FastPathFirmwareRequestStarts; /*0x24 */ 2406 U32 2407 FastPathHostCompletions; /*0x28 */ 2408 U32 2409 FastPathFirmwareCompletions; /*0x2C */ 2410 U32 2411 NonFastPathRequestStarts; /*0x30 */ 2412 U32 2413 NonFastPathHostCompletions; /*0x30 */ 2414 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2415 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2416 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2417 2418 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2419 2420 2421 /**************************************************************************** 2422 * SAS Expander Config Pages 2423 ****************************************************************************/ 2424 2425 /*SAS Expander Page 0 */ 2426 2427 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2428 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2429 Header; /*0x00 */ 2430 U8 2431 PhysicalPort; /*0x08 */ 2432 U8 2433 ReportGenLength; /*0x09 */ 2434 U16 2435 EnclosureHandle; /*0x0A */ 2436 U64 2437 SASAddress; /*0x0C */ 2438 U32 2439 DiscoveryStatus; /*0x14 */ 2440 U16 2441 DevHandle; /*0x18 */ 2442 U16 2443 ParentDevHandle; /*0x1A */ 2444 U16 2445 ExpanderChangeCount; /*0x1C */ 2446 U16 2447 ExpanderRouteIndexes; /*0x1E */ 2448 U8 2449 NumPhys; /*0x20 */ 2450 U8 2451 SASLevel; /*0x21 */ 2452 U16 2453 Flags; /*0x22 */ 2454 U16 2455 STPBusInactivityTimeLimit; /*0x24 */ 2456 U16 2457 STPMaxConnectTimeLimit; /*0x26 */ 2458 U16 2459 STP_SMP_NexusLossTime; /*0x28 */ 2460 U16 2461 MaxNumRoutedSasAddresses; /*0x2A */ 2462 U64 2463 ActiveZoneManagerSASAddress;/*0x2C */ 2464 U16 2465 ZoneLockInactivityLimit; /*0x34 */ 2466 U16 2467 Reserved1; /*0x36 */ 2468 U8 2469 TimeToReducedFunc; /*0x38 */ 2470 U8 2471 InitialTimeToReducedFunc; /*0x39 */ 2472 U8 2473 MaxReducedFuncTime; /*0x3A */ 2474 U8 2475 Reserved2; /*0x3B */ 2476 } MPI2_CONFIG_PAGE_EXPANDER_0, 2477 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2478 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2479 2480 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2481 2482 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2483 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2484 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2485 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2486 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2487 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2488 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2489 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2490 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2491 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2492 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2493 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2494 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2495 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2496 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2497 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2498 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2499 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2500 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2501 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2502 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2503 2504 /*values for SAS Expander Page 0 Flags field */ 2505 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2506 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2507 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2508 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2509 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2510 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2511 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2512 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2513 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2514 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2515 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2516 2517 2518 /*SAS Expander Page 1 */ 2519 2520 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2521 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2522 Header; /*0x00 */ 2523 U8 2524 PhysicalPort; /*0x08 */ 2525 U8 2526 Reserved1; /*0x09 */ 2527 U16 2528 Reserved2; /*0x0A */ 2529 U8 2530 NumPhys; /*0x0C */ 2531 U8 2532 Phy; /*0x0D */ 2533 U16 2534 NumTableEntriesProgrammed; /*0x0E */ 2535 U8 2536 ProgrammedLinkRate; /*0x10 */ 2537 U8 2538 HwLinkRate; /*0x11 */ 2539 U16 2540 AttachedDevHandle; /*0x12 */ 2541 U32 2542 PhyInfo; /*0x14 */ 2543 U32 2544 AttachedDeviceInfo; /*0x18 */ 2545 U16 2546 ExpanderDevHandle; /*0x1C */ 2547 U8 2548 ChangeCount; /*0x1E */ 2549 U8 2550 NegotiatedLinkRate; /*0x1F */ 2551 U8 2552 PhyIdentifier; /*0x20 */ 2553 U8 2554 AttachedPhyIdentifier; /*0x21 */ 2555 U8 2556 Reserved3; /*0x22 */ 2557 U8 2558 DiscoveryInfo; /*0x23 */ 2559 U32 2560 AttachedPhyInfo; /*0x24 */ 2561 U8 2562 ZoneGroup; /*0x28 */ 2563 U8 2564 SelfConfigStatus; /*0x29 */ 2565 U16 2566 Reserved4; /*0x2A */ 2567 } MPI2_CONFIG_PAGE_EXPANDER_1, 2568 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2569 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2570 2571 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2572 2573 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2574 2575 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2576 2577 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2578 2579 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2580 *used for the AttachedDeviceInfo field */ 2581 2582 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2583 2584 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2585 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2586 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2587 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2588 2589 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2590 2591 2592 /**************************************************************************** 2593 * SAS Device Config Pages 2594 ****************************************************************************/ 2595 2596 /*SAS Device Page 0 */ 2597 2598 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2599 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2600 Header; /*0x00 */ 2601 U16 2602 Slot; /*0x08 */ 2603 U16 2604 EnclosureHandle; /*0x0A */ 2605 U64 2606 SASAddress; /*0x0C */ 2607 U16 2608 ParentDevHandle; /*0x14 */ 2609 U8 2610 PhyNum; /*0x16 */ 2611 U8 2612 AccessStatus; /*0x17 */ 2613 U16 2614 DevHandle; /*0x18 */ 2615 U8 2616 AttachedPhyIdentifier; /*0x1A */ 2617 U8 2618 ZoneGroup; /*0x1B */ 2619 U32 2620 DeviceInfo; /*0x1C */ 2621 U16 2622 Flags; /*0x20 */ 2623 U8 2624 PhysicalPort; /*0x22 */ 2625 U8 2626 MaxPortConnections; /*0x23 */ 2627 U64 2628 DeviceName; /*0x24 */ 2629 U8 2630 PortGroups; /*0x2C */ 2631 U8 2632 DmaGroup; /*0x2D */ 2633 U8 2634 ControlGroup; /*0x2E */ 2635 U8 2636 Reserved1; /*0x2F */ 2637 U32 2638 Reserved2; /*0x30 */ 2639 U32 2640 Reserved3; /*0x34 */ 2641 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2642 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2643 Mpi2SasDevicePage0_t, 2644 *pMpi2SasDevicePage0_t; 2645 2646 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2647 2648 /*values for SAS Device Page 0 AccessStatus field */ 2649 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2650 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2651 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2652 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2653 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2654 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2655 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2656 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2657 /*specific values for SATA Init failures */ 2658 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2659 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2660 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2661 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2662 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2663 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2664 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2665 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2666 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2667 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2668 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2669 2670 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2671 2672 /*values for SAS Device Page 0 Flags field */ 2673 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2674 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2675 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2676 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2677 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2678 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2679 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2680 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2681 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2682 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2683 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2684 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2685 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2686 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2687 2688 2689 /*SAS Device Page 1 */ 2690 2691 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2692 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2693 Header; /*0x00 */ 2694 U32 2695 Reserved1; /*0x08 */ 2696 U64 2697 SASAddress; /*0x0C */ 2698 U32 2699 Reserved2; /*0x14 */ 2700 U16 2701 DevHandle; /*0x18 */ 2702 U16 2703 Reserved3; /*0x1A */ 2704 U8 2705 InitialRegDeviceFIS[20];/*0x1C */ 2706 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2707 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2708 Mpi2SasDevicePage1_t, 2709 *pMpi2SasDevicePage1_t; 2710 2711 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2712 2713 2714 /**************************************************************************** 2715 * SAS PHY Config Pages 2716 ****************************************************************************/ 2717 2718 /*SAS PHY Page 0 */ 2719 2720 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2721 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2722 Header; /*0x00 */ 2723 U16 2724 OwnerDevHandle; /*0x08 */ 2725 U16 2726 Reserved1; /*0x0A */ 2727 U16 2728 AttachedDevHandle; /*0x0C */ 2729 U8 2730 AttachedPhyIdentifier; /*0x0E */ 2731 U8 2732 Reserved2; /*0x0F */ 2733 U32 2734 AttachedPhyInfo; /*0x10 */ 2735 U8 2736 ProgrammedLinkRate; /*0x14 */ 2737 U8 2738 HwLinkRate; /*0x15 */ 2739 U8 2740 ChangeCount; /*0x16 */ 2741 U8 2742 Flags; /*0x17 */ 2743 U32 2744 PhyInfo; /*0x18 */ 2745 U8 2746 NegotiatedLinkRate; /*0x1C */ 2747 U8 2748 Reserved3; /*0x1D */ 2749 U16 2750 Reserved4; /*0x1E */ 2751 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2752 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2753 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2754 2755 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2756 2757 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2758 2759 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2760 2761 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2762 2763 /*values for SAS PHY Page 0 Flags field */ 2764 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2765 2766 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2767 2768 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2769 2770 2771 /*SAS PHY Page 1 */ 2772 2773 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 2774 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2775 Header; /*0x00 */ 2776 U32 2777 Reserved1; /*0x08 */ 2778 U32 2779 InvalidDwordCount; /*0x0C */ 2780 U32 2781 RunningDisparityErrorCount; /*0x10 */ 2782 U32 2783 LossDwordSynchCount; /*0x14 */ 2784 U32 2785 PhyResetProblemCount; /*0x18 */ 2786 } MPI2_CONFIG_PAGE_SAS_PHY_1, 2787 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2788 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 2789 2790 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2791 2792 2793 /*SAS PHY Page 2 */ 2794 2795 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2796 U8 PhyEventCode; /*0x00 */ 2797 U8 Reserved1; /*0x01 */ 2798 U16 Reserved2; /*0x02 */ 2799 U32 PhyEventInfo; /*0x04 */ 2800 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 2801 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 2802 2803 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2804 2805 2806 /* 2807 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2808 *one and check the value returned for NumPhyEvents at runtime. 2809 */ 2810 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2811 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2812 #endif 2813 2814 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2815 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2816 Header; /*0x00 */ 2817 U32 2818 Reserved1; /*0x08 */ 2819 U8 2820 NumPhyEvents; /*0x0C */ 2821 U8 2822 Reserved2; /*0x0D */ 2823 U16 2824 Reserved3; /*0x0E */ 2825 MPI2_SASPHY2_PHY_EVENT 2826 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 2827 } MPI2_CONFIG_PAGE_SAS_PHY_2, 2828 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2829 Mpi2SasPhyPage2_t, 2830 *pMpi2SasPhyPage2_t; 2831 2832 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2833 2834 2835 /*SAS PHY Page 3 */ 2836 2837 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2838 U8 PhyEventCode; /*0x00 */ 2839 U8 Reserved1; /*0x01 */ 2840 U16 Reserved2; /*0x02 */ 2841 U8 CounterType; /*0x04 */ 2842 U8 ThresholdWindow; /*0x05 */ 2843 U8 TimeUnits; /*0x06 */ 2844 U8 Reserved3; /*0x07 */ 2845 U32 EventThreshold; /*0x08 */ 2846 U16 ThresholdFlags; /*0x0C */ 2847 U16 Reserved4; /*0x0E */ 2848 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 2849 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2850 Mpi2SasPhy3PhyEventConfig_t, 2851 *pMpi2SasPhy3PhyEventConfig_t; 2852 2853 /*values for PhyEventCode field */ 2854 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2855 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2856 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2857 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2858 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2859 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2860 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2861 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2862 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2863 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2864 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2865 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2866 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2867 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2868 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2869 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2870 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2871 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2872 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2873 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2874 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2875 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2876 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2877 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2878 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2879 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2880 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2881 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2882 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2883 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2884 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2885 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2886 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2887 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2888 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2889 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2890 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2891 2892 /*values for the CounterType field */ 2893 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2894 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2895 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2896 2897 /*values for the TimeUnits field */ 2898 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2899 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2900 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2901 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2902 2903 /*values for the ThresholdFlags field */ 2904 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2905 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2906 2907 /* 2908 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2909 *one and check the value returned for NumPhyEvents at runtime. 2910 */ 2911 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2912 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2913 #endif 2914 2915 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 2916 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2917 Header; /*0x00 */ 2918 U32 2919 Reserved1; /*0x08 */ 2920 U8 2921 NumPhyEvents; /*0x0C */ 2922 U8 2923 Reserved2; /*0x0D */ 2924 U16 2925 Reserved3; /*0x0E */ 2926 MPI2_SASPHY3_PHY_EVENT_CONFIG 2927 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 2928 } MPI2_CONFIG_PAGE_SAS_PHY_3, 2929 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2930 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 2931 2932 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2933 2934 2935 /*SAS PHY Page 4 */ 2936 2937 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 2938 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2939 Header; /*0x00 */ 2940 U16 2941 Reserved1; /*0x08 */ 2942 U8 2943 Reserved2; /*0x0A */ 2944 U8 2945 Flags; /*0x0B */ 2946 U8 2947 InitialFrame[28]; /*0x0C */ 2948 } MPI2_CONFIG_PAGE_SAS_PHY_4, 2949 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2950 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 2951 2952 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2953 2954 /*values for the Flags field */ 2955 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2956 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2957 2958 2959 2960 2961 /**************************************************************************** 2962 * SAS Port Config Pages 2963 ****************************************************************************/ 2964 2965 /*SAS Port Page 0 */ 2966 2967 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 2968 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2969 Header; /*0x00 */ 2970 U8 2971 PortNumber; /*0x08 */ 2972 U8 2973 PhysicalPort; /*0x09 */ 2974 U8 2975 PortWidth; /*0x0A */ 2976 U8 2977 PhysicalPortWidth; /*0x0B */ 2978 U8 2979 ZoneGroup; /*0x0C */ 2980 U8 2981 Reserved1; /*0x0D */ 2982 U16 2983 Reserved2; /*0x0E */ 2984 U64 2985 SASAddress; /*0x10 */ 2986 U32 2987 DeviceInfo; /*0x18 */ 2988 U32 2989 Reserved3; /*0x1C */ 2990 U32 2991 Reserved4; /*0x20 */ 2992 } MPI2_CONFIG_PAGE_SAS_PORT_0, 2993 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2994 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 2995 2996 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2997 2998 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2999 3000 3001 /**************************************************************************** 3002 * SAS Enclosure Config Pages 3003 ****************************************************************************/ 3004 3005 /*SAS Enclosure Page 0 */ 3006 3007 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3008 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3009 Header; /*0x00 */ 3010 U32 3011 Reserved1; /*0x08 */ 3012 U64 3013 EnclosureLogicalID; /*0x0C */ 3014 U16 3015 Flags; /*0x14 */ 3016 U16 3017 EnclosureHandle; /*0x16 */ 3018 U16 3019 NumSlots; /*0x18 */ 3020 U16 3021 StartSlot; /*0x1A */ 3022 U16 3023 Reserved2; /*0x1C */ 3024 U16 3025 SEPDevHandle; /*0x1E */ 3026 U32 3027 Reserved3; /*0x20 */ 3028 U32 3029 Reserved4; /*0x24 */ 3030 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3031 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3032 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t; 3033 3034 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 3035 3036 /*values for SAS Enclosure Page 0 Flags field */ 3037 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3038 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3039 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3040 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3041 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3042 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3043 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3044 3045 3046 /**************************************************************************** 3047 * Log Config Page 3048 ****************************************************************************/ 3049 3050 /*Log Page 0 */ 3051 3052 /* 3053 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3054 *one and check the value returned for NumLogEntries at runtime. 3055 */ 3056 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3057 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3058 #endif 3059 3060 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3061 3062 typedef struct _MPI2_LOG_0_ENTRY { 3063 U64 TimeStamp; /*0x00 */ 3064 U32 Reserved1; /*0x08 */ 3065 U16 LogSequence; /*0x0C */ 3066 U16 LogEntryQualifier; /*0x0E */ 3067 U8 VP_ID; /*0x10 */ 3068 U8 VF_ID; /*0x11 */ 3069 U16 Reserved2; /*0x12 */ 3070 U8 3071 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3072 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3073 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3074 3075 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3076 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3077 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3078 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3079 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3080 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3081 3082 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3083 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3084 U32 Reserved1; /*0x08 */ 3085 U32 Reserved2; /*0x0C */ 3086 U16 NumLogEntries;/*0x10 */ 3087 U16 Reserved3; /*0x12 */ 3088 MPI2_LOG_0_ENTRY 3089 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3090 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3091 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3092 3093 #define MPI2_LOG_0_PAGEVERSION (0x02) 3094 3095 3096 /**************************************************************************** 3097 * RAID Config Page 3098 ****************************************************************************/ 3099 3100 /*RAID Page 0 */ 3101 3102 /* 3103 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3104 *one and check the value returned for NumElements at runtime. 3105 */ 3106 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3107 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3108 #endif 3109 3110 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3111 U16 ElementFlags; /*0x00 */ 3112 U16 VolDevHandle; /*0x02 */ 3113 U8 HotSparePool; /*0x04 */ 3114 U8 PhysDiskNum; /*0x05 */ 3115 U16 PhysDiskDevHandle; /*0x06 */ 3116 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3117 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3118 Mpi2RaidConfig0ConfigElement_t, 3119 *pMpi2RaidConfig0ConfigElement_t; 3120 3121 /*values for the ElementFlags field */ 3122 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3123 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3124 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3125 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3126 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3127 3128 3129 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3130 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3131 U8 NumHotSpares; /*0x08 */ 3132 U8 NumPhysDisks; /*0x09 */ 3133 U8 NumVolumes; /*0x0A */ 3134 U8 ConfigNum; /*0x0B */ 3135 U32 Flags; /*0x0C */ 3136 U8 ConfigGUID[24]; /*0x10 */ 3137 U32 Reserved1; /*0x28 */ 3138 U8 NumElements; /*0x2C */ 3139 U8 Reserved2; /*0x2D */ 3140 U16 Reserved3; /*0x2E */ 3141 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3142 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3143 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3144 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3145 Mpi2RaidConfigurationPage0_t, 3146 *pMpi2RaidConfigurationPage0_t; 3147 3148 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3149 3150 /*values for RAID Configuration Page 0 Flags field */ 3151 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3152 3153 3154 /**************************************************************************** 3155 * Driver Persistent Mapping Config Pages 3156 ****************************************************************************/ 3157 3158 /*Driver Persistent Mapping Page 0 */ 3159 3160 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3161 U64 PhysicalIdentifier; /*0x00 */ 3162 U16 MappingInformation; /*0x08 */ 3163 U16 DeviceIndex; /*0x0A */ 3164 U32 PhysicalBitsMapping; /*0x0C */ 3165 U32 Reserved1; /*0x10 */ 3166 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3167 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3168 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3169 3170 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3171 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3172 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3173 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3174 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3175 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3176 3177 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3178 3179 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3180 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3181 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3182 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3183 3184 3185 /**************************************************************************** 3186 * Ethernet Config Pages 3187 ****************************************************************************/ 3188 3189 /*Ethernet Page 0 */ 3190 3191 /*IP address (union of IPv4 and IPv6) */ 3192 typedef union _MPI2_ETHERNET_IP_ADDR { 3193 U32 IPv4Addr; 3194 U32 IPv6Addr[4]; 3195 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3196 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3197 3198 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3199 3200 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3201 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3202 U8 NumInterfaces; /*0x08 */ 3203 U8 Reserved0; /*0x09 */ 3204 U16 Reserved1; /*0x0A */ 3205 U32 Status; /*0x0C */ 3206 U8 MediaState; /*0x10 */ 3207 U8 Reserved2; /*0x11 */ 3208 U16 Reserved3; /*0x12 */ 3209 U8 MacAddress[6]; /*0x14 */ 3210 U8 Reserved4; /*0x1A */ 3211 U8 Reserved5; /*0x1B */ 3212 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3213 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3214 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3215 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3216 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3217 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3218 U8 3219 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3220 } MPI2_CONFIG_PAGE_ETHERNET_0, 3221 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3222 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3223 3224 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3225 3226 /*values for Ethernet Page 0 Status field */ 3227 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3228 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3229 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3230 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3231 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3232 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3233 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3234 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3235 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3236 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3237 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3238 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3239 3240 /*values for Ethernet Page 0 MediaState field */ 3241 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3242 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3243 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3244 3245 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3246 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3247 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3248 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3249 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3250 3251 3252 /*Ethernet Page 1 */ 3253 3254 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3255 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3256 Header; /*0x00 */ 3257 U32 3258 Reserved0; /*0x08 */ 3259 U32 3260 Flags; /*0x0C */ 3261 U8 3262 MediaState; /*0x10 */ 3263 U8 3264 Reserved1; /*0x11 */ 3265 U16 3266 Reserved2; /*0x12 */ 3267 U8 3268 MacAddress[6]; /*0x14 */ 3269 U8 3270 Reserved3; /*0x1A */ 3271 U8 3272 Reserved4; /*0x1B */ 3273 MPI2_ETHERNET_IP_ADDR 3274 StaticIpAddress; /*0x1C */ 3275 MPI2_ETHERNET_IP_ADDR 3276 StaticSubnetMask; /*0x2C */ 3277 MPI2_ETHERNET_IP_ADDR 3278 StaticGatewayIpAddress; /*0x3C */ 3279 MPI2_ETHERNET_IP_ADDR 3280 StaticDNS1IpAddress; /*0x4C */ 3281 MPI2_ETHERNET_IP_ADDR 3282 StaticDNS2IpAddress; /*0x5C */ 3283 U32 3284 Reserved5; /*0x6C */ 3285 U32 3286 Reserved6; /*0x70 */ 3287 U32 3288 Reserved7; /*0x74 */ 3289 U32 3290 Reserved8; /*0x78 */ 3291 U8 3292 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3293 } MPI2_CONFIG_PAGE_ETHERNET_1, 3294 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3295 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3296 3297 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3298 3299 /*values for Ethernet Page 1 Flags field */ 3300 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3301 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3302 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3303 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3304 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3305 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3306 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3307 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3308 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3309 3310 /*values for Ethernet Page 1 MediaState field */ 3311 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3312 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3313 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3314 3315 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3316 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3317 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3318 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3319 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3320 3321 3322 /**************************************************************************** 3323 * Extended Manufacturing Config Pages 3324 ****************************************************************************/ 3325 3326 /* 3327 *Generic structure to use for product-specific extended manufacturing pages 3328 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3329 *Page 60). 3330 */ 3331 3332 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3333 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3334 Header; /*0x00 */ 3335 U32 3336 ProductSpecificInfo; /*0x08 */ 3337 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3338 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3339 Mpi2ExtManufacturingPagePS_t, 3340 *pMpi2ExtManufacturingPagePS_t; 3341 3342 /*PageVersion should be provided by product-specific code */ 3343 3344 #endif 3345