1 /* 2 * Copyright (c) 2000-2011 LSI Corporation. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.22 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 23 * Added Manufacturing Page 11. 24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 25 * define. 26 * 06-26-07 02.00.02 Adding generic structure for product-specific 27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 28 * Rework of BIOS Page 2 configuration page. 29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 30 * forms. 31 * Added configuration pages IOC Page 8 and Driver 32 * Persistent Mapping Page 0. 33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 35 * RAID Physical Disk Pages 0 and 1, RAID Configuration 36 * Page 0). 37 * Added new value for AccessStatus field of SAS Device 38 * Page 0 (_SATA_NEEDS_INITIALIZATION). 39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 42 * NVDATA. 43 * Modified IOC Page 7 to use masks and added field for 44 * SASBroadcastPrimitiveMasks. 45 * Added MPI2_CONFIG_PAGE_BIOS_4. 46 * Added MPI2_CONFIG_PAGE_LOG_0. 47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 48 * Added SAS Device IDs. 49 * Updated Integrated RAID configuration pages including 50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 51 * Page 0. 52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 55 * Added missing MaxNumRoutedSasAddresses field to 56 * MPI2_CONFIG_PAGE_EXPANDER_0. 57 * Added SAS Port Page 0. 58 * Modified structure layout for 59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 63 * to 0x000000FF. 64 * Added two new values for the Physical Disk Coercion Size 65 * bits in the Flags field of Manufacturing Page 4. 66 * Added product-specific Manufacturing pages 16 to 31. 67 * Modified Flags bits for controlling write cache on SATA 68 * drives in IO Unit Page 1. 69 * Added new bit to AdditionalControlFlags of SAS IO Unit 70 * Page 1 to control Invalid Topology Correction. 71 * Added additional defines for RAID Volume Page 0 72 * VolumeStatusFlags field. 73 * Modified meaning of RAID Volume Page 0 VolumeSettings 74 * define for auto-configure of hot-swap drives. 75 * Added SupportedPhysDisks field to RAID Volume Page 1 and 76 * added related defines. 77 * Added PhysDiskAttributes field (and related defines) to 78 * RAID Physical Disk Page 0. 79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 80 * Added three new DiscoveryStatus bits for SAS IO Unit 81 * Page 0 and SAS Expander Page 0. 82 * Removed multiplexing information from SAS IO Unit pages. 83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 84 * Removed Zone Address Resolved bit from PhyInfo and from 85 * Expander Page 0 Flags field. 86 * Added two new AccessStatus values to SAS Device Page 0 87 * for indicating routing problems. Added 3 reserved words 88 * to this page. 89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 90 * Inserted missing reserved field into structure for IOC 91 * Page 6. 92 * Added more pending task bits to RAID Volume Page 0 93 * VolumeStatusFlags defines. 94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 96 * and SAS Expander Page 0 to flag a downstream initiator 97 * when in simplified routing mode. 98 * Removed SATA Init Failure defines for DiscoveryStatus 99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 101 * Added PortGroups, DmaGroup, and ControlGroup fields to 102 * SAS Device Page 0. 103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 104 * Unit Page 6. 105 * Added expander reduced functionality data to SAS 106 * Expander Page 0. 107 * Added SAS PHY Page 2 and SAS PHY Page 3. 108 * 07-30-09 02.00.12 Added IO Unit Page 7. 109 * Added new device ids. 110 * Added SAS IO Unit Page 5. 111 * Added partial and slumber power management capable flags 112 * to SAS Device Page 0 Flags field. 113 * Added PhyInfo defines for power condition. 114 * Added Ethernet configuration pages. 115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 116 * Added SAS PHY Page 4 structure and defines. 117 * 02-10-10 02.00.14 Modified the comments for the configuration page 118 * structures that contain an array of data. The host 119 * should use the "count" field in the page data (e.g. the 120 * NumPhys field) to determine the number of valid elements 121 * in the array. 122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 123 * Added PowerManagementCapabilities to IO Unit Page 7. 124 * Added PortWidthModGroup field to 125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 130 * define. 131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 134 * defines. 135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 137 * the Pinout field. 138 * Added BoardTemperature and BoardTemperatureUnits fields 139 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 143 * Added IO Unit Page 8, IO Unit Page 9, 144 * and IO Unit Page 10. 145 * Added SASNotifyPrimitiveMasks field to 146 * MPI2_CONFIG_PAGE_IOC_7. 147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 148 * 05-25-11 02.00.20 Cleaned up a few comments. 149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 150 * for PCIe link as obsolete. 151 * Added SpinupFlags field containing a Disable Spin-up bit 152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 153 * Unit Page 4. 154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 155 * Added UEFIVersion field to BIOS Page 1 and defined new 156 * BiosOptions bits. 157 * Incorporating additions for MPI v2.5. 158 * -------------------------------------------------------------------------- 159 */ 160 161 #ifndef MPI2_CNFG_H 162 #define MPI2_CNFG_H 163 164 /***************************************************************************** 165 * Configuration Page Header and defines 166 *****************************************************************************/ 167 168 /*Config Page Header */ 169 typedef struct _MPI2_CONFIG_PAGE_HEADER { 170 U8 PageVersion; /*0x00 */ 171 U8 PageLength; /*0x01 */ 172 U8 PageNumber; /*0x02 */ 173 U8 PageType; /*0x03 */ 174 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 175 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 176 177 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 178 MPI2_CONFIG_PAGE_HEADER Struct; 179 U8 Bytes[4]; 180 U16 Word16[2]; 181 U32 Word32; 182 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 183 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 184 185 /*Extended Config Page Header */ 186 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 187 U8 PageVersion; /*0x00 */ 188 U8 Reserved1; /*0x01 */ 189 U8 PageNumber; /*0x02 */ 190 U8 PageType; /*0x03 */ 191 U16 ExtPageLength; /*0x04 */ 192 U8 ExtPageType; /*0x06 */ 193 U8 Reserved2; /*0x07 */ 194 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 195 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 196 Mpi2ConfigExtendedPageHeader_t, 197 *pMpi2ConfigExtendedPageHeader_t; 198 199 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 200 MPI2_CONFIG_PAGE_HEADER Struct; 201 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 202 U8 Bytes[8]; 203 U16 Word16[4]; 204 U32 Word32[2]; 205 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 206 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 207 Mpi2ConfigPageExtendedHeaderUnion, 208 *pMpi2ConfigPageExtendedHeaderUnion; 209 210 211 /*PageType field values */ 212 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 213 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 214 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 215 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 216 217 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 218 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 219 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 220 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 221 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 222 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 223 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 224 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 225 226 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 227 228 229 /*ExtPageType field values */ 230 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 231 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 232 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 233 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 234 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 235 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 236 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 237 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 238 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 239 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 240 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 241 242 243 /***************************************************************************** 244 * PageAddress defines 245 *****************************************************************************/ 246 247 /*RAID Volume PageAddress format */ 248 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 249 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 250 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 251 252 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 253 254 255 /*RAID Physical Disk PageAddress format */ 256 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 257 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 258 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 259 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 260 261 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 262 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 263 264 265 /*SAS Expander PageAddress format */ 266 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 267 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 268 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 269 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 270 271 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 272 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 273 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 274 275 276 /*SAS Device PageAddress format */ 277 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 278 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 279 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 280 281 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 282 283 284 /*SAS PHY PageAddress format */ 285 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 286 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 287 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 288 289 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 290 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 291 292 293 /*SAS Port PageAddress format */ 294 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 295 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 296 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 297 298 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 299 300 301 /*SAS Enclosure PageAddress format */ 302 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 303 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 304 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 305 306 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 307 308 309 /*RAID Configuration PageAddress format */ 310 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 311 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 312 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 313 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 314 315 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 316 317 318 /*Driver Persistent Mapping PageAddress format */ 319 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 320 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 321 322 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 323 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 324 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 325 326 327 /*Ethernet PageAddress format */ 328 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 329 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 330 331 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 332 333 334 335 /**************************************************************************** 336 * Configuration messages 337 ****************************************************************************/ 338 339 /*Configuration Request Message */ 340 typedef struct _MPI2_CONFIG_REQUEST { 341 U8 Action; /*0x00 */ 342 U8 SGLFlags; /*0x01 */ 343 U8 ChainOffset; /*0x02 */ 344 U8 Function; /*0x03 */ 345 U16 ExtPageLength; /*0x04 */ 346 U8 ExtPageType; /*0x06 */ 347 U8 MsgFlags; /*0x07 */ 348 U8 VP_ID; /*0x08 */ 349 U8 VF_ID; /*0x09 */ 350 U16 Reserved1; /*0x0A */ 351 U8 Reserved2; /*0x0C */ 352 U8 ProxyVF_ID; /*0x0D */ 353 U16 Reserved4; /*0x0E */ 354 U32 Reserved3; /*0x10 */ 355 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 356 U32 PageAddress; /*0x18 */ 357 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 358 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 359 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 360 361 /*values for the Action field */ 362 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 363 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 364 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 365 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 366 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 367 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 368 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 369 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 370 371 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 372 373 374 /*Config Reply Message */ 375 typedef struct _MPI2_CONFIG_REPLY { 376 U8 Action; /*0x00 */ 377 U8 SGLFlags; /*0x01 */ 378 U8 MsgLength; /*0x02 */ 379 U8 Function; /*0x03 */ 380 U16 ExtPageLength; /*0x04 */ 381 U8 ExtPageType; /*0x06 */ 382 U8 MsgFlags; /*0x07 */ 383 U8 VP_ID; /*0x08 */ 384 U8 VF_ID; /*0x09 */ 385 U16 Reserved1; /*0x0A */ 386 U16 Reserved2; /*0x0C */ 387 U16 IOCStatus; /*0x0E */ 388 U32 IOCLogInfo; /*0x10 */ 389 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 390 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 391 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 392 393 394 395 /***************************************************************************** 396 * 397 * C o n f i g u r a t i o n P a g e s 398 * 399 *****************************************************************************/ 400 401 /**************************************************************************** 402 * Manufacturing Config pages 403 ****************************************************************************/ 404 405 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 406 407 /*MPI v2.0 SAS products */ 408 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 409 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 410 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 411 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 412 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 413 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 414 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 415 416 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 417 418 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 419 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 420 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 421 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 422 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 423 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 424 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 425 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 426 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 427 428 /*MPI v2.5 SAS products */ 429 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 430 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 431 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 432 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 433 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 434 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 435 436 437 438 439 /*Manufacturing Page 0 */ 440 441 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 442 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 443 U8 ChipName[16]; /*0x04 */ 444 U8 ChipRevision[8]; /*0x14 */ 445 U8 BoardName[16]; /*0x1C */ 446 U8 BoardAssembly[16]; /*0x2C */ 447 U8 BoardTracerNumber[16]; /*0x3C */ 448 } MPI2_CONFIG_PAGE_MAN_0, 449 *PTR_MPI2_CONFIG_PAGE_MAN_0, 450 Mpi2ManufacturingPage0_t, 451 *pMpi2ManufacturingPage0_t; 452 453 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 454 455 456 /*Manufacturing Page 1 */ 457 458 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 459 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 460 U8 VPD[256]; /*0x04 */ 461 } MPI2_CONFIG_PAGE_MAN_1, 462 *PTR_MPI2_CONFIG_PAGE_MAN_1, 463 Mpi2ManufacturingPage1_t, 464 *pMpi2ManufacturingPage1_t; 465 466 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 467 468 469 typedef struct _MPI2_CHIP_REVISION_ID { 470 U16 DeviceID; /*0x00 */ 471 U8 PCIRevisionID; /*0x02 */ 472 U8 Reserved; /*0x03 */ 473 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 474 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 475 476 477 /*Manufacturing Page 2 */ 478 479 /* 480 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 481 *one and check Header.PageLength at runtime. 482 */ 483 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 484 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 485 #endif 486 487 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 488 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 489 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 490 U32 491 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 492 } MPI2_CONFIG_PAGE_MAN_2, 493 *PTR_MPI2_CONFIG_PAGE_MAN_2, 494 Mpi2ManufacturingPage2_t, 495 *pMpi2ManufacturingPage2_t; 496 497 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 498 499 500 /*Manufacturing Page 3 */ 501 502 /* 503 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 504 *one and check Header.PageLength at runtime. 505 */ 506 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 507 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 508 #endif 509 510 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 511 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 512 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 513 U32 514 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 515 } MPI2_CONFIG_PAGE_MAN_3, 516 *PTR_MPI2_CONFIG_PAGE_MAN_3, 517 Mpi2ManufacturingPage3_t, 518 *pMpi2ManufacturingPage3_t; 519 520 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 521 522 523 /*Manufacturing Page 4 */ 524 525 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 526 U8 PowerSaveFlags; /*0x00 */ 527 U8 InternalOperationsSleepTime; /*0x01 */ 528 U8 InternalOperationsRunTime; /*0x02 */ 529 U8 HostIdleTime; /*0x03 */ 530 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 531 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 532 Mpi2ManPage4PwrSaveSettings_t, 533 *pMpi2ManPage4PwrSaveSettings_t; 534 535 /*defines for the PowerSaveFlags field */ 536 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 537 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 538 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 539 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 540 541 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 542 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 543 U32 Reserved1; /*0x04 */ 544 U32 Flags; /*0x08 */ 545 U8 InquirySize; /*0x0C */ 546 U8 Reserved2; /*0x0D */ 547 U16 Reserved3; /*0x0E */ 548 U8 InquiryData[56]; /*0x10 */ 549 U32 RAID0VolumeSettings; /*0x48 */ 550 U32 RAID1EVolumeSettings; /*0x4C */ 551 U32 RAID1VolumeSettings; /*0x50 */ 552 U32 RAID10VolumeSettings; /*0x54 */ 553 U32 Reserved4; /*0x58 */ 554 U32 Reserved5; /*0x5C */ 555 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 556 U8 MaxOCEDisks; /*0x64 */ 557 U8 ResyncRate; /*0x65 */ 558 U16 DataScrubDuration; /*0x66 */ 559 U8 MaxHotSpares; /*0x68 */ 560 U8 MaxPhysDisksPerVol; /*0x69 */ 561 U8 MaxPhysDisks; /*0x6A */ 562 U8 MaxVolumes; /*0x6B */ 563 } MPI2_CONFIG_PAGE_MAN_4, 564 *PTR_MPI2_CONFIG_PAGE_MAN_4, 565 Mpi2ManufacturingPage4_t, 566 *pMpi2ManufacturingPage4_t; 567 568 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 569 570 /*Manufacturing Page 4 Flags field */ 571 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 572 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 573 574 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 575 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 576 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 577 578 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 579 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 580 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 581 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 582 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 583 584 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 585 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 586 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 587 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 588 589 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 590 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 591 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 592 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 593 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 594 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 595 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 596 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 597 598 599 /*Manufacturing Page 5 */ 600 601 /* 602 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 603 *one and check the value returned for NumPhys at runtime. 604 */ 605 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 606 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 607 #endif 608 609 typedef struct _MPI2_MANUFACTURING5_ENTRY { 610 U64 WWID; /*0x00 */ 611 U64 DeviceName; /*0x08 */ 612 } MPI2_MANUFACTURING5_ENTRY, 613 *PTR_MPI2_MANUFACTURING5_ENTRY, 614 Mpi2Manufacturing5Entry_t, 615 *pMpi2Manufacturing5Entry_t; 616 617 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 618 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 619 U8 NumPhys; /*0x04 */ 620 U8 Reserved1; /*0x05 */ 621 U16 Reserved2; /*0x06 */ 622 U32 Reserved3; /*0x08 */ 623 U32 Reserved4; /*0x0C */ 624 MPI2_MANUFACTURING5_ENTRY 625 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 626 } MPI2_CONFIG_PAGE_MAN_5, 627 *PTR_MPI2_CONFIG_PAGE_MAN_5, 628 Mpi2ManufacturingPage5_t, 629 *pMpi2ManufacturingPage5_t; 630 631 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 632 633 634 /*Manufacturing Page 6 */ 635 636 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 637 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 638 U32 ProductSpecificInfo;/*0x04 */ 639 } MPI2_CONFIG_PAGE_MAN_6, 640 *PTR_MPI2_CONFIG_PAGE_MAN_6, 641 Mpi2ManufacturingPage6_t, 642 *pMpi2ManufacturingPage6_t; 643 644 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 645 646 647 /*Manufacturing Page 7 */ 648 649 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 650 U32 Pinout; /*0x00 */ 651 U8 Connector[16]; /*0x04 */ 652 U8 Location; /*0x14 */ 653 U8 ReceptacleID; /*0x15 */ 654 U16 Slot; /*0x16 */ 655 U32 Reserved2; /*0x18 */ 656 } MPI2_MANPAGE7_CONNECTOR_INFO, 657 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 658 Mpi2ManPage7ConnectorInfo_t, 659 *pMpi2ManPage7ConnectorInfo_t; 660 661 /*defines for the Pinout field */ 662 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 663 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 664 665 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 666 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 667 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 668 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 669 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 670 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 671 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 672 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 673 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 674 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 675 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 676 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 677 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 678 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 679 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 680 681 /*defines for the Location field */ 682 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 683 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 684 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 685 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 686 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 687 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 688 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 689 690 /* 691 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 692 *one and check the value returned for NumPhys at runtime. 693 */ 694 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 695 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 696 #endif 697 698 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 699 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 700 U32 Reserved1; /*0x04 */ 701 U32 Reserved2; /*0x08 */ 702 U32 Flags; /*0x0C */ 703 U8 EnclosureName[16]; /*0x10 */ 704 U8 NumPhys; /*0x20 */ 705 U8 Reserved3; /*0x21 */ 706 U16 Reserved4; /*0x22 */ 707 MPI2_MANPAGE7_CONNECTOR_INFO 708 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 709 } MPI2_CONFIG_PAGE_MAN_7, 710 *PTR_MPI2_CONFIG_PAGE_MAN_7, 711 Mpi2ManufacturingPage7_t, 712 *pMpi2ManufacturingPage7_t; 713 714 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 715 716 /*defines for the Flags field */ 717 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 718 719 720 /* 721 *Generic structure to use for product-specific manufacturing pages 722 *(currently Manufacturing Page 8 through Manufacturing Page 31). 723 */ 724 725 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 726 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 727 U32 ProductSpecificInfo;/*0x04 */ 728 } MPI2_CONFIG_PAGE_MAN_PS, 729 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 730 Mpi2ManufacturingPagePS_t, 731 *pMpi2ManufacturingPagePS_t; 732 733 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 734 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 735 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 736 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 737 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 738 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 739 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 740 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 741 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 742 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 743 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 744 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 745 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 746 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 747 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 748 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 749 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 750 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 751 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 752 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 753 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 754 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 755 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 756 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 757 758 759 /**************************************************************************** 760 * IO Unit Config Pages 761 ****************************************************************************/ 762 763 /*IO Unit Page 0 */ 764 765 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 766 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 767 U64 UniqueValue; /*0x04 */ 768 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 769 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 770 } MPI2_CONFIG_PAGE_IO_UNIT_0, 771 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 772 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 773 774 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 775 776 777 /*IO Unit Page 1 */ 778 779 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 780 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 781 U32 Flags; /*0x04 */ 782 } MPI2_CONFIG_PAGE_IO_UNIT_1, 783 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 784 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 785 786 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 787 788 /*IO Unit Page 1 Flags defines */ 789 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 790 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 791 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 792 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 793 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 794 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 795 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 796 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 797 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 798 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 799 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 800 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 801 802 803 /*IO Unit Page 3 */ 804 805 /* 806 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 807 *one and check the value returned for GPIOCount at runtime. 808 */ 809 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 810 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 811 #endif 812 813 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 814 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 815 U8 GPIOCount; /*0x04 */ 816 U8 Reserved1; /*0x05 */ 817 U16 Reserved2; /*0x06 */ 818 U16 819 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 820 } MPI2_CONFIG_PAGE_IO_UNIT_3, 821 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 822 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 823 824 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 825 826 /*defines for IO Unit Page 3 GPIOVal field */ 827 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 828 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 829 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 830 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 831 832 833 /*IO Unit Page 5 */ 834 835 /* 836 *Upper layer code (drivers, utilities, etc.) should leave this define set to 837 *one and check the value returned for NumDmaEngines at runtime. 838 */ 839 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 840 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 841 #endif 842 843 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 844 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 845 U64 846 RaidAcceleratorBufferBaseAddress; /*0x04 */ 847 U64 848 RaidAcceleratorBufferSize; /*0x0C */ 849 U64 850 RaidAcceleratorControlBaseAddress; /*0x14 */ 851 U8 RAControlSize; /*0x1C */ 852 U8 NumDmaEngines; /*0x1D */ 853 U8 RAMinControlSize; /*0x1E */ 854 U8 RAMaxControlSize; /*0x1F */ 855 U32 Reserved1; /*0x20 */ 856 U32 Reserved2; /*0x24 */ 857 U32 Reserved3; /*0x28 */ 858 U32 859 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 860 } MPI2_CONFIG_PAGE_IO_UNIT_5, 861 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 862 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 863 864 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 865 866 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 867 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 868 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 869 870 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 871 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 872 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 873 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 874 875 876 /*IO Unit Page 6 */ 877 878 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 879 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 880 U16 Flags; /*0x04 */ 881 U8 RAHostControlSize; /*0x06 */ 882 U8 Reserved0; /*0x07 */ 883 U64 884 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 885 U32 Reserved1; /*0x10 */ 886 U32 Reserved2; /*0x14 */ 887 U32 Reserved3; /*0x18 */ 888 } MPI2_CONFIG_PAGE_IO_UNIT_6, 889 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 890 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 891 892 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 893 894 /*defines for IO Unit Page 6 Flags field */ 895 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 896 897 898 /*IO Unit Page 7 */ 899 900 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 901 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 902 U8 CurrentPowerMode; /*0x04 */ 903 U8 PreviousPowerMode; /*0x05 */ 904 U8 PCIeWidth; /*0x06 */ 905 U8 PCIeSpeed; /*0x07 */ 906 U32 ProcessorState; /*0x08 */ 907 U32 908 PowerManagementCapabilities; /*0x0C */ 909 U16 IOCTemperature; /*0x10 */ 910 U8 911 IOCTemperatureUnits; /*0x12 */ 912 U8 IOCSpeed; /*0x13 */ 913 U16 BoardTemperature; /*0x14 */ 914 U8 915 BoardTemperatureUnits; /*0x16 */ 916 U8 Reserved3; /*0x17 */ 917 } MPI2_CONFIG_PAGE_IO_UNIT_7, 918 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 919 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 920 921 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 922 923 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 924 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 925 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 926 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 927 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 928 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 929 930 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 931 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 932 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 933 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 934 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 935 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 936 937 938 /*defines for IO Unit Page 7 PCIeWidth field */ 939 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 940 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 941 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 942 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 943 944 /*defines for IO Unit Page 7 PCIeSpeed field */ 945 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 946 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 947 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 948 949 /*defines for IO Unit Page 7 ProcessorState field */ 950 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 951 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 952 953 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 954 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 955 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 956 957 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 958 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 959 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 960 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 961 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 962 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 963 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 964 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 965 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 966 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 967 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 968 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 969 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 970 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 971 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 972 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 973 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 974 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 975 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 976 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 977 978 /*obsolete names for the PowerManagementCapabilities bits (above) */ 979 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 980 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 981 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 982 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 983 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 984 985 986 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 987 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 988 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 989 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 990 991 /*defines for IO Unit Page 7 IOCSpeed field */ 992 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 993 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 994 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 995 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 996 997 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 998 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 999 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1000 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1001 1002 1003 /*IO Unit Page 8 */ 1004 1005 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1006 1007 typedef struct _MPI2_IOUNIT8_SENSOR { 1008 U16 Flags; /*0x00 */ 1009 U16 Reserved1; /*0x02 */ 1010 U16 1011 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1012 U32 Reserved2; /*0x0C */ 1013 U32 Reserved3; /*0x10 */ 1014 U32 Reserved4; /*0x14 */ 1015 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1016 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1017 1018 /*defines for IO Unit Page 8 Sensor Flags field */ 1019 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1020 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1021 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1022 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1023 1024 /* 1025 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1026 *one and check the value returned for NumSensors at runtime. 1027 */ 1028 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1029 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1030 #endif 1031 1032 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1033 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1034 U32 Reserved1; /*0x04 */ 1035 U32 Reserved2; /*0x08 */ 1036 U8 NumSensors; /*0x0C */ 1037 U8 PollingInterval; /*0x0D */ 1038 U16 Reserved3; /*0x0E */ 1039 MPI2_IOUNIT8_SENSOR 1040 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1041 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1042 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1043 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1044 1045 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1046 1047 1048 /*IO Unit Page 9 */ 1049 1050 typedef struct _MPI2_IOUNIT9_SENSOR { 1051 U16 CurrentTemperature; /*0x00 */ 1052 U16 Reserved1; /*0x02 */ 1053 U8 Flags; /*0x04 */ 1054 U8 Reserved2; /*0x05 */ 1055 U16 Reserved3; /*0x06 */ 1056 U32 Reserved4; /*0x08 */ 1057 U32 Reserved5; /*0x0C */ 1058 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1059 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1060 1061 /*defines for IO Unit Page 9 Sensor Flags field */ 1062 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1063 1064 /* 1065 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1066 *one and check the value returned for NumSensors at runtime. 1067 */ 1068 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1069 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1070 #endif 1071 1072 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1073 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1074 U32 Reserved1; /*0x04 */ 1075 U32 Reserved2; /*0x08 */ 1076 U8 NumSensors; /*0x0C */ 1077 U8 Reserved4; /*0x0D */ 1078 U16 Reserved3; /*0x0E */ 1079 MPI2_IOUNIT9_SENSOR 1080 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1081 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1082 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1083 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1084 1085 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1086 1087 1088 /*IO Unit Page 10 */ 1089 1090 typedef struct _MPI2_IOUNIT10_FUNCTION { 1091 U8 CreditPercent; /*0x00 */ 1092 U8 Reserved1; /*0x01 */ 1093 U16 Reserved2; /*0x02 */ 1094 } MPI2_IOUNIT10_FUNCTION, 1095 *PTR_MPI2_IOUNIT10_FUNCTION, 1096 Mpi2IOUnit10Function_t, 1097 *pMpi2IOUnit10Function_t; 1098 1099 /* 1100 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1101 *one and check the value returned for NumFunctions at runtime. 1102 */ 1103 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1104 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1105 #endif 1106 1107 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1108 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1109 U8 NumFunctions; /*0x04 */ 1110 U8 Reserved1; /*0x05 */ 1111 U16 Reserved2; /*0x06 */ 1112 U32 Reserved3; /*0x08 */ 1113 U32 Reserved4; /*0x0C */ 1114 MPI2_IOUNIT10_FUNCTION 1115 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1116 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1117 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1118 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1119 1120 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1121 1122 1123 1124 /**************************************************************************** 1125 * IOC Config Pages 1126 ****************************************************************************/ 1127 1128 /*IOC Page 0 */ 1129 1130 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1131 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1132 U32 Reserved1; /*0x04 */ 1133 U32 Reserved2; /*0x08 */ 1134 U16 VendorID; /*0x0C */ 1135 U16 DeviceID; /*0x0E */ 1136 U8 RevisionID; /*0x10 */ 1137 U8 Reserved3; /*0x11 */ 1138 U16 Reserved4; /*0x12 */ 1139 U32 ClassCode; /*0x14 */ 1140 U16 SubsystemVendorID; /*0x18 */ 1141 U16 SubsystemID; /*0x1A */ 1142 } MPI2_CONFIG_PAGE_IOC_0, 1143 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1144 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1145 1146 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1147 1148 1149 /*IOC Page 1 */ 1150 1151 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1152 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1153 U32 Flags; /*0x04 */ 1154 U32 CoalescingTimeout; /*0x08 */ 1155 U8 CoalescingDepth; /*0x0C */ 1156 U8 PCISlotNum; /*0x0D */ 1157 U8 PCIBusNum; /*0x0E */ 1158 U8 PCIDomainSegment; /*0x0F */ 1159 U32 Reserved1; /*0x10 */ 1160 U32 Reserved2; /*0x14 */ 1161 } MPI2_CONFIG_PAGE_IOC_1, 1162 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1163 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1164 1165 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1166 1167 /*defines for IOC Page 1 Flags field */ 1168 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1169 1170 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1171 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1172 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1173 1174 /*IOC Page 6 */ 1175 1176 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1177 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1178 U32 1179 CapabilitiesFlags; /*0x04 */ 1180 U8 MaxDrivesRAID0; /*0x08 */ 1181 U8 MaxDrivesRAID1; /*0x09 */ 1182 U8 1183 MaxDrivesRAID1E; /*0x0A */ 1184 U8 1185 MaxDrivesRAID10; /*0x0B */ 1186 U8 MinDrivesRAID0; /*0x0C */ 1187 U8 MinDrivesRAID1; /*0x0D */ 1188 U8 1189 MinDrivesRAID1E; /*0x0E */ 1190 U8 1191 MinDrivesRAID10; /*0x0F */ 1192 U32 Reserved1; /*0x10 */ 1193 U8 1194 MaxGlobalHotSpares; /*0x14 */ 1195 U8 MaxPhysDisks; /*0x15 */ 1196 U8 MaxVolumes; /*0x16 */ 1197 U8 MaxConfigs; /*0x17 */ 1198 U8 MaxOCEDisks; /*0x18 */ 1199 U8 Reserved2; /*0x19 */ 1200 U16 Reserved3; /*0x1A */ 1201 U32 1202 SupportedStripeSizeMapRAID0; /*0x1C */ 1203 U32 1204 SupportedStripeSizeMapRAID1E; /*0x20 */ 1205 U32 1206 SupportedStripeSizeMapRAID10; /*0x24 */ 1207 U32 Reserved4; /*0x28 */ 1208 U32 Reserved5; /*0x2C */ 1209 U16 1210 DefaultMetadataSize; /*0x30 */ 1211 U16 Reserved6; /*0x32 */ 1212 U16 1213 MaxBadBlockTableEntries; /*0x34 */ 1214 U16 Reserved7; /*0x36 */ 1215 U32 1216 IRNvsramVersion; /*0x38 */ 1217 } MPI2_CONFIG_PAGE_IOC_6, 1218 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1219 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1220 1221 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1222 1223 /*defines for IOC Page 6 CapabilitiesFlags */ 1224 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1225 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1226 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1227 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1228 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1229 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1230 1231 1232 /*IOC Page 7 */ 1233 1234 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1235 1236 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1237 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1238 U32 Reserved1; /*0x04 */ 1239 U32 1240 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1241 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1242 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1243 U32 Reserved3; /*0x1C */ 1244 } MPI2_CONFIG_PAGE_IOC_7, 1245 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1246 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1247 1248 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1249 1250 1251 /*IOC Page 8 */ 1252 1253 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1254 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1255 U8 NumDevsPerEnclosure; /*0x04 */ 1256 U8 Reserved1; /*0x05 */ 1257 U16 Reserved2; /*0x06 */ 1258 U16 MaxPersistentEntries; /*0x08 */ 1259 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1260 U16 Flags; /*0x0C */ 1261 U16 Reserved3; /*0x0E */ 1262 U16 IRVolumeMappingFlags; /*0x10 */ 1263 U16 Reserved4; /*0x12 */ 1264 U32 Reserved5; /*0x14 */ 1265 } MPI2_CONFIG_PAGE_IOC_8, 1266 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1267 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1268 1269 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1270 1271 /*defines for IOC Page 8 Flags field */ 1272 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1273 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1274 1275 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1276 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1277 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1278 1279 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1280 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1281 1282 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1283 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1284 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1285 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1286 1287 1288 /**************************************************************************** 1289 * BIOS Config Pages 1290 ****************************************************************************/ 1291 1292 /*BIOS Page 1 */ 1293 1294 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1295 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1296 U32 BiosOptions; /*0x04 */ 1297 U32 IOCSettings; /*0x08 */ 1298 U32 Reserved1; /*0x0C */ 1299 U32 DeviceSettings; /*0x10 */ 1300 U16 NumberOfDevices; /*0x14 */ 1301 U16 UEFIVersion; /*0x16 */ 1302 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1303 U16 IOTimeoutSequential; /*0x1A */ 1304 U16 IOTimeoutOther; /*0x1C */ 1305 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1306 } MPI2_CONFIG_PAGE_BIOS_1, 1307 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1308 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1309 1310 #define MPI2_BIOSPAGE1_PAGEVERSION (0x05) 1311 1312 /*values for BIOS Page 1 BiosOptions field */ 1313 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1314 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1315 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1316 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1317 1318 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1319 1320 /*values for BIOS Page 1 IOCSettings field */ 1321 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1322 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1323 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1324 1325 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1326 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1327 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1328 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1329 1330 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1331 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1332 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1333 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1334 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1335 1336 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1337 1338 /*values for BIOS Page 1 DeviceSettings field */ 1339 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1340 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1341 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1342 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1343 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1344 1345 /*defines for BIOS Page 1 UEFIVersion field */ 1346 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1347 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1348 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1349 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1350 1351 1352 1353 /*BIOS Page 2 */ 1354 1355 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1356 U32 Reserved1; /*0x00 */ 1357 U32 Reserved2; /*0x04 */ 1358 U32 Reserved3; /*0x08 */ 1359 U32 Reserved4; /*0x0C */ 1360 U32 Reserved5; /*0x10 */ 1361 U32 Reserved6; /*0x14 */ 1362 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1363 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1364 Mpi2BootDeviceAdapterOrder_t, 1365 *pMpi2BootDeviceAdapterOrder_t; 1366 1367 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1368 U64 SASAddress; /*0x00 */ 1369 U8 LUN[8]; /*0x08 */ 1370 U32 Reserved1; /*0x10 */ 1371 U32 Reserved2; /*0x14 */ 1372 } MPI2_BOOT_DEVICE_SAS_WWID, 1373 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1374 Mpi2BootDeviceSasWwid_t, 1375 *pMpi2BootDeviceSasWwid_t; 1376 1377 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1378 U64 EnclosureLogicalID; /*0x00 */ 1379 U32 Reserved1; /*0x08 */ 1380 U32 Reserved2; /*0x0C */ 1381 U16 SlotNumber; /*0x10 */ 1382 U16 Reserved3; /*0x12 */ 1383 U32 Reserved4; /*0x14 */ 1384 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1385 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1386 Mpi2BootDeviceEnclosureSlot_t, 1387 *pMpi2BootDeviceEnclosureSlot_t; 1388 1389 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1390 U64 DeviceName; /*0x00 */ 1391 U8 LUN[8]; /*0x08 */ 1392 U32 Reserved1; /*0x10 */ 1393 U32 Reserved2; /*0x14 */ 1394 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1395 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1396 Mpi2BootDeviceDeviceName_t, 1397 *pMpi2BootDeviceDeviceName_t; 1398 1399 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1400 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1401 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1402 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1403 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1404 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1405 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1406 Mpi2BiosPage2BootDevice_t, 1407 *pMpi2BiosPage2BootDevice_t; 1408 1409 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1410 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1411 U32 Reserved1; /*0x04 */ 1412 U32 Reserved2; /*0x08 */ 1413 U32 Reserved3; /*0x0C */ 1414 U32 Reserved4; /*0x10 */ 1415 U32 Reserved5; /*0x14 */ 1416 U32 Reserved6; /*0x18 */ 1417 U8 ReqBootDeviceForm; /*0x1C */ 1418 U8 Reserved7; /*0x1D */ 1419 U16 Reserved8; /*0x1E */ 1420 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1421 U8 ReqAltBootDeviceForm; /*0x38 */ 1422 U8 Reserved9; /*0x39 */ 1423 U16 Reserved10; /*0x3A */ 1424 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1425 U8 CurrentBootDeviceForm; /*0x58 */ 1426 U8 Reserved11; /*0x59 */ 1427 U16 Reserved12; /*0x5A */ 1428 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1429 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1430 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1431 1432 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1433 1434 /*values for BIOS Page 2 BootDeviceForm fields */ 1435 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1436 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1437 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1438 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1439 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1440 1441 1442 /*BIOS Page 3 */ 1443 1444 typedef struct _MPI2_ADAPTER_INFO { 1445 U8 PciBusNumber; /*0x00 */ 1446 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1447 U16 AdapterFlags; /*0x02 */ 1448 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1449 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1450 1451 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1452 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1453 1454 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1455 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1456 U32 GlobalFlags; /*0x04 */ 1457 U32 BiosVersion; /*0x08 */ 1458 MPI2_ADAPTER_INFO AdapterOrder[4]; /*0x0C */ 1459 U32 Reserved1; /*0x1C */ 1460 } MPI2_CONFIG_PAGE_BIOS_3, 1461 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1462 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1463 1464 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1465 1466 /*values for BIOS Page 3 GlobalFlags */ 1467 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1468 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1469 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1470 1471 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1472 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1473 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1474 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1475 1476 1477 /*BIOS Page 4 */ 1478 1479 /* 1480 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1481 *one and check the value returned for NumPhys at runtime. 1482 */ 1483 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1484 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1485 #endif 1486 1487 typedef struct _MPI2_BIOS4_ENTRY { 1488 U64 ReassignmentWWID; /*0x00 */ 1489 U64 ReassignmentDeviceName; /*0x08 */ 1490 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1491 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1492 1493 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1494 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1495 U8 NumPhys; /*0x04 */ 1496 U8 Reserved1; /*0x05 */ 1497 U16 Reserved2; /*0x06 */ 1498 MPI2_BIOS4_ENTRY 1499 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1500 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1501 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1502 1503 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1504 1505 1506 /**************************************************************************** 1507 * RAID Volume Config Pages 1508 ****************************************************************************/ 1509 1510 /*RAID Volume Page 0 */ 1511 1512 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1513 U8 RAIDSetNum; /*0x00 */ 1514 U8 PhysDiskMap; /*0x01 */ 1515 U8 PhysDiskNum; /*0x02 */ 1516 U8 Reserved; /*0x03 */ 1517 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1518 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1519 1520 /*defines for the PhysDiskMap field */ 1521 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1522 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1523 1524 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1525 U16 Settings; /*0x00 */ 1526 U8 HotSparePool; /*0x01 */ 1527 U8 Reserved; /*0x02 */ 1528 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1529 Mpi2RaidVol0Settings_t, 1530 *pMpi2RaidVol0Settings_t; 1531 1532 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1533 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1534 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1535 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1536 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1537 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1538 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1539 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1540 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1541 1542 /*RAID Volume Page 0 VolumeSettings defines */ 1543 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1544 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1545 1546 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1547 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1548 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1549 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1550 1551 /* 1552 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1553 *one and check the value returned for NumPhysDisks at runtime. 1554 */ 1555 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1556 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1557 #endif 1558 1559 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1560 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1561 U16 DevHandle; /*0x04 */ 1562 U8 VolumeState; /*0x06 */ 1563 U8 VolumeType; /*0x07 */ 1564 U32 VolumeStatusFlags; /*0x08 */ 1565 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1566 U64 MaxLBA; /*0x10 */ 1567 U32 StripeSize; /*0x18 */ 1568 U16 BlockSize; /*0x1C */ 1569 U16 Reserved1; /*0x1E */ 1570 U8 SupportedPhysDisks;/*0x20 */ 1571 U8 ResyncRate; /*0x21 */ 1572 U16 DataScrubDuration; /*0x22 */ 1573 U8 NumPhysDisks; /*0x24 */ 1574 U8 Reserved2; /*0x25 */ 1575 U8 Reserved3; /*0x26 */ 1576 U8 InactiveStatus; /*0x27 */ 1577 MPI2_RAIDVOL0_PHYS_DISK 1578 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1579 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1580 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1581 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1582 1583 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1584 1585 /*values for RAID VolumeState */ 1586 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1587 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1588 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1589 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1590 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1591 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1592 1593 /*values for RAID VolumeType */ 1594 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1595 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1596 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1597 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1598 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1599 1600 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1601 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1602 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1603 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1604 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1605 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1606 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1607 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1608 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1609 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1610 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1611 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1612 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1613 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1614 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1615 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1616 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1617 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1618 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1619 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1620 1621 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1622 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1623 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1624 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1625 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1626 1627 /*values for RAID Volume Page 0 InactiveStatus field */ 1628 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1629 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1630 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1631 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1632 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1633 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1634 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1635 1636 1637 /*RAID Volume Page 1 */ 1638 1639 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1640 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1641 U16 DevHandle; /*0x04 */ 1642 U16 Reserved0; /*0x06 */ 1643 U8 GUID[24]; /*0x08 */ 1644 U8 Name[16]; /*0x20 */ 1645 U64 WWID; /*0x30 */ 1646 U32 Reserved1; /*0x38 */ 1647 U32 Reserved2; /*0x3C */ 1648 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1649 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1650 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1651 1652 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1653 1654 1655 /**************************************************************************** 1656 * RAID Physical Disk Config Pages 1657 ****************************************************************************/ 1658 1659 /*RAID Physical Disk Page 0 */ 1660 1661 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1662 U16 Reserved1; /*0x00 */ 1663 U8 HotSparePool; /*0x02 */ 1664 U8 Reserved2; /*0x03 */ 1665 } MPI2_RAIDPHYSDISK0_SETTINGS, 1666 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1667 Mpi2RaidPhysDisk0Settings_t, 1668 *pMpi2RaidPhysDisk0Settings_t; 1669 1670 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1671 1672 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1673 U8 VendorID[8]; /*0x00 */ 1674 U8 ProductID[16]; /*0x08 */ 1675 U8 ProductRevLevel[4]; /*0x18 */ 1676 U8 SerialNum[32]; /*0x1C */ 1677 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1678 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1679 Mpi2RaidPhysDisk0InquiryData_t, 1680 *pMpi2RaidPhysDisk0InquiryData_t; 1681 1682 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1683 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1684 U16 DevHandle; /*0x04 */ 1685 U8 Reserved1; /*0x06 */ 1686 U8 PhysDiskNum; /*0x07 */ 1687 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1688 U32 Reserved2; /*0x0C */ 1689 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1690 U32 Reserved3; /*0x4C */ 1691 U8 PhysDiskState; /*0x50 */ 1692 U8 OfflineReason; /*0x51 */ 1693 U8 IncompatibleReason; /*0x52 */ 1694 U8 PhysDiskAttributes; /*0x53 */ 1695 U32 PhysDiskStatusFlags;/*0x54 */ 1696 U64 DeviceMaxLBA; /*0x58 */ 1697 U64 HostMaxLBA; /*0x60 */ 1698 U64 CoercedMaxLBA; /*0x68 */ 1699 U16 BlockSize; /*0x70 */ 1700 U16 Reserved5; /*0x72 */ 1701 U32 Reserved6; /*0x74 */ 1702 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1703 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1704 Mpi2RaidPhysDiskPage0_t, 1705 *pMpi2RaidPhysDiskPage0_t; 1706 1707 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1708 1709 /*PhysDiskState defines */ 1710 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1711 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1712 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1713 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1714 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1715 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1716 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1717 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1718 1719 /*OfflineReason defines */ 1720 #define MPI2_PHYSDISK0_ONLINE (0x00) 1721 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1722 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1723 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1724 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1725 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1726 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1727 1728 /*IncompatibleReason defines */ 1729 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1730 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1731 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1732 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1733 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1734 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1735 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1736 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1737 1738 /*PhysDiskAttributes defines */ 1739 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1740 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1741 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1742 1743 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1744 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1745 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1746 1747 /*PhysDiskStatusFlags defines */ 1748 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1749 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1750 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1751 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1752 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1753 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1754 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1755 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1756 1757 1758 /*RAID Physical Disk Page 1 */ 1759 1760 /* 1761 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1762 *one and check the value returned for NumPhysDiskPaths at runtime. 1763 */ 1764 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1765 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1766 #endif 1767 1768 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 1769 U16 DevHandle; /*0x00 */ 1770 U16 Reserved1; /*0x02 */ 1771 U64 WWID; /*0x04 */ 1772 U64 OwnerWWID; /*0x0C */ 1773 U8 OwnerIdentifier; /*0x14 */ 1774 U8 Reserved2; /*0x15 */ 1775 U16 Flags; /*0x16 */ 1776 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 1777 Mpi2RaidPhysDisk1Path_t, 1778 *pMpi2RaidPhysDisk1Path_t; 1779 1780 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1781 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1782 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1783 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1784 1785 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 1786 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1787 U8 NumPhysDiskPaths; /*0x04 */ 1788 U8 PhysDiskNum; /*0x05 */ 1789 U16 Reserved1; /*0x06 */ 1790 U32 Reserved2; /*0x08 */ 1791 MPI2_RAIDPHYSDISK1_PATH 1792 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 1793 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1794 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1795 Mpi2RaidPhysDiskPage1_t, 1796 *pMpi2RaidPhysDiskPage1_t; 1797 1798 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1799 1800 1801 /**************************************************************************** 1802 * values for fields used by several types of SAS Config Pages 1803 ****************************************************************************/ 1804 1805 /*values for NegotiatedLinkRates fields */ 1806 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1807 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1808 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1809 /*link rates used for Negotiated Physical and Logical Link Rate */ 1810 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1811 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1812 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1813 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1814 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1815 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1816 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1817 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1818 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1819 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1820 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1821 1822 1823 /*values for AttachedPhyInfo fields */ 1824 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1825 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1826 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1827 1828 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1829 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1830 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1831 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1832 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1833 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1834 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1835 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1836 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1837 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1838 1839 1840 /*values for PhyInfo fields */ 1841 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1842 1843 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1844 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1845 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1846 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1847 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1848 1849 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1850 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1851 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1852 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1853 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1854 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1855 1856 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1857 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1858 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1859 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1860 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1861 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1862 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1863 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1864 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1865 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1866 1867 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1868 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1869 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1870 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1871 1872 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1873 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1874 1875 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1876 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1877 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1878 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1879 1880 1881 /*values for SAS ProgrammedLinkRate fields */ 1882 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1883 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1884 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1885 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1886 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1887 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1888 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1889 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1890 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1891 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1892 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 1893 1894 1895 /*values for SAS HwLinkRate fields */ 1896 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1897 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1898 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1899 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1900 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1901 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1902 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1903 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1904 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 1905 1906 1907 1908 /**************************************************************************** 1909 * SAS IO Unit Config Pages 1910 ****************************************************************************/ 1911 1912 /*SAS IO Unit Page 0 */ 1913 1914 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 1915 U8 Port; /*0x00 */ 1916 U8 PortFlags; /*0x01 */ 1917 U8 PhyFlags; /*0x02 */ 1918 U8 NegotiatedLinkRate; /*0x03 */ 1919 U32 ControllerPhyDeviceInfo;/*0x04 */ 1920 U16 AttachedDevHandle; /*0x08 */ 1921 U16 ControllerDevHandle; /*0x0A */ 1922 U32 DiscoveryStatus; /*0x0C */ 1923 U32 Reserved; /*0x10 */ 1924 } MPI2_SAS_IO_UNIT0_PHY_DATA, 1925 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1926 Mpi2SasIOUnit0PhyData_t, 1927 *pMpi2SasIOUnit0PhyData_t; 1928 1929 /* 1930 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1931 *one and check the value returned for NumPhys at runtime. 1932 */ 1933 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1934 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1935 #endif 1936 1937 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 1938 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 1939 U32 Reserved1;/*0x08 */ 1940 U8 NumPhys; /*0x0C */ 1941 U8 Reserved2;/*0x0D */ 1942 U16 Reserved3;/*0x0E */ 1943 MPI2_SAS_IO_UNIT0_PHY_DATA 1944 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 1945 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1946 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1947 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 1948 1949 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1950 1951 /*values for SAS IO Unit Page 0 PortFlags */ 1952 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1953 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1954 1955 /*values for SAS IO Unit Page 0 PhyFlags */ 1956 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1957 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1958 1959 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1960 1961 /*see mpi2_sas.h for values for 1962 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1963 1964 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 1965 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1966 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1967 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1968 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1969 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1970 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1971 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1972 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1973 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1974 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1975 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1976 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1977 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1978 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1979 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1980 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1981 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1982 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1983 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1984 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1985 1986 1987 /*SAS IO Unit Page 1 */ 1988 1989 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 1990 U8 Port; /*0x00 */ 1991 U8 PortFlags; /*0x01 */ 1992 U8 PhyFlags; /*0x02 */ 1993 U8 MaxMinLinkRate; /*0x03 */ 1994 U32 ControllerPhyDeviceInfo; /*0x04 */ 1995 U16 MaxTargetPortConnectTime; /*0x08 */ 1996 U16 Reserved1; /*0x0A */ 1997 } MPI2_SAS_IO_UNIT1_PHY_DATA, 1998 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1999 Mpi2SasIOUnit1PhyData_t, 2000 *pMpi2SasIOUnit1PhyData_t; 2001 2002 /* 2003 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2004 *one and check the value returned for NumPhys at runtime. 2005 */ 2006 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2007 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2008 #endif 2009 2010 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2011 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2012 U16 2013 ControlFlags; /*0x08 */ 2014 U16 2015 SASNarrowMaxQueueDepth; /*0x0A */ 2016 U16 2017 AdditionalControlFlags; /*0x0C */ 2018 U16 2019 SASWideMaxQueueDepth; /*0x0E */ 2020 U8 2021 NumPhys; /*0x10 */ 2022 U8 2023 SATAMaxQDepth; /*0x11 */ 2024 U8 2025 ReportDeviceMissingDelay; /*0x12 */ 2026 U8 2027 IODeviceMissingDelay; /*0x13 */ 2028 MPI2_SAS_IO_UNIT1_PHY_DATA 2029 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2030 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2031 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2032 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2033 2034 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2035 2036 /*values for SAS IO Unit Page 1 ControlFlags */ 2037 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2038 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2039 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2040 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2041 2042 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2043 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2044 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2045 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2046 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2047 2048 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2049 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2050 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2051 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2052 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2053 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2054 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2055 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2056 2057 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2058 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2059 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2060 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2061 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2062 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2063 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2064 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2065 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2066 2067 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2068 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2069 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2070 2071 /*values for SAS IO Unit Page 1 PortFlags */ 2072 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2073 2074 /*values for SAS IO Unit Page 1 PhyFlags */ 2075 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2076 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2077 2078 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2079 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2080 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2081 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2082 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2083 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2084 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2085 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2086 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2087 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2088 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2089 2090 /*see mpi2_sas.h for values for 2091 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2092 2093 2094 /*SAS IO Unit Page 4 */ 2095 2096 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2097 U8 MaxTargetSpinup; /*0x00 */ 2098 U8 SpinupDelay; /*0x01 */ 2099 U8 SpinupFlags; /*0x02 */ 2100 U8 Reserved1; /*0x03 */ 2101 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2102 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2103 Mpi2SasIOUnit4SpinupGroup_t, 2104 *pMpi2SasIOUnit4SpinupGroup_t; 2105 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2106 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2107 2108 2109 /* 2110 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2111 *one and check the value returned for NumPhys at runtime. 2112 */ 2113 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2114 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2115 #endif 2116 2117 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2118 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2119 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2120 SpinupGroupParameters[4]; /*0x08 */ 2121 U32 2122 Reserved1; /*0x18 */ 2123 U32 2124 Reserved2; /*0x1C */ 2125 U32 2126 Reserved3; /*0x20 */ 2127 U8 2128 BootDeviceWaitTime; /*0x24 */ 2129 U8 2130 Reserved4; /*0x25 */ 2131 U16 2132 Reserved5; /*0x26 */ 2133 U8 2134 NumPhys; /*0x28 */ 2135 U8 2136 PEInitialSpinupDelay; /*0x29 */ 2137 U8 2138 PEReplyDelay; /*0x2A */ 2139 U8 2140 Flags; /*0x2B */ 2141 U8 2142 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2143 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2144 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2145 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2146 2147 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2148 2149 /*defines for Flags field */ 2150 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2151 2152 /*defines for PHY field */ 2153 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2154 2155 2156 /*SAS IO Unit Page 5 */ 2157 2158 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2159 U8 ControlFlags; /*0x00 */ 2160 U8 PortWidthModGroup; /*0x01 */ 2161 U16 InactivityTimerExponent; /*0x02 */ 2162 U8 SATAPartialTimeout; /*0x04 */ 2163 U8 Reserved2; /*0x05 */ 2164 U8 SATASlumberTimeout; /*0x06 */ 2165 U8 Reserved3; /*0x07 */ 2166 U8 SASPartialTimeout; /*0x08 */ 2167 U8 Reserved4; /*0x09 */ 2168 U8 SASSlumberTimeout; /*0x0A */ 2169 U8 Reserved5; /*0x0B */ 2170 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2171 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2172 Mpi2SasIOUnit5PhyPmSettings_t, 2173 *pMpi2SasIOUnit5PhyPmSettings_t; 2174 2175 /*defines for ControlFlags field */ 2176 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2177 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2178 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2179 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2180 2181 /*defines for PortWidthModeGroup field */ 2182 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2183 2184 /*defines for InactivityTimerExponent field */ 2185 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2186 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2187 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2188 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2189 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2190 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2191 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2192 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2193 2194 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2195 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2196 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2197 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2198 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2199 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2200 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2201 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2202 2203 /* 2204 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2205 *one and check the value returned for NumPhys at runtime. 2206 */ 2207 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2208 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2209 #endif 2210 2211 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2212 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2213 U8 NumPhys; /*0x08 */ 2214 U8 Reserved1;/*0x09 */ 2215 U16 Reserved2;/*0x0A */ 2216 U32 Reserved3;/*0x0C */ 2217 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2218 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2219 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2220 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2221 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2222 2223 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2224 2225 2226 /*SAS IO Unit Page 6 */ 2227 2228 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2229 U8 CurrentStatus; /*0x00 */ 2230 U8 CurrentModulation; /*0x01 */ 2231 U8 CurrentUtilization; /*0x02 */ 2232 U8 Reserved1; /*0x03 */ 2233 U32 Reserved2; /*0x04 */ 2234 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2235 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2236 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2237 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2238 2239 /*defines for CurrentStatus field */ 2240 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2241 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2242 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2243 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2244 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2245 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2246 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2247 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2248 2249 /*defines for CurrentModulation field */ 2250 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2251 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2252 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2253 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2254 2255 /* 2256 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2257 *one and check the value returned for NumGroups at runtime. 2258 */ 2259 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2260 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2261 #endif 2262 2263 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2264 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2265 U32 Reserved1; /*0x08 */ 2266 U32 Reserved2; /*0x0C */ 2267 U8 NumGroups; /*0x10 */ 2268 U8 Reserved3; /*0x11 */ 2269 U16 Reserved4; /*0x12 */ 2270 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2271 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2272 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2273 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2274 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2275 2276 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2277 2278 2279 /*SAS IO Unit Page 7 */ 2280 2281 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2282 U8 Flags; /*0x00 */ 2283 U8 Reserved1; /*0x01 */ 2284 U16 Reserved2; /*0x02 */ 2285 U8 Threshold75Pct; /*0x04 */ 2286 U8 Threshold50Pct; /*0x05 */ 2287 U8 Threshold25Pct; /*0x06 */ 2288 U8 Reserved3; /*0x07 */ 2289 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2290 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2291 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2292 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2293 2294 /*defines for Flags field */ 2295 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2296 2297 2298 /* 2299 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2300 *one and check the value returned for NumGroups at runtime. 2301 */ 2302 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2303 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2304 #endif 2305 2306 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2307 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2308 U8 SamplingInterval; /*0x08 */ 2309 U8 WindowLength; /*0x09 */ 2310 U16 Reserved1; /*0x0A */ 2311 U32 Reserved2; /*0x0C */ 2312 U32 Reserved3; /*0x10 */ 2313 U8 NumGroups; /*0x14 */ 2314 U8 Reserved4; /*0x15 */ 2315 U16 Reserved5; /*0x16 */ 2316 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2317 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2318 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2319 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2320 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2321 2322 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2323 2324 2325 /*SAS IO Unit Page 8 */ 2326 2327 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2328 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2329 Header; /*0x00 */ 2330 U32 2331 Reserved1; /*0x08 */ 2332 U32 2333 PowerManagementCapabilities; /*0x0C */ 2334 U8 2335 TxRxSleepStatus; /*0x10 */ 2336 U8 2337 Reserved2; /*0x11 */ 2338 U16 2339 Reserved3; /*0x12 */ 2340 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2341 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2342 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2343 2344 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2345 2346 /*defines for PowerManagementCapabilities field */ 2347 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2348 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2349 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2350 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2351 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2352 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2353 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2354 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2355 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2356 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2357 2358 /*defines for TxRxSleepStatus field */ 2359 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2360 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2361 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2362 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2363 2364 2365 2366 /*SAS IO Unit Page 16 */ 2367 2368 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2369 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2370 Header; /*0x00 */ 2371 U64 2372 TimeStamp; /*0x08 */ 2373 U32 2374 Reserved1; /*0x10 */ 2375 U32 2376 Reserved2; /*0x14 */ 2377 U32 2378 FastPathPendedRequests; /*0x18 */ 2379 U32 2380 FastPathUnPendedRequests; /*0x1C */ 2381 U32 2382 FastPathHostRequestStarts; /*0x20 */ 2383 U32 2384 FastPathFirmwareRequestStarts; /*0x24 */ 2385 U32 2386 FastPathHostCompletions; /*0x28 */ 2387 U32 2388 FastPathFirmwareCompletions; /*0x2C */ 2389 U32 2390 NonFastPathRequestStarts; /*0x30 */ 2391 U32 2392 NonFastPathHostCompletions; /*0x30 */ 2393 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2394 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2395 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2396 2397 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2398 2399 2400 /**************************************************************************** 2401 * SAS Expander Config Pages 2402 ****************************************************************************/ 2403 2404 /*SAS Expander Page 0 */ 2405 2406 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2407 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2408 Header; /*0x00 */ 2409 U8 2410 PhysicalPort; /*0x08 */ 2411 U8 2412 ReportGenLength; /*0x09 */ 2413 U16 2414 EnclosureHandle; /*0x0A */ 2415 U64 2416 SASAddress; /*0x0C */ 2417 U32 2418 DiscoveryStatus; /*0x14 */ 2419 U16 2420 DevHandle; /*0x18 */ 2421 U16 2422 ParentDevHandle; /*0x1A */ 2423 U16 2424 ExpanderChangeCount; /*0x1C */ 2425 U16 2426 ExpanderRouteIndexes; /*0x1E */ 2427 U8 2428 NumPhys; /*0x20 */ 2429 U8 2430 SASLevel; /*0x21 */ 2431 U16 2432 Flags; /*0x22 */ 2433 U16 2434 STPBusInactivityTimeLimit; /*0x24 */ 2435 U16 2436 STPMaxConnectTimeLimit; /*0x26 */ 2437 U16 2438 STP_SMP_NexusLossTime; /*0x28 */ 2439 U16 2440 MaxNumRoutedSasAddresses; /*0x2A */ 2441 U64 2442 ActiveZoneManagerSASAddress;/*0x2C */ 2443 U16 2444 ZoneLockInactivityLimit; /*0x34 */ 2445 U16 2446 Reserved1; /*0x36 */ 2447 U8 2448 TimeToReducedFunc; /*0x38 */ 2449 U8 2450 InitialTimeToReducedFunc; /*0x39 */ 2451 U8 2452 MaxReducedFuncTime; /*0x3A */ 2453 U8 2454 Reserved2; /*0x3B */ 2455 } MPI2_CONFIG_PAGE_EXPANDER_0, 2456 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2457 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2458 2459 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2460 2461 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2462 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2463 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2464 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2465 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2466 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2467 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2468 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2469 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2470 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2471 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2472 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2473 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2474 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2475 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2476 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2477 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2478 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2479 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2480 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2481 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2482 2483 /*values for SAS Expander Page 0 Flags field */ 2484 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2485 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2486 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2487 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2488 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2489 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2490 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2491 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2492 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2493 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2494 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2495 2496 2497 /*SAS Expander Page 1 */ 2498 2499 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2500 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2501 Header; /*0x00 */ 2502 U8 2503 PhysicalPort; /*0x08 */ 2504 U8 2505 Reserved1; /*0x09 */ 2506 U16 2507 Reserved2; /*0x0A */ 2508 U8 2509 NumPhys; /*0x0C */ 2510 U8 2511 Phy; /*0x0D */ 2512 U16 2513 NumTableEntriesProgrammed; /*0x0E */ 2514 U8 2515 ProgrammedLinkRate; /*0x10 */ 2516 U8 2517 HwLinkRate; /*0x11 */ 2518 U16 2519 AttachedDevHandle; /*0x12 */ 2520 U32 2521 PhyInfo; /*0x14 */ 2522 U32 2523 AttachedDeviceInfo; /*0x18 */ 2524 U16 2525 ExpanderDevHandle; /*0x1C */ 2526 U8 2527 ChangeCount; /*0x1E */ 2528 U8 2529 NegotiatedLinkRate; /*0x1F */ 2530 U8 2531 PhyIdentifier; /*0x20 */ 2532 U8 2533 AttachedPhyIdentifier; /*0x21 */ 2534 U8 2535 Reserved3; /*0x22 */ 2536 U8 2537 DiscoveryInfo; /*0x23 */ 2538 U32 2539 AttachedPhyInfo; /*0x24 */ 2540 U8 2541 ZoneGroup; /*0x28 */ 2542 U8 2543 SelfConfigStatus; /*0x29 */ 2544 U16 2545 Reserved4; /*0x2A */ 2546 } MPI2_CONFIG_PAGE_EXPANDER_1, 2547 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2548 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2549 2550 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2551 2552 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2553 2554 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2555 2556 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2557 2558 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2559 *used for the AttachedDeviceInfo field */ 2560 2561 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2562 2563 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2564 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2565 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2566 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2567 2568 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2569 2570 2571 /**************************************************************************** 2572 * SAS Device Config Pages 2573 ****************************************************************************/ 2574 2575 /*SAS Device Page 0 */ 2576 2577 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2578 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2579 Header; /*0x00 */ 2580 U16 2581 Slot; /*0x08 */ 2582 U16 2583 EnclosureHandle; /*0x0A */ 2584 U64 2585 SASAddress; /*0x0C */ 2586 U16 2587 ParentDevHandle; /*0x14 */ 2588 U8 2589 PhyNum; /*0x16 */ 2590 U8 2591 AccessStatus; /*0x17 */ 2592 U16 2593 DevHandle; /*0x18 */ 2594 U8 2595 AttachedPhyIdentifier; /*0x1A */ 2596 U8 2597 ZoneGroup; /*0x1B */ 2598 U32 2599 DeviceInfo; /*0x1C */ 2600 U16 2601 Flags; /*0x20 */ 2602 U8 2603 PhysicalPort; /*0x22 */ 2604 U8 2605 MaxPortConnections; /*0x23 */ 2606 U64 2607 DeviceName; /*0x24 */ 2608 U8 2609 PortGroups; /*0x2C */ 2610 U8 2611 DmaGroup; /*0x2D */ 2612 U8 2613 ControlGroup; /*0x2E */ 2614 U8 2615 Reserved1; /*0x2F */ 2616 U32 2617 Reserved2; /*0x30 */ 2618 U32 2619 Reserved3; /*0x34 */ 2620 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2621 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2622 Mpi2SasDevicePage0_t, 2623 *pMpi2SasDevicePage0_t; 2624 2625 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2626 2627 /*values for SAS Device Page 0 AccessStatus field */ 2628 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2629 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2630 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2631 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2632 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2633 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2634 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2635 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2636 /*specific values for SATA Init failures */ 2637 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2638 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2639 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2640 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2641 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2642 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2643 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2644 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2645 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2646 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2647 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2648 2649 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2650 2651 /*values for SAS Device Page 0 Flags field */ 2652 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2653 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2654 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2655 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2656 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2657 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2658 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2659 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2660 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2661 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2662 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2663 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2664 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2665 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2666 2667 2668 /*SAS Device Page 1 */ 2669 2670 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2671 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2672 Header; /*0x00 */ 2673 U32 2674 Reserved1; /*0x08 */ 2675 U64 2676 SASAddress; /*0x0C */ 2677 U32 2678 Reserved2; /*0x14 */ 2679 U16 2680 DevHandle; /*0x18 */ 2681 U16 2682 Reserved3; /*0x1A */ 2683 U8 2684 InitialRegDeviceFIS[20];/*0x1C */ 2685 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2686 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2687 Mpi2SasDevicePage1_t, 2688 *pMpi2SasDevicePage1_t; 2689 2690 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2691 2692 2693 /**************************************************************************** 2694 * SAS PHY Config Pages 2695 ****************************************************************************/ 2696 2697 /*SAS PHY Page 0 */ 2698 2699 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2700 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2701 Header; /*0x00 */ 2702 U16 2703 OwnerDevHandle; /*0x08 */ 2704 U16 2705 Reserved1; /*0x0A */ 2706 U16 2707 AttachedDevHandle; /*0x0C */ 2708 U8 2709 AttachedPhyIdentifier; /*0x0E */ 2710 U8 2711 Reserved2; /*0x0F */ 2712 U32 2713 AttachedPhyInfo; /*0x10 */ 2714 U8 2715 ProgrammedLinkRate; /*0x14 */ 2716 U8 2717 HwLinkRate; /*0x15 */ 2718 U8 2719 ChangeCount; /*0x16 */ 2720 U8 2721 Flags; /*0x17 */ 2722 U32 2723 PhyInfo; /*0x18 */ 2724 U8 2725 NegotiatedLinkRate; /*0x1C */ 2726 U8 2727 Reserved3; /*0x1D */ 2728 U16 2729 Reserved4; /*0x1E */ 2730 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2731 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2732 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2733 2734 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2735 2736 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2737 2738 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2739 2740 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2741 2742 /*values for SAS PHY Page 0 Flags field */ 2743 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2744 2745 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2746 2747 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2748 2749 2750 /*SAS PHY Page 1 */ 2751 2752 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 2753 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2754 Header; /*0x00 */ 2755 U32 2756 Reserved1; /*0x08 */ 2757 U32 2758 InvalidDwordCount; /*0x0C */ 2759 U32 2760 RunningDisparityErrorCount; /*0x10 */ 2761 U32 2762 LossDwordSynchCount; /*0x14 */ 2763 U32 2764 PhyResetProblemCount; /*0x18 */ 2765 } MPI2_CONFIG_PAGE_SAS_PHY_1, 2766 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2767 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 2768 2769 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2770 2771 2772 /*SAS PHY Page 2 */ 2773 2774 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2775 U8 PhyEventCode; /*0x00 */ 2776 U8 Reserved1; /*0x01 */ 2777 U16 Reserved2; /*0x02 */ 2778 U32 PhyEventInfo; /*0x04 */ 2779 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 2780 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 2781 2782 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2783 2784 2785 /* 2786 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2787 *one and check the value returned for NumPhyEvents at runtime. 2788 */ 2789 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2790 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2791 #endif 2792 2793 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2794 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2795 Header; /*0x00 */ 2796 U32 2797 Reserved1; /*0x08 */ 2798 U8 2799 NumPhyEvents; /*0x0C */ 2800 U8 2801 Reserved2; /*0x0D */ 2802 U16 2803 Reserved3; /*0x0E */ 2804 MPI2_SASPHY2_PHY_EVENT 2805 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 2806 } MPI2_CONFIG_PAGE_SAS_PHY_2, 2807 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2808 Mpi2SasPhyPage2_t, 2809 *pMpi2SasPhyPage2_t; 2810 2811 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2812 2813 2814 /*SAS PHY Page 3 */ 2815 2816 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2817 U8 PhyEventCode; /*0x00 */ 2818 U8 Reserved1; /*0x01 */ 2819 U16 Reserved2; /*0x02 */ 2820 U8 CounterType; /*0x04 */ 2821 U8 ThresholdWindow; /*0x05 */ 2822 U8 TimeUnits; /*0x06 */ 2823 U8 Reserved3; /*0x07 */ 2824 U32 EventThreshold; /*0x08 */ 2825 U16 ThresholdFlags; /*0x0C */ 2826 U16 Reserved4; /*0x0E */ 2827 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 2828 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2829 Mpi2SasPhy3PhyEventConfig_t, 2830 *pMpi2SasPhy3PhyEventConfig_t; 2831 2832 /*values for PhyEventCode field */ 2833 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2834 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2835 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2836 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2837 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2838 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2839 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2840 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2841 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2842 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2843 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2844 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2845 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2846 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2847 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2848 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2849 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2850 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2851 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2852 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2853 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2854 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2855 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2856 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2857 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2858 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2859 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2860 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2861 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2862 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2863 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2864 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2865 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2866 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2867 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2868 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2869 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2870 2871 /*values for the CounterType field */ 2872 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2873 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2874 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2875 2876 /*values for the TimeUnits field */ 2877 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2878 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2879 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2880 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2881 2882 /*values for the ThresholdFlags field */ 2883 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2884 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2885 2886 /* 2887 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2888 *one and check the value returned for NumPhyEvents at runtime. 2889 */ 2890 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2891 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2892 #endif 2893 2894 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 2895 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2896 Header; /*0x00 */ 2897 U32 2898 Reserved1; /*0x08 */ 2899 U8 2900 NumPhyEvents; /*0x0C */ 2901 U8 2902 Reserved2; /*0x0D */ 2903 U16 2904 Reserved3; /*0x0E */ 2905 MPI2_SASPHY3_PHY_EVENT_CONFIG 2906 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 2907 } MPI2_CONFIG_PAGE_SAS_PHY_3, 2908 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2909 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 2910 2911 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2912 2913 2914 /*SAS PHY Page 4 */ 2915 2916 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 2917 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2918 Header; /*0x00 */ 2919 U16 2920 Reserved1; /*0x08 */ 2921 U8 2922 Reserved2; /*0x0A */ 2923 U8 2924 Flags; /*0x0B */ 2925 U8 2926 InitialFrame[28]; /*0x0C */ 2927 } MPI2_CONFIG_PAGE_SAS_PHY_4, 2928 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2929 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 2930 2931 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2932 2933 /*values for the Flags field */ 2934 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2935 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2936 2937 2938 2939 2940 /**************************************************************************** 2941 * SAS Port Config Pages 2942 ****************************************************************************/ 2943 2944 /*SAS Port Page 0 */ 2945 2946 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 2947 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2948 Header; /*0x00 */ 2949 U8 2950 PortNumber; /*0x08 */ 2951 U8 2952 PhysicalPort; /*0x09 */ 2953 U8 2954 PortWidth; /*0x0A */ 2955 U8 2956 PhysicalPortWidth; /*0x0B */ 2957 U8 2958 ZoneGroup; /*0x0C */ 2959 U8 2960 Reserved1; /*0x0D */ 2961 U16 2962 Reserved2; /*0x0E */ 2963 U64 2964 SASAddress; /*0x10 */ 2965 U32 2966 DeviceInfo; /*0x18 */ 2967 U32 2968 Reserved3; /*0x1C */ 2969 U32 2970 Reserved4; /*0x20 */ 2971 } MPI2_CONFIG_PAGE_SAS_PORT_0, 2972 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2973 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 2974 2975 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2976 2977 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2978 2979 2980 /**************************************************************************** 2981 * SAS Enclosure Config Pages 2982 ****************************************************************************/ 2983 2984 /*SAS Enclosure Page 0 */ 2985 2986 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 2987 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2988 Header; /*0x00 */ 2989 U32 2990 Reserved1; /*0x08 */ 2991 U64 2992 EnclosureLogicalID; /*0x0C */ 2993 U16 2994 Flags; /*0x14 */ 2995 U16 2996 EnclosureHandle; /*0x16 */ 2997 U16 2998 NumSlots; /*0x18 */ 2999 U16 3000 StartSlot; /*0x1A */ 3001 U16 3002 Reserved2; /*0x1C */ 3003 U16 3004 SEPDevHandle; /*0x1E */ 3005 U32 3006 Reserved3; /*0x20 */ 3007 U32 3008 Reserved4; /*0x24 */ 3009 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3010 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3011 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t; 3012 3013 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 3014 3015 /*values for SAS Enclosure Page 0 Flags field */ 3016 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3017 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3018 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3019 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3020 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3021 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3022 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3023 3024 3025 /**************************************************************************** 3026 * Log Config Page 3027 ****************************************************************************/ 3028 3029 /*Log Page 0 */ 3030 3031 /* 3032 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3033 *one and check the value returned for NumLogEntries at runtime. 3034 */ 3035 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3036 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3037 #endif 3038 3039 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3040 3041 typedef struct _MPI2_LOG_0_ENTRY { 3042 U64 TimeStamp; /*0x00 */ 3043 U32 Reserved1; /*0x08 */ 3044 U16 LogSequence; /*0x0C */ 3045 U16 LogEntryQualifier; /*0x0E */ 3046 U8 VP_ID; /*0x10 */ 3047 U8 VF_ID; /*0x11 */ 3048 U16 Reserved2; /*0x12 */ 3049 U8 3050 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3051 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3052 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3053 3054 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3055 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3056 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3057 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3058 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3059 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3060 3061 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3062 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3063 U32 Reserved1; /*0x08 */ 3064 U32 Reserved2; /*0x0C */ 3065 U16 NumLogEntries;/*0x10 */ 3066 U16 Reserved3; /*0x12 */ 3067 MPI2_LOG_0_ENTRY 3068 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3069 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3070 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3071 3072 #define MPI2_LOG_0_PAGEVERSION (0x02) 3073 3074 3075 /**************************************************************************** 3076 * RAID Config Page 3077 ****************************************************************************/ 3078 3079 /*RAID Page 0 */ 3080 3081 /* 3082 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3083 *one and check the value returned for NumElements at runtime. 3084 */ 3085 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3086 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3087 #endif 3088 3089 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3090 U16 ElementFlags; /*0x00 */ 3091 U16 VolDevHandle; /*0x02 */ 3092 U8 HotSparePool; /*0x04 */ 3093 U8 PhysDiskNum; /*0x05 */ 3094 U16 PhysDiskDevHandle; /*0x06 */ 3095 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3096 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3097 Mpi2RaidConfig0ConfigElement_t, 3098 *pMpi2RaidConfig0ConfigElement_t; 3099 3100 /*values for the ElementFlags field */ 3101 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3102 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3103 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3104 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3105 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3106 3107 3108 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3109 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3110 U8 NumHotSpares; /*0x08 */ 3111 U8 NumPhysDisks; /*0x09 */ 3112 U8 NumVolumes; /*0x0A */ 3113 U8 ConfigNum; /*0x0B */ 3114 U32 Flags; /*0x0C */ 3115 U8 ConfigGUID[24]; /*0x10 */ 3116 U32 Reserved1; /*0x28 */ 3117 U8 NumElements; /*0x2C */ 3118 U8 Reserved2; /*0x2D */ 3119 U16 Reserved3; /*0x2E */ 3120 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3121 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3122 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3123 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3124 Mpi2RaidConfigurationPage0_t, 3125 *pMpi2RaidConfigurationPage0_t; 3126 3127 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3128 3129 /*values for RAID Configuration Page 0 Flags field */ 3130 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3131 3132 3133 /**************************************************************************** 3134 * Driver Persistent Mapping Config Pages 3135 ****************************************************************************/ 3136 3137 /*Driver Persistent Mapping Page 0 */ 3138 3139 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3140 U64 PhysicalIdentifier; /*0x00 */ 3141 U16 MappingInformation; /*0x08 */ 3142 U16 DeviceIndex; /*0x0A */ 3143 U32 PhysicalBitsMapping; /*0x0C */ 3144 U32 Reserved1; /*0x10 */ 3145 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3146 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3147 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3148 3149 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3150 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3151 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3152 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3153 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3154 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3155 3156 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3157 3158 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3159 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3160 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3161 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3162 3163 3164 /**************************************************************************** 3165 * Ethernet Config Pages 3166 ****************************************************************************/ 3167 3168 /*Ethernet Page 0 */ 3169 3170 /*IP address (union of IPv4 and IPv6) */ 3171 typedef union _MPI2_ETHERNET_IP_ADDR { 3172 U32 IPv4Addr; 3173 U32 IPv6Addr[4]; 3174 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3175 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3176 3177 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3178 3179 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3180 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3181 U8 NumInterfaces; /*0x08 */ 3182 U8 Reserved0; /*0x09 */ 3183 U16 Reserved1; /*0x0A */ 3184 U32 Status; /*0x0C */ 3185 U8 MediaState; /*0x10 */ 3186 U8 Reserved2; /*0x11 */ 3187 U16 Reserved3; /*0x12 */ 3188 U8 MacAddress[6]; /*0x14 */ 3189 U8 Reserved4; /*0x1A */ 3190 U8 Reserved5; /*0x1B */ 3191 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3192 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3193 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3194 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3195 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3196 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3197 U8 3198 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3199 } MPI2_CONFIG_PAGE_ETHERNET_0, 3200 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3201 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3202 3203 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3204 3205 /*values for Ethernet Page 0 Status field */ 3206 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3207 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3208 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3209 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3210 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3211 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3212 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3213 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3214 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3215 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3216 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3217 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3218 3219 /*values for Ethernet Page 0 MediaState field */ 3220 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3221 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3222 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3223 3224 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3225 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3226 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3227 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3228 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3229 3230 3231 /*Ethernet Page 1 */ 3232 3233 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3234 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3235 Header; /*0x00 */ 3236 U32 3237 Reserved0; /*0x08 */ 3238 U32 3239 Flags; /*0x0C */ 3240 U8 3241 MediaState; /*0x10 */ 3242 U8 3243 Reserved1; /*0x11 */ 3244 U16 3245 Reserved2; /*0x12 */ 3246 U8 3247 MacAddress[6]; /*0x14 */ 3248 U8 3249 Reserved3; /*0x1A */ 3250 U8 3251 Reserved4; /*0x1B */ 3252 MPI2_ETHERNET_IP_ADDR 3253 StaticIpAddress; /*0x1C */ 3254 MPI2_ETHERNET_IP_ADDR 3255 StaticSubnetMask; /*0x2C */ 3256 MPI2_ETHERNET_IP_ADDR 3257 StaticGatewayIpAddress; /*0x3C */ 3258 MPI2_ETHERNET_IP_ADDR 3259 StaticDNS1IpAddress; /*0x4C */ 3260 MPI2_ETHERNET_IP_ADDR 3261 StaticDNS2IpAddress; /*0x5C */ 3262 U32 3263 Reserved5; /*0x6C */ 3264 U32 3265 Reserved6; /*0x70 */ 3266 U32 3267 Reserved7; /*0x74 */ 3268 U32 3269 Reserved8; /*0x78 */ 3270 U8 3271 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3272 } MPI2_CONFIG_PAGE_ETHERNET_1, 3273 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3274 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3275 3276 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3277 3278 /*values for Ethernet Page 1 Flags field */ 3279 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3280 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3281 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3282 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3283 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3284 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3285 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3286 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3287 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3288 3289 /*values for Ethernet Page 1 MediaState field */ 3290 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3291 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3292 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3293 3294 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3295 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3296 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3297 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3298 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3299 3300 3301 /**************************************************************************** 3302 * Extended Manufacturing Config Pages 3303 ****************************************************************************/ 3304 3305 /* 3306 *Generic structure to use for product-specific extended manufacturing pages 3307 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3308 *Page 60). 3309 */ 3310 3311 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3312 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3313 Header; /*0x00 */ 3314 U32 3315 ProductSpecificInfo; /*0x08 */ 3316 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3317 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3318 Mpi2ExtManufacturingPagePS_t, 3319 *pMpi2ExtManufacturingPagePS_t; 3320 3321 /*PageVersion should be provided by product-specific code */ 3322 3323 #endif 3324