1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/delay.h> 16 #include <linux/dmapool.h> 17 #include <linux/errno.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/interrupt.h> 21 #include <linux/kernel.h> 22 #include <linux/miscdevice.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/aer.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/workqueue.h> 33 #include <linux/unaligned.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_dbg.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 #include <scsi/scsi_tcq.h> 40 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 41 #include <scsi/scsi_transport_sas.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi/mpi30_tool.h" 51 #include "mpi3mr_debug.h" 52 53 /* Global list and lock for storing multiple adapters managed by the driver */ 54 extern spinlock_t mrioc_list_lock; 55 extern struct list_head mrioc_list; 56 extern int prot_mask; 57 extern atomic64_t event_counter; 58 59 #define MPI3MR_DRIVER_VERSION "8.12.0.3.50" 60 #define MPI3MR_DRIVER_RELDATE "11-November-2024" 61 62 #define MPI3MR_DRIVER_NAME "mpi3mr" 63 #define MPI3MR_DRIVER_LICENSE "GPL" 64 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 65 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 66 67 #define MPI3MR_NAME_LENGTH 64 68 #define IOCNAME "%s: " 69 70 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 71 72 /* Definitions for internal SGL and Chain SGL buffers */ 73 #define MPI3MR_PAGE_SIZE_4K 4096 74 #define MPI3MR_DEFAULT_SGL_ENTRIES 256 75 #define MPI3MR_MAX_SGL_ENTRIES 2048 76 77 /* Definitions for MAX values for shost */ 78 #define MPI3MR_MAX_CMDS_LUN 128 79 #define MPI3MR_MAX_CDB_LENGTH 32 80 81 /* Admin queue management definitions */ 82 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 83 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 84 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 85 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 86 87 /* Operational queue management definitions */ 88 #define MPI3MR_OP_REQ_Q_QD 512 89 #define MPI3MR_OP_REP_Q_QD 1024 90 #define MPI3MR_OP_REP_Q_QD4K 4096 91 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 92 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 93 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 94 95 /* Reserved Host Tag definitions */ 96 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 97 #define MPI3MR_HOSTTAG_INITCMDS 1 98 #define MPI3MR_HOSTTAG_BSG_CMDS 2 99 #define MPI3MR_HOSTTAG_PEL_ABORT 3 100 #define MPI3MR_HOSTTAG_PEL_WAIT 4 101 #define MPI3MR_HOSTTAG_BLK_TMS 5 102 #define MPI3MR_HOSTTAG_CFG_CMDS 6 103 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 104 105 #define MPI3MR_NUM_DEVRMCMD 16 106 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 107 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 108 MPI3MR_NUM_DEVRMCMD - 1) 109 110 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 111 #define MPI3MR_NUM_EVTACKCMD 4 112 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 113 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 114 MPI3MR_NUM_EVTACKCMD - 1) 115 116 /* Reduced resource count definition for crash kernel */ 117 #define MPI3MR_HOST_IOS_KDUMP 128 118 119 /* command/controller interaction timeout definitions in seconds */ 120 #define MPI3MR_INTADMCMD_TIMEOUT 60 121 #define MPI3MR_PORTENABLE_TIMEOUT 300 122 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5 123 #define MPI3MR_ABORTTM_TIMEOUT 60 124 #define MPI3MR_RESETTM_TIMEOUT 60 125 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 126 #define MPI3MR_TSUPDATE_INTERVAL 900 127 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 128 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 129 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 130 #define MPI3MR_RESET_ACK_TIMEOUT 30 131 #define MPI3MR_MUR_TIMEOUT 120 132 #define MPI3MR_RESET_TIMEOUT 510 133 134 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 135 136 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 137 138 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 139 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 140 141 /* Internal admin command state definitions*/ 142 #define MPI3MR_CMD_NOTUSED 0x8000 143 #define MPI3MR_CMD_COMPLETE 0x0001 144 #define MPI3MR_CMD_PENDING 0x0002 145 #define MPI3MR_CMD_REPLY_VALID 0x0004 146 #define MPI3MR_CMD_RESET 0x0008 147 148 /* Definitions for Event replies and sense buffer allocated per controller */ 149 #define MPI3MR_NUM_EVT_REPLIES 64 150 #define MPI3MR_SENSE_BUF_SZ 256 151 #define MPI3MR_SENSEBUF_FACTOR 3 152 #define MPI3MR_CHAINBUF_FACTOR 3 153 #define MPI3MR_CHAINBUFDIX_FACTOR 2 154 155 /* Invalid target device handle */ 156 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 157 158 /* Controller Reset related definitions */ 159 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 160 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 161 162 /* ResponseCode definitions */ 163 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 164 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 165 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 166 167 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 168 #define MPI3MR_DEFAULT_PGSZEXP (12) 169 170 /* Command retry count definitions */ 171 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 172 #define MPI3MR_PEL_RETRY_COUNT 3 173 174 /* Default target device queue depth */ 175 #define MPI3MR_DEFAULT_SDEV_QD 32 176 177 /* Definitions for Threaded IRQ poll*/ 178 #define MPI3MR_IRQ_POLL_SLEEP 20 179 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 180 181 /* Definitions for the controller security status*/ 182 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 183 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 184 185 #define MPI3MR_INVALID_DEVICE 0x00 186 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 187 #define MPI3MR_HARD_SECURE_DEVICE 0x08 188 #define MPI3MR_TAMPERED_DEVICE 0x0C 189 190 #define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024) 191 #define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024) 192 #define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024) 193 #define MPI3MR_MAX_NUM_HDB 2 194 195 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0 196 #define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1 197 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2 198 #define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3 199 #define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4 200 #define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5 201 202 #define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0 203 #define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1 204 #define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2 205 #define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3 206 207 #define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024) 208 #define MPI3MR_MAX_NUM_HDB 2 209 210 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0 211 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1 212 213 #define MPI3MR_THRESHOLD_REPLY_COUNT 100 214 215 /* SGE Flag definition */ 216 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 217 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 218 MPI3_SGE_FLAGS_END_OF_LIST) 219 220 /* MSI Index from Reply Queue Index */ 221 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 222 223 /* 224 * Maximum data transfer size definitions for management 225 * application commands 226 */ 227 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 228 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 229 /* 230 * 2048 sectors are for data buffers and additional 512 sectors for 231 * other buffers 232 */ 233 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 234 235 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256 236 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048 237 238 #define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD) 239 240 /** 241 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 242 * Encapsulated commands. 243 * 244 * @base_addr: Physical address 245 * @length: SGE length 246 * @rsvd: Reserved 247 * @rsvd1: Reserved 248 * @sub_type: sgl sub type 249 * @type: sgl type 250 */ 251 struct mpi3mr_nvme_pt_sge { 252 __le64 base_addr; 253 __le32 length; 254 u16 rsvd; 255 u8 rsvd1; 256 u8 sub_type:4; 257 u8 type:4; 258 }; 259 260 /** 261 * struct mpi3mr_buf_map - local structure to 262 * track kernel and user buffers associated with an BSG 263 * structure. 264 * 265 * @bsg_buf: BSG buffer virtual address 266 * @bsg_buf_len: BSG buffer length 267 * @kern_buf: Kernel buffer virtual address 268 * @kern_buf_len: Kernel buffer length 269 * @kern_buf_dma: Kernel buffer DMA address 270 * @data_dir: Data direction. 271 */ 272 struct mpi3mr_buf_map { 273 void *bsg_buf; 274 u32 bsg_buf_len; 275 void *kern_buf; 276 u32 kern_buf_len; 277 dma_addr_t kern_buf_dma; 278 u8 data_dir; 279 u16 num_dma_desc; 280 struct dma_memory_desc *dma_desc; 281 }; 282 283 /* IOC State definitions */ 284 enum mpi3mr_iocstate { 285 MRIOC_STATE_READY = 1, 286 MRIOC_STATE_RESET, 287 MRIOC_STATE_FAULT, 288 MRIOC_STATE_BECOMING_READY, 289 MRIOC_STATE_RESET_REQUESTED, 290 MRIOC_STATE_UNRECOVERABLE, 291 }; 292 293 /* Reset reason code definitions*/ 294 enum mpi3mr_reset_reason { 295 MPI3MR_RESET_FROM_BRINGUP = 1, 296 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 297 MPI3MR_RESET_FROM_APP = 3, 298 MPI3MR_RESET_FROM_EH_HOS = 4, 299 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 300 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 301 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 302 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 303 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 304 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 305 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 306 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 307 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 308 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 309 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 310 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 311 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 312 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 313 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 314 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 315 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 316 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 317 MPI3MR_RESET_FROM_SYSFS = 23, 318 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 319 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 320 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26, 321 MPI3MR_RESET_FROM_FIRMWARE = 27, 322 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 323 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 324 MPI3MR_RESET_FROM_TRIGGER = 31, 325 }; 326 327 #define MPI3MR_RESET_REASON_OSTYPE_LINUX 1 328 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 329 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 330 331 /* Queue type definitions */ 332 enum queue_type { 333 MPI3MR_DEFAULT_QUEUE = 0, 334 MPI3MR_POLL_QUEUE, 335 }; 336 337 /** 338 * struct mpi3mr_compimg_ver - replica of component image 339 * version defined in mpi30_image.h in host endianness 340 * 341 */ 342 struct mpi3mr_compimg_ver { 343 u16 build_num; 344 u16 cust_id; 345 u8 ph_minor; 346 u8 ph_major; 347 u8 gen_minor; 348 u8 gen_major; 349 }; 350 351 /** 352 * struct mpi3mr_ioc_facs - replica of component image version 353 * defined in mpi30_ioc.h in host endianness 354 * 355 */ 356 struct mpi3mr_ioc_facts { 357 u32 ioc_capabilities; 358 struct mpi3mr_compimg_ver fw_ver; 359 u32 mpi_version; 360 u32 diag_trace_sz; 361 u32 diag_fw_sz; 362 u32 diag_drvr_sz; 363 u16 max_reqs; 364 u16 product_id; 365 u16 op_req_sz; 366 u16 reply_sz; 367 u16 exceptions; 368 u16 max_perids; 369 u16 max_pds; 370 u16 max_sasexpanders; 371 u32 max_data_length; 372 u16 max_sasinitiators; 373 u16 max_enclosures; 374 u16 max_pcie_switches; 375 u16 max_nvme; 376 u16 max_vds; 377 u16 max_hpds; 378 u16 max_advhpds; 379 u16 max_raid_pds; 380 u16 min_devhandle; 381 u16 max_devhandle; 382 u16 max_op_req_q; 383 u16 max_op_reply_q; 384 u16 shutdown_timeout; 385 u8 ioc_num; 386 u8 who_init; 387 u16 max_msix_vectors; 388 u8 personality; 389 u8 dma_mask; 390 u8 protocol_flags; 391 u8 sge_mod_mask; 392 u8 sge_mod_value; 393 u8 sge_mod_shift; 394 u8 max_dev_per_tg; 395 u16 max_io_throttle_group; 396 u16 io_throttle_data_length; 397 u16 io_throttle_low; 398 u16 io_throttle_high; 399 400 }; 401 402 /** 403 * struct segments - memory descriptor structure to store 404 * virtual and dma addresses for operational queue segments. 405 * 406 * @segment: virtual address 407 * @segment_dma: dma address 408 */ 409 struct segments { 410 void *segment; 411 dma_addr_t segment_dma; 412 }; 413 414 /** 415 * struct op_req_qinfo - Operational Request Queue Information 416 * 417 * @ci: consumer index 418 * @pi: producer index 419 * @num_request: Maximum number of entries in the queue 420 * @qid: Queue Id starting from 1 421 * @reply_qid: Associated reply queue Id 422 * @num_segments: Number of discontiguous memory segments 423 * @segment_qd: Depth of each segments 424 * @q_lock: Concurrent queue access lock 425 * @q_segments: Segment descriptor pointer 426 * @q_segment_list: Segment list base virtual address 427 * @q_segment_list_dma: Segment list base DMA address 428 */ 429 struct op_req_qinfo { 430 u16 ci; 431 u16 pi; 432 u16 num_requests; 433 u16 qid; 434 u16 reply_qid; 435 u16 num_segments; 436 u16 segment_qd; 437 spinlock_t q_lock; 438 struct segments *q_segments; 439 void *q_segment_list; 440 dma_addr_t q_segment_list_dma; 441 }; 442 443 /** 444 * struct op_reply_qinfo - Operational Reply Queue Information 445 * 446 * @ci: consumer index 447 * @qid: Queue Id starting from 1 448 * @num_replies: Maximum number of entries in the queue 449 * @num_segments: Number of discontiguous memory segments 450 * @segment_qd: Depth of each segments 451 * @q_segments: Segment descriptor pointer 452 * @q_segment_list: Segment list base virtual address 453 * @q_segment_list_dma: Segment list base DMA address 454 * @ephase: Expected phased identifier for the reply queue 455 * @pend_ios: Number of IOs pending in HW for this queue 456 * @enable_irq_poll: Flag to indicate polling is enabled 457 * @in_use: Queue is handled by poll/ISR 458 * @qtype: Type of queue (types defined in enum queue_type) 459 */ 460 struct op_reply_qinfo { 461 u16 ci; 462 u16 qid; 463 u16 num_replies; 464 u16 num_segments; 465 u16 segment_qd; 466 struct segments *q_segments; 467 void *q_segment_list; 468 dma_addr_t q_segment_list_dma; 469 u8 ephase; 470 atomic_t pend_ios; 471 bool enable_irq_poll; 472 atomic_t in_use; 473 enum queue_type qtype; 474 }; 475 476 /** 477 * struct mpi3mr_intr_info - Interrupt cookie information 478 * 479 * @mrioc: Adapter instance reference 480 * @os_irq: irq number 481 * @msix_index: MSIx index 482 * @op_reply_q: Associated operational reply queue 483 * @name: Dev name for the irq claiming device 484 */ 485 struct mpi3mr_intr_info { 486 struct mpi3mr_ioc *mrioc; 487 int os_irq; 488 u16 msix_index; 489 struct op_reply_qinfo *op_reply_q; 490 char name[MPI3MR_NAME_LENGTH]; 491 }; 492 493 /** 494 * struct mpi3mr_throttle_group_info - Throttle group info 495 * 496 * @io_divert: Flag indicates io divert is on or off for the TG 497 * @need_qd_reduction: Flag to indicate QD reduction is needed 498 * @qd_reduction: Queue Depth reduction in units of 10% 499 * @fw_qd: QueueDepth value reported by the firmware 500 * @modified_qd: Modified QueueDepth value due to throttling 501 * @id: Throttle Group ID. 502 * @high: High limit to turn on throttling in 512 byte blocks 503 * @low: Low limit to turn off throttling in 512 byte blocks 504 * @pend_large_data_sz: Counter to track pending large data 505 */ 506 struct mpi3mr_throttle_group_info { 507 u8 io_divert; 508 u8 need_qd_reduction; 509 u8 qd_reduction; 510 u16 fw_qd; 511 u16 modified_qd; 512 u16 id; 513 u32 high; 514 u32 low; 515 atomic_t pend_large_data_sz; 516 }; 517 518 /* HBA port flags */ 519 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 520 #define MPI3MR_HBA_PORT_FLAG_NEW 0x02 521 522 /* IOCTL data transfer sge*/ 523 #define MPI3MR_NUM_IOCTL_SGE 256 524 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 525 526 /** 527 * struct mpi3mr_hba_port - HBA's port information 528 * @port_id: Port number 529 * @flags: HBA port flags 530 */ 531 struct mpi3mr_hba_port { 532 struct list_head list; 533 u8 port_id; 534 u8 flags; 535 }; 536 537 /** 538 * struct mpi3mr_sas_port - Internal SAS port information 539 * @port_list: List of ports belonging to a SAS node 540 * @num_phys: Number of phys associated with port 541 * @marked_responding: used while refresing the sas ports 542 * @lowest_phy: lowest phy ID of current sas port, valid for controller port 543 * @phy_mask: phy_mask of current sas port, valid for controller port 544 * @hba_port: HBA port entry 545 * @remote_identify: Attached device identification 546 * @rphy: SAS transport layer rphy object 547 * @port: SAS transport layer port object 548 * @phy_list: mpi3mr_sas_phy objects belonging to this port 549 */ 550 struct mpi3mr_sas_port { 551 struct list_head port_list; 552 u8 num_phys; 553 u8 marked_responding; 554 int lowest_phy; 555 u64 phy_mask; 556 struct mpi3mr_hba_port *hba_port; 557 struct sas_identify remote_identify; 558 struct sas_rphy *rphy; 559 struct sas_port *port; 560 struct list_head phy_list; 561 }; 562 563 /** 564 * struct mpi3mr_sas_phy - Internal SAS Phy information 565 * @port_siblings: List of phys belonging to a port 566 * @identify: Phy identification 567 * @remote_identify: Attached device identification 568 * @phy: SAS transport layer Phy object 569 * @phy_id: Unique phy id within a port 570 * @handle: Firmware device handle for this phy 571 * @attached_handle: Firmware device handle for attached device 572 * @phy_belongs_to_port: Flag to indicate phy belongs to port 573 @hba_port: HBA port entry 574 */ 575 struct mpi3mr_sas_phy { 576 struct list_head port_siblings; 577 struct sas_identify identify; 578 struct sas_identify remote_identify; 579 struct sas_phy *phy; 580 u8 phy_id; 581 u16 handle; 582 u16 attached_handle; 583 u8 phy_belongs_to_port; 584 struct mpi3mr_hba_port *hba_port; 585 }; 586 587 /** 588 * struct mpi3mr_sas_node - SAS host/expander information 589 * @list: List of sas nodes in a controller 590 * @parent_dev: Parent device class 591 * @num_phys: Number phys belonging to sas_node 592 * @sas_address: SAS address of sas_node 593 * @handle: Firmware device handle for this sas_host/expander 594 * @sas_address_parent: SAS address of parent expander or host 595 * @enclosure_handle: Firmware handle of enclosure of this node 596 * @device_info: Capabilities of this sas_host/expander 597 * @non_responding: used to refresh the expander devices during reset 598 * @host_node: Flag to indicate this is a host_node 599 * @hba_port: HBA port entry 600 * @phy: A list of phys that make up this sas_host/expander 601 * @sas_port_list: List of internal ports of this node 602 * @rphy: sas_rphy object of this expander node 603 */ 604 struct mpi3mr_sas_node { 605 struct list_head list; 606 struct device *parent_dev; 607 u8 num_phys; 608 u64 sas_address; 609 u16 handle; 610 u64 sas_address_parent; 611 u16 enclosure_handle; 612 u64 enclosure_logical_id; 613 u8 non_responding; 614 u8 host_node; 615 struct mpi3mr_hba_port *hba_port; 616 struct mpi3mr_sas_phy *phy; 617 struct list_head sas_port_list; 618 struct sas_rphy *rphy; 619 }; 620 621 /** 622 * struct mpi3mr_enclosure_node - enclosure information 623 * @list: List of enclosures 624 * @pg0: Enclosure page 0; 625 */ 626 struct mpi3mr_enclosure_node { 627 struct list_head list; 628 struct mpi3_enclosure_page0 pg0; 629 }; 630 631 /** 632 * struct tgt_dev_sas_sata - SAS/SATA device specific 633 * information cached from firmware given data 634 * 635 * @sas_address: World wide unique SAS address 636 * @sas_address_parent: Sas address of parent expander or host 637 * @dev_info: Device information bits 638 * @phy_id: Phy identifier provided in device page 0 639 * @attached_phy_id: Attached phy identifier provided in device page 0 640 * @sas_transport_attached: Is this device exposed to transport 641 * @pend_sas_rphy_add: Flag to check device is in process of add 642 * @hba_port: HBA port entry 643 * @rphy: SAS transport layer rphy object 644 */ 645 struct tgt_dev_sas_sata { 646 u64 sas_address; 647 u64 sas_address_parent; 648 u16 dev_info; 649 u8 phy_id; 650 u8 attached_phy_id; 651 u8 sas_transport_attached; 652 u8 pend_sas_rphy_add; 653 struct mpi3mr_hba_port *hba_port; 654 struct sas_rphy *rphy; 655 }; 656 657 /** 658 * struct tgt_dev_pcie - PCIe device specific information cached 659 * from firmware given data 660 * 661 * @mdts: Maximum data transfer size 662 * @capb: Device capabilities 663 * @pgsz: Device page size 664 * @abort_to: Timeout for abort TM 665 * @reset_to: Timeout for Target/LUN reset TM 666 * @dev_info: Device information bits 667 */ 668 struct tgt_dev_pcie { 669 u32 mdts; 670 u16 capb; 671 u8 pgsz; 672 u8 abort_to; 673 u8 reset_to; 674 u16 dev_info; 675 }; 676 677 /** 678 * struct tgt_dev_vd - virtual device specific information 679 * cached from firmware given data 680 * 681 * @state: State of the VD 682 * @tg_qd_reduction: Queue Depth reduction in units of 10% 683 * @tg_id: VDs throttle group ID 684 * @high: High limit to turn on throttling in 512 byte blocks 685 * @low: Low limit to turn off throttling in 512 byte blocks 686 * @tg: Pointer to throttle group info 687 */ 688 struct tgt_dev_vd { 689 u8 state; 690 u8 tg_qd_reduction; 691 u16 tg_id; 692 u32 tg_high; 693 u32 tg_low; 694 struct mpi3mr_throttle_group_info *tg; 695 }; 696 697 698 /** 699 * union _form_spec_inf - union of device specific information 700 */ 701 union _form_spec_inf { 702 struct tgt_dev_sas_sata sas_sata_inf; 703 struct tgt_dev_pcie pcie_inf; 704 struct tgt_dev_vd vd_inf; 705 }; 706 707 enum mpi3mr_dev_state { 708 MPI3MR_DEV_CREATED = 1, 709 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 710 MPI3MR_DEV_DELETED = 3, 711 }; 712 713 /** 714 * struct mpi3mr_tgt_dev - target device data structure 715 * 716 * @list: List pointer 717 * @starget: Scsi_target pointer 718 * @dev_handle: FW device handle 719 * @parent_handle: FW parent device handle 720 * @slot: Slot number 721 * @encl_handle: FW enclosure handle 722 * @perst_id: FW assigned Persistent ID 723 * @devpg0_flag: Device Page0 flag 724 * @dev_type: SAS/SATA/PCIE device type 725 * @is_hidden: Should be exposed to upper layers or not 726 * @host_exposed: Already exposed to host or not 727 * @io_unit_port: IO Unit port ID 728 * @non_stl: Is this device not to be attached with SAS TL 729 * @io_throttle_enabled: I/O throttling needed or not 730 * @wslen: Write same max length 731 * @q_depth: Device specific Queue Depth 732 * @wwid: World wide ID 733 * @enclosure_logical_id: Enclosure logical identifier 734 * @dev_spec: Device type specific information 735 * @ref_count: Reference count 736 * @state: device state 737 */ 738 struct mpi3mr_tgt_dev { 739 struct list_head list; 740 struct scsi_target *starget; 741 u16 dev_handle; 742 u16 parent_handle; 743 u16 slot; 744 u16 encl_handle; 745 u16 perst_id; 746 u16 devpg0_flag; 747 u8 dev_type; 748 u8 is_hidden; 749 u8 host_exposed; 750 u8 io_unit_port; 751 u8 non_stl; 752 u8 io_throttle_enabled; 753 u16 wslen; 754 u16 q_depth; 755 u64 wwid; 756 u64 enclosure_logical_id; 757 union _form_spec_inf dev_spec; 758 struct kref ref_count; 759 enum mpi3mr_dev_state state; 760 }; 761 762 /** 763 * mpi3mr_tgtdev_get - k reference incrementor 764 * @s: Target device reference 765 * 766 * Increment target device reference count. 767 */ 768 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 769 { 770 kref_get(&s->ref_count); 771 } 772 773 /** 774 * mpi3mr_free_tgtdev - target device memory dealloctor 775 * @r: k reference pointer of the target device 776 * 777 * Free target device memory when no reference. 778 */ 779 static inline void mpi3mr_free_tgtdev(struct kref *r) 780 { 781 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 782 } 783 784 /** 785 * mpi3mr_tgtdev_put - k reference decrementor 786 * @s: Target device reference 787 * 788 * Decrement target device reference count. 789 */ 790 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 791 { 792 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 793 } 794 795 796 /** 797 * struct mpi3mr_stgt_priv_data - SCSI target private structure 798 * 799 * @starget: Scsi_target pointer 800 * @dev_handle: FW device handle 801 * @perst_id: FW assigned Persistent ID 802 * @num_luns: Number of Logical Units 803 * @block_io: I/O blocked to the device or not 804 * @dev_removed: Device removed in the Firmware 805 * @dev_removedelay: Device is waiting to be removed in FW 806 * @dev_type: Device type 807 * @dev_nvme_dif: Device is NVMe DIF enabled 808 * @wslen: Write same max length 809 * @io_throttle_enabled: I/O throttling needed or not 810 * @io_divert: Flag indicates io divert is on or off for the dev 811 * @throttle_group: Pointer to throttle group info 812 * @tgt_dev: Internal target device pointer 813 * @pend_count: Counter to track pending I/Os during error 814 * handling 815 */ 816 struct mpi3mr_stgt_priv_data { 817 struct scsi_target *starget; 818 u16 dev_handle; 819 u16 perst_id; 820 u32 num_luns; 821 atomic_t block_io; 822 u8 dev_removed; 823 u8 dev_removedelay; 824 u8 dev_type; 825 u8 dev_nvme_dif; 826 u16 wslen; 827 u8 io_throttle_enabled; 828 u8 io_divert; 829 struct mpi3mr_throttle_group_info *throttle_group; 830 struct mpi3mr_tgt_dev *tgt_dev; 831 u32 pend_count; 832 }; 833 834 /** 835 * struct mpi3mr_stgt_priv_data - SCSI device private structure 836 * 837 * @tgt_priv_data: Scsi_target private data pointer 838 * @lun_id: LUN ID of the device 839 * @ncq_prio_enable: NCQ priority enable for SATA device 840 * @pend_count: Counter to track pending I/Os during error 841 * handling 842 * @wslen: Write same max length 843 */ 844 struct mpi3mr_sdev_priv_data { 845 struct mpi3mr_stgt_priv_data *tgt_priv_data; 846 u32 lun_id; 847 u8 ncq_prio_enable; 848 u32 pend_count; 849 u16 wslen; 850 }; 851 852 /** 853 * struct mpi3mr_drv_cmd - Internal command tracker 854 * 855 * @mutex: Command mutex 856 * @done: Completeor for wakeup 857 * @reply: Firmware reply for internal commands 858 * @sensebuf: Sensebuf for SCSI IO commands 859 * @iou_rc: IO Unit control reason code 860 * @state: Command State 861 * @dev_handle: Firmware handle for device specific commands 862 * @ioc_status: IOC status from the firmware 863 * @ioc_loginfo:IOC log info from the firmware 864 * @is_waiting: Is the command issued in block mode 865 * @is_sense: Is Sense data present 866 * @retry_count: Retry count for retriable commands 867 * @host_tag: Host tag used by the command 868 * @callback: Callback for non blocking commands 869 */ 870 struct mpi3mr_drv_cmd { 871 struct mutex mutex; 872 struct completion done; 873 void *reply; 874 u8 *sensebuf; 875 u8 iou_rc; 876 u16 state; 877 u16 dev_handle; 878 u16 ioc_status; 879 u32 ioc_loginfo; 880 u8 is_waiting; 881 u8 is_sense; 882 u8 retry_count; 883 u16 host_tag; 884 885 void (*callback)(struct mpi3mr_ioc *mrioc, 886 struct mpi3mr_drv_cmd *drv_cmd); 887 }; 888 889 /** 890 * union mpi3mr_trigger_data - Trigger data information 891 * @fault: Fault code 892 * @global: Global trigger data 893 * @element: element trigger data 894 */ 895 union mpi3mr_trigger_data { 896 u16 fault; 897 u64 global; 898 union mpi3_driver2_trigger_element element; 899 }; 900 901 /** 902 * struct trigger_event_data - store trigger related 903 * information. 904 * 905 * @trace_hdb: Trace diag buffer descriptor reference 906 * @fw_hdb: FW diag buffer descriptor reference 907 * @trigger_type: Trigger type 908 * @trigger_specific_data: Trigger specific data 909 * @snapdump: Snapdump enable or disable flag 910 */ 911 struct trigger_event_data { 912 struct diag_buffer_desc *trace_hdb; 913 struct diag_buffer_desc *fw_hdb; 914 u8 trigger_type; 915 union mpi3mr_trigger_data trigger_specific_data; 916 bool snapdump; 917 }; 918 919 /** 920 * struct diag_buffer_desc - memory descriptor structure to 921 * store virtual, dma addresses, size, buffer status for host 922 * diagnostic buffers. 923 * 924 * @type: Buffer type 925 * @trigger_data: Trigger data 926 * @trigger_type: Trigger type 927 * @status: Buffer status 928 * @size: Buffer size 929 * @addr: Virtual address 930 * @dma_addr: Buffer DMA address 931 */ 932 struct diag_buffer_desc { 933 u8 type; 934 union mpi3mr_trigger_data trigger_data; 935 u8 trigger_type; 936 u8 status; 937 u32 size; 938 void *addr; 939 dma_addr_t dma_addr; 940 }; 941 942 /** 943 * struct dma_memory_desc - memory descriptor structure to store 944 * virtual address, dma address and size for any generic dma 945 * memory allocations in the driver. 946 * 947 * @size: buffer size 948 * @addr: virtual address 949 * @dma_addr: dma address 950 */ 951 struct dma_memory_desc { 952 u32 size; 953 void *addr; 954 dma_addr_t dma_addr; 955 }; 956 957 958 /** 959 * struct chain_element - memory descriptor structure to store 960 * virtual and dma addresses for chain elements. 961 * 962 * @addr: virtual address 963 * @dma_addr: dma address 964 */ 965 struct chain_element { 966 void *addr; 967 dma_addr_t dma_addr; 968 }; 969 970 /** 971 * struct scmd_priv - SCSI command private data 972 * 973 * @host_tag: Host tag specific to operational queue 974 * @in_lld_scope: Command in LLD scope or not 975 * @meta_sg_valid: DIX command with meta data SGL or not 976 * @scmd: SCSI Command pointer 977 * @req_q_idx: Operational request queue index 978 * @chain_idx: Chain frame index 979 * @meta_chain_idx: Chain frame index of meta data SGL 980 * @mpi3mr_scsiio_req: MPI SCSI IO request 981 */ 982 struct scmd_priv { 983 u16 host_tag; 984 u8 in_lld_scope; 985 u8 meta_sg_valid; 986 struct scsi_cmnd *scmd; 987 u16 req_q_idx; 988 int chain_idx; 989 int meta_chain_idx; 990 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 991 }; 992 993 /** 994 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 995 * private data 996 * 997 * @list: List pointer 998 * @pdev: PCI device pointer 999 * @shost: Scsi_Host pointer 1000 * @id: Controller ID 1001 * @cpu_count: Number of online CPUs 1002 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 1003 * @name: Controller ASCII name 1004 * @driver_name: Driver ASCII name 1005 * @sysif_regs: System interface registers virtual address 1006 * @sysif_regs_phys: System interface registers physical address 1007 * @bars: PCI BARS 1008 * @dma_mask: DMA mask 1009 * @msix_count: Number of MSIX vectors used 1010 * @intr_enabled: Is interrupts enabled 1011 * @num_admin_req: Number of admin requests 1012 * @admin_req_q_sz: Admin request queue size 1013 * @admin_req_pi: Admin request queue producer index 1014 * @admin_req_ci: Admin request queue consumer index 1015 * @admin_req_base: Admin request queue base virtual address 1016 * @admin_req_dma: Admin request queue base dma address 1017 * @admin_req_lock: Admin queue access lock 1018 * @num_admin_replies: Number of admin replies 1019 * @admin_reply_q_sz: Admin reply queue size 1020 * @admin_reply_ci: Admin reply queue consumer index 1021 * @admin_reply_ephase:Admin reply queue expected phase 1022 * @admin_reply_base: Admin reply queue base virtual address 1023 * @admin_reply_dma: Admin reply queue base dma address 1024 * @admin_reply_q_in_use: Queue is handled by poll/ISR 1025 * @ready_timeout: Controller ready timeout 1026 * @intr_info: Interrupt cookie pointer 1027 * @intr_info_count: Number of interrupt cookies 1028 * @is_intr_info_set: Flag to indicate intr info is setup 1029 * @num_queues: Number of operational queues 1030 * @num_op_req_q: Number of operational request queues 1031 * @req_qinfo: Operational request queue info pointer 1032 * @num_op_reply_q: Number of operational reply queues 1033 * @op_reply_qinfo: Operational reply queue info pointer 1034 * @init_cmds: Command tracker for initialization commands 1035 * @cfg_cmds: Command tracker for configuration requests 1036 * @facts: Cached IOC facts data 1037 * @op_reply_desc_sz: Operational reply descriptor size 1038 * @num_reply_bufs: Number of reply buffers allocated 1039 * @reply_buf_pool: Reply buffer pool 1040 * @reply_buf: Reply buffer base virtual address 1041 * @reply_buf_dma: Reply buffer DMA address 1042 * @reply_buf_dma_max_address: Reply DMA address max limit 1043 * @reply_free_qsz: Reply free queue size 1044 * @reply_free_q_pool: Reply free queue pool 1045 * @reply_free_q: Reply free queue base virtual address 1046 * @reply_free_q_dma: Reply free queue base DMA address 1047 * @reply_free_queue_lock: Reply free queue lock 1048 * @reply_free_queue_host_index: Reply free queue host index 1049 * @num_sense_bufs: Number of sense buffers 1050 * @sense_buf_pool: Sense buffer pool 1051 * @sense_buf: Sense buffer base virtual address 1052 * @sense_buf_dma: Sense buffer base DMA address 1053 * @sense_buf_q_sz: Sense buffer queue size 1054 * @sense_buf_q_pool: Sense buffer queue pool 1055 * @sense_buf_q: Sense buffer queue virtual address 1056 * @sense_buf_q_dma: Sense buffer queue DMA address 1057 * @sbq_lock: Sense buffer queue lock 1058 * @sbq_host_index: Sense buffer queuehost index 1059 * @event_masks: Event mask bitmap 1060 * @fwevt_worker_thread: Firmware event worker thread 1061 * @fwevt_lock: Firmware event lock 1062 * @fwevt_list: Firmware event list 1063 * @watchdog_work_q_name: Fault watchdog worker thread name 1064 * @watchdog_work_q: Fault watchdog worker thread 1065 * @watchdog_work: Fault watchdog work 1066 * @watchdog_lock: Fault watchdog lock 1067 * @is_driver_loading: Is driver still loading 1068 * @scan_started: Async scan started 1069 * @scan_failed: Asycn scan failed 1070 * @stop_drv_processing: Stop all command processing 1071 * @device_refresh_on: Don't process the events until devices are refreshed 1072 * @max_host_ios: Maximum host I/O count 1073 * @max_sgl_entries: Max SGL entries per I/O 1074 * @chain_buf_count: Chain buffer count 1075 * @chain_buf_pool: Chain buffer pool 1076 * @chain_sgl_list: Chain SGL list 1077 * @chain_bitmap: Chain buffer allocator bitmap 1078 * @chain_buf_lock: Chain buffer list lock 1079 * @bsg_cmds: Command tracker for BSG command 1080 * @host_tm_cmds: Command tracker for task management commands 1081 * @dev_rmhs_cmds: Command tracker for device removal commands 1082 * @evtack_cmds: Command tracker for event ack commands 1083 * @devrem_bitmap: Device removal bitmap 1084 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 1085 * @removepend_bitmap: Remove pending bitmap 1086 * @delayed_rmhs_list: Delayed device removal list 1087 * @evtack_cmds_bitmap: Event Ack bitmap 1088 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 1089 * @ts_update_counter: Timestamp update counter 1090 * @ts_update_interval: Timestamp update interval 1091 * @reset_in_progress: Reset in progress flag 1092 * @unrecoverable: Controller unrecoverable flag 1093 * @prev_reset_result: Result of previous reset 1094 * @reset_mutex: Controller reset mutex 1095 * @reset_waitq: Controller reset wait queue 1096 * @prepare_for_reset: Prepare for reset event received 1097 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 1098 * @prp_list_virt: NVMe encapsulated PRP list virtual base 1099 * @prp_list_dma: NVMe encapsulated PRP list DMA 1100 * @prp_sz: NVME encapsulated PRP list size 1101 * @diagsave_timeout: Diagnostic information save timeout 1102 * @logging_level: Controller debug logging level 1103 * @flush_io_count: I/O count to flush after reset 1104 * @current_event: Firmware event currently in process 1105 * @driver_info: Driver, Kernel, OS information to firmware 1106 * @change_count: Topology change count 1107 * @pel_enabled: Persistent Event Log(PEL) enabled or not 1108 * @pel_abort_requested: PEL abort is requested or not 1109 * @pel_class: PEL Class identifier 1110 * @pel_locale: PEL Locale identifier 1111 * @pel_cmds: Command tracker for PEL wait command 1112 * @pel_abort_cmd: Command tracker for PEL abort command 1113 * @pel_newest_seqnum: Newest PEL sequenece number 1114 * @pel_seqnum_virt: PEL sequence number virtual address 1115 * @pel_seqnum_dma: PEL sequence number DMA address 1116 * @pel_seqnum_sz: PEL sequenece number size 1117 * @op_reply_q_offset: Operational reply queue offset with MSIx 1118 * @default_qcount: Total Default queues 1119 * @active_poll_qcount: Currently active poll queue count 1120 * @requested_poll_qcount: User requested poll queue count 1121 * @bsg_dev: BSG device structure 1122 * @bsg_queue: Request queue for BSG device 1123 * @stop_bsgs: Stop BSG request flag 1124 * @logdata_buf: Circular buffer to store log data entries 1125 * @logdata_buf_idx: Index of entry in buffer to store 1126 * @logdata_entry_sz: log data entry size 1127 * @pend_large_data_sz: Counter to track pending large data 1128 * @io_throttle_data_length: I/O size to track in 512b blocks 1129 * @io_throttle_high: I/O size to start throttle in 512b blocks 1130 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1131 * @num_io_throttle_group: Maximum number of throttle groups 1132 * @throttle_groups: Pointer to throttle group info structures 1133 * @sas_transport_enabled: SAS transport enabled or not 1134 * @scsi_device_channel: Channel ID for SCSI devices 1135 * @transport_cmds: Command tracker for SAS transport commands 1136 * @sas_hba: SAS node for the controller 1137 * @sas_expander_list: SAS node list of expanders 1138 * @sas_node_lock: Lock to protect SAS node list 1139 * @hba_port_table_list: List of HBA Ports 1140 * @enclosure_list: List of Enclosure objects 1141 * @diag_buffers: Host diagnostic buffers 1142 * @driver_pg2: Driver page 2 pointer 1143 * @reply_trigger_present: Reply trigger present flag 1144 * @event_trigger_present: Event trigger present flag 1145 * @scsisense_trigger_present: Scsi sense trigger present flag 1146 * @ioctl_dma_pool: DMA pool for IOCTL data buffers 1147 * @ioctl_sge: DMA buffer descriptors for IOCTL data 1148 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain 1149 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response 1150 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not 1151 * @trace_release_trigger_active: Trace trigger active flag 1152 * @fw_release_trigger_active: Fw release trigger active flag 1153 * @snapdump_trigger_active: Snapdump trigger active flag 1154 * @pci_err_recovery: PCI error recovery in progress 1155 * @block_on_pci_err: Block IO during PCI error recovery 1156 */ 1157 struct mpi3mr_ioc { 1158 struct list_head list; 1159 struct pci_dev *pdev; 1160 struct Scsi_Host *shost; 1161 u8 id; 1162 int cpu_count; 1163 bool enable_segqueue; 1164 u32 irqpoll_sleep; 1165 1166 char name[MPI3MR_NAME_LENGTH]; 1167 char driver_name[MPI3MR_NAME_LENGTH]; 1168 1169 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1170 resource_size_t sysif_regs_phys; 1171 int bars; 1172 u64 dma_mask; 1173 1174 u16 msix_count; 1175 u8 intr_enabled; 1176 1177 u16 num_admin_req; 1178 u32 admin_req_q_sz; 1179 u16 admin_req_pi; 1180 u16 admin_req_ci; 1181 void *admin_req_base; 1182 dma_addr_t admin_req_dma; 1183 spinlock_t admin_req_lock; 1184 1185 u16 num_admin_replies; 1186 u32 admin_reply_q_sz; 1187 u16 admin_reply_ci; 1188 u8 admin_reply_ephase; 1189 void *admin_reply_base; 1190 dma_addr_t admin_reply_dma; 1191 atomic_t admin_reply_q_in_use; 1192 1193 u32 ready_timeout; 1194 1195 struct mpi3mr_intr_info *intr_info; 1196 u16 intr_info_count; 1197 bool is_intr_info_set; 1198 1199 u16 num_queues; 1200 u16 num_op_req_q; 1201 struct op_req_qinfo *req_qinfo; 1202 1203 u16 num_op_reply_q; 1204 struct op_reply_qinfo *op_reply_qinfo; 1205 1206 struct mpi3mr_drv_cmd init_cmds; 1207 struct mpi3mr_drv_cmd cfg_cmds; 1208 struct mpi3mr_ioc_facts facts; 1209 u16 op_reply_desc_sz; 1210 1211 u32 num_reply_bufs; 1212 struct dma_pool *reply_buf_pool; 1213 u8 *reply_buf; 1214 dma_addr_t reply_buf_dma; 1215 dma_addr_t reply_buf_dma_max_address; 1216 1217 u16 reply_free_qsz; 1218 u16 reply_sz; 1219 struct dma_pool *reply_free_q_pool; 1220 __le64 *reply_free_q; 1221 dma_addr_t reply_free_q_dma; 1222 spinlock_t reply_free_queue_lock; 1223 u32 reply_free_queue_host_index; 1224 1225 u32 num_sense_bufs; 1226 struct dma_pool *sense_buf_pool; 1227 u8 *sense_buf; 1228 dma_addr_t sense_buf_dma; 1229 1230 u16 sense_buf_q_sz; 1231 struct dma_pool *sense_buf_q_pool; 1232 __le64 *sense_buf_q; 1233 dma_addr_t sense_buf_q_dma; 1234 spinlock_t sbq_lock; 1235 u32 sbq_host_index; 1236 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1237 1238 struct workqueue_struct *fwevt_worker_thread; 1239 spinlock_t fwevt_lock; 1240 struct list_head fwevt_list; 1241 1242 char watchdog_work_q_name[50]; 1243 struct workqueue_struct *watchdog_work_q; 1244 struct delayed_work watchdog_work; 1245 spinlock_t watchdog_lock; 1246 1247 u8 is_driver_loading; 1248 u8 scan_started; 1249 u16 scan_failed; 1250 u8 stop_drv_processing; 1251 u8 device_refresh_on; 1252 1253 u16 max_host_ios; 1254 spinlock_t tgtdev_lock; 1255 struct list_head tgtdev_list; 1256 u16 max_sgl_entries; 1257 1258 u32 chain_buf_count; 1259 struct dma_pool *chain_buf_pool; 1260 struct chain_element *chain_sgl_list; 1261 unsigned long *chain_bitmap; 1262 spinlock_t chain_buf_lock; 1263 1264 struct mpi3mr_drv_cmd bsg_cmds; 1265 struct mpi3mr_drv_cmd host_tm_cmds; 1266 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1267 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1268 unsigned long *devrem_bitmap; 1269 u16 dev_handle_bitmap_bits; 1270 unsigned long *removepend_bitmap; 1271 struct list_head delayed_rmhs_list; 1272 unsigned long *evtack_cmds_bitmap; 1273 struct list_head delayed_evtack_cmds_list; 1274 1275 u16 ts_update_counter; 1276 u16 ts_update_interval; 1277 u8 reset_in_progress; 1278 u8 unrecoverable; 1279 int prev_reset_result; 1280 struct mutex reset_mutex; 1281 wait_queue_head_t reset_waitq; 1282 1283 u8 prepare_for_reset; 1284 u16 prepare_for_reset_timeout_counter; 1285 1286 void *prp_list_virt; 1287 dma_addr_t prp_list_dma; 1288 u32 prp_sz; 1289 1290 u16 diagsave_timeout; 1291 int logging_level; 1292 u16 flush_io_count; 1293 1294 struct mpi3mr_fwevt *current_event; 1295 struct mpi3_driver_info_layout driver_info; 1296 u16 change_count; 1297 1298 u8 pel_enabled; 1299 u8 pel_abort_requested; 1300 u8 pel_class; 1301 u16 pel_locale; 1302 struct mpi3mr_drv_cmd pel_cmds; 1303 struct mpi3mr_drv_cmd pel_abort_cmd; 1304 1305 u32 pel_newest_seqnum; 1306 void *pel_seqnum_virt; 1307 dma_addr_t pel_seqnum_dma; 1308 u32 pel_seqnum_sz; 1309 1310 u16 op_reply_q_offset; 1311 u16 default_qcount; 1312 u16 active_poll_qcount; 1313 u16 requested_poll_qcount; 1314 1315 struct device bsg_dev; 1316 struct request_queue *bsg_queue; 1317 u8 stop_bsgs; 1318 u8 *logdata_buf; 1319 u16 logdata_buf_idx; 1320 u16 logdata_entry_sz; 1321 1322 atomic_t pend_large_data_sz; 1323 u32 io_throttle_data_length; 1324 u32 io_throttle_high; 1325 u32 io_throttle_low; 1326 u16 num_io_throttle_group; 1327 struct mpi3mr_throttle_group_info *throttle_groups; 1328 1329 u8 sas_transport_enabled; 1330 u8 scsi_device_channel; 1331 struct mpi3mr_drv_cmd transport_cmds; 1332 struct mpi3mr_sas_node sas_hba; 1333 struct list_head sas_expander_list; 1334 spinlock_t sas_node_lock; 1335 struct list_head hba_port_table_list; 1336 struct list_head enclosure_list; 1337 1338 struct dma_pool *ioctl_dma_pool; 1339 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 1340 struct dma_memory_desc ioctl_chain_sge; 1341 struct dma_memory_desc ioctl_resp_sge; 1342 bool ioctl_sges_allocated; 1343 bool reply_trigger_present; 1344 bool event_trigger_present; 1345 bool scsisense_trigger_present; 1346 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB]; 1347 struct mpi3_driver_page2 *driver_pg2; 1348 spinlock_t trigger_lock; 1349 bool snapdump_trigger_active; 1350 bool trace_release_trigger_active; 1351 bool fw_release_trigger_active; 1352 bool pci_err_recovery; 1353 bool block_on_pci_err; 1354 }; 1355 1356 /** 1357 * struct mpi3mr_fwevt - Firmware event structure. 1358 * 1359 * @list: list head 1360 * @work: Work structure 1361 * @mrioc: Adapter instance reference 1362 * @event_id: MPI3 firmware event ID 1363 * @send_ack: Event acknowledgment required or not 1364 * @process_evt: Bottomhalf processing required or not 1365 * @evt_ctx: Event context to send in Ack 1366 * @event_data_size: size of the event data in bytes 1367 * @pending_at_sml: waiting for device add/remove API to complete 1368 * @discard: discard this event 1369 * @ref_count: kref count 1370 * @event_data: Actual MPI3 event data 1371 */ 1372 struct mpi3mr_fwevt { 1373 struct list_head list; 1374 struct work_struct work; 1375 struct mpi3mr_ioc *mrioc; 1376 u16 event_id; 1377 bool send_ack; 1378 bool process_evt; 1379 u32 evt_ctx; 1380 u16 event_data_size; 1381 bool pending_at_sml; 1382 bool discard; 1383 struct kref ref_count; 1384 char event_data[] __aligned(4); 1385 }; 1386 1387 1388 /** 1389 * struct delayed_dev_rmhs_node - Delayed device removal node 1390 * 1391 * @list: list head 1392 * @handle: Device handle 1393 * @iou_rc: IO Unit Control Reason Code 1394 */ 1395 struct delayed_dev_rmhs_node { 1396 struct list_head list; 1397 u16 handle; 1398 u8 iou_rc; 1399 }; 1400 1401 /** 1402 * struct delayed_evt_ack_node - Delayed event ack node 1403 * @list: list head 1404 * @event: MPI3 event ID 1405 * @event_ctx: event context 1406 */ 1407 struct delayed_evt_ack_node { 1408 struct list_head list; 1409 u8 event; 1410 u32 event_ctx; 1411 }; 1412 1413 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1414 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1415 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1416 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1417 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1418 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1419 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1420 u16 admin_req_sz, u8 ignore_reset); 1421 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1422 struct op_req_qinfo *opreqq, u8 *req); 1423 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1424 dma_addr_t dma_addr); 1425 void mpi3mr_build_zero_len_sge(void *paddr); 1426 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1427 dma_addr_t phys_addr); 1428 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1429 dma_addr_t phys_addr); 1430 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1431 u64 sense_buf_dma); 1432 1433 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1434 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1435 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1436 struct mpi3_event_notification_reply *event_reply); 1437 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1438 struct mpi3_default_reply_descriptor *reply_desc, 1439 u64 *reply_dma, u16 qidx); 1440 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1441 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1442 1443 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1444 u16 reset_reason, u8 snapdump); 1445 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1446 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1447 1448 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1449 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1450 u32 event_ctx); 1451 1452 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1453 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1454 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1455 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1456 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1457 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1458 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1459 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1460 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1461 struct op_reply_qinfo *op_reply_q); 1462 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1463 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1464 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1465 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1466 u16 handle, uint lun, u16 htag, ulong timeout, 1467 struct mpi3mr_drv_cmd *drv_cmd, 1468 u8 *resp_code, struct scsi_cmnd *scmd); 1469 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1470 struct mpi3mr_ioc *mrioc, u16 handle); 1471 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1472 struct mpi3mr_drv_cmd *drv_cmd); 1473 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1474 struct mpi3mr_drv_cmd *drv_cmd); 1475 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1476 u16 event_data_size); 1477 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1478 struct mpi3mr_ioc *mrioc, u16 handle); 1479 extern const struct attribute_group *mpi3mr_host_groups[]; 1480 extern const struct attribute_group *mpi3mr_dev_groups[]; 1481 1482 extern struct sas_function_template mpi3mr_transport_functions; 1483 extern struct scsi_transport_template *mpi3mr_transport_template; 1484 1485 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1486 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1487 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1488 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1489 u32 form_spec); 1490 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1491 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1492 u32 form_spec); 1493 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1494 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1495 u32 form_spec); 1496 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1497 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1498 u32 form_spec); 1499 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1500 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1501 u32 form_spec); 1502 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1503 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1504 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1505 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1506 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1507 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1508 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1509 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1510 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, 1511 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type); 1512 1513 u8 mpi3mr_is_expander_device(u16 device_info); 1514 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1515 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1516 struct mpi3mr_hba_port *hba_port); 1517 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1518 *mrioc, u16 handle); 1519 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1520 u8 port_id); 1521 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1522 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1523 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1524 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1525 struct mpi3mr_hba_port *hba_port); 1526 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1527 struct mpi3mr_tgt_dev *tgtdev); 1528 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1529 struct mpi3mr_tgt_dev *tgtdev); 1530 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1531 struct mpi3mr_tgt_dev *tgtdev); 1532 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1533 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1534 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1535 bool device_add); 1536 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1537 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1538 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1539 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1540 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1541 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1542 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1543 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1544 struct mpi3mr_sas_node *sas_expander); 1545 void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc); 1546 int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc); 1547 int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc, 1548 struct diag_buffer_desc *diag_buffer); 1549 void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action); 1550 void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb, 1551 u8 type, union mpi3mr_trigger_data *trigger_data, bool force); 1552 int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type); 1553 struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc, 1554 u8 buf_type); 1555 int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc, 1556 struct diag_buffer_desc *diag_buffer); 1557 void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc, 1558 u8 type, union mpi3mr_trigger_data *trigger_data, bool force); 1559 void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus, 1560 u32 iocloginfo); 1561 void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc, 1562 struct trigger_event_data *event_data); 1563 void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc, 1564 u8 ascq); 1565 void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event); 1566 void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data); 1567 void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc, 1568 struct mpi3_event_notification_reply *event_reply); 1569 #endif /*MPI3MR_H_INCLUDED*/ 1570