1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/workqueue.h> 33 #include <asm/unaligned.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_dbg.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 #include <scsi/scsi_tcq.h> 40 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 41 #include <scsi/scsi_transport_sas.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.5.0.0.0" 59 #define MPI3MR_DRIVER_RELDATE "24-July-2023" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_DEFAULT_SGL_ENTRIES 256 74 #define MPI3MR_MAX_SGL_ENTRIES 2048 75 76 /* Definitions for MAX values for shost */ 77 #define MPI3MR_MAX_CMDS_LUN 128 78 #define MPI3MR_MAX_CDB_LENGTH 32 79 80 /* Admin queue management definitions */ 81 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 83 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 84 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 85 86 /* Operational queue management definitions */ 87 #define MPI3MR_OP_REQ_Q_QD 512 88 #define MPI3MR_OP_REP_Q_QD 1024 89 #define MPI3MR_OP_REP_Q_QD4K 4096 90 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 91 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 92 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 93 94 /* Reserved Host Tag definitions */ 95 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 96 #define MPI3MR_HOSTTAG_INITCMDS 1 97 #define MPI3MR_HOSTTAG_BSG_CMDS 2 98 #define MPI3MR_HOSTTAG_PEL_ABORT 3 99 #define MPI3MR_HOSTTAG_PEL_WAIT 4 100 #define MPI3MR_HOSTTAG_BLK_TMS 5 101 #define MPI3MR_HOSTTAG_CFG_CMDS 6 102 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 103 104 #define MPI3MR_NUM_DEVRMCMD 16 105 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 106 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 107 MPI3MR_NUM_DEVRMCMD - 1) 108 109 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 110 #define MPI3MR_NUM_EVTACKCMD 4 111 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 112 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 113 MPI3MR_NUM_EVTACKCMD - 1) 114 115 /* Reduced resource count definition for crash kernel */ 116 #define MPI3MR_HOST_IOS_KDUMP 128 117 118 /* command/controller interaction timeout definitions in seconds */ 119 #define MPI3MR_INTADMCMD_TIMEOUT 60 120 #define MPI3MR_PORTENABLE_TIMEOUT 300 121 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5 122 #define MPI3MR_ABORTTM_TIMEOUT 60 123 #define MPI3MR_RESETTM_TIMEOUT 60 124 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 125 #define MPI3MR_TSUPDATE_INTERVAL 900 126 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 127 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 128 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 129 #define MPI3MR_RESET_ACK_TIMEOUT 30 130 #define MPI3MR_MUR_TIMEOUT 120 131 132 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 133 134 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 135 136 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 137 138 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 139 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 140 141 /* Internal admin command state definitions*/ 142 #define MPI3MR_CMD_NOTUSED 0x8000 143 #define MPI3MR_CMD_COMPLETE 0x0001 144 #define MPI3MR_CMD_PENDING 0x0002 145 #define MPI3MR_CMD_REPLY_VALID 0x0004 146 #define MPI3MR_CMD_RESET 0x0008 147 148 /* Definitions for Event replies and sense buffer allocated per controller */ 149 #define MPI3MR_NUM_EVT_REPLIES 64 150 #define MPI3MR_SENSE_BUF_SZ 256 151 #define MPI3MR_SENSEBUF_FACTOR 3 152 #define MPI3MR_CHAINBUF_FACTOR 3 153 #define MPI3MR_CHAINBUFDIX_FACTOR 2 154 155 /* Invalid target device handle */ 156 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 157 158 /* Controller Reset related definitions */ 159 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 160 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 161 162 /* ResponseCode definitions */ 163 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 164 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 165 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 166 167 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 168 #define MPI3MR_DEFAULT_PGSZEXP (12) 169 170 /* Command retry count definitions */ 171 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 172 #define MPI3MR_PEL_RETRY_COUNT 3 173 174 /* Default target device queue depth */ 175 #define MPI3MR_DEFAULT_SDEV_QD 32 176 177 /* Definitions for Threaded IRQ poll*/ 178 #define MPI3MR_IRQ_POLL_SLEEP 2 179 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 180 181 /* Definitions for the controller security status*/ 182 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 183 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 184 185 #define MPI3MR_INVALID_DEVICE 0x00 186 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 187 #define MPI3MR_HARD_SECURE_DEVICE 0x08 188 #define MPI3MR_TAMPERED_DEVICE 0x0C 189 190 /* SGE Flag definition */ 191 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 192 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 193 MPI3_SGE_FLAGS_END_OF_LIST) 194 195 /* MSI Index from Reply Queue Index */ 196 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 197 198 /* 199 * Maximum data transfer size definitions for management 200 * application commands 201 */ 202 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 203 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 204 /* 205 * 2048 sectors are for data buffers and additional 512 sectors for 206 * other buffers 207 */ 208 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 209 210 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256 211 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048 212 213 /** 214 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 215 * Encapsulated commands. 216 * 217 * @base_addr: Physical address 218 * @length: SGE length 219 * @rsvd: Reserved 220 * @rsvd1: Reserved 221 * @sgl_type: sgl type 222 */ 223 struct mpi3mr_nvme_pt_sge { 224 u64 base_addr; 225 u32 length; 226 u16 rsvd; 227 u8 rsvd1; 228 u8 sgl_type; 229 }; 230 231 /** 232 * struct mpi3mr_buf_map - local structure to 233 * track kernel and user buffers associated with an BSG 234 * structure. 235 * 236 * @bsg_buf: BSG buffer virtual address 237 * @bsg_buf_len: BSG buffer length 238 * @kern_buf: Kernel buffer virtual address 239 * @kern_buf_len: Kernel buffer length 240 * @kern_buf_dma: Kernel buffer DMA address 241 * @data_dir: Data direction. 242 */ 243 struct mpi3mr_buf_map { 244 void *bsg_buf; 245 u32 bsg_buf_len; 246 void *kern_buf; 247 u32 kern_buf_len; 248 dma_addr_t kern_buf_dma; 249 u8 data_dir; 250 }; 251 252 /* IOC State definitions */ 253 enum mpi3mr_iocstate { 254 MRIOC_STATE_READY = 1, 255 MRIOC_STATE_RESET, 256 MRIOC_STATE_FAULT, 257 MRIOC_STATE_BECOMING_READY, 258 MRIOC_STATE_RESET_REQUESTED, 259 MRIOC_STATE_UNRECOVERABLE, 260 }; 261 262 /* Reset reason code definitions*/ 263 enum mpi3mr_reset_reason { 264 MPI3MR_RESET_FROM_BRINGUP = 1, 265 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 266 MPI3MR_RESET_FROM_APP = 3, 267 MPI3MR_RESET_FROM_EH_HOS = 4, 268 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 269 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 270 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 271 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 272 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 273 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 274 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 275 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 276 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 277 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 278 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 279 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 280 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 281 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 282 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 283 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 284 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 285 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 286 MPI3MR_RESET_FROM_SYSFS = 23, 287 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 288 MPI3MR_RESET_FROM_FIRMWARE = 27, 289 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 290 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 291 }; 292 293 /* Queue type definitions */ 294 enum queue_type { 295 MPI3MR_DEFAULT_QUEUE = 0, 296 MPI3MR_POLL_QUEUE, 297 }; 298 299 /** 300 * struct mpi3mr_compimg_ver - replica of component image 301 * version defined in mpi30_image.h in host endianness 302 * 303 */ 304 struct mpi3mr_compimg_ver { 305 u16 build_num; 306 u16 cust_id; 307 u8 ph_minor; 308 u8 ph_major; 309 u8 gen_minor; 310 u8 gen_major; 311 }; 312 313 /** 314 * struct mpi3mr_ioc_facs - replica of component image version 315 * defined in mpi30_ioc.h in host endianness 316 * 317 */ 318 struct mpi3mr_ioc_facts { 319 u32 ioc_capabilities; 320 struct mpi3mr_compimg_ver fw_ver; 321 u32 mpi_version; 322 u16 max_reqs; 323 u16 product_id; 324 u16 op_req_sz; 325 u16 reply_sz; 326 u16 exceptions; 327 u16 max_perids; 328 u16 max_pds; 329 u16 max_sasexpanders; 330 u32 max_data_length; 331 u16 max_sasinitiators; 332 u16 max_enclosures; 333 u16 max_pcie_switches; 334 u16 max_nvme; 335 u16 max_vds; 336 u16 max_hpds; 337 u16 max_advhpds; 338 u16 max_raid_pds; 339 u16 min_devhandle; 340 u16 max_devhandle; 341 u16 max_op_req_q; 342 u16 max_op_reply_q; 343 u16 shutdown_timeout; 344 u8 ioc_num; 345 u8 who_init; 346 u16 max_msix_vectors; 347 u8 personality; 348 u8 dma_mask; 349 u8 protocol_flags; 350 u8 sge_mod_mask; 351 u8 sge_mod_value; 352 u8 sge_mod_shift; 353 u8 max_dev_per_tg; 354 u16 max_io_throttle_group; 355 u16 io_throttle_data_length; 356 u16 io_throttle_low; 357 u16 io_throttle_high; 358 359 }; 360 361 /** 362 * struct segments - memory descriptor structure to store 363 * virtual and dma addresses for operational queue segments. 364 * 365 * @segment: virtual address 366 * @segment_dma: dma address 367 */ 368 struct segments { 369 void *segment; 370 dma_addr_t segment_dma; 371 }; 372 373 /** 374 * struct op_req_qinfo - Operational Request Queue Information 375 * 376 * @ci: consumer index 377 * @pi: producer index 378 * @num_request: Maximum number of entries in the queue 379 * @qid: Queue Id starting from 1 380 * @reply_qid: Associated reply queue Id 381 * @num_segments: Number of discontiguous memory segments 382 * @segment_qd: Depth of each segments 383 * @q_lock: Concurrent queue access lock 384 * @q_segments: Segment descriptor pointer 385 * @q_segment_list: Segment list base virtual address 386 * @q_segment_list_dma: Segment list base DMA address 387 */ 388 struct op_req_qinfo { 389 u16 ci; 390 u16 pi; 391 u16 num_requests; 392 u16 qid; 393 u16 reply_qid; 394 u16 num_segments; 395 u16 segment_qd; 396 spinlock_t q_lock; 397 struct segments *q_segments; 398 void *q_segment_list; 399 dma_addr_t q_segment_list_dma; 400 }; 401 402 /** 403 * struct op_reply_qinfo - Operational Reply Queue Information 404 * 405 * @ci: consumer index 406 * @qid: Queue Id starting from 1 407 * @num_replies: Maximum number of entries in the queue 408 * @num_segments: Number of discontiguous memory segments 409 * @segment_qd: Depth of each segments 410 * @q_segments: Segment descriptor pointer 411 * @q_segment_list: Segment list base virtual address 412 * @q_segment_list_dma: Segment list base DMA address 413 * @ephase: Expected phased identifier for the reply queue 414 * @pend_ios: Number of IOs pending in HW for this queue 415 * @enable_irq_poll: Flag to indicate polling is enabled 416 * @in_use: Queue is handled by poll/ISR 417 * @qtype: Type of queue (types defined in enum queue_type) 418 */ 419 struct op_reply_qinfo { 420 u16 ci; 421 u16 qid; 422 u16 num_replies; 423 u16 num_segments; 424 u16 segment_qd; 425 struct segments *q_segments; 426 void *q_segment_list; 427 dma_addr_t q_segment_list_dma; 428 u8 ephase; 429 atomic_t pend_ios; 430 bool enable_irq_poll; 431 atomic_t in_use; 432 enum queue_type qtype; 433 }; 434 435 /** 436 * struct mpi3mr_intr_info - Interrupt cookie information 437 * 438 * @mrioc: Adapter instance reference 439 * @os_irq: irq number 440 * @msix_index: MSIx index 441 * @op_reply_q: Associated operational reply queue 442 * @name: Dev name for the irq claiming device 443 */ 444 struct mpi3mr_intr_info { 445 struct mpi3mr_ioc *mrioc; 446 int os_irq; 447 u16 msix_index; 448 struct op_reply_qinfo *op_reply_q; 449 char name[MPI3MR_NAME_LENGTH]; 450 }; 451 452 /** 453 * struct mpi3mr_throttle_group_info - Throttle group info 454 * 455 * @io_divert: Flag indicates io divert is on or off for the TG 456 * @need_qd_reduction: Flag to indicate QD reduction is needed 457 * @qd_reduction: Queue Depth reduction in units of 10% 458 * @fw_qd: QueueDepth value reported by the firmware 459 * @modified_qd: Modified QueueDepth value due to throttling 460 * @id: Throttle Group ID. 461 * @high: High limit to turn on throttling in 512 byte blocks 462 * @low: Low limit to turn off throttling in 512 byte blocks 463 * @pend_large_data_sz: Counter to track pending large data 464 */ 465 struct mpi3mr_throttle_group_info { 466 u8 io_divert; 467 u8 need_qd_reduction; 468 u8 qd_reduction; 469 u16 fw_qd; 470 u16 modified_qd; 471 u16 id; 472 u32 high; 473 u32 low; 474 atomic_t pend_large_data_sz; 475 }; 476 477 /* HBA port flags */ 478 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 479 480 /** 481 * struct mpi3mr_hba_port - HBA's port information 482 * @port_id: Port number 483 * @flags: HBA port flags 484 */ 485 struct mpi3mr_hba_port { 486 struct list_head list; 487 u8 port_id; 488 u8 flags; 489 }; 490 491 /** 492 * struct mpi3mr_sas_port - Internal SAS port information 493 * @port_list: List of ports belonging to a SAS node 494 * @num_phys: Number of phys associated with port 495 * @marked_responding: used while refresing the sas ports 496 * @lowest_phy: lowest phy ID of current sas port 497 * @phy_mask: phy_mask of current sas port 498 * @hba_port: HBA port entry 499 * @remote_identify: Attached device identification 500 * @rphy: SAS transport layer rphy object 501 * @port: SAS transport layer port object 502 * @phy_list: mpi3mr_sas_phy objects belonging to this port 503 */ 504 struct mpi3mr_sas_port { 505 struct list_head port_list; 506 u8 num_phys; 507 u8 marked_responding; 508 int lowest_phy; 509 u32 phy_mask; 510 struct mpi3mr_hba_port *hba_port; 511 struct sas_identify remote_identify; 512 struct sas_rphy *rphy; 513 struct sas_port *port; 514 struct list_head phy_list; 515 }; 516 517 /** 518 * struct mpi3mr_sas_phy - Internal SAS Phy information 519 * @port_siblings: List of phys belonging to a port 520 * @identify: Phy identification 521 * @remote_identify: Attached device identification 522 * @phy: SAS transport layer Phy object 523 * @phy_id: Unique phy id within a port 524 * @handle: Firmware device handle for this phy 525 * @attached_handle: Firmware device handle for attached device 526 * @phy_belongs_to_port: Flag to indicate phy belongs to port 527 @hba_port: HBA port entry 528 */ 529 struct mpi3mr_sas_phy { 530 struct list_head port_siblings; 531 struct sas_identify identify; 532 struct sas_identify remote_identify; 533 struct sas_phy *phy; 534 u8 phy_id; 535 u16 handle; 536 u16 attached_handle; 537 u8 phy_belongs_to_port; 538 struct mpi3mr_hba_port *hba_port; 539 }; 540 541 /** 542 * struct mpi3mr_sas_node - SAS host/expander information 543 * @list: List of sas nodes in a controller 544 * @parent_dev: Parent device class 545 * @num_phys: Number phys belonging to sas_node 546 * @sas_address: SAS address of sas_node 547 * @handle: Firmware device handle for this sas_host/expander 548 * @sas_address_parent: SAS address of parent expander or host 549 * @enclosure_handle: Firmware handle of enclosure of this node 550 * @device_info: Capabilities of this sas_host/expander 551 * @non_responding: used to refresh the expander devices during reset 552 * @host_node: Flag to indicate this is a host_node 553 * @hba_port: HBA port entry 554 * @phy: A list of phys that make up this sas_host/expander 555 * @sas_port_list: List of internal ports of this node 556 * @rphy: sas_rphy object of this expander node 557 */ 558 struct mpi3mr_sas_node { 559 struct list_head list; 560 struct device *parent_dev; 561 u8 num_phys; 562 u64 sas_address; 563 u16 handle; 564 u64 sas_address_parent; 565 u16 enclosure_handle; 566 u64 enclosure_logical_id; 567 u8 non_responding; 568 u8 host_node; 569 struct mpi3mr_hba_port *hba_port; 570 struct mpi3mr_sas_phy *phy; 571 struct list_head sas_port_list; 572 struct sas_rphy *rphy; 573 }; 574 575 /** 576 * struct mpi3mr_enclosure_node - enclosure information 577 * @list: List of enclosures 578 * @pg0: Enclosure page 0; 579 */ 580 struct mpi3mr_enclosure_node { 581 struct list_head list; 582 struct mpi3_enclosure_page0 pg0; 583 }; 584 585 /** 586 * struct tgt_dev_sas_sata - SAS/SATA device specific 587 * information cached from firmware given data 588 * 589 * @sas_address: World wide unique SAS address 590 * @sas_address_parent: Sas address of parent expander or host 591 * @dev_info: Device information bits 592 * @phy_id: Phy identifier provided in device page 0 593 * @attached_phy_id: Attached phy identifier provided in device page 0 594 * @sas_transport_attached: Is this device exposed to transport 595 * @pend_sas_rphy_add: Flag to check device is in process of add 596 * @hba_port: HBA port entry 597 * @rphy: SAS transport layer rphy object 598 */ 599 struct tgt_dev_sas_sata { 600 u64 sas_address; 601 u64 sas_address_parent; 602 u16 dev_info; 603 u8 phy_id; 604 u8 attached_phy_id; 605 u8 sas_transport_attached; 606 u8 pend_sas_rphy_add; 607 struct mpi3mr_hba_port *hba_port; 608 struct sas_rphy *rphy; 609 }; 610 611 /** 612 * struct tgt_dev_pcie - PCIe device specific information cached 613 * from firmware given data 614 * 615 * @mdts: Maximum data transfer size 616 * @capb: Device capabilities 617 * @pgsz: Device page size 618 * @abort_to: Timeout for abort TM 619 * @reset_to: Timeout for Target/LUN reset TM 620 * @dev_info: Device information bits 621 */ 622 struct tgt_dev_pcie { 623 u32 mdts; 624 u16 capb; 625 u8 pgsz; 626 u8 abort_to; 627 u8 reset_to; 628 u16 dev_info; 629 }; 630 631 /** 632 * struct tgt_dev_vd - virtual device specific information 633 * cached from firmware given data 634 * 635 * @state: State of the VD 636 * @tg_qd_reduction: Queue Depth reduction in units of 10% 637 * @tg_id: VDs throttle group ID 638 * @high: High limit to turn on throttling in 512 byte blocks 639 * @low: Low limit to turn off throttling in 512 byte blocks 640 * @tg: Pointer to throttle group info 641 */ 642 struct tgt_dev_vd { 643 u8 state; 644 u8 tg_qd_reduction; 645 u16 tg_id; 646 u32 tg_high; 647 u32 tg_low; 648 struct mpi3mr_throttle_group_info *tg; 649 }; 650 651 652 /** 653 * union _form_spec_inf - union of device specific information 654 */ 655 union _form_spec_inf { 656 struct tgt_dev_sas_sata sas_sata_inf; 657 struct tgt_dev_pcie pcie_inf; 658 struct tgt_dev_vd vd_inf; 659 }; 660 661 enum mpi3mr_dev_state { 662 MPI3MR_DEV_CREATED = 1, 663 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 664 MPI3MR_DEV_DELETED = 3, 665 }; 666 667 /** 668 * struct mpi3mr_tgt_dev - target device data structure 669 * 670 * @list: List pointer 671 * @starget: Scsi_target pointer 672 * @dev_handle: FW device handle 673 * @parent_handle: FW parent device handle 674 * @slot: Slot number 675 * @encl_handle: FW enclosure handle 676 * @perst_id: FW assigned Persistent ID 677 * @devpg0_flag: Device Page0 flag 678 * @dev_type: SAS/SATA/PCIE device type 679 * @is_hidden: Should be exposed to upper layers or not 680 * @host_exposed: Already exposed to host or not 681 * @io_unit_port: IO Unit port ID 682 * @non_stl: Is this device not to be attached with SAS TL 683 * @io_throttle_enabled: I/O throttling needed or not 684 * @wslen: Write same max length 685 * @q_depth: Device specific Queue Depth 686 * @wwid: World wide ID 687 * @enclosure_logical_id: Enclosure logical identifier 688 * @dev_spec: Device type specific information 689 * @ref_count: Reference count 690 * @state: device state 691 */ 692 struct mpi3mr_tgt_dev { 693 struct list_head list; 694 struct scsi_target *starget; 695 u16 dev_handle; 696 u16 parent_handle; 697 u16 slot; 698 u16 encl_handle; 699 u16 perst_id; 700 u16 devpg0_flag; 701 u8 dev_type; 702 u8 is_hidden; 703 u8 host_exposed; 704 u8 io_unit_port; 705 u8 non_stl; 706 u8 io_throttle_enabled; 707 u16 wslen; 708 u16 q_depth; 709 u64 wwid; 710 u64 enclosure_logical_id; 711 union _form_spec_inf dev_spec; 712 struct kref ref_count; 713 enum mpi3mr_dev_state state; 714 }; 715 716 /** 717 * mpi3mr_tgtdev_get - k reference incrementor 718 * @s: Target device reference 719 * 720 * Increment target device reference count. 721 */ 722 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 723 { 724 kref_get(&s->ref_count); 725 } 726 727 /** 728 * mpi3mr_free_tgtdev - target device memory dealloctor 729 * @r: k reference pointer of the target device 730 * 731 * Free target device memory when no reference. 732 */ 733 static inline void mpi3mr_free_tgtdev(struct kref *r) 734 { 735 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 736 } 737 738 /** 739 * mpi3mr_tgtdev_put - k reference decrementor 740 * @s: Target device reference 741 * 742 * Decrement target device reference count. 743 */ 744 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 745 { 746 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 747 } 748 749 750 /** 751 * struct mpi3mr_stgt_priv_data - SCSI target private structure 752 * 753 * @starget: Scsi_target pointer 754 * @dev_handle: FW device handle 755 * @perst_id: FW assigned Persistent ID 756 * @num_luns: Number of Logical Units 757 * @block_io: I/O blocked to the device or not 758 * @dev_removed: Device removed in the Firmware 759 * @dev_removedelay: Device is waiting to be removed in FW 760 * @dev_type: Device type 761 * @dev_nvme_dif: Device is NVMe DIF enabled 762 * @wslen: Write same max length 763 * @io_throttle_enabled: I/O throttling needed or not 764 * @io_divert: Flag indicates io divert is on or off for the dev 765 * @throttle_group: Pointer to throttle group info 766 * @tgt_dev: Internal target device pointer 767 * @pend_count: Counter to track pending I/Os during error 768 * handling 769 */ 770 struct mpi3mr_stgt_priv_data { 771 struct scsi_target *starget; 772 u16 dev_handle; 773 u16 perst_id; 774 u32 num_luns; 775 atomic_t block_io; 776 u8 dev_removed; 777 u8 dev_removedelay; 778 u8 dev_type; 779 u8 dev_nvme_dif; 780 u16 wslen; 781 u8 io_throttle_enabled; 782 u8 io_divert; 783 struct mpi3mr_throttle_group_info *throttle_group; 784 struct mpi3mr_tgt_dev *tgt_dev; 785 u32 pend_count; 786 }; 787 788 /** 789 * struct mpi3mr_stgt_priv_data - SCSI device private structure 790 * 791 * @tgt_priv_data: Scsi_target private data pointer 792 * @lun_id: LUN ID of the device 793 * @ncq_prio_enable: NCQ priority enable for SATA device 794 * @pend_count: Counter to track pending I/Os during error 795 * handling 796 * @wslen: Write same max length 797 */ 798 struct mpi3mr_sdev_priv_data { 799 struct mpi3mr_stgt_priv_data *tgt_priv_data; 800 u32 lun_id; 801 u8 ncq_prio_enable; 802 u32 pend_count; 803 u16 wslen; 804 }; 805 806 /** 807 * struct mpi3mr_drv_cmd - Internal command tracker 808 * 809 * @mutex: Command mutex 810 * @done: Completeor for wakeup 811 * @reply: Firmware reply for internal commands 812 * @sensebuf: Sensebuf for SCSI IO commands 813 * @iou_rc: IO Unit control reason code 814 * @state: Command State 815 * @dev_handle: Firmware handle for device specific commands 816 * @ioc_status: IOC status from the firmware 817 * @ioc_loginfo:IOC log info from the firmware 818 * @is_waiting: Is the command issued in block mode 819 * @is_sense: Is Sense data present 820 * @retry_count: Retry count for retriable commands 821 * @host_tag: Host tag used by the command 822 * @callback: Callback for non blocking commands 823 */ 824 struct mpi3mr_drv_cmd { 825 struct mutex mutex; 826 struct completion done; 827 void *reply; 828 u8 *sensebuf; 829 u8 iou_rc; 830 u16 state; 831 u16 dev_handle; 832 u16 ioc_status; 833 u32 ioc_loginfo; 834 u8 is_waiting; 835 u8 is_sense; 836 u8 retry_count; 837 u16 host_tag; 838 839 void (*callback)(struct mpi3mr_ioc *mrioc, 840 struct mpi3mr_drv_cmd *drv_cmd); 841 }; 842 843 /** 844 * struct dma_memory_desc - memory descriptor structure to store 845 * virtual address, dma address and size for any generic dma 846 * memory allocations in the driver. 847 * 848 * @size: buffer size 849 * @addr: virtual address 850 * @dma_addr: dma address 851 */ 852 struct dma_memory_desc { 853 u32 size; 854 void *addr; 855 dma_addr_t dma_addr; 856 }; 857 858 859 /** 860 * struct chain_element - memory descriptor structure to store 861 * virtual and dma addresses for chain elements. 862 * 863 * @addr: virtual address 864 * @dma_addr: dma address 865 */ 866 struct chain_element { 867 void *addr; 868 dma_addr_t dma_addr; 869 }; 870 871 /** 872 * struct scmd_priv - SCSI command private data 873 * 874 * @host_tag: Host tag specific to operational queue 875 * @in_lld_scope: Command in LLD scope or not 876 * @meta_sg_valid: DIX command with meta data SGL or not 877 * @scmd: SCSI Command pointer 878 * @req_q_idx: Operational request queue index 879 * @chain_idx: Chain frame index 880 * @meta_chain_idx: Chain frame index of meta data SGL 881 * @mpi3mr_scsiio_req: MPI SCSI IO request 882 */ 883 struct scmd_priv { 884 u16 host_tag; 885 u8 in_lld_scope; 886 u8 meta_sg_valid; 887 struct scsi_cmnd *scmd; 888 u16 req_q_idx; 889 int chain_idx; 890 int meta_chain_idx; 891 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 892 }; 893 894 /** 895 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 896 * private data 897 * 898 * @list: List pointer 899 * @pdev: PCI device pointer 900 * @shost: Scsi_Host pointer 901 * @id: Controller ID 902 * @cpu_count: Number of online CPUs 903 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 904 * @name: Controller ASCII name 905 * @driver_name: Driver ASCII name 906 * @sysif_regs: System interface registers virtual address 907 * @sysif_regs_phys: System interface registers physical address 908 * @bars: PCI BARS 909 * @dma_mask: DMA mask 910 * @msix_count: Number of MSIX vectors used 911 * @intr_enabled: Is interrupts enabled 912 * @num_admin_req: Number of admin requests 913 * @admin_req_q_sz: Admin request queue size 914 * @admin_req_pi: Admin request queue producer index 915 * @admin_req_ci: Admin request queue consumer index 916 * @admin_req_base: Admin request queue base virtual address 917 * @admin_req_dma: Admin request queue base dma address 918 * @admin_req_lock: Admin queue access lock 919 * @num_admin_replies: Number of admin replies 920 * @admin_reply_q_sz: Admin reply queue size 921 * @admin_reply_ci: Admin reply queue consumer index 922 * @admin_reply_ephase:Admin reply queue expected phase 923 * @admin_reply_base: Admin reply queue base virtual address 924 * @admin_reply_dma: Admin reply queue base dma address 925 * @admin_reply_q_in_use: Queue is handled by poll/ISR 926 * @ready_timeout: Controller ready timeout 927 * @intr_info: Interrupt cookie pointer 928 * @intr_info_count: Number of interrupt cookies 929 * @is_intr_info_set: Flag to indicate intr info is setup 930 * @num_queues: Number of operational queues 931 * @num_op_req_q: Number of operational request queues 932 * @req_qinfo: Operational request queue info pointer 933 * @num_op_reply_q: Number of operational reply queues 934 * @op_reply_qinfo: Operational reply queue info pointer 935 * @init_cmds: Command tracker for initialization commands 936 * @cfg_cmds: Command tracker for configuration requests 937 * @facts: Cached IOC facts data 938 * @op_reply_desc_sz: Operational reply descriptor size 939 * @num_reply_bufs: Number of reply buffers allocated 940 * @reply_buf_pool: Reply buffer pool 941 * @reply_buf: Reply buffer base virtual address 942 * @reply_buf_dma: Reply buffer DMA address 943 * @reply_buf_dma_max_address: Reply DMA address max limit 944 * @reply_free_qsz: Reply free queue size 945 * @reply_free_q_pool: Reply free queue pool 946 * @reply_free_q: Reply free queue base virtual address 947 * @reply_free_q_dma: Reply free queue base DMA address 948 * @reply_free_queue_lock: Reply free queue lock 949 * @reply_free_queue_host_index: Reply free queue host index 950 * @num_sense_bufs: Number of sense buffers 951 * @sense_buf_pool: Sense buffer pool 952 * @sense_buf: Sense buffer base virtual address 953 * @sense_buf_dma: Sense buffer base DMA address 954 * @sense_buf_q_sz: Sense buffer queue size 955 * @sense_buf_q_pool: Sense buffer queue pool 956 * @sense_buf_q: Sense buffer queue virtual address 957 * @sense_buf_q_dma: Sense buffer queue DMA address 958 * @sbq_lock: Sense buffer queue lock 959 * @sbq_host_index: Sense buffer queuehost index 960 * @event_masks: Event mask bitmap 961 * @fwevt_worker_name: Firmware event worker thread name 962 * @fwevt_worker_thread: Firmware event worker thread 963 * @fwevt_lock: Firmware event lock 964 * @fwevt_list: Firmware event list 965 * @watchdog_work_q_name: Fault watchdog worker thread name 966 * @watchdog_work_q: Fault watchdog worker thread 967 * @watchdog_work: Fault watchdog work 968 * @watchdog_lock: Fault watchdog lock 969 * @is_driver_loading: Is driver still loading 970 * @scan_started: Async scan started 971 * @scan_failed: Asycn scan failed 972 * @stop_drv_processing: Stop all command processing 973 * @device_refresh_on: Don't process the events until devices are refreshed 974 * @max_host_ios: Maximum host I/O count 975 * @max_sgl_entries: Max SGL entries per I/O 976 * @chain_buf_count: Chain buffer count 977 * @chain_buf_pool: Chain buffer pool 978 * @chain_sgl_list: Chain SGL list 979 * @chain_bitmap: Chain buffer allocator bitmap 980 * @chain_buf_lock: Chain buffer list lock 981 * @bsg_cmds: Command tracker for BSG command 982 * @host_tm_cmds: Command tracker for task management commands 983 * @dev_rmhs_cmds: Command tracker for device removal commands 984 * @evtack_cmds: Command tracker for event ack commands 985 * @devrem_bitmap: Device removal bitmap 986 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 987 * @removepend_bitmap: Remove pending bitmap 988 * @delayed_rmhs_list: Delayed device removal list 989 * @evtack_cmds_bitmap: Event Ack bitmap 990 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 991 * @ts_update_counter: Timestamp update counter 992 * @reset_in_progress: Reset in progress flag 993 * @unrecoverable: Controller unrecoverable flag 994 * @prev_reset_result: Result of previous reset 995 * @reset_mutex: Controller reset mutex 996 * @reset_waitq: Controller reset wait queue 997 * @prepare_for_reset: Prepare for reset event received 998 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 999 * @prp_list_virt: NVMe encapsulated PRP list virtual base 1000 * @prp_list_dma: NVMe encapsulated PRP list DMA 1001 * @prp_sz: NVME encapsulated PRP list size 1002 * @diagsave_timeout: Diagnostic information save timeout 1003 * @logging_level: Controller debug logging level 1004 * @flush_io_count: I/O count to flush after reset 1005 * @current_event: Firmware event currently in process 1006 * @driver_info: Driver, Kernel, OS information to firmware 1007 * @change_count: Topology change count 1008 * @pel_enabled: Persistent Event Log(PEL) enabled or not 1009 * @pel_abort_requested: PEL abort is requested or not 1010 * @pel_class: PEL Class identifier 1011 * @pel_locale: PEL Locale identifier 1012 * @pel_cmds: Command tracker for PEL wait command 1013 * @pel_abort_cmd: Command tracker for PEL abort command 1014 * @pel_newest_seqnum: Newest PEL sequenece number 1015 * @pel_seqnum_virt: PEL sequence number virtual address 1016 * @pel_seqnum_dma: PEL sequence number DMA address 1017 * @pel_seqnum_sz: PEL sequenece number size 1018 * @op_reply_q_offset: Operational reply queue offset with MSIx 1019 * @default_qcount: Total Default queues 1020 * @active_poll_qcount: Currently active poll queue count 1021 * @requested_poll_qcount: User requested poll queue count 1022 * @bsg_dev: BSG device structure 1023 * @bsg_queue: Request queue for BSG device 1024 * @stop_bsgs: Stop BSG request flag 1025 * @logdata_buf: Circular buffer to store log data entries 1026 * @logdata_buf_idx: Index of entry in buffer to store 1027 * @logdata_entry_sz: log data entry size 1028 * @pend_large_data_sz: Counter to track pending large data 1029 * @io_throttle_data_length: I/O size to track in 512b blocks 1030 * @io_throttle_high: I/O size to start throttle in 512b blocks 1031 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1032 * @num_io_throttle_group: Maximum number of throttle groups 1033 * @throttle_groups: Pointer to throttle group info structures 1034 * @cfg_page: Default memory for configuration pages 1035 * @cfg_page_dma: Configuration page DMA address 1036 * @cfg_page_sz: Default configuration page memory size 1037 * @sas_transport_enabled: SAS transport enabled or not 1038 * @scsi_device_channel: Channel ID for SCSI devices 1039 * @transport_cmds: Command tracker for SAS transport commands 1040 * @sas_hba: SAS node for the controller 1041 * @sas_expander_list: SAS node list of expanders 1042 * @sas_node_lock: Lock to protect SAS node list 1043 * @hba_port_table_list: List of HBA Ports 1044 * @enclosure_list: List of Enclosure objects 1045 */ 1046 struct mpi3mr_ioc { 1047 struct list_head list; 1048 struct pci_dev *pdev; 1049 struct Scsi_Host *shost; 1050 u8 id; 1051 int cpu_count; 1052 bool enable_segqueue; 1053 u32 irqpoll_sleep; 1054 1055 char name[MPI3MR_NAME_LENGTH]; 1056 char driver_name[MPI3MR_NAME_LENGTH]; 1057 1058 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1059 resource_size_t sysif_regs_phys; 1060 int bars; 1061 u64 dma_mask; 1062 1063 u16 msix_count; 1064 u8 intr_enabled; 1065 1066 u16 num_admin_req; 1067 u32 admin_req_q_sz; 1068 u16 admin_req_pi; 1069 u16 admin_req_ci; 1070 void *admin_req_base; 1071 dma_addr_t admin_req_dma; 1072 spinlock_t admin_req_lock; 1073 1074 u16 num_admin_replies; 1075 u32 admin_reply_q_sz; 1076 u16 admin_reply_ci; 1077 u8 admin_reply_ephase; 1078 void *admin_reply_base; 1079 dma_addr_t admin_reply_dma; 1080 atomic_t admin_reply_q_in_use; 1081 1082 u32 ready_timeout; 1083 1084 struct mpi3mr_intr_info *intr_info; 1085 u16 intr_info_count; 1086 bool is_intr_info_set; 1087 1088 u16 num_queues; 1089 u16 num_op_req_q; 1090 struct op_req_qinfo *req_qinfo; 1091 1092 u16 num_op_reply_q; 1093 struct op_reply_qinfo *op_reply_qinfo; 1094 1095 struct mpi3mr_drv_cmd init_cmds; 1096 struct mpi3mr_drv_cmd cfg_cmds; 1097 struct mpi3mr_ioc_facts facts; 1098 u16 op_reply_desc_sz; 1099 1100 u32 num_reply_bufs; 1101 struct dma_pool *reply_buf_pool; 1102 u8 *reply_buf; 1103 dma_addr_t reply_buf_dma; 1104 dma_addr_t reply_buf_dma_max_address; 1105 1106 u16 reply_free_qsz; 1107 u16 reply_sz; 1108 struct dma_pool *reply_free_q_pool; 1109 __le64 *reply_free_q; 1110 dma_addr_t reply_free_q_dma; 1111 spinlock_t reply_free_queue_lock; 1112 u32 reply_free_queue_host_index; 1113 1114 u32 num_sense_bufs; 1115 struct dma_pool *sense_buf_pool; 1116 u8 *sense_buf; 1117 dma_addr_t sense_buf_dma; 1118 1119 u16 sense_buf_q_sz; 1120 struct dma_pool *sense_buf_q_pool; 1121 __le64 *sense_buf_q; 1122 dma_addr_t sense_buf_q_dma; 1123 spinlock_t sbq_lock; 1124 u32 sbq_host_index; 1125 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1126 1127 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 1128 struct workqueue_struct *fwevt_worker_thread; 1129 spinlock_t fwevt_lock; 1130 struct list_head fwevt_list; 1131 1132 char watchdog_work_q_name[20]; 1133 struct workqueue_struct *watchdog_work_q; 1134 struct delayed_work watchdog_work; 1135 spinlock_t watchdog_lock; 1136 1137 u8 is_driver_loading; 1138 u8 scan_started; 1139 u16 scan_failed; 1140 u8 stop_drv_processing; 1141 u8 device_refresh_on; 1142 1143 u16 max_host_ios; 1144 spinlock_t tgtdev_lock; 1145 struct list_head tgtdev_list; 1146 u16 max_sgl_entries; 1147 1148 u32 chain_buf_count; 1149 struct dma_pool *chain_buf_pool; 1150 struct chain_element *chain_sgl_list; 1151 unsigned long *chain_bitmap; 1152 spinlock_t chain_buf_lock; 1153 1154 struct mpi3mr_drv_cmd bsg_cmds; 1155 struct mpi3mr_drv_cmd host_tm_cmds; 1156 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1157 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1158 unsigned long *devrem_bitmap; 1159 u16 dev_handle_bitmap_bits; 1160 unsigned long *removepend_bitmap; 1161 struct list_head delayed_rmhs_list; 1162 unsigned long *evtack_cmds_bitmap; 1163 struct list_head delayed_evtack_cmds_list; 1164 1165 u32 ts_update_counter; 1166 u8 reset_in_progress; 1167 u8 unrecoverable; 1168 int prev_reset_result; 1169 struct mutex reset_mutex; 1170 wait_queue_head_t reset_waitq; 1171 1172 u8 prepare_for_reset; 1173 u16 prepare_for_reset_timeout_counter; 1174 1175 void *prp_list_virt; 1176 dma_addr_t prp_list_dma; 1177 u32 prp_sz; 1178 1179 u16 diagsave_timeout; 1180 int logging_level; 1181 u16 flush_io_count; 1182 1183 struct mpi3mr_fwevt *current_event; 1184 struct mpi3_driver_info_layout driver_info; 1185 u16 change_count; 1186 1187 u8 pel_enabled; 1188 u8 pel_abort_requested; 1189 u8 pel_class; 1190 u16 pel_locale; 1191 struct mpi3mr_drv_cmd pel_cmds; 1192 struct mpi3mr_drv_cmd pel_abort_cmd; 1193 1194 u32 pel_newest_seqnum; 1195 void *pel_seqnum_virt; 1196 dma_addr_t pel_seqnum_dma; 1197 u32 pel_seqnum_sz; 1198 1199 u16 op_reply_q_offset; 1200 u16 default_qcount; 1201 u16 active_poll_qcount; 1202 u16 requested_poll_qcount; 1203 1204 struct device bsg_dev; 1205 struct request_queue *bsg_queue; 1206 u8 stop_bsgs; 1207 u8 *logdata_buf; 1208 u16 logdata_buf_idx; 1209 u16 logdata_entry_sz; 1210 1211 atomic_t pend_large_data_sz; 1212 u32 io_throttle_data_length; 1213 u32 io_throttle_high; 1214 u32 io_throttle_low; 1215 u16 num_io_throttle_group; 1216 struct mpi3mr_throttle_group_info *throttle_groups; 1217 1218 void *cfg_page; 1219 dma_addr_t cfg_page_dma; 1220 u16 cfg_page_sz; 1221 1222 u8 sas_transport_enabled; 1223 u8 scsi_device_channel; 1224 struct mpi3mr_drv_cmd transport_cmds; 1225 struct mpi3mr_sas_node sas_hba; 1226 struct list_head sas_expander_list; 1227 spinlock_t sas_node_lock; 1228 struct list_head hba_port_table_list; 1229 struct list_head enclosure_list; 1230 }; 1231 1232 /** 1233 * struct mpi3mr_fwevt - Firmware event structure. 1234 * 1235 * @list: list head 1236 * @work: Work structure 1237 * @mrioc: Adapter instance reference 1238 * @event_id: MPI3 firmware event ID 1239 * @send_ack: Event acknowledgment required or not 1240 * @process_evt: Bottomhalf processing required or not 1241 * @evt_ctx: Event context to send in Ack 1242 * @event_data_size: size of the event data in bytes 1243 * @pending_at_sml: waiting for device add/remove API to complete 1244 * @discard: discard this event 1245 * @ref_count: kref count 1246 * @event_data: Actual MPI3 event data 1247 */ 1248 struct mpi3mr_fwevt { 1249 struct list_head list; 1250 struct work_struct work; 1251 struct mpi3mr_ioc *mrioc; 1252 u16 event_id; 1253 bool send_ack; 1254 bool process_evt; 1255 u32 evt_ctx; 1256 u16 event_data_size; 1257 bool pending_at_sml; 1258 bool discard; 1259 struct kref ref_count; 1260 char event_data[] __aligned(4); 1261 }; 1262 1263 1264 /** 1265 * struct delayed_dev_rmhs_node - Delayed device removal node 1266 * 1267 * @list: list head 1268 * @handle: Device handle 1269 * @iou_rc: IO Unit Control Reason Code 1270 */ 1271 struct delayed_dev_rmhs_node { 1272 struct list_head list; 1273 u16 handle; 1274 u8 iou_rc; 1275 }; 1276 1277 /** 1278 * struct delayed_evt_ack_node - Delayed event ack node 1279 * @list: list head 1280 * @event: MPI3 event ID 1281 * @event_ctx: event context 1282 */ 1283 struct delayed_evt_ack_node { 1284 struct list_head list; 1285 u8 event; 1286 u32 event_ctx; 1287 }; 1288 1289 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1290 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1291 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1292 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1293 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1294 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1295 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1296 u16 admin_req_sz, u8 ignore_reset); 1297 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1298 struct op_req_qinfo *opreqq, u8 *req); 1299 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1300 dma_addr_t dma_addr); 1301 void mpi3mr_build_zero_len_sge(void *paddr); 1302 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1303 dma_addr_t phys_addr); 1304 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1305 dma_addr_t phys_addr); 1306 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1307 u64 sense_buf_dma); 1308 1309 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1310 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1311 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1312 struct mpi3_event_notification_reply *event_reply); 1313 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1314 struct mpi3_default_reply_descriptor *reply_desc, 1315 u64 *reply_dma, u16 qidx); 1316 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1317 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1318 1319 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1320 u32 reset_reason, u8 snapdump); 1321 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1322 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1323 1324 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1325 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1326 u32 event_ctx); 1327 1328 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1329 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1330 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1331 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1332 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1333 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1334 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1335 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1336 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1337 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1338 struct op_reply_qinfo *op_reply_q); 1339 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1340 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1341 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1342 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1343 u16 handle, uint lun, u16 htag, ulong timeout, 1344 struct mpi3mr_drv_cmd *drv_cmd, 1345 u8 *resp_code, struct scsi_cmnd *scmd); 1346 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1347 struct mpi3mr_ioc *mrioc, u16 handle); 1348 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1349 struct mpi3mr_drv_cmd *drv_cmd); 1350 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1351 struct mpi3mr_drv_cmd *drv_cmd); 1352 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1353 u16 event_data_size); 1354 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1355 struct mpi3mr_ioc *mrioc, u16 handle); 1356 extern const struct attribute_group *mpi3mr_host_groups[]; 1357 extern const struct attribute_group *mpi3mr_dev_groups[]; 1358 1359 extern struct sas_function_template mpi3mr_transport_functions; 1360 extern struct scsi_transport_template *mpi3mr_transport_template; 1361 1362 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1363 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1364 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1365 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1366 u32 form_spec); 1367 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1368 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1369 u32 form_spec); 1370 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1371 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1372 u32 form_spec); 1373 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1374 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1375 u32 form_spec); 1376 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1377 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1378 u32 form_spec); 1379 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1380 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1381 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1382 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1383 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1384 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1385 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1386 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1387 1388 u8 mpi3mr_is_expander_device(u16 device_info); 1389 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1390 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1391 struct mpi3mr_hba_port *hba_port); 1392 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1393 *mrioc, u16 handle); 1394 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1395 u8 port_id); 1396 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1397 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1398 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1399 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1400 struct mpi3mr_hba_port *hba_port); 1401 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1402 struct mpi3mr_tgt_dev *tgtdev); 1403 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1404 struct mpi3mr_tgt_dev *tgtdev); 1405 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1406 struct mpi3mr_tgt_dev *tgtdev); 1407 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1408 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1409 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1410 bool device_add); 1411 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1412 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1413 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1414 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1415 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1416 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1417 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1418 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1419 struct mpi3mr_sas_node *sas_expander); 1420 #endif /*MPI3MR_H_INCLUDED*/ 1421